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Merge bd8b70efb4 into 8be86d4a24
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de07b17f85
1 changed files with 8 additions and 0 deletions
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@ -91,6 +91,14 @@
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#define portFPU_REG_SIZE ( __riscv_flen / 8 )
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#define portFPU_REG_COUNT 33 /* 32 Floating point registers plus one CSR. */
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/*
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* Reserve space at the beginning of the FPU context block for:
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* 1. The FCSR (one portWORD_SIZE slot).
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* 2. Padding (one portWORD_SIZE slot) to align the FP registers:
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* - RV32: 8-byte boundary for double-precision registers.
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* - RV64: 16-byte boundary mandated by the RISC-V ABI.
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*/
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#define portFPU_REG_OFFSET( regIndex ) ( ( 2 * portWORD_SIZE ) + ( regIndex * portFPU_REG_SIZE ) )
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#define portFPU_CONTEXT_SIZE ( portFPU_REG_SIZE * portFPU_REG_COUNT )
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#else
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