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RISC-V port updates: The machine timer compare register can now be for any HART, and correct the sequence used to update the 64-bit machine timer compare register on 32-bit cores.

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This commit is contained in:
Richard Barry 2019-09-04 15:46:45 +00:00
parent 96bad0f6c3
commit da3d370ff7
5 changed files with 22 additions and 119 deletions
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6
FreeRTOS/Source/portable/IAR/RISC-V/portASM.s
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@ -110,7 +110,7 @@ at the top of this file. */
/*-----------------------------------------------------------*/
SECTION `.text`:CODE:NOROOT(2)
CODE
CODE
freertos_risc_v_trap_handler:
addi sp, sp, -portCONTEXT_SIZE
@ -177,10 +177,12 @@ handle_asynchronous:
#if( __riscv_xlen == 32 )
/* Update the 64-bit mtimer compare match value in two 32-bit writes. */
li t4, -1
lw t2, 0(t1) /* Load the low word of ullNextTime into t2. */
lw t3, 4(t1) /* Load the high word of ullNextTime into t3. */
sw t4, 0(t0) /* Low word no smaller than old value. */
sw t3, 4(t0) /* Store high word of ullNextTime into compare register. No smaller than new value. */
sw t2, 0(t0) /* Store low word of ullNextTime into compare register. */
sw t3, 4(t0) /* Store high word of ullNextTime into compare register. */
lw t0, uxTimerIncrementsForOneTick /* Load the value of ullTimerIncrementForOneTick into t0 (could this be optimized by storing in an array next to pullNextTime?). */
add t4, t0, t2 /* Add the low word of ullNextTime to the timer increments for one tick (assumes timer increment for one tick fits in 32-bits). */
sltu t5, t4, t2 /* See if the sum of low words overflowed (what about the zero case?). */