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port: riscv: Fix typo

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Jonathan Cubides 2025-01-23 15:02:06 +01:00
parent 742729ed29
commit d82b6d1dc9
1 changed files with 1 additions and 1 deletions
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portable/GCC/RISC-V/portASM.S
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@ -197,7 +197,7 @@ definitions. */
*/ */
pxPortInitialiseStack: pxPortInitialiseStack:
csrr t0, mstatus /* Obtain current mstatus value. */ csrr t0, mstatus /* Obtain current mstatus value. */
andi t0, t0, ~0x8 /* Ensure interrupts are disabled when the stack is restored within an ISR. Required when a task is created after the schedulre has been started, otherwise interrupts would be disabled anyway. */ andi t0, t0, ~0x8 /* Ensure interrupts are disabled when the stack is restored within an ISR. Required when a task is created after the scheduler has been started, otherwise interrupts would be disabled anyway. */
addi t1, x0, 0x188 /* Generate the value 0x1880, which are the MPIE and MPP bits to set in mstatus. */ addi t1, x0, 0x188 /* Generate the value 0x1880, which are the MPIE and MPP bits to set in mstatus. */
slli t1, t1, 4 slli t1, t1, 4
or t0, t0, t1 /* Set MPIE and MPP bits in mstatus value. */ or t0, t0, t1 /* Set MPIE and MPP bits in mstatus value. */