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Update GCC compiler for:

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* RX600v2
 * RX600
 * RX100

Signed-off-by: Dinh Van Nam <vannam.dinh.xt@renesas.com>
This commit is contained in:
Dinh Van Nam 2020-07-16 16:39:48 +09:00
parent 226af680e1
commit d7c280593d
6 changed files with 1146 additions and 1136 deletions
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896
portable/GCC/RX100/port.c
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142
portable/GCC/RX100/portmacro.h
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@ -44,100 +44,100 @@
*/ */
/* Type definitions - these are a bit legacy and not really used now, other than /* Type definitions - these are a bit legacy and not really used now, other than
* portSTACK_TYPE and portBASE_TYPE. */ portSTACK_TYPE and portBASE_TYPE. */
#define portCHAR char #define portCHAR char
#define portFLOAT float #define portFLOAT float
#define portDOUBLE double #define portDOUBLE double
#define portLONG long #define portLONG long
#define portSHORT short #define portSHORT short
#define portSTACK_TYPE uint32_t #define portSTACK_TYPE uint32_t
#define portBASE_TYPE long #define portBASE_TYPE long
typedef portSTACK_TYPE StackType_t; typedef portSTACK_TYPE StackType_t;
typedef long BaseType_t; typedef long BaseType_t;
typedef unsigned long UBaseType_t; typedef unsigned long UBaseType_t;
#if ( configUSE_16_BIT_TICKS == 1 ) #if( configUSE_16_BIT_TICKS == 1 )
typedef uint16_t TickType_t; typedef uint16_t TickType_t;
#define portMAX_DELAY ( TickType_t ) 0xffff #define portMAX_DELAY ( TickType_t ) 0xffff
#else #else
typedef uint32_t TickType_t; typedef uint32_t TickType_t;
#define portMAX_DELAY ( TickType_t ) 0xffffffffUL #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
* not need to be guarded with a critical section. */ not need to be guarded with a critical section. */
#define portTICK_TYPE_IS_ATOMIC 1 #define portTICK_TYPE_IS_ATOMIC 1
#endif #endif
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
/* Hardware specifics. */ /* Hardware specifics. */
#define portBYTE_ALIGNMENT 8 /* Could make four, according to manual. */ #define portBYTE_ALIGNMENT 8 /* Could make four, according to manual. */
#define portSTACK_GROWTH -1 #define portSTACK_GROWTH -1
#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
#define portNOP() __asm volatile ( "NOP" ) #define portNOP() __asm volatile( "NOP" )
/* Save clobbered register, set ITU SWINR (at address 0x872E0), read the value /* Save clobbered register, set ITU SWINR (at address 0x872E0), read the value
* back to ensure it is set before continuing, then restore the clobbered back to ensure it is set before continuing, then restore the clobbered
* register. */ register. */
#define portYIELD() \ #define portYIELD() \
__asm volatile \ __asm volatile \
( \ ( \
"MOV.L #0x872E0, r5 \n\t"\ "MOV.L #0x872E0, r5 \n\t" \
"MOV.B #1, [r5] \n\t"\ "MOV.B #1, [r5] \n\t" \
"MOV.L [r5], r5 \n\t"\ "MOV.L [r5], r5 \n\t" \
::: "r5" \ ::: "r5" \
) )
#define portYIELD_FROM_ISR( x ) if( x != pdFALSE ) { portYIELD(); } #define portYIELD_FROM_ISR( x ) if( x != pdFALSE ) { portYIELD(); }
/* These macros should not be called directly, but through the /* These macros should not be called directly, but through the
* taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros. An extra check is taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros. An extra check is
* performed if configASSERT() is defined to ensure an assertion handler does not performed if configASSERT() is defined to ensure an assertion handler does not
* inadvertently attempt to lower the IPL when the call to assert was triggered inadvertently attempt to lower the IPL when the call to assert was triggered
* because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY
* when an ISR safe FreeRTOS API function was executed. ISR safe FreeRTOS API when an ISR safe FreeRTOS API function was executed. ISR safe FreeRTOS API
* functions are those that end in FromISR. FreeRTOS maintains a separate functions are those that end in FromISR. FreeRTOS maintains a separate
* interrupt API to ensure API function and interrupt entry is as fast and as interrupt API to ensure API function and interrupt entry is as fast and as
* simple as possible. */ simple as possible. */
#define portENABLE_INTERRUPTS() __asm volatile ( "MVTIPL #0") #define portENABLE_INTERRUPTS() __asm volatile ( "MVTIPL #0" )
#ifdef configASSERT #ifdef configASSERT
#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( ulPortGetIPL() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) ) #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( ulPortGetIPL() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
#define portDISABLE_INTERRUPTS() if( ulPortGetIPL() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __asm volatile ( "MVTIPL %0"::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) ) #define portDISABLE_INTERRUPTS() if( ulPortGetIPL() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __asm volatile ( "MVTIPL %0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) )
#else #else
#define portDISABLE_INTERRUPTS() __asm volatile ( "MVTIPL %0"::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) ) #define portDISABLE_INTERRUPTS() __asm volatile ( "MVTIPL %0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) )
#endif #endif
/* Critical nesting counts are stored in the TCB. */ /* Critical nesting counts are stored in the TCB. */
#define portCRITICAL_NESTING_IN_TCB ( 1 ) #define portCRITICAL_NESTING_IN_TCB ( 1 )
/* The critical nesting functions defined within tasks.c. */ /* The critical nesting functions defined within tasks.c. */
extern void vTaskEnterCritical( void ); extern void vTaskEnterCritical( void );
extern void vTaskExitCritical( void ); extern void vTaskExitCritical( void );
#define portENTER_CRITICAL() vTaskEnterCritical() #define portENTER_CRITICAL() vTaskEnterCritical()
#define portEXIT_CRITICAL() vTaskExitCritical() #define portEXIT_CRITICAL() vTaskExitCritical()
/* As this port allows interrupt nesting... */ /* As this port allows interrupt nesting... */
uint32_t ulPortGetIPL( void ) __attribute__( ( naked ) ); uint32_t ulPortGetIPL( void ) __attribute__((naked));
void vPortSetIPL( uint32_t ulNewIPL ) __attribute__( ( naked ) ); void vPortSetIPL( uint32_t ulNewIPL ) __attribute__((naked));
#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortGetIPL(); portDISABLE_INTERRUPTS() #define portSET_INTERRUPT_MASK_FROM_ISR() ulPortGetIPL(); portDISABLE_INTERRUPTS()
#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) vPortSetIPL( uxSavedInterruptStatus ) #define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) vPortSetIPL( uxSavedInterruptStatus )
/* Tickless idle/low power functionality. */ /* Tickless idle/low power functionality. */
#if configUSE_TICKLESS_IDLE == 1 #if configUSE_TICKLESS_IDLE == 1
#ifndef portSUPPRESS_TICKS_AND_SLEEP #ifndef portSUPPRESS_TICKS_AND_SLEEP
extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime ); extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
#define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime ) #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
#endif #endif
#endif #endif
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. */ /* Task function macros as described on the FreeRTOS.org WEB site. */
#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif
#endif /* PORTMACRO_H */ #endif /* PORTMACRO_H */

446
portable/GCC/RX600/port.c
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@ -37,22 +37,26 @@
#include "string.h" #include "string.h"
/* Hardware specifics. */ /* Hardware specifics. */
#if defined(configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H) && (configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H == 1)
#include "platform.h"
#else
#include "iodefine.h" #include "iodefine.h"
#endif
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
/* Tasks should start with interrupts enabled and in Supervisor mode, therefore /* Tasks should start with interrupts enabled and in Supervisor mode, therefore
* PSW is set with U and I set, and PM and IPL clear. */ PSW is set with U and I set, and PM and IPL clear. */
#define portINITIAL_PSW ( ( StackType_t ) 0x00030000 ) #define portINITIAL_PSW ( ( StackType_t ) 0x00030000 )
#define portINITIAL_FPSW ( ( StackType_t ) 0x00000100 ) #define portINITIAL_FPSW ( ( StackType_t ) 0x00000100 )
/* These macros allow a critical section to be added around the call to /* These macros allow a critical section to be added around the call to
* xTaskIncrementTick(), which is only ever called from interrupts at the kernel xTaskIncrementTick(), which is only ever called from interrupts at the kernel
* priority - ie a known priority. Therefore these local macros are a slight priority - ie a known priority. Therefore these local macros are a slight
* optimisation compared to calling the global SET/CLEAR_INTERRUPT_MASK macros, optimisation compared to calling the global SET/CLEAR_INTERRUPT_MASK macros,
* which would require the old IPL to be read first and stored in a local variable. */ which would require the old IPL to be read first and stored in a local variable. */
#define portDISABLE_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0"::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) ) #define portDISABLE_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) )
#define portENABLE_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0"::"i" ( configKERNEL_INTERRUPT_PRIORITY ) ) #define portENABLE_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0" ::"i"(configKERNEL_INTERRUPT_PRIORITY) )
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
@ -60,308 +64,310 @@
* Function to start the first task executing - written in asm code as direct * Function to start the first task executing - written in asm code as direct
* access to registers is required. * access to registers is required.
*/ */
static void prvStartFirstTask( void ) __attribute__( ( naked ) ); static void prvStartFirstTask( void ) __attribute__((naked));
/* /*
* Software interrupt handler. Performs the actual context switch (saving and * Software interrupt handler. Performs the actual context switch (saving and
* restoring of registers). Written in asm code as direct register access is * restoring of registers). Written in asm code as direct register access is
* required. * required.
*/ */
void vSoftwareInterruptISR( void ) __attribute__( ( naked ) ); #if defined(configTICK_VECTOR)
void vSoftwareInterruptISR( void ) __attribute__((naked, vector( R_SECNAME_INTVECTTBL, VECT_ICU_SWINT )));
#else
void vSoftwareInterruptISR( void ) __attribute__((naked));
#endif
/* /*
* The tick interrupt handler. * The tick interrupt handler.
*/ */
void vTickISR( void ) __attribute__( ( interrupt ) ); #if defined(configTICK_VECTOR)
void vTickISR( void ) __attribute__((interrupt( R_SECNAME_INTVECTTBL, _VECT( configTICK_VECTOR ) )));
#else
void vTickISR( void ) __attribute__((interrupt));
#endif
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
extern void * pxCurrentTCB; extern void *pxCurrentTCB;
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
/* /*
* See header file for description. * See header file for description.
*/ */
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
TaskFunction_t pxCode,
void * pvParameters )
{ {
/* R0 is not included as it is the stack pointer. */ /* R0 is not included as it is the stack pointer. */
*pxTopOfStack = 0x00; *pxTopOfStack = 0x00;
pxTopOfStack--; pxTopOfStack--;
*pxTopOfStack = portINITIAL_PSW; *pxTopOfStack = portINITIAL_PSW;
pxTopOfStack--; pxTopOfStack--;
*pxTopOfStack = ( StackType_t ) pxCode; *pxTopOfStack = ( StackType_t ) pxCode;
/* When debugging it can be useful if every register is set to a known /* When debugging it can be useful if every register is set to a known
* value. Otherwise code space can be saved by just setting the registers value. Otherwise code space can be saved by just setting the registers
* that need to be set. */ that need to be set. */
#ifdef USE_FULL_REGISTER_INITIALISATION #ifdef USE_FULL_REGISTER_INITIALISATION
{ {
pxTopOfStack--; pxTopOfStack--;
*pxTopOfStack = 0xffffffff; /* r15. */ *pxTopOfStack = 0xffffffff; /* r15. */
pxTopOfStack--; pxTopOfStack--;
*pxTopOfStack = 0xeeeeeeee; *pxTopOfStack = 0xeeeeeeee;
pxTopOfStack--; pxTopOfStack--;
*pxTopOfStack = 0xdddddddd; *pxTopOfStack = 0xdddddddd;
pxTopOfStack--; pxTopOfStack--;
*pxTopOfStack = 0xcccccccc; *pxTopOfStack = 0xcccccccc;
pxTopOfStack--; pxTopOfStack--;
*pxTopOfStack = 0xbbbbbbbb; *pxTopOfStack = 0xbbbbbbbb;
pxTopOfStack--; pxTopOfStack--;
*pxTopOfStack = 0xaaaaaaaa; *pxTopOfStack = 0xaaaaaaaa;
pxTopOfStack--; pxTopOfStack--;
*pxTopOfStack = 0x99999999; *pxTopOfStack = 0x99999999;
pxTopOfStack--; pxTopOfStack--;
*pxTopOfStack = 0x88888888; *pxTopOfStack = 0x88888888;
pxTopOfStack--; pxTopOfStack--;
*pxTopOfStack = 0x77777777; *pxTopOfStack = 0x77777777;
pxTopOfStack--; pxTopOfStack--;
*pxTopOfStack = 0x66666666; *pxTopOfStack = 0x66666666;
pxTopOfStack--; pxTopOfStack--;
*pxTopOfStack = 0x55555555; *pxTopOfStack = 0x55555555;
pxTopOfStack--; pxTopOfStack--;
*pxTopOfStack = 0x44444444; *pxTopOfStack = 0x44444444;
pxTopOfStack--; pxTopOfStack--;
*pxTopOfStack = 0x33333333; *pxTopOfStack = 0x33333333;
pxTopOfStack--; pxTopOfStack--;
*pxTopOfStack = 0x22222222; *pxTopOfStack = 0x22222222;
pxTopOfStack--; pxTopOfStack--;
} }
#else /* ifdef USE_FULL_REGISTER_INITIALISATION */ #else
{ {
pxTopOfStack -= 15; pxTopOfStack -= 15;
} }
#endif /* ifdef USE_FULL_REGISTER_INITIALISATION */ #endif
*pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */ *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */
pxTopOfStack--; pxTopOfStack--;
*pxTopOfStack = portINITIAL_FPSW; *pxTopOfStack = portINITIAL_FPSW;
pxTopOfStack--; pxTopOfStack--;
*pxTopOfStack = 0x12345678; /* Accumulator. */ *pxTopOfStack = 0x12345678; /* Accumulator. */
pxTopOfStack--; pxTopOfStack--;
*pxTopOfStack = 0x87654321; /* Accumulator. */ *pxTopOfStack = 0x87654321; /* Accumulator. */
return pxTopOfStack; return pxTopOfStack;
} }
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
BaseType_t xPortStartScheduler( void ) BaseType_t xPortStartScheduler( void )
{ {
extern void vApplicationSetupTimerInterrupt( void ); extern void vApplicationSetupTimerInterrupt( void );
/* Use pxCurrentTCB just so it does not get optimised away. */ /* Use pxCurrentTCB just so it does not get optimised away. */
if( pxCurrentTCB != NULL ) if( pxCurrentTCB != NULL )
{ {
/* Call an application function to set up the timer that will generate the /* Call an application function to set up the timer that will generate the
* tick interrupt. This way the application can decide which peripheral to tick interrupt. This way the application can decide which peripheral to
* use. A demo application is provided to show a suitable example. */ use. A demo application is provided to show a suitable example. */
vApplicationSetupTimerInterrupt(); vApplicationSetupTimerInterrupt();
/* Enable the software interrupt. */ /* Enable the software interrupt. */
_IEN( _ICU_SWINT ) = 1; _IEN( _ICU_SWINT ) = 1;
/* Ensure the software interrupt is clear. */ /* Ensure the software interrupt is clear. */
_IR( _ICU_SWINT ) = 0; _IR( _ICU_SWINT ) = 0;
/* Ensure the software interrupt is set to the kernel priority. */ /* Ensure the software interrupt is set to the kernel priority. */
_IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY; _IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY;
/* Start the first task. */ /* Start the first task. */
prvStartFirstTask(); prvStartFirstTask();
} }
/* Should not get here. */ /* Should not get here. */
return pdFAIL; return pdFAIL;
} }
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
void vPortEndScheduler( void ) void vPortEndScheduler( void )
{ {
/* Not implemented in ports where there is nothing to return to. /* Not implemented in ports where there is nothing to return to.
* Artificially force an assert. */ Artificially force an assert. */
configASSERT( pxCurrentTCB == NULL ); configASSERT( pxCurrentTCB == NULL );
} }
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
static void prvStartFirstTask( void ) static void prvStartFirstTask( void )
{ {
__asm volatile __asm volatile
( (
/* When starting the scheduler there is nothing that needs moving to the
interrupt stack because the function is not called from an interrupt.
Just ensure the current stack is the user stack. */
"SETPSW U \n" \
/* When starting the scheduler there is nothing that needs moving to the /* Obtain the location of the stack associated with which ever task
* interrupt stack because the function is not called from an interrupt. pxCurrentTCB is currently pointing to. */
* Just ensure the current stack is the user stack. */ "MOV.L #_pxCurrentTCB, R15 \n" \
"SETPSW U \n"\ "MOV.L [R15], R15 \n" \
"MOV.L [R15], R0 \n" \
/* Restore the registers from the stack of the task pointed to by
pxCurrentTCB. */
"POP R15 \n" \
/* Obtain the location of the stack associated with which ever task /* Accumulator low 32 bits. */
* pxCurrentTCB is currently pointing to. */ "MVTACLO R15 \n" \
"MOV.L #_pxCurrentTCB, R15 \n"\ "POP R15 \n" \
"MOV.L [R15], R15 \n"\
"MOV.L [R15], R0 \n"\
/* Accumulator high 32 bits. */
"MVTACHI R15 \n" \
"POP R15 \n" \
/* Restore the registers from the stack of the task pointed to by /* Floating point status word. */
* pxCurrentTCB. */ "MVTC R15, FPSW \n" \
"POP R15 \n"\
/* Accumulator low 32 bits. */ /* R1 to R15 - R0 is not included as it is the SP. */
"MVTACLO R15 \n"\ "POPM R1-R15 \n" \
"POP R15 \n"\
/* Accumulator high 32 bits. */ /* This pops the remaining registers. */
"MVTACHI R15 \n"\ "RTE \n" \
"POP R15 \n"\ "NOP \n" \
"NOP \n"
/* Floating point status word. */ );
"MVTC R15, FPSW \n"\
/* R1 to R15 - R0 is not included as it is the SP. */
"POPM R1-R15 \n"\
/* This pops the remaining registers. */
"RTE \n"\
"NOP \n"\
"NOP \n"
);
} }
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
void vSoftwareInterruptISR( void ) void vSoftwareInterruptISR( void )
{ {
__asm volatile __asm volatile
( (
/* Re-enable interrupts. */ /* Re-enable interrupts. */
"SETPSW I \n"\ "SETPSW I \n" \
/* Move the data that was automatically pushed onto the interrupt stack when
the interrupt occurred from the interrupt stack to the user stack.
/* Move the data that was automatically pushed onto the interrupt stack when R15 is saved before it is clobbered. */
* the interrupt occurred from the interrupt stack to the user stack. "PUSH.L R15 \n" \
*
* R15 is saved before it is clobbered. */
"PUSH.L R15 \n"\
/* Read the user stack pointer. */ /* Read the user stack pointer. */
"MVFC USP, R15 \n"\ "MVFC USP, R15 \n" \
/* Move the address down to the data being moved. */ /* Move the address down to the data being moved. */
"SUB #12, R15 \n"\ "SUB #12, R15 \n" \
"MVTC R15, USP \n"\ "MVTC R15, USP \n" \
/* Copy the data across, R15, then PC, then PSW. */ /* Copy the data across, R15, then PC, then PSW. */
"MOV.L [ R0 ], [ R15 ] \n"\ "MOV.L [ R0 ], [ R15 ] \n" \
"MOV.L 4[ R0 ], 4[ R15 ] \n"\ "MOV.L 4[ R0 ], 4[ R15 ] \n" \
"MOV.L 8[ R0 ], 8[ R15 ] \n"\ "MOV.L 8[ R0 ], 8[ R15 ] \n" \
/* Move the interrupt stack pointer to its new correct position. */ /* Move the interrupt stack pointer to its new correct position. */
"ADD #12, R0 \n"\ "ADD #12, R0 \n" \
/* All the rest of the registers are saved directly to the user stack. */ /* All the rest of the registers are saved directly to the user stack. */
"SETPSW U \n"\ "SETPSW U \n" \
/* Save the rest of the general registers (R15 has been saved already). */ /* Save the rest of the general registers (R15 has been saved already). */
"PUSHM R1-R14 \n"\ "PUSHM R1-R14 \n" \
/* Save the FPSW and accumulator. */ /* Save the FPSW and accumulator. */
"MVFC FPSW, R15 \n"\ "MVFC FPSW, R15 \n" \
"PUSH.L R15 \n"\ "PUSH.L R15 \n" \
"MVFACHI R15 \n"\ "MVFACHI R15 \n" \
"PUSH.L R15 \n"\ "PUSH.L R15 \n" \
/* Middle word. */ /* Middle word. */
"MVFACMI R15 \n"\ "MVFACMI R15 \n" \
/* Shifted left as it is restored to the low order word. */ /* Shifted left as it is restored to the low order word. */
"SHLL #16, R15 \n"\ "SHLL #16, R15 \n" \
"PUSH.L R15 \n"\ "PUSH.L R15 \n" \
/* Save the stack pointer to the TCB. */ /* Save the stack pointer to the TCB. */
"MOV.L #_pxCurrentTCB, R15 \n"\ "MOV.L #_pxCurrentTCB, R15 \n" \
"MOV.L [ R15 ], R15 \n"\ "MOV.L [ R15 ], R15 \n" \
"MOV.L R0, [ R15 ] \n"\ "MOV.L R0, [ R15 ] \n" \
/* Ensure the interrupt mask is set to the syscall priority while the kernel
structures are being accessed. */
"MVTIPL %0 \n" \
/* Ensure the interrupt mask is set to the syscall priority while the kernel /* Select the next task to run. */
* structures are being accessed. */ "BSR.A _vTaskSwitchContext \n" \
"MVTIPL %0 \n"\
/* Select the next task to run. */ /* Reset the interrupt mask as no more data structure access is required. */
"BSR.A _vTaskSwitchContext \n"\ "MVTIPL %1 \n" \
/* Reset the interrupt mask as no more data structure access is required. */ /* Load the stack pointer of the task that is now selected as the Running
"MVTIPL %1 \n"\ state task from its TCB. */
"MOV.L #_pxCurrentTCB,R15 \n" \
"MOV.L [ R15 ], R15 \n" \
"MOV.L [ R15 ], R0 \n" \
/* Restore the context of the new task. The PSW (Program Status Word) and
/* Load the stack pointer of the task that is now selected as the Running PC will be popped by the RTE instruction. */
* state task from its TCB. */ "POP R15 \n" \
"MOV.L #_pxCurrentTCB,R15 \n"\ "MVTACLO R15 \n" \
"MOV.L [ R15 ], R15 \n"\ "POP R15 \n" \
"MOV.L [ R15 ], R0 \n"\ "MVTACHI R15 \n" \
"POP R15 \n" \
"MVTC R15, FPSW \n" \
/* Restore the context of the new task. The PSW (Program Status Word) and "POPM R1-R15 \n" \
* PC will be popped by the RTE instruction. */ "RTE \n" \
"POP R15 \n"\ "NOP \n" \
"MVTACLO R15 \n"\ "NOP "
"POP R15 \n"\ :: "i"(configMAX_SYSCALL_INTERRUPT_PRIORITY), "i"(configKERNEL_INTERRUPT_PRIORITY)
"MVTACHI R15 \n"\ );
"POP R15 \n"\
"MVTC R15, FPSW \n"\
"POPM R1-R15 \n"\
"RTE \n"\
"NOP \n"\
"NOP "
::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ), "i" ( configKERNEL_INTERRUPT_PRIORITY )
);
} }
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
void vTickISR( void ) void vTickISR( void )
{ {
/* Re-enabled interrupts. */ /* Re-enabled interrupts. */
__asm volatile ( "SETPSW I"); __asm volatile( "SETPSW I" );
/* Increment the tick, and perform any processing the new tick value /* Increment the tick, and perform any processing the new tick value
* necessitates. Ensure IPL is at the max syscall value first. */ necessitates. Ensure IPL is at the max syscall value first. */
portDISABLE_INTERRUPTS_FROM_KERNEL_ISR(); portDISABLE_INTERRUPTS_FROM_KERNEL_ISR();
{ {
if( xTaskIncrementTick() != pdFALSE ) if( xTaskIncrementTick() != pdFALSE )
{ {
taskYIELD(); taskYIELD();
} }
} }
portENABLE_INTERRUPTS_FROM_KERNEL_ISR(); portENABLE_INTERRUPTS_FROM_KERNEL_ISR();
} }
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
uint32_t ulPortGetIPL( void ) uint32_t ulPortGetIPL( void )
{ {
__asm volatile __asm volatile
( (
"MVFC PSW, R1 \n"\ "MVFC PSW, R1 \n" \
"SHLR #24, R1 \n"\ "SHLR #24, R1 \n" \
"RTS " "RTS "
); );
/* This will never get executed, but keeps the compiler from complaining. */ /* This will never get executed, but keeps the compiler from complaining. */
return 0; return 0;
} }
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
void vPortSetIPL( uint32_t ulNewIPL ) void vPortSetIPL( uint32_t ulNewIPL )
{ {
__asm volatile /* Avoid compiler warning about unreferenced parameter. */
( ( void ) ulNewIPL;
"PUSH R5 \n"\
"MVFC PSW, R5 \n"\ __asm volatile
"SHLL #24, R1 \n"\ (
"AND #-0F000001H, R5 \n"\ "PUSH R5 \n" \
"OR R1, R5 \n"\ "MVFC PSW, R5 \n" \
"MVTC R5, PSW \n"\ "SHLL #24, R1 \n" \
"POP R5 \n"\ "AND #-0F000001H, R5 \n" \
"RTS " "OR R1, R5 \n" \
); "MVTC R5, PSW \n" \
"POP R5 \n" \
"RTS "
);
} }

134
portable/GCC/RX600/portmacro.h
View file

@ -44,94 +44,94 @@
*/ */
/* Type definitions - these are a bit legacy and not really used now, other than /* Type definitions - these are a bit legacy and not really used now, other than
* portSTACK_TYPE and portBASE_TYPE. */ portSTACK_TYPE and portBASE_TYPE. */
#define portCHAR char #define portCHAR char
#define portFLOAT float #define portFLOAT float
#define portDOUBLE double #define portDOUBLE double
#define portLONG long #define portLONG long
#define portSHORT short #define portSHORT short
#define portSTACK_TYPE uint32_t #define portSTACK_TYPE uint32_t
#define portBASE_TYPE long #define portBASE_TYPE long
typedef portSTACK_TYPE StackType_t; typedef portSTACK_TYPE StackType_t;
typedef long BaseType_t; typedef long BaseType_t;
typedef unsigned long UBaseType_t; typedef unsigned long UBaseType_t;
#if ( configUSE_16_BIT_TICKS == 1 ) #if( configUSE_16_BIT_TICKS == 1 )
typedef uint16_t TickType_t; typedef uint16_t TickType_t;
#define portMAX_DELAY ( TickType_t ) 0xffff #define portMAX_DELAY ( TickType_t ) 0xffff
#else #else
typedef uint32_t TickType_t; typedef uint32_t TickType_t;
#define portMAX_DELAY ( TickType_t ) 0xffffffffUL #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
* not need to be guarded with a critical section. */ not need to be guarded with a critical section. */
#define portTICK_TYPE_IS_ATOMIC 1 #define portTICK_TYPE_IS_ATOMIC 1
#endif #endif
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
/* Hardware specifics. */ /* Hardware specifics. */
#define portBYTE_ALIGNMENT 8 /* Could make four, according to manual. */ #define portBYTE_ALIGNMENT 8 /* Could make four, according to manual. */
#define portSTACK_GROWTH -1 #define portSTACK_GROWTH -1
#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
#define portNOP() __asm volatile ( "NOP" ) #define portNOP() __asm volatile( "NOP" )
/* Yield equivalent to "*portITU_SWINTR = 0x01; ( void ) *portITU_SWINTR;" /* Yield equivalent to "*portITU_SWINTR = 0x01; ( void ) *portITU_SWINTR;"
* where portITU_SWINTR is the location of the software interrupt register where portITU_SWINTR is the location of the software interrupt register
* (0x000872E0). Don't rely on the assembler to select a register, so instead (0x000872E0). Don't rely on the assembler to select a register, so instead
* save and restore clobbered registers manually. */ save and restore clobbered registers manually. */
#define portYIELD() \ #define portYIELD() \
__asm volatile \ __asm volatile \
( \ ( \
"PUSH.L R10 \n"\ "PUSH.L R10 \n" \
"MOV.L #0x872E0, R10 \n"\ "MOV.L #0x872E0, R10 \n" \
"MOV.B #0x1, [R10] \n"\ "MOV.B #0x1, [R10] \n" \
"MOV.L [R10], R10 \n"\ "MOV.L [R10], R10 \n" \
"POP R10 \n"\ "POP R10 \n" \
) )
#define portYIELD_FROM_ISR( x ) if( x != pdFALSE ) portYIELD() #define portYIELD_FROM_ISR( x ) if( x != pdFALSE ) portYIELD()
/* These macros should not be called directly, but through the /* These macros should not be called directly, but through the
* taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros. An extra check is taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros. An extra check is
* performed if configASSERT() is defined to ensure an assertion handler does not performed if configASSERT() is defined to ensure an assertion handler does not
* inadvertently attempt to lower the IPL when the call to assert was triggered inadvertently attempt to lower the IPL when the call to assert was triggered
* because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY
* when an ISR safe FreeRTOS API function was executed. ISR safe FreeRTOS API when an ISR safe FreeRTOS API function was executed. ISR safe FreeRTOS API
* functions are those that end in FromISR. FreeRTOS maintains a separate functions are those that end in FromISR. FreeRTOS maintains a separate
* interrupt API to ensure API function and interrupt entry is as fast and as interrupt API to ensure API function and interrupt entry is as fast and as
* simple as possible. */ simple as possible. */
#define portENABLE_INTERRUPTS() __asm volatile ( "MVTIPL #0") #define portENABLE_INTERRUPTS() __asm volatile ( "MVTIPL #0" )
#ifdef configASSERT #ifdef configASSERT
#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( ulPortGetIPL() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) ) #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( ulPortGetIPL() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
#define portDISABLE_INTERRUPTS() if( ulPortGetIPL() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __asm volatile ( "MVTIPL %0"::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) ) #define portDISABLE_INTERRUPTS() if( ulPortGetIPL() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __asm volatile ( "MVTIPL %0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) )
#else #else
#define portDISABLE_INTERRUPTS() __asm volatile ( "MVTIPL %0"::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) ) #define portDISABLE_INTERRUPTS() __asm volatile ( "MVTIPL %0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) )
#endif #endif
/* Critical nesting counts are stored in the TCB. */ /* Critical nesting counts are stored in the TCB. */
#define portCRITICAL_NESTING_IN_TCB ( 1 ) #define portCRITICAL_NESTING_IN_TCB ( 1 )
/* The critical nesting functions defined within tasks.c. */ /* The critical nesting functions defined within tasks.c. */
extern void vTaskEnterCritical( void ); extern void vTaskEnterCritical( void );
extern void vTaskExitCritical( void ); extern void vTaskExitCritical( void );
#define portENTER_CRITICAL() vTaskEnterCritical() #define portENTER_CRITICAL() vTaskEnterCritical()
#define portEXIT_CRITICAL() vTaskExitCritical() #define portEXIT_CRITICAL() vTaskExitCritical()
/* As this port allows interrupt nesting... */ /* As this port allows interrupt nesting... */
uint32_t ulPortGetIPL( void ) __attribute__( ( naked ) ); uint32_t ulPortGetIPL( void ) __attribute__((naked));
void vPortSetIPL( uint32_t ulNewIPL ) __attribute__( ( naked ) ); void vPortSetIPL( uint32_t ulNewIPL ) __attribute__((naked));
#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortGetIPL(); portDISABLE_INTERRUPTS() #define portSET_INTERRUPT_MASK_FROM_ISR() ulPortGetIPL(); portDISABLE_INTERRUPTS()
#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) vPortSetIPL( uxSavedInterruptStatus ) #define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) vPortSetIPL( uxSavedInterruptStatus )
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. */ /* Task function macros as described on the FreeRTOS.org WEB site. */
#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif
#endif /* PORTMACRO_H */ #endif /* PORTMACRO_H */

528
portable/GCC/RX600v2/port.c
View file

@ -37,22 +37,26 @@
#include "string.h" #include "string.h"
/* Hardware specifics. */ /* Hardware specifics. */
#if defined(configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H) && (configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H == 1)
#include "platform.h"
#else
#include "iodefine.h" #include "iodefine.h"
#endif
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
/* Tasks should start with interrupts enabled and in Supervisor mode, therefore /* Tasks should start with interrupts enabled and in Supervisor mode, therefore
* PSW is set with U and I set, and PM and IPL clear. */ PSW is set with U and I set, and PM and IPL clear. */
#define portINITIAL_PSW ( ( StackType_t ) 0x00030000 ) #define portINITIAL_PSW ( ( StackType_t ) 0x00030000 )
#define portINITIAL_FPSW ( ( StackType_t ) 0x00000100 ) #define portINITIAL_FPSW ( ( StackType_t ) 0x00000100 )
/* These macros allow a critical section to be added around the call to /* These macros allow a critical section to be added around the call to
* xTaskIncrementTick(), which is only ever called from interrupts at the kernel xTaskIncrementTick(), which is only ever called from interrupts at the kernel
* priority - ie a known priority. Therefore these local macros are a slight priority - ie a known priority. Therefore these local macros are a slight
* optimisation compared to calling the global SET/CLEAR_INTERRUPT_MASK macros, optimisation compared to calling the global SET/CLEAR_INTERRUPT_MASK macros,
* which would require the old IPL to be read first and stored in a local variable. */ which would require the old IPL to be read first and stored in a local variable. */
#define portMASK_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0" ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) ) #define portMASK_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) )
#define portUNMASK_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0" ::"i" ( configKERNEL_INTERRUPT_PRIORITY ) ) #define portUNMASK_INTERRUPTS_FROM_KERNEL_ISR() __asm volatile ( "MVTIPL %0" ::"i"(configKERNEL_INTERRUPT_PRIORITY) )
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
@ -60,357 +64,359 @@
* Function to start the first task executing - written in asm code as direct * Function to start the first task executing - written in asm code as direct
* access to registers is required. * access to registers is required.
*/ */
static void prvStartFirstTask( void ) __attribute__( ( naked ) ); static void prvStartFirstTask( void ) __attribute__((naked));
/* /*
* Software interrupt handler. Performs the actual context switch (saving and * Software interrupt handler. Performs the actual context switch (saving and
* restoring of registers). Written in asm code as direct register access is * restoring of registers). Written in asm code as direct register access is
* required. * required.
*/ */
void vSoftwareInterruptISR( void ) __attribute__( ( naked ) ); #if defined(configTICK_VECTOR)
void vSoftwareInterruptISR( void ) __attribute__((naked, vector( R_BSP_SECNAME_INTVECTTBL, VECT_ICU_SWINT )));
#else
void vSoftwareInterruptISR( void ) __attribute__((naked));
#endif
/* /*
* The tick interrupt handler. * The tick interrupt handler.
*/ */
void vTickISR( void ) __attribute__( ( interrupt ) ); #if defined(configTICK_VECTOR)
void vTickISR( void ) __attribute__((interrupt( R_BSP_SECNAME_INTVECTTBL, _VECT( configTICK_VECTOR ) )));
#else
void vTickISR( void ) __attribute__((interrupt));
#endif
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
extern void * pxCurrentTCB; extern void *pxCurrentTCB;
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
/* /*
* See header file for description. * See header file for description.
*/ */
StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack, StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
TaskFunction_t pxCode,
void * pvParameters )
{ {
/* R0 is not included as it is the stack pointer. */ /* R0 is not included as it is the stack pointer. */
*pxTopOfStack = 0x00; *pxTopOfStack = 0x00;
pxTopOfStack--; pxTopOfStack--;
*pxTopOfStack = portINITIAL_PSW; *pxTopOfStack = portINITIAL_PSW;
pxTopOfStack--; pxTopOfStack--;
*pxTopOfStack = ( StackType_t ) pxCode; *pxTopOfStack = ( StackType_t ) pxCode;
/* When debugging it can be useful if every register is set to a known /* When debugging it can be useful if every register is set to a known
* value. Otherwise code space can be saved by just setting the registers value. Otherwise code space can be saved by just setting the registers
* that need to be set. */ that need to be set. */
#ifdef USE_FULL_REGISTER_INITIALISATION #ifdef USE_FULL_REGISTER_INITIALISATION
{ {
pxTopOfStack--; pxTopOfStack--;
*pxTopOfStack = 0xffffffff; /* r15. */ *pxTopOfStack = 0xffffffff; /* r15. */
pxTopOfStack--; pxTopOfStack--;
*pxTopOfStack = 0xeeeeeeee; *pxTopOfStack = 0xeeeeeeee;
pxTopOfStack--; pxTopOfStack--;
*pxTopOfStack = 0xdddddddd; *pxTopOfStack = 0xdddddddd;
pxTopOfStack--; pxTopOfStack--;
*pxTopOfStack = 0xcccccccc; *pxTopOfStack = 0xcccccccc;
pxTopOfStack--; pxTopOfStack--;
*pxTopOfStack = 0xbbbbbbbb; *pxTopOfStack = 0xbbbbbbbb;
pxTopOfStack--; pxTopOfStack--;
*pxTopOfStack = 0xaaaaaaaa; *pxTopOfStack = 0xaaaaaaaa;
pxTopOfStack--; pxTopOfStack--;
*pxTopOfStack = 0x99999999; *pxTopOfStack = 0x99999999;
pxTopOfStack--; pxTopOfStack--;
*pxTopOfStack = 0x88888888; *pxTopOfStack = 0x88888888;
pxTopOfStack--; pxTopOfStack--;
*pxTopOfStack = 0x77777777; *pxTopOfStack = 0x77777777;
pxTopOfStack--; pxTopOfStack--;
*pxTopOfStack = 0x66666666; *pxTopOfStack = 0x66666666;
pxTopOfStack--; pxTopOfStack--;
*pxTopOfStack = 0x55555555; *pxTopOfStack = 0x55555555;
pxTopOfStack--; pxTopOfStack--;
*pxTopOfStack = 0x44444444; *pxTopOfStack = 0x44444444;
pxTopOfStack--; pxTopOfStack--;
*pxTopOfStack = 0x33333333; *pxTopOfStack = 0x33333333;
pxTopOfStack--; pxTopOfStack--;
*pxTopOfStack = 0x22222222; *pxTopOfStack = 0x22222222;
pxTopOfStack--; pxTopOfStack--;
} }
#else /* ifdef USE_FULL_REGISTER_INITIALISATION */ #else
{ {
pxTopOfStack -= 15; pxTopOfStack -= 15;
} }
#endif /* ifdef USE_FULL_REGISTER_INITIALISATION */ #endif
*pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */ *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */
pxTopOfStack--; pxTopOfStack--;
*pxTopOfStack = portINITIAL_FPSW; *pxTopOfStack = portINITIAL_FPSW;
pxTopOfStack--; pxTopOfStack--;
*pxTopOfStack = 0x11111111; /* Accumulator 0. */ *pxTopOfStack = 0x11111111; /* Accumulator 0. */
pxTopOfStack--; pxTopOfStack--;
*pxTopOfStack = 0x22222222; /* Accumulator 0. */ *pxTopOfStack = 0x22222222; /* Accumulator 0. */
pxTopOfStack--; pxTopOfStack--;
*pxTopOfStack = 0x33333333; /* Accumulator 0. */ *pxTopOfStack = 0x33333333; /* Accumulator 0. */
pxTopOfStack--; pxTopOfStack--;
*pxTopOfStack = 0x44444444; /* Accumulator 1. */ *pxTopOfStack = 0x44444444; /* Accumulator 1. */
pxTopOfStack--; pxTopOfStack--;
*pxTopOfStack = 0x55555555; /* Accumulator 1. */ *pxTopOfStack = 0x55555555; /* Accumulator 1. */
pxTopOfStack--; pxTopOfStack--;
*pxTopOfStack = 0x66666666; /* Accumulator 1. */ *pxTopOfStack = 0x66666666; /* Accumulator 1. */
return pxTopOfStack; return pxTopOfStack;
} }
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
BaseType_t xPortStartScheduler( void ) BaseType_t xPortStartScheduler( void )
{ {
extern void vApplicationSetupTimerInterrupt( void ); extern void vApplicationSetupTimerInterrupt( void );
/* Use pxCurrentTCB just so it does not get optimised away. */ /* Use pxCurrentTCB just so it does not get optimised away. */
if( pxCurrentTCB != NULL ) if( pxCurrentTCB != NULL )
{ {
/* Call an application function to set up the timer that will generate the /* Call an application function to set up the timer that will generate the
* tick interrupt. This way the application can decide which peripheral to tick interrupt. This way the application can decide which peripheral to
* use. A demo application is provided to show a suitable example. */ use. A demo application is provided to show a suitable example. */
vApplicationSetupTimerInterrupt(); vApplicationSetupTimerInterrupt();
/* Enable the software interrupt. */ /* Enable the software interrupt. */
_IEN( _ICU_SWINT ) = 1; _IEN( _ICU_SWINT ) = 1;
/* Ensure the software interrupt is clear. */ /* Ensure the software interrupt is clear. */
_IR( _ICU_SWINT ) = 0; _IR( _ICU_SWINT ) = 0;
/* Ensure the software interrupt is set to the kernel priority. */ /* Ensure the software interrupt is set to the kernel priority. */
_IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY; _IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY;
/* Start the first task. */ /* Start the first task. */
prvStartFirstTask(); prvStartFirstTask();
} }
/* Should not get here. */ /* Should not get here. */
return pdFAIL; return pdFAIL;
} }
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
void vPortEndScheduler( void ) void vPortEndScheduler( void )
{ {
/* Not implemented in ports where there is nothing to return to. /* Not implemented in ports where there is nothing to return to.
* Artificially force an assert. */ Artificially force an assert. */
configASSERT( pxCurrentTCB == NULL ); configASSERT( pxCurrentTCB == NULL );
} }
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
static void prvStartFirstTask( void ) static void prvStartFirstTask( void )
{ {
__asm volatile __asm volatile
( (
/* When starting the scheduler there is nothing that needs moving to the
interrupt stack because the function is not called from an interrupt.
Just ensure the current stack is the user stack. */
"SETPSW U \n" \
/* When starting the scheduler there is nothing that needs moving to the /* Obtain the location of the stack associated with which ever task
* interrupt stack because the function is not called from an interrupt. pxCurrentTCB is currently pointing to. */
* Just ensure the current stack is the user stack. */ "MOV.L #_pxCurrentTCB, R15 \n" \
"SETPSW U \n"\ "MOV.L [R15], R15 \n" \
"MOV.L [R15], R0 \n" \
/* Restore the registers from the stack of the task pointed to by
pxCurrentTCB. */
"POP R15 \n" \
/* Obtain the location of the stack associated with which ever task /* Accumulator low 32 bits. */
* pxCurrentTCB is currently pointing to. */ "MVTACLO R15, A0 \n" \
"MOV.L #_pxCurrentTCB, R15 \n"\ "POP R15 \n" \
"MOV.L [R15], R15 \n"\
"MOV.L [R15], R0 \n"\
/* Accumulator high 32 bits. */
"MVTACHI R15, A0 \n" \
"POP R15 \n" \
/* Restore the registers from the stack of the task pointed to by /* Accumulator guard. */
* pxCurrentTCB. */ "MVTACGU R15, A0 \n" \
"POP R15 \n"\ "POP R15 \n" \
/* Accumulator low 32 bits. */ /* Accumulator low 32 bits. */
"MVTACLO R15, A0 \n"\ "MVTACLO R15, A1 \n" \
"POP R15 \n"\ "POP R15 \n" \
/* Accumulator high 32 bits. */ /* Accumulator high 32 bits. */
"MVTACHI R15, A0 \n"\ "MVTACHI R15, A1 \n" \
"POP R15 \n"\ "POP R15 \n" \
/* Accumulator guard. */ /* Accumulator guard. */
"MVTACGU R15, A0 \n"\ "MVTACGU R15, A1 \n" \
"POP R15 \n"\ "POP R15 \n" \
/* Accumulator low 32 bits. */ /* Floating point status word. */
"MVTACLO R15, A1 \n"\ "MVTC R15, FPSW \n" \
"POP R15 \n"\
/* Accumulator high 32 bits. */ /* R1 to R15 - R0 is not included as it is the SP. */
"MVTACHI R15, A1 \n"\ "POPM R1-R15 \n" \
"POP R15 \n"\
/* Accumulator guard. */ /* This pops the remaining registers. */
"MVTACGU R15, A1 \n"\ "RTE \n" \
"POP R15 \n"\ "NOP \n" \
"NOP \n"
/* Floating point status word. */ );
"MVTC R15, FPSW \n"\
/* R1 to R15 - R0 is not included as it is the SP. */
"POPM R1-R15 \n"\
/* This pops the remaining registers. */
"RTE \n"\
"NOP \n"\
"NOP \n"
);
} }
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
void vSoftwareInterruptISR( void ) void vSoftwareInterruptISR( void )
{ {
__asm volatile __asm volatile
( (
/* Re-enable interrupts. */ /* Re-enable interrupts. */
"SETPSW I \n"\ "SETPSW I \n" \
/* Move the data that was automatically pushed onto the interrupt stack when
the interrupt occurred from the interrupt stack to the user stack.
/* Move the data that was automatically pushed onto the interrupt stack when R15 is saved before it is clobbered. */
* the interrupt occurred from the interrupt stack to the user stack. "PUSH.L R15 \n" \
*
* R15 is saved before it is clobbered. */
"PUSH.L R15 \n"\
/* Read the user stack pointer. */ /* Read the user stack pointer. */
"MVFC USP, R15 \n"\ "MVFC USP, R15 \n" \
/* Move the address down to the data being moved. */ /* Move the address down to the data being moved. */
"SUB #12, R15 \n"\ "SUB #12, R15 \n" \
"MVTC R15, USP \n"\ "MVTC R15, USP \n" \
/* Copy the data across, R15, then PC, then PSW. */ /* Copy the data across, R15, then PC, then PSW. */
"MOV.L [ R0 ], [ R15 ] \n"\ "MOV.L [ R0 ], [ R15 ] \n" \
"MOV.L 4[ R0 ], 4[ R15 ] \n"\ "MOV.L 4[ R0 ], 4[ R15 ] \n" \
"MOV.L 8[ R0 ], 8[ R15 ] \n"\ "MOV.L 8[ R0 ], 8[ R15 ] \n" \
/* Move the interrupt stack pointer to its new correct position. */ /* Move the interrupt stack pointer to its new correct position. */
"ADD #12, R0 \n"\ "ADD #12, R0 \n" \
/* All the rest of the registers are saved directly to the user stack. */ /* All the rest of the registers are saved directly to the user stack. */
"SETPSW U \n"\ "SETPSW U \n" \
/* Save the rest of the general registers (R15 has been saved already). */ /* Save the rest of the general registers (R15 has been saved already). */
"PUSHM R1-R14 \n"\ "PUSHM R1-R14 \n" \
/* Save the FPSW and accumulator. */ /* Save the FPSW and accumulator. */
"MVFC FPSW, R15 \n"\ "MVFC FPSW, R15 \n" \
"PUSH.L R15 \n"\ "PUSH.L R15 \n" \
"MVFACGU #0, A1, R15 \n"\ "MVFACGU #0, A1, R15 \n" \
"PUSH.L R15 \n"\ "PUSH.L R15 \n" \
"MVFACHI #0, A1, R15 \n"\ "MVFACHI #0, A1, R15 \n" \
"PUSH.L R15 \n"\ "PUSH.L R15 \n" \
/* Low order word. */ /* Low order word. */
"MVFACLO #0, A1, R15 \n"\ "MVFACLO #0, A1, R15 \n" \
"PUSH.L R15 \n"\ "PUSH.L R15 \n" \
"MVFACGU #0, A0, R15 \n"\ "MVFACGU #0, A0, R15 \n" \
"PUSH.L R15 \n"\ "PUSH.L R15 \n" \
"MVFACHI #0, A0, R15 \n"\ "MVFACHI #0, A0, R15 \n" \
"PUSH.L R15 \n"\ "PUSH.L R15 \n" \
/* Low order word. */ /* Low order word. */
"MVFACLO #0, A0, R15 \n"\ "MVFACLO #0, A0, R15 \n" \
"PUSH.L R15 \n"\ "PUSH.L R15 \n" \
/* Save the stack pointer to the TCB. */ /* Save the stack pointer to the TCB. */
"MOV.L #_pxCurrentTCB, R15 \n"\ "MOV.L #_pxCurrentTCB, R15 \n" \
"MOV.L [ R15 ], R15 \n"\ "MOV.L [ R15 ], R15 \n" \
"MOV.L R0, [ R15 ] \n"\ "MOV.L R0, [ R15 ] \n" \
/* Ensure the interrupt mask is set to the syscall priority while the kernel
structures are being accessed. */
"MVTIPL %0 \n" \
/* Ensure the interrupt mask is set to the syscall priority while the kernel /* Select the next task to run. */
* structures are being accessed. */ "BSR.A _vTaskSwitchContext \n" \
"MVTIPL %0 \n"\
/* Select the next task to run. */ /* Reset the interrupt mask as no more data structure access is required. */
"BSR.A _vTaskSwitchContext \n"\ "MVTIPL %1 \n" \
/* Reset the interrupt mask as no more data structure access is required. */ /* Load the stack pointer of the task that is now selected as the Running
"MVTIPL %1 \n"\ state task from its TCB. */
"MOV.L #_pxCurrentTCB,R15 \n" \
"MOV.L [ R15 ], R15 \n" \
"MOV.L [ R15 ], R0 \n" \
/* Restore the context of the new task. The PSW (Program Status Word) and
PC will be popped by the RTE instruction. */
"POP R15 \n" \
/* Load the stack pointer of the task that is now selected as the Running /* Accumulator low 32 bits. */
* state task from its TCB. */ "MVTACLO R15, A0 \n" \
"MOV.L #_pxCurrentTCB,R15 \n"\ "POP R15 \n" \
"MOV.L [ R15 ], R15 \n"\
"MOV.L [ R15 ], R0 \n"\
/* Accumulator high 32 bits. */
"MVTACHI R15, A0 \n" \
"POP R15 \n" \
/* Restore the context of the new task. The PSW (Program Status Word) and /* Accumulator guard. */
* PC will be popped by the RTE instruction. */ "MVTACGU R15, A0 \n" \
"POP R15 \n"\ "POP R15 \n" \
/* Accumulator low 32 bits. */ /* Accumulator low 32 bits. */
"MVTACLO R15, A0 \n"\ "MVTACLO R15, A1 \n" \
"POP R15 \n"\ "POP R15 \n" \
/* Accumulator high 32 bits. */ /* Accumulator high 32 bits. */
"MVTACHI R15, A0 \n"\ "MVTACHI R15, A1 \n" \
"POP R15 \n"\ "POP R15 \n" \
/* Accumulator guard. */ /* Accumulator guard. */
"MVTACGU R15, A0 \n"\ "MVTACGU R15, A1 \n" \
"POP R15 \n"\ "POP R15 \n" \
"MVTC R15, FPSW \n" \
/* Accumulator low 32 bits. */ "POPM R1-R15 \n" \
"MVTACLO R15, A1 \n"\ "RTE \n" \
"POP R15 \n"\ "NOP \n" \
"NOP "
/* Accumulator high 32 bits. */ :: "i"(configMAX_SYSCALL_INTERRUPT_PRIORITY), "i"(configKERNEL_INTERRUPT_PRIORITY)
"MVTACHI R15, A1 \n"\ );
"POP R15 \n"\
/* Accumulator guard. */
"MVTACGU R15, A1 \n"\
"POP R15 \n"\
"MVTC R15, FPSW \n"\
"POPM R1-R15 \n"\
"RTE \n"\
"NOP \n"\
"NOP "
::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ), "i" ( configKERNEL_INTERRUPT_PRIORITY )
);
} }
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
void vTickISR( void ) void vTickISR( void )
{ {
/* Re-enabled interrupts. */ /* Re-enabled interrupts. */
__asm volatile ( "SETPSW I"); __asm volatile( "SETPSW I" );
/* Increment the tick, and perform any processing the new tick value /* Increment the tick, and perform any processing the new tick value
* necessitates. Ensure IPL is at the max syscall value first. */ necessitates. Ensure IPL is at the max syscall value first. */
portMASK_INTERRUPTS_FROM_KERNEL_ISR(); portMASK_INTERRUPTS_FROM_KERNEL_ISR();
{ {
if( xTaskIncrementTick() != pdFALSE ) if( xTaskIncrementTick() != pdFALSE )
{ {
taskYIELD(); taskYIELD();
} }
} }
portUNMASK_INTERRUPTS_FROM_KERNEL_ISR(); portUNMASK_INTERRUPTS_FROM_KERNEL_ISR();
} }
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
uint32_t ulPortGetIPL( void ) uint32_t ulPortGetIPL( void )
{ {
__asm volatile __asm volatile
( (
"MVFC PSW, R1 \n"\ "MVFC PSW, R1 \n" \
"SHLR #24, R1 \n"\ "SHLR #24, R1 \n" \
"RTS " "RTS "
); );
/* This will never get executed, but keeps the compiler from complaining. */ /* This will never get executed, but keeps the compiler from complaining. */
return 0; return 0;
} }
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
void vPortSetIPL( uint32_t ulNewIPL ) void vPortSetIPL( uint32_t ulNewIPL )
{ {
__asm volatile /* Avoid compiler warning about unreferenced parameter. */
( ( void ) ulNewIPL;
"PUSH R5 \n"\
"MVFC PSW, R5 \n"\ __asm volatile
"SHLL #24, R1 \n"\ (
"AND #-0F000001H, R5 \n"\ "PUSH R5 \n" \
"OR R1, R5 \n"\ "MVFC PSW, R5 \n" \
"MVTC R5, PSW \n"\ "SHLL #24, R1 \n" \
"POP R5 \n"\ "AND #-0F000001H, R5 \n" \
"RTS " "OR R1, R5 \n" \
); "MVTC R5, PSW \n" \
"POP R5 \n" \
"RTS "
);
} }

134
portable/GCC/RX600v2/portmacro.h
View file

@ -44,94 +44,94 @@
*/ */
/* Type definitions - these are a bit legacy and not really used now, other than /* Type definitions - these are a bit legacy and not really used now, other than
* portSTACK_TYPE and portBASE_TYPE. */ portSTACK_TYPE and portBASE_TYPE. */
#define portCHAR char #define portCHAR char
#define portFLOAT float #define portFLOAT float
#define portDOUBLE double #define portDOUBLE double
#define portLONG long #define portLONG long
#define portSHORT short #define portSHORT short
#define portSTACK_TYPE uint32_t #define portSTACK_TYPE uint32_t
#define portBASE_TYPE long #define portBASE_TYPE long
typedef portSTACK_TYPE StackType_t; typedef portSTACK_TYPE StackType_t;
typedef long BaseType_t; typedef long BaseType_t;
typedef unsigned long UBaseType_t; typedef unsigned long UBaseType_t;
#if ( configUSE_16_BIT_TICKS == 1 ) #if( configUSE_16_BIT_TICKS == 1 )
typedef uint16_t TickType_t; typedef uint16_t TickType_t;
#define portMAX_DELAY ( TickType_t ) 0xffff #define portMAX_DELAY ( TickType_t ) 0xffff
#else #else
typedef uint32_t TickType_t; typedef uint32_t TickType_t;
#define portMAX_DELAY ( TickType_t ) 0xffffffffUL #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
* not need to be guarded with a critical section. */ not need to be guarded with a critical section. */
#define portTICK_TYPE_IS_ATOMIC 1 #define portTICK_TYPE_IS_ATOMIC 1
#endif #endif
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
/* Hardware specifics. */ /* Hardware specifics. */
#define portBYTE_ALIGNMENT 8 /* Could make four, according to manual. */ #define portBYTE_ALIGNMENT 8 /* Could make four, according to manual. */
#define portSTACK_GROWTH -1 #define portSTACK_GROWTH -1
#define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ ) #define portTICK_PERIOD_MS ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
#define portNOP() __asm volatile ( "NOP" ) #define portNOP() __asm volatile( "NOP" )
/* Yield equivalent to "*portITU_SWINTR = 0x01; ( void ) *portITU_SWINTR;" /* Yield equivalent to "*portITU_SWINTR = 0x01; ( void ) *portITU_SWINTR;"
* where portITU_SWINTR is the location of the software interrupt register where portITU_SWINTR is the location of the software interrupt register
* (0x000872E0). Don't rely on the assembler to select a register, so instead (0x000872E0). Don't rely on the assembler to select a register, so instead
* save and restore clobbered registers manually. */ save and restore clobbered registers manually. */
#define portYIELD() \ #define portYIELD() \
__asm volatile \ __asm volatile \
( \ ( \
"PUSH.L R10 \n"\ "PUSH.L R10 \n" \
"MOV.L #0x872E0, R10 \n"\ "MOV.L #0x872E0, R10 \n" \
"MOV.B #0x1, [R10] \n"\ "MOV.B #0x1, [R10] \n" \
"MOV.L [R10], R10 \n"\ "MOV.L [R10], R10 \n" \
"POP R10 \n"\ "POP R10 \n" \
) )
#define portYIELD_FROM_ISR( x ) if( x != pdFALSE ) portYIELD() #define portYIELD_FROM_ISR( x ) if( x != pdFALSE ) portYIELD()
/* These macros should not be called directly, but through the /* These macros should not be called directly, but through the
* taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros. An extra check is taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros. An extra check is
* performed if configASSERT() is defined to ensure an assertion handler does not performed if configASSERT() is defined to ensure an assertion handler does not
* inadvertently attempt to lower the IPL when the call to assert was triggered inadvertently attempt to lower the IPL when the call to assert was triggered
* because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY because the IPL value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY
* when an ISR safe FreeRTOS API function was executed. ISR safe FreeRTOS API when an ISR safe FreeRTOS API function was executed. ISR safe FreeRTOS API
* functions are those that end in FromISR. FreeRTOS maintains a separate functions are those that end in FromISR. FreeRTOS maintains a separate
* interrupt API to ensure API function and interrupt entry is as fast and as interrupt API to ensure API function and interrupt entry is as fast and as
* simple as possible. */ simple as possible. */
#define portENABLE_INTERRUPTS() __asm volatile ( "MVTIPL #0") #define portENABLE_INTERRUPTS() __asm volatile ( "MVTIPL #0" )
#ifdef configASSERT #ifdef configASSERT
#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( ulPortGetIPL() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) ) #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( ulPortGetIPL() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
#define portDISABLE_INTERRUPTS() if( ulPortGetIPL() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __asm volatile ( "MVTIPL %0"::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) ) #define portDISABLE_INTERRUPTS() if( ulPortGetIPL() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __asm volatile ( "MVTIPL %0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) )
#else #else
#define portDISABLE_INTERRUPTS() __asm volatile ( "MVTIPL %0"::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) ) #define portDISABLE_INTERRUPTS() __asm volatile ( "MVTIPL %0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) )
#endif #endif
/* Critical nesting counts are stored in the TCB. */ /* Critical nesting counts are stored in the TCB. */
#define portCRITICAL_NESTING_IN_TCB ( 1 ) #define portCRITICAL_NESTING_IN_TCB ( 1 )
/* The critical nesting functions defined within tasks.c. */ /* The critical nesting functions defined within tasks.c. */
extern void vTaskEnterCritical( void ); extern void vTaskEnterCritical( void );
extern void vTaskExitCritical( void ); extern void vTaskExitCritical( void );
#define portENTER_CRITICAL() vTaskEnterCritical() #define portENTER_CRITICAL() vTaskEnterCritical()
#define portEXIT_CRITICAL() vTaskExitCritical() #define portEXIT_CRITICAL() vTaskExitCritical()
/* As this port allows interrupt nesting... */ /* As this port allows interrupt nesting... */
uint32_t ulPortGetIPL( void ) __attribute__( ( naked ) ); uint32_t ulPortGetIPL( void ) __attribute__((naked));
void vPortSetIPL( uint32_t ulNewIPL ) __attribute__( ( naked ) ); void vPortSetIPL( uint32_t ulNewIPL ) __attribute__((naked));
#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortGetIPL(); portDISABLE_INTERRUPTS() #define portSET_INTERRUPT_MASK_FROM_ISR() ulPortGetIPL(); portDISABLE_INTERRUPTS()
#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) vPortSetIPL( uxSavedInterruptStatus ) #define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) vPortSetIPL( uxSavedInterruptStatus )
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
/* Task function macros as described on the FreeRTOS.org WEB site. */ /* Task function macros as described on the FreeRTOS.org WEB site. */
#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters ) #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters ) #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif
#endif /* PORTMACRO_H */ #endif /* PORTMACRO_H */