len0rd/FreeRTOS-Kernel
1
0
Fork 0
mirror of https://github.com/FreeRTOS/FreeRTOS-Kernel.git synced 2025-10-13 16:27:43 -04:00
Code Issues Projects Releases Packages Wiki Activity

Remove redundant code and preprocessor directives

Browse source
This commit is contained in:
Pascal Reich 2025-09-30 00:23:20 -04:00
parent a8ae21c88e
commit d5b2130646
1 changed files with 12 additions and 19 deletions
Download patch file Download diff file Expand all files Collapse all files

31
portable/ThirdParty/GCC/RP2040/port.c vendored
View file

@ -243,35 +243,28 @@ void vPortStartFirstTask( void )
" ldr r0, [r0] \n" " ldr r0, [r0] \n"
" msr msp, r0 \n" /* Set the msp back to the start of the stack. */ " msr msp, r0 \n" /* Set the msp back to the start of the stack. */
#endif /* configRESET_STACK_POINTER */ #endif /* configRESET_STACK_POINTER */
#if ( configNUMBER_OF_CORES != 1 )
" adr r1, ulAsmLocals \n" /* Get the location of the current TCB for the current core. */ " adr r1, ulAsmLocals \n" /* Get the location of the current TCB for the current core. */
" ldmia r1!, {r2, r3} \n" " ldmia r1!, {r2, r3} \n"
" ldr r2, [r2] \n" /* r2 = Core number */ " ldr r2, [r2] \n" /* r2 = Core number */
" lsls r2, #2 \n" " lsls r2, #2 \n"
" ldr r3, [r3, r2] \n" /* r3 = pxCurrentTCBs[get_core_num()] */ " ldr r3, [r3, r2] \n" /* r3 = pxCurrentTCBs[get_core_num()] */
#else /* configNUMBER_OF_CORES != 1 */ " ldr r0, [r3] \n" /* The first item in pxCurrentTCB is the task top of stack. */
" ldr r3, =pxCurrentTCBs \n" " adds r0, #32 \n" /* Discard everything up to r0. */
" ldr r3, [r3] \n" /* r3 = pxCurrentTCBs[0] */ " msr psp, r0 \n" /* This is now the new top of stack to use in the task. */
#endif /* configNUMBER_OF_CORES != 1 */ " movs r0, #2 \n" /* Switch to the psp stack. */
" ldr r0, [r3] \n" /* The first item in pxCurrentTCB is the task top of stack. */ " msr CONTROL, r0 \n"
" adds r0, #32 \n" /* Discard everything up to r0. */ " isb \n"
" msr psp, r0 \n" /* This is now the new top of stack to use in the task. */ " pop {r0-r5} \n" /* Pop the registers that are saved automatically. */
" movs r0, #2 \n" /* Switch to the psp stack. */ " mov lr, r5 \n" /* lr is now in r5. */
" msr CONTROL, r0 \n" " pop {r3} \n" /* Return address is now in r3. */
" isb \n" " pop {r2} \n" /* Pop and discard XPSR. */
" pop {r0-r5} \n" /* Pop the registers that are saved automatically. */ " cpsie i \n" /* The first task has its context and interrupts can be enabled. */
" mov lr, r5 \n" /* lr is now in r5. */ " bx r3 \n" /* Finally, jump to the user defined task code. */
" pop {r3} \n" /* Return address is now in r3. */
" pop {r2} \n" /* Pop and discard XPSR. */
" cpsie i \n" /* The first task has its context and interrupts can be enabled. */
" bx r3 \n" /* Finally, jump to the user defined task code. */
#if configNUMBER_OF_CORES != 1
" \n" " \n"
" .align 4 \n" " .align 4 \n"
"ulAsmLocals: \n" "ulAsmLocals: \n"
" .word 0xD0000000 \n" /* SIO */ " .word 0xD0000000 \n" /* SIO */
" .word pxCurrentTCBs \n" " .word pxCurrentTCBs \n"
#endif /* portRUNNING_ON_BOTH_CORES */
); );
#endif /* if ( configNUMBER_OF_CORES == 1 ) */ #endif /* if ( configNUMBER_OF_CORES == 1 ) */
} }