mirror of
https://github.com/FreeRTOS/FreeRTOS-Kernel.git
synced 2025-12-10 05:35:17 -05:00
Update previous AVR ATmega0 and AVR Dx projecs + addition of equivalent projects in MPLAB.X and IAR (#180)
* Updated indentation in AVR_ATMega4809_Atmel_Studio and AVR_Dx_Atmel_Studio projects, plus small fixes in their readme files. * Added AVR_ATMega4809_IAR, AVR_ATMega4809_MPLAB.X, AVR_Dx_IAR and AVR_Dx_MPLAB.X demo projects. * Removed build artefacts and added .gitignore files in AVR_ATMega4809_MPLAB.X and AVR_Dx_MPLAB.X projects. Co-authored-by: Yuhui Zheng <10982575+yuhui-zheng@users.noreply.github.com>
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103 changed files with 24974 additions and 1368 deletions
382
FreeRTOS/Demo/AVR_Dx_IAR/RegTest.c
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382
FreeRTOS/Demo/AVR_Dx_IAR/RegTest.c
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/*
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* FreeRTOS Kernel V10.3.0
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* Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy of
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* this software and associated documentation files (the "Software"), to deal in
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* the Software without restriction, including without limitation the rights to
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* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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* the Software, and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* http://www.FreeRTOS.org
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* http://aws.amazon.com/freertos
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*
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* 1 tab == 4 spaces!
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*/
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/* Scheduler include files. */
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#include "FreeRTOS.h"
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#include "task.h"
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/* Demo file headers. */
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#include "regtest.h"
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/* Test tasks that sets registers to known values, then checks to ensure the
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values remain as expected. Test 1 and test 2 use different values. */
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static void prvRegisterCheck1( void *pvParameters );
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static void prvRegisterCheck2( void *pvParameters );
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/* Set to a non zero value should an error be found. */
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portBASE_TYPE xRegTestError = pdFALSE;
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/*-----------------------------------------------------------*/
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void vStartRegTestTasks( void )
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{
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xTaskCreate( prvRegisterCheck1, "Reg1", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
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xTaskCreate( prvRegisterCheck2, "Reg2", configMINIMAL_STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
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}
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/*-----------------------------------------------------------*/
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portBASE_TYPE xAreRegTestTasksStillRunning( void )
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{
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portBASE_TYPE xReturn;
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/* If a register was found to contain an unexpected value then the
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xRegTestError variable would have been set to a non zero value. */
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if( xRegTestError == pdFALSE )
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{
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xReturn = pdTRUE;
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}
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else
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{
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xReturn = pdFALSE;
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}
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return xReturn;
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}
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/*-----------------------------------------------------------*/
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static void prvRegisterCheck1( void *pvParameters )
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{
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( void ) pvParameters;
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for( ;; )
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{
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asm( "LDI r31, 5 \n"
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"MOV r0, r31 \n"
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"LDI r31, 6 \n"
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"MOV r1, r31 \n"
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"LDI r31, 7 \n"
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"MOV r2, r31 \n"
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"LDI r31, 8 \n"
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"MOV r3, r31 \n"
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"LDI r31, 9 \n"
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"MOV r4, r31 \n"
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"LDI r31, 10 \n"
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"MOV r5, r31 \n"
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"LDI r31, 11 \n"
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"MOV r6, r31 \n"
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"LDI r31, 12 \n"
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"MOV r7, r31 \n"
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"LDI r31, 13 \n"
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"MOV r8, r31 \n"
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"LDI r31, 14 \n"
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"MOV r9, r31 \n"
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"LDI r31, 15 \n"
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"MOV r10, r31 \n"
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"LDI r31, 16 \n"
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"MOV r11, r31 \n"
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"LDI r31, 17 \n"
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"MOV r12, r31 \n"
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"LDI r31, 18 \n"
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"MOV r13, r31 \n"
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"LDI r31, 19 \n"
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"MOV r14, r31 \n"
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"LDI r31, 20 \n"
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"MOV r15, r31 \n"
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"LDI r16, 21 \n"
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"LDI r17, 22 \n"
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"LDI r18, 23 \n"
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"LDI r19, 24 \n"
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"LDI r20, 25 \n"
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"LDI r21, 26 \n"
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"LDI r22, 27 \n"
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"LDI r23, 28 \n"
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"LDI r24, 29 \n"
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"LDI r25, 30 \n"
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"LDI r26, 31 \n"
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"LDI r27, 32 \n"
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"LDI r28, 33 \n"
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"LDI r29, 34 \n"
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"LDI r30, 35 " );
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taskYIELD();
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asm( "CPI r31, 20 \n"
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"BREQ no_err_1 \n"
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"STS xRegTestError, r0 \n"
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"no_err_1: \n"
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"LDI r31, 5 \n"
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"CPSE r31, r0 \n"
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"STS xRegTestError, r0 \n"
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"LDI r31, 6 \n"
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"CPSE r31, r1 \n"
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"STS xRegTestError, r0 \n"
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"LDI r31, 7 \n"
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"CPSE r31, r2 \n"
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"STS xRegTestError, r0 \n"
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"LDI r31, 8 \n"
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"CPSE r31, r3 \n"
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"STS xRegTestError, r0 \n"
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"LDI r31, 9 \n"
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"CPSE r31, r4 \n"
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"STS xRegTestError, r0 \n"
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"LDI r31, 10 \n"
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"CPSE r31, r5 \n"
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"STS xRegTestError, r0 \n"
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"LDI r31, 11 \n"
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"CPSE r31, r6 \n"
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"STS xRegTestError, r0 \n"
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"LDI r31, 12 \n"
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"CPSE r31, r7 \n"
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"STS xRegTestError, r0 \n"
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"LDI r31, 13 \n"
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"CPSE r31, r8 \n"
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"STS xRegTestError, r0 \n"
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"LDI r31, 14 \n"
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"CPSE r31, r9 \n"
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"STS xRegTestError, r0 \n"
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"LDI r31, 15 \n"
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"CPSE r31, r10 \n"
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"STS xRegTestError, r0 \n"
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"LDI r31, 16 \n"
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"CPSE r31, r11 \n"
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"STS xRegTestError, r0 \n"
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"LDI r31, 17 \n"
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"CPSE r31, r12 \n"
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"STS xRegTestError, r0 \n"
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"LDI r31, 18 \n"
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"CPSE r31, r13 \n"
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"STS xRegTestError, r0 \n"
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"LDI r31, 19 \n"
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"CPSE r31, r14 \n"
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"STS xRegTestError, r0 \n"
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"LDI r31, 20 \n"
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"CPSE r31, r15 \n"
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"STS xRegTestError, r0 \n"
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"LDI r31, 21 \n"
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"CPSE r31, r16 \n"
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"STS xRegTestError, r0 \n"
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"LDI r31, 22 \n"
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"CPSE r31, r17 \n"
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"STS xRegTestError, r0 \n"
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"LDI r31, 23 \n"
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"CPSE r31, r18 \n"
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"STS xRegTestError, r0 \n"
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"LDI r31, 24 \n"
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"CPSE r31, r19 \n"
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"STS xRegTestError, r0 \n"
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"LDI r31, 25 \n"
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"CPSE r31, r20 \n"
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"STS xRegTestError, r0 \n"
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"LDI r31, 26 \n"
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"CPSE r31, r21 \n"
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"STS xRegTestError, r0 \n"
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"LDI r31, 27 \n"
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"CPSE r31, r22 \n"
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"STS xRegTestError, r0 \n"
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"LDI r31, 28 \n"
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"CPSE r31, r23 \n"
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"STS xRegTestError, r0 \n"
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"LDI r31, 29 \n"
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"CPSE r31, r24 \n"
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"STS xRegTestError, r0 \n"
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"LDI r31, 30 \n"
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"CPSE r31, r25 \n"
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"STS xRegTestError, r0 \n"
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"LDI r31, 31 \n"
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"CPSE r31, r26 \n"
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"STS xRegTestError, r0 \n"
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"LDI r31, 32 \n"
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"CPSE r31, r27 \n"
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"STS xRegTestError, r0 \n"
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"LDI r31, 33 \n"
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"CPSE r31, r28 \n"
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"STS xRegTestError, r0 \n"
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"LDI r31, 34 \n"
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"CPSE r31, r29 \n"
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"STS xRegTestError, r0 \n"
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"LDI r31, 35 \n"
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"CPSE r31, r30 \n"
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"STS xRegTestError, r0 " );
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}
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}
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/*-----------------------------------------------------------*/
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static void prvRegisterCheck2( void *pvParameters )
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{
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( void ) pvParameters;
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for( ;; )
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{
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asm( "LDI r31, 1 \n"
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"MOV r0, r31 \n"
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"LDI r31, 2 \n"
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"MOV r1, r31 \n"
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"LDI r31, 3 \n"
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"MOV r2, r31 \n"
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"LDI r31, 4 \n"
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"MOV r3, r31 \n"
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"LDI r31, 5 \n"
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"MOV r4, r31 \n"
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"LDI r31, 6 \n"
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"MOV r5, r31 \n"
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"LDI r31, 7 \n"
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"MOV r6, r31 \n"
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"LDI r31, 8 \n"
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"MOV r7, r31 \n"
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"LDI r31, 9 \n"
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"MOV r8, r31 \n"
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"LDI r31, 10 \n"
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"MOV r9, r31 \n"
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"LDI r31, 11 \n"
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"MOV r10, r31 \n"
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"LDI r31, 12 \n"
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"MOV r11, r31 \n"
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"LDI r31, 13 \n"
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"MOV r12, r31 \n"
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"LDI r31, 14 \n"
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"MOV r13, r31 \n"
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"LDI r31, 15 \n"
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"MOV r14, r31 \n"
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"LDI r31, 16 \n"
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"MOV r15, r31 \n"
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"LDI r16, 17 \n"
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"LDI r17, 18 \n"
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"LDI r18, 19 \n"
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"LDI r19, 20 \n"
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"LDI r20, 21 \n"
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"LDI r21, 22 \n"
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"LDI r22, 23 \n"
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"LDI r23, 24 \n"
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"LDI r24, 25 \n"
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"LDI r25, 26 \n"
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"LDI r26, 27 \n"
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"LDI r27, 28 \n"
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"LDI r28, 29 \n"
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"LDI r29, 30 \n"
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"LDI r30, 31 " );
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taskYIELD();
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asm( "CPI r31, 16 \n"
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"BREQ no_err_2 \n"
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"STS xRegTestError, r0 \n"
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"no_err_2: \n"
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"LDI r31, 1 \n"
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"CPSE r31, r0 \n"
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"STS xRegTestError, r0 \n"
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"LDI r31, 2 \n"
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"CPSE r31, r1 \n"
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"STS xRegTestError, r0 \n"
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"LDI r31, 3 \n"
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"CPSE r31, r2 \n"
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"STS xRegTestError, r0 \n"
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"LDI r31, 4 \n"
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"CPSE r31, r3 \n"
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"STS xRegTestError, r0 \n"
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"LDI r31, 5 \n"
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"CPSE r31, r4 \n"
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"STS xRegTestError, r0 \n"
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"LDI r31, 6 \n"
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"CPSE r31, r5 \n"
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"STS xRegTestError, r0 \n"
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"LDI r31, 7 \n"
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"CPSE r31, r6 \n"
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"STS xRegTestError, r0 \n"
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"LDI r31, 8 \n"
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"CPSE r31, r7 \n"
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"STS xRegTestError, r0 \n"
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"LDI r31, 9 \n"
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"CPSE r31, r8 \n"
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"STS xRegTestError, r0 \n"
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"LDI r31, 10 \n"
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"CPSE r31, r9 \n"
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"STS xRegTestError, r0 \n"
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"LDI r31, 11 \n"
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"CPSE r31, r10 \n"
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"STS xRegTestError, r0 \n"
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"LDI r31, 12 \n"
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"CPSE r31, r11 \n"
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"STS xRegTestError, r0 \n"
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"LDI r31, 13 \n"
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"CPSE r31, r12 \n"
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"STS xRegTestError, r0 \n"
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"LDI r31, 14 \n"
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"CPSE r31, r13 \n"
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"STS xRegTestError, r0 \n"
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"LDI r31, 15 \n"
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"CPSE r31, r14 \n"
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"STS xRegTestError, r0 \n"
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"LDI r31, 16 \n"
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"CPSE r31, r15 \n"
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"STS xRegTestError, r0 \n"
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"LDI r31, 17 \n"
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"CPSE r31, r16 \n"
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"STS xRegTestError, r0 \n"
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"LDI r31, 18 \n"
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"CPSE r31, r17 \n"
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"STS xRegTestError, r0 \n"
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"LDI r31, 19 \n"
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"CPSE r31, r18 \n"
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"STS xRegTestError, r0 \n"
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"LDI r31, 20 \n"
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"CPSE r31, r19 \n"
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"STS xRegTestError, r0 \n"
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"LDI r31, 21 \n"
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"CPSE r31, r20 \n"
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"STS xRegTestError, r0 \n"
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"LDI r31, 22 \n"
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"CPSE r31, r21 \n"
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"STS xRegTestError, r0 \n"
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"LDI r31, 23 \n"
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"CPSE r31, r22 \n"
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"STS xRegTestError, r0 \n"
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"LDI r31, 24 \n"
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"CPSE r31, r23 \n"
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"STS xRegTestError, r0 \n"
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"LDI r31, 25 \n"
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"CPSE r31, r24 \n"
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"STS xRegTestError, r0 \n"
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"LDI r31, 26 \n"
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"CPSE r31, r25 \n"
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"STS xRegTestError, r0 \n"
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"LDI r31, 27 \n"
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"CPSE r31, r26 \n"
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"STS xRegTestError, r0 \n"
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"LDI r31, 28 \n"
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"CPSE r31, r27 \n"
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"STS xRegTestError, r0 \n"
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"LDI r31, 29 \n"
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"CPSE r31, r28 \n"
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"STS xRegTestError, r0 \n"
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"LDI r31, 30 \n"
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"CPSE r31, r29 \n"
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"STS xRegTestError, r0 \n"
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"LDI r31, 31 \n"
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"CPSE r31, r30 \n"
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"STS xRegTestError, r0 \n" );
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}
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}
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