mirror of
https://github.com/FreeRTOS/FreeRTOS-Kernel.git
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Restart the Microblaze project (again).
This commit is contained in:
Richard Barry
parent
3c5b78631b
commit
d4670870fb
41 changed files with 21161 additions and 0 deletions
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<?xml version="1.0" encoding="UTF-8"?>
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<!-- IMPORTANT: This is an internal file that has been generated
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by the Xilinx ISE software. Any direct editing or
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||||
changes made to this file may result in unpredictable
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behavior or data corruption. It is strongly advised that
|
||||
users do not edit the contents of this file. -->
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<messages>
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||||
<msg type="info" file="EDK" num="0" delta="new" >IPNAME: <arg fmt="%s" index="1">axi_interconnect</arg>, INSTANCE:<arg fmt="%s" index="2">axi4_0</arg> - <arg fmt="%s" index="3">tcl</arg> is overriding <arg fmt="%s" index="4">PARAMETER</arg> <arg fmt="%s" index="5">C_BASEFAMILY</arg> value to <arg fmt="%s" index="6">spartan6</arg> - <arg fmt="%s" index="7">C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_interconnect_v1_02_a\data\axi_interconnect_v2_1_0.mpd line 69</arg>
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</msg>
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<msg type="info" file="EDK" num="0" delta="new" >IPNAME: <arg fmt="%s" index="1">axi_interconnect</arg>, INSTANCE:<arg fmt="%s" index="2">axi4lite_0</arg> - <arg fmt="%s" index="3">tcl</arg> is overriding <arg fmt="%s" index="4">PARAMETER</arg> <arg fmt="%s" index="5">C_BASEFAMILY</arg> value to <arg fmt="%s" index="6">spartan6</arg> - <arg fmt="%s" index="7">C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_interconnect_v1_02_a\data\axi_interconnect_v2_1_0.mpd line 69</arg>
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</msg>
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<msg type="info" file="EDK" num="0" delta="new" >IPNAME: <arg fmt="%s" index="1">microblaze</arg>, INSTANCE:<arg fmt="%s" index="2">microblaze_0</arg> - <arg fmt="%s" index="3">tcl</arg> is overriding <arg fmt="%s" index="4">PARAMETER</arg> <arg fmt="%s" index="5">C_ENDIANNESS</arg> value to <arg fmt="%s" index="6">1</arg> - <arg fmt="%s" index="7">C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_10_a\data\microblaze_v2_1_0.mpd line 183</arg>
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</msg>
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<msg type="info" file="EDK" num="0" delta="new" >IPNAME: <arg fmt="%s" index="1">microblaze</arg>, INSTANCE:<arg fmt="%s" index="2">microblaze_0</arg> - <arg fmt="%s" index="3">tcl</arg> is overriding <arg fmt="%s" index="4">PARAMETER</arg> <arg fmt="%s" index="5">C_ICACHE_USE_FSL</arg> value to <arg fmt="%s" index="6">0</arg> - <arg fmt="%s" index="7">C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_10_a\data\microblaze_v2_1_0.mpd line 322</arg>
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</msg>
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<msg type="info" file="EDK" num="0" delta="new" >IPNAME: <arg fmt="%s" index="1">microblaze</arg>, INSTANCE:<arg fmt="%s" index="2">microblaze_0</arg> - <arg fmt="%s" index="3">tcl</arg> is overriding <arg fmt="%s" index="4">PARAMETER</arg> <arg fmt="%s" index="5">C_DCACHE_USE_FSL</arg> value to <arg fmt="%s" index="6">0</arg> - <arg fmt="%s" index="7">C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_10_a\data\microblaze_v2_1_0.mpd line 352</arg>
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</msg>
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|
||||
<msg type="info" file="EDK" num="0" delta="new" >IPNAME: <arg fmt="%s" index="1">axi_s6_ddrx</arg>, INSTANCE:<arg fmt="%s" index="2">MCB_DDR3</arg> - <arg fmt="%s" index="3">tcl</arg> is overriding <arg fmt="%s" index="4">PARAMETER</arg> <arg fmt="%s" index="5">C_SYS_RST_PRESENT</arg> value to <arg fmt="%s" index="6">1</arg> - <arg fmt="%s" index="7">C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_s6_ddrx_v1_02_a\data\axi_s6_ddrx_v2_1_0.mpd line 228</arg>
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</msg>
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<msg type="info" file="EDK" num="740" delta="new" >Cannot determine the input clock associated with port : <arg fmt="%s" index="1">microblaze_0_i_bram_ctrl</arg>:<arg fmt="%s" index="2">BRAM_Clk_A</arg>. Clock DRCs will not be performed on this core and cores connected to it.
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</msg>
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<msg type="info" file="EDK" num="740" delta="new" >Cannot determine the input clock associated with port : <arg fmt="%s" index="1">microblaze_0_d_bram_ctrl</arg>:<arg fmt="%s" index="2">BRAM_Clk_A</arg>. Clock DRCs will not be performed on this core and cores connected to it.
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</msg>
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<msg type="info" file="EDK" num="0" delta="new" >IPNAME: <arg fmt="%s" index="1">axi_ethernetlite</arg>, INSTANCE: <arg fmt="%s" index="2">Ethernet_Lite</arg> - <arg fmt="%s" index="3">This design requires design constraints to guarantee performance.
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Please refer to the data sheet for details.
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The AXI clock frequency must be greater than or equal to 50 MHz for 100 Mbs Ethernet operation and greater than or equal to 5.0 MHz for 10 Mbs Ethernet operation.</arg> - <arg fmt="%s" index="4">C:\E\Dev\FreeRTOS\WorkingCopy\Demo\MicroBlaze_Spartan-6_SP605\system.mhs line 324</arg>
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</msg>
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||||
|
||||
<msg type="info" file="EDK" num="0" delta="new" >IPNAME: <arg fmt="%s" index="1">lmb_v10</arg>, INSTANCE:<arg fmt="%s" index="2">microblaze_0_ilmb</arg> - <arg fmt="%s" index="3">tool</arg> is overriding <arg fmt="%s" index="4">PARAMETER</arg> <arg fmt="%s" index="5">C_LMB_NUM_SLAVES</arg> value to <arg fmt="%s" index="6">1</arg> - <arg fmt="%s" index="7">C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\lmb_v10_v2_00_a\data\lmb_v10_v2_1_0.mpd line 70</arg>
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</msg>
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||||
|
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<msg type="info" file="EDK" num="0" delta="new" >IPNAME: <arg fmt="%s" index="1">lmb_v10</arg>, INSTANCE:<arg fmt="%s" index="2">microblaze_0_dlmb</arg> - <arg fmt="%s" index="3">tool</arg> is overriding <arg fmt="%s" index="4">PARAMETER</arg> <arg fmt="%s" index="5">C_LMB_NUM_SLAVES</arg> value to <arg fmt="%s" index="6">1</arg> - <arg fmt="%s" index="7">C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\lmb_v10_v2_00_a\data\lmb_v10_v2_1_0.mpd line 70</arg>
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</msg>
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<msg type="info" file="EDK" num="0" delta="new" >IPNAME: <arg fmt="%s" index="1">bram_block</arg>, INSTANCE:<arg fmt="%s" index="2">microblaze_0_bram_block</arg> - <arg fmt="%s" index="3">tool</arg> is overriding <arg fmt="%s" index="4">PARAMETER</arg> <arg fmt="%s" index="5">C_MEMSIZE</arg> value to <arg fmt="%s" index="6">0x2000</arg> - <arg fmt="%s" index="7">C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\bram_block_v1_00_a\data\bram_block_v2_1_0.mpd line 67</arg>
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</msg>
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||||
|
||||
<msg type="warning" file="EDK" num="0" delta="new" >PORT: <arg fmt="%s" index="1">bscan_tdo1</arg>, CONNECTOR: <arg fmt="%s" index="2">bscan_tdo1</arg> - No driver found. Port will be driven to <arg fmt="%s" index="3">GND</arg> - <arg fmt="%s" index="4">C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\mdm_v2_00_b\data\mdm_v2_1_0.mpd line 230</arg>
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</msg>
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|
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<msg type="warning" file="EDK" num="0" delta="new" >PORT: <arg fmt="%s" index="1">bscan_tdi</arg>, CONNECTOR: <arg fmt="%s" index="2">bscan_tdi</arg> - floating connection - <arg fmt="%s" index="3">C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\mdm_v2_00_b\data\mdm_v2_1_0.mpd line 223</arg>
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</msg>
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||||
|
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<msg type="warning" file="EDK" num="0" delta="new" >PORT: <arg fmt="%s" index="1">bscan_reset</arg>, CONNECTOR: <arg fmt="%s" index="2">bscan_reset</arg> - floating connection - <arg fmt="%s" index="3">C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\mdm_v2_00_b\data\mdm_v2_1_0.mpd line 224</arg>
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</msg>
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<msg type="warning" file="EDK" num="0" delta="new" >PORT: <arg fmt="%s" index="1">bscan_shift</arg>, CONNECTOR: <arg fmt="%s" index="2">bscan_shift</arg> - floating connection - <arg fmt="%s" index="3">C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\mdm_v2_00_b\data\mdm_v2_1_0.mpd line 225</arg>
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</msg>
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<msg type="warning" file="EDK" num="0" delta="new" >PORT: <arg fmt="%s" index="1">bscan_update</arg>, CONNECTOR: <arg fmt="%s" index="2">bscan_update</arg> - floating connection - <arg fmt="%s" index="3">C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\mdm_v2_00_b\data\mdm_v2_1_0.mpd line 226</arg>
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</msg>
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||||
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<msg type="warning" file="EDK" num="0" delta="new" >PORT: <arg fmt="%s" index="1">bscan_capture</arg>, CONNECTOR: <arg fmt="%s" index="2">bscan_capture</arg> - floating connection - <arg fmt="%s" index="3">C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\mdm_v2_00_b\data\mdm_v2_1_0.mpd line 227</arg>
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</msg>
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<msg type="warning" file="EDK" num="0" delta="new" >PORT: <arg fmt="%s" index="1">bscan_sel1</arg>, CONNECTOR: <arg fmt="%s" index="2">bscan_sel1</arg> - floating connection - <arg fmt="%s" index="3">C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\mdm_v2_00_b\data\mdm_v2_1_0.mpd line 228</arg>
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</msg>
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<msg type="warning" file="EDK" num="0" delta="new" >PORT: <arg fmt="%s" index="1">bscan_drck1</arg>, CONNECTOR: <arg fmt="%s" index="2">bscan_drck1</arg> - floating connection - <arg fmt="%s" index="3">C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\mdm_v2_00_b\data\mdm_v2_1_0.mpd line 229</arg>
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</msg>
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<msg type="info" file="EDK" num="0" delta="new" >IPNAME: <arg fmt="%s" index="1">axi_interconnect</arg>, INSTANCE:<arg fmt="%s" index="2">axi4_0</arg> - <arg fmt="%s" index="3">tcl</arg> is overriding <arg fmt="%s" index="4">PARAMETER</arg> <arg fmt="%s" index="5">C_RANGE_CHECK</arg> value to <arg fmt="%s" index="6">0</arg> - <arg fmt="%s" index="7">C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_interconnect_v1_02_a\data\axi_interconnect_v2_1_0.mpd line 137</arg>
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</msg>
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<msg type="info" file="EDK" num="0" delta="new" >IPNAME: <arg fmt="%s" index="1">axi_interconnect</arg>, INSTANCE:<arg fmt="%s" index="2">axi4lite_0</arg> - <arg fmt="%s" index="3">tcl</arg> is overriding <arg fmt="%s" index="4">PARAMETER</arg> <arg fmt="%s" index="5">C_RANGE_CHECK</arg> value to <arg fmt="%s" index="6">1</arg> - <arg fmt="%s" index="7">C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_interconnect_v1_02_a\data\axi_interconnect_v2_1_0.mpd line 137</arg>
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</msg>
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<msg type="info" file="EDK" num="0" delta="new" >IPNAME: <arg fmt="%s" index="1">microblaze</arg>, INSTANCE:<arg fmt="%s" index="2">microblaze_0</arg> - <arg fmt="%s" index="3">tcl</arg> is overriding <arg fmt="%s" index="4">PARAMETER</arg> <arg fmt="%s" index="5">C_D_AXI</arg> value to <arg fmt="%s" index="6">1</arg> - <arg fmt="%s" index="7">C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_10_a\data\microblaze_v2_1_0.mpd line 216</arg>
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</msg>
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<msg type="info" file="EDK" num="0" delta="new" >IPNAME: <arg fmt="%s" index="1">microblaze</arg>, INSTANCE:<arg fmt="%s" index="2">microblaze_0</arg> - <arg fmt="%s" index="3">tcl</arg> is overriding <arg fmt="%s" index="4">PARAMETER</arg> <arg fmt="%s" index="5">C_ADDR_TAG_BITS</arg> value to <arg fmt="%s" index="6">13</arg> - <arg fmt="%s" index="7">C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_10_a\data\microblaze_v2_1_0.mpd line 320</arg>
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</msg>
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<msg type="info" file="EDK" num="0" delta="new" >IPNAME: <arg fmt="%s" index="1">microblaze</arg>, INSTANCE:<arg fmt="%s" index="2">microblaze_0</arg> - <arg fmt="%s" index="3">tcl</arg> is overriding <arg fmt="%s" index="4">PARAMETER</arg> <arg fmt="%s" index="5">C_DCACHE_ADDR_TAG</arg> value to <arg fmt="%s" index="6">13</arg> - <arg fmt="%s" index="7">C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_10_a\data\microblaze_v2_1_0.mpd line 350</arg>
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</msg>
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<msg type="info" file="EDK" num="0" delta="new" >IPNAME: <arg fmt="%s" index="1">microblaze</arg>, INSTANCE:<arg fmt="%s" index="2">microblaze_0</arg> - <arg fmt="%s" index="3">tcl</arg> is overriding <arg fmt="%s" index="4">PARAMETER</arg> <arg fmt="%s" index="5">C_USE_INTERRUPT</arg> value to <arg fmt="%s" index="6">1</arg> - <arg fmt="%s" index="7">C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_10_a\data\microblaze_v2_1_0.mpd line 384</arg>
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</msg>
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<msg type="info" file="EDK" num="0" delta="new" >IPNAME: <arg fmt="%s" index="1">microblaze</arg>, INSTANCE:<arg fmt="%s" index="2">microblaze_0</arg> - <arg fmt="%s" index="3">tcl</arg> is overriding <arg fmt="%s" index="4">PARAMETER</arg> <arg fmt="%s" index="5">C_USE_EXT_BRK</arg> value to <arg fmt="%s" index="6">1</arg> - <arg fmt="%s" index="7">C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_10_a\data\microblaze_v2_1_0.mpd line 385</arg>
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</msg>
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<msg type="info" file="EDK" num="0" delta="new" >IPNAME: <arg fmt="%s" index="1">microblaze</arg>, INSTANCE:<arg fmt="%s" index="2">microblaze_0</arg> - <arg fmt="%s" index="3">tcl</arg> is overriding <arg fmt="%s" index="4">PARAMETER</arg> <arg fmt="%s" index="5">C_USE_EXT_NM_BRK</arg> value to <arg fmt="%s" index="6">1</arg> - <arg fmt="%s" index="7">C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v8_10_a\data\microblaze_v2_1_0.mpd line 386</arg>
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</msg>
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<msg type="info" file="EDK" num="0" delta="new" >IPNAME: <arg fmt="%s" index="1">lmb_bram_if_cntlr</arg>, INSTANCE:<arg fmt="%s" index="2">microblaze_0_i_bram_ctrl</arg> - <arg fmt="%s" index="3">tcl</arg> is overriding <arg fmt="%s" index="4">PARAMETER</arg> <arg fmt="%s" index="5">C_MASK</arg> value to <arg fmt="%s" index="6">0x40000000</arg> - <arg fmt="%s" index="7">C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\lmb_bram_if_cntlr_v3_00_a\data\lmb_bram_if_cntlr_v2_1_0.mpd line 78</arg>
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</msg>
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<msg type="info" file="EDK" num="0" delta="new" >IPNAME: <arg fmt="%s" index="1">lmb_bram_if_cntlr</arg>, INSTANCE:<arg fmt="%s" index="2">microblaze_0_d_bram_ctrl</arg> - <arg fmt="%s" index="3">tcl</arg> is overriding <arg fmt="%s" index="4">PARAMETER</arg> <arg fmt="%s" index="5">C_MASK</arg> value to <arg fmt="%s" index="6">0x40000000</arg> - <arg fmt="%s" index="7">C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\lmb_bram_if_cntlr_v3_00_a\data\lmb_bram_if_cntlr_v2_1_0.mpd line 78</arg>
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</msg>
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<msg type="info" file="EDK" num="0" delta="new" >IPNAME: <arg fmt="%s" index="1">axi_s6_ddrx</arg>, INSTANCE:<arg fmt="%s" index="2">MCB_DDR3</arg> - <arg fmt="%s" index="3">tcl</arg> is overriding <arg fmt="%s" index="4">PARAMETER</arg> <arg fmt="%s" index="5">C_MEMCLK_PERIOD</arg> value to <arg fmt="%s" index="6">3333</arg> - <arg fmt="%s" index="7">C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_s6_ddrx_v1_02_a\data\axi_s6_ddrx_v2_1_0.mpd line 110</arg>
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</msg>
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<msg type="info" file="EDK" num="0" delta="new" >IPNAME: <arg fmt="%s" index="1">axi_s6_ddrx</arg>, INSTANCE:<arg fmt="%s" index="2">MCB_DDR3</arg> - <arg fmt="%s" index="3">tcl</arg> is overriding <arg fmt="%s" index="4">PARAMETER</arg> <arg fmt="%s" index="5">C_S0_AXI_STRICT_COHERENCY</arg> value to <arg fmt="%s" index="6">0</arg> - <arg fmt="%s" index="7">C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_s6_ddrx_v1_02_a\data\axi_s6_ddrx_v2_1_0.mpd line 153</arg>
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</msg>
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<msg type="info" file="EDK" num="0" delta="new" >IPNAME: <arg fmt="%s" index="1">axi_s6_ddrx</arg>, INSTANCE:<arg fmt="%s" index="2">MCB_DDR3</arg> - <arg fmt="%s" index="3">tcl</arg> is overriding <arg fmt="%s" index="4">PARAMETER</arg> <arg fmt="%s" index="5">C_S1_AXI_REG_EN0</arg> value to <arg fmt="%s" index="6">0x0000F</arg> - <arg fmt="%s" index="7">C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_s6_ddrx_v1_02_a\data\axi_s6_ddrx_v2_1_0.mpd line 165</arg>
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</msg>
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<msg type="info" file="EDK" num="0" delta="new" >IPNAME: <arg fmt="%s" index="1">axi_s6_ddrx</arg>, INSTANCE:<arg fmt="%s" index="2">MCB_DDR3</arg> - <arg fmt="%s" index="3">tcl</arg> is overriding <arg fmt="%s" index="4">PARAMETER</arg> <arg fmt="%s" index="5">C_S2_AXI_REG_EN0</arg> value to <arg fmt="%s" index="6">0x0000F</arg> - <arg fmt="%s" index="7">C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_s6_ddrx_v1_02_a\data\axi_s6_ddrx_v2_1_0.mpd line 179</arg>
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</msg>
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<msg type="info" file="EDK" num="0" delta="new" >IPNAME: <arg fmt="%s" index="1">axi_s6_ddrx</arg>, INSTANCE:<arg fmt="%s" index="2">MCB_DDR3</arg> - <arg fmt="%s" index="3">tcl</arg> is overriding <arg fmt="%s" index="4">PARAMETER</arg> <arg fmt="%s" index="5">C_S3_AXI_REG_EN0</arg> value to <arg fmt="%s" index="6">0x0000F</arg> - <arg fmt="%s" index="7">C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_s6_ddrx_v1_02_a\data\axi_s6_ddrx_v2_1_0.mpd line 193</arg>
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</msg>
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|
||||
<msg type="info" file="EDK" num="0" delta="new" >IPNAME: <arg fmt="%s" index="1">axi_s6_ddrx</arg>, INSTANCE:<arg fmt="%s" index="2">MCB_DDR3</arg> - <arg fmt="%s" index="3">tcl</arg> is overriding <arg fmt="%s" index="4">PARAMETER</arg> <arg fmt="%s" index="5">C_S4_AXI_REG_EN0</arg> value to <arg fmt="%s" index="6">0x0000F</arg> - <arg fmt="%s" index="7">C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_s6_ddrx_v1_02_a\data\axi_s6_ddrx_v2_1_0.mpd line 207</arg>
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="EDK" num="0" delta="new" >IPNAME: <arg fmt="%s" index="1">axi_s6_ddrx</arg>, INSTANCE:<arg fmt="%s" index="2">MCB_DDR3</arg> - <arg fmt="%s" index="3">tcl</arg> is overriding <arg fmt="%s" index="4">PARAMETER</arg> <arg fmt="%s" index="5">C_S5_AXI_REG_EN0</arg> value to <arg fmt="%s" index="6">0x0000F</arg> - <arg fmt="%s" index="7">C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_s6_ddrx_v1_02_a\data\axi_s6_ddrx_v2_1_0.mpd line 221</arg>
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="EDK" num="0" delta="new" >IPNAME: <arg fmt="%s" index="1">axi_intc</arg>, INSTANCE:<arg fmt="%s" index="2">microblaze_0_intc</arg> - <arg fmt="%s" index="3">tcl</arg> is overriding <arg fmt="%s" index="4">PARAMETER</arg> <arg fmt="%s" index="5">C_NUM_INTR_INPUTS</arg> value to <arg fmt="%s" index="6">4</arg> - <arg fmt="%s" index="7">C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_intc_v1_01_a\data\axi_intc_v2_1_0.mpd line 71</arg>
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="EDK" num="0" delta="new" >IPNAME: <arg fmt="%s" index="1">axi_intc</arg>, INSTANCE:<arg fmt="%s" index="2">microblaze_0_intc</arg> - <arg fmt="%s" index="3">tcl</arg> is overriding <arg fmt="%s" index="4">PARAMETER</arg> <arg fmt="%s" index="5">C_KIND_OF_INTR</arg> value to <arg fmt="%s" index="6">0b11111111111111111111111111111011</arg> - <arg fmt="%s" index="7">C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_intc_v1_01_a\data\axi_intc_v2_1_0.mpd line 72</arg>
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="EDK" num="0" delta="new" >IPNAME: <arg fmt="%s" index="1">axi_intc</arg>, INSTANCE:<arg fmt="%s" index="2">microblaze_0_intc</arg> - <arg fmt="%s" index="3">tcl</arg> is overriding <arg fmt="%s" index="4">PARAMETER</arg> <arg fmt="%s" index="5">C_KIND_OF_EDGE</arg> value to <arg fmt="%s" index="6">0b11111111111111111111111111111111</arg> - <arg fmt="%s" index="7">C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_intc_v1_01_a\data\axi_intc_v2_1_0.mpd line 73</arg>
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="EDK" num="0" delta="new" >IPNAME: <arg fmt="%s" index="1">axi_intc</arg>, INSTANCE:<arg fmt="%s" index="2">microblaze_0_intc</arg> - <arg fmt="%s" index="3">tcl</arg> is overriding <arg fmt="%s" index="4">PARAMETER</arg> <arg fmt="%s" index="5">C_KIND_OF_LVL</arg> value to <arg fmt="%s" index="6">0b11111111111111111111111111111111</arg> - <arg fmt="%s" index="7">C:\devtools\Xilinx\13.1\ISE_DS\EDK\hw\XilinxProcessorIPLib\pcores\axi_intc_v1_01_a\data\axi_intc_v2_1_0.mpd line 74</arg>
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="EDK" num="0" delta="new" >The following instances are synthesized with <arg fmt="%s" index="1">XST</arg>. The MPD option IMP_NETLIST=TRUE indicates that a NGC file is to be produced using <arg fmt="%s" index="2">XST</arg> synthesis. IMP_NETLIST=FALSE (default) instances are not synthesized.
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="EDK" num="3509" delta="new" >NCF files should not be modified as they will be regenerated.
|
||||
If any constraint needs to be overridden, this should be done by modifying the data/<arg fmt="%s" index="1">system</arg>.ucf file.
|
||||
</msg>
|
||||
|
||||
</messages>
|
||||
|
||||
|
|
@ -0,0 +1,218 @@
|
|||
<?xml version='1.0' encoding='UTF-8'?>
|
||||
<report-views version="2.0" >
|
||||
<header>
|
||||
<DateModified>2011-05-31T10:04:43</DateModified>
|
||||
<ModuleName>system</ModuleName>
|
||||
<SummaryTimeStamp>2011-05-31T10:04:43</SummaryTimeStamp>
|
||||
<SavedFilePath>C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/__xps/ise/system.xreport</SavedFilePath>
|
||||
<FilterFile>filter.filter</FilterFile>
|
||||
<SavedFilterFilePath>C:/E/Dev/FreeRTOS/WorkingCopy/Demo/MicroBlaze_Spartan-6_EthernetLite/PlatformStudioProject/__xps/ise</SavedFilterFilePath>
|
||||
<DateInitialized>2011-05-30T21:44:59</DateInitialized>
|
||||
<EnableMessageFiltering>false</EnableMessageFiltering>
|
||||
</header>
|
||||
<body>
|
||||
<viewgroup label="Design Overview" >
|
||||
<view inputState="Unknown" program="implementation" ShowPartitionData="false" type="FPGASummary" file="implementation\system_summary.html" label="Summary" >
|
||||
<toc-item title="Design Overview" target="Design Overview" />
|
||||
<toc-item title="Design Utilization Summary" target="Design Utilization Summary" />
|
||||
<toc-item title="Performance Summary" target="Performance Summary" />
|
||||
<toc-item title="Failing Constraints" target="Failing Constraints" />
|
||||
<toc-item title="Detailed Reports" target="Detailed Reports" />
|
||||
</view>
|
||||
<view inputState="Unknown" program="implementation" contextTags="FPGA_ONLY" hidden="true" type="HTML" file="implementation\system_envsettings.html" label="System Settings" />
|
||||
<view inputState="Translated" program="map" locator="MAP_IOB_TABLE" contextTags="FPGA_ONLY" type="IOBProperties" file="implementation\system_map.xrpt" label="IOB Properties" />
|
||||
<view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Control_Sets" file="implementation\system_map.xrpt" label="Control Set Information" />
|
||||
<view inputState="Translated" program="map" locator="MAP_MODULE_HIERARCHY" contextTags="FPGA_ONLY" type="Module_Utilization" file="implementation\system_map.xrpt" label="Module Level Utilization" />
|
||||
<view inputState="Mapped" program="par" locator="CONSTRAINT_TABLE" contextTags="FPGA_ONLY" type="ConstraintsData" file="implementation\system.ptwx" label="Timing Constraints" translator="ptwxToTableXML.xslt" />
|
||||
<view inputState="Mapped" program="par" locator="PAR_PINOUT_BY_PIN_NUMBER" contextTags="FPGA_ONLY" type="PinoutData" file="implementation\system_par.xrpt" label="Pinout Report" />
|
||||
<view inputState="Mapped" program="par" locator="PAR_CLOCK_TABLE" contextTags="FPGA_ONLY" type="ClocksData" file="implementation\system_par.xrpt" label="Clock Report" />
|
||||
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY,EDK_OFF" hidden="true" type="Timing_Analyzer" file="implementation\system.twx" label="Static Timing" />
|
||||
<view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="implementation\system_html/fit/report.htm" label="CPLD Fitter Report" />
|
||||
<view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="implementation\system_html/tim/report.htm" label="CPLD Timing Report" />
|
||||
</viewgroup>
|
||||
<viewgroup label="XPS Errors and Warnings" >
|
||||
<view program="platgen" WrapMessages="true" contextTags="EDK_ON" hidden="false" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/platgen.xmsgs" label="Platgen Messages" />
|
||||
<view program="libgen" WrapMessages="true" contextTags="EDK_ON" hidden="false" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/libgen.xmsgs" label="Libgen Messages" />
|
||||
<view program="simgen" WrapMessages="true" contextTags="EDK_ON" hidden="false" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/simgen.xmsgs" label="Simgen Messages" />
|
||||
<view program="bitinit" WrapMessages="true" contextTags="EDK_ON" hidden="false" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/bitinit.xmsgs" label="BitInit Messages" />
|
||||
</viewgroup>
|
||||
<viewgroup label="XPS Reports" >
|
||||
<view inputState="PreSynthesized" program="platgen" contextTags="EDK_ON" hidden="false" type="Secondary_Report" file="platgen.log" label="Platgen Log File" />
|
||||
<view inputState="PreSynthesized" program="libgen" contextTags="EDK_ON" hidden="false" type="Secondary_Report" file="libgen.log" label="Libgen Log File" />
|
||||
<view inputState="PreSynthesized" program="simgen" contextTags="EDK_ON" hidden="false" type="Secondary_Report" file="simgen.log" label="Simgen Log File" />
|
||||
<view inputState="PreSynthesized" program="bitinit" contextTags="EDK_ON" hidden="false" type="Secondary_Report" file="bitinit.log" label="BitInit Log File" />
|
||||
<view inputState="PreSynthesized" program="system" contextTags="EDK_ON" hidden="false" type="Secondary_Report" file="system.log" label="System Log File" />
|
||||
</viewgroup>
|
||||
<viewgroup label="Errors and Warnings" >
|
||||
<view program="pn" WrapMessages="true" contextTags="EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered, New" file="implementation\_xmsgs/pn_parser.xmsgs" label="Parser Messages" />
|
||||
<view program="xst" WrapMessages="true" contextTags="XST_ONLY,EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="synthesis\_xmsgs/xst.xmsgs" label="Synthesis Messages" />
|
||||
<view inputState="Synthesized" program="ngdbuild" WrapMessages="true" type="MessageList" hideColumns="Filtered" file="implementation\_xmsgs/ngdbuild.xmsgs" label="Translation Messages" />
|
||||
<view inputState="Translated" program="map" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="implementation\_xmsgs/map.xmsgs" label="Map Messages" />
|
||||
<view inputState="Mapped" program="par" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="implementation\_xmsgs/par.xmsgs" label="Place and Route Messages" />
|
||||
<view inputState="Routed" program="trce" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="implementation\_xmsgs/trce.xmsgs" label="Timing Messages" />
|
||||
<view inputState="Routed" program="xpwr" WrapMessages="true" contextTags="EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="implementation\_xmsgs/xpwr.xmsgs" label="Power Messages" />
|
||||
<view inputState="Routed" program="bitgen" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="implementation\_xmsgs/bitgen.xmsgs" label="Bitgen Messages" />
|
||||
<view inputState="Translated" program="cpldfit" WrapMessages="true" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="implementation\_xmsgs/cpldfit.xmsgs" label="Fitter Messages" />
|
||||
<view inputState="Current" program="implementation" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/map.xmsgs,_xmsgs/par.xmsgs,_xmsgs/trce.xmsgs,_xmsgs/xpwr.xmsgs,_xmsgs/bitgen.xmsgs" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="implementation\_xmsgs/*.xmsgs" label="All Implementation Messages" />
|
||||
<view inputState="Current" program="fitting" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/cpldfit.xmsgs,_xmsgs/xpwr.xmsgs" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="CPLD_MessageList" hideColumns="Filtered" file="implementation\_xmsgs/*.xmsgs" label="All Implementation Messages (CPLD)" />
|
||||
</viewgroup>
|
||||
<viewgroup label="Detailed Reports" >
|
||||
<view program="xst" contextTags="XST_ONLY,EDK_OFF" hidden="true" type="Report" file="implementation\system.syr" label="Synthesis Report" >
|
||||
<toc-item title="Top of Report" target="Copyright " searchDir="Forward" />
|
||||
<toc-item title="Synthesis Options Summary" target=" Synthesis Options Summary " />
|
||||
<toc-item title="HDL Compilation" target=" HDL Compilation " />
|
||||
<toc-item title="Design Hierarchy Analysis" target=" Design Hierarchy Analysis " />
|
||||
<toc-item title="HDL Analysis" target=" HDL Analysis " />
|
||||
<toc-item title="HDL Parsing" target=" HDL Parsing " />
|
||||
<toc-item title="HDL Elaboration" target=" HDL Elaboration " />
|
||||
<toc-item title="HDL Synthesis" target=" HDL Synthesis " />
|
||||
<toc-item title="HDL Synthesis Report" target="HDL Synthesis Report" searchCnt="2" searchDir="Backward" subItemLevel="1" />
|
||||
<toc-item title="Advanced HDL Synthesis" target=" Advanced HDL Synthesis " searchDir="Backward" />
|
||||
<toc-item title="Advanced HDL Synthesis Report" target="Advanced HDL Synthesis Report" subItemLevel="1" />
|
||||
<toc-item title="Low Level Synthesis" target=" Low Level Synthesis " />
|
||||
<toc-item title="Partition Report" target=" Partition Report " />
|
||||
<toc-item title="Final Report" target=" Final Report " />
|
||||
<toc-item title="Design Summary" target=" Design Summary " />
|
||||
<toc-item title="Primitive and Black Box Usage" target="Primitive and Black Box Usage:" subItemLevel="1" />
|
||||
<toc-item title="Device Utilization Summary" target="Device utilization summary:" subItemLevel="1" />
|
||||
<toc-item title="Partition Resource Summary" target="Partition Resource Summary:" subItemLevel="1" />
|
||||
<toc-item title="Timing Report" target="Timing Report" subItemLevel="1" />
|
||||
<toc-item title="Clock Information" target="Clock Information" subItemLevel="2" />
|
||||
<toc-item title="Asynchronous Control Signals Information" target="Asynchronous Control Signals Information" subItemLevel="2" />
|
||||
<toc-item title="Timing Summary" target="Timing Summary" subItemLevel="2" />
|
||||
<toc-item title="Timing Details" target="Timing Details" subItemLevel="2" />
|
||||
<toc-item title="Cross Clock Domains Report" target="Cross Clock Domains Report:" subItemLevel="2" />
|
||||
</view>
|
||||
<view program="synplify" contextTags="SYNPLIFY_ONLY,EDK_OFF" hidden="true" type="Report" file="implementation\system.srr" label="Synplify Report" />
|
||||
<view program="precision" contextTags="PRECISION_ONLY,EDK_OFF" hidden="true" type="Report" file="implementation\system.prec_log" label="Precision Report" />
|
||||
<view inputState="Synthesized" program="ngdbuild" type="Report" file="implementation\system.bld" label="Translation Report" >
|
||||
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
|
||||
<toc-item title="Command Line" target="Command Line:" />
|
||||
<toc-item title="Partition Status" target="Partition Implementation Status" />
|
||||
<toc-item title="Final Summary" target="NGDBUILD Design Results Summary:" />
|
||||
</view>
|
||||
<view inputState="Translated" program="map" contextTags="FPGA_ONLY" type="Report" file="implementation\system_map.mrp" label="Map Report" >
|
||||
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
|
||||
<toc-item title="Section 1: Errors" target="Section 1 -" searchDir="Backward" />
|
||||
<toc-item title="Section 2: Warnings" target="Section 2 -" searchDir="Backward" />
|
||||
<toc-item title="Section 3: Infos" target="Section 3 -" searchDir="Backward" />
|
||||
<toc-item title="Section 4: Removed Logic Summary" target="Section 4 -" searchDir="Backward" />
|
||||
<toc-item title="Section 5: Removed Logic" target="Section 5 -" searchDir="Backward" />
|
||||
<toc-item title="Section 6: IOB Properties" target="Section 6 -" searchDir="Backward" />
|
||||
<toc-item title="Section 7: RPMs" target="Section 7 -" searchDir="Backward" />
|
||||
<toc-item title="Section 8: Guide Report" target="Section 8 -" searchDir="Backward" />
|
||||
<toc-item title="Section 9: Area Group and Partition Summary" target="Section 9 -" searchDir="Backward" />
|
||||
<toc-item title="Section 10: Timing Report" target="Section 10 -" searchDir="Backward" />
|
||||
<toc-item title="Section 11: Configuration String Details" target="Section 11 -" searchDir="Backward" />
|
||||
<toc-item title="Section 12: Control Set Information" target="Section 12 -" searchDir="Backward" />
|
||||
<toc-item title="Section 13: Utilization by Hierarchy" target="Section 13 -" searchDir="Backward" />
|
||||
</view>
|
||||
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" type="Report" file="implementation\system.par" label="Place and Route Report" >
|
||||
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
|
||||
<toc-item title="Device Utilization" target="Device Utilization Summary:" />
|
||||
<toc-item title="Router Information" target="Starting Router" />
|
||||
<toc-item title="Partition Status" target="Partition Implementation Status" />
|
||||
<toc-item title="Clock Report" target="Generating Clock Report" />
|
||||
<toc-item title="Timing Results" target="Timing Score:" />
|
||||
<toc-item title="Final Summary" target="Peak Memory Usage:" />
|
||||
</view>
|
||||
<view inputState="Routed" program="trce" contextTags="FPGA_ONLY" type="Report" file="implementation\system.twr" label="Post-PAR Static Timing Report" >
|
||||
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
|
||||
<toc-item title="Timing Report Description" target="Device,package,speed:" />
|
||||
<toc-item title="Informational Messages" target="INFO:" />
|
||||
<toc-item title="Warning Messages" target="WARNING:" />
|
||||
<toc-item title="Timing Constraints" target="Timing constraint:" />
|
||||
<toc-item title="Derived Constraint Report" target="Derived Constraint Report" />
|
||||
<toc-item title="Data Sheet Report" target="Data Sheet report:" />
|
||||
<toc-item title="Timing Summary" target="Timing summary:" />
|
||||
<toc-item title="Trace Settings" target="Trace Settings:" />
|
||||
</view>
|
||||
<view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="implementation\system.rpt" label="CPLD Fitter Report (Text)" >
|
||||
<toc-item title="Top of Report" target="cpldfit:" searchDir="Forward" />
|
||||
<toc-item title="Resources Summary" target="** Mapped Resource Summary **" />
|
||||
<toc-item title="Pin Resources" target="** Pin Resources **" />
|
||||
<toc-item title="Global Resources" target="** Global Control Resources **" />
|
||||
</view>
|
||||
<view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="implementation\system.tim" label="CPLD Timing Report (Text)" >
|
||||
<toc-item title="Top of Report" target="Performance Summary Report" searchDir="Forward" />
|
||||
<toc-item title="Performance Summary" target="Performance Summary:" />
|
||||
</view>
|
||||
<view inputState="Routed" program="xpwr" contextTags="EDK_OFF" hidden="true" type="Report" file="implementation\system.pwr" label="Power Report" >
|
||||
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
|
||||
<toc-item title="Power summary" target="Power summary" />
|
||||
<toc-item title="Thermal summary" target="Thermal summary" />
|
||||
</view>
|
||||
<view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" type="Report" file="implementation\system.bgn" label="Bitgen Report" >
|
||||
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
|
||||
<toc-item title="Bitgen Options" target="Summary of Bitgen Options:" />
|
||||
<toc-item title="Final Summary" target="DRC detected" />
|
||||
</view>
|
||||
</viewgroup>
|
||||
<viewgroup label="Secondary Reports" >
|
||||
<view inputState="PreSynthesized" program="isim" hidden="if_missing" type="Secondary_Report" file="implementation\isim.log" label="ISIM Simulator Log" />
|
||||
<view inputState="Synthesized" program="netgen" hidden="if_missing" type="Secondary_Report" file="implementation\netgen/synthesis/system_synthesis.nlf" label="Post-Synthesis Simulation Model Report" >
|
||||
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
|
||||
</view>
|
||||
<view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="implementation\netgen/translate/system_translate.nlf" label="Post-Translate Simulation Model Report" >
|
||||
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
|
||||
</view>
|
||||
<view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="implementation\system_tran_fecn.nlf" label="Post-Translate Formality Netlist Report" />
|
||||
<view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="implementation\system_map.map" label="Map Log File" >
|
||||
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
|
||||
<toc-item title="Design Information" target="Design Information" />
|
||||
<toc-item title="Design Summary" target="Design Summary" />
|
||||
</view>
|
||||
<view inputState="Routed" program="smartxplorer" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="implementation\smartxplorer_results/smartxplorer.txt" label="SmartXplorer Report" />
|
||||
<view inputState="Mapped" program="trce" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="implementation\system_preroute.twr" label="Post-Map Static Timing Report" >
|
||||
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
|
||||
<toc-item title="Timing Report Description" target="Device,package,speed:" />
|
||||
<toc-item title="Informational Messages" target="INFO:" />
|
||||
<toc-item title="Warning Messages" target="WARNING:" />
|
||||
<toc-item title="Timing Constraints" target="Timing constraint:" />
|
||||
<toc-item title="Derived Constraint Report" target="Derived Constraint Report" />
|
||||
<toc-item title="Data Sheet Report" target="Data Sheet report:" />
|
||||
<toc-item title="Timing Summary" target="Timing summary:" />
|
||||
<toc-item title="Trace Settings" target="Trace Settings:" />
|
||||
</view>
|
||||
<view inputState="Mapped" program="netgen" hidden="if_missing" type="Secondary_Report" file="implementation\netgen/map/system_map.nlf" label="Post-Map Simulation Model Report" />
|
||||
<view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="implementation\system_map.psr" label="Physical Synthesis Report" >
|
||||
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
|
||||
</view>
|
||||
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Pad_Report" file="implementation\system_pad.txt" label="Pad Report" >
|
||||
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
|
||||
</view>
|
||||
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="implementation\system.unroutes" label="Unroutes Report" >
|
||||
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
|
||||
</view>
|
||||
<view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="implementation\system_preroute.tsi" label="Post-Map Constraints Interaction Report" >
|
||||
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
|
||||
</view>
|
||||
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="implementation\system.grf" label="Guide Results Report" />
|
||||
<view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="implementation\system.dly" label="Asynchronous Delay Report" />
|
||||
<view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="implementation\system.clk_rgn" label="Clock Region Report" />
|
||||
<view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="implementation\system.tsi" label="Post-Place and Route Constraints Interaction Report" >
|
||||
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
|
||||
</view>
|
||||
<view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="implementation\system_par_fecn.nlf" label="Post-Place and Route Formality Netlist Report" />
|
||||
<view inputState="Routed" program="netgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="implementation\netgen/par/system_timesim.nlf" label="Post-Place and Route Simulation Model Report" />
|
||||
<view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="implementation\system_sta.nlf" label="Primetime Netlist Report" >
|
||||
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
|
||||
</view>
|
||||
<view inputState="Routed" program="ibiswriter" hidden="if_missing" type="Secondary_Report" file="implementation\system.ibs" label="IBIS Model" >
|
||||
<toc-item title="Top of Report" target="IBIS Models for" searchDir="Forward" />
|
||||
<toc-item title="Component" target="Component " />
|
||||
</view>
|
||||
<view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="implementation\system.lck" label="Back-annotate Pin Report" >
|
||||
<toc-item title="Top of Report" target="pin2ucf Report File" searchDir="Forward" />
|
||||
<toc-item title="Constraint Conflicts Information" target="Constraint Conflicts Information" />
|
||||
</view>
|
||||
<view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="implementation\system.lpc" label="Locked Pin Constraints" >
|
||||
<toc-item title="Top of Report" target="top.lpc" searchDir="Forward" />
|
||||
<toc-item title="Newly Added Constraints" target="The following constraints were newly added" />
|
||||
</view>
|
||||
<view inputState="Translated" program="netgen" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Secondary_Report" file="implementation\netgen/fit/system_timesim.nlf" label="Post-Fit Simulation Model Report" />
|
||||
<view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="HTML" file="implementation\usage_statistics_webtalk.html" label="WebTalk Report" />
|
||||
<view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="implementation\webtalk.log" label="WebTalk Log File" />
|
||||
</viewgroup>
|
||||
</body>
|
||||
</report-views>
|
||||
|
|
@ -0,0 +1,3 @@
|
|||
MessageCaptureEnabled: TRUE
|
||||
MessageFilteringEnabled: FALSE
|
||||
IncrementalMessagingEnabled: TRUE
|
||||
Loading…
Add table
Add a link
Reference in a new issue