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MSP430:

Browse source 
Add additional NOPs as required by hardware manual.

Microblaze:
Previously a task inherited the exception enable state from the context from which xTaskCreate() was called.  Now tasks all have exceptions enabled if they are enabled in the hardware.

Windows/GCC:
Improve the implementation of portGET_HIGHEST_PRIORITY.

Common code:
Simplify the pointer use in xQueueGenericCreate()

Demo apps: 
Remove jpg images that were used to create web pages.
Fix capitalisation issues in some demos where some header files are incldued with the wrong case, preventing building on Linux.
Remove the Microblaze demos that are using obsolete tools.
Update main_blinky for the Windows port demo to include a software timer example.
This commit is contained in:
Richard Barry 2015-07-26 16:41:12 +00:00
parent 95b73d40d9
commit d3e053568d
157 changed files with 157 additions and 65765 deletions
Download patch file Download diff file Expand all files Collapse all files

2
FreeRTOS/Source/portable/CCS/MSP430X/portext.asm
View file

@ -89,7 +89,9 @@ portRESTORE_CONTEXT .macro
pop_x r15
mov.w r15, &usCriticalNesting
popm_x #12, r15
nop
pop.w sr
nop
ret_x
.endm
;-----------------------------------------------------------

14
FreeRTOS/Source/portable/GCC/MicroBlazeV8/port.c
View file

@ -89,8 +89,10 @@ the scheduler being commenced interrupts should not be enabled, so the critical
nesting variable is initialised to a non-zero value. */
#define portINITIAL_NESTING_VALUE ( 0xff )
/* The bit within the MSR register that enabled/disables interrupts. */
/* The bit within the MSR register that enabled/disables interrupts and
exceptions respectively. */
#define portMSR_IE ( 0x02U )
#define portMSR_EE ( 0x100U )
/* If the floating point unit is included in the MicroBlaze build, then the
FSR register is saved as part of the task context. portINITIAL_FSR is the value
@ -159,7 +161,7 @@ const uint32_t ulR13 = ( uint32_t ) &_SDA_BASE_;
*pxTopOfStack = ( StackType_t ) 0x00000000;
pxTopOfStack--;
#if XPAR_MICROBLAZE_0_USE_FPU != 0
#if( XPAR_MICROBLAZE_USE_FPU != 0 )
/* The FSR value placed in the initial task context is just 0. */
*pxTopOfStack = portINITIAL_FSR;
pxTopOfStack--;
@ -169,6 +171,14 @@ const uint32_t ulR13 = ( uint32_t ) &_SDA_BASE_;
disabled. Each task will enable interrupts automatically when it enters
the running state for the first time. */
*pxTopOfStack = mfmsr() & ~portMSR_IE;
#if( MICROBLAZE_EXCEPTIONS_ENABLED == 1 )
{
/* Ensure exceptions are enabled for the task. */
*pxTopOfStack |= portMSR_EE;
}
#endif
pxTopOfStack--;
/* First stack an initial value for the critical section nesting. This

44
FreeRTOS/Source/portable/GCC/MicroBlazeV8/port_exceptions.c
View file

@ -200,7 +200,7 @@ extern void *pxCurrentTCB;
exception. */
xRegisterDump.ulPC = xRegisterDump.ulR17_return_address_from_exceptions - portexINSTRUCTION_SIZE;
#if XPAR_MICROBLAZE_0_USE_FPU != 0
#if( XPAR_MICROBLAZE_USE_FPU != 0 )
{
xRegisterDump.ulFSR = mffsr();
}
@ -243,13 +243,13 @@ extern void *pxCurrentTCB;
xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_STACK_VIOLATION or XEXC_ID_MMU";
break;
#if XPAR_MICROBLAZE_0_USE_FPU != 0
#if( XPAR_MICROBLAZE_USE_FPU != 0 )
case XEXC_ID_FPU :
xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_FPU see ulFSR value";
break;
#endif /* XPAR_MICROBLAZE_0_USE_FPU */
#endif /* XPAR_MICROBLAZE_USE_FPU */
}
/* vApplicationExceptionRegisterDump() is a callback function that the
@ -275,41 +275,43 @@ static uint32_t ulHandlersAlreadyInstalled = pdFALSE;
{
ulHandlersAlreadyInstalled = pdTRUE;
#if XPAR_MICROBLAZE_0_UNALIGNED_EXCEPTIONS == 1
#if XPAR_MICROBLAZE_UNALIGNED_EXCEPTIONS == 1
microblaze_register_exception_handler( XEXC_ID_UNALIGNED_ACCESS, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_UNALIGNED_ACCESS );
#endif /* XPAR_MICROBLAZE_0_UNALIGNED_EXCEPTIONS*/
#endif /* XPAR_MICROBLAZE_UNALIGNED_EXCEPTIONS*/
#if XPAR_MICROBLAZE_0_ILL_OPCODE_EXCEPTION == 1
#if XPAR_MICROBLAZE_ILL_OPCODE_EXCEPTION == 1
microblaze_register_exception_handler( XEXC_ID_ILLEGAL_OPCODE, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_ILLEGAL_OPCODE );
#endif /* XPAR_MICROBLAZE_0_ILL_OPCODE_EXCEPTION*/
#endif /* XPAR_MICROBLAZE_ILL_OPCODE_EXCEPTION */
#if XPAR_MICROBLAZE_0_M_AXI_I_BUS_EXCEPTION == 1
#if XPAR_MICROBLAZE_M_AXI_I_BUS_EXCEPTION == 1
microblaze_register_exception_handler( XEXC_ID_M_AXI_I_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_M_AXI_I_EXCEPTION );
#endif /* XPAR_MICROBLAZE_0_M_AXI_I_BUS_EXCEPTION*/
#endif /* XPAR_MICROBLAZE_M_AXI_I_BUS_EXCEPTION */
#if XPAR_MICROBLAZE_0_M_AXI_D_BUS_EXCEPTION == 1
#if XPAR_MICROBLAZE_M_AXI_D_BUS_EXCEPTION == 1
microblaze_register_exception_handler( XEXC_ID_M_AXI_D_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_M_AXI_D_EXCEPTION );
#endif /* XPAR_MICROBLAZE_0_M_AXI_D_BUS_EXCEPTION*/
#endif /* XPAR_MICROBLAZE_M_AXI_D_BUS_EXCEPTION */
#if XPAR_MICROBLAZE_0_IPLB_BUS_EXCEPTION == 1
#if XPAR_MICROBLAZE_IPLB_BUS_EXCEPTION == 1
microblaze_register_exception_handler( XEXC_ID_IPLB_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_IPLB_EXCEPTION );
#endif /* XPAR_MICROBLAZE_0_IPLB_BUS_EXCEPTION*/
#endif /* XPAR_MICROBLAZE_IPLB_BUS_EXCEPTION */
#if XPAR_MICROBLAZE_0_DPLB_BUS_EXCEPTION == 1
#if XPAR_MICROBLAZE_DPLB_BUS_EXCEPTION == 1
microblaze_register_exception_handler( XEXC_ID_DPLB_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_DPLB_EXCEPTION );
#endif /* XPAR_MICROBLAZE_0_DPLB_BUS_EXCEPTION*/
#endif /* XPAR_MICROBLAZE_DPLB_BUS_EXCEPTION */
#if XPAR_MICROBLAZE_0_DIV_ZERO_EXCEPTION == 1
#if XPAR_MICROBLAZE_DIV_ZERO_EXCEPTION == 1
microblaze_register_exception_handler( XEXC_ID_DIV_BY_ZERO, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_DIV_BY_ZERO );
#endif /* XPAR_MICROBLAZE_0_DIV_ZERO_EXCEPTION*/
#endif /* XPAR_MICROBLAZE_DIV_ZERO_EXCEPTION */
#if XPAR_MICROBLAZE_0_FPU_EXCEPTION == 1
#if XPAR_MICROBLAZE_FPU_EXCEPTION == 1
microblaze_register_exception_handler( XEXC_ID_FPU, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_FPU );
#endif /* XPAR_MICROBLAZE_0_FPU_EXCEPTION*/
#endif /* XPAR_MICROBLAZE_FPU_EXCEPTION */
#if XPAR_MICROBLAZE_0_FSL_EXCEPTION == 1
#if XPAR_MICROBLAZE_FSL_EXCEPTION == 1
microblaze_register_exception_handler( XEXC_ID_FSL, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_FSL );
#endif /* XPAR_MICROBLAZE_0_FSL_EXCEPTION*/
#endif /* XPAR_MICROBLAZE_FSL_EXCEPTION */
microblaze_enable_exceptions();
}
}

6
FreeRTOS/Source/portable/GCC/MicroBlazeV8/portasm.S
View file

@ -76,7 +76,7 @@
/* The context is oversized to allow functions called from the ISR to write
back into the caller stack. */
#if XPAR_MICROBLAZE_0_USE_FPU != 0
#if( XPAR_MICROBLAZE_USE_FPU != 0 )
#define portCONTEXT_SIZE 136
#define portMINUS_CONTEXT_SIZE -136
#else
@ -179,7 +179,7 @@ back into the caller stack. */
mfs r18, rmsr
swi r18, r1, portMSR_OFFSET
#if XPAR_MICROBLAZE_0_USE_FPU != 0
#if( XPAR_MICROBLAZE_USE_FPU != 0 )
/* Stack FSR. */
mfs r18, rfsr
swi r18, r1, portFSR_OFFSET
@ -232,7 +232,7 @@ back into the caller stack. */
lwi r18, r1, portMSR_OFFSET
mts rmsr, r18
#if XPAR_MICROBLAZE_0_USE_FPU != 0
#if( XPAR_MICROBLAZE_USE_FPU != 0 )
/* Reload the FSR from the stack. */
lwi r18, r1, portFSR_OFFSET
mts rfsr, r18

2
FreeRTOS/Source/portable/GCC/MicroBlazeV8/portmacro.h
View file

@ -156,7 +156,7 @@ context, if the flag is not false. This is done to prevent multiple calls to
vTaskSwitchContext() being made from a single interrupt, as a single interrupt
can result in multiple peripherals being serviced. */
extern volatile uint32_t ulTaskSwitchRequested;
#define portYIELD_FROM_ISR( x ) if( x != pdFALSE ) ulTaskSwitchRequested = 1
#define portYIELD_FROM_ISR( x ) if( ( x ) != pdFALSE ) ulTaskSwitchRequested = 1
#if( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )

8
FreeRTOS/Source/portable/MSVC-MingW/portmacro.h
View file

@ -152,11 +152,9 @@ void vPortExitCritical( void );
/*-----------------------------------------------------------*/
#ifdef __GNUC__
#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) \
__asm volatile( "mov %0, %%eax \n\t" \
"bsr %%eax, %%eax \n\t" \
"mov %%eax, %1 \n\t" \
:"=r"(uxTopPriority) : "r"(uxReadyPriorities) : "eax" )
#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) \
__asm volatile( "bsr %1, %0\n\t" \
:"=r"(uxTopPriority) : "rm"(uxReadyPriorities) : "cc" )
#else
/* BitScanReverse returns the bit position of the most significant '1'
in the word. */