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Demo project only: Cyclone V SoC now running from external RAM.

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This commit is contained in:
Richard Barry 2014-10-01 09:30:35 +00:00
parent e2f2cfa816
commit d269f2027a
2 changed files with 14 additions and 2 deletions
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2
FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/.cproject
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@ -41,7 +41,7 @@
</tool>
<tool id="cdt.managedbuild.tool.gnu.cross.c.linker.451869963" name="Cross GCC Linker" superClass="cdt.managedbuild.tool.gnu.cross.c.linker">
<option id="gnu.c.link.option.other.1746198439" name="Other options (-Xlinker [option])" superClass="gnu.c.link.option.other" valueType="stringList">
<listOptionValue builtIn="false" value="-TcycloneV-dk-oc-ram.ld"/>
<listOptionValue builtIn="false" value="-TcycloneV-dk-ram.ld"/>
<listOptionValue builtIn="false" value="--defsym=__cs3_isr_irq=FreeRTOS_IRQ_Handler"/>
<listOptionValue builtIn="false" value="--defsym=__cs3_isr_swi=FreeRTOS_SWI_Handler"/>
<listOptionValue builtIn="false" value="-Map=RTOSDemo.map"/>

14
FreeRTOS/Demo/CORTEX_A9_Cyclone_V_SoC_DK/main.c
View file

@ -29,9 +29,21 @@ int main( void )
static void prvSetupHardware( void )
{
extern uint8_t __cs3_interrupt_vector;
uint32_t ulSCTLR, ulVectorTable = ( uint32_t ) &__cs3_interrupt_vector;
const uint32_t ulVBit = 13U;
alt_int_global_init();
/* Clear SCTLR.V for low vectors and map the vector table to the beginning
of the code. */
__asm( "MRC p15, 0, %0, c1, c0, 0" : "=r" ( ulSCTLR ) );
ulSCTLR &= ~( 1 << ulVBit );
__asm( "MCR p15, 0, %0, c1, c0, 0" : : "r" ( ulSCTLR ) );
__asm( "MCR p15, 0, %0, c12, c0, 0" : : "r" ( ulVectorTable ) );
cache_init();
//_RB_mmu_init();
mmu_init();
}
/*-----------------------------------------------------------*/