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Adding GIC v2 interrupt group handling to GCC_AARCH64 port.

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sean 2024-09-03 22:25:45 -05:00
parent 4a3c9204ff
commit d1605b581b
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GPG key ID: 57BD8DD03FBC5838
3 changed files with 64 additions and 17 deletions
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3
portable/GCC/ARM_AARCH64/port.c
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@ -170,6 +170,9 @@ __attribute__( ( used ) ) const uint64_t ullICCEOIR = portICCEOIR_END_OF_INTERRU
__attribute__( ( used ) ) const uint64_t ullICCIAR = portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS; __attribute__( ( used ) ) const uint64_t ullICCIAR = portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS;
__attribute__( ( used ) ) const uint64_t ullICCPMR = portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS; __attribute__( ( used ) ) const uint64_t ullICCPMR = portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS;
__attribute__( ( used ) ) const uint64_t ullMaxAPIPriorityMask = ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ); __attribute__( ( used ) ) const uint64_t ullMaxAPIPriorityMask = ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
__attribute__( ( used ) ) const uint64_t ullICCHPPIR = portICCHPPIR_HIGHEST_PRIORITY_INTERRUPT_REGISTER_ADDRESS;
__attribute__( ( used ) ) const uint64_t ullICCAIAR = portICCAIAR_ALIASED_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS;
__attribute__( ( used ) ) const uint64_t ullICCAEOIR = portICCAEOIR_ALIASED_END_OF_INTERRUPT_REGISTER_ADDRESS;
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/

57
portable/GCC/ARM_AARCH64/portASM.S
View file

@ -307,13 +307,34 @@ FreeRTOS_IRQ_Handler:
/* Maintain the interrupt nesting information across the function call. */ /* Maintain the interrupt nesting information across the function call. */
STP X1, X5, [SP, #-0x10]! STP X1, X5, [SP, #-0x10]!
/* Read value from the interrupt acknowledge register, which is stored in W0 /* Read value from the HPPI register
for future parameter and interrupt clearing use. */ * In GIC v2, the HPPI register will contain:
LDR X2, ullICCIARConst * - 0x3FF on GIC ack or spurious IRQ
LDR X3, [X2] * - 0x3FE on pending IRQ within Group 1 (IRQ, non-secure)
LDR W0, [X3] /* ICCIAR in W0 as parameter. */ * - IRQn on pending IRQ within Group 0 (FIQ, secure)
*
* X0 to contain IRQn
* X1 to contain IRQn Group number
*/
LDR X2, ullICCHPPIRConst
LDR X2, [X2]
LDR W3, [X2]
CMP W3, #0x3FE
B.NE 1f
/* if IRQn Group 1, AIAR contains IRQn */
2: LDR X2, ullICCAIARConst
MOV X1, #1
B 0f
/* if IRQn Group 0, IAR contains IRQn */
1: LDR X2, ullICCIARConst
MOV X1, #0
/* Maintain the ICCIAR value across the function call. */ 0: LDR W2, [X2]
LDR W0, [X2]
/* Maintain the IRQn value across the function call. */
STP X0, X1, [SP, #-0x10]! STP X0, X1, [SP, #-0x10]!
/* Call the C handler. */ /* Call the C handler. */
@ -324,12 +345,25 @@ FreeRTOS_IRQ_Handler:
DSB SY DSB SY
ISB SY ISB SY
/* Restore the ICCIAR value. */ /* Restore the IRqn value. */
LDP X0, X1, [SP], #0x10 LDP X0, X1, [SP], #0x10
/* End IRQ processing by writing ICCIAR to the EOI register. */ /* End IRQ processing by writing to the EOI register.
LDR X4, ullICCEOIRConst * In GIV v2, the EOI register to be used depends on the interrupt group:
LDR X4, [X4] * - IRQn Group 0 -> EOI
* - IRQn Group 1 -> AEOI
*/
CMP X1, #1
B.NE 1f
/* if IRQn Group 1, use AEOIR */
2: LDR X4, ullICCAEOIRConst
B 0f
/* if IRQn Group 0, use EOIR */
1: LDR X4, ullICCEOIRConst
0: LDR W4, [X4]
STR W0, [X4] STR W0, [X4]
/* Restore the critical nesting count. */ /* Restore the critical nesting count. */
@ -420,6 +454,9 @@ ullPortInterruptNestingConst: .dword ullPortInterruptNesting
ullPortYieldRequiredConst: .dword ullPortYieldRequired ullPortYieldRequiredConst: .dword ullPortYieldRequired
ullICCIARConst: .dword ullICCIAR ullICCIARConst: .dword ullICCIAR
ullICCEOIRConst: .dword ullICCEOIR ullICCEOIRConst: .dword ullICCEOIR
ullICCHPPIRConst: .dword ullICCHPPIR
ullICCAIARConst: .dword ullICCAIAR
ullICCAEOIRConst: .dword ullICCAEOIR
vApplicationIRQHandlerConst: .word vApplicationIRQHandler vApplicationIRQHandlerConst: .word vApplicationIRQHandler

21
portable/GCC/ARM_AARCH64/portmacro.h
View file

@ -204,14 +204,21 @@ void FreeRTOS_Tick_Handler( void );
#define portICCEOIR_END_OF_INTERRUPT_OFFSET ( 0x10 ) #define portICCEOIR_END_OF_INTERRUPT_OFFSET ( 0x10 )
#define portICCBPR_BINARY_POINT_OFFSET ( 0x08 ) #define portICCBPR_BINARY_POINT_OFFSET ( 0x08 )
#define portICCRPR_RUNNING_PRIORITY_OFFSET ( 0x14 ) #define portICCRPR_RUNNING_PRIORITY_OFFSET ( 0x14 )
#define portICCHPPIR_HIGHEST_PRIORITY_INTERRUPT_OFFSET ( 0x18 )
#define portICCAIAR_ALIASED_INTERRUPT_ACKNOWLEDGE_OFFSET ( 0x20 )
#define portICCAEOIR_ALIASED_END_OF_INTERRUPT_OFFSET ( 0x24 )
#define portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET )
#define portICCPMR_PRIORITY_MASK_REGISTER ( *( ( volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET ) ) )
#define portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET )
#define portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCEOIR_END_OF_INTERRUPT_OFFSET )
#define portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET )
#define portICCBPR_BINARY_POINT_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCBPR_BINARY_POINT_OFFSET ) ) )
#define portICCRPR_RUNNING_PRIORITY_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCRPR_RUNNING_PRIORITY_OFFSET ) ) )
#define portICCHPPIR_HIGHEST_PRIORITY_INTERRUPT_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCHPPIR_HIGHEST_PRIORITY_INTERRUPT_OFFSET )
#define portICCAIAR_ALIASED_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCAIAR_ALIASED_INTERRUPT_ACKNOWLEDGE_OFFSET )
#define portICCAEOIR_ALIASED_END_OF_INTERRUPT_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCAEOIR_ALIASED_END_OF_INTERRUPT_OFFSET )
#define portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET )
#define portICCPMR_PRIORITY_MASK_REGISTER ( *( ( volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET ) ) )
#define portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET )
#define portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCEOIR_END_OF_INTERRUPT_OFFSET )
#define portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET )
#define portICCBPR_BINARY_POINT_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCBPR_BINARY_POINT_OFFSET ) ) )
#define portICCRPR_RUNNING_PRIORITY_REGISTER ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCRPR_RUNNING_PRIORITY_OFFSET ) ) )
#define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" ) #define portMEMORY_BARRIER() __asm volatile ( "" ::: "memory" )