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Implement functionality that allows the memory required to create a queue or semaphore to be allocated statically.

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Update the standard demo task that tests statically allocated tasks to also test statically allocated queues.
This commit is contained in:
Richard Barry 2016-01-19 13:41:28 +00:00
parent eae4815bf3
commit cf0ed4e2ac
10 changed files with 592 additions and 211 deletions
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5
FreeRTOS/Demo/CORTEX_M7_SAME70_Xplained_AtmelStudio/ReadMe_Instructions.url Normal file
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@ -0,0 +1,5 @@
[{000214A0-0000-0000-C000-000000000046}]
Prop3=19,2
[InternetShortcut]
URL=http://www.freertos.org/Atmel_SAMV7_Cortex-M7_RTOS_Demo.html
IDList=

13
FreeRTOS/Demo/CORTEX_M7_SAME70_Xplained_AtmelStudio/src/Full_Demo/IntQueueTimer.c
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@ -72,7 +72,10 @@
* In this case, there was difficulty generating interrupts from TC1, so only
* TC0 is used. Nested interrupts are instead generated by manually pending the
* TC1 interrupt from inside the TC0 interrupt handler. This means TC1 must be
* assigned an interrupt priority above TC0.
* assigned an interrupt priority above TC0. [Note this arrangement does not
* really fulfil the purpose of the test as the nesting always occurs at the
* same point in the code, whereas the test is designed to test nesting
* occurring within the queue API functions]
*/
/* Scheduler includes. */
@ -119,9 +122,9 @@ uint32_t ulDivider, ulTCCLKS;
NVIC_ClearPendingIRQ( TC1_IRQn );
NVIC_SetPriority( TC0_IRQn, tmrLOWER_PRIORITY );
NVIC_SetPriority( TC1_IRQn, tmrHIGHER_PRIORITY );
NVIC_EnableIRQ( TC0_IRQn );
NVIC_EnableIRQ( TC1_IRQn );
NVIC_EnableIRQ( TC0_IRQn );
NVIC_EnableIRQ( TC1_IRQn );
/* Start the timer last of all. */
tc_start( TC0, 0 );
}
@ -144,7 +147,7 @@ static uint32_t ulISRCount = 0;
/* Pend an interrupt that will nest with this interrupt. */
NVIC_SetPendingIRQ( TC1_IRQn );
}
/* Call the IntQ test function for this channel. */
portYIELD_FROM_ISR( xFirstTimerHandler() );
}