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https://github.com/FreeRTOS/FreeRTOS-Kernel.git
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Rename directories in the RISC-V port.
This commit is contained in:
Richard Barry
parent
2181c0375e
commit
ce36928ea8
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@ -61,14 +61,6 @@
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#ifndef __FREERTOS_RISC_V_EXTENSIONS_H__
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#define __FREERTOS_RISC_V_EXTENSIONS_H__
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.macro portSAVE_ADDITIONAL_REGISTERS
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/* This file is for use with chips that do not add to the standard RISC-V
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* register set, so there is nothing to do here. */
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.endm
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.macro portRESTORE_ADDITIONAL_REGISTERS
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/* This file is for use with chips that do not add to the standard RISC-V
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* register set, so there is nothing to do here. */
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.endm
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#define portasmHAS_CLINT 1
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#endif /* __FREERTOS_RISC_V_EXTENSIONS_H__ */
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@ -0,0 +1,73 @@
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/*
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* FreeRTOS Kernel V10.1.1
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* Copyright (C) 2018 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy of
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* this software and associated documentation files (the "Software"), to deal in
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* the Software without restriction, including without limitation the rights to
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* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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* the Software, and t
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o permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* http://www.FreeRTOS.org
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* http://aws.amazon.com/freertos
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*
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* 1 tab == 4 spaces!
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*/
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/*
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* The FreeRTOS kernel's RISC-V port is split between the the code that is
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* common across all currently supported RISC-V chips (implementations of the
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* RISC-V ISA), and code which tailors the port to a specific RISC-V chip:
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*
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* + The code that is common to all RISC-V chips is implemented in
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* FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S. There is only one
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* portASM.S file because the same file is used no matter which RISC-V chip is
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* in use.
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*
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* + The code that tailors the kernel's RISC-V port to a specific RISC-V
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* chip is implemented in freertos_risc_v_port_specific_extensions.h. There
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* is one freertos_risc_v_port_specific_extensions.h that can be used with any
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* RISC-V chip that both includes a standard CLINT and does not add to the
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* base set of RISC-V registers. There are additional
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* freertos_risc_v_port_specific_extensions.h files for RISC-V implementations
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* that do not include a standard CLINT or do add to the base set of RISC-V
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* regiters.
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*
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* CARE MUST BE TAKEN TO INCLDUE THE CORRECT
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* freertos_risc_v_port_specific_extensions.h HEADER FILE FOR THE CHIP
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* IN USE. To include the correct freertos_risc_v_port_specific_extensions.h
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* header file ensure the path to the correct header file is in the assembler's
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* include path.
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*
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* This freertos_risc_v_port_specific_extensions.h is for use with Pulpino Ri5cy
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* devices, developed and tested using the Vega board RV32M1RM.
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*
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*/
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#ifndef __FREERTOS_RISC_V_EXTENSIONS_H__
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#define __FREERTOS_RISC_V_EXTENSIONS_H__
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#define portasmHAS_CLINT 0
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.macro portasmSAVE_ADDITIONAL_REGISTERS
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.endm
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.macro portasmRESTORE_ADDITIONAL_REGISTERS
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/* This file is for use with chips that do not add to the standard RISC-V
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* register set, so there is nothing to do here. */
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.endm
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#endif /* __FREERTOS_RISC_V_EXTENSIONS_H__ */
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@ -206,6 +206,8 @@ const uint32_t ulMPIE_Bit = 0x80, ulMPP_Bits = 0x1800;
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}
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/*-----------------------------------------------------------*/
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#if( configCLINT_BASE_ADDRESS != 0 )
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void vPortSetupTimerInterrupt( void )
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{
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uint32_t ulCurrentTimeHigh, ulCurrentTimeLow;
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@ -227,6 +229,8 @@ volatile uint32_t * const pulTimeLow = ( volatile uint32_t * const ) ( configCLI
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/* Prepare the time to use after the next tick interrupt. */
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ullNextTime += ( uint64_t ) ulTimerIncrementsForOneTick;
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}
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#endif /* ( configCLINT_BASE_ADDRESS != 0 ) */
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/*-----------------------------------------------------------*/
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BaseType_t xPortStartScheduler( void )
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@ -247,14 +251,26 @@ extern void xPortStartFirstTask( void );
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started. */
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configASSERT( ( xISRStackTop & portBYTE_ALIGNMENT_MASK ) == 0 );
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}
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#endif
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#endif /* configASSERT_DEFINED */
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/* If there is a CLINT then it is ok to use the default implementation
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in this file, otherwise vPortSetupTimerInterrupt() must be implemented to
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configure whichever clock is to be used to generate the tick interrupt. */
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vPortSetupTimerInterrupt();
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#if( configCLINT_BASE_ADDRESS != 0 )
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{
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/* Enable mtime and external interrupts. 1<<7 for timer interrupt, 1<<11
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for external interrupt. _RB_ What happens here when mtime is not present as
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with pulpino? */
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__asm volatile( "csrs mie, %0" :: "r"(0x880) );
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}
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#else
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{
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/* Enable external interrupts. */
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__asm volatile( "csrs mie, %0" :: "r"(0x800) );
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}
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#endif /* configCLINT_BASE_ADDRESS */
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xPortStartFirstTask();
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@ -6,9 +6,7 @@
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* this software and associated documentation files (the "Software"), to deal in
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* the Software without restriction, including without limitation the rights to
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* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
|
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* the Software, and t
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o permit persons to whom the Software is furnished to do so,
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* the Software, and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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@ -59,25 +57,50 @@
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*/
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#include "freertos_risc_v_port_specific_extensions.h"
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#if __riscv_xlen == 64
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#error Not implemented yet - change lw to ld, and sw to sd.
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#define WORD_SIZE 8
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#elif __riscv_xlen == 32
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#define WORD_SIZE 4
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#else
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#error Assembler has not defined __riscv_xlen
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/* Check the freertos_risc_v_port_specific_extensions.h and/or command line
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definitions. */
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#ifndef portasmHAS_CLINT
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#error freertos_risc_v_port_specific_extensions.h must define portasmHAS_CLINT to either 1 (CLINT present) or 0 (clint not present).
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#endif
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#define CONTEXT_SIZE ( 30 * WORD_SIZE )
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#ifndef portasmHANDLE_INTERRUPT
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#error portasmHANDLE_INTERRUPT must be defined to the function to be called to handle external/peripheral interrupts. portASM_HANDLE_INTERRUPT can be defined on the assmbler command line or in the appropriate freertos_risc_v_port_specific_extensions.h header file.
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#endif
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#ifndef portasmSAVE_ADDITIONAL_REGISTERS
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/* portasmSAVE_ADDITIONAL_REGISTERS is not defined so assume no additional
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registers need to be saved. */
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#define portasmSAVE_ADDITIONAL_REGISTERS
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#endif
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#ifndef portasmRESTORE_ADDITIONAL_REGISTERS
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/* portasmRESTORE_ADDITIONAL_REGISTERS is not defined so assume no
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additional registers need to be restored. */
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#define portasmRESTORE_ADDITIONAL_REGISTERS
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#endif
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#if __riscv_xlen == 64
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#error Not implemented yet - change lw to ld, and sw to sd.
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#define portWORD_SIZE 8
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#elif __riscv_xlen == 32
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#define portWORD_SIZE 4
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#else
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#error Assembler did not define __riscv_xlen
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#endif
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/* Only the standard core registers are stored by default. Any additional
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registers must be saved by the portasmSAVE_ADDITIONAL_REGISTERS and
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portasmRESTORE_ADDITIONAL_REGISTERS macros - which can be defined in a chip
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specific version of freertos_risc_v_port_specific_extensions.h. See the notes
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at the top of this file. */
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#define portCONTEXT_SIZE ( 30 * portWORD_SIZE )
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.global xPortStartFirstTask
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.global vPortTrapHandler
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.global vFreeRTOSPortTrapHandler
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.extern pxCurrentTCB
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.extern ulPortTrapHandler
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.extern vTaskSwitchContext
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.extern Timer_IRQHandler
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.extern pullMachineTimerCompareRegister
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.extern pullNextTime
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.extern ulTimerIncrementsForOneTick
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@ -86,42 +109,42 @@
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/*-----------------------------------------------------------*/
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.align 8
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vPortTrapHandler:
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addi sp, sp, -CONTEXT_SIZE
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sw x1, 1 * WORD_SIZE( sp )
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sw x5, 2 * WORD_SIZE( sp )
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sw x6, 3 * WORD_SIZE( sp )
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sw x7, 4 * WORD_SIZE( sp )
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sw x8, 5 * WORD_SIZE( sp )
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sw x9, 6 * WORD_SIZE( sp )
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sw x10, 7 * WORD_SIZE( sp )
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sw x11, 8 * WORD_SIZE( sp )
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sw x12, 9 * WORD_SIZE( sp )
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sw x13, 10 * WORD_SIZE( sp )
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sw x14, 11 * WORD_SIZE( sp )
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sw x15, 12 * WORD_SIZE( sp )
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sw x16, 13 * WORD_SIZE( sp )
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sw x17, 14 * WORD_SIZE( sp )
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sw x18, 15 * WORD_SIZE( sp )
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sw x19, 16 * WORD_SIZE( sp )
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sw x20, 17 * WORD_SIZE( sp )
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sw x21, 18 * WORD_SIZE( sp )
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sw x22, 19 * WORD_SIZE( sp )
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sw x23, 20 * WORD_SIZE( sp )
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sw x24, 21 * WORD_SIZE( sp )
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sw x25, 22 * WORD_SIZE( sp )
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sw x26, 23 * WORD_SIZE( sp )
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sw x27, 24 * WORD_SIZE( sp )
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sw x28, 25 * WORD_SIZE( sp )
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sw x29, 26 * WORD_SIZE( sp )
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sw x30, 27 * WORD_SIZE( sp )
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sw x31, 28 * WORD_SIZE( sp )
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.align 16
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vFreeRTOSPortTrapHandler:
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addi sp, sp, -portCONTEXT_SIZE
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sw x1, 1 * portWORD_SIZE( sp )
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sw x5, 2 * portWORD_SIZE( sp )
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sw x6, 3 * portWORD_SIZE( sp )
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sw x7, 4 * portWORD_SIZE( sp )
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sw x8, 5 * portWORD_SIZE( sp )
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sw x9, 6 * portWORD_SIZE( sp )
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sw x10, 7 * portWORD_SIZE( sp )
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sw x11, 8 * portWORD_SIZE( sp )
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sw x12, 9 * portWORD_SIZE( sp )
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sw x13, 10 * portWORD_SIZE( sp )
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sw x14, 11 * portWORD_SIZE( sp )
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sw x15, 12 * portWORD_SIZE( sp )
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sw x16, 13 * portWORD_SIZE( sp )
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sw x17, 14 * portWORD_SIZE( sp )
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sw x18, 15 * portWORD_SIZE( sp )
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sw x19, 16 * portWORD_SIZE( sp )
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sw x20, 17 * portWORD_SIZE( sp )
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sw x21, 18 * portWORD_SIZE( sp )
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sw x22, 19 * portWORD_SIZE( sp )
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sw x23, 20 * portWORD_SIZE( sp )
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sw x24, 21 * portWORD_SIZE( sp )
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sw x25, 22 * portWORD_SIZE( sp )
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sw x26, 23 * portWORD_SIZE( sp )
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sw x27, 24 * portWORD_SIZE( sp )
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sw x28, 25 * portWORD_SIZE( sp )
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sw x29, 26 * portWORD_SIZE( sp )
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sw x30, 27 * portWORD_SIZE( sp )
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sw x31, 28 * portWORD_SIZE( sp )
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portSAVE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_port_specific_extensions.h to save any registers unique to the RISC-V implementation. */
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portasmSAVE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_port_specific_extensions.h to save any registers unique to the RISC-V implementation. */
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csrr t0, mstatus /* Required for MPIE bit. */
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sw t0, 29 * WORD_SIZE( sp )
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sw t0, 29 * portWORD_SIZE( sp )
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lw t0, pxCurrentTCB /* Load pxCurrentTCB. */
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sw sp, 0( t0 ) /* Write sp to first TCB member. */
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@ -135,7 +158,10 @@ test_if_asynchronous:
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sw a1, 0( sp ) /* Asynch so save unmodified exception return address. */
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handle_asynchronous:
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test_if_mtimer:
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#if( portasmHAS_CLINT != 0 )
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test_if_mtimer: /* If there is a CLINT then the mtimer is used to generate the tick interrupt. */
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lui t0, 0x80000
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addi t1, t0, 7 /* 0x80000007 == machine timer interrupt. */
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bne a0, t1, test_if_external_interrupt
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@ -158,10 +184,14 @@ test_if_mtimer:
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jal vTaskSwitchContext
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j processed_source
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test_if_external_interrupt:
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test_if_external_interrupt: /* If there is a CLINT and the mtimer interrupt is not pending then check to see if an external interrupt is pending. */
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addi t1, t1, 4 /* 0x80000007 + 4 = 0x8000000b == Machine external interrupt. */
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bne a0, t1, as_yet_unhandled /* Something as yet unhandled. */
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jal vPortHandleInterrupt
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#endif /* portasmHAS_CLINT */
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lw sp, xISRStackTop /* Switch to ISR stack before function call. */
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jal portasmHANDLE_INTERRUPT /* Jump to the interrupt handler if there is no CLINT or if there is a CLINT and it has been determined that an external interrupt is pending. */
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j processed_source
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handle_synchronous:
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@ -192,82 +222,87 @@ processed_source:
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csrw mepc, t0
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/* Load mstatus with the interrupt enable bits used by the task. */
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lw t0, 29 * WORD_SIZE( sp )
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lw t0, 29 * portWORD_SIZE( sp )
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csrw mstatus, t0 /* Required for MPIE bit. */
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portRESTORE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_port_specific_extensions.h to restore any registers unique to the RISC-V implementation. */
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portasmRESTORE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_port_specific_extensions.h to restore any registers unique to the RISC-V implementation. */
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lw x1, 1 * WORD_SIZE( sp )
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lw x5, 2 * WORD_SIZE( sp ) /* t0 */
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lw x6, 3 * WORD_SIZE( sp ) /* t1 */
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lw x7, 4 * WORD_SIZE( sp ) /* t2 */
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lw x8, 5 * WORD_SIZE( sp ) /* s0/fp */
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lw x9, 6 * WORD_SIZE( sp ) /* s1 */
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lw x10, 7 * WORD_SIZE( sp ) /* a0 */
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lw x11, 8 * WORD_SIZE( sp ) /* a1 */
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lw x12, 9 * WORD_SIZE( sp ) /* a2 */
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lw x13, 10 * WORD_SIZE( sp ) /* a3 */
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lw x14, 11 * WORD_SIZE( sp ) /* a4 */
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lw x15, 12 * WORD_SIZE( sp ) /* a5 */
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lw x16, 13 * WORD_SIZE( sp ) /* a6 */
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lw x17, 14 * WORD_SIZE( sp ) /* a7 */
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lw x18, 15 * WORD_SIZE( sp ) /* s2 */
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lw x19, 16 * WORD_SIZE( sp ) /* s3 */
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lw x20, 17 * WORD_SIZE( sp ) /* s4 */
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lw x21, 18 * WORD_SIZE( sp ) /* s5 */
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lw x22, 19 * WORD_SIZE( sp ) /* s6 */
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lw x23, 20 * WORD_SIZE( sp ) /* s7 */
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lw x24, 21 * WORD_SIZE( sp ) /* s8 */
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lw x25, 22 * WORD_SIZE( sp ) /* s9 */
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lw x26, 23 * WORD_SIZE( sp ) /* s10 */
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lw x27, 24 * WORD_SIZE( sp ) /* s11 */
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lw x28, 25 * WORD_SIZE( sp ) /* t3 */
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lw x29, 26 * WORD_SIZE( sp ) /* t4 */
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lw x30, 27 * WORD_SIZE( sp ) /* t5 */
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lw x31, 28 * WORD_SIZE( sp ) /* t6 */
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addi sp, sp, CONTEXT_SIZE
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lw x1, 1 * portWORD_SIZE( sp )
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lw x5, 2 * portWORD_SIZE( sp ) /* t0 */
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lw x6, 3 * portWORD_SIZE( sp ) /* t1 */
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lw x7, 4 * portWORD_SIZE( sp ) /* t2 */
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lw x8, 5 * portWORD_SIZE( sp ) /* s0/fp */
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lw x9, 6 * portWORD_SIZE( sp ) /* s1 */
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lw x10, 7 * portWORD_SIZE( sp ) /* a0 */
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lw x11, 8 * portWORD_SIZE( sp ) /* a1 */
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lw x12, 9 * portWORD_SIZE( sp ) /* a2 */
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lw x13, 10 * portWORD_SIZE( sp ) /* a3 */
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lw x14, 11 * portWORD_SIZE( sp ) /* a4 */
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lw x15, 12 * portWORD_SIZE( sp ) /* a5 */
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lw x16, 13 * portWORD_SIZE( sp ) /* a6 */
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lw x17, 14 * portWORD_SIZE( sp ) /* a7 */
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lw x18, 15 * portWORD_SIZE( sp ) /* s2 */
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lw x19, 16 * portWORD_SIZE( sp ) /* s3 */
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lw x20, 17 * portWORD_SIZE( sp ) /* s4 */
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lw x21, 18 * portWORD_SIZE( sp ) /* s5 */
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lw x22, 19 * portWORD_SIZE( sp ) /* s6 */
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lw x23, 20 * portWORD_SIZE( sp ) /* s7 */
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lw x24, 21 * portWORD_SIZE( sp ) /* s8 */
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lw x25, 22 * portWORD_SIZE( sp ) /* s9 */
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lw x26, 23 * portWORD_SIZE( sp ) /* s10 */
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lw x27, 24 * portWORD_SIZE( sp ) /* s11 */
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lw x28, 25 * portWORD_SIZE( sp ) /* t3 */
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lw x29, 26 * portWORD_SIZE( sp ) /* t4 */
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lw x30, 27 * portWORD_SIZE( sp ) /* t5 */
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lw x31, 28 * portWORD_SIZE( sp ) /* t6 */
|
||||
addi sp, sp, portCONTEXT_SIZE
|
||||
|
||||
mret
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
.align 8
|
||||
.align 16
|
||||
xPortStartFirstTask:
|
||||
|
||||
la t0, vPortTrapHandler
|
||||
#if( portasmHAS_CLINT != 0 )
|
||||
/* If there is a clint then interrupts can branch directly to the FreeRTOS
|
||||
trap handler. Otherwise the interrupt controller will need to be configured
|
||||
outside of this file. */
|
||||
la t0, vFreeRTOSPortTrapHandler
|
||||
csrw mtvec, t0
|
||||
#endif /* portasmHAS_CLILNT */
|
||||
|
||||
lw sp, pxCurrentTCB /* Load pxCurrentTCB. */
|
||||
lw sp, 0( sp ) /* Read sp from first TCB member. */
|
||||
|
||||
lw x1, 0( sp ) /* Note for starting the scheduler the exception return address is used as the function return address. */
|
||||
lw x5, 2 * WORD_SIZE( sp ) /* t0 */
|
||||
lw x6, 3 * WORD_SIZE( sp ) /* t1 */
|
||||
lw x7, 4 * WORD_SIZE( sp ) /* t2 */
|
||||
lw x8, 5 * WORD_SIZE( sp ) /* s0/fp */
|
||||
lw x9, 6 * WORD_SIZE( sp ) /* s1 */
|
||||
lw x10, 7 * WORD_SIZE( sp ) /* a0 */
|
||||
lw x11, 8 * WORD_SIZE( sp ) /* a1 */
|
||||
lw x12, 9 * WORD_SIZE( sp ) /* a2 */
|
||||
lw x13, 10 * WORD_SIZE( sp ) /* a3 */
|
||||
lw x14, 11 * WORD_SIZE( sp ) /* a4 */
|
||||
lw x15, 12 * WORD_SIZE( sp ) /* a5 */
|
||||
lw x16, 13 * WORD_SIZE( sp ) /* a6 */
|
||||
lw x17, 14 * WORD_SIZE( sp ) /* a7 */
|
||||
lw x18, 15 * WORD_SIZE( sp ) /* s2 */
|
||||
lw x19, 16 * WORD_SIZE( sp ) /* s3 */
|
||||
lw x20, 17 * WORD_SIZE( sp ) /* s4 */
|
||||
lw x21, 18 * WORD_SIZE( sp ) /* s5 */
|
||||
lw x22, 19 * WORD_SIZE( sp ) /* s6 */
|
||||
lw x23, 20 * WORD_SIZE( sp ) /* s7 */
|
||||
lw x24, 21 * WORD_SIZE( sp ) /* s8 */
|
||||
lw x25, 22 * WORD_SIZE( sp ) /* s9 */
|
||||
lw x26, 23 * WORD_SIZE( sp ) /* s10 */
|
||||
lw x27, 24 * WORD_SIZE( sp ) /* s11 */
|
||||
lw x28, 25 * WORD_SIZE( sp ) /* t3 */
|
||||
lw x29, 26 * WORD_SIZE( sp ) /* t4 */
|
||||
lw x30, 27 * WORD_SIZE( sp ) /* t5 */
|
||||
lw x31, 28 * WORD_SIZE( sp ) /* t6 */
|
||||
addi sp, sp, CONTEXT_SIZE
|
||||
lw x5, 2 * portWORD_SIZE( sp ) /* t0 */
|
||||
lw x6, 3 * portWORD_SIZE( sp ) /* t1 */
|
||||
lw x7, 4 * portWORD_SIZE( sp ) /* t2 */
|
||||
lw x8, 5 * portWORD_SIZE( sp ) /* s0/fp */
|
||||
lw x9, 6 * portWORD_SIZE( sp ) /* s1 */
|
||||
lw x10, 7 * portWORD_SIZE( sp ) /* a0 */
|
||||
lw x11, 8 * portWORD_SIZE( sp ) /* a1 */
|
||||
lw x12, 9 * portWORD_SIZE( sp ) /* a2 */
|
||||
lw x13, 10 * portWORD_SIZE( sp ) /* a3 */
|
||||
lw x14, 11 * portWORD_SIZE( sp ) /* a4 */
|
||||
lw x15, 12 * portWORD_SIZE( sp ) /* a5 */
|
||||
lw x16, 13 * portWORD_SIZE( sp ) /* a6 */
|
||||
lw x17, 14 * portWORD_SIZE( sp ) /* a7 */
|
||||
lw x18, 15 * portWORD_SIZE( sp ) /* s2 */
|
||||
lw x19, 16 * portWORD_SIZE( sp ) /* s3 */
|
||||
lw x20, 17 * portWORD_SIZE( sp ) /* s4 */
|
||||
lw x21, 18 * portWORD_SIZE( sp ) /* s5 */
|
||||
lw x22, 19 * portWORD_SIZE( sp ) /* s6 */
|
||||
lw x23, 20 * portWORD_SIZE( sp ) /* s7 */
|
||||
lw x24, 21 * portWORD_SIZE( sp ) /* s8 */
|
||||
lw x25, 22 * portWORD_SIZE( sp ) /* s9 */
|
||||
lw x26, 23 * portWORD_SIZE( sp ) /* s10 */
|
||||
lw x27, 24 * portWORD_SIZE( sp ) /* s11 */
|
||||
lw x28, 25 * portWORD_SIZE( sp ) /* t3 */
|
||||
lw x29, 26 * portWORD_SIZE( sp ) /* t4 */
|
||||
lw x30, 27 * portWORD_SIZE( sp ) /* t5 */
|
||||
lw x31, 28 * portWORD_SIZE( sp ) /* t6 */
|
||||
addi sp, sp, portCONTEXT_SIZE
|
||||
csrs mstatus, 8 /* Enable machine interrupts. */
|
||||
ret
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue