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Fix comment typos (#1461)

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Fix several documentation and example-code issues in the kernel header comments:

 * queue.h: remove a stray semicolon after the 'if' and correct the
   xHigherPriorityTaskWoken variable casing in the xQueueReceiveFromISR()
   example; add the missing comma between parameters in the
   xQueueGenericSend() prototype example.
 * list.h: correct the doxygen \page tag for listGET_ITEM_VALUE_OF_HEAD_ENTRY.
 * task.h: fix the uxIndexToCLear typo (-> uxIndexToClear).

These are documentation/example only changes that do not affect the
compiled library.

Signed-off-by: chenrongjun <chenrongjun@zepp.com>
This commit is contained in:
zepp-chen 2026-08-08 07:14:30 +08:00 • committed by GitHub
parent c5d22b28f2
commit ce221a8bb4
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46 changed files with 83 additions and 83 deletions
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2
portable/GCC/RISC-V/chip_specific_extensions/Pulpino_Vega_RV32M1RM/freertos_risc_v_chip_specific_extensions.h
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@ -27,7 +27,7 @@
*/
/*
* The FreeRTOS kernel's RISC-V port is split between the the code that is
* The FreeRTOS kernel's RISC-V port is split between the code that is
* common across all currently supported RISC-V chips (implementations of the
* RISC-V ISA), and code that tailors the port to a specific RISC-V chip:
*

2
portable/GCC/RISC-V/chip_specific_extensions/RISCV_MTIME_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h
View file

@ -27,7 +27,7 @@
*/
/*
* The FreeRTOS kernel's RISC-V port is split between the the code that is
* The FreeRTOS kernel's RISC-V port is split between the code that is
* common across all currently supported RISC-V chips (implementations of the
* RISC-V ISA), and code that tailors the port to a specific RISC-V chip:
*

2
portable/GCC/RISC-V/chip_specific_extensions/RISCV_no_extensions/freertos_risc_v_chip_specific_extensions.h
View file

@ -27,7 +27,7 @@
*/
/*
* The FreeRTOS kernel's RISC-V port is split between the the code that is
* The FreeRTOS kernel's RISC-V port is split between the code that is
* common across all currently supported RISC-V chips (implementations of the
* RISC-V ISA), and code that tailors the port to a specific RISC-V chip:
*

2
portable/GCC/RISC-V/chip_specific_extensions/RV32I_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h
View file

@ -27,7 +27,7 @@
*/
/*
* The FreeRTOS kernel's RISC-V port is split between the the code that is
* The FreeRTOS kernel's RISC-V port is split between the code that is
* common across all currently supported RISC-V chips (implementations of the
* RISC-V ISA), and code that tailors the port to a specific RISC-V chip:
*