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Fix comment typos (#1461)

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Fix several documentation and example-code issues in the kernel header comments:

 * queue.h: remove a stray semicolon after the 'if' and correct the
   xHigherPriorityTaskWoken variable casing in the xQueueReceiveFromISR()
   example; add the missing comma between parameters in the
   xQueueGenericSend() prototype example.
 * list.h: correct the doxygen \page tag for listGET_ITEM_VALUE_OF_HEAD_ENTRY.
 * task.h: fix the uxIndexToCLear typo (-> uxIndexToClear).

These are documentation/example only changes that do not affect the
compiled library.

Signed-off-by: chenrongjun <chenrongjun@zepp.com>
This commit is contained in:
zepp-chen 2026-08-08 07:14:30 +08:00 • committed by GitHub
parent c5d22b28f2
commit ce221a8bb4
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GPG key ID: B5690EEEBB952194
46 changed files with 83 additions and 83 deletions
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8
portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portasm.c
View file

@ -126,9 +126,9 @@
" restore_general_regs_first_task: \n"
" subs r2, #32 \n"
" ldmia r2!, {r4-r7} \n" /* r4-r7 contain half of the hardware saved context. */
" stmia r3!, {r4-r7} \n" /* Copy half of the the hardware saved context on the task stack. */
" stmia r3!, {r4-r7} \n" /* Copy half of the hardware saved context on the task stack. */
" ldmia r2!, {r4-r7} \n" /* r4-r7 contain rest half of the hardware saved context. */
" stmia r3!, {r4-r7} \n" /* Copy rest half of the the hardware saved context on the task stack. */
" stmia r3!, {r4-r7} \n" /* Copy rest half of the hardware saved context on the task stack. */
" subs r2, #48 \n"
" ldmia r2!, {r4-r7} \n" /* Restore r8-r11. */
" mov r8, r4 \n" /* r8 = r4. */
@ -402,9 +402,9 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
" restore_general_regs: \n"
" subs r2, #32 \n"
" ldmia r2!, {r4-r7} \n" /* r4-r7 contain half of the hardware saved context. */
" stmia r3!, {r4-r7} \n" /* Copy half of the the hardware saved context on the task stack. */
" stmia r3!, {r4-r7} \n" /* Copy half of the hardware saved context on the task stack. */
" ldmia r2!, {r4-r7} \n" /* r4-r7 contain rest half of the hardware saved context. */
" stmia r3!, {r4-r7} \n" /* Copy rest half of the the hardware saved context on the task stack. */
" stmia r3!, {r4-r7} \n" /* Copy rest half of the hardware saved context on the task stack. */
" subs r2, #48 \n"
" ldmia r2!, {r4-r7} \n" /* Restore r8-r11. */
" mov r8, r4 \n" /* r8 = r4. */

8
portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portasm.c
View file

@ -121,9 +121,9 @@
" restore_general_regs_first_task: \n"
" subs r1, #32 \n"
" ldmia r1!, {r4-r7} \n" /* r4-r7 contain half of the hardware saved context. */
" stmia r2!, {r4-r7} \n" /* Copy half of the the hardware saved context on the task stack. */
" stmia r2!, {r4-r7} \n" /* Copy half of the hardware saved context on the task stack. */
" ldmia r1!, {r4-r7} \n" /* r4-r7 contain rest half of the hardware saved context. */
" stmia r2!, {r4-r7} \n" /* Copy rest half of the the hardware saved context on the task stack. */
" stmia r2!, {r4-r7} \n" /* Copy rest half of the hardware saved context on the task stack. */
" subs r1, #48 \n"
" ldmia r1!, {r4-r7} \n" /* Restore r8-r11. */
" mov r8, r4 \n" /* r8 = r4. */
@ -375,9 +375,9 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
" restore_general_regs: \n"
" subs r1, #32 \n"
" ldmia r1!, {r4-r7} \n" /* r4-r7 contain half of the hardware saved context. */
" stmia r2!, {r4-r7} \n" /* Copy half of the the hardware saved context on the task stack. */
" stmia r2!, {r4-r7} \n" /* Copy half of the hardware saved context on the task stack. */
" ldmia r1!, {r4-r7} \n" /* r4-r7 contain rest half of the hardware saved context. */
" stmia r2!, {r4-r7} \n" /* Copy rest half of the the hardware saved context on the task stack. */
" stmia r2!, {r4-r7} \n" /* Copy rest half of the hardware saved context on the task stack. */
" subs r1, #48 \n"
" ldmia r1!, {r4-r7} \n" /* Restore r8-r11. */
" mov r8, r4 \n" /* r8 = r4. */

2
portable/ARMv8M/secure/context/secure_context.c
View file

@ -349,7 +349,7 @@ secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandl
secureportREAD_PSPLIM( pucStackLimit );
/* Ensure that task's context is loaded and the task is saving it's own
/* Ensure that task's context is loaded and the task is saving its own
* context. */
if( ( xSecureContexts[ ulSecureContextIndex ].pucStackLimit == pucStackLimit ) &&
( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) )

2
portable/CodeWarrior/HCS12/port.c
View file

@ -63,7 +63,7 @@ scheduler startup function. */
/* Calls to portENTER_CRITICAL() can be nested. When they are nested the
critical section should not be left (i.e. interrupts should not be re-enabled)
until the nesting depth reaches 0. This variable simply tracks the nesting
depth. Each task maintains it's own critical nesting depth variable so
depth. Each task maintains its own critical nesting depth variable so
uxCriticalNesting is saved and restored from the task stack during a context
switch. */
volatile UBaseType_t uxCriticalNesting = 0xff;

2
portable/GCC/ARM_CM0/port.c
View file

@ -689,7 +689,7 @@ static void prvTaskExitError( void )
}
/* Shift the code by one before returning so it can be written directly
* into the the correct bit position of the attribute register. */
* into the correct bit position of the attribute register. */
return( ulReturnValue << 1UL );
}

8
portable/GCC/ARM_CM0/portasm.c
View file

@ -111,9 +111,9 @@
" restore_general_regs_first_task: \n"
" subs r1, #32 \n"
" ldmia r1!, {r4-r7} \n" /* r4-r7 contain half of the hardware saved context. */
" stmia r2!, {r4-r7} \n" /* Copy half of the the hardware saved context on the task stack. */
" stmia r2!, {r4-r7} \n" /* Copy half of the hardware saved context on the task stack. */
" ldmia r1!, {r4-r7} \n" /* r4-r7 contain rest half of the hardware saved context. */
" stmia r2!, {r4-r7} \n" /* Copy rest half of the the hardware saved context on the task stack. */
" stmia r2!, {r4-r7} \n" /* Copy rest half of the hardware saved context on the task stack. */
" subs r1, #48 \n"
" ldmia r1!, {r4-r7} \n" /* Restore r8-r11. */
" mov r8, r4 \n" /* r8 = r4. */
@ -366,9 +366,9 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
" restore_general_regs: \n"
" subs r1, #32 \n"
" ldmia r1!, {r4-r7} \n" /* r4-r7 contain half of the hardware saved context. */
" stmia r2!, {r4-r7} \n" /* Copy half of the the hardware saved context on the task stack. */
" stmia r2!, {r4-r7} \n" /* Copy half of the hardware saved context on the task stack. */
" ldmia r1!, {r4-r7} \n" /* r4-r7 contain rest half of the hardware saved context. */
" stmia r2!, {r4-r7} \n" /* Copy rest half of the the hardware saved context on the task stack. */
" stmia r2!, {r4-r7} \n" /* Copy rest half of the hardware saved context on the task stack. */
" subs r1, #48 \n"
" ldmia r1!, {r4-r7} \n" /* Restore r8-r11. */
" mov r8, r4 \n" /* r8 = r4. */

8
portable/GCC/ARM_CM23/non_secure/portasm.c
View file

@ -126,9 +126,9 @@
" restore_general_regs_first_task: \n"
" subs r2, #32 \n"
" ldmia r2!, {r4-r7} \n" /* r4-r7 contain half of the hardware saved context. */
" stmia r3!, {r4-r7} \n" /* Copy half of the the hardware saved context on the task stack. */
" stmia r3!, {r4-r7} \n" /* Copy half of the hardware saved context on the task stack. */
" ldmia r2!, {r4-r7} \n" /* r4-r7 contain rest half of the hardware saved context. */
" stmia r3!, {r4-r7} \n" /* Copy rest half of the the hardware saved context on the task stack. */
" stmia r3!, {r4-r7} \n" /* Copy rest half of the hardware saved context on the task stack. */
" subs r2, #48 \n"
" ldmia r2!, {r4-r7} \n" /* Restore r8-r11. */
" mov r8, r4 \n" /* r8 = r4. */
@ -402,9 +402,9 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
" restore_general_regs: \n"
" subs r2, #32 \n"
" ldmia r2!, {r4-r7} \n" /* r4-r7 contain half of the hardware saved context. */
" stmia r3!, {r4-r7} \n" /* Copy half of the the hardware saved context on the task stack. */
" stmia r3!, {r4-r7} \n" /* Copy half of the hardware saved context on the task stack. */
" ldmia r2!, {r4-r7} \n" /* r4-r7 contain rest half of the hardware saved context. */
" stmia r3!, {r4-r7} \n" /* Copy rest half of the the hardware saved context on the task stack. */
" stmia r3!, {r4-r7} \n" /* Copy rest half of the hardware saved context on the task stack. */
" subs r2, #48 \n"
" ldmia r2!, {r4-r7} \n" /* Restore r8-r11. */
" mov r8, r4 \n" /* r8 = r4. */

2
portable/GCC/ARM_CM23/secure/secure_context.c
View file

@ -349,7 +349,7 @@ secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandl
secureportREAD_PSPLIM( pucStackLimit );
/* Ensure that task's context is loaded and the task is saving it's own
/* Ensure that task's context is loaded and the task is saving its own
* context. */
if( ( xSecureContexts[ ulSecureContextIndex ].pucStackLimit == pucStackLimit ) &&
( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) )

8
portable/GCC/ARM_CM23_NTZ/non_secure/portasm.c
View file

@ -121,9 +121,9 @@
" restore_general_regs_first_task: \n"
" subs r1, #32 \n"
" ldmia r1!, {r4-r7} \n" /* r4-r7 contain half of the hardware saved context. */
" stmia r2!, {r4-r7} \n" /* Copy half of the the hardware saved context on the task stack. */
" stmia r2!, {r4-r7} \n" /* Copy half of the hardware saved context on the task stack. */
" ldmia r1!, {r4-r7} \n" /* r4-r7 contain rest half of the hardware saved context. */
" stmia r2!, {r4-r7} \n" /* Copy rest half of the the hardware saved context on the task stack. */
" stmia r2!, {r4-r7} \n" /* Copy rest half of the hardware saved context on the task stack. */
" subs r1, #48 \n"
" ldmia r1!, {r4-r7} \n" /* Restore r8-r11. */
" mov r8, r4 \n" /* r8 = r4. */
@ -375,9 +375,9 @@ void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __att
" restore_general_regs: \n"
" subs r1, #32 \n"
" ldmia r1!, {r4-r7} \n" /* r4-r7 contain half of the hardware saved context. */
" stmia r2!, {r4-r7} \n" /* Copy half of the the hardware saved context on the task stack. */
" stmia r2!, {r4-r7} \n" /* Copy half of the hardware saved context on the task stack. */
" ldmia r1!, {r4-r7} \n" /* r4-r7 contain rest half of the hardware saved context. */
" stmia r2!, {r4-r7} \n" /* Copy rest half of the the hardware saved context on the task stack. */
" stmia r2!, {r4-r7} \n" /* Copy rest half of the hardware saved context on the task stack. */
" subs r1, #48 \n"
" ldmia r1!, {r4-r7} \n" /* Restore r8-r11. */
" mov r8, r4 \n" /* r8 = r4. */

2
portable/GCC/ARM_CM33/secure/secure_context.c
View file

@ -349,7 +349,7 @@ secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandl
secureportREAD_PSPLIM( pucStackLimit );
/* Ensure that task's context is loaded and the task is saving it's own
/* Ensure that task's context is loaded and the task is saving its own
* context. */
if( ( xSecureContexts[ ulSecureContextIndex ].pucStackLimit == pucStackLimit ) &&
( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) )

2
portable/GCC/ARM_CM35P/secure/secure_context.c
View file

@ -349,7 +349,7 @@ secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandl
secureportREAD_PSPLIM( pucStackLimit );
/* Ensure that task's context is loaded and the task is saving it's own
/* Ensure that task's context is loaded and the task is saving its own
* context. */
if( ( xSecureContexts[ ulSecureContextIndex ].pucStackLimit == pucStackLimit ) &&
( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) )

2
portable/GCC/ARM_CM3_MPU/port.c
View file

@ -1206,7 +1206,7 @@ static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes )
}
/* Shift the code by one before returning so it can be written directly
* into the the correct bit position of the attribute register. */
* into the correct bit position of the attribute register. */
return( ulReturnValue << 1UL );
}
/*-----------------------------------------------------------*/

2
portable/GCC/ARM_CM4_MPU/port.c
View file

@ -1350,7 +1350,7 @@ static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes )
}
/* Shift the code by one before returning so it can be written directly
* into the the correct bit position of the attribute register. */
* into the correct bit position of the attribute register. */
return( ulReturnValue << 1UL );
}
/*-----------------------------------------------------------*/

2
portable/GCC/ARM_CM52/secure/secure_context.c
View file

@ -349,7 +349,7 @@ secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandl
secureportREAD_PSPLIM( pucStackLimit );
/* Ensure that task's context is loaded and the task is saving it's own
/* Ensure that task's context is loaded and the task is saving its own
* context. */
if( ( xSecureContexts[ ulSecureContextIndex ].pucStackLimit == pucStackLimit ) &&
( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) )

2
portable/GCC/ARM_CM55/secure/secure_context.c
View file

@ -349,7 +349,7 @@ secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandl
secureportREAD_PSPLIM( pucStackLimit );
/* Ensure that task's context is loaded and the task is saving it's own
/* Ensure that task's context is loaded and the task is saving its own
* context. */
if( ( xSecureContexts[ ulSecureContextIndex ].pucStackLimit == pucStackLimit ) &&
( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) )

2
portable/GCC/ARM_CM85/secure/secure_context.c
View file

@ -349,7 +349,7 @@ secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandl
secureportREAD_PSPLIM( pucStackLimit );
/* Ensure that task's context is loaded and the task is saving it's own
/* Ensure that task's context is loaded and the task is saving its own
* context. */
if( ( xSecureContexts[ ulSecureContextIndex ].pucStackLimit == pucStackLimit ) &&
( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) )

2
portable/GCC/ARM_CRx_MPU/port.c
View file

@ -489,7 +489,7 @@ static uint32_t prvGetMPURegionSizeEncoding( uint32_t ulActualMPURegionSize )
}
/* Shift the code by one before returning so it can be written directly
* into the the correct bit position of the attribute register. */
* into the correct bit position of the attribute register. */
return ulReturnValue << 1UL;
}

2
portable/GCC/ARM_STAR_MC3/secure/secure_context.c
View file

@ -349,7 +349,7 @@ secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandl
secureportREAD_PSPLIM( pucStackLimit );
/* Ensure that task's context is loaded and the task is saving it's own
/* Ensure that task's context is loaded and the task is saving its own
* context. */
if( ( xSecureContexts[ ulSecureContextIndex ].pucStackLimit == pucStackLimit ) &&
( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) )

2
portable/GCC/HCS12/port.c
View file

@ -64,7 +64,7 @@ BaseType_t ATTR_NEAR xStartSchedulerNear( void );
/* Calls to portENTER_CRITICAL() can be nested. When they are nested the
* critical section should not be left (i.e. interrupts should not be re-enabled)
* until the nesting depth reaches 0. This variable simply tracks the nesting
* depth. Each task maintains it's own critical nesting depth variable so
* depth. Each task maintains its own critical nesting depth variable so
* uxCriticalNesting is saved and restored from the task stack during a context
* switch. */
volatile UBaseType_t uxCriticalNesting = 0x80; /* un-initialized */

4
portable/GCC/MicroBlaze/port.c
View file

@ -63,7 +63,7 @@
#define portISR_STACK_FILL_VALUE 0x55555555
/* Counts the nesting depth of calls to portENTER_CRITICAL(). Each task
* maintains it's own count, so this variable is saved as part of the task
* maintains its own count, so this variable is saved as part of the task
* context. */
volatile UBaseType_t uxCriticalNesting = portINITIAL_NESTING_VALUE;
@ -235,7 +235,7 @@ void vPortYield( void )
/* Perform the context switch in a critical section to assure it is
* not interrupted by the tick ISR. It is not a problem to do this as
* each task maintains it's own interrupt status. */
* each task maintains its own interrupt status. */
portENTER_CRITICAL();
/* Jump directly to the yield function to ensure there is no

2
portable/GCC/MicroBlazeV8/portmacro.h
View file

@ -322,7 +322,7 @@ void vApplicationSetupTimerInterrupt( void );
/*
* This is an application defined callback function used to clear whichever
* interrupt was installed by the the vApplicationSetupTimerInterrupt() callback
* interrupt was installed by the vApplicationSetupTimerInterrupt() callback
* function - in this case the interrupt generated by the AXI timer. It is
* provided as an application callback because the kernel will run on lots of
* different MicroBlaze and FPGA configurations - not all of which will have the

2
portable/GCC/MicroBlazeV9/portmacro.h
View file

@ -337,7 +337,7 @@ void vApplicationSetupTimerInterrupt( void );
/*
* This is an application defined callback function used to clear whichever
* interrupt was installed by the the vApplicationSetupTimerInterrupt() callback
* interrupt was installed by the vApplicationSetupTimerInterrupt() callback
* function - in this case the interrupt generated by the AXI timer. It is
* provided as an application callback because the kernel will run on lots of
* different MicroBlaze and FPGA configurations - not all of which will have the

2
portable/GCC/RISC-V/chip_specific_extensions/Pulpino_Vega_RV32M1RM/freertos_risc_v_chip_specific_extensions.h
View file

@ -27,7 +27,7 @@
*/
/*
* The FreeRTOS kernel's RISC-V port is split between the the code that is
* The FreeRTOS kernel's RISC-V port is split between the code that is
* common across all currently supported RISC-V chips (implementations of the
* RISC-V ISA), and code that tailors the port to a specific RISC-V chip:
*

2
portable/GCC/RISC-V/chip_specific_extensions/RISCV_MTIME_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h
View file

@ -27,7 +27,7 @@
*/
/*
* The FreeRTOS kernel's RISC-V port is split between the the code that is
* The FreeRTOS kernel's RISC-V port is split between the code that is
* common across all currently supported RISC-V chips (implementations of the
* RISC-V ISA), and code that tailors the port to a specific RISC-V chip:
*

2
portable/GCC/RISC-V/chip_specific_extensions/RISCV_no_extensions/freertos_risc_v_chip_specific_extensions.h
View file

@ -27,7 +27,7 @@
*/
/*
* The FreeRTOS kernel's RISC-V port is split between the the code that is
* The FreeRTOS kernel's RISC-V port is split between the code that is
* common across all currently supported RISC-V chips (implementations of the
* RISC-V ISA), and code that tailors the port to a specific RISC-V chip:
*

2
portable/GCC/RISC-V/chip_specific_extensions/RV32I_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h
View file

@ -27,7 +27,7 @@
*/
/*
* The FreeRTOS kernel's RISC-V port is split between the the code that is
* The FreeRTOS kernel's RISC-V port is split between the code that is
* common across all currently supported RISC-V chips (implementations of the
* RISC-V ISA), and code that tailors the port to a specific RISC-V chip:
*

2
portable/IAR/ARM_CM23/secure/secure_context.c
View file

@ -349,7 +349,7 @@ secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandl
secureportREAD_PSPLIM( pucStackLimit );
/* Ensure that task's context is loaded and the task is saving it's own
/* Ensure that task's context is loaded and the task is saving its own
* context. */
if( ( xSecureContexts[ ulSecureContextIndex ].pucStackLimit == pucStackLimit ) &&
( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) )

2
portable/IAR/ARM_CM33/secure/secure_context.c
View file

@ -349,7 +349,7 @@ secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandl
secureportREAD_PSPLIM( pucStackLimit );
/* Ensure that task's context is loaded and the task is saving it's own
/* Ensure that task's context is loaded and the task is saving its own
* context. */
if( ( xSecureContexts[ ulSecureContextIndex ].pucStackLimit == pucStackLimit ) &&
( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) )

2
portable/IAR/ARM_CM35P/secure/secure_context.c
View file

@ -349,7 +349,7 @@ secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandl
secureportREAD_PSPLIM( pucStackLimit );
/* Ensure that task's context is loaded and the task is saving it's own
/* Ensure that task's context is loaded and the task is saving its own
* context. */
if( ( xSecureContexts[ ulSecureContextIndex ].pucStackLimit == pucStackLimit ) &&
( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) )

2
portable/IAR/ARM_CM4F_MPU/port.c
View file

@ -1139,7 +1139,7 @@ static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes )
}
/* Shift the code by one before returning so it can be written directly
* into the the correct bit position of the attribute register. */
* into the correct bit position of the attribute register. */
return( ulReturnValue << 1UL );
}
/*-----------------------------------------------------------*/

2
portable/IAR/ARM_CM52/secure/secure_context.c
View file

@ -349,7 +349,7 @@ secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandl
secureportREAD_PSPLIM( pucStackLimit );
/* Ensure that task's context is loaded and the task is saving it's own
/* Ensure that task's context is loaded and the task is saving its own
* context. */
if( ( xSecureContexts[ ulSecureContextIndex ].pucStackLimit == pucStackLimit ) &&
( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) )

2
portable/IAR/ARM_CM55/secure/secure_context.c
View file

@ -349,7 +349,7 @@ secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandl
secureportREAD_PSPLIM( pucStackLimit );
/* Ensure that task's context is loaded and the task is saving it's own
/* Ensure that task's context is loaded and the task is saving its own
* context. */
if( ( xSecureContexts[ ulSecureContextIndex ].pucStackLimit == pucStackLimit ) &&
( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) )

2
portable/IAR/ARM_CM85/secure/secure_context.c
View file

@ -349,7 +349,7 @@ secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandl
secureportREAD_PSPLIM( pucStackLimit );
/* Ensure that task's context is loaded and the task is saving it's own
/* Ensure that task's context is loaded and the task is saving its own
* context. */
if( ( xSecureContexts[ ulSecureContextIndex ].pucStackLimit == pucStackLimit ) &&
( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) )

2
portable/IAR/ARM_STAR_MC3/secure/secure_context.c
View file

@ -349,7 +349,7 @@ secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandl
secureportREAD_PSPLIM( pucStackLimit );
/* Ensure that task's context is loaded and the task is saving it's own
/* Ensure that task's context is loaded and the task is saving its own
* context. */
if( ( xSecureContexts[ ulSecureContextIndex ].pucStackLimit == pucStackLimit ) &&
( xSecureContexts[ ulSecureContextIndex ].pvTaskHandle == pvTaskHandle ) )

2
portable/IAR/RISC-V/chip_specific_extensions/RV32I_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h
View file

@ -27,7 +27,7 @@
*/
/*
* The FreeRTOS kernel's RISC-V port is split between the the code that is
* The FreeRTOS kernel's RISC-V port is split between the code that is
* common across all currently supported RISC-V chips (implementations of the
* RISC-V ISA), and code that tailors the port to a specific RISC-V chip:
*

2
portable/MPLAB/PIC32MEC14xx/ISR_Support.h
View file

@ -78,7 +78,7 @@
la k0, uxInterruptNesting
lw s6, (k0)
/* If the nesting count is 0 then swap to the the system stack, otherwise
/* If the nesting count is 0 then swap to the system stack, otherwise
the system stack is already being used. */
bne s6, zero, 1f
nop

2
portable/MPLAB/PIC32MX/ISR_Support.h
View file

@ -60,7 +60,7 @@
la k0, uxInterruptNesting
lw s6, (k0)
/* If the nesting count is 0 then swap to the the system stack, otherwise
/* If the nesting count is 0 then swap to the system stack, otherwise
the system stack is already being used. */
bne s6, zero, 1f
nop

2
portable/MPLAB/PIC32MZ/ISR_Support.h
View file

@ -174,7 +174,7 @@
la k0, uxInterruptNesting
lw s6, (k0)
/* If the nesting count is 0 then swap to the the system stack, otherwise
/* If the nesting count is 0 then swap to the system stack, otherwise
the system stack is already being used. */
bne s6, zero, 1f
nop

2
portable/RVDS/ARM_CM4_MPU/port.c
View file

@ -1351,7 +1351,7 @@ static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes )
}
/* Shift the code by one before returning so it can be written directly
* into the the correct bit position of the attribute register. */
* into the correct bit position of the attribute register. */
return( ulReturnValue << 1UL );
}
/*-----------------------------------------------------------*/