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https://github.com/FreeRTOS/FreeRTOS-Kernel.git
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Pre-allocate secure-side context structures
This commit improves ARMv8-M security by pre-allocating secure-side task context structures and changing how tasks reference a secure-side context structure when calling a secure function. The new configuration constant secureconfigMAX_SECURE_CONTEXTS sets the number of secure context structures to pre-allocate. secureconfigMAX_SECURE_CONTEXTS defaults to 8 if left undefined. Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
This commit is contained in:
Gaurav Aggarwal
Gaurav-Aggarwal-AWS
parent
f8ada39d85
commit
ccaa0f4d6e
27 changed files with 1012 additions and 657 deletions
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@ -36,56 +36,60 @@
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#error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.
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#endif
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secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle )
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void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext )
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{
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/* xSecureContextHandle value is in r0. */
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/* pxSecureContext value is in r0. */
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__asm volatile
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(
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" .syntax unified \n"
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" \n"
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" mrs r1, ipsr \n"/* r1 = IPSR. */
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" cbz r1, load_ctx_therad_mode \n"/* Do nothing if the processor is running in the Thread Mode. */
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" ldmia r0!, {r1, r2} \n"/* r1 = xSecureContextHandle->pucCurrentStackPointer, r2 = xSecureContextHandle->pucStackLimit. */
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" .syntax unified \n"
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" \n"
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" mrs r1, ipsr \n" /* r1 = IPSR. */
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" cbz r1, load_ctx_therad_mode \n" /* Do nothing if the processor is running in the Thread Mode. */
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" ldmia r0!, {r1, r2} \n" /* r1 = pxSecureContext->pucCurrentStackPointer, r2 = pxSecureContext->pucStackLimit. */
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" \n"
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#if ( configENABLE_MPU == 1 )
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" ldmia r1!, {r3} \n"/* Read CONTROL register value from task's stack. r3 = CONTROL. */
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" msr control, r3 \n"/* CONTROL = r3. */
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" ldmia r1!, {r3} \n" /* Read CONTROL register value from task's stack. r3 = CONTROL. */
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" msr control, r3 \n" /* CONTROL = r3. */
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#endif /* configENABLE_MPU */
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" msr psplim, r2 \n"/* PSPLIM = r2. */
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" msr psp, r1 \n"/* PSP = r1. */
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" \n"
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" load_ctx_therad_mode: \n"
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" nop \n"
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" \n"
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" \n"
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" msr psplim, r2 \n" /* PSPLIM = r2. */
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" msr psp, r1 \n" /* PSP = r1. */
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" \n"
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" load_ctx_therad_mode: \n"
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" bx lr \n"
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" \n"
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::: "r0", "r1", "r2"
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);
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}
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/*-----------------------------------------------------------*/
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secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle )
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void SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext )
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{
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/* xSecureContextHandle value is in r0. */
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/* pxSecureContext value is in r0. */
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__asm volatile
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(
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" .syntax unified \n"
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" \n"
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" mrs r1, ipsr \n"/* r1 = IPSR. */
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" cbz r1, save_ctx_therad_mode \n"/* Do nothing if the processor is running in the Thread Mode. */
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" mrs r1, psp \n"/* r1 = PSP. */
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" .syntax unified \n"
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" \n"
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" mrs r1, ipsr \n" /* r1 = IPSR. */
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" cbz r1, save_ctx_therad_mode \n" /* Do nothing if the processor is running in the Thread Mode. */
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" mrs r1, psp \n" /* r1 = PSP. */
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" \n"
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#if ( configENABLE_MPU == 1 )
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" mrs r2, control \n"/* r2 = CONTROL. */
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" subs r1, r1, #4 \n"/* Make space for the CONTROL value on the stack. */
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" str r1, [r0] \n"/* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */
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" stmia r1!, {r2} \n"/* Store CONTROL value on the stack. */
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" mrs r2, control \n" /* r2 = CONTROL. */
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" subs r1, r1, #4 \n" /* Make space for the CONTROL value on the stack. */
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" str r1, [r0] \n" /* Save the top of stack in context. pxSecureContext->pucCurrentStackPointer = r1. */
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" stmia r1!, {r2} \n" /* Store CONTROL value on the stack. */
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#else /* configENABLE_MPU */
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" str r1, [r0] \n"/* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */
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" str r1, [r0] \n" /* Save the top of stack in context. pxSecureContext->pucCurrentStackPointer = r1. */
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#endif /* configENABLE_MPU */
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" movs r1, %0 \n"/* r1 = securecontextNO_STACK. */
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" msr psplim, r1 \n"/* PSPLIM = securecontextNO_STACK. */
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" msr psp, r1 \n"/* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */
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" \n"
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" save_ctx_therad_mode: \n"
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" nop \n"
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" \n"
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" \n"
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" movs r1, %0 \n" /* r1 = securecontextNO_STACK. */
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" msr psplim, r1 \n" /* PSPLIM = securecontextNO_STACK. */
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" msr psp, r1 \n" /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */
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" \n"
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" save_ctx_therad_mode: \n"
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" bx lr \n"
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" \n"
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::"i" ( securecontextNO_STACK ) : "r1", "memory"
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);
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}
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@ -32,57 +32,62 @@
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/* Secure port macros. */
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#include "secure_port_macros.h"
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secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle )
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void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext )
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{
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/* xSecureContextHandle value is in r0. */
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/* pxSecureContext value is in r0. */
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__asm volatile
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(
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" .syntax unified \n"
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" \n"
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" mrs r1, ipsr \n"/* r1 = IPSR. */
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" cbz r1, load_ctx_therad_mode \n"/* Do nothing if the processor is running in the Thread Mode. */
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" ldmia r0!, {r1, r2} \n"/* r1 = xSecureContextHandle->pucCurrentStackPointer, r2 = xSecureContextHandle->pucStackLimit. */
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" .syntax unified \n"
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" \n"
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" mrs r1, ipsr \n" /* r1 = IPSR. */
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" cbz r1, load_ctx_therad_mode \n" /* Do nothing if the processor is running in the Thread Mode. */
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" ldmia r0!, {r1, r2} \n" /* r1 = pxSecureContext->pucCurrentStackPointer, r2 = pxSecureContext->pucStackLimit. */
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" \n"
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#if ( configENABLE_MPU == 1 )
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" ldmia r1!, {r3} \n"/* Read CONTROL register value from task's stack. r3 = CONTROL. */
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" msr control, r3 \n"/* CONTROL = r3. */
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" ldmia r1!, {r3} \n" /* Read CONTROL register value from task's stack. r3 = CONTROL. */
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" msr control, r3 \n" /* CONTROL = r3. */
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#endif /* configENABLE_MPU */
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" msr psplim, r2 \n"/* PSPLIM = r2. */
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" msr psp, r1 \n"/* PSP = r1. */
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" \n"
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" load_ctx_therad_mode: \n"
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" nop \n"
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" \n"
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" \n"
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" msr psplim, r2 \n" /* PSPLIM = r2. */
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" msr psp, r1 \n" /* PSP = r1. */
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" \n"
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" load_ctx_therad_mode: \n"
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" bx lr \n"
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" \n"
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::: "r0", "r1", "r2"
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);
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}
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/*-----------------------------------------------------------*/
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secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle )
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void SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext )
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{
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/* xSecureContextHandle value is in r0. */
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/* pxSecureContext value is in r0. */
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__asm volatile
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(
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" .syntax unified \n"
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" \n"
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" mrs r1, ipsr \n"/* r1 = IPSR. */
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" cbz r1, save_ctx_therad_mode \n"/* Do nothing if the processor is running in the Thread Mode. */
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" mrs r1, psp \n"/* r1 = PSP. */
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" .syntax unified \n"
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" \n"
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" mrs r1, ipsr \n" /* r1 = IPSR. */
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" cbz r1, save_ctx_therad_mode \n" /* Do nothing if the processor is running in the Thread Mode. */
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" mrs r1, psp \n" /* r1 = PSP. */
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" \n"
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#if ( configENABLE_FPU == 1 )
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" vstmdb r1!, {s0} \n"/* Trigger the defferred stacking of FPU registers. */
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" vldmia r1!, {s0} \n"/* Nullify the effect of the pervious statement. */
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" vstmdb r1!, {s0} \n" /* Trigger the defferred stacking of FPU registers. */
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" vldmia r1!, {s0} \n" /* Nullify the effect of the pervious statement. */
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#endif /* configENABLE_FPU */
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" \n"
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#if ( configENABLE_MPU == 1 )
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" mrs r2, control \n"/* r2 = CONTROL. */
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" stmdb r1!, {r2} \n"/* Store CONTROL value on the stack. */
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" mrs r2, control \n" /* r2 = CONTROL. */
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" stmdb r1!, {r2} \n" /* Store CONTROL value on the stack. */
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#endif /* configENABLE_MPU */
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" str r1, [r0] \n"/* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */
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" movs r1, %0 \n"/* r1 = securecontextNO_STACK. */
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" msr psplim, r1 \n"/* PSPLIM = securecontextNO_STACK. */
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" msr psp, r1 \n"/* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */
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" \n"
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" save_ctx_therad_mode: \n"
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" nop \n"
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" \n"
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" \n"
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" str r1, [r0] \n" /* Save the top of stack in context. pxSecureContext->pucCurrentStackPointer = r1. */
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" movs r1, %0 \n" /* r1 = securecontextNO_STACK. */
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" msr psplim, r1 \n" /* PSPLIM = securecontextNO_STACK. */
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" msr psp, r1 \n" /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */
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" \n"
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" save_ctx_therad_mode: \n"
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" bx lr \n"
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" \n"
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::"i" ( securecontextNO_STACK ) : "r1", "memory"
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);
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}
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