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The LPC43xx fast start files are now included.

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This commit is contained in:
Richard Barry 2011-12-13 11:36:38 +00:00
parent a0eb27a69e
commit cc06119b86
16 changed files with 34611 additions and 1705 deletions
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4
Demo/CORTEX_M4F_M0_LPC43xx_Keil/M4/FreeRTOSConfig.h
View file

@ -73,11 +73,11 @@
#define configUSE_PREEMPTION 1 #define configUSE_PREEMPTION 1
#define configUSE_IDLE_HOOK 1 #define configUSE_IDLE_HOOK 1
#define configUSE_TICK_HOOK 1 #define configUSE_TICK_HOOK 1
#define configCPU_CLOCK_HZ ( 120000000UL ) #define configCPU_CLOCK_HZ ( 204000000UL )
#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) #define configTICK_RATE_HZ ( ( portTickType ) 1000 )
#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 ) #define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 )
#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 130 ) #define configMINIMAL_STACK_SIZE ( ( unsigned short ) 130 )
#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 75 * 1024 ) ) #define configTOTAL_HEAP_SIZE ( ( size_t ) ( 40960 ) )
#define configMAX_TASK_NAME_LEN ( 10 ) #define configMAX_TASK_NAME_LEN ( 10 )
#define configUSE_TRACE_FACILITY 1 #define configUSE_TRACE_FACILITY 1
#define configUSE_16_BIT_TICKS 0 #define configUSE_16_BIT_TICKS 0

62
Demo/CORTEX_M4F_M0_LPC43xx_Keil/M4/M4.uvopt
View file

@ -151,7 +151,7 @@
<Type>0</Type> <Type>0</Type>
<LineNumber>308</LineNumber> <LineNumber>308</LineNumber>
<EnabledFlag>1</EnabledFlag> <EnabledFlag>1</EnabledFlag>
<Address>469765048</Address> <Address>469766624</Address>
<ByteObject>0</ByteObject> <ByteObject>0</ByteObject>
<ManyObjects>0</ManyObjects> <ManyObjects>0</ManyObjects>
<SizeOfObject>0</SizeOfObject> <SizeOfObject>0</SizeOfObject>
@ -206,8 +206,8 @@
<Focus>0</Focus> <Focus>0</Focus>
<ColumnNumber>0</ColumnNumber> <ColumnNumber>0</ColumnNumber>
<tvExpOptDlg>0</tvExpOptDlg> <tvExpOptDlg>0</tvExpOptDlg>
<TopLine>0</TopLine> <TopLine>164</TopLine>
<CurrentLine>0</CurrentLine> <CurrentLine>164</CurrentLine>
<bDave2>0</bDave2> <bDave2>0</bDave2>
<PathWithFileName>..\platform\startup_LPC43xx.s</PathWithFileName> <PathWithFileName>..\platform\startup_LPC43xx.s</PathWithFileName>
<FilenameWithoutPath>startup_LPC43xx.s</FilenameWithoutPath> <FilenameWithoutPath>startup_LPC43xx.s</FilenameWithoutPath>
@ -290,8 +290,8 @@
<Focus>0</Focus> <Focus>0</Focus>
<ColumnNumber>0</ColumnNumber> <ColumnNumber>0</ColumnNumber>
<tvExpOptDlg>0</tvExpOptDlg> <tvExpOptDlg>0</tvExpOptDlg>
<TopLine>0</TopLine> <TopLine>39</TopLine>
<CurrentLine>0</CurrentLine> <CurrentLine>58</CurrentLine>
<bDave2>0</bDave2> <bDave2>0</bDave2>
<PathWithFileName>..\system\Hitex_Fast_Startup.c</PathWithFileName> <PathWithFileName>..\system\Hitex_Fast_Startup.c</PathWithFileName>
<FilenameWithoutPath>Hitex_Fast_Startup.c</FilenameWithoutPath> <FilenameWithoutPath>Hitex_Fast_Startup.c</FilenameWithoutPath>
@ -304,8 +304,8 @@
<Focus>0</Focus> <Focus>0</Focus>
<ColumnNumber>0</ColumnNumber> <ColumnNumber>0</ColumnNumber>
<tvExpOptDlg>0</tvExpOptDlg> <tvExpOptDlg>0</tvExpOptDlg>
<TopLine>0</TopLine> <TopLine>142</TopLine>
<CurrentLine>0</CurrentLine> <CurrentLine>164</CurrentLine>
<bDave2>0</bDave2> <bDave2>0</bDave2>
<PathWithFileName>..\platform\M4_PeripheralLibraryFiles\lpc43xx_emc.c</PathWithFileName> <PathWithFileName>..\platform\M4_PeripheralLibraryFiles\lpc43xx_emc.c</PathWithFileName>
<FilenameWithoutPath>lpc43xx_emc.c</FilenameWithoutPath> <FilenameWithoutPath>lpc43xx_emc.c</FilenameWithoutPath>
@ -337,10 +337,10 @@
<FileType>1</FileType> <FileType>1</FileType>
<tvExp>0</tvExp> <tvExp>0</tvExp>
<Focus>0</Focus> <Focus>0</Focus>
<ColumnNumber>0</ColumnNumber> <ColumnNumber>54</ColumnNumber>
<tvExpOptDlg>0</tvExpOptDlg> <tvExpOptDlg>0</tvExpOptDlg>
<TopLine>0</TopLine> <TopLine>1</TopLine>
<CurrentLine>0</CurrentLine> <CurrentLine>25</CurrentLine>
<bDave2>0</bDave2> <bDave2>0</bDave2>
<PathWithFileName>..\platform\platform_config.c</PathWithFileName> <PathWithFileName>..\platform\platform_config.c</PathWithFileName>
<FilenameWithoutPath>platform_config.c</FilenameWithoutPath> <FilenameWithoutPath>platform_config.c</FilenameWithoutPath>
@ -358,10 +358,10 @@
<FileType>1</FileType> <FileType>1</FileType>
<tvExp>0</tvExp> <tvExp>0</tvExp>
<Focus>0</Focus> <Focus>0</Focus>
<ColumnNumber>15</ColumnNumber> <ColumnNumber>4</ColumnNumber>
<tvExpOptDlg>0</tvExpOptDlg> <tvExpOptDlg>0</tvExpOptDlg>
<TopLine>195</TopLine> <TopLine>47</TopLine>
<CurrentLine>199</CurrentLine> <CurrentLine>62</CurrentLine>
<bDave2>0</bDave2> <bDave2>0</bDave2>
<PathWithFileName>.\main.c</PathWithFileName> <PathWithFileName>.\main.c</PathWithFileName>
<FilenameWithoutPath>main.c</FilenameWithoutPath> <FilenameWithoutPath>main.c</FilenameWithoutPath>
@ -374,8 +374,8 @@
<Focus>0</Focus> <Focus>0</Focus>
<ColumnNumber>0</ColumnNumber> <ColumnNumber>0</ColumnNumber>
<tvExpOptDlg>0</tvExpOptDlg> <tvExpOptDlg>0</tvExpOptDlg>
<TopLine>0</TopLine> <TopLine>97</TopLine>
<CurrentLine>0</CurrentLine> <CurrentLine>104</CurrentLine>
<bDave2>0</bDave2> <bDave2>0</bDave2>
<PathWithFileName>.\ParTest.c</PathWithFileName> <PathWithFileName>.\ParTest.c</PathWithFileName>
<FilenameWithoutPath>ParTest.c</FilenameWithoutPath> <FilenameWithoutPath>ParTest.c</FilenameWithoutPath>
@ -388,12 +388,26 @@
<Focus>0</Focus> <Focus>0</Focus>
<ColumnNumber>0</ColumnNumber> <ColumnNumber>0</ColumnNumber>
<tvExpOptDlg>0</tvExpOptDlg> <tvExpOptDlg>0</tvExpOptDlg>
<TopLine>0</TopLine> <TopLine>109</TopLine>
<CurrentLine>0</CurrentLine> <CurrentLine>122</CurrentLine>
<bDave2>0</bDave2> <bDave2>0</bDave2>
<PathWithFileName>.\RegTest.c</PathWithFileName> <PathWithFileName>.\RegTest.c</PathWithFileName>
<FilenameWithoutPath>RegTest.c</FilenameWithoutPath> <FilenameWithoutPath>RegTest.c</FilenameWithoutPath>
</File> </File>
<File>
<GroupNumber>3</GroupNumber>
<FileNumber>0</FileNumber>
<FileType>5</FileType>
<tvExp>0</tvExp>
<Focus>0</Focus>
<ColumnNumber>41</ColumnNumber>
<tvExpOptDlg>0</tvExpOptDlg>
<TopLine>55</TopLine>
<CurrentLine>76</CurrentLine>
<bDave2>0</bDave2>
<PathWithFileName>.\FreeRTOSConfig.h</PathWithFileName>
<FilenameWithoutPath>FreeRTOSConfig.h</FilenameWithoutPath>
</File>
</Group> </Group>
<Group> <Group>
@ -465,8 +479,8 @@
<Focus>0</Focus> <Focus>0</Focus>
<ColumnNumber>0</ColumnNumber> <ColumnNumber>0</ColumnNumber>
<tvExpOptDlg>0</tvExpOptDlg> <tvExpOptDlg>0</tvExpOptDlg>
<TopLine>0</TopLine> <TopLine>432</TopLine>
<CurrentLine>0</CurrentLine> <CurrentLine>445</CurrentLine>
<bDave2>0</bDave2> <bDave2>0</bDave2>
<PathWithFileName>..\..\..\Source\queue.c</PathWithFileName> <PathWithFileName>..\..\..\Source\queue.c</PathWithFileName>
<FilenameWithoutPath>queue.c</FilenameWithoutPath> <FilenameWithoutPath>queue.c</FilenameWithoutPath>
@ -689,8 +703,8 @@
<Focus>0</Focus> <Focus>0</Focus>
<ColumnNumber>0</ColumnNumber> <ColumnNumber>0</ColumnNumber>
<tvExpOptDlg>0</tvExpOptDlg> <tvExpOptDlg>0</tvExpOptDlg>
<TopLine>0</TopLine> <TopLine>412</TopLine>
<CurrentLine>0</CurrentLine> <CurrentLine>425</CurrentLine>
<bDave2>0</bDave2> <bDave2>0</bDave2>
<PathWithFileName>..\platform\M4_PeripheralLibraryFiles\lpc43xx_cgu.c</PathWithFileName> <PathWithFileName>..\platform\M4_PeripheralLibraryFiles\lpc43xx_cgu.c</PathWithFileName>
<FilenameWithoutPath>lpc43xx_cgu.c</FilenameWithoutPath> <FilenameWithoutPath>lpc43xx_cgu.c</FilenameWithoutPath>
@ -706,9 +720,9 @@
<Documents> <Documents>
<Doc> <Doc>
<Name>.\main.c</Name> <Name>.\main.c</Name>
<ColumnNumber>15</ColumnNumber> <ColumnNumber>4</ColumnNumber>
<TopLine>195</TopLine> <TopLine>47</TopLine>
<CurrentLine>199</CurrentLine> <CurrentLine>62</CurrentLine>
</Doc> </Doc>
</Documents> </Documents>
</MDIGroup> </MDIGroup>

7
Demo/CORTEX_M4F_M0_LPC43xx_Keil/M4/M4.uvproj
View file

@ -331,7 +331,7 @@
</ArmAdsMisc> </ArmAdsMisc>
<Cads> <Cads>
<interw>1</interw> <interw>1</interw>
<Optim>2</Optim> <Optim>1</Optim>
<oTime>0</oTime> <oTime>0</oTime>
<SplitLS>0</SplitLS> <SplitLS>0</SplitLS>
<OneElfS>0</OneElfS> <OneElfS>0</OneElfS>
@ -461,6 +461,11 @@
<FileType>1</FileType> <FileType>1</FileType>
<FilePath>.\RegTest.c</FilePath> <FilePath>.\RegTest.c</FilePath>
</File> </File>
<File>
<FileName>FreeRTOSConfig.h</FileName>
<FileType>5</FileType>
<FilePath>.\FreeRTOSConfig.h</FilePath>
</File>
</Files> </Files>
</Group> </Group>
<Group> <Group>

7
Demo/CORTEX_M4F_M0_LPC43xx_Keil/M4/main.c
View file

@ -196,7 +196,7 @@ volatile unsigned long ulRegTest1LoopCounter = 0UL, ulRegTest2LoopCounter = 0UL;
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
int main(void) int main( void )
{ {
/* Configure the hardware ready to run the test. */ /* Configure the hardware ready to run the test. */
prvSetupHardware(); prvSetupHardware();
@ -320,9 +320,14 @@ unsigned long ulErrorFound = pdFALSE;
static void prvSetupHardware( void ) static void prvSetupHardware( void )
{ {
extern void Hitex_CGU_Init( void );
/* Setup system (clock, PLL and Flash configuration) */ /* Setup system (clock, PLL and Flash configuration) */
platformInit(); platformInit();
/* Wind the clock speed up in steps to its maximum. */
Hitex_CGU_Init();
/* Ensure all priority bits are assigned as preemption priority bits. */ /* Ensure all priority bits are assigned as preemption priority bits. */
NVIC_SetPriorityGrouping( 0 ); NVIC_SetPriorityGrouping( 0 );

53
Demo/CORTEX_M4F_M0_LPC43xx_Keil/abstract.txt
View file

@ -1,53 +0,0 @@
IPC demo program based on mailbox
-----------------------------------------
- within the file platform_config.h the user needs to specify the system configuration.
The user can specifiy:
* which mailboxes are required (host, slave, or both)
* if the M0 memory has to be initialized to a specific value before download
* the usage of an optional 32-bit parameter for the mailboxes
* the availability of a callback function for the mailboxes
* the priority of the interrupt associated with the IPC communication
* the memory locations of the M0 code/data, buffers for M0 and M4, location of the mailboxes
* if the M4 shall download the M0 and start it via INITIALIZE_M0_IMAGE (YES/NO)
The linker scatter file needs to be consistent with the provided ROM/RAM addresses in case of changes.
Set it to NO if you want to debug the M0 application separately.
Set to YES means the M4 will reset, download, and release the M0. In this case, the debug connection could be lost.
For debugging, in this scenario the .ini file shall be modified, not to download the application but just to connect to the processor.
- according to the number of mailbox desired, if callbacks are enabled, the user has to provide a callback table within the Mx_usr_mbx_callbacks.c file.
In Mx_usr_mbx_callbacks.h file the mailbox numbering is defined. Within the callback table, each callback gets associated to the related mailbox number.
The order in the table is not important, since the callback function addresses are plugged-in at runtime by the IPC initialization routines.
- The mailbox table defined in ipc_buffer.c needs also to be updated accordingly to accomodate the desired number of mailboxes. There can be
- since the callbacks are executed within the ISR, their usage is meant for quick operations that need to be performed in reaction to the mailbox event
For normal application processing, message pending flags are provided and shall rather be used, to avoid increasing unnecessarily interrupt latency
- the type of logical messages for the mailboxes are defined within the Mx_ipc_msg.h file
- the application runs completely from RAM and exchanges messages between the processors, showing how to post and read from the mailboxes.

2
Demo/CORTEX_M4F_M0_LPC43xx_Keil/platform/M4_Flash.sct
View file

@ -24,6 +24,8 @@ LR_IROM1 0x1C000000 0x400000 { ; load region size_region
RW_IRAM1 +0 (0x18000 - 0xC0) { ; RW data RW_IRAM1 +0 (0x18000 - 0xC0) { ; RW data
.ANY (+RW +ZI) .ANY (+RW +ZI)
Hitex_Fast_Startup.o (+RO +ZI +RW)
lpc43xx_cgu.o (+RO +ZI +RW)
} }
; #define M4_BUF_START 0x20000000 ; #define M4_BUF_START 0x20000000

2
Demo/CORTEX_M4F_M0_LPC43xx_Keil/platform/M4_PeripheralLibraryFiles/lpc43xx_cgu.c
View file

@ -31,7 +31,7 @@
/* Includes ------------------------------------------------------------------- */ /* Includes ------------------------------------------------------------------- */
#include "lpc_types.h" #include "lpc_types.h"
#include "lpc43xx_scu.h" #include "scu.h"
#include "lpc43xx_cgu.h" #include "lpc43xx_cgu.h"
/** This define used to fix mistake when run with IAR compiler */ /** This define used to fix mistake when run with IAR compiler */

233
Demo/CORTEX_M4F_M0_LPC43xx_Keil/platform/M4_PeripheralLibraryFiles/lpc43xx_emc.c Normal file
View file

@ -0,0 +1,233 @@
/**********************************************************************
* $Id: lpc43xx_emc.c 8765 2011-12-08 00:51:21Z nxp21346 $ lpc43xx_emc.c 2011-12-07
*//**
* @file lpc43xx_emc.c
* @brief Contains all functions support for Clock Generation and Control
* firmware library on lpc43xx
* @version 1.0
* @date 07. December. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/
#include "LPC43xx.h"
#include "lpc43xx_emc.h"
#include "scu.h"
#define M32(x) *((uint32_t *)x)
#define DELAYCYCLES(ns) (ns / ((1.0 / __EMCHZ) * 1E9))
void emc_WaitMinUS(volatile uint32_t us)
{
us *= (120000000UL / 1000000) / 3;
while(us--);
}
void emc_WaitMinMS(uint32_t ms)
{
emc_WaitMinUS(ms * 1000);
}
void MemoryPinInit(void)
{
/* select correct functions on the GPIOs */
#if 1
/* DATA LINES 0..31 > D0..D31 */
/* P1_7 - EXTBUS_D0 — External memory data line 0 */
scu_pinmux(0x1, 7, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P1_7: D0 (function 0) errata */
scu_pinmux(0x1, 8, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P1_8: D1 (function 0) errata */
scu_pinmux(0x1, 9, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P1_9: D2 (function 0) errata */
scu_pinmux(0x1, 10, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P1_10: D3 (function 0) errata */
scu_pinmux(0x1, 11, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P1_11: D4 (function 0) errata */
scu_pinmux(0x1, 12, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P1_12: D5 (function 0) errata */
scu_pinmux(0x1, 13, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P1_13: D6 (function 0) errata */
scu_pinmux(0x1, 14, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P1_14: D7 (function 0) errata */
scu_pinmux(0x5, 4, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* P5_4: D8 (function 0) errata */
scu_pinmux(0x5, 5, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* P5_5: D9 (function 0) errata */
scu_pinmux(0x5, 6, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* P5_6: D10 (function 0) errata */
scu_pinmux(0x5, 7, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* P5_7: D11 (function 0) errata */
scu_pinmux(0x5, 0, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* P5_0: D12 (function 0) errata */
scu_pinmux(0x5, 1, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* P5_1: D13 (function 0) errata */
scu_pinmux(0x5, 2, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* P5_2: D14 (function 0) errata */
scu_pinmux(0x5, 3, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* P5_3: D15 (function 0) errata */
#if 0
scu_pinmux(0xD, 2, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* PD_2: D16 (function 0) errata */
scu_pinmux(0xD, 3, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* PD_3: D17 (function 0) errata */
scu_pinmux(0xD, 4, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* PD_4: D18 (function 0) errata */
scu_pinmux(0xD, 5, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* PD_5: D19 (function 0) errata */
scu_pinmux(0xD, 6, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* PD_6: D20 (function 0) errata */
scu_pinmux(0xD, 7, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* PD_7: D21 (function 0) errata */
scu_pinmux(0xD, 8, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* PD_8: D22 (function 0) errata */
scu_pinmux(0xD, 9, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* PD_9: D23 (function 0) errata */
scu_pinmux(0xE, 5, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* PE_5: D24 (function 0) errata */
scu_pinmux(0xE, 6, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* PE_6: D25 (function 0) errata */
scu_pinmux(0xE, 7, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* PE_7: D26 (function 0) errata */
scu_pinmux(0xE, 8, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* PE_8: D27 (function 0) errata */
scu_pinmux(0xE, 9, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* PE_9: D28 (function 0) errata */
scu_pinmux(0xE, 10, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* PE_10: D29 (function 0) errata */
scu_pinmux(0xE, 11, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* PE_11: D30 (function 0) errata */
scu_pinmux(0xE, 12, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* PE_12: D31 (function 0) errata */
#endif
/* ADDRESS LINES A0..A11 > A0..A11 */
scu_pinmux(0x2, 9, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P2_9 - EXTBUS_A0 — External memory address line 0 */
scu_pinmux(0x2, 10, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P2_10 - EXTBUS_A1 — External memory address line 1 */
scu_pinmux(0x2, 11, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P2_11 - EXTBUS_A2 — External memory address line 2 */
scu_pinmux(0x2, 12, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P2_12 - EXTBUS_A3 — External memory address line 3 */
scu_pinmux(0x2, 13, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P2_13 - EXTBUS_A4 — External memory address line 4 */
scu_pinmux(0x1, 0, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* P1_0 - EXTBUS_A5 — External memory address line 5 */
scu_pinmux(0x1, 1, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* P1_1 - EXTBUS_A6 — External memory address line 6 */
scu_pinmux(0x1, 2, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* P1_2 - EXTBUS_A7 — External memory address line 7 */
scu_pinmux(0x2, 8, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P2_8 - EXTBUS_A8 — External memory address line 8 */
scu_pinmux(0x2, 7, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P2_7 - EXTBUS_A9 — External memory address line 9 */
scu_pinmux(0x2, 6, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* P2_6 - EXTBUS_A10 — External memory address line 10 */
scu_pinmux(0x2, 2, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* P2_2 - EXTBUS_A11 — External memory address line 11 */
scu_pinmux(0x2, 1, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* P2_1 - EXTBUS_A12 — External memory address line 12 */
scu_pinmux(0x2, 0, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* P2_0 - EXTBUS_A13 — External memory address line 13 */
scu_pinmux(0x6, 8, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC1); /* P6_8 - EXTBUS_A14 — External memory address line 14 */
scu_pinmux(0x6, 7, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC1); /* P6_7 - EXTBUS_A15 — External memory address line 15 */
scu_pinmux(0xD, 16, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* PD_16 - EXTBUS_A16 — External memory address line 16 */
scu_pinmux(0xD, 15, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* PD_15 - EXTBUS_A17 — External memory address line 17 */
scu_pinmux(0xE, 0, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* PE_0 - EXTBUS_A18 — External memory address line 18 */
scu_pinmux(0xE, 1, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* PE_1 - EXTBUS_A19 — External memory address line 19 */
scu_pinmux(0xE, 2, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* PE_2 - EXTBUS_A20 — External memory address line 20 */
scu_pinmux(0xE, 3, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* PE_3 - EXTBUS_A21 — External memory address line 21 */
scu_pinmux(0xE, 4, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* PE_4 - EXTBUS_A22 — External memory address line 22 */
scu_pinmux(0xA, 4, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* PA_4 - EXTBUS_A23 — External memory address line 23 */
/* BYTE ENABLES */
scu_pinmux(0x1, 4, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P1_4 - EXTBUS_BLS0 — LOW active Byte Lane select signal 0 */
scu_pinmux(0x6, 6, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC1); /* P6_6 - EXTBUS_BLS1 — LOW active Byte Lane select signal 1 */
scu_pinmux(0xD, 13, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* PD_13 - EXTBUS_BLS2 — LOW active Byte Lane select signal 2 */
scu_pinmux(0xD, 10, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* PD_10 - EXTBUS_BLS3 — LOW active Byte Lane select signal 3 */
scu_pinmux(0x6, 9, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P6_9: EXTBUS_DYCS0 (function 0) > CS# errata */
scu_pinmux(0x1, 6, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P1_6: WE (function 0) errata */
scu_pinmux(0x6, 4, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P6_4: CAS (function 0) > CAS# errata */
scu_pinmux(0x6, 5, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P6_5: RAS (function 0) > RAS# errata */
LPC_SCU_CLK(0) = 0 + (MD_PLN | MD_EZI | MD_ZI | MD_EHS); /* SFSCLK0: EXTBUS_CLK0 (function 0, from datasheet) > CLK ds */
LPC_SCU_CLK(1) = 0 + (MD_PLN | MD_EZI | MD_ZI | MD_EHS); /* SFSCLK1: EXTBUS_CLK1 (function 2, from datasheet) */
LPC_SCU_CLK(2) = 0 + (MD_PLN | MD_EZI | MD_ZI | MD_EHS); /* SFSCLK2: EXTBUS_CLK2 (function 2, from datasheet) */
LPC_SCU_CLK(3) = 0 + (MD_PLN | MD_EZI | MD_ZI | MD_EHS); /* SFSCLK3: EXTBUS_CLK3 (function 2, from datasheet) */
scu_pinmux(0x6, 11, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P6_11: CKEOUT0 (function 0) > CKE errata */
scu_pinmux(0x6, 12, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P6_12: DQMOUT0 (function 0) > DQM0 errata */
scu_pinmux(0x6, 10, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* P6_10: DQMOUT1 (function 0) > DQM1 errata */
scu_pinmux(0xD, 0, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC2); /* PD_0: DQMOUT2 (function 2, from datasheet) > DQM2 errata */
scu_pinmux(0xE, 13, (MD_PLN | MD_EZI | MD_ZI | MD_EHS), FUNC3); /* PE_13: DQMOUT3 (function 3, from datasheet) > DQM3 errata */
scu_pinmux( 1 , 3 , MD_PLN_FAST , 3 ); //OE
scu_pinmux( 1 , 4 , MD_PLN_FAST , 3 ); //BLS0
scu_pinmux( 1 , 5 , MD_PLN_FAST , 3 ); //CS0
scu_pinmux( 1 , 6 , MD_PLN_FAST , 3 ); //WE
#endif
}
void EMCFlashInit(void)
{
// Hitex board SST39VF3201B Flash
// Read Cycle Time 70 nS minimum
// Chip Enable Access Time 70 ns maximum
// Address Access Time 70 ns max
// Toe 35 ns max
// CE/OE high to inactive output 16 ns
/* Set up EMC Controller */
LPC_EMC->STATICWAITRD0 = DELAYCYCLES(70)+1;
LPC_EMC->STATICWAITPAG0 = DELAYCYCLES(70)+1;
LPC_EMC->CONTROL = 0x01;
LPC_EMC->STATICCONFIG0 = (1UL<<7) | (1UL);
LPC_EMC->STATICWAITOEN0 = DELAYCYCLES(35)+1;
/*Enable Buffer for External Flash*/
LPC_EMC->STATICCONFIG0 |= 1<<19;
}
/* SDRAM refresh time to 16 clock num */
#define EMC_SDRAM_REFRESH(freq,time) \
(((uint64_t)((uint64_t)time * freq)/16000000000ull)+1)
void vEMC_InitSRDRAM(uint32_t u32BaseAddr, uint32_t u32Width, uint32_t u32Size, uint32_t u32DataBus, uint32_t u32ColAddrBits)
{
// adjust the CCU delaye for EMI (default to zero)
//LPC_SCU->EMCCLKDELAY = (CLK0_DELAY | (CLKE0_DELAY << 16));
// Move all clock delays together
LPC_SCU->EMCDELAYCLK = ((CLK0_DELAY)
| (CLK0_DELAY << 4)
| (CLK0_DELAY << 8)
| (CLK0_DELAY << 12));
/* Initialize EMC to interface with SDRAM */
LPC_EMC->CONTROL = 0x00000001; /* Enable the external memory controller */
LPC_EMC->CONFIG = 0;
LPC_EMC->DYNAMICCONFIG0 = ((u32Width << 7) | (u32Size << 9) | (1UL << 12) | (u32DataBus << 14));
LPC_EMC->DYNAMICCONFIG2 = ((u32Width << 7) | (u32Size << 9) | (1UL << 12) | (u32DataBus << 14));
LPC_EMC->DYNAMICRASCAS0 = (3 << 0) | (3 << 8); // aem
LPC_EMC->DYNAMICRASCAS2 = (3 << 0) | (3 << 8); // aem
LPC_EMC->DYNAMICREADCONFIG = EMC_COMMAND_DELAYED_STRATEGY;
LPC_EMC->DYNAMICRP = 1; // calculated from xls sheet
LPC_EMC->DYNAMICRAS = 3;
LPC_EMC->DYNAMICSREX = 5;
LPC_EMC->DYNAMICAPR = 0;
LPC_EMC->DYNAMICDAL = 4;
LPC_EMC->DYNAMICWR = 1;
LPC_EMC->DYNAMICRC = 5;
LPC_EMC->DYNAMICRFC = 5;
LPC_EMC->DYNAMICXSR = 5;
LPC_EMC->DYNAMICRRD = 1;
LPC_EMC->DYNAMICMRD = 1;
LPC_EMC->DYNAMICCONTROL = EMC_CE_ENABLE | EMC_CS_ENABLE | EMC_INIT(EMC_NOP);
emc_WaitMinUS(100);
LPC_EMC->DYNAMICCONTROL = EMC_CE_ENABLE | EMC_CS_ENABLE | EMC_INIT(EMC_PRECHARGE_ALL);
LPC_EMC->DYNAMICREFRESH = 2;
emc_WaitMinUS(100);
LPC_EMC->DYNAMICREFRESH = 50;
LPC_EMC->DYNAMICCONTROL = EMC_CE_ENABLE | EMC_CS_ENABLE | EMC_INIT(EMC_MODE);
if(u32DataBus == 0)
{
/* burst size 8 */
*((volatile uint32_t *)(u32BaseAddr | ((3 | (3 << 4)) << (u32ColAddrBits + 1))));
}
else
{
/* burst size 4 */
*((volatile uint32_t *)(u32BaseAddr | ((2UL | (2UL << 4)) << (u32ColAddrBits + 2))));
}
LPC_EMC->DYNAMICCONTROL = 0; // EMC_CE_ENABLE | EMC_CS_ENABLE;
LPC_EMC->DYNAMICCONFIG0 = ((u32Width << 7) | (u32Size << 9) | (1UL << 12) | (u32DataBus << 14)) | EMC_B_ENABLE;
LPC_EMC->DYNAMICCONFIG1 = ((u32Width << 7) | (u32Size << 9) | (1UL << 12) | (u32DataBus << 14)) | EMC_B_ENABLE;
LPC_EMC->DYNAMICCONFIG2 = ((u32Width << 7) | (u32Size << 9) | (1UL << 12) | (u32DataBus << 14)) | EMC_B_ENABLE;
LPC_EMC->DYNAMICCONFIG3 = ((u32Width << 7) | (u32Size << 9) | (1UL << 12) | (u32DataBus << 14)) | EMC_B_ENABLE;
}

79
Demo/CORTEX_M4F_M0_LPC43xx_Keil/platform/M4_PeripheralLibraryFiles/lpc43xx_emc.h Normal file
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@ -0,0 +1,79 @@
/**********************************************************************
* $Id: lpc43xx_emc.h 8765 2011-12-08 00:51:21Z nxp21346 $ lpc43xx_emc.h 2011-12-07
*//**
* @file lpc43xx_emc.h
* @brief Contains all functions support for Clock Generation and Control
* firmware library on lpc43xx
* @version 1.0
* @date 07. December. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/
#define __CRYSTAL (12000000UL) /* Crystal Oscillator frequency */
#define __PLLMULT (15)
#define __PLLOUTHZ (__CRYSTAL * __PLLMULT)
#define __EMCDIV (2)
#define __EMCHZ (__PLLOUTHZ / __EMCDIV)
void MemoryPinInit(void);
void EMCFlashInit(void);
/* SDRAM Address Base for DYCS0*/
#define SDRAM_BASE_ADDR 0x28000000
#define FLASH_BASE_ADDR 0x1C000000
#define EMC_SDRAM_WIDTH_8_BITS 0
#define EMC_SDRAM_WIDTH_16_BITS 1
#define EMC_SDRAM_WIDTH_32_BITS 2
#define EMC_SDRAM_SIZE_16_MBITS 0
#define EMC_SDRAM_SIZE_64_MBITS 1
#define EMC_SDRAM_SIZE_128_MBITS 2
#define EMC_SDRAM_SIZE_256_MBITS 3
#define EMC_SDRAM_SIZE_512_MBITS 4
#define EMC_SDRAM_DATA_BUS_16_BITS 0
#define EMC_SDRAM_DATA_BUS_32_BITS 1
#define EMC_B_ENABLE (1 << 19)
#define EMC_ENABLE (1 << 0)
#define EMC_CE_ENABLE (1 << 0)
#define EMC_CS_ENABLE (1 << 1)
#define EMC_CLOCK_DELAYED_STRATEGY (0 << 0)
#define EMC_COMMAND_DELAYED_STRATEGY (1 << 0)
#define EMC_COMMAND_DELAYED_STRATEGY2 (2 << 0)
#define EMC_COMMAND_DELAYED_STRATEGY3 (3 << 0)
#define EMC_INIT(i) ((i) << 7)
#define EMC_NORMAL (0)
#define EMC_MODE (1)
#define EMC_PRECHARGE_ALL (2)
#define EMC_NOP (3)
/* The Hitex LPC18xx Evaluation board contains a 64Mb SDRAM with a 16-bit data bus */
#define SDRAM_SIZE_BYTES (1024UL * 1024UL * 8UL)
#define SDRAM_WIDTH EMC_SDRAM_WIDTH_16_BITS
#define SDRAM_SIZE_MBITS EMC_SDRAM_SIZE_64_MBITS
#define SDRAM_DATA_BUS_BITS EMC_SDRAM_DATA_BUS_16_BITS
#define SDRAM_COL_ADDR_BITS 8
#define CLK0_DELAY 0
void vEMC_InitSRDRAM(uint32_t u32BaseAddr, uint32_t u32Width, uint32_t u32Size, uint32_t u32DataBus, uint32_t u32ColAddrBits);
void emc_WaitUS(volatile uint32_t us);
void emc_WaitMS(uint32_t ms);

4
Demo/CORTEX_M4F_M0_LPC43xx_Keil/platform/M4_PeripheralLibraryFiles/lpc43xx_i2c.c
View file

@ -32,7 +32,7 @@
/* Includes ------------------------------------------------------------------- */ /* Includes ------------------------------------------------------------------- */
#include "lpc43xx_i2c.h" #include "lpc43xx_i2c.h"
#include "lpc43xx_cgu.h" #include "lpc43xx_cgu.h"
#include "lpc43xx_scu.h" #include "scu.h"
#define MD_EZI (0x1<<6) #define MD_EZI (0x1<<6)
#define MD_ZI (0x1<<7) #define MD_ZI (0x1<<7)
@ -947,7 +947,7 @@ Status I2C_SlaveTransferData(LPC_I2Cn_Type *I2Cx, I2C_S_SETUP_Type *TransferCfg,
{ {
uint8_t *txdat; uint8_t *txdat;
uint8_t *rxdat; uint8_t *rxdat;
uint32_t CodeStatus; uint32_t CodeStatus = 0;
uint32_t timeout; uint32_t timeout;
int32_t time_en; int32_t time_en;
int32_t tmp; int32_t tmp;

98
Demo/CORTEX_M4F_M0_LPC43xx_Keil/platform/M4_PeripheralLibraryFiles/lpc43xx_scu.h
View file

@ -1,98 +0,0 @@
/**********************************************************************
* $Id$ lpc43xx_scu.h 2011-06-02
*//**
* @file lpc43xx_scu.h
* @brief Contains all macro definitions and function prototypes
* support for SCU firmware library on lpc43xx
* @version 1.0
* @date 02. June. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/
/* Peripheral group ----------------------------------------------------------- */
/** @defgroup SCU SCU (System Control Unit)
* @ingroup LPC4300CMSIS_FwLib_Drivers
* @{
*/
#ifndef __SCU_H
#define __SCU_H
#ifdef __cplusplus
extern "C"
{
#endif
/* Private macros ------------------------------------------------------------- */
/** @defgroup SCT_Private_Macros SCT Private Macros
* @{
*/
/** Port offset definition */
#define PORT_OFFSET 0x80
/** Pin offset definition */
#define PIN_OFFSET 0x04
/* Pin modes */
#define MD_PUP (0x0<<3)
#define MD_BUK (0x1<<3)
#define MD_PLN (0x2<<3)
#define MD_PDN (0x3<<3)
#define MD_EHS (0x1<<5)
#define MD_EZI (0x1<<6)
#define MD_ZI (0x1<<7)
#define MD_EHD0 (0x1<<8)
#define MD_EHD1 (0x1<<8)
#define MD_PLN_FAST (MD_PLN | MD_EZI | MD_ZI | MD_EHS)
// 0xF0
/* Pin function */
#define FUNC0 0x0 /** Function 0 */
#define FUNC1 0x1 /** Function 1 */
#define FUNC2 0x2 /** Function 2 */
#define FUNC3 0x3 /** Function 3 */
#define FUNC4 0x4
#define FUNC5 0x5
#define FUNC6 0x6
#define FUNC7 0x7
/**
* @}
*/
/* Public Functions ----------------------------------------------------------- */
/** @defgroup SCU_Public_Functions SCU Public Functions
* @{
*/
void scu_pinmux(uint8_t port, uint8_t pin, uint8_t mode, uint8_t func);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* end __SCU_H */
/**
* @}
*/
/* --------------------------------- End Of File ------------------------------ */

6
Demo/CORTEX_M4F_M0_LPC43xx_Keil/platform/platform_config.c
View file

@ -22,7 +22,7 @@ void platformInit(void) {
fpuInit(); fpuInit();
clockInit(); /* clockInit(); the clock is set in Hitex_CGU_Init */
vIOInit(); vIOInit();
@ -50,12 +50,12 @@ void vIOInit(void)
#if (PLATFORM == NXP_VALIDATION_BOARD) #if (PLATFORM == NXP_VALIDATION_BOARD)
// P9.2 : GPIO4_14: LD11 (LED) // P9.2 : GPIO4_14: LD11 (LED)
scu_pinmux(0x9 ,2 , PDN_ENABLE, FUNC0); scu_pinmux(0x9 ,2 , PDN_ENABLE, FUNC0);
LPC_GPIO4->DIR |= (1UL << 14); LPC_GPIO_PORT->DIR[4] |= (1UL << 14);
#endif #endif
#if (PLATFORM == HITEX_A2_BOARD) #if (PLATFORM == HITEX_A2_BOARD)
// P9.3 : GPIO4_15 // P9.3 : GPIO4_15
scu_pinmux(0x9 , 3 , PDN_ENABLE, FUNC0); scu_pinmux(0x9 , 3 , PDN_ENABLE, FUNC0);
LPC_GPIO4->DIR |= (1UL << 15); LPC_GPIO_PORT->DIR[4] |= (1UL << 15);
#endif #endif
} }

103
Demo/CORTEX_M4F_M0_LPC43xx_Keil/system/Hitex_Fast_Startup.c Normal file
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@ -0,0 +1,103 @@
/**********************************************************************
* $Id: Hitex_Fast_Startup.c 8763 2011-12-08 00:45:50Z nxp21346 $ lpc43xx_emc.c 2011-12-07
*//**
* @file lpc43xx_emc.c
* @brief Contains all functions support for Clock Generation and Control
* firmware library on lpc43xx
* @version 1.0
* @date 07. December. 2011
* @author NXP MCU SW Application Team
*
* Copyright(C) 2011, NXP Semiconductor
* All rights reserved.
*
***********************************************************************
* Software that is described herein is for illustrative purposes only
* which provides customers with programming information regarding the
* products. This software is supplied "AS IS" without any warranties.
* NXP Semiconductors assumes no responsibility or liability for the
* use of the software, conveys no license or title under any patent,
* copyright, or mask work right to the product. NXP Semiconductors
* reserves the right to make changes in the software without
* notification. NXP Semiconductors also make no representation or
* warranty that such application will be suitable for the specified
* use without further testing or modification.
**********************************************************************/
#include "LPC43xx.h"
#include "lpc43xx_cgu.h"
#include "lpc43xx_emc.h"
#include "spifi_rom_api.h"
void WaitMinUS( volatile uint32_t us, uint32_t SystemClock )
{
us *= (SystemClock / 1000000UL) / 3;
while(us--);
}
void WaitMinMS( uint32_t ms, uint32_t SystemClock )
{
WaitMinUS( ( ms * 1000 ), SystemClock );
}
/* hardware-control routine used by spifi_rom_api.c */
void pullMISO(int high) {
/* undocumented bit 7 included as 1, Aug 2 2011 */
LPC_SCU->SFSP3_6 = high == 0 ? 0xDB /* pull down */
: high == 1 ? 0xC3 /* pull up */
: 0xD3; /* neither */
}
void Hitex_CGU_Init(void)
{
__disable_irq();
MemoryPinInit(); // Make sure EMC is in high-speed pin mode
/* Set the XTAL oscillator frequency to 12MHz*/
CGU_SetXTALOSC(__CRYSTAL);
CGU_EnableEntity(CGU_CLKSRC_XTAL_OSC, ENABLE);
CGU_EntityConnect(CGU_CLKSRC_XTAL_OSC, CGU_BASE_M3);
/* Set PL160M 12*1 = 12 MHz */
CGU_EntityConnect(CGU_CLKSRC_XTAL_OSC, CGU_CLKSRC_PLL1);
CGU_SetPLL1(1);
CGU_EnableEntity(CGU_CLKSRC_PLL1, ENABLE);
/* Run SPIFI from PL160M, /2 */
CGU_EntityConnect(CGU_CLKSRC_PLL1, CGU_CLKSRC_IDIVA);
CGU_EnableEntity(CGU_CLKSRC_IDIVA, ENABLE);
CGU_SetDIV(CGU_CLKSRC_IDIVA, 2);
CGU_EntityConnect(CGU_CLKSRC_IDIVA, CGU_BASE_SPIFI);
CGU_UpdateClock();
LPC_CCU1->CLK_M4_EMCDIV_CFG |= (1<<0) | (1<<5); // Turn on clock / 2
LPC_CREG->CREG6 |= (1<<16); // EMC divided by 2
LPC_CCU1->CLK_M4_EMC_CFG |= (1<<0); // Turn on clock
/* Set PL160M @ 12*9=108 MHz */
CGU_SetPLL1(9);
/* Run base M3 clock from PL160M, no division */
CGU_EntityConnect(CGU_CLKSRC_PLL1, CGU_BASE_M3);
WaitMinMS(10, 108000000UL);
/* Change the clock to 204 MHz */
/* Set PL160M @ 12*15=180 MHz */
CGU_SetPLL1(17);
WaitMinMS(10, 180000000UL);
CGU_UpdateClock();
EMCFlashInit();
vEMC_InitSRDRAM(SDRAM_BASE_ADDR, SDRAM_WIDTH, SDRAM_SIZE_MBITS, SDRAM_DATA_BUS_BITS, SDRAM_COL_ADDR_BITS);
LPC_SCU->SFSP3_3 = 0xF3; /* high drive for SCLK */
/* IO pins */
LPC_SCU->SFSP3_4=LPC_SCU->SFSP3_5=LPC_SCU->SFSP3_6=LPC_SCU->SFSP3_7 = 0xD3;
LPC_SCU->SFSP3_8 = 0x13; /* CS doesn't need feedback */
__enable_irq();
}

35585
Demo/CORTEX_M4F_M0_LPC43xx_Keil/system/LPC43xx.h
View file

File diff suppressed because it is too large Load diff

19
Demo/CORTEX_M4F_M0_LPC43xx_Keil/system/scu.h
View file

@ -25,15 +25,16 @@
#define PIN_OFFSET 0x04 #define PIN_OFFSET 0x04
/* Pin modes */ /* Pin modes */
//#define MD_PUP (0x0<<3) #define MD_PUP (0x0<<3)
//#define MD_BUK (0x1<<3) #define MD_BUK (0x1<<3)
//#define MD_PLN (0x2<<3) #define MD_PLN (0x2<<3)
//#define MD_PDN (0x3<<3) #define MD_PDN (0x3<<3)
//#define MD_EHS (0x1<<5) #define MD_EHS (0x1<<5)
//#define MD_EZI (0x1<<6) #define MD_EZI (0x1<<6)
//#define MD_ZI (0x1<<7) #define MD_ZI (0x1<<7)
//#define MD_EHD0 (0x1<<8) #define MD_EHD0 (0x1<<8)
//#define MD_EHD1 (0x1<<8) #define MD_EHD1 (0x1<<8)
#define MD_PLN_FAST (MD_PLN | MD_EHS | MD_EZI | MD_ZI)
/* Pin modes /* Pin modes
* ========= * =========

36
Demo/CORTEX_M4F_M0_LPC43xx_Keil/system/system_LPC43xx.c
View file

@ -22,11 +22,11 @@
#include <stdint.h> #include <stdint.h>
#if defined CORE_M4 #if defined CORE_M4
#include "LPC43xx.h" /* LPC18xx definitions */ #include "LPC43xx.h"
#endif #endif
#ifdef CORE_M0 #ifdef CORE_M0
#include "LPC43xx_M0.h" /* LPC18xx definitions */ #include "LPC43xx_M0.h"
#endif #endif
#include "scu.h" #include "scu.h"
@ -145,27 +145,6 @@ uint32_t SPARE1Frequency = 0;
*/ */
void SystemInit(void) void SystemInit(void)
{ {
#ifdef OTP
// Set IRC trim if OTP is not programmed.
if( *(uint32_t *)LPC_OTP_CTRL_BASE == 0x00FF ||
*(uint32_t *)(LPC_OTP_CTRL_BASE+4) == 0x0000)
{
LPC_CREG->IRCTRM = IRC_TRIM_VAL;
}
#else
LPC_CREG->IRCTRM = IRC_TRIM_VAL;
#endif
// Set all GPIO as input.
LPC_GPIO0->DIR = 0x0000;
LPC_GPIO1->DIR = 0x0000;
LPC_GPIO2->DIR = 0x0000;
LPC_GPIO3->DIR = 0x0000;
LPC_GPIO4->DIR = 0x0000;
LPC_GPIO5->DIR = 0x0000;
LPC_GPIO6->DIR = 0x0000;
LPC_GPIO7->DIR = 0x0000;
// M4 runs on IRC by default // M4 runs on IRC by default
M4Frequency = IRC_OSC; M4Frequency = IRC_OSC;
XtalFrequency = XTAL_FREQ; XtalFrequency = XTAL_FREQ;
@ -548,14 +527,16 @@ void SetPLLUSB(CLKSRC_Type src_clk, uint8_t enable)
void EnableSourceClk(CLKSRC_Type src_clk) void EnableSourceClk(CLKSRC_Type src_clk)
{ {
uint32_t i=0; uint32_t i=0;
const uint32_t PlainEnable = (0x2 << 3); /* no pull up, no pull down (plain) */
if(src_clk == SRC_OSC32K) if(src_clk == SRC_OSC32K)
{ {
LPC_CREG->CREG0 &= ~((1<<3)|(1<<2)); // Active mode of 32 KHz osc and release reset LPC_CREG->CREG0 &= ~((1<<3)|(1<<2)); // Active mode of 32 KHz osc and release reset
LPC_CREG->CREG0 |= (1<<1)|(1<<0); // Enable 32 kHz & 1 kHz on osc32k LPC_CREG->CREG0 |= (1<<1)|(1<<0); // Enable 32 kHz & 1 kHz on osc32k
} }
if(src_clk == SRC_ENET_RX_CLK)scu_pinmux(0xC ,0 , PLAIN_ENABLE, FUNC3); // enet_rx_clk on PC_0 func 3 if(src_clk == SRC_ENET_RX_CLK)scu_pinmux(0xC ,0 , PlainEnable, FUNC3); // enet_rx_clk on PC_0 func 3
if(src_clk == SRC_ENET_TX_CLK)scu_pinmux(0x1 ,19, PLAIN_ENABLE, FUNC0); // enet_tx_clk on P1_19 func 0 if(src_clk == SRC_ENET_TX_CLK)scu_pinmux(0x1 ,19, PlainEnable, FUNC0); // enet_tx_clk on P1_19 func 0
if(src_clk == SRC_XTAL && (LPC_CGU->XTAL_OSC_CTRL&0x1)) if(src_clk == SRC_XTAL && (LPC_CGU->XTAL_OSC_CTRL&0x1))
{ {
LPC_CGU->XTAL_OSC_CTRL &= ~(1<<0); // Enable Xo50M LPC_CGU->XTAL_OSC_CTRL &= ~(1<<0); // Enable Xo50M
@ -574,14 +555,15 @@ void EnableSourceClk(CLKSRC_Type src_clk)
void DisableSourceClk(CLKSRC_Type src_clk) void DisableSourceClk(CLKSRC_Type src_clk)
{ {
uint32_t i=0; uint32_t i=0;
const uint32_t PlainEnable = (0x2 << 3); /* no pull up, no pull down (plain) */
if(src_clk == SRC_OSC32K) if(src_clk == SRC_OSC32K)
{ {
LPC_CREG->CREG0 &= ~((1<<1)|(1<<0)); // Disable 32 kHz & 1 kHz on osc32k LPC_CREG->CREG0 &= ~((1<<1)|(1<<0)); // Disable 32 kHz & 1 kHz on osc32k
LPC_CREG->CREG0 |= ((1<<3)|(1<<2)); // osc32k in power down and in reset mode LPC_CREG->CREG0 |= ((1<<3)|(1<<2)); // osc32k in power down and in reset mode
} }
if(src_clk == SRC_ENET_RX_CLK)scu_pinmux(0xC ,0 , PLAIN_ENABLE, FUNC0); // nc on PC_0 func 0 if(src_clk == SRC_ENET_RX_CLK)scu_pinmux(0xC ,0 , PlainEnable, FUNC0); // nc on PC_0 func 0
if(src_clk == SRC_ENET_TX_CLK)scu_pinmux(0x1 ,19, PLAIN_ENABLE, FUNC2); // nc on P1_19 func 2 if(src_clk == SRC_ENET_TX_CLK)scu_pinmux(0x1 ,19, PlainEnable, FUNC2); // nc on P1_19 func 2
if(src_clk == SRC_XTAL) if(src_clk == SRC_XTAL)
{ {
LPC_CGU->XTAL_OSC_CTRL = (1<<0); // Disable Xo50M LPC_CGU->XTAL_OSC_CTRL = (1<<0); // Disable Xo50M