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The LPC43xx fast start files are now included.
This commit is contained in:
Richard Barry
parent
a0eb27a69e
commit
cc06119b86
16 changed files with 34611 additions and 1705 deletions
103
Demo/CORTEX_M4F_M0_LPC43xx_Keil/system/Hitex_Fast_Startup.c
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103
Demo/CORTEX_M4F_M0_LPC43xx_Keil/system/Hitex_Fast_Startup.c
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@ -0,0 +1,103 @@
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/**********************************************************************
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* $Id: Hitex_Fast_Startup.c 8763 2011-12-08 00:45:50Z nxp21346 $ lpc43xx_emc.c 2011-12-07
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*//**
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* @file lpc43xx_emc.c
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* @brief Contains all functions support for Clock Generation and Control
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* firmware library on lpc43xx
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* @version 1.0
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* @date 07. December. 2011
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* @author NXP MCU SW Application Team
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*
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* Copyright(C) 2011, NXP Semiconductor
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* All rights reserved.
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*
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***********************************************************************
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* Software that is described herein is for illustrative purposes only
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* which provides customers with programming information regarding the
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* products. This software is supplied "AS IS" without any warranties.
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* NXP Semiconductors assumes no responsibility or liability for the
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* use of the software, conveys no license or title under any patent,
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* copyright, or mask work right to the product. NXP Semiconductors
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* reserves the right to make changes in the software without
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* notification. NXP Semiconductors also make no representation or
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* warranty that such application will be suitable for the specified
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* use without further testing or modification.
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**********************************************************************/
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#include "LPC43xx.h"
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#include "lpc43xx_cgu.h"
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#include "lpc43xx_emc.h"
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#include "spifi_rom_api.h"
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void WaitMinUS( volatile uint32_t us, uint32_t SystemClock )
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{
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us *= (SystemClock / 1000000UL) / 3;
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while(us--);
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}
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void WaitMinMS( uint32_t ms, uint32_t SystemClock )
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{
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WaitMinUS( ( ms * 1000 ), SystemClock );
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}
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/* hardware-control routine used by spifi_rom_api.c */
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void pullMISO(int high) {
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/* undocumented bit 7 included as 1, Aug 2 2011 */
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LPC_SCU->SFSP3_6 = high == 0 ? 0xDB /* pull down */
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: high == 1 ? 0xC3 /* pull up */
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: 0xD3; /* neither */
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}
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void Hitex_CGU_Init(void)
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{
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__disable_irq();
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MemoryPinInit(); // Make sure EMC is in high-speed pin mode
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/* Set the XTAL oscillator frequency to 12MHz*/
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CGU_SetXTALOSC(__CRYSTAL);
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CGU_EnableEntity(CGU_CLKSRC_XTAL_OSC, ENABLE);
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CGU_EntityConnect(CGU_CLKSRC_XTAL_OSC, CGU_BASE_M3);
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/* Set PL160M 12*1 = 12 MHz */
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CGU_EntityConnect(CGU_CLKSRC_XTAL_OSC, CGU_CLKSRC_PLL1);
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CGU_SetPLL1(1);
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CGU_EnableEntity(CGU_CLKSRC_PLL1, ENABLE);
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/* Run SPIFI from PL160M, /2 */
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CGU_EntityConnect(CGU_CLKSRC_PLL1, CGU_CLKSRC_IDIVA);
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CGU_EnableEntity(CGU_CLKSRC_IDIVA, ENABLE);
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CGU_SetDIV(CGU_CLKSRC_IDIVA, 2);
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CGU_EntityConnect(CGU_CLKSRC_IDIVA, CGU_BASE_SPIFI);
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CGU_UpdateClock();
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LPC_CCU1->CLK_M4_EMCDIV_CFG |= (1<<0) | (1<<5); // Turn on clock / 2
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LPC_CREG->CREG6 |= (1<<16); // EMC divided by 2
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LPC_CCU1->CLK_M4_EMC_CFG |= (1<<0); // Turn on clock
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/* Set PL160M @ 12*9=108 MHz */
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CGU_SetPLL1(9);
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/* Run base M3 clock from PL160M, no division */
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CGU_EntityConnect(CGU_CLKSRC_PLL1, CGU_BASE_M3);
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WaitMinMS(10, 108000000UL);
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/* Change the clock to 204 MHz */
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/* Set PL160M @ 12*15=180 MHz */
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CGU_SetPLL1(17);
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WaitMinMS(10, 180000000UL);
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CGU_UpdateClock();
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EMCFlashInit();
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vEMC_InitSRDRAM(SDRAM_BASE_ADDR, SDRAM_WIDTH, SDRAM_SIZE_MBITS, SDRAM_DATA_BUS_BITS, SDRAM_COL_ADDR_BITS);
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LPC_SCU->SFSP3_3 = 0xF3; /* high drive for SCLK */
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/* IO pins */
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LPC_SCU->SFSP3_4=LPC_SCU->SFSP3_5=LPC_SCU->SFSP3_6=LPC_SCU->SFSP3_7 = 0xD3;
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LPC_SCU->SFSP3_8 = 0x13; /* CS doesn't need feedback */
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__enable_irq();
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}
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File diff suppressed because it is too large
Load diff
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@ -25,15 +25,16 @@
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#define PIN_OFFSET 0x04
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/* Pin modes */
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//#define MD_PUP (0x0<<3)
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//#define MD_BUK (0x1<<3)
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//#define MD_PLN (0x2<<3)
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//#define MD_PDN (0x3<<3)
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//#define MD_EHS (0x1<<5)
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//#define MD_EZI (0x1<<6)
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//#define MD_ZI (0x1<<7)
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//#define MD_EHD0 (0x1<<8)
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//#define MD_EHD1 (0x1<<8)
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#define MD_PUP (0x0<<3)
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#define MD_BUK (0x1<<3)
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#define MD_PLN (0x2<<3)
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#define MD_PDN (0x3<<3)
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#define MD_EHS (0x1<<5)
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#define MD_EZI (0x1<<6)
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#define MD_ZI (0x1<<7)
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#define MD_EHD0 (0x1<<8)
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#define MD_EHD1 (0x1<<8)
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#define MD_PLN_FAST (MD_PLN | MD_EHS | MD_EZI | MD_ZI)
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/* Pin modes
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* =========
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@ -22,14 +22,14 @@
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#include <stdint.h>
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#if defined CORE_M4
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#include "LPC43xx.h" /* LPC18xx definitions */
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#include "LPC43xx.h"
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#endif
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#ifdef CORE_M0
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#include "LPC43xx_M0.h" /* LPC18xx definitions */
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#include "LPC43xx_M0.h"
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#endif
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#include "scu.h"
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#include "scu.h"
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#include "type.h"
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#include "config.h"
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@ -145,27 +145,6 @@ uint32_t SPARE1Frequency = 0;
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*/
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void SystemInit(void)
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{
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#ifdef OTP
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// Set IRC trim if OTP is not programmed.
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if( *(uint32_t *)LPC_OTP_CTRL_BASE == 0x00FF ||
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*(uint32_t *)(LPC_OTP_CTRL_BASE+4) == 0x0000)
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{
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LPC_CREG->IRCTRM = IRC_TRIM_VAL;
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}
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#else
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LPC_CREG->IRCTRM = IRC_TRIM_VAL;
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#endif
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// Set all GPIO as input.
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LPC_GPIO0->DIR = 0x0000;
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LPC_GPIO1->DIR = 0x0000;
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LPC_GPIO2->DIR = 0x0000;
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LPC_GPIO3->DIR = 0x0000;
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LPC_GPIO4->DIR = 0x0000;
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LPC_GPIO5->DIR = 0x0000;
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LPC_GPIO6->DIR = 0x0000;
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LPC_GPIO7->DIR = 0x0000;
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// M4 runs on IRC by default
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M4Frequency = IRC_OSC;
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XtalFrequency = XTAL_FREQ;
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@ -548,14 +527,16 @@ void SetPLLUSB(CLKSRC_Type src_clk, uint8_t enable)
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void EnableSourceClk(CLKSRC_Type src_clk)
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{
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uint32_t i=0;
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const uint32_t PlainEnable = (0x2 << 3); /* no pull up, no pull down (plain) */
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if(src_clk == SRC_OSC32K)
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{
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LPC_CREG->CREG0 &= ~((1<<3)|(1<<2)); // Active mode of 32 KHz osc and release reset
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LPC_CREG->CREG0 |= (1<<1)|(1<<0); // Enable 32 kHz & 1 kHz on osc32k
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}
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if(src_clk == SRC_ENET_RX_CLK)scu_pinmux(0xC ,0 , PLAIN_ENABLE, FUNC3); // enet_rx_clk on PC_0 func 3
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if(src_clk == SRC_ENET_TX_CLK)scu_pinmux(0x1 ,19, PLAIN_ENABLE, FUNC0); // enet_tx_clk on P1_19 func 0
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if(src_clk == SRC_ENET_RX_CLK)scu_pinmux(0xC ,0 , PlainEnable, FUNC3); // enet_rx_clk on PC_0 func 3
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if(src_clk == SRC_ENET_TX_CLK)scu_pinmux(0x1 ,19, PlainEnable, FUNC0); // enet_tx_clk on P1_19 func 0
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if(src_clk == SRC_XTAL && (LPC_CGU->XTAL_OSC_CTRL&0x1))
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{
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LPC_CGU->XTAL_OSC_CTRL &= ~(1<<0); // Enable Xo50M
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@ -574,14 +555,15 @@ void EnableSourceClk(CLKSRC_Type src_clk)
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void DisableSourceClk(CLKSRC_Type src_clk)
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{
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uint32_t i=0;
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const uint32_t PlainEnable = (0x2 << 3); /* no pull up, no pull down (plain) */
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if(src_clk == SRC_OSC32K)
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{
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LPC_CREG->CREG0 &= ~((1<<1)|(1<<0)); // Disable 32 kHz & 1 kHz on osc32k
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LPC_CREG->CREG0 |= ((1<<3)|(1<<2)); // osc32k in power down and in reset mode
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}
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if(src_clk == SRC_ENET_RX_CLK)scu_pinmux(0xC ,0 , PLAIN_ENABLE, FUNC0); // nc on PC_0 func 0
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if(src_clk == SRC_ENET_TX_CLK)scu_pinmux(0x1 ,19, PLAIN_ENABLE, FUNC2); // nc on P1_19 func 2
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if(src_clk == SRC_ENET_RX_CLK)scu_pinmux(0xC ,0 , PlainEnable, FUNC0); // nc on PC_0 func 0
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if(src_clk == SRC_ENET_TX_CLK)scu_pinmux(0x1 ,19, PlainEnable, FUNC2); // nc on P1_19 func 2
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if(src_clk == SRC_XTAL)
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{
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LPC_CGU->XTAL_OSC_CTRL = (1<<0); // Disable Xo50M
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