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Sync with a:FR (#75)
* AFR sync * AFR sync: CBMC * AFR sync: CBMC: remove .bak files * AFR sync: CBMC: more cleanup * Corrected CBMC proofs * Corrected CBMC patches * Corrected CBMC patches-1 * Corrected CBMC patches-2 * remove .bak files (3) Co-authored-by: Yuhui Zheng <10982575+yuhui-zheng@users.noreply.github.com>
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Aniruddha Kanhere
GitHub
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commit
cb7edd2323
99 changed files with 6475 additions and 4241 deletions
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@ -34,60 +34,60 @@
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#ifndef ipconfigPHY_LS_HIGH_CHECK_TIME_MS
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/* Check if the LinkStatus in the PHY is still high after 15 seconds of not
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receiving packets. */
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#define ipconfigPHY_LS_HIGH_CHECK_TIME_MS 15000uL
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#define ipconfigPHY_LS_HIGH_CHECK_TIME_MS 15000UL
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#endif
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#ifndef ipconfigPHY_LS_LOW_CHECK_TIME_MS
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/* Check if the LinkStatus in the PHY is still low every second. */
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#define ipconfigPHY_LS_LOW_CHECK_TIME_MS 1000uL
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#define ipconfigPHY_LS_LOW_CHECK_TIME_MS 1000UL
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#endif
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/* As the following 3 macro's are OK in most situations, and so they're not
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included in 'FreeRTOSIPConfigDefaults.h'.
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Users can change their values in the project's 'FreeRTOSIPConfig.h'. */
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#ifndef phyPHY_MAX_RESET_TIME_MS
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#define phyPHY_MAX_RESET_TIME_MS 1000uL
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#define phyPHY_MAX_RESET_TIME_MS 1000UL
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#endif
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#ifndef phyPHY_MAX_NEGOTIATE_TIME_MS
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#define phyPHY_MAX_NEGOTIATE_TIME_MS 3000uL
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#define phyPHY_MAX_NEGOTIATE_TIME_MS 3000UL
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#endif
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#ifndef phySHORT_DELAY_MS
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#define phySHORT_DELAY_MS 50uL
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#define phySHORT_DELAY_MS 50UL
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#endif
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/* Naming and numbering of basic PHY registers. */
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#define phyREG_00_BMCR 0x00u /* Basic Mode Control Register. */
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#define phyREG_01_BMSR 0x01u /* Basic Mode Status Register. */
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#define phyREG_02_PHYSID1 0x02u /* PHYS ID 1 */
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#define phyREG_03_PHYSID2 0x03u /* PHYS ID 2 */
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#define phyREG_04_ADVERTISE 0x04u /* Advertisement control reg */
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#define phyREG_00_BMCR 0x00U /* Basic Mode Control Register. */
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#define phyREG_01_BMSR 0x01U /* Basic Mode Status Register. */
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#define phyREG_02_PHYSID1 0x02U /* PHYS ID 1 */
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#define phyREG_03_PHYSID2 0x03U /* PHYS ID 2 */
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#define phyREG_04_ADVERTISE 0x04U /* Advertisement control reg */
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/* Naming and numbering of extended PHY registers. */
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#define PHYREG_10_PHYSTS 0x10u /* 16 PHY status register Offset */
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#define phyREG_19_PHYCR 0x19u /* 25 RW PHY Control Register */
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#define phyREG_1F_PHYSPCS 0x1Fu /* 31 RW PHY Special Control Status */
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#define PHYREG_10_PHYSTS 0x10U /* 16 PHY status register Offset */
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#define phyREG_19_PHYCR 0x19U /* 25 RW PHY Control Register */
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#define phyREG_1F_PHYSPCS 0x1FU /* 31 RW PHY Special Control Status */
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/* Bit fields for 'phyREG_00_BMCR', the 'Basic Mode Control Register'. */
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#define phyBMCR_FULL_DUPLEX 0x0100u /* Full duplex. */
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#define phyBMCR_AN_RESTART 0x0200u /* Auto negotiation restart. */
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#define phyBMCR_ISOLATE 0x0400u /* 1 = Isolates 0 = Normal operation. */
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#define phyBMCR_AN_ENABLE 0x1000u /* Enable auto negotiation. */
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#define phyBMCR_SPEED_100 0x2000u /* Select 100Mbps. */
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#define phyBMCR_RESET 0x8000u /* Reset the PHY. */
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#define phyBMCR_FULL_DUPLEX 0x0100U /* Full duplex. */
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#define phyBMCR_AN_RESTART 0x0200U /* Auto negotiation restart. */
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#define phyBMCR_ISOLATE 0x0400U /* 1 = Isolates 0 = Normal operation. */
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#define phyBMCR_AN_ENABLE 0x1000U /* Enable auto negotiation. */
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#define phyBMCR_SPEED_100 0x2000U /* Select 100Mbps. */
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#define phyBMCR_RESET 0x8000U /* Reset the PHY. */
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/* Bit fields for 'phyREG_19_PHYCR', the 'PHY Control Register'. */
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#define PHYCR_MDIX_EN 0x8000u /* Enable Auto MDIX. */
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#define PHYCR_MDIX_FORCE 0x4000u /* Force MDIX crossed. */
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#define PHYCR_MDIX_EN 0x8000U /* Enable Auto MDIX. */
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#define PHYCR_MDIX_FORCE 0x4000U /* Force MDIX crossed. */
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#define phyBMSR_AN_COMPLETE 0x0020u /* Auto-Negotiation process completed */
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#define phyBMSR_AN_COMPLETE 0x0020U /* Auto-Negotiation process completed */
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#define phyBMSR_LINK_STATUS 0x0004u
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#define phyBMSR_LINK_STATUS 0x0004U
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#define phyPHYSTS_LINK_STATUS 0x0001u /* PHY Link mask */
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#define phyPHYSTS_SPEED_STATUS 0x0002u /* PHY Speed mask */
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#define phyPHYSTS_DUPLEX_STATUS 0x0004u /* PHY Duplex mask */
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#define phyPHYSTS_LINK_STATUS 0x0001U /* PHY Link mask */
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#define phyPHYSTS_SPEED_STATUS 0x0002U /* PHY Speed mask */
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#define phyPHYSTS_DUPLEX_STATUS 0x0004U /* PHY Duplex mask */
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/* Bit fields for 'phyREG_1F_PHYSPCS
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001 = 10BASE-T half-duplex
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@ -95,20 +95,20 @@ Users can change their values in the project's 'FreeRTOSIPConfig.h'. */
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010 = 100BASE-TX half-duplex
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110 = 100BASE-TX full-duplex
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*/
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#define phyPHYSPCS_SPEED_MASK 0x000Cu
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#define phyPHYSPCS_SPEED_10 0x0004u
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#define phyPHYSPCS_FULL_DUPLEX 0x0010u
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#define phyPHYSPCS_SPEED_MASK 0x000CU
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#define phyPHYSPCS_SPEED_10 0x0004U
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#define phyPHYSPCS_FULL_DUPLEX 0x0010U
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/*
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* Description of all capabilities that can be advertised to
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* the peer (usually a switch or router).
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*/
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#define phyADVERTISE_CSMA 0x0001u /* Supports IEEE 802.3u: Fast Ethernet at 100 Mbit/s */
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#define phyADVERTISE_10HALF 0x0020u /* Try for 10mbps half-duplex. */
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#define phyADVERTISE_10FULL 0x0040u /* Try for 10mbps full-duplex. */
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#define phyADVERTISE_100HALF 0x0080u /* Try for 100mbps half-duplex. */
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#define phyADVERTISE_100FULL 0x0100u /* Try for 100mbps full-duplex. */
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#define phyADVERTISE_CSMA 0x0001U /* Supports IEEE 802.3u: Fast Ethernet at 100 Mbit/s */
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#define phyADVERTISE_10HALF 0x0020U /* Try for 10mbps half-duplex. */
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#define phyADVERTISE_10FULL 0x0040U /* Try for 10mbps full-duplex. */
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#define phyADVERTISE_100HALF 0x0080U /* Try for 100mbps half-duplex. */
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#define phyADVERTISE_100FULL 0x0100U /* Try for 100mbps full-duplex. */
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#define phyADVERTISE_ALL ( phyADVERTISE_10HALF | phyADVERTISE_10FULL | \
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phyADVERTISE_100HALF | phyADVERTISE_100FULL | \
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@ -167,7 +167,7 @@ BaseType_t xResult;
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/* Initialise the struct and assign a PHY-read and -write function. */
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void vPhyInitialise( EthernetPhy_t *pxPhyObject, xApplicationPhyReadHook_t fnPhyRead, xApplicationPhyWriteHook_t fnPhyWrite )
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{
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memset( ( void * )pxPhyObject, '\0', sizeof( *pxPhyObject ) );
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memset( ( void * )pxPhyObject, 0, sizeof( *pxPhyObject ) );
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pxPhyObject->fnPhyRead = fnPhyRead;
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pxPhyObject->fnPhyWrite = fnPhyWrite;
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@ -187,7 +187,7 @@ BaseType_t xPhyAddress;
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pxPhyObject->fnPhyRead( xPhyAddress, phyREG_03_PHYSID2, &ulLowerID );
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/* A valid PHY id can not be all zeros or all ones. */
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if( ( ulLowerID != ( uint16_t )~0u ) && ( ulLowerID != ( uint16_t )0u ) )
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if( ( ulLowerID != ( uint16_t ) ~0U ) && ( ulLowerID != ( uint16_t ) 0U ) )
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{
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uint32_t ulUpperID;
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uint32_t ulPhyID;
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@ -225,7 +225,7 @@ TimeOut_t xTimer;
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BaseType_t xPhyIndex;
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/* A bit-mask of PHY ports that are ready. */
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ulDoneMask = 0ul;
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ulDoneMask = 0UL;
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/* Set the RESET bits high. */
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for( xPhyIndex = 0; xPhyIndex < pxPhyObject->xPortCount; xPhyIndex++ )
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@ -251,7 +251,7 @@ BaseType_t xPhyIndex;
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if( ( ulConfig & phyBMCR_RESET ) == 0 )
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{
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FreeRTOS_printf( ( "xPhyReset: phyBMCR_RESET %d ready\n", (int)xPhyIndex ) );
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ulDoneMask |= ( 1ul << xPhyIndex );
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ulDoneMask |= ( 1UL << xPhyIndex );
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}
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}
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if( ulDoneMask == ulPhyMask )
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@ -270,7 +270,7 @@ BaseType_t xPhyIndex;
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/* Clear the reset bits. */
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for( xPhyIndex = 0; xPhyIndex < pxPhyObject->xPortCount; xPhyIndex++ )
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{
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if( ( ulDoneMask & ( 1ul << xPhyIndex ) ) == 0uL )
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if( ( ulDoneMask & ( 1UL << xPhyIndex ) ) == 0UL )
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{
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BaseType_t xPhyAddress = pxPhyObject->ucPhyIndexes[ xPhyIndex ];
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@ -454,9 +454,9 @@ with ulPhyMask. */
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BaseType_t xPhyFixedValue( EthernetPhy_t *pxPhyObject, uint32_t ulPhyMask )
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{
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BaseType_t xPhyIndex;
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uint32_t ulValue, ulBitMask = ( uint32_t )1u;
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uint32_t ulValue, ulBitMask = ( uint32_t )1U;
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ulValue = ( uint32_t )0u;
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ulValue = ( uint32_t ) 0U;
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if( pxPhyObject->xPhyPreferences.ucDuplex == PHY_DUPLEX_FULL )
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{
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@ -491,7 +491,7 @@ uint32_t ulPHYLinkStatus, ulRegValue;
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TickType_t xRemainingTime;
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TimeOut_t xTimer;
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if( ulPhyMask == ( uint32_t )0u )
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if( ulPhyMask == ( uint32_t ) 0U )
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{
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return 0;
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}
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@ -512,7 +512,7 @@ TimeOut_t xTimer;
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/* Wait until the auto-negotiation will be completed */
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for( ;; )
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{
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ulBitMask = ( uint32_t )1u;
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ulBitMask = ( uint32_t ) 1U;
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for( xPhyIndex = 0; xPhyIndex < ( uint32_t ) pxPhyObject->xPortCount; xPhyIndex++, ulBitMask <<= 1 )
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{
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if( ( ulPhyMask & ulBitMask ) != 0lu )
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@ -541,16 +541,16 @@ TimeOut_t xTimer;
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vTaskDelay( pdMS_TO_TICKS( phySHORT_DELAY_MS ) );
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}
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if( ulDoneMask != ( uint32_t)0u )
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if( ulDoneMask != ( uint32_t) 0U )
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{
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ulBitMask = ( uint32_t )1u;
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ulBitMask = ( uint32_t ) 1U;
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pxPhyObject->ulLinkStatusMask &= ~( ulDoneMask );
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for( xPhyIndex = 0; xPhyIndex < ( uint32_t ) pxPhyObject->xPortCount; xPhyIndex++, ulBitMask <<= 1 )
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{
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BaseType_t xPhyAddress = pxPhyObject->ucPhyIndexes[ xPhyIndex ];
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uint32_t ulPhyID = pxPhyObject->ulPhyIDs[ xPhyIndex ];
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if( ( ulDoneMask & ulBitMask ) == ( uint32_t )0u )
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if( ( ulDoneMask & ulBitMask ) == ( uint32_t ) 0U )
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{
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continue;
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}
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@ -632,7 +632,7 @@ TimeOut_t xTimer;
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( ulRegValue & phyPHYSTS_DUPLEX_STATUS ) ? "full" : "half",
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( ulRegValue & phyPHYSTS_SPEED_STATUS ) ? 10 : 100,
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( ( ulPHYLinkStatus |= phyBMSR_LINK_STATUS ) != 0) ? "high" : "low" ) );
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if( ( ulRegValue & phyPHYSTS_DUPLEX_STATUS ) != ( uint32_t )0u )
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if( ( ulRegValue & phyPHYSTS_DUPLEX_STATUS ) != ( uint32_t ) 0U )
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{
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pxPhyObject->xPhyProperties.ucDuplex = PHY_DUPLEX_FULL;
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}
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@ -650,7 +650,7 @@ TimeOut_t xTimer;
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pxPhyObject->xPhyProperties.ucSpeed = PHY_SPEED_100;
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}
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}
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} /* if( ulDoneMask != ( uint32_t)0u ) */
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} /* if( ulDoneMask != ( uint32_t) 0U ) */
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return 0;
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}
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@ -658,7 +658,7 @@ TimeOut_t xTimer;
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BaseType_t xPhyCheckLinkStatus( EthernetPhy_t *pxPhyObject, BaseType_t xHadReception )
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{
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uint32_t ulStatus, ulBitMask = 1u;
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uint32_t ulStatus, ulBitMask = 1U;
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BaseType_t xPhyIndex;
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BaseType_t xNeedCheck = pdFALSE;
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@ -670,7 +670,7 @@ BaseType_t xNeedCheck = pdFALSE;
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pxPhyObject->xLinkStatusRemaining = pdMS_TO_TICKS( ipconfigPHY_LS_HIGH_CHECK_TIME_MS );
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for( xPhyIndex = 0; xPhyIndex < pxPhyObject->xPortCount; xPhyIndex++, ulBitMask <<= 1 )
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{
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if( ( pxPhyObject->ulLinkStatusMask & ulBitMask ) == 0ul )
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if( ( pxPhyObject->ulLinkStatusMask & ulBitMask ) == 0UL )
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{
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pxPhyObject->ulLinkStatusMask |= ulBitMask;
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FreeRTOS_printf( ( "xPhyCheckLinkStatus: PHY LS now %02lX\n", pxPhyObject->ulLinkStatusMask ) );
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@ -705,7 +705,7 @@ BaseType_t xNeedCheck = pdFALSE;
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}
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}
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vTaskSetTimeOutState( &( pxPhyObject->xLinkStatusTimer ) );
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if( ( pxPhyObject->ulLinkStatusMask & phyBMSR_LINK_STATUS ) != 0 )
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if( ( pxPhyObject->ulLinkStatusMask & ( ulBitMask >> 1 ) ) != 0 )
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{
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/* The link status is high, so don't poll the PHY too often. */
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pxPhyObject->xLinkStatusRemaining = pdMS_TO_TICKS( ipconfigPHY_LS_HIGH_CHECK_TIME_MS );
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