mirror of
https://github.com/FreeRTOS/FreeRTOS-Kernel.git
synced 2025-12-09 05:05:17 -05:00
Respond to additional review feedback. Use periods at end of briefs. Remove same line brief. Add a check back in, change some file names, slight code formatting change.
This commit is contained in:
Soren Ptak
parent
11beb7156e
commit
ca37a2cfc7
4 changed files with 437 additions and 460 deletions
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@ -45,7 +45,7 @@ extern "C" {
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#define portMPU_TOTAL_REGIONS ( 16UL )
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#else
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#error "Set configTOTAL_MPU_REGIONS to the number of MPU regions in FreeRTOSConfig.h"
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#endif
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#endif /* configTOTAL_MPU_REGIONS */
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/** On the ArmV7-R Architecture the Operating mode of the Processor is set using
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* the Current Program Status and Control Register (CPSR) Mode bits, [4:0]
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@ -58,67 +58,86 @@ extern "C" {
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*
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* */
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/** @brief CPSR Mode bit field value for User Mode
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/**
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* @brief CPSR Mode bit field value for User Mode.
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* @ingroup Port Privilege
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*/
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#define USER_MODE 0x10U
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/** @brief CPSR Mode bit field value for Fast Interrupt Handler (FIQ) Mode
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/**
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* @brief CPSR Mode bit field value for Fast Interrupt Handler (FIQ) Mode.
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* @ingroup Port Privilege
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*/
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#define FIQ_MODE 0x11U
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/** @brief CPSR Mode bit field value for Interrupt Handler (IRQ) Mode
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/**
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* @brief CPSR Mode bit field value for Interrupt Handler (IRQ) Mode.
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* @ingroup Port Privilege
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*/
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#define IRQ_MODE 0x12U
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/** @brief CPSR Mode bit field value for Supervisor (SVC) Mode
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/**
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* @brief CPSR Mode bit field value for Supervisor (SVC) Mode.
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* @ingroup Port Privilege
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*/
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#define SVC_MODE 0x13U
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/** @brief CPSR Mode bit field value for Monitor (MON) Mode
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/**
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* @brief CPSR Mode bit field value for Monitor (MON) Mode.
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* @ingroup Port Privilege
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*/
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#define MON_MODE 0x16U
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/** @brief CPSR Mode bit field value for Abort (ABT) Mode
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/**
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* @brief CPSR Mode bit field value for Abort (ABT) Mode.
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* @ingroup Port Privilege
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*/
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#define ABT_MODE 0x17U
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/** @brief CPSR Mode bit field value for Hypervisor (HYP) Mode
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/**
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* @brief CPSR Mode bit field value for Hypervisor (HYP) Mode.
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* @ingroup Port Privilege
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*/
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#define HYP_MODE 0x1AU
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/** @brief CPSR Mode bit field value for Undefined (UND) Mode
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/**
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* @brief CPSR Mode bit field value for Undefined (UND) Mode.
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* @ingroup Port Privilege
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*/
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#define UND_MODE 0x1BU
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/** @brief CPSR Mode bit field value for System (SYS) Mode
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/**
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* @brief CPSR Mode bit field value for System (SYS) Mode.
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* @ingroup Port Privilege
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*/
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#define SYS_MODE 0x1FU
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/** @brief Mark that a Task Stack has padding values added
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/**
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* @brief Used to mark if a task should be created as a privileged task.
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*
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* @ingroup Task Context
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* @ingroup MPU Control
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*
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* @note This is done by performing a bitwise OR of this value and the task priority.
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* For example, to create a privileged task at priority 2 the uxPriority
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* parameter should be set to ( 2 | portPRIVILEGE_BIT ).
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*/
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#define portSTACK_FRAME_HAS_PADDING_FLAG ( 1UL << 0UL )
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#define portPRIVILEGE_BIT ( 0x80000000UL )
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/** @brief Flag uses to mark that a FreeRTOS Task is privileged
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/**
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* @brief Flag uses to mark that a FreeRTOS Task is privileged.
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* @ingroup Port Privilege
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*/
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#define portTASK_IS_PRIVILEGED_FLAG ( 1UL << 1UL )
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/** @brief SVC Number to use when requesting a context swap.
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/**
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* @brief SVC Number to use when requesting a context swap.
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* @ingroup Scheduler
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*/
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#define portSVC_YIELD 0x0100
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/** @brief SVC Number to use when exiting a FreeRTOS System Call
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/**
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* @brief SVC Number to use when exiting a FreeRTOS System Call.
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* @ingroup MPU Control
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*/
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#define portSVC_SYSTEM_CALL_EXIT 0x0104
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@ -131,7 +150,7 @@ extern "C" {
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*
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*/
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/* MPU Sub Region region */
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/* MPU Sub Region settings */
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#define portMPU_SUBREGION_0_DISABLE ( 0x1UL << 8UL )
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#define portMPU_SUBREGION_1_DISABLE ( 0x1UL << 9UL )
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#define portMPU_SUBREGION_2_DISABLE ( 0x1UL << 10UL )
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@ -184,126 +203,25 @@ extern "C" {
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#define portMPU_SIZE_2GB ( 0x1EUL << 1UL )
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#define portMPU_SIZE_4GB ( 0x1FUL << 1UL )
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/** @brief Used to mark if a task should be created as a privileged task.
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*
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* @ingroup Task Context
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* @ingroup MPU Control
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*
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* @note This is done by performing a bitwise OR of this value and the task priority.
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* For example, to create a privileged task at priority 2 the uxPriority
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* parameter should be set to ( 2 | portPRIVILEGE_BIT ).
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*/
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#define portPRIVILEGE_BIT ( 0x80000000UL )
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/** @brief MPU Setting for a Strongly Ordered Memory Region
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*
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* @ingroup MPU Control
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*
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*/
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/* MPU Device Memory Types */
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#define portMPU_REGION_STRONGLY_ORDERED ( 0x00UL )
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/** @brief MPU Setting for a Strongly Ordered Memory Region
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*
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* @ingroup MPU Control
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*
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*/
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#define portMPU_REGION_DEVICE ( 0x01UL )
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/** @brief MPU Setting for a Strongly Ordered Memory Region
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*
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* @ingroup MPU Control
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*
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*/
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#define portMPU_REGION_CACHEABLE_BUFFERABLE ( 0x03UL )
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/** @brief MPU Setting for a Strongly Ordered Memory Region
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*
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* @ingroup MPU Control
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*
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*/
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#define portMPU_REGION_EXECUTE_NEVER ( 0x01UL << 12UL )
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/** @brief MPU Setting for a Strongly Ordered and Shareable Memory Region
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*
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* @ingroup MPU Control
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*
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*/
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#define portMPU_STRONGLYORDERED_SHAREABLE ( 0x0000UL )
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/** @brief MPU Setting for a Device and Shareable Memory Region
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*
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* @ingroup MPU Control
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*
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*/
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#define portMPU_DEVICE_SHAREABLE ( 0x0001UL )
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/** @brief MPU Setting for a Device and Non-Shareable Memory Region
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*
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* @ingroup MPU Control
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*
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*/
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#define portMPU_DEVICE_NONSHAREABLE ( 0x0010UL )
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/** @brief MPU Setting for a Normal Outer & Inner Write-Through, No Write Allocate & Non
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* Shared
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*
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* @ingroup MPU Control
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*
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*/
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#define portMPU_NORMAL_OIWTNOWA_NONSHARED ( 0x0002UL )
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/** @brief MPU Setting for a Normal Outer & Inner Write-Back, No Write Allocate & Non
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* Shared
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*
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* @ingroup MPU Control
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*
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*/
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#define portMPU_NORMAL_OIWBNOWA_NONSHARED ( 0x0003UL )
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/** @brief MPU Setting for a Normal Outer & Inner Write-Through, no Write Allocate &
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* Shared
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*
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* @ingroup MPU Control
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*
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*/
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#define portMPU_NORMAL_OIWTNOWA_SHARED ( 0x0006UL )
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/** @brief MPU Setting for a Normal Outer & Inner Write-back, no Write Allocate & Shared
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*
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* @ingroup MPU Control
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*
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*/
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#define portMPU_NORMAL_OIWBNOWA_SHARED ( 0x0007UL )
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/** @brief MPU Setting for a Normal Outer & Inner Non-Cacheable & Non Shared
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*
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* @ingroup MPU Control
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*
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*/
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#define portMPU_NORMAL_OINC_NONSHARED ( 0x0008UL )
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/** @brief MPU Setting for a Normal Outer & Inner Write-Back, Write Allocate & Non Shared
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*
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* @ingroup MPU Control
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*
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*/
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#define portMPU_NORMAL_OIWBWA_NONSHARED ( 0x000BUL )
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/** @brief MPU Setting for a Normal Outer & Inner Non-Cacheable & Shared
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*
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* @ingroup MPU Control
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*
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*/
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#define portMPU_NORMAL_OINC_SHARED ( 0x000CUL )
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/** @brief MPU Setting for a Normal Outer & Inner Write-Back, Write Allocate & Shared
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*
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* @ingroup MPU Control
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*
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*/
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#define portMPU_NORMAL_OIWBWA_SHARED ( 0x000FUL )
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/** @brief MPU_CTRL value for: No Access and No Execute
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/**
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* @brief MPU_CTRL value for: No Access and No Execute
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*
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* @ingroup MPU Control
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*
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@ -313,7 +231,8 @@ extern "C" {
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*/
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#define portMPU_PRIV_NA_USER_NA_NOEXEC ( 0x1000UL )
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/** @brief MPU_CTRL value for Privileged Read and Exec
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/**
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* @brief MPU_CTRL value for Privileged Read and Exec
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*
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* @ingroup MPU Control
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*
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@ -323,7 +242,8 @@ extern "C" {
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*/
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#define portMPU_PRIV_RO_USER_NA_EXEC ( 0x0500UL )
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/** @brief MPU_CTRL value for Privileged Read, Write, and Exec
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/**
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* @brief MPU_CTRL value for Privileged Read, Write, and Exec
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*
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* @ingroup MPU Control
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*
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@ -333,7 +253,8 @@ extern "C" {
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*/
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#define portMPU_PRIV_RW_USER_NA_EXEC ( 0x0100UL )
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/** @brief MPU_CTRL value for Read Only and Execute
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/**
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* @brief MPU_CTRL value for Read Only and Execute
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*
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* @ingroup MPU Control
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*
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@ -343,7 +264,8 @@ extern "C" {
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* */
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#define portMPU_PRIV_RO_USER_RO_EXEC ( 0x0600UL )
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/** @brief MPU_CTRL value for: Read, Execute, and Privileged Write
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/**
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* @brief MPU_CTRL value for: Read, Execute, and Privileged Write
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*
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* @ingroup MPU Control
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*
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@ -353,7 +275,8 @@ extern "C" {
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*/
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#define portMPU_PRIV_RW_USER_RO_EXEC ( 0x0200UL )
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/** @brief MPU_CTRL value for: Read, Write, and Execute
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/**
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* @brief MPU_CTRL value for: Read, Write, and Execute
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*
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* @ingroup MPU Control
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*
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@ -363,7 +286,8 @@ extern "C" {
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*/
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#define portMPU_PRIV_RW_USER_RW_EXEC ( 0x0300UL )
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/** @brief MPU_CTRL value for: Privileged Read, Write Only, no Execute
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/**
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* @brief MPU_CTRL value for: Privileged Read, Write Only, no Execute
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*
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* @ingroup MPU Control
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*
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@ -373,7 +297,8 @@ extern "C" {
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*/
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#define portMPU_PRIV_RW_USER_NA_NOEXEC ( 0x1100UL )
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/** @brief MPU_CTRL value for: All Read, Privileged Write, no Execute
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/**
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* @brief MPU_CTRL value for: All Read, Privileged Write, no Execute
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*
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* @ingroup MPU Control
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*
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@ -383,7 +308,8 @@ extern "C" {
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*/
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#define portMPU_PRIV_RW_USER_RO_NOEXEC ( 0x1200UL )
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/** @brief MPU_CTRL value for: Read, Write, no Execute
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/**
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* @brief MPU_CTRL value for: Read, Write, no Execute
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*
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* @ingroup MPU Control
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*
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@ -393,7 +319,8 @@ extern "C" {
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*/
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#define portMPU_PRIV_RW_USER_RW_NOEXEC ( 0x1300UL )
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/** @brief MPU_CTRL value for: Privileged Read Only, No Execute
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/**
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* @brief MPU_CTRL value for: Privileged Read Only, No Execute
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*
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* @ingroup MPU Control
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*
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@ -403,7 +330,8 @@ extern "C" {
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*/
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#define portMPU_PRIV_RO_USER_NA_NOEXEC ( 0x1500UL )
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/** @brief MPU_CTRL value for: Read Only, No Execute
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/**
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* @brief MPU_CTRL value for: Read Only, No Execute
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*
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* @ingroup MPU Control
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*
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@ -413,14 +341,12 @@ extern "C" {
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*/
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#define portMPU_PRIV_RO_USER_RO_NOEXEC ( 0x1600UL )
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/** @brief MPU_CTRL value to enable an MPU Region
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/**
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* @brief MPU_CTRL value to enable an MPU Region
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* @ingroup MPU Control
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*/
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#define portMPU_REGION_ENABLE ( 0x01UL )
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/** @brief The lowest priority interrupt that is usable by the system */
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#define portLOWEST_USABLE_INTERRUPT_PRIORITY ( portLOWEST_INTERRUPT_PRIORITY - 1UL )
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/** This following section is used to create the proper size for the ulContext array.
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* This array is where all registers related to a task's context are saved.
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* The size of this array will depend on if the system is using an integrated
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@ -452,17 +378,15 @@ extern "C" {
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*
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*/
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/** @brief The length in ulContext for the General Purpose Registers in bytes
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* @note There are 13 GPRs, R0-R12 each is 32 bits, so 13 registers * 4 Bytes each
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/**
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* @brief The length in ulContext for the General Purpose Registers in bytes.
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* @note There are 13 GPRs, R0-R12, the SP, and the LR. Each are 32 bits,
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* which leads to the 15 registers * 4 in length.
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*/
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#define portGPR_LENGTH ( 15U * 4U )
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#define portREGISTER_LENGTH ( 15U * 4U )
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/** @brief The length in ulContext for all the registers in a context
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* @note There are the 13 GPRs, the Stack Pointer, and the Link Register
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*/
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#define portREGISTER_CONTEXT_LENGTH ( ( 16 * 4U ) )
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/** If you KNOW that your system will not utilize the FPU in any capacity
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/**
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* If you KNOW that your system will not utilize the FPU in any capacity
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* you can set portENABLE_FPU to 0, which will reduce the per-task RAM usage
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* by ( 32 FPRs + 32 bit FPSCR ) * 4 bytes per register = 132, or 0x84, Bytes Per Task
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* BE CAREFUL DISABLING THIS: Certain APIs will try and optimize themselves
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@ -474,7 +398,8 @@ extern "C" {
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#define configENABLE_FPU 1
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#endif /* configENABLE_FPU */
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/** @brief Mark if the Floating Point Registers will be saved.
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/**
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* @brief Mark if the Floating Point Registers will be saved.
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* @ingroup Task Context
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* @note When using the FPU, we must save additional registers into the task's context
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* These consist of the Floating Point Status and Control Register (FPSCR),
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@ -483,7 +408,8 @@ extern "C" {
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#define portENABLE_FPU configENABLE_FPU
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#if( portENABLE_FPU == 1 )
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/** @brief Length of a Task's Register Context when using an FPU.
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/**
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* @brief Length of a Task's Register Context when using an FPU.
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* @ingroup Task Context
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* @note Task Context which is stored in ulContext in order, consists of:
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* ulContext[ 0 ]: Critical Nesting Count: ulCriticalNesting
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@ -497,7 +423,8 @@ extern "C" {
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*/
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#define MAX_CONTEXT_SIZE 51U
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#else
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/** @brief Length of a Task's Register Context when not using an FPU.
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/**
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* @brief Length of a Task's Register Context when not using an FPU.
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* @ingroup Task Context
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* @note Task Context which is stored in ulContext in order, consists of:
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* ulContext[ 0 ]: Critical Nesting Count: ulCriticalNesting
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@ -510,7 +437,8 @@ extern "C" {
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#define MAX_CONTEXT_SIZE 18U
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#endif /* MAX_CONTEXT_SIZE */
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/** @brief Numerical offset from the start of a TCB to xSystemCallStackInfo
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/**
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* @brief Numerical offset from the start of a TCB to xSystemCallStackInfo.
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* @note In the exception handlers it is necessary to load this variable from the TCB.
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* This provides an easy way for the exception handlers to get this structure.
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* The numerical value here should be equal to:
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