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Use saved mstatus for FPU/VPU state determination (#1330)
According to the RISC-V Privileged Architecture Specification (20211203), writing Initial or Clean to the FS field of mstatus may result in the FS value getting set to Dirty in some implementations. This means we cannot rely on reading back the same FS value after writing to mstatus. Previously, the context restore code would: 1. Write an FS value to mstatus 2. Read mstatus again at a later point 3. Use the read FS value to determine FPU status This change updates the context restore code to use the mstatus value from the saved context instead of re-reading mstatus after writing to it. This required chaning the location of the mstatus slot in the context. Fixes: https://github.com/FreeRTOS/FreeRTOS-Kernel/issues/1327 Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
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3 changed files with 35 additions and 34 deletions
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@ -193,8 +193,8 @@ definitions. */
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* portTASK_RETURN_ADDRESS
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* [FPU registers (when enabled/available) go here]
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* [VPU registers (when enabled/available) go here]
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* [chip specific registers go here]
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* mstatus
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* [chip specific registers go here]
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* pxCode
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*/
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pxPortInitialiseStack:
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@ -212,14 +212,6 @@ pxPortInitialiseStack:
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load_x t0, xTaskReturnAddress
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store_x t0, 0(a0) /* Return address onto the stack. */
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addi t0, x0, portasmADDITIONAL_CONTEXT_SIZE /* The number of chip specific additional registers. */
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chip_specific_stack_frame: /* First add any chip specific registers to the stack frame being created. */
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beq t0, x0, 1f /* No more chip specific registers to save. */
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addi a0, a0, -portWORD_SIZE /* Make space for chip specific register. */
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store_x x0, 0(a0) /* Give the chip specific register an initial value of zero. */
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addi t0, t0, -1 /* Decrement the count of chip specific registers remaining. */
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j chip_specific_stack_frame /* Until no more chip specific registers. */
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1:
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csrr t0, mstatus /* Obtain current mstatus value. */
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andi t0, t0, ~0x8 /* Ensure interrupts are disabled when the stack is restored within an ISR. Required when a task is created after the scheduler has been started, otherwise interrupts would be disabled anyway. */
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addi t1, x0, 0x188 /* Generate the value 0x1880, which are the MPIE=1 and MPP=M_Mode in mstatus. */
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@ -245,6 +237,15 @@ chip_specific_stack_frame: /* First add any chip specific registers
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addi a0, a0, -portWORD_SIZE
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store_x t0, 0(a0) /* mstatus onto the stack. */
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addi t0, x0, portasmADDITIONAL_CONTEXT_SIZE /* The number of chip specific additional registers. */
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chip_specific_stack_frame: /* First add any chip specific registers to the stack frame being created. */
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beq t0, x0, 1f /* No more chip specific registers to save. */
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addi a0, a0, -portWORD_SIZE /* Make space for chip specific register. */
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store_x x0, 0(a0) /* Give the chip specific register an initial value of zero. */
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addi t0, t0, -1 /* Decrement the count of chip specific registers remaining. */
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j chip_specific_stack_frame /* Until no more chip specific registers. */
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1:
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addi a0, a0, -portWORD_SIZE
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store_x a1, 0(a0) /* mret value (pxCode parameter) onto the stack. */
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ret
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@ -256,12 +257,12 @@ xPortStartFirstTask:
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load_x x1, 0( sp ) /* Note for starting the scheduler the exception return address is used as the function return address. */
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portasmRESTORE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_chip_specific_extensions.h to restore any registers unique to the RISC-V implementation. */
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load_x x5, 1 * portWORD_SIZE( sp ) /* Initial mstatus into x5 (t0). */
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addi x5, x5, 0x08 /* Set MIE bit so the first task starts with interrupts enabled - required as returns with ret not eret. */
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csrw mstatus, x5 /* Interrupts enabled from here! */
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portasmRESTORE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_chip_specific_extensions.h to restore any registers unique to the RISC-V implementation. */
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load_x x7, 5 * portWORD_SIZE( sp ) /* t2 */
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load_x x8, 6 * portWORD_SIZE( sp ) /* s0/fp */
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load_x x9, 7 * portWORD_SIZE( sp ) /* s1 */
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