mirror of
https://github.com/FreeRTOS/FreeRTOS-Kernel.git
synced 2025-04-19 21:11:57 -04:00
Work in progress on the Cortus port.
This commit is contained in:
parent
a671be77bf
commit
c848059d5f
|
@ -71,7 +71,7 @@
|
|||
/*
|
||||
* Perform any hardware configuration necessary to generate the tick interrupt.
|
||||
*/
|
||||
static void prvSetupTickInterrupt( void );
|
||||
static void prvSetupTimerInterrupt( void );
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Variables used to hold interrupt and critical nesting depths, with variables
|
||||
|
@ -123,8 +123,8 @@ portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE * pxTopOfStack, pdTASK_COD
|
|||
|
||||
portBASE_TYPE xPortStartScheduler( void )
|
||||
{
|
||||
/* Set-up the Tick Interrupt. */
|
||||
prvSetupTickInterrupt();
|
||||
/* Set-up the timer interrupt. */
|
||||
prvSetupTimerInterrupt();
|
||||
|
||||
/* Enable the TRAP yield. */
|
||||
irq[ portIRQ_TRAP_YIELD ].ien = 1;
|
||||
|
@ -137,7 +137,7 @@ portBASE_TYPE xPortStartScheduler( void )
|
|||
/* Restore calleree saved registers. */
|
||||
portRESTORE_CONTEXT_REDUCED();
|
||||
|
||||
/* Mimic an ISR epiplogue to start the task executing. */
|
||||
/* Mimic an ISR epilogue to start the task executing. */
|
||||
asm __volatile__( \
|
||||
"mov r1, r14 \n" \
|
||||
"ldd r6, [r1]+0x20 \n" \
|
||||
|
@ -155,7 +155,7 @@ portBASE_TYPE xPortStartScheduler( void )
|
|||
}
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
static void prvSetupTickInterrupt( void )
|
||||
static void prvSetupTimerInterrupt( void )
|
||||
{
|
||||
/* Enable timer interrupts */
|
||||
counter1->reload = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1;
|
||||
|
|
|
@ -114,6 +114,20 @@ extern volatile unsigned portBASE_TYPE uxInterruptNestingCount;
|
|||
#define portYIELD() asm __volatile__( " trap #%0 "::"i"(portIRQ_TRAP_YIELD):"memory")
|
||||
/*---------------------------------------------------------------------------*/
|
||||
|
||||
extern void vTaskEnterCritical( void );
|
||||
extern void vTaskExitCritical( void );
|
||||
#define portENTER_CRITICAL() vTaskEnterCritical()
|
||||
#define portEXIT_CRITICAL() vTaskExitCritical()
|
||||
/*---------------------------------------------------------------------------*/
|
||||
|
||||
/* Critical section management. */
|
||||
#define portDISABLE_INTERRUPTS() ic->cpl = ( portSYSTEM_INTERRUPT_PRIORITY_LEVEL + 1 )
|
||||
#define portENABLE_INTERRUPTS() ic->cpl = portKERNEL_INTERRUPT_PRIORITY_LEVEL
|
||||
|
||||
#define portSET_INTERRUPT_MASK_FROM_ISR() ic->cpl; portDISABLE_INTERRUPTS()
|
||||
#define portRESTORE_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) ic->cpl = uxSavedInterruptStatus
|
||||
/*---------------------------------------------------------------------------*/
|
||||
|
||||
#define portYIELD_FROM_ISR() \
|
||||
{ \
|
||||
asm __volatile__( \
|
||||
|
@ -132,43 +146,13 @@ extern volatile unsigned portBASE_TYPE uxInterruptNestingCount;
|
|||
:"i"(portSYSTEM_INTERRUPT_PRIORITY_LEVEL+1) \
|
||||
:"r2","r3"); \
|
||||
}
|
||||
/*---------------------------------------------------------------------------*/
|
||||
|
||||
extern void vTaskEnterCritical( void );
|
||||
extern void vTaskExitCritical( void );
|
||||
#define portENTER_CRITICAL() vTaskEnterCritical()
|
||||
#define portEXIT_CRITICAL() vTaskExitCritical()
|
||||
/*---------------------------------------------------------------------------*/
|
||||
|
||||
/* Critical section management. */
|
||||
#define portDISABLE_INTERRUPTS() \
|
||||
{ /*ic->cpl = ( portSYSTEM_INTERRUPT_PRIORITY_LEVEL + 1 );*/ \
|
||||
asm __volatile__( \
|
||||
" movhi r2, #16384 \n" \
|
||||
" mov r3, #%0 \n" \
|
||||
" stb r3, [r2]+2" \
|
||||
: \
|
||||
:"i"(portSYSTEM_INTERRUPT_PRIORITY_LEVEL+1) \
|
||||
:"r2", "r3" ); \
|
||||
}
|
||||
/*---------------------------------------------------------------------------*/
|
||||
|
||||
#define portENABLE_INTERRUPTS() \
|
||||
{ /*ic->cpl = portKERNEL_INTERRUPT_PRIORITY_LEVEL;*/ \
|
||||
asm __volatile__( \
|
||||
" movhi r2, #16384 \n" \
|
||||
" mov r3, #%0 \n" \
|
||||
" stb r3, [r2]+2" \
|
||||
: \
|
||||
:"i"(portKERNEL_INTERRUPT_PRIORITY_LEVEL) \
|
||||
:"r2", "r3" ); \
|
||||
}
|
||||
/*---------------------------------------------------------------------------*/
|
||||
|
||||
#define portSAVE_CONTEXT_REDUCED() \
|
||||
{ \
|
||||
asm __volatile__( \
|
||||
/* "sub r1, #0x28" */ \
|
||||
/* "sub r1, #0x28" */ /* Prologue generated by the compiler. */ \
|
||||
/* "stq r4, [r1]+0x8" */ \
|
||||
/* "mov r6, psr" */ \
|
||||
/* "mov r7, rtt" */ \
|
||||
|
@ -221,7 +205,7 @@ extern void vTaskExitCritical( void );
|
|||
"ldq r8, [r1] \n" \
|
||||
"add r1, #0x1c \n" \
|
||||
"mov r14, r1 \n" \
|
||||
/* "mov r1, r14" */ \
|
||||
/* "mov r1, r14" */ /* Epilogue generated by the compiler. */ \
|
||||
/* "ldd r6, [r1]+0x20" */ \
|
||||
/* "mov psr, r6" */ \
|
||||
/* "mov rtt, r7" */ \
|
||||
|
|
Loading…
Reference in a new issue