mirror of
https://github.com/FreeRTOS/FreeRTOS-Kernel.git
synced 2025-08-19 09:38:32 -04:00
Added back in the Coldfire MCF52233 demo with makefile, not yet including the Eclipse project.
This commit is contained in:
Richard Barry
parent
4e8383be43
commit
c5991e5f68
60 changed files with 11950 additions and 0 deletions
86
Demo/ColdFire_MCF52233_Eclipse/RTOSDemo/MCF5223x/MCF52235.h
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86
Demo/ColdFire_MCF52233_Eclipse/RTOSDemo/MCF5223x/MCF52235.h
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/* Coldfire C Header File
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* Copyright Freescale Semiconductor Inc
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* All rights reserved.
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*
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* 2007/03/19 Revision: 0.91
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*/
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#ifndef __MCF52235_H__
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#define __MCF52235_H__
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//#include "common.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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typedef unsigned char uint8; /* 8 bits */
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typedef unsigned short int uint16; /* 16 bits */
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typedef unsigned long int uint32; /* 32 bits */
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typedef signed char int8; /* 8 bits */
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typedef signed short int int16; /* 16 bits */
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typedef signed long int int32; /* 32 bits */
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typedef volatile uint8 vuint8; /* 8 bits */
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typedef volatile uint16 vuint16; /* 16 bits */
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typedef volatile uint32 vuint32; /* 32 bits */
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#ifdef THESE_ARE_CODEWARRIOR_DEFINITIONS
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#pragma define_section system ".system" far_absolute RW
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/***
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* MCF52235 Derivative Memory map definitions from linker command files:
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* __IPSBAR, __RAMBAR, __RAMBAR_SIZE, __FLASHBAR, __FLASHBAR_SIZE linker
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* symbols must be defined in the linker command file.
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*/
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extern __declspec(system) uint8 __IPSBAR[];
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extern __declspec(system) uint8 __RAMBAR[];
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extern __declspec(system) uint8 __RAMBAR_SIZE[];
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extern __declspec(system) uint8 __FLASHBAR[];
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extern __declspec(system) uint8 __FLASHBAR_SIZE[];
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#endif
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#define __IPSBAR ( ( uint8 * ) 0x40000000 )
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#define __RAMBAR ( ( uint8 * ) 0x20000000 )
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#define IPSBAR_ADDRESS (uint32)__IPSBAR
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#define RAMBAR_ADDRESS (uint32)__RAMBAR
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#define RAMBAR_SIZE (uint32)__RAMBAR_SIZE
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#define FLASHBAR_ADDRESS (uint32)__FLASHBAR
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#define FLASHBAR_SIZE (uint32)__FLASHBAR_SIZE
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#include "MCF52235_SCM.h"
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#include "MCF52235_DMA.h"
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#include "MCF52235_UART.h"
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#include "MCF52235_I2C.h"
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#include "MCF52235_QSPI.h"
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#include "MCF52235_RTC.h"
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#include "MCF52235_DTIM.h"
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#include "MCF52235_INTC.h"
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#include "MCF52235_GIACR.h"
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#include "MCF52235_FEC.h"
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#include "MCF52235_GPIO.h"
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#include "MCF52235_PAD.h"
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#include "MCF52235_RCM.h"
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#include "MCF52235_CCM.h"
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#include "MCF52235_PMM.h"
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#include "MCF52235_CLOCK.h"
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#include "MCF52235_EPORT.h"
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#include "MCF52235_PIT.h"
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#include "MCF52235_ADC.h"
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#include "MCF52235_GPTA.h"
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#include "MCF52235_PWM.h"
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#include "MCF52235_FlexCAN.h"
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#include "MCF52235_CFM.h"
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#include "MCF52235_EPHY.h"
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#include "MCF52235_RNGA.h"
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#ifdef __cplusplus
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}
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#endif
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#endif /* __MCF52235_H__ */
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193
Demo/ColdFire_MCF52233_Eclipse/RTOSDemo/MCF5223x/MCF52235_ADC.h
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193
Demo/ColdFire_MCF52233_Eclipse/RTOSDemo/MCF5223x/MCF52235_ADC.h
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/* Coldfire C Header File
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* Copyright Freescale Semiconductor Inc
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* All rights reserved.
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*
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* 2007/03/19 Revision: 0.91
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*/
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#ifndef __MCF52235_ADC_H__
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#define __MCF52235_ADC_H__
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/*********************************************************************
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*
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* Analog-to-Digital Converter (ADC)
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*
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*********************************************************************/
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/* Register read/write macros */
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#define MCF_ADC_CTRL1 (*(vuint16*)(&__IPSBAR[0x190000]))
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#define MCF_ADC_CTRL2 (*(vuint16*)(&__IPSBAR[0x190002]))
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#define MCF_ADC_ADZCC (*(vuint16*)(&__IPSBAR[0x190004]))
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#define MCF_ADC_ADLST1 (*(vuint16*)(&__IPSBAR[0x190006]))
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#define MCF_ADC_ADLST2 (*(vuint16*)(&__IPSBAR[0x190008]))
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#define MCF_ADC_ADSDIS (*(vuint16*)(&__IPSBAR[0x19000A]))
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#define MCF_ADC_ADSTAT (*(vuint16*)(&__IPSBAR[0x19000C]))
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#define MCF_ADC_ADLSTAT (*(vuint16*)(&__IPSBAR[0x19000E]))
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#define MCF_ADC_ADZCSTAT (*(vuint16*)(&__IPSBAR[0x190010]))
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#define MCF_ADC_ADRSLT0 (*(vuint16*)(&__IPSBAR[0x190012]))
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#define MCF_ADC_ADRSLT1 (*(vuint16*)(&__IPSBAR[0x190014]))
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#define MCF_ADC_ADRSLT2 (*(vuint16*)(&__IPSBAR[0x190016]))
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#define MCF_ADC_ADRSLT3 (*(vuint16*)(&__IPSBAR[0x190018]))
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#define MCF_ADC_ADRSLT4 (*(vuint16*)(&__IPSBAR[0x19001A]))
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#define MCF_ADC_ADRSLT5 (*(vuint16*)(&__IPSBAR[0x19001C]))
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#define MCF_ADC_ADRSLT6 (*(vuint16*)(&__IPSBAR[0x19001E]))
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#define MCF_ADC_ADRSLT7 (*(vuint16*)(&__IPSBAR[0x190020]))
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#define MCF_ADC_ADLLMT0 (*(vuint16*)(&__IPSBAR[0x190022]))
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#define MCF_ADC_ADLLMT1 (*(vuint16*)(&__IPSBAR[0x190024]))
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#define MCF_ADC_ADLLMT2 (*(vuint16*)(&__IPSBAR[0x190026]))
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#define MCF_ADC_ADLLMT3 (*(vuint16*)(&__IPSBAR[0x190028]))
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#define MCF_ADC_ADLLMT4 (*(vuint16*)(&__IPSBAR[0x19002A]))
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#define MCF_ADC_ADLLMT5 (*(vuint16*)(&__IPSBAR[0x19002C]))
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#define MCF_ADC_ADLLMT6 (*(vuint16*)(&__IPSBAR[0x19002E]))
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#define MCF_ADC_ADLLMT7 (*(vuint16*)(&__IPSBAR[0x190030]))
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#define MCF_ADC_ADHLMT0 (*(vuint16*)(&__IPSBAR[0x190032]))
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#define MCF_ADC_ADHLMT1 (*(vuint16*)(&__IPSBAR[0x190034]))
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#define MCF_ADC_ADHLMT2 (*(vuint16*)(&__IPSBAR[0x190036]))
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#define MCF_ADC_ADHLMT3 (*(vuint16*)(&__IPSBAR[0x190038]))
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#define MCF_ADC_ADHLMT4 (*(vuint16*)(&__IPSBAR[0x19003A]))
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#define MCF_ADC_ADHLMT5 (*(vuint16*)(&__IPSBAR[0x19003C]))
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#define MCF_ADC_ADHLMT6 (*(vuint16*)(&__IPSBAR[0x19003E]))
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#define MCF_ADC_ADHLMT7 (*(vuint16*)(&__IPSBAR[0x190040]))
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#define MCF_ADC_ADOFS0 (*(vuint16*)(&__IPSBAR[0x190042]))
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#define MCF_ADC_ADOFS1 (*(vuint16*)(&__IPSBAR[0x190044]))
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#define MCF_ADC_ADOFS2 (*(vuint16*)(&__IPSBAR[0x190046]))
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#define MCF_ADC_ADOFS3 (*(vuint16*)(&__IPSBAR[0x190048]))
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#define MCF_ADC_ADOFS4 (*(vuint16*)(&__IPSBAR[0x19004A]))
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#define MCF_ADC_ADOFS5 (*(vuint16*)(&__IPSBAR[0x19004C]))
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#define MCF_ADC_ADOFS6 (*(vuint16*)(&__IPSBAR[0x19004E]))
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#define MCF_ADC_ADOFS7 (*(vuint16*)(&__IPSBAR[0x190050]))
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#define MCF_ADC_POWER (*(vuint16*)(&__IPSBAR[0x190052]))
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#define MCF_ADC_CAL (*(vuint16*)(&__IPSBAR[0x190054]))
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#define MCF_ADC_ADRSLT(x) (*(vuint16*)(&__IPSBAR[0x190012 + ((x)*0x2)]))
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#define MCF_ADC_ADLLMT(x) (*(vuint16*)(&__IPSBAR[0x190022 + ((x)*0x2)]))
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#define MCF_ADC_ADHLMT(x) (*(vuint16*)(&__IPSBAR[0x190032 + ((x)*0x2)]))
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#define MCF_ADC_ADOFS(x) (*(vuint16*)(&__IPSBAR[0x190042 + ((x)*0x2)]))
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/* Bit definitions and macros for MCF_ADC_CTRL1 */
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#define MCF_ADC_CTRL1_SMODE(x) (((x)&0x7)<<0)
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#define MCF_ADC_CTRL1_CHNCFG(x) (((x)&0xF)<<0x4)
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#define MCF_ADC_CTRL1_HLMTIE (0x100)
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#define MCF_ADC_CTRL1_LLMTIE (0x200)
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#define MCF_ADC_CTRL1_ZCIE (0x400)
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#define MCF_ADC_CTRL1_EOSIE0 (0x800)
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#define MCF_ADC_CTRL1_SYNC0 (0x1000)
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#define MCF_ADC_CTRL1_START0 (0x2000)
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#define MCF_ADC_CTRL1_STOP0 (0x4000)
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/* Bit definitions and macros for MCF_ADC_CTRL2 */
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#define MCF_ADC_CTRL2_DIV(x) (((x)&0x1F)<<0)
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#define MCF_ADC_CTRL2_SIMULT (0x20)
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#define MCF_ADC_CTRL2_EOSIE1 (0x800)
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#define MCF_ADC_CTRL2_SYNC1 (0x1000)
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#define MCF_ADC_CTRL2_START1 (0x2000)
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#define MCF_ADC_CTRL2_STOP1 (0x4000)
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/* Bit definitions and macros for MCF_ADC_ADZCC */
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#define MCF_ADC_ADZCC_ZCE0(x) (((x)&0x3)<<0)
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#define MCF_ADC_ADZCC_ZCE1(x) (((x)&0x3)<<0x2)
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#define MCF_ADC_ADZCC_ZCE2(x) (((x)&0x3)<<0x4)
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#define MCF_ADC_ADZCC_ZCE3(x) (((x)&0x3)<<0x6)
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#define MCF_ADC_ADZCC_ZCE4(x) (((x)&0x3)<<0x8)
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#define MCF_ADC_ADZCC_ZCE5(x) (((x)&0x3)<<0xA)
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#define MCF_ADC_ADZCC_ZCE6(x) (((x)&0x3)<<0xC)
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#define MCF_ADC_ADZCC_ZCE7(x) (((x)&0x3)<<0xE)
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/* Bit definitions and macros for MCF_ADC_ADLST1 */
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#define MCF_ADC_ADLST1_SAMPLE0(x) (((x)&0x7)<<0)
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#define MCF_ADC_ADLST1_SAMPLE1(x) (((x)&0x7)<<0x4)
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#define MCF_ADC_ADLST1_SAMPLE2(x) (((x)&0x7)<<0x8)
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#define MCF_ADC_ADLST1_SAMPLE3(x) (((x)&0x7)<<0xC)
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/* Bit definitions and macros for MCF_ADC_ADLST2 */
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#define MCF_ADC_ADLST2_SAMPLE4(x) (((x)&0x7)<<0)
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#define MCF_ADC_ADLST2_SAMPLE5(x) (((x)&0x7)<<0x4)
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#define MCF_ADC_ADLST2_SAMPLE6(x) (((x)&0x7)<<0x8)
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#define MCF_ADC_ADLST2_SAMPLE7(x) (((x)&0x7)<<0xC)
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/* Bit definitions and macros for MCF_ADC_ADSDIS */
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#define MCF_ADC_ADSDIS_DS0 (0x1)
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#define MCF_ADC_ADSDIS_DS1 (0x2)
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#define MCF_ADC_ADSDIS_DS2 (0x4)
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#define MCF_ADC_ADSDIS_DS3 (0x8)
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#define MCF_ADC_ADSDIS_DS4 (0x10)
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#define MCF_ADC_ADSDIS_DS5 (0x20)
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#define MCF_ADC_ADSDIS_DS6 (0x40)
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#define MCF_ADC_ADSDIS_DS7 (0x80)
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/* Bit definitions and macros for MCF_ADC_ADSTAT */
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#define MCF_ADC_ADSTAT_RDY0 (0x1)
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#define MCF_ADC_ADSTAT_RDY1 (0x2)
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#define MCF_ADC_ADSTAT_RDY2 (0x4)
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#define MCF_ADC_ADSTAT_RDY3 (0x8)
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#define MCF_ADC_ADSTAT_RDY4 (0x10)
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#define MCF_ADC_ADSTAT_RDY5 (0x20)
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#define MCF_ADC_ADSTAT_RDY6 (0x40)
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#define MCF_ADC_ADSTAT_RDY7 (0x80)
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#define MCF_ADC_ADSTAT_HLMTI (0x100)
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#define MCF_ADC_ADSTAT_LLMTI (0x200)
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#define MCF_ADC_ADSTAT_ZCI (0x400)
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#define MCF_ADC_ADSTAT_EOSI0 (0x800)
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#define MCF_ADC_ADSTAT_EOSI1 (0x1000)
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#define MCF_ADC_ADSTAT_CIP1 (0x4000)
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#define MCF_ADC_ADSTAT_CIP0 (0x8000)
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/* Bit definitions and macros for MCF_ADC_ADLSTAT */
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#define MCF_ADC_ADLSTAT_LLS0 (0x1)
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#define MCF_ADC_ADLSTAT_LLS1 (0x2)
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#define MCF_ADC_ADLSTAT_LLS2 (0x4)
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#define MCF_ADC_ADLSTAT_LLS3 (0x8)
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#define MCF_ADC_ADLSTAT_LLS4 (0x10)
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#define MCF_ADC_ADLSTAT_LLS5 (0x20)
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#define MCF_ADC_ADLSTAT_LLS6 (0x40)
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#define MCF_ADC_ADLSTAT_LLS7 (0x80)
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#define MCF_ADC_ADLSTAT_HLS0 (0x100)
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#define MCF_ADC_ADLSTAT_HLS1 (0x200)
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#define MCF_ADC_ADLSTAT_HLS2 (0x400)
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#define MCF_ADC_ADLSTAT_HLS3 (0x800)
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#define MCF_ADC_ADLSTAT_HLS4 (0x1000)
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#define MCF_ADC_ADLSTAT_HLS5 (0x2000)
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#define MCF_ADC_ADLSTAT_HLS6 (0x4000)
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#define MCF_ADC_ADLSTAT_HLS7 (0x8000)
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/* Bit definitions and macros for MCF_ADC_ADZCSTAT */
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#define MCF_ADC_ADZCSTAT_ZCS0 (0x1)
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#define MCF_ADC_ADZCSTAT_ZCS1 (0x2)
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#define MCF_ADC_ADZCSTAT_ZCS2 (0x4)
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#define MCF_ADC_ADZCSTAT_ZCS3 (0x8)
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#define MCF_ADC_ADZCSTAT_ZCS4 (0x10)
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#define MCF_ADC_ADZCSTAT_ZCS5 (0x20)
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#define MCF_ADC_ADZCSTAT_ZCS6 (0x40)
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#define MCF_ADC_ADZCSTAT_ZCS7 (0x80)
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/* Bit definitions and macros for MCF_ADC_ADRSLT */
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#define MCF_ADC_ADRSLT_RSLT(x) (((x)&0xFFF)<<0x3)
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#define MCF_ADC_ADRSLT_SEXT (0x8000)
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/* Bit definitions and macros for MCF_ADC_ADLLMT */
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#define MCF_ADC_ADLLMT_LLMT(x) (((x)&0xFFF)<<0x3)
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/* Bit definitions and macros for MCF_ADC_ADHLMT */
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#define MCF_ADC_ADHLMT_HLMT(x) (((x)&0xFFF)<<0x3)
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/* Bit definitions and macros for MCF_ADC_ADOFS */
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#define MCF_ADC_ADOFS_OFFSET(x) (((x)&0xFFF)<<0x3)
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/* Bit definitions and macros for MCF_ADC_POWER */
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#define MCF_ADC_POWER_PD0 (0x1)
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#define MCF_ADC_POWER_PD1 (0x2)
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#define MCF_ADC_POWER_PD2 (0x4)
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#define MCF_ADC_POWER_APD (0x8)
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#define MCF_ADC_POWER_PUDELAY(x) (((x)&0x3F)<<0x4)
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#define MCF_ADC_POWER_PSTS0 (0x400)
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#define MCF_ADC_POWER_PSTS1 (0x800)
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#define MCF_ADC_POWER_PSTS2 (0x1000)
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#define MCF_ADC_POWER_ASB (0x8000)
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/* Bit definitions and macros for MCF_ADC_CAL */
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#define MCF_ADC_CAL_SEL_VREFL (0x4000)
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#define MCF_ADC_CAL_SEL_VREFH (0x8000)
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#endif /* __MCF52235_ADC_H__ */
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/* Coldfire C Header File
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* Copyright Freescale Semiconductor Inc
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* All rights reserved.
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*
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* 2007/03/19 Revision: 0.91
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*/
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#ifndef __MCF52235_CCM_H__
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#define __MCF52235_CCM_H__
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/*********************************************************************
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*
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* Chip Configuration Module (CCM)
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*
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*********************************************************************/
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/* Register read/write macros */
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#define MCF_CCM_CCR (*(vuint16*)(&__IPSBAR[0x110004]))
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#define MCF_CCM_RCON (*(vuint16*)(&__IPSBAR[0x110008]))
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#define MCF_CCM_CIR (*(vuint16*)(&__IPSBAR[0x11000A]))
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/* Bit definitions and macros for MCF_CCM_CCR */
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#define MCF_CCM_CCR_BMT(x) (((x)&0x7)<<0)
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#define MCF_CCM_CCR_BMT_65536 (0)
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#define MCF_CCM_CCR_BMT_32768 (0x1)
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#define MCF_CCM_CCR_BMT_16384 (0x2)
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#define MCF_CCM_CCR_BMT_8192 (0x3)
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#define MCF_CCM_CCR_BMT_4096 (0x4)
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#define MCF_CCM_CCR_BMT_2048 (0x5)
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#define MCF_CCM_CCR_BMT_1024 (0x6)
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#define MCF_CCM_CCR_BMT_512 (0x7)
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#define MCF_CCM_CCR_BME (0x8)
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#define MCF_CCM_CCR_PSTEN (0x20)
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#define MCF_CCM_CCR_SZEN (0x40)
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/* Bit definitions and macros for MCF_CCM_RCON */
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#define MCF_CCM_RCON_MODE (0x1)
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#define MCF_CCM_RCON_RLOAD (0x20)
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/* Bit definitions and macros for MCF_CCM_CIR */
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#define MCF_CCM_CIR_PRN(x) (((x)&0x3F)<<0)
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#define MCF_CCM_CIR_PIN(x) (((x)&0x3FF)<<0x6)
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#endif /* __MCF52235_CCM_H__ */
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@ -0,0 +1,76 @@
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/* Coldfire C Header File
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||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2007/03/19 Revision: 0.91
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*/
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#ifndef __MCF52235_CFM_H__
|
||||
#define __MCF52235_CFM_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* ColdFire Flash Module (CFM)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_CFM_CFMMCR (*(vuint16*)(&__IPSBAR[0x1D0000]))
|
||||
#define MCF_CFM_CFMCLKD (*(vuint8 *)(&__IPSBAR[0x1D0002]))
|
||||
#define MCF_CFM_CFMSEC (*(vuint32*)(&__IPSBAR[0x1D0008]))
|
||||
#define MCF_CFM_CFMPROT (*(vuint32*)(&__IPSBAR[0x1D0010]))
|
||||
#define MCF_CFM_CFMSACC (*(vuint32*)(&__IPSBAR[0x1D0014]))
|
||||
#define MCF_CFM_CFMDACC (*(vuint32*)(&__IPSBAR[0x1D0018]))
|
||||
#define MCF_CFM_CFMUSTAT (*(vuint8 *)(&__IPSBAR[0x1D0020]))
|
||||
#define MCF_CFM_CFMCMD (*(vuint8 *)(&__IPSBAR[0x1D0024]))
|
||||
#define MCF_CFM_CFMCLKSEL (*(vuint16*)(&__IPSBAR[0x1D004A]))
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_CFM_CFMMCR */
|
||||
#define MCF_CFM_CFMMCR_KEYACC (0x20)
|
||||
#define MCF_CFM_CFMMCR_CCIE (0x40)
|
||||
#define MCF_CFM_CFMMCR_CBEIE (0x80)
|
||||
#define MCF_CFM_CFMMCR_AEIE (0x100)
|
||||
#define MCF_CFM_CFMMCR_PVIE (0x200)
|
||||
#define MCF_CFM_CFMMCR_LOCK (0x400)
|
||||
|
||||
/* Bit definitions and macros for MCF_CFM_CFMCLKD */
|
||||
#define MCF_CFM_CFMCLKD_DIV(x) (((x)&0x3F)<<0)
|
||||
#define MCF_CFM_CFMCLKD_PRDIV8 (0x40)
|
||||
#define MCF_CFM_CFMCLKD_DIVLD (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_CFM_CFMSEC */
|
||||
#define MCF_CFM_CFMSEC_SEC(x) (((x)&0xFFFF)<<0)
|
||||
#define MCF_CFM_CFMSEC_SECSTAT (0x40000000)
|
||||
#define MCF_CFM_CFMSEC_KEYEN (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_CFM_CFMPROT */
|
||||
#define MCF_CFM_CFMPROT_PROTECT(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_CFM_CFMSACC */
|
||||
#define MCF_CFM_CFMSACC_SUPV(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_CFM_CFMDACC */
|
||||
#define MCF_CFM_CFMDACC_DACC(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_CFM_CFMUSTAT */
|
||||
#define MCF_CFM_CFMUSTAT_BLANK (0x4)
|
||||
#define MCF_CFM_CFMUSTAT_ACCERR (0x10)
|
||||
#define MCF_CFM_CFMUSTAT_PVIOL (0x20)
|
||||
#define MCF_CFM_CFMUSTAT_CCIF (0x40)
|
||||
#define MCF_CFM_CFMUSTAT_CBEIF (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_CFM_CFMCMD */
|
||||
#define MCF_CFM_CFMCMD_CMD(x) (((x)&0x7F)<<0)
|
||||
#define MCF_CFM_CFMCMD_BLANK_CHECK (0x5)
|
||||
#define MCF_CFM_CFMCMD_PAGE_ERASE_VERIFY (0x6)
|
||||
#define MCF_CFM_CFMCMD_WORD_PROGRAM (0x20)
|
||||
#define MCF_CFM_CFMCMD_PAGE_ERASE (0x40)
|
||||
#define MCF_CFM_CFMCMD_MASS_ERASE (0x41)
|
||||
|
||||
/* Bit definitions and macros for MCF_CFM_CFMCLKSEL */
|
||||
#define MCF_CFM_CFMCLKSEL_CLKSEL(x) (((x)&0x3)<<0)
|
||||
|
||||
|
||||
#endif /* __MCF52235_CFM_H__ */
|
||||
|
|
@ -0,0 +1,54 @@
|
|||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2007/03/19 Revision: 0.91
|
||||
*/
|
||||
|
||||
#ifndef __MCF52235_CLOCK_H__
|
||||
#define __MCF52235_CLOCK_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Clock Module (CLOCK)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_CLOCK_SYNCR (*(vuint16*)(&__IPSBAR[0x120000]))
|
||||
#define MCF_CLOCK_SYNSR (*(vuint8 *)(&__IPSBAR[0x120002]))
|
||||
#define MCF_CLOCK_LPCR (*(vuint8 *)(&__IPSBAR[0x120007]))
|
||||
#define MCF_CLOCK_CCHR (*(vuint8 *)(&__IPSBAR[0x120008]))
|
||||
#define MCF_CLOCK_RTCDR (*(vuint32*)(&__IPSBAR[0x12000C]))
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_CLOCK_SYNCR */
|
||||
#define MCF_CLOCK_SYNCR_PLLEN (0x1)
|
||||
#define MCF_CLOCK_SYNCR_PLLMODE (0x2)
|
||||
#define MCF_CLOCK_SYNCR_CLKSRC (0x4)
|
||||
#define MCF_CLOCK_SYNCR_FWKUP (0x20)
|
||||
#define MCF_CLOCK_SYNCR_DISCLK (0x40)
|
||||
#define MCF_CLOCK_SYNCR_LOCEN (0x80)
|
||||
#define MCF_CLOCK_SYNCR_RFD(x) (((x)&0x7)<<0x8)
|
||||
#define MCF_CLOCK_SYNCR_LOCRE (0x800)
|
||||
#define MCF_CLOCK_SYNCR_MFD(x) (((x)&0x7)<<0xC)
|
||||
#define MCF_CLOCK_SYNCR_LOLRE (0x8000)
|
||||
|
||||
/* Bit definitions and macros for MCF_CLOCK_SYNSR */
|
||||
#define MCF_CLOCK_SYNSR_LOCS (0x4)
|
||||
#define MCF_CLOCK_SYNSR_LOCK (0x8)
|
||||
#define MCF_CLOCK_SYNSR_LOCKS (0x10)
|
||||
#define MCF_CLOCK_SYNSR_EXTOSC (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_CLOCK_LPCR */
|
||||
#define MCF_CLOCK_LPCR_LPD(x) (((x)&0xF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_CLOCK_CCHR */
|
||||
#define MCF_CLOCK_CCHR_CCHR(x) (((x)&0x7)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_CLOCK_RTCDR */
|
||||
#define MCF_CLOCK_RTCDR_RTCDF(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
|
||||
#endif /* __MCF52235_CLOCK_H__ */
|
||||
142
Demo/ColdFire_MCF52233_Eclipse/RTOSDemo/MCF5223x/MCF52235_DMA.h
Normal file
142
Demo/ColdFire_MCF52233_Eclipse/RTOSDemo/MCF5223x/MCF52235_DMA.h
Normal file
|
|
@ -0,0 +1,142 @@
|
|||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2007/03/19 Revision: 0.91
|
||||
*/
|
||||
|
||||
#ifndef __MCF52235_DMA_H__
|
||||
#define __MCF52235_DMA_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* DMA Controller (DMA)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_DMA0_SAR (*(vuint32*)(&__IPSBAR[0x100]))
|
||||
#define MCF_DMA0_DAR (*(vuint32*)(&__IPSBAR[0x104]))
|
||||
#define MCF_DMA0_DSR (*(vuint8 *)(&__IPSBAR[0x108]))
|
||||
#define MCF_DMA0_BCR (*(vuint32*)(&__IPSBAR[0x108]))
|
||||
#define MCF_DMA0_DCR (*(vuint32*)(&__IPSBAR[0x10C]))
|
||||
|
||||
#define MCF_DMA1_SAR (*(vuint32*)(&__IPSBAR[0x110]))
|
||||
#define MCF_DMA1_DAR (*(vuint32*)(&__IPSBAR[0x114]))
|
||||
#define MCF_DMA1_DSR (*(vuint8 *)(&__IPSBAR[0x118]))
|
||||
#define MCF_DMA1_BCR (*(vuint32*)(&__IPSBAR[0x118]))
|
||||
#define MCF_DMA1_DCR (*(vuint32*)(&__IPSBAR[0x11C]))
|
||||
|
||||
#define MCF_DMA2_SAR (*(vuint32*)(&__IPSBAR[0x120]))
|
||||
#define MCF_DMA2_DAR (*(vuint32*)(&__IPSBAR[0x124]))
|
||||
#define MCF_DMA2_DSR (*(vuint8 *)(&__IPSBAR[0x128]))
|
||||
#define MCF_DMA2_BCR (*(vuint32*)(&__IPSBAR[0x128]))
|
||||
#define MCF_DMA2_DCR (*(vuint32*)(&__IPSBAR[0x12C]))
|
||||
|
||||
#define MCF_DMA3_SAR (*(vuint32*)(&__IPSBAR[0x130]))
|
||||
#define MCF_DMA3_DAR (*(vuint32*)(&__IPSBAR[0x134]))
|
||||
#define MCF_DMA3_DSR (*(vuint8 *)(&__IPSBAR[0x138]))
|
||||
#define MCF_DMA3_BCR (*(vuint32*)(&__IPSBAR[0x138]))
|
||||
#define MCF_DMA3_DCR (*(vuint32*)(&__IPSBAR[0x13C]))
|
||||
|
||||
#define MCF_DMA_SAR(x) (*(vuint32*)(&__IPSBAR[0x100 + ((x)*0x10)]))
|
||||
#define MCF_DMA_DAR(x) (*(vuint32*)(&__IPSBAR[0x104 + ((x)*0x10)]))
|
||||
#define MCF_DMA_DSR(x) (*(vuint8 *)(&__IPSBAR[0x108 + ((x)*0x10)]))
|
||||
#define MCF_DMA_BCR(x) (*(vuint32*)(&__IPSBAR[0x108 + ((x)*0x10)]))
|
||||
#define MCF_DMA_DCR(x) (*(vuint32*)(&__IPSBAR[0x10C + ((x)*0x10)]))
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_DMA_SAR */
|
||||
#define MCF_DMA_SAR_SAR(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_DMA_DAR */
|
||||
#define MCF_DMA_DAR_DAR(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_DMA_DSR */
|
||||
#define MCF_DMA_DSR_DONE (0x1)
|
||||
#define MCF_DMA_DSR_BSY (0x2)
|
||||
#define MCF_DMA_DSR_REQ (0x4)
|
||||
#define MCF_DMA_DSR_BED (0x10)
|
||||
#define MCF_DMA_DSR_BES (0x20)
|
||||
#define MCF_DMA_DSR_CE (0x40)
|
||||
|
||||
/* Bit definitions and macros for MCF_DMA_BCR */
|
||||
#define MCF_DMA_BCR_BCR(x) (((x)&0xFFFFFF)<<0)
|
||||
#define MCF_DMA_BCR_DSR(x) (((x)&0xFF)<<0x18)
|
||||
|
||||
/* Bit definitions and macros for MCF_DMA_DCR */
|
||||
#define MCF_DMA_DCR_LCH2(x) (((x)&0x3)<<0)
|
||||
#define MCF_DMA_DCR_LCH2_CH0 (0)
|
||||
#define MCF_DMA_DCR_LCH2_CH1 (0x1)
|
||||
#define MCF_DMA_DCR_LCH2_CH2 (0x2)
|
||||
#define MCF_DMA_DCR_LCH2_CH3 (0x3)
|
||||
#define MCF_DMA_DCR_LCH1(x) (((x)&0x3)<<0x2)
|
||||
#define MCF_DMA_DCR_LCH1_CH0 (0)
|
||||
#define MCF_DMA_DCR_LCH1_CH1 (0x1)
|
||||
#define MCF_DMA_DCR_LCH1_CH2 (0x2)
|
||||
#define MCF_DMA_DCR_LCH1_CH3 (0x3)
|
||||
#define MCF_DMA_DCR_LINKCC(x) (((x)&0x3)<<0x4)
|
||||
#define MCF_DMA_DCR_D_REQ (0x80)
|
||||
#define MCF_DMA_DCR_DMOD(x) (((x)&0xF)<<0x8)
|
||||
#define MCF_DMA_DCR_DMOD_DIS (0)
|
||||
#define MCF_DMA_DCR_DMOD_16 (0x1)
|
||||
#define MCF_DMA_DCR_DMOD_32 (0x2)
|
||||
#define MCF_DMA_DCR_DMOD_64 (0x3)
|
||||
#define MCF_DMA_DCR_DMOD_128 (0x4)
|
||||
#define MCF_DMA_DCR_DMOD_256 (0x5)
|
||||
#define MCF_DMA_DCR_DMOD_512 (0x6)
|
||||
#define MCF_DMA_DCR_DMOD_1K (0x7)
|
||||
#define MCF_DMA_DCR_DMOD_2K (0x8)
|
||||
#define MCF_DMA_DCR_DMOD_4K (0x9)
|
||||
#define MCF_DMA_DCR_DMOD_8K (0xA)
|
||||
#define MCF_DMA_DCR_DMOD_16K (0xB)
|
||||
#define MCF_DMA_DCR_DMOD_32K (0xC)
|
||||
#define MCF_DMA_DCR_DMOD_64K (0xD)
|
||||
#define MCF_DMA_DCR_DMOD_128K (0xE)
|
||||
#define MCF_DMA_DCR_DMOD_256K (0xF)
|
||||
#define MCF_DMA_DCR_SMOD(x) (((x)&0xF)<<0xC)
|
||||
#define MCF_DMA_DCR_SMOD_DIS (0)
|
||||
#define MCF_DMA_DCR_SMOD_16 (0x1)
|
||||
#define MCF_DMA_DCR_SMOD_32 (0x2)
|
||||
#define MCF_DMA_DCR_SMOD_64 (0x3)
|
||||
#define MCF_DMA_DCR_SMOD_128 (0x4)
|
||||
#define MCF_DMA_DCR_SMOD_256 (0x5)
|
||||
#define MCF_DMA_DCR_SMOD_512 (0x6)
|
||||
#define MCF_DMA_DCR_SMOD_1K (0x7)
|
||||
#define MCF_DMA_DCR_SMOD_2K (0x8)
|
||||
#define MCF_DMA_DCR_SMOD_4K (0x9)
|
||||
#define MCF_DMA_DCR_SMOD_8K (0xA)
|
||||
#define MCF_DMA_DCR_SMOD_16K (0xB)
|
||||
#define MCF_DMA_DCR_SMOD_32K (0xC)
|
||||
#define MCF_DMA_DCR_SMOD_64K (0xD)
|
||||
#define MCF_DMA_DCR_SMOD_128K (0xE)
|
||||
#define MCF_DMA_DCR_SMOD_256K (0xF)
|
||||
#define MCF_DMA_DCR_START (0x10000)
|
||||
#define MCF_DMA_DCR_DSIZE(x) (((x)&0x3)<<0x11)
|
||||
#define MCF_DMA_DCR_DSIZE_LONG (0)
|
||||
#define MCF_DMA_DCR_DSIZE_BYTE (0x1)
|
||||
#define MCF_DMA_DCR_DSIZE_WORD (0x2)
|
||||
#define MCF_DMA_DCR_DSIZE_LINE (0x3)
|
||||
#define MCF_DMA_DCR_DINC (0x80000)
|
||||
#define MCF_DMA_DCR_SSIZE(x) (((x)&0x3)<<0x14)
|
||||
#define MCF_DMA_DCR_SSIZE_LONG (0)
|
||||
#define MCF_DMA_DCR_SSIZE_BYTE (0x1)
|
||||
#define MCF_DMA_DCR_SSIZE_WORD (0x2)
|
||||
#define MCF_DMA_DCR_SSIZE_LINE (0x3)
|
||||
#define MCF_DMA_DCR_SINC (0x400000)
|
||||
#define MCF_DMA_DCR_BWC(x) (((x)&0x7)<<0x19)
|
||||
#define MCF_DMA_DCR_BWC_16K (0x1)
|
||||
#define MCF_DMA_DCR_BWC_32K (0x2)
|
||||
#define MCF_DMA_DCR_BWC_64K (0x3)
|
||||
#define MCF_DMA_DCR_BWC_128K (0x4)
|
||||
#define MCF_DMA_DCR_BWC_256K (0x5)
|
||||
#define MCF_DMA_DCR_BWC_512K (0x6)
|
||||
#define MCF_DMA_DCR_BWC_1024K (0x7)
|
||||
#define MCF_DMA_DCR_AA (0x10000000)
|
||||
#define MCF_DMA_DCR_CS (0x20000000)
|
||||
#define MCF_DMA_DCR_EEXT (0x40000000)
|
||||
#define MCF_DMA_DCR_INT (0x80000000)
|
||||
|
||||
|
||||
#endif /* __MCF52235_DMA_H__ */
|
||||
|
|
@ -0,0 +1,91 @@
|
|||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2007/03/19 Revision: 0.91
|
||||
*/
|
||||
|
||||
#ifndef __MCF52235_DTIM_H__
|
||||
#define __MCF52235_DTIM_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* DMA Timers (DTIM)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_DTIM0_DTMR (*(vuint16*)(&__IPSBAR[0x400]))
|
||||
#define MCF_DTIM0_DTXMR (*(vuint8 *)(&__IPSBAR[0x402]))
|
||||
#define MCF_DTIM0_DTER (*(vuint8 *)(&__IPSBAR[0x403]))
|
||||
#define MCF_DTIM0_DTRR (*(vuint32*)(&__IPSBAR[0x404]))
|
||||
#define MCF_DTIM0_DTCR (*(vuint32*)(&__IPSBAR[0x408]))
|
||||
#define MCF_DTIM0_DTCN (*(vuint32*)(&__IPSBAR[0x40C]))
|
||||
|
||||
#define MCF_DTIM1_DTMR (*(vuint16*)(&__IPSBAR[0x440]))
|
||||
#define MCF_DTIM1_DTXMR (*(vuint8 *)(&__IPSBAR[0x442]))
|
||||
#define MCF_DTIM1_DTER (*(vuint8 *)(&__IPSBAR[0x443]))
|
||||
#define MCF_DTIM1_DTRR (*(vuint32*)(&__IPSBAR[0x444]))
|
||||
#define MCF_DTIM1_DTCR (*(vuint32*)(&__IPSBAR[0x448]))
|
||||
#define MCF_DTIM1_DTCN (*(vuint32*)(&__IPSBAR[0x44C]))
|
||||
|
||||
#define MCF_DTIM2_DTMR (*(vuint16*)(&__IPSBAR[0x480]))
|
||||
#define MCF_DTIM2_DTXMR (*(vuint8 *)(&__IPSBAR[0x482]))
|
||||
#define MCF_DTIM2_DTER (*(vuint8 *)(&__IPSBAR[0x483]))
|
||||
#define MCF_DTIM2_DTRR (*(vuint32*)(&__IPSBAR[0x484]))
|
||||
#define MCF_DTIM2_DTCR (*(vuint32*)(&__IPSBAR[0x488]))
|
||||
#define MCF_DTIM2_DTCN (*(vuint32*)(&__IPSBAR[0x48C]))
|
||||
|
||||
#define MCF_DTIM3_DTMR (*(vuint16*)(&__IPSBAR[0x4C0]))
|
||||
#define MCF_DTIM3_DTXMR (*(vuint8 *)(&__IPSBAR[0x4C2]))
|
||||
#define MCF_DTIM3_DTER (*(vuint8 *)(&__IPSBAR[0x4C3]))
|
||||
#define MCF_DTIM3_DTRR (*(vuint32*)(&__IPSBAR[0x4C4]))
|
||||
#define MCF_DTIM3_DTCR (*(vuint32*)(&__IPSBAR[0x4C8]))
|
||||
#define MCF_DTIM3_DTCN (*(vuint32*)(&__IPSBAR[0x4CC]))
|
||||
|
||||
#define MCF_DTIM_DTMR(x) (*(vuint16*)(&__IPSBAR[0x400 + ((x)*0x40)]))
|
||||
#define MCF_DTIM_DTXMR(x) (*(vuint8 *)(&__IPSBAR[0x402 + ((x)*0x40)]))
|
||||
#define MCF_DTIM_DTER(x) (*(vuint8 *)(&__IPSBAR[0x403 + ((x)*0x40)]))
|
||||
#define MCF_DTIM_DTRR(x) (*(vuint32*)(&__IPSBAR[0x404 + ((x)*0x40)]))
|
||||
#define MCF_DTIM_DTCR(x) (*(vuint32*)(&__IPSBAR[0x408 + ((x)*0x40)]))
|
||||
#define MCF_DTIM_DTCN(x) (*(vuint32*)(&__IPSBAR[0x40C + ((x)*0x40)]))
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_DTIM_DTMR */
|
||||
#define MCF_DTIM_DTMR_RST (0x1)
|
||||
#define MCF_DTIM_DTMR_CLK(x) (((x)&0x3)<<0x1)
|
||||
#define MCF_DTIM_DTMR_CLK_STOP (0)
|
||||
#define MCF_DTIM_DTMR_CLK_DIV1 (0x2)
|
||||
#define MCF_DTIM_DTMR_CLK_DIV16 (0x4)
|
||||
#define MCF_DTIM_DTMR_CLK_DTIN (0x6)
|
||||
#define MCF_DTIM_DTMR_FRR (0x8)
|
||||
#define MCF_DTIM_DTMR_ORRI (0x10)
|
||||
#define MCF_DTIM_DTMR_OM (0x20)
|
||||
#define MCF_DTIM_DTMR_CE(x) (((x)&0x3)<<0x6)
|
||||
#define MCF_DTIM_DTMR_CE_NONE (0)
|
||||
#define MCF_DTIM_DTMR_CE_RISE (0x40)
|
||||
#define MCF_DTIM_DTMR_CE_FALL (0x80)
|
||||
#define MCF_DTIM_DTMR_CE_ANY (0xC0)
|
||||
#define MCF_DTIM_DTMR_PS(x) (((x)&0xFF)<<0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_DTIM_DTXMR */
|
||||
#define MCF_DTIM_DTXMR_MODE16 (0x1)
|
||||
#define MCF_DTIM_DTXMR_HALTED (0x40)
|
||||
#define MCF_DTIM_DTXMR_DMAEN (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_DTIM_DTER */
|
||||
#define MCF_DTIM_DTER_CAP (0x1)
|
||||
#define MCF_DTIM_DTER_REF (0x2)
|
||||
|
||||
/* Bit definitions and macros for MCF_DTIM_DTRR */
|
||||
#define MCF_DTIM_DTRR_REF(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_DTIM_DTCR */
|
||||
#define MCF_DTIM_DTCR_CAP(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_DTIM_DTCN */
|
||||
#define MCF_DTIM_DTCN_CNT(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
|
||||
#endif /* __MCF52235_DTIM_H__ */
|
||||
|
|
@ -0,0 +1,42 @@
|
|||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2007/03/19 Revision: 0.91
|
||||
*/
|
||||
|
||||
#ifndef __MCF52235_EPHY_H__
|
||||
#define __MCF52235_EPHY_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Ethernet Physical Transceiver (EPHY)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_EPHY_EPHYCTL0 (*(vuint8 *)(&__IPSBAR[0x1E0000]))
|
||||
#define MCF_EPHY_EPHYCTL1 (*(vuint8 *)(&__IPSBAR[0x1E0001]))
|
||||
#define MCF_EPHY_EPHYSR (*(vuint8 *)(&__IPSBAR[0x1E0002]))
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_EPHY_EPHYCTL0 */
|
||||
#define MCF_EPHY_EPHYCTL0_EPHYIEN (0x1)
|
||||
#define MCF_EPHY_EPHYCTL0_EPHYWAI (0x4)
|
||||
#define MCF_EPHY_EPHYCTL0_LEDEN (0x8)
|
||||
#define MCF_EPHY_EPHYCTL0_DIS10 (0x10)
|
||||
#define MCF_EPHY_EPHYCTL0_DIS100 (0x20)
|
||||
#define MCF_EPHY_EPHYCTL0_ANDIS (0x40)
|
||||
#define MCF_EPHY_EPHYCTL0_EPHYEN (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_EPHY_EPHYCTL1 */
|
||||
#define MCF_EPHY_EPHYCTL1_PHYADD(x) (((x)&0x1F)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_EPHY_EPHYSR */
|
||||
#define MCF_EPHY_EPHYSR_EPHYIF (0x1)
|
||||
#define MCF_EPHY_EPHYSR_10DIS (0x10)
|
||||
#define MCF_EPHY_EPHYSR_100DIS (0x20)
|
||||
|
||||
|
||||
#endif /* __MCF52235_EPHY_H__ */
|
||||
|
|
@ -0,0 +1,220 @@
|
|||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2007/03/19 Revision: 0.91
|
||||
*/
|
||||
|
||||
#ifndef __MCF52235_EPORT_H__
|
||||
#define __MCF52235_EPORT_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Edge Port Module (EPORT)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_EPORT0_EPPAR (*(vuint16*)(&__IPSBAR[0x130000]))
|
||||
#define MCF_EPORT0_EPDDR (*(vuint8 *)(&__IPSBAR[0x130002]))
|
||||
#define MCF_EPORT0_EPIER (*(vuint8 *)(&__IPSBAR[0x130003]))
|
||||
#define MCF_EPORT0_EPDR (*(vuint8 *)(&__IPSBAR[0x130004]))
|
||||
#define MCF_EPORT0_EPPDR (*(vuint8 *)(&__IPSBAR[0x130005]))
|
||||
#define MCF_EPORT0_EPFR (*(vuint8 *)(&__IPSBAR[0x130006]))
|
||||
|
||||
#define MCF_EPORT1_EPPAR (*(vuint16*)(&__IPSBAR[0x140000]))
|
||||
#define MCF_EPORT1_EPDDR (*(vuint8 *)(&__IPSBAR[0x140002]))
|
||||
#define MCF_EPORT1_EPIER (*(vuint8 *)(&__IPSBAR[0x140003]))
|
||||
#define MCF_EPORT1_EPDR (*(vuint8 *)(&__IPSBAR[0x140004]))
|
||||
#define MCF_EPORT1_EPPDR (*(vuint8 *)(&__IPSBAR[0x140005]))
|
||||
#define MCF_EPORT1_EPFR (*(vuint8 *)(&__IPSBAR[0x140006]))
|
||||
|
||||
#define MCF_EPORT_EPPAR(x) (*(vuint16*)(&__IPSBAR[0x130000 + ((x)*0x10000)]))
|
||||
#define MCF_EPORT_EPDDR(x) (*(vuint8 *)(&__IPSBAR[0x130002 + ((x)*0x10000)]))
|
||||
#define MCF_EPORT_EPIER(x) (*(vuint8 *)(&__IPSBAR[0x130003 + ((x)*0x10000)]))
|
||||
#define MCF_EPORT_EPDR(x) (*(vuint8 *)(&__IPSBAR[0x130004 + ((x)*0x10000)]))
|
||||
#define MCF_EPORT_EPPDR(x) (*(vuint8 *)(&__IPSBAR[0x130005 + ((x)*0x10000)]))
|
||||
#define MCF_EPORT_EPFR(x) (*(vuint8 *)(&__IPSBAR[0x130006 + ((x)*0x10000)]))
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_EPORT_EPPAR */
|
||||
#define MCF_EPORT_EPPAR_EPPA1(x) (((x)&0x3)<<0x2)
|
||||
#define MCF_EPORT_EPPAR_EPPA1_LEVEL (0)
|
||||
#define MCF_EPORT_EPPAR_EPPA1_RISING (0x4)
|
||||
#define MCF_EPORT_EPPAR_EPPA1_FALLING (0x8)
|
||||
#define MCF_EPORT_EPPAR_EPPA1_BOTH (0xC)
|
||||
#define MCF_EPORT_EPPAR_EPPA2(x) (((x)&0x3)<<0x4)
|
||||
#define MCF_EPORT_EPPAR_EPPA2_LEVEL (0)
|
||||
#define MCF_EPORT_EPPAR_EPPA2_RISING (0x10)
|
||||
#define MCF_EPORT_EPPAR_EPPA2_FALLING (0x20)
|
||||
#define MCF_EPORT_EPPAR_EPPA2_BOTH (0x30)
|
||||
#define MCF_EPORT_EPPAR_EPPA3(x) (((x)&0x3)<<0x6)
|
||||
#define MCF_EPORT_EPPAR_EPPA3_LEVEL (0)
|
||||
#define MCF_EPORT_EPPAR_EPPA3_RISING (0x40)
|
||||
#define MCF_EPORT_EPPAR_EPPA3_FALLING (0x80)
|
||||
#define MCF_EPORT_EPPAR_EPPA3_BOTH (0xC0)
|
||||
#define MCF_EPORT_EPPAR_EPPA4(x) (((x)&0x3)<<0x8)
|
||||
#define MCF_EPORT_EPPAR_EPPA4_LEVEL (0)
|
||||
#define MCF_EPORT_EPPAR_EPPA4_RISING (0x100)
|
||||
#define MCF_EPORT_EPPAR_EPPA4_FALLING (0x200)
|
||||
#define MCF_EPORT_EPPAR_EPPA4_BOTH (0x300)
|
||||
#define MCF_EPORT_EPPAR_EPPA5(x) (((x)&0x3)<<0xA)
|
||||
#define MCF_EPORT_EPPAR_EPPA5_LEVEL (0)
|
||||
#define MCF_EPORT_EPPAR_EPPA5_RISING (0x400)
|
||||
#define MCF_EPORT_EPPAR_EPPA5_FALLING (0x800)
|
||||
#define MCF_EPORT_EPPAR_EPPA5_BOTH (0xC00)
|
||||
#define MCF_EPORT_EPPAR_EPPA6(x) (((x)&0x3)<<0xC)
|
||||
#define MCF_EPORT_EPPAR_EPPA6_LEVEL (0)
|
||||
#define MCF_EPORT_EPPAR_EPPA6_RISING (0x1000)
|
||||
#define MCF_EPORT_EPPAR_EPPA6_FALLING (0x2000)
|
||||
#define MCF_EPORT_EPPAR_EPPA6_BOTH (0x3000)
|
||||
#define MCF_EPORT_EPPAR_EPPA7(x) (((x)&0x3)<<0xE)
|
||||
#define MCF_EPORT_EPPAR_EPPA7_LEVEL (0)
|
||||
#define MCF_EPORT_EPPAR_EPPA7_RISING (0x4000)
|
||||
#define MCF_EPORT_EPPAR_EPPA7_FALLING (0x8000)
|
||||
#define MCF_EPORT_EPPAR_EPPA7_BOTH (0xC000)
|
||||
#define MCF_EPORT_EPPAR_LEVEL (0)
|
||||
#define MCF_EPORT_EPPAR_RISING (0x1)
|
||||
#define MCF_EPORT_EPPAR_FALLING (0x2)
|
||||
#define MCF_EPORT_EPPAR_BOTH (0x3)
|
||||
|
||||
/* Bit definitions and macros for MCF_EPORT_EPDDR */
|
||||
#define MCF_EPORT_EPDDR_EPDD1 (0x2)
|
||||
#define MCF_EPORT_EPDDR_EPDD2 (0x4)
|
||||
#define MCF_EPORT_EPDDR_EPDD3 (0x8)
|
||||
#define MCF_EPORT_EPDDR_EPDD4 (0x10)
|
||||
#define MCF_EPORT_EPDDR_EPDD5 (0x20)
|
||||
#define MCF_EPORT_EPDDR_EPDD6 (0x40)
|
||||
#define MCF_EPORT_EPDDR_EPDD7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_EPORT_EPIER */
|
||||
#define MCF_EPORT_EPIER_EPIE1 (0x2)
|
||||
#define MCF_EPORT_EPIER_EPIE2 (0x4)
|
||||
#define MCF_EPORT_EPIER_EPIE3 (0x8)
|
||||
#define MCF_EPORT_EPIER_EPIE4 (0x10)
|
||||
#define MCF_EPORT_EPIER_EPIE5 (0x20)
|
||||
#define MCF_EPORT_EPIER_EPIE6 (0x40)
|
||||
#define MCF_EPORT_EPIER_EPIE7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_EPORT_EPDR */
|
||||
#define MCF_EPORT_EPDR_EPD1 (0x2)
|
||||
#define MCF_EPORT_EPDR_EPD2 (0x4)
|
||||
#define MCF_EPORT_EPDR_EPD3 (0x8)
|
||||
#define MCF_EPORT_EPDR_EPD4 (0x10)
|
||||
#define MCF_EPORT_EPDR_EPD5 (0x20)
|
||||
#define MCF_EPORT_EPDR_EPD6 (0x40)
|
||||
#define MCF_EPORT_EPDR_EPD7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_EPORT_EPPDR */
|
||||
#define MCF_EPORT_EPPDR_EPPD1 (0x2)
|
||||
#define MCF_EPORT_EPPDR_EPPD2 (0x4)
|
||||
#define MCF_EPORT_EPPDR_EPPD3 (0x8)
|
||||
#define MCF_EPORT_EPPDR_EPPD4 (0x10)
|
||||
#define MCF_EPORT_EPPDR_EPPD5 (0x20)
|
||||
#define MCF_EPORT_EPPDR_EPPD6 (0x40)
|
||||
#define MCF_EPORT_EPPDR_EPPD7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_EPORT_EPFR */
|
||||
#define MCF_EPORT_EPFR_EPF1 (0x2)
|
||||
#define MCF_EPORT_EPFR_EPF2 (0x4)
|
||||
#define MCF_EPORT_EPFR_EPF3 (0x8)
|
||||
#define MCF_EPORT_EPFR_EPF4 (0x10)
|
||||
#define MCF_EPORT_EPFR_EPF5 (0x20)
|
||||
#define MCF_EPORT_EPFR_EPF6 (0x40)
|
||||
#define MCF_EPORT_EPFR_EPF7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_EPORT_EPPAR */
|
||||
#define MCF_EPORT_EPPAR_EPPA8(x) (((x)&0x3)<<0)
|
||||
#define MCF_EPORT_EPPAR_EPPA8_LEVEL (0)
|
||||
#define MCF_EPORT_EPPAR_EPPA8_RISING (0x1)
|
||||
#define MCF_EPORT_EPPAR_EPPA8_FALLING (0x2)
|
||||
#define MCF_EPORT_EPPAR_EPPA8_BOTH (0x3)
|
||||
#define MCF_EPORT_EPPAR_EPPA9(x) (((x)&0x3)<<0x2)
|
||||
#define MCF_EPORT_EPPAR_EPPA9_LEVEL (0)
|
||||
#define MCF_EPORT_EPPAR_EPPA9_RISING (0x4)
|
||||
#define MCF_EPORT_EPPAR_EPPA9_FALLING (0x8)
|
||||
#define MCF_EPORT_EPPAR_EPPA9_BOTH (0xC)
|
||||
#define MCF_EPORT_EPPAR_EPPA10(x) (((x)&0x3)<<0x4)
|
||||
#define MCF_EPORT_EPPAR_EPPA10_LEVEL (0)
|
||||
#define MCF_EPORT_EPPAR_EPPA10_RISING (0x10)
|
||||
#define MCF_EPORT_EPPAR_EPPA10_FALLING (0x20)
|
||||
#define MCF_EPORT_EPPAR_EPPA10_BOTH (0x30)
|
||||
#define MCF_EPORT_EPPAR_EPPA11(x) (((x)&0x3)<<0x6)
|
||||
#define MCF_EPORT_EPPAR_EPPA11_LEVEL (0)
|
||||
#define MCF_EPORT_EPPAR_EPPA11_RISING (0x40)
|
||||
#define MCF_EPORT_EPPAR_EPPA11_FALLING (0x80)
|
||||
#define MCF_EPORT_EPPAR_EPPA11_BOTH (0xC0)
|
||||
#define MCF_EPORT_EPPAR_EPPA12(x) (((x)&0x3)<<0x8)
|
||||
#define MCF_EPORT_EPPAR_EPPA12_LEVEL (0)
|
||||
#define MCF_EPORT_EPPAR_EPPA12_RISING (0x100)
|
||||
#define MCF_EPORT_EPPAR_EPPA12_FALLING (0x200)
|
||||
#define MCF_EPORT_EPPAR_EPPA12_BOTH (0x300)
|
||||
#define MCF_EPORT_EPPAR_EPPA13(x) (((x)&0x3)<<0xA)
|
||||
#define MCF_EPORT_EPPAR_EPPA13_LEVEL (0)
|
||||
#define MCF_EPORT_EPPAR_EPPA13_RISING (0x400)
|
||||
#define MCF_EPORT_EPPAR_EPPA13_FALLING (0x800)
|
||||
#define MCF_EPORT_EPPAR_EPPA13_BOTH (0xC00)
|
||||
#define MCF_EPORT_EPPAR_EPPA14(x) (((x)&0x3)<<0xC)
|
||||
#define MCF_EPORT_EPPAR_EPPA14_LEVEL (0)
|
||||
#define MCF_EPORT_EPPAR_EPPA14_RISING (0x1000)
|
||||
#define MCF_EPORT_EPPAR_EPPA14_FALLING (0x2000)
|
||||
#define MCF_EPORT_EPPAR_EPPA14_BOTH (0x3000)
|
||||
#define MCF_EPORT_EPPAR_EPPA15(x) (((x)&0x3)<<0xE)
|
||||
#define MCF_EPORT_EPPAR_EPPA15_LEVEL (0)
|
||||
#define MCF_EPORT_EPPAR_EPPA15_RISING (0x4000)
|
||||
#define MCF_EPORT_EPPAR_EPPA15_FALLING (0x8000)
|
||||
#define MCF_EPORT_EPPAR_EPPA15_BOTH (0xC000)
|
||||
|
||||
/* Bit definitions and macros for MCF_EPORT_EPDDR */
|
||||
#define MCF_EPORT_EPDDR_EPDD8 (0x1)
|
||||
#define MCF_EPORT_EPDDR_EPDD9 (0x2)
|
||||
#define MCF_EPORT_EPDDR_EPDD10 (0x4)
|
||||
#define MCF_EPORT_EPDDR_EPDD11 (0x8)
|
||||
#define MCF_EPORT_EPDDR_EPDD12 (0x10)
|
||||
#define MCF_EPORT_EPDDR_EPDD13 (0x20)
|
||||
#define MCF_EPORT_EPDDR_EPDD14 (0x40)
|
||||
#define MCF_EPORT_EPDDR_EPDD15 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_EPORT_EPIER */
|
||||
#define MCF_EPORT_EPIER_EPIE8 (0x1)
|
||||
#define MCF_EPORT_EPIER_EPIE9 (0x2)
|
||||
#define MCF_EPORT_EPIER_EPIE10 (0x4)
|
||||
#define MCF_EPORT_EPIER_EPIE11 (0x8)
|
||||
#define MCF_EPORT_EPIER_EPIE12 (0x10)
|
||||
#define MCF_EPORT_EPIER_EPIE13 (0x20)
|
||||
#define MCF_EPORT_EPIER_EPIE14 (0x40)
|
||||
#define MCF_EPORT_EPIER_EPIE15 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_EPORT_EPDR */
|
||||
#define MCF_EPORT_EPDR_EPD8 (0x1)
|
||||
#define MCF_EPORT_EPDR_EPD9 (0x2)
|
||||
#define MCF_EPORT_EPDR_EPD10 (0x4)
|
||||
#define MCF_EPORT_EPDR_EPD11 (0x8)
|
||||
#define MCF_EPORT_EPDR_EPD12 (0x10)
|
||||
#define MCF_EPORT_EPDR_EPD13 (0x20)
|
||||
#define MCF_EPORT_EPDR_EPD14 (0x40)
|
||||
#define MCF_EPORT_EPDR_EPD15 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_EPORT_EPPDR */
|
||||
#define MCF_EPORT_EPPDR_EPPD8 (0x1)
|
||||
#define MCF_EPORT_EPPDR_EPPD9 (0x2)
|
||||
#define MCF_EPORT_EPPDR_EPPD10 (0x4)
|
||||
#define MCF_EPORT_EPPDR_EPPD11 (0x8)
|
||||
#define MCF_EPORT_EPPDR_EPPD12 (0x10)
|
||||
#define MCF_EPORT_EPPDR_EPPD13 (0x20)
|
||||
#define MCF_EPORT_EPPDR_EPPD14 (0x40)
|
||||
#define MCF_EPORT_EPPDR_EPPD15 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_EPORT_EPFR */
|
||||
#define MCF_EPORT_EPFR_EPF8 (0x1)
|
||||
#define MCF_EPORT_EPFR_EPF9 (0x2)
|
||||
#define MCF_EPORT_EPFR_EPF10 (0x4)
|
||||
#define MCF_EPORT_EPFR_EPF11 (0x8)
|
||||
#define MCF_EPORT_EPFR_EPF12 (0x10)
|
||||
#define MCF_EPORT_EPFR_EPF13 (0x20)
|
||||
#define MCF_EPORT_EPFR_EPF14 (0x40)
|
||||
#define MCF_EPORT_EPFR_EPF15 (0x80)
|
||||
|
||||
|
||||
#endif /* __MCF52235_EPORT_H__ */
|
||||
385
Demo/ColdFire_MCF52233_Eclipse/RTOSDemo/MCF5223x/MCF52235_FEC.h
Normal file
385
Demo/ColdFire_MCF52233_Eclipse/RTOSDemo/MCF5223x/MCF52235_FEC.h
Normal file
|
|
@ -0,0 +1,385 @@
|
|||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2007/03/19 Revision: 0.91
|
||||
*/
|
||||
|
||||
#ifndef __MCF52235_FEC_H__
|
||||
#define __MCF52235_FEC_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Fast Ethernet Controller(FEC)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_FEC_EIR (*(vuint32*)(&__IPSBAR[0x1004]))
|
||||
#define MCF_FEC_EIMR (*(vuint32*)(&__IPSBAR[0x1008]))
|
||||
#define MCF_FEC_RDAR (*(vuint32*)(&__IPSBAR[0x1010]))
|
||||
#define MCF_FEC_TDAR (*(vuint32*)(&__IPSBAR[0x1014]))
|
||||
#define MCF_FEC_ECR (*(vuint32*)(&__IPSBAR[0x1024]))
|
||||
#define MCF_FEC_MMFR (*(vuint32*)(&__IPSBAR[0x1040]))
|
||||
#define MCF_FEC_MSCR (*(vuint32*)(&__IPSBAR[0x1044]))
|
||||
#define MCF_FEC_MIBC (*(vuint32*)(&__IPSBAR[0x1064]))
|
||||
#define MCF_FEC_RCR (*(vuint32*)(&__IPSBAR[0x1084]))
|
||||
#define MCF_FEC_TCR (*(vuint32*)(&__IPSBAR[0x10C4]))
|
||||
#define MCF_FEC_PALR (*(vuint32*)(&__IPSBAR[0x10E4]))
|
||||
#define MCF_FEC_PAUR (*(vuint32*)(&__IPSBAR[0x10E8]))
|
||||
#define MCF_FEC_OPD (*(vuint32*)(&__IPSBAR[0x10EC]))
|
||||
#define MCF_FEC_IAUR (*(vuint32*)(&__IPSBAR[0x1118]))
|
||||
#define MCF_FEC_IALR (*(vuint32*)(&__IPSBAR[0x111C]))
|
||||
#define MCF_FEC_GAUR (*(vuint32*)(&__IPSBAR[0x1120]))
|
||||
#define MCF_FEC_GALR (*(vuint32*)(&__IPSBAR[0x1124]))
|
||||
#define MCF_FEC_TFWR (*(vuint32*)(&__IPSBAR[0x1144]))
|
||||
#define MCF_FEC_FRBR (*(vuint32*)(&__IPSBAR[0x114C]))
|
||||
#define MCF_FEC_FRSR (*(vuint32*)(&__IPSBAR[0x1150]))
|
||||
#define MCF_FEC_ERDSR (*(vuint32*)(&__IPSBAR[0x1180]))
|
||||
#define MCF_FEC_ETSDR (*(vuint32*)(&__IPSBAR[0x1184]))
|
||||
#define MCF_FEC_EMRBR (*(vuint32*)(&__IPSBAR[0x1188]))
|
||||
#define MCF_FEC_RMON_T_DROP (*(vuint32*)(&__IPSBAR[0x1200]))
|
||||
#define MCF_FEC_RMON_T_PACKETS (*(vuint32*)(&__IPSBAR[0x1204]))
|
||||
#define MCF_FEC_RMON_T_BC_PKT (*(vuint32*)(&__IPSBAR[0x1208]))
|
||||
#define MCF_FEC_RMON_T_MC_PKT (*(vuint32*)(&__IPSBAR[0x120C]))
|
||||
#define MCF_FEC_RMON_T_CRC_ALIGN (*(vuint32*)(&__IPSBAR[0x1210]))
|
||||
#define MCF_FEC_RMON_T_UNDERSIZE (*(vuint32*)(&__IPSBAR[0x1214]))
|
||||
#define MCF_FEC_RMON_T_OVERSIZE (*(vuint32*)(&__IPSBAR[0x1218]))
|
||||
#define MCF_FEC_RMON_T_FRAG (*(vuint32*)(&__IPSBAR[0x121C]))
|
||||
#define MCF_FEC_RMON_T_JAB (*(vuint32*)(&__IPSBAR[0x1220]))
|
||||
#define MCF_FEC_RMON_T_COL (*(vuint32*)(&__IPSBAR[0x1224]))
|
||||
#define MCF_FEC_RMON_T_P64 (*(vuint32*)(&__IPSBAR[0x1228]))
|
||||
#define MCF_FEC_RMON_T_P65TO127 (*(vuint32*)(&__IPSBAR[0x122C]))
|
||||
#define MCF_FEC_RMON_T_P128TO255 (*(vuint32*)(&__IPSBAR[0x1230]))
|
||||
#define MCF_FEC_RMON_T_P256TO511 (*(vuint32*)(&__IPSBAR[0x1234]))
|
||||
#define MCF_FEC_RMON_T_P512TO1023 (*(vuint32*)(&__IPSBAR[0x1238]))
|
||||
#define MCF_FEC_RMON_T_P1024TO2047 (*(vuint32*)(&__IPSBAR[0x123C]))
|
||||
#define MCF_FEC_RMON_T_P_GTE2048 (*(vuint32*)(&__IPSBAR[0x1240]))
|
||||
#define MCF_FEC_RMON_T_OCTETS (*(vuint32*)(&__IPSBAR[0x1244]))
|
||||
#define MCF_FEC_IEEE_T_DROP (*(vuint32*)(&__IPSBAR[0x1248]))
|
||||
#define MCF_FEC_IEEE_T_FRAME_OK (*(vuint32*)(&__IPSBAR[0x124C]))
|
||||
#define MCF_FEC_IEEE_T_1COL (*(vuint32*)(&__IPSBAR[0x1250]))
|
||||
#define MCF_FEC_IEEE_T_MCOL (*(vuint32*)(&__IPSBAR[0x1254]))
|
||||
#define MCF_FEC_IEEE_T_DEF (*(vuint32*)(&__IPSBAR[0x1258]))
|
||||
#define MCF_FEC_IEEE_T_LCOL (*(vuint32*)(&__IPSBAR[0x125C]))
|
||||
#define MCF_FEC_IEEE_T_EXCOL (*(vuint32*)(&__IPSBAR[0x1260]))
|
||||
#define MCF_FEC_IEEE_T_MACERR (*(vuint32*)(&__IPSBAR[0x1264]))
|
||||
#define MCF_FEC_IEEE_T_CSERR (*(vuint32*)(&__IPSBAR[0x1268]))
|
||||
#define MCF_FEC_IEEE_T_SQE (*(vuint32*)(&__IPSBAR[0x126C]))
|
||||
#define MCF_FEC_IEEE_T_FDXFC (*(vuint32*)(&__IPSBAR[0x1270]))
|
||||
#define MCF_FEC_IEEE_T_OCTETS_OK (*(vuint32*)(&__IPSBAR[0x1274]))
|
||||
#define MCF_FEC_RMON_R_PACKETS (*(vuint32*)(&__IPSBAR[0x1284]))
|
||||
#define MCF_FEC_RMON_R_BC_PKT (*(vuint32*)(&__IPSBAR[0x1288]))
|
||||
#define MCF_FEC_RMON_R_MC_PKT (*(vuint32*)(&__IPSBAR[0x128C]))
|
||||
#define MCF_FEC_RMON_R_CRC_ALIGN (*(vuint32*)(&__IPSBAR[0x1290]))
|
||||
#define MCF_FEC_RMON_R_UNDERSIZE (*(vuint32*)(&__IPSBAR[0x1294]))
|
||||
#define MCF_FEC_RMON_R_OVERSIZE (*(vuint32*)(&__IPSBAR[0x1298]))
|
||||
#define MCF_FEC_RMON_R_FRAG (*(vuint32*)(&__IPSBAR[0x129C]))
|
||||
#define MCF_FEC_RMON_R_JAB (*(vuint32*)(&__IPSBAR[0x12A0]))
|
||||
#define MCF_FEC_RMON_R_RESVD_0 (*(vuint32*)(&__IPSBAR[0x12A4]))
|
||||
#define MCF_FEC_RMON_R_P64 (*(vuint32*)(&__IPSBAR[0x12A8]))
|
||||
#define MCF_FEC_RMON_R_P65TO127 (*(vuint32*)(&__IPSBAR[0x12AC]))
|
||||
#define MCF_FEC_RMON_R_P128TO255 (*(vuint32*)(&__IPSBAR[0x12B0]))
|
||||
#define MCF_FEC_RMON_R_P256TO511 (*(vuint32*)(&__IPSBAR[0x12B4]))
|
||||
#define MCF_FEC_RMON_R_P512TO1023 (*(vuint32*)(&__IPSBAR[0x12B8]))
|
||||
#define MCF_FEC_RMON_R_P1024TO2047 (*(vuint32*)(&__IPSBAR[0x12BC]))
|
||||
#define MCF_FEC_RMON_R_P_GTE2048 (*(vuint32*)(&__IPSBAR[0x12C0]))
|
||||
#define MCF_FEC_RMON_R_OCTETS (*(vuint32*)(&__IPSBAR[0x12C4]))
|
||||
#define MCF_FEC_IEEE_R_DROP (*(vuint32*)(&__IPSBAR[0x12C8]))
|
||||
#define MCF_FEC_IEEE_R_FRAME_OK (*(vuint32*)(&__IPSBAR[0x12CC]))
|
||||
#define MCF_FEC_IEEE_R_CRC (*(vuint32*)(&__IPSBAR[0x12D0]))
|
||||
#define MCF_FEC_IEEE_R_ALIGN (*(vuint32*)(&__IPSBAR[0x12D4]))
|
||||
#define MCF_FEC_IEEE_R_MACERR (*(vuint32*)(&__IPSBAR[0x12D8]))
|
||||
#define MCF_FEC_IEEE_R_FDXFC (*(vuint32*)(&__IPSBAR[0x12DC]))
|
||||
#define MCF_FEC_IEEE_R_OCTETS_OK (*(vuint32*)(&__IPSBAR[0x12E0]))
|
||||
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_EIR */
|
||||
#define MCF_FEC_EIR_UN (0x80000)
|
||||
#define MCF_FEC_EIR_RL (0x100000)
|
||||
#define MCF_FEC_EIR_LC (0x200000)
|
||||
#define MCF_FEC_EIR_EBERR (0x400000)
|
||||
#define MCF_FEC_EIR_MII (0x800000)
|
||||
#define MCF_FEC_EIR_RXB (0x1000000)
|
||||
#define MCF_FEC_EIR_RXF (0x2000000)
|
||||
#define MCF_FEC_EIR_TXB (0x4000000)
|
||||
#define MCF_FEC_EIR_TXF (0x8000000)
|
||||
#define MCF_FEC_EIR_GRA (0x10000000)
|
||||
#define MCF_FEC_EIR_BABT (0x20000000)
|
||||
#define MCF_FEC_EIR_BABR (0x40000000)
|
||||
#define MCF_FEC_EIR_HBERR (0x80000000)
|
||||
#define MCF_FEC_EIR_CLEAR_ALL (0xFFFFFFFF)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_EIMR */
|
||||
#define MCF_FEC_EIMR_UN (0x80000)
|
||||
#define MCF_FEC_EIMR_RL (0x100000)
|
||||
#define MCF_FEC_EIMR_LC (0x200000)
|
||||
#define MCF_FEC_EIMR_EBERR (0x400000)
|
||||
#define MCF_FEC_EIMR_MII (0x800000)
|
||||
#define MCF_FEC_EIMR_RXB (0x1000000)
|
||||
#define MCF_FEC_EIMR_RXF (0x2000000)
|
||||
#define MCF_FEC_EIMR_TXB (0x4000000)
|
||||
#define MCF_FEC_EIMR_TXF (0x8000000)
|
||||
#define MCF_FEC_EIMR_GRA (0x10000000)
|
||||
#define MCF_FEC_EIMR_BABT (0x20000000)
|
||||
#define MCF_FEC_EIMR_BABR (0x40000000)
|
||||
#define MCF_FEC_EIMR_HBERR (0x80000000)
|
||||
#define MCF_FEC_EIMR_MASK_ALL (0)
|
||||
#define MCF_FEC_EIMR_UNMASK_ALL (0xFFFFFFFF)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RDAR */
|
||||
#define MCF_FEC_RDAR_R_DES_ACTIVE (0x1000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_TDAR */
|
||||
#define MCF_FEC_TDAR_X_DES_ACTIVE (0x1000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_ECR */
|
||||
#define MCF_FEC_ECR_RESET (0x1)
|
||||
#define MCF_FEC_ECR_ETHER_EN (0x2)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_MMFR */
|
||||
#define MCF_FEC_MMFR_DATA(x) (((x)&0xFFFF)<<0)
|
||||
#define MCF_FEC_MMFR_TA(x) (((x)&0x3)<<0x10)
|
||||
#define MCF_FEC_MMFR_TA_10 (0x20000)
|
||||
#define MCF_FEC_MMFR_RA(x) (((x)&0x1F)<<0x12)
|
||||
#define MCF_FEC_MMFR_PA(x) (((x)&0x1F)<<0x17)
|
||||
#define MCF_FEC_MMFR_OP(x) (((x)&0x3)<<0x1C)
|
||||
#define MCF_FEC_MMFR_OP_READ (0x20000000)
|
||||
#define MCF_FEC_MMFR_OP_WRITE (0x10000000)
|
||||
#define MCF_FEC_MMFR_ST(x) (((x)&0x3)<<0x1E)
|
||||
#define MCF_FEC_MMFR_ST_01 (0x40000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_MSCR */
|
||||
#define MCF_FEC_MSCR_MII_SPEED(x) (((x)&0x3F)<<0x1)
|
||||
#define MCF_FEC_MSCR_DIS_PREAMBLE (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_MIBC */
|
||||
#define MCF_FEC_MIBC_MIB_IDLE (0x40000000)
|
||||
#define MCF_FEC_MIBC_MIB_DISABLE (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RCR */
|
||||
#define MCF_FEC_RCR_LOOP (0x1)
|
||||
#define MCF_FEC_RCR_DRT (0x2)
|
||||
#define MCF_FEC_RCR_MII_MODE (0x4)
|
||||
#define MCF_FEC_RCR_PROM (0x8)
|
||||
#define MCF_FEC_RCR_BC_REJ (0x10)
|
||||
#define MCF_FEC_RCR_FCE (0x20)
|
||||
#define MCF_FEC_RCR_MAX_FL(x) (((x)&0x7FF)<<0x10)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_TCR */
|
||||
#define MCF_FEC_TCR_GTS (0x1)
|
||||
#define MCF_FEC_TCR_HBC (0x2)
|
||||
#define MCF_FEC_TCR_FDEN (0x4)
|
||||
#define MCF_FEC_TCR_TFC_PAUSE (0x8)
|
||||
#define MCF_FEC_TCR_RFC_PAUSE (0x10)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_PALR */
|
||||
#define MCF_FEC_PALR_PADDR1(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_PAUR */
|
||||
#define MCF_FEC_PAUR_TYPE(x) (((x)&0xFFFF)<<0)
|
||||
#define MCF_FEC_PAUR_PADDR2(x) (((x)&0xFFFF)<<0x10)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_OPD */
|
||||
#define MCF_FEC_OPD_PAUSE_DUR(x) (((x)&0xFFFF)<<0)
|
||||
#define MCF_FEC_OPD_OPCODE(x) (((x)&0xFFFF)<<0x10)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_IAUR */
|
||||
#define MCF_FEC_IAUR_IADDR1(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_IALR */
|
||||
#define MCF_FEC_IALR_IADDR2(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_GAUR */
|
||||
#define MCF_FEC_GAUR_GADDR1(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_GALR */
|
||||
#define MCF_FEC_GALR_GADDR2(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_TFWR */
|
||||
#define MCF_FEC_TFWR_X_WMRK(x) (((x)&0x3)<<0)
|
||||
#define MCF_FEC_TFWR_X_WMRK_64 (0)
|
||||
#define MCF_FEC_TFWR_X_WMRK_128 (0x2)
|
||||
#define MCF_FEC_TFWR_X_WMRK_192 (0x3)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_FRBR */
|
||||
#define MCF_FEC_FRBR_R_BOUND(x) (((x)&0xFF)<<0x2)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_FRSR */
|
||||
#define MCF_FEC_FRSR_R_FSTART(x) (((x)&0xFF)<<0x2)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_ERDSR */
|
||||
#define MCF_FEC_ERDSR_R_DES_START(x) (((x)&0x3FFFFFFF)<<0x2)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_ETSDR */
|
||||
#define MCF_FEC_ETSDR_X_DES_START(x) (((x)&0x3FFFFFFF)<<0x2)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_EMRBR */
|
||||
#define MCF_FEC_EMRBR_R_BUF_SIZE(x) (((x)&0x7F)<<0x4)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_T_DROP */
|
||||
#define MCF_FEC_RMON_T_DROP_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_T_PACKETS */
|
||||
#define MCF_FEC_RMON_T_PACKETS_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_T_BC_PKT */
|
||||
#define MCF_FEC_RMON_T_BC_PKT_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_T_MC_PKT */
|
||||
#define MCF_FEC_RMON_T_MC_PKT_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_T_CRC_ALIGN */
|
||||
#define MCF_FEC_RMON_T_CRC_ALIGN_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_T_UNDERSIZE */
|
||||
#define MCF_FEC_RMON_T_UNDERSIZE_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_T_OVERSIZE */
|
||||
#define MCF_FEC_RMON_T_OVERSIZE_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_T_FRAG */
|
||||
#define MCF_FEC_RMON_T_FRAG_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_T_JAB */
|
||||
#define MCF_FEC_RMON_T_JAB_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_T_COL */
|
||||
#define MCF_FEC_RMON_T_COL_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_T_P64 */
|
||||
#define MCF_FEC_RMON_T_P64_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_T_P65TO127 */
|
||||
#define MCF_FEC_RMON_T_P65TO127_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_T_P128TO255 */
|
||||
#define MCF_FEC_RMON_T_P128TO255_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_T_P256TO511 */
|
||||
#define MCF_FEC_RMON_T_P256TO511_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_T_P512TO1023 */
|
||||
#define MCF_FEC_RMON_T_P512TO1023_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_T_P1024TO2047 */
|
||||
#define MCF_FEC_RMON_T_P1024TO2047_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_T_P_GTE2048 */
|
||||
#define MCF_FEC_RMON_T_P_GTE2048_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_T_OCTETS */
|
||||
#define MCF_FEC_RMON_T_OCTETS_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_IEEE_T_DROP */
|
||||
#define MCF_FEC_IEEE_T_DROP_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_IEEE_T_FRAME_OK */
|
||||
#define MCF_FEC_IEEE_T_FRAME_OK_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_IEEE_T_1COL */
|
||||
#define MCF_FEC_IEEE_T_1COL_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_IEEE_T_MCOL */
|
||||
#define MCF_FEC_IEEE_T_MCOL_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_IEEE_T_DEF */
|
||||
#define MCF_FEC_IEEE_T_DEF_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_IEEE_T_LCOL */
|
||||
#define MCF_FEC_IEEE_T_LCOL_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_IEEE_T_EXCOL */
|
||||
#define MCF_FEC_IEEE_T_EXCOL_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_IEEE_T_MACERR */
|
||||
#define MCF_FEC_IEEE_T_MACERR_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_IEEE_T_CSERR */
|
||||
#define MCF_FEC_IEEE_T_CSERR_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_IEEE_T_SQE */
|
||||
#define MCF_FEC_IEEE_T_SQE_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_IEEE_T_FDXFC */
|
||||
#define MCF_FEC_IEEE_T_FDXFC_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_IEEE_T_OCTETS_OK */
|
||||
#define MCF_FEC_IEEE_T_OCTETS_OK_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_R_PACKETS */
|
||||
#define MCF_FEC_RMON_R_PACKETS_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_R_BC_PKT */
|
||||
#define MCF_FEC_RMON_R_BC_PKT_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_R_MC_PKT */
|
||||
#define MCF_FEC_RMON_R_MC_PKT_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_R_CRC_ALIGN */
|
||||
#define MCF_FEC_RMON_R_CRC_ALIGN_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_R_UNDERSIZE */
|
||||
#define MCF_FEC_RMON_R_UNDERSIZE_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_R_OVERSIZE */
|
||||
#define MCF_FEC_RMON_R_OVERSIZE_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_R_FRAG */
|
||||
#define MCF_FEC_RMON_R_FRAG_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_R_JAB */
|
||||
#define MCF_FEC_RMON_R_JAB_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_R_RESVD_0 */
|
||||
#define MCF_FEC_RMON_R_RESVD_0_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_R_P64 */
|
||||
#define MCF_FEC_RMON_R_P64_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_R_P65TO127 */
|
||||
#define MCF_FEC_RMON_R_P65TO127_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_R_P128TO255 */
|
||||
#define MCF_FEC_RMON_R_P128TO255_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_R_P256TO511 */
|
||||
#define MCF_FEC_RMON_R_P256TO511_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_R_P512TO1023 */
|
||||
#define MCF_FEC_RMON_R_P512TO1023_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_R_P1024TO2047 */
|
||||
#define MCF_FEC_RMON_R_P1024TO2047_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_R_P_GTE2048 */
|
||||
#define MCF_FEC_RMON_R_P_GTE2048_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_R_OCTETS */
|
||||
#define MCF_FEC_RMON_R_OCTETS_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_IEEE_R_DROP */
|
||||
#define MCF_FEC_IEEE_R_DROP_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_IEEE_R_FRAME_OK */
|
||||
#define MCF_FEC_IEEE_R_FRAME_OK_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_IEEE_R_CRC */
|
||||
#define MCF_FEC_IEEE_R_CRC_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_IEEE_R_ALIGN */
|
||||
#define MCF_FEC_IEEE_R_ALIGN_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_IEEE_R_MACERR */
|
||||
#define MCF_FEC_IEEE_R_MACERR_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_IEEE_R_FDXFC */
|
||||
#define MCF_FEC_IEEE_R_FDXFC_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_IEEE_R_OCTETS_OK */
|
||||
#define MCF_FEC_IEEE_R_OCTETS_OK_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
|
||||
#endif /* __MCF52235_FEC_H__ */
|
||||
|
|
@ -0,0 +1,132 @@
|
|||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2007/03/19 Revision: 0.91
|
||||
*/
|
||||
|
||||
#ifndef __MCF52235_FlexCAN_H__
|
||||
#define __MCF52235_FlexCAN_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Flex Controller Area Network (FlexCAN)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_FlexCAN_CANMCR (*(vuint32*)(&__IPSBAR[0x1C0000]))
|
||||
#define MCF_FlexCAN_CANCTRL (*(vuint32*)(&__IPSBAR[0x1C0004]))
|
||||
#define MCF_FlexCAN_TIMER (*(vuint32*)(&__IPSBAR[0x1C0008]))
|
||||
#define MCF_FlexCAN_RXGMASK (*(vuint32*)(&__IPSBAR[0x1C0010]))
|
||||
#define MCF_FlexCAN_RX14MASK (*(vuint32*)(&__IPSBAR[0x1C0014]))
|
||||
#define MCF_FlexCAN_RX15MASK (*(vuint32*)(&__IPSBAR[0x1C0018]))
|
||||
#define MCF_FlexCAN_ERRCNT (*(vuint32*)(&__IPSBAR[0x1C001C]))
|
||||
#define MCF_FlexCAN_ERRSTAT (*(vuint32*)(&__IPSBAR[0x1C0020]))
|
||||
#define MCF_FlexCAN_IMASK (*(vuint32*)(&__IPSBAR[0x1C0028]))
|
||||
#define MCF_FlexCAN_IFLAG (*(vuint32*)(&__IPSBAR[0x1C0030]))
|
||||
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_FlexCAN_CANMCR */
|
||||
#define MCF_FlexCAN_CANMCR_MAXMB(x) (((x)&0xF)<<0)
|
||||
#define MCF_FlexCAN_CANMCR_LPMACK (0x100000)
|
||||
#define MCF_FlexCAN_CANMCR_SUPV (0x800000)
|
||||
#define MCF_FlexCAN_CANMCR_FRZACK (0x1000000)
|
||||
#define MCF_FlexCAN_CANMCR_SOFTRST (0x2000000)
|
||||
#define MCF_FlexCAN_CANMCR_NOTRDY (0x8000000)
|
||||
#define MCF_FlexCAN_CANMCR_HALT (0x10000000)
|
||||
#define MCF_FlexCAN_CANMCR_FRZ (0x40000000)
|
||||
#define MCF_FlexCAN_CANMCR_MDIS (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_FlexCAN_CANCTRL */
|
||||
#define MCF_FlexCAN_CANCTRL_PROPSEG(x) (((x)&0x7)<<0)
|
||||
#define MCF_FlexCAN_CANCTRL_LOM (0x8)
|
||||
#define MCF_FlexCAN_CANCTRL_LBUF (0x10)
|
||||
#define MCF_FlexCAN_CANCTRL_TSYNC (0x20)
|
||||
#define MCF_FlexCAN_CANCTRL_BOFFREC (0x40)
|
||||
#define MCF_FlexCAN_CANCTRL_SAMP (0x80)
|
||||
#define MCF_FlexCAN_CANCTRL_LPB (0x1000)
|
||||
#define MCF_FlexCAN_CANCTRL_CLK_SRC (0x2000)
|
||||
#define MCF_FlexCAN_CANCTRL_ERRMSK (0x4000)
|
||||
#define MCF_FlexCAN_CANCTRL_BOFFMSK (0x8000)
|
||||
#define MCF_FlexCAN_CANCTRL_PSEG2(x) (((x)&0x7)<<0x10)
|
||||
#define MCF_FlexCAN_CANCTRL_PSEG1(x) (((x)&0x7)<<0x13)
|
||||
#define MCF_FlexCAN_CANCTRL_RJW(x) (((x)&0x3)<<0x16)
|
||||
#define MCF_FlexCAN_CANCTRL_PRESDIV(x) (((x)&0xFF)<<0x18)
|
||||
|
||||
/* Bit definitions and macros for MCF_FlexCAN_TIMER */
|
||||
#define MCF_FlexCAN_TIMER_TIMER(x) (((x)&0xFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FlexCAN_RXGMASK */
|
||||
#define MCF_FlexCAN_RXGMASK_MI(x) (((x)&0x1FFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FlexCAN_RX14MASK */
|
||||
#define MCF_FlexCAN_RX14MASK_MI(x) (((x)&0x1FFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FlexCAN_RX15MASK */
|
||||
#define MCF_FlexCAN_RX15MASK_MI(x) (((x)&0x1FFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FlexCAN_ERRCNT */
|
||||
#define MCF_FlexCAN_ERRCNT_TXECTR(x) (((x)&0xFF)<<0)
|
||||
#define MCF_FlexCAN_ERRCNT_RXECTR(x) (((x)&0xFF)<<0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_FlexCAN_ERRSTAT */
|
||||
#define MCF_FlexCAN_ERRSTAT_ERRINT (0x2)
|
||||
#define MCF_FlexCAN_ERRSTAT_BOFFINT (0x4)
|
||||
#define MCF_FlexCAN_ERRSTAT_FLTCONF(x) (((x)&0x3)<<0x4)
|
||||
#define MCF_FlexCAN_ERRSTAT_FLTCONF_ACTIVE (0)
|
||||
#define MCF_FlexCAN_ERRSTAT_FLTCONF_PASSIVE (0x10)
|
||||
#define MCF_FlexCAN_ERRSTAT_FLTCONF_BUSOFF (0x20)
|
||||
#define MCF_FlexCAN_ERRSTAT_TXRX (0x40)
|
||||
#define MCF_FlexCAN_ERRSTAT_IDLE (0x80)
|
||||
#define MCF_FlexCAN_ERRSTAT_RXWRN (0x100)
|
||||
#define MCF_FlexCAN_ERRSTAT_TXWRN (0x200)
|
||||
#define MCF_FlexCAN_ERRSTAT_STFERR (0x400)
|
||||
#define MCF_FlexCAN_ERRSTAT_FRMERR (0x800)
|
||||
#define MCF_FlexCAN_ERRSTAT_CRCERR (0x1000)
|
||||
#define MCF_FlexCAN_ERRSTAT_ACKERR (0x2000)
|
||||
#define MCF_FlexCAN_ERRSTAT_BIT0ERR (0x4000)
|
||||
#define MCF_FlexCAN_ERRSTAT_BIT1ERR (0x8000)
|
||||
|
||||
/* Bit definitions and macros for MCF_FlexCAN_IMASK */
|
||||
#define MCF_FlexCAN_IMASK_BUF0M (0x1)
|
||||
#define MCF_FlexCAN_IMASK_BUF1M (0x2)
|
||||
#define MCF_FlexCAN_IMASK_BUF2M (0x4)
|
||||
#define MCF_FlexCAN_IMASK_BUF3M (0x8)
|
||||
#define MCF_FlexCAN_IMASK_BUF4M (0x10)
|
||||
#define MCF_FlexCAN_IMASK_BUF5M (0x20)
|
||||
#define MCF_FlexCAN_IMASK_BUF6M (0x40)
|
||||
#define MCF_FlexCAN_IMASK_BUF7M (0x80)
|
||||
#define MCF_FlexCAN_IMASK_BUF8M (0x100)
|
||||
#define MCF_FlexCAN_IMASK_BUF9M (0x200)
|
||||
#define MCF_FlexCAN_IMASK_BUF10M (0x400)
|
||||
#define MCF_FlexCAN_IMASK_BUF11M (0x800)
|
||||
#define MCF_FlexCAN_IMASK_BUF12M (0x1000)
|
||||
#define MCF_FlexCAN_IMASK_BUF13M (0x2000)
|
||||
#define MCF_FlexCAN_IMASK_BUF14M (0x4000)
|
||||
#define MCF_FlexCAN_IMASK_BUF15M (0x8000)
|
||||
#define MCF_FlexCAN_IMASK_BUF(x) (0x1<<(x))
|
||||
|
||||
/* Bit definitions and macros for MCF_FlexCAN_IFLAG */
|
||||
#define MCF_FlexCAN_IFLAG_BUF0I (0x1)
|
||||
#define MCF_FlexCAN_IFLAG_BUF1I (0x2)
|
||||
#define MCF_FlexCAN_IFLAG_BUF2I (0x4)
|
||||
#define MCF_FlexCAN_IFLAG_BUF3I (0x8)
|
||||
#define MCF_FlexCAN_IFLAG_BUF4I (0x10)
|
||||
#define MCF_FlexCAN_IFLAG_BUF5I (0x20)
|
||||
#define MCF_FlexCAN_IFLAG_BUF6I (0x40)
|
||||
#define MCF_FlexCAN_IFLAG_BUF7I (0x80)
|
||||
#define MCF_FlexCAN_IFLAG_BUF8I (0x100)
|
||||
#define MCF_FlexCAN_IFLAG_BUF9I (0x200)
|
||||
#define MCF_FlexCAN_IFLAG_BUF10I (0x400)
|
||||
#define MCF_FlexCAN_IFLAG_BUF11I (0x800)
|
||||
#define MCF_FlexCAN_IFLAG_BUF12I (0x1000)
|
||||
#define MCF_FlexCAN_IFLAG_BUF13I (0x2000)
|
||||
#define MCF_FlexCAN_IFLAG_BUF14I (0x4000)
|
||||
#define MCF_FlexCAN_IFLAG_BUF15I (0x8000)
|
||||
#define MCF_FlexCAN_IFLAG_BUF(x) (0x1<<(x))
|
||||
|
||||
|
||||
#endif /* __MCF52235_FlexCAN_H__ */
|
||||
|
|
@ -0,0 +1,37 @@
|
|||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2007/03/19 Revision: 0.91
|
||||
*/
|
||||
|
||||
#ifndef __MCF52235_GIACR_H__
|
||||
#define __MCF52235_GIACR_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Global Interrupt Acknowledge Control Registers Module (GIACR)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_GIACR_GSWIACK (*(vuint8 *)(&__IPSBAR[0xFE0]))
|
||||
#define MCF_GIACR_GL1IACK (*(vuint8 *)(&__IPSBAR[0xFE4]))
|
||||
#define MCF_GIACR_GL2IACK (*(vuint8 *)(&__IPSBAR[0xFE8]))
|
||||
#define MCF_GIACR_GL3IACK (*(vuint8 *)(&__IPSBAR[0xFEC]))
|
||||
#define MCF_GIACR_GL4IACK (*(vuint8 *)(&__IPSBAR[0xFF0]))
|
||||
#define MCF_GIACR_GL5IACK (*(vuint8 *)(&__IPSBAR[0xFF4]))
|
||||
#define MCF_GIACR_GL6IACK (*(vuint8 *)(&__IPSBAR[0xFF8]))
|
||||
#define MCF_GIACR_GL7IACK (*(vuint8 *)(&__IPSBAR[0xFFC]))
|
||||
#define MCF_GIACR_GLIACK(x) (*(vuint8 *)(&__IPSBAR[0xFE4 + ((x-1)*0x4)]))
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_GIACR_GSWIACK */
|
||||
#define MCF_GIACR_GSWIACK_VECTOR(x) (((x)&0xFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_GIACR_GLIACK */
|
||||
#define MCF_GIACR_GLIACK_VECTOR(x) (((x)&0xFF)<<0)
|
||||
|
||||
|
||||
#endif /* __MCF52235_GIACR_H__ */
|
||||
795
Demo/ColdFire_MCF52233_Eclipse/RTOSDemo/MCF5223x/MCF52235_GPIO.h
Normal file
795
Demo/ColdFire_MCF52233_Eclipse/RTOSDemo/MCF5223x/MCF52235_GPIO.h
Normal file
|
|
@ -0,0 +1,795 @@
|
|||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2007/03/19 Revision: 0.91
|
||||
*/
|
||||
|
||||
#ifndef __MCF52235_GPIO_H__
|
||||
#define __MCF52235_GPIO_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* General Purpose I/O (GPIO)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_GPIO_PORTNQ (*(vuint8 *)(&__IPSBAR[0x100008]))
|
||||
#define MCF_GPIO_DDRNQ (*(vuint8 *)(&__IPSBAR[0x100020]))
|
||||
#define MCF_GPIO_SETNQ (*(vuint8 *)(&__IPSBAR[0x100038]))
|
||||
#define MCF_GPIO_CLRNQ (*(vuint8 *)(&__IPSBAR[0x100050]))
|
||||
#define MCF_GPIO_PNQPAR (*(vuint16*)(&__IPSBAR[0x100068]))
|
||||
|
||||
#define MCF_GPIO_PORTAN (*(vuint8 *)(&__IPSBAR[0x10000A]))
|
||||
#define MCF_GPIO_DDRAN (*(vuint8 *)(&__IPSBAR[0x100022]))
|
||||
#define MCF_GPIO_SETAN (*(vuint8 *)(&__IPSBAR[0x10003A]))
|
||||
#define MCF_GPIO_CLRAN (*(vuint8 *)(&__IPSBAR[0x100052]))
|
||||
#define MCF_GPIO_PANPAR (*(vuint8 *)(&__IPSBAR[0x10006A]))
|
||||
|
||||
#define MCF_GPIO_PORTAS (*(vuint8 *)(&__IPSBAR[0x10000B]))
|
||||
#define MCF_GPIO_DDRAS (*(vuint8 *)(&__IPSBAR[0x100023]))
|
||||
#define MCF_GPIO_SETAS (*(vuint8 *)(&__IPSBAR[0x10003B]))
|
||||
#define MCF_GPIO_CLRAS (*(vuint8 *)(&__IPSBAR[0x100053]))
|
||||
#define MCF_GPIO_PASPAR (*(vuint8 *)(&__IPSBAR[0x10006B]))
|
||||
|
||||
#define MCF_GPIO_PORTQS (*(vuint8 *)(&__IPSBAR[0x10000C]))
|
||||
#define MCF_GPIO_DDRQS (*(vuint8 *)(&__IPSBAR[0x100024]))
|
||||
#define MCF_GPIO_SETQS (*(vuint8 *)(&__IPSBAR[0x10003C]))
|
||||
#define MCF_GPIO_CLRQS (*(vuint8 *)(&__IPSBAR[0x100054]))
|
||||
#define MCF_GPIO_PQSPAR (*(vuint16*)(&__IPSBAR[0x10006C]))
|
||||
|
||||
#define MCF_GPIO_PORTTA (*(vuint8 *)(&__IPSBAR[0x10000E]))
|
||||
#define MCF_GPIO_DDRTA (*(vuint8 *)(&__IPSBAR[0x100026]))
|
||||
#define MCF_GPIO_SETTA (*(vuint8 *)(&__IPSBAR[0x10003E]))
|
||||
#define MCF_GPIO_CLRTA (*(vuint8 *)(&__IPSBAR[0x100056]))
|
||||
#define MCF_GPIO_PTAPAR (*(vuint8 *)(&__IPSBAR[0x10006E]))
|
||||
|
||||
#define MCF_GPIO_PORTTC (*(vuint8 *)(&__IPSBAR[0x10000F]))
|
||||
#define MCF_GPIO_DDRTC (*(vuint8 *)(&__IPSBAR[0x100027]))
|
||||
#define MCF_GPIO_SETTC (*(vuint8 *)(&__IPSBAR[0x10003F]))
|
||||
#define MCF_GPIO_CLRTC (*(vuint8 *)(&__IPSBAR[0x100057]))
|
||||
#define MCF_GPIO_PTCPAR (*(vuint8 *)(&__IPSBAR[0x10006F]))
|
||||
|
||||
#define MCF_GPIO_PORTTD (*(vuint8 *)(&__IPSBAR[0x100010]))
|
||||
#define MCF_GPIO_DDRTD (*(vuint8 *)(&__IPSBAR[0x100028]))
|
||||
#define MCF_GPIO_SETTD (*(vuint8 *)(&__IPSBAR[0x100040]))
|
||||
#define MCF_GPIO_CLRTD (*(vuint8 *)(&__IPSBAR[0x100058]))
|
||||
#define MCF_GPIO_PTDPAR (*(vuint8 *)(&__IPSBAR[0x100070]))
|
||||
|
||||
#define MCF_GPIO_PORTUA (*(vuint8 *)(&__IPSBAR[0x100011]))
|
||||
#define MCF_GPIO_DDRUA (*(vuint8 *)(&__IPSBAR[0x100029]))
|
||||
#define MCF_GPIO_SETUA (*(vuint8 *)(&__IPSBAR[0x100041]))
|
||||
#define MCF_GPIO_CLRUA (*(vuint8 *)(&__IPSBAR[0x100059]))
|
||||
#define MCF_GPIO_PUAPAR (*(vuint8 *)(&__IPSBAR[0x100071]))
|
||||
|
||||
#define MCF_GPIO_PORTUB (*(vuint8 *)(&__IPSBAR[0x100012]))
|
||||
#define MCF_GPIO_DDRUB (*(vuint8 *)(&__IPSBAR[0x10002A]))
|
||||
#define MCF_GPIO_SETUB (*(vuint8 *)(&__IPSBAR[0x100042]))
|
||||
#define MCF_GPIO_CLRUB (*(vuint8 *)(&__IPSBAR[0x10005A]))
|
||||
#define MCF_GPIO_PUBPAR (*(vuint8 *)(&__IPSBAR[0x100072]))
|
||||
|
||||
#define MCF_GPIO_PORTUC (*(vuint8 *)(&__IPSBAR[0x100013]))
|
||||
#define MCF_GPIO_DDRUC (*(vuint8 *)(&__IPSBAR[0x10002B]))
|
||||
#define MCF_GPIO_SETUC (*(vuint8 *)(&__IPSBAR[0x100043]))
|
||||
#define MCF_GPIO_CLRUC (*(vuint8 *)(&__IPSBAR[0x10005B]))
|
||||
#define MCF_GPIO_PUCPAR (*(vuint8 *)(&__IPSBAR[0x100073]))
|
||||
|
||||
#define MCF_GPIO_PORTDD (*(vuint8 *)(&__IPSBAR[0x100014]))
|
||||
#define MCF_GPIO_DDRDD (*(vuint8 *)(&__IPSBAR[0x10002C]))
|
||||
#define MCF_GPIO_SETDD (*(vuint8 *)(&__IPSBAR[0x100044]))
|
||||
#define MCF_GPIO_CLRDD (*(vuint8 *)(&__IPSBAR[0x10005C]))
|
||||
#define MCF_GPIO_PDDPAR (*(vuint8 *)(&__IPSBAR[0x100074]))
|
||||
|
||||
#define MCF_GPIO_PORTLD (*(vuint8 *)(&__IPSBAR[0x100015]))
|
||||
#define MCF_GPIO_DDRLD (*(vuint8 *)(&__IPSBAR[0x10002D]))
|
||||
#define MCF_GPIO_SETLD (*(vuint8 *)(&__IPSBAR[0x100045]))
|
||||
#define MCF_GPIO_CLRLD (*(vuint8 *)(&__IPSBAR[0x10005D]))
|
||||
#define MCF_GPIO_PLDPAR (*(vuint8 *)(&__IPSBAR[0x100075]))
|
||||
|
||||
#define MCF_GPIO_PORTGP (*(vuint8 *)(&__IPSBAR[0x100016]))
|
||||
#define MCF_GPIO_DDRGP (*(vuint8 *)(&__IPSBAR[0x10002E]))
|
||||
#define MCF_GPIO_SETGP (*(vuint8 *)(&__IPSBAR[0x100046]))
|
||||
#define MCF_GPIO_CLRGP (*(vuint8 *)(&__IPSBAR[0x10005E]))
|
||||
#define MCF_GPIO_PGPPAR (*(vuint8 *)(&__IPSBAR[0x100076]))
|
||||
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PORTNQ */
|
||||
#define MCF_GPIO_PORTNQ_PORTNQ1 (0x2)
|
||||
#define MCF_GPIO_PORTNQ_PORTNQ2 (0x4)
|
||||
#define MCF_GPIO_PORTNQ_PORTNQ3 (0x8)
|
||||
#define MCF_GPIO_PORTNQ_PORTNQ4 (0x10)
|
||||
#define MCF_GPIO_PORTNQ_PORTNQ5 (0x20)
|
||||
#define MCF_GPIO_PORTNQ_PORTNQ6 (0x40)
|
||||
#define MCF_GPIO_PORTNQ_PORTNQ7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_DDRNQ */
|
||||
#define MCF_GPIO_DDRNQ_DDRNQ1 (0x2)
|
||||
#define MCF_GPIO_DDRNQ_DDRNQ2 (0x4)
|
||||
#define MCF_GPIO_DDRNQ_DDRNQ3 (0x8)
|
||||
#define MCF_GPIO_DDRNQ_DDRNQ4 (0x10)
|
||||
#define MCF_GPIO_DDRNQ_DDRNQ5 (0x20)
|
||||
#define MCF_GPIO_DDRNQ_DDRNQ6 (0x40)
|
||||
#define MCF_GPIO_DDRNQ_DDRNQ7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_SETNQ */
|
||||
#define MCF_GPIO_SETNQ_SETNQ1 (0x2)
|
||||
#define MCF_GPIO_SETNQ_SETNQ2 (0x4)
|
||||
#define MCF_GPIO_SETNQ_SETNQ3 (0x8)
|
||||
#define MCF_GPIO_SETNQ_SETNQ4 (0x10)
|
||||
#define MCF_GPIO_SETNQ_SETNQ5 (0x20)
|
||||
#define MCF_GPIO_SETNQ_SETNQ6 (0x40)
|
||||
#define MCF_GPIO_SETNQ_SETNQ7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_CLRNQ */
|
||||
#define MCF_GPIO_CLRNQ_CLRNQ1 (0x2)
|
||||
#define MCF_GPIO_CLRNQ_CLRNQ2 (0x4)
|
||||
#define MCF_GPIO_CLRNQ_CLRNQ3 (0x8)
|
||||
#define MCF_GPIO_CLRNQ_CLRNQ4 (0x10)
|
||||
#define MCF_GPIO_CLRNQ_CLRNQ5 (0x20)
|
||||
#define MCF_GPIO_CLRNQ_CLRNQ6 (0x40)
|
||||
#define MCF_GPIO_CLRNQ_CLRNQ7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PNQPAR */
|
||||
#define MCF_GPIO_PNQPAR_PNQPAR1(x) (((x)&0x3)<<0x2)
|
||||
#define MCF_GPIO_PNQPAR_IRQ1_GPIO (0)
|
||||
#define MCF_GPIO_PNQPAR_IRQ1_IRQ1 (0x4)
|
||||
#define MCF_GPIO_PNQPAR_IRQ1_SYNCA (0x8)
|
||||
#define MCF_GPIO_PNQPAR_IRQ1_PWM1 (0xC)
|
||||
#define MCF_GPIO_PNQPAR_PNQPAR2(x) (((x)&0x3)<<0x4)
|
||||
#define MCF_GPIO_PNQPAR_IRQ2_GPIO (0)
|
||||
#define MCF_GPIO_PNQPAR_IRQ2_IRQ2 (0x10)
|
||||
#define MCF_GPIO_PNQPAR_IRQ2_FEC_RXD3 (0x30)
|
||||
#define MCF_GPIO_PNQPAR_PNQPAR3(x) (((x)&0x3)<<0x6)
|
||||
#define MCF_GPIO_PNQPAR_IRQ3_GPIO (0)
|
||||
#define MCF_GPIO_PNQPAR_IRQ3_IRQ3 (0x40)
|
||||
#define MCF_GPIO_PNQPAR_IRQ3_FEC_RXD2 (0xC0)
|
||||
#define MCF_GPIO_PNQPAR_PNQPAR4(x) (((x)&0x3)<<0x8)
|
||||
#define MCF_GPIO_PNQPAR_IRQ4_GPIO (0)
|
||||
#define MCF_GPIO_PNQPAR_IRQ4_IRQ4 (0x100)
|
||||
#define MCF_GPIO_PNQPAR_PNQPAR5(x) (((x)&0x3)<<0xA)
|
||||
#define MCF_GPIO_PNQPAR_IRQ5_GPIO (0)
|
||||
#define MCF_GPIO_PNQPAR_IRQ5_IRQ5 (0x400)
|
||||
#define MCF_GPIO_PNQPAR_IRQ5_FEC_RXD1 (0xC00)
|
||||
#define MCF_GPIO_PNQPAR_PNQPAR6(x) (((x)&0x3)<<0xC)
|
||||
#define MCF_GPIO_PNQPAR_IRQ6_GPIO (0)
|
||||
#define MCF_GPIO_PNQPAR_IRQ6_IRQ6 (0x1000)
|
||||
#define MCF_GPIO_PNQPAR_IRQ6_FEC_RXER (0x3000)
|
||||
#define MCF_GPIO_PNQPAR_PNQPAR7(x) (((x)&0x3)<<0xE)
|
||||
#define MCF_GPIO_PNQPAR_IRQ7_GPIO (0)
|
||||
#define MCF_GPIO_PNQPAR_IRQ7_IRQ7 (0x4000)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PORTAN */
|
||||
#define MCF_GPIO_PORTAN_PORTAN0 (0x1)
|
||||
#define MCF_GPIO_PORTAN_PORTAN1 (0x2)
|
||||
#define MCF_GPIO_PORTAN_PORTAN2 (0x4)
|
||||
#define MCF_GPIO_PORTAN_PORTAN3 (0x8)
|
||||
#define MCF_GPIO_PORTAN_PORTAN4 (0x10)
|
||||
#define MCF_GPIO_PORTAN_PORTAN5 (0x20)
|
||||
#define MCF_GPIO_PORTAN_PORTAN6 (0x40)
|
||||
#define MCF_GPIO_PORTAN_PORTAN7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_DDRAN */
|
||||
#define MCF_GPIO_DDRAN_DDRAN0 (0x1)
|
||||
#define MCF_GPIO_DDRAN_DDRAN1 (0x2)
|
||||
#define MCF_GPIO_DDRAN_DDRAN2 (0x4)
|
||||
#define MCF_GPIO_DDRAN_DDRAN3 (0x8)
|
||||
#define MCF_GPIO_DDRAN_DDRAN4 (0x10)
|
||||
#define MCF_GPIO_DDRAN_DDRAN5 (0x20)
|
||||
#define MCF_GPIO_DDRAN_DDRAN6 (0x40)
|
||||
#define MCF_GPIO_DDRAN_DDRAN7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_SETAN */
|
||||
#define MCF_GPIO_SETAN_SETAN0 (0x1)
|
||||
#define MCF_GPIO_SETAN_SETAN1 (0x2)
|
||||
#define MCF_GPIO_SETAN_SETAN2 (0x4)
|
||||
#define MCF_GPIO_SETAN_SETAN3 (0x8)
|
||||
#define MCF_GPIO_SETAN_SETAN4 (0x10)
|
||||
#define MCF_GPIO_SETAN_SETAN5 (0x20)
|
||||
#define MCF_GPIO_SETAN_SETAN6 (0x40)
|
||||
#define MCF_GPIO_SETAN_SETAN7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_CLRAN */
|
||||
#define MCF_GPIO_CLRAN_CLRAN0 (0x1)
|
||||
#define MCF_GPIO_CLRAN_CLRAN1 (0x2)
|
||||
#define MCF_GPIO_CLRAN_CLRAN2 (0x4)
|
||||
#define MCF_GPIO_CLRAN_CLRAN3 (0x8)
|
||||
#define MCF_GPIO_CLRAN_CLRAN4 (0x10)
|
||||
#define MCF_GPIO_CLRAN_CLRAN5 (0x20)
|
||||
#define MCF_GPIO_CLRAN_CLRAN6 (0x40)
|
||||
#define MCF_GPIO_CLRAN_CLRAN7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PANPAR */
|
||||
#define MCF_GPIO_PANPAR_PANPAR0 (0x1)
|
||||
#define MCF_GPIO_PANPAR_AN0_GPIO (0)
|
||||
#define MCF_GPIO_PANPAR_AN0_AN0 (0x1)
|
||||
#define MCF_GPIO_PANPAR_PANPAR1 (0x2)
|
||||
#define MCF_GPIO_PANPAR_AN1_GPIO (0)
|
||||
#define MCF_GPIO_PANPAR_AN1_AN1 (0x2)
|
||||
#define MCF_GPIO_PANPAR_PANPAR2 (0x4)
|
||||
#define MCF_GPIO_PANPAR_AN2_GPIO (0)
|
||||
#define MCF_GPIO_PANPAR_AN2_AN2 (0x4)
|
||||
#define MCF_GPIO_PANPAR_PANPAR3 (0x8)
|
||||
#define MCF_GPIO_PANPAR_AN3_GPIO (0)
|
||||
#define MCF_GPIO_PANPAR_AN3_AN3 (0x8)
|
||||
#define MCF_GPIO_PANPAR_PANPAR4 (0x10)
|
||||
#define MCF_GPIO_PANPAR_AN4_GPIO (0)
|
||||
#define MCF_GPIO_PANPAR_AN4_AN4 (0x10)
|
||||
#define MCF_GPIO_PANPAR_PANPAR5 (0x20)
|
||||
#define MCF_GPIO_PANPAR_AN5_GPIO (0)
|
||||
#define MCF_GPIO_PANPAR_AN5_AN5 (0x20)
|
||||
#define MCF_GPIO_PANPAR_PANPAR6 (0x40)
|
||||
#define MCF_GPIO_PANPAR_AN6_GPIO (0)
|
||||
#define MCF_GPIO_PANPAR_AN6_AN6 (0x40)
|
||||
#define MCF_GPIO_PANPAR_PANPAR7 (0x80)
|
||||
#define MCF_GPIO_PANPAR_AN7_GPIO (0)
|
||||
#define MCF_GPIO_PANPAR_AN7_AN7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PORTAS */
|
||||
#define MCF_GPIO_PORTAS_PORTAS0 (0x1)
|
||||
#define MCF_GPIO_PORTAS_PORTAS1 (0x2)
|
||||
#define MCF_GPIO_PORTAS_PORTAS2 (0x4)
|
||||
#define MCF_GPIO_PORTAS_PORTAS3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_DDRAS */
|
||||
#define MCF_GPIO_DDRAS_DDRAS0 (0x1)
|
||||
#define MCF_GPIO_DDRAS_DDRAS1 (0x2)
|
||||
#define MCF_GPIO_DDRAS_DDRAS2 (0x4)
|
||||
#define MCF_GPIO_DDRAS_DDRAS3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_SETAS */
|
||||
#define MCF_GPIO_SETAS_SETAS0 (0x1)
|
||||
#define MCF_GPIO_SETAS_SETAS1 (0x2)
|
||||
#define MCF_GPIO_SETAS_SETAS2 (0x4)
|
||||
#define MCF_GPIO_SETAS_SETAS3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_CLRAS */
|
||||
#define MCF_GPIO_CLRAS_CLRAS0 (0x1)
|
||||
#define MCF_GPIO_CLRAS_CLRAS1 (0x2)
|
||||
#define MCF_GPIO_CLRAS_CLRAS2 (0x4)
|
||||
#define MCF_GPIO_CLRAS_CLRAS3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PASPAR */
|
||||
#define MCF_GPIO_PASPAR_PASPAR0(x) (((x)&0x3)<<0)
|
||||
#define MCF_GPIO_PASPAR_SCL_GPIO (0)
|
||||
#define MCF_GPIO_PASPAR_SCL_SCL (0x1)
|
||||
#define MCF_GPIO_PASPAR_SCL_CANTX (0x2)
|
||||
#define MCF_GPIO_PASPAR_SCL_UTXD2 (0x3)
|
||||
#define MCF_GPIO_PASPAR_PASPAR1(x) (((x)&0x3)<<0x2)
|
||||
#define MCF_GPIO_PASPAR_SDA_GPIO (0)
|
||||
#define MCF_GPIO_PASPAR_SDA_SDA (0x4)
|
||||
#define MCF_GPIO_PASPAR_SDA_CANRX (0x8)
|
||||
#define MCF_GPIO_PASPAR_SDA_URXD2 (0xC)
|
||||
#define MCF_GPIO_PASPAR_PASPAR2(x) (((x)&0x3)<<0x4)
|
||||
#define MCF_GPIO_PASPAR_SYNCB_GPIO (0)
|
||||
#define MCF_GPIO_PASPAR_SYNCB_SYNCB (0x10)
|
||||
#define MCF_GPIO_PASPAR_SYNCB_CANTX (0x20)
|
||||
#define MCF_GPIO_PASPAR_SYNCB_FEC_MDC (0x30)
|
||||
#define MCF_GPIO_PASPAR_PASPAR3(x) (((x)&0x3)<<0x6)
|
||||
#define MCF_GPIO_PASPAR_SYNCA_GPIO (0)
|
||||
#define MCF_GPIO_PASPAR_SYNCA_SYNCA (0x40)
|
||||
#define MCF_GPIO_PASPAR_SYNCA_CANRX (0x80)
|
||||
#define MCF_GPIO_PASPAR_SYNC_FEC_MDIO (0xC0)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PORTQS */
|
||||
#define MCF_GPIO_PORTQS_PORTQS0 (0x1)
|
||||
#define MCF_GPIO_PORTQS_PORTQS1 (0x2)
|
||||
#define MCF_GPIO_PORTQS_PORTQS2 (0x4)
|
||||
#define MCF_GPIO_PORTQS_PORTQS3 (0x8)
|
||||
#define MCF_GPIO_PORTQS_PORTQS4 (0x10)
|
||||
#define MCF_GPIO_PORTQS_PORTQS5 (0x20)
|
||||
#define MCF_GPIO_PORTQS_PORTQS6 (0x40)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_DDRQS */
|
||||
#define MCF_GPIO_DDRQS_DDRQS0 (0x1)
|
||||
#define MCF_GPIO_DDRQS_DDRQS1 (0x2)
|
||||
#define MCF_GPIO_DDRQS_DDRQS2 (0x4)
|
||||
#define MCF_GPIO_DDRQS_DDRQS3 (0x8)
|
||||
#define MCF_GPIO_DDRQS_DDRQS4 (0x10)
|
||||
#define MCF_GPIO_DDRQS_DDRQS5 (0x20)
|
||||
#define MCF_GPIO_DDRQS_DDRQS6 (0x40)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_SETQS */
|
||||
#define MCF_GPIO_SETQS_SETQS0 (0x1)
|
||||
#define MCF_GPIO_SETQS_SETQS1 (0x2)
|
||||
#define MCF_GPIO_SETQS_SETQS2 (0x4)
|
||||
#define MCF_GPIO_SETQS_SETQS3 (0x8)
|
||||
#define MCF_GPIO_SETQS_SETQS4 (0x10)
|
||||
#define MCF_GPIO_SETQS_SETQS5 (0x20)
|
||||
#define MCF_GPIO_SETQS_SETQS6 (0x40)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_CLRQS */
|
||||
#define MCF_GPIO_CLRQS_CLRQS0 (0x1)
|
||||
#define MCF_GPIO_CLRQS_CLRQS1 (0x2)
|
||||
#define MCF_GPIO_CLRQS_CLRQS2 (0x4)
|
||||
#define MCF_GPIO_CLRQS_CLRQS3 (0x8)
|
||||
#define MCF_GPIO_CLRQS_CLRQS4 (0x10)
|
||||
#define MCF_GPIO_CLRQS_CLRQS5 (0x20)
|
||||
#define MCF_GPIO_CLRQS_CLRQS6 (0x40)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PQSPAR */
|
||||
#define MCF_GPIO_PQSPAR_PQSPAR0(x) (((x)&0x3)<<0)
|
||||
#define MCF_GPIO_PQSPAR_QSPI_DOUT_GPIO (0)
|
||||
#define MCF_GPIO_PQSPAR_QSPI_DOUT_DOUT (0x1)
|
||||
#define MCF_GPIO_PQSPAR_QSPI_DOUT_CANTX (0x2)
|
||||
#define MCF_GPIO_PQSPAR_QSPI_DOUT_UTXD1 (0x3)
|
||||
#define MCF_GPIO_PQSPAR_PQSPAR1(x) (((x)&0x3)<<0x2)
|
||||
#define MCF_GPIO_PQSPAR_QSPI_DIN_GPIO (0)
|
||||
#define MCF_GPIO_PQSPAR_QSPI_DIN_DIN (0x4)
|
||||
#define MCF_GPIO_PQSPAR_QSPI_DIN_CANRX (0x8)
|
||||
#define MCF_GPIO_PQSPAR_QSPI_DIN_URXD1 (0xC)
|
||||
#define MCF_GPIO_PQSPAR_PQSPAR2(x) (((x)&0x3)<<0x4)
|
||||
#define MCF_GPIO_PQSPAR_QSPI_CLK_GPIO (0)
|
||||
#define MCF_GPIO_PQSPAR_QSPI_CLK_CLK (0x10)
|
||||
#define MCF_GPIO_PQSPAR_QSPI_CLK_SCL (0x20)
|
||||
#define MCF_GPIO_PQSPAR_QSPI_CLK_URTS1 (0x30)
|
||||
#define MCF_GPIO_PQSPAR_PQSPAR3(x) (((x)&0x3)<<0x6)
|
||||
#define MCF_GPIO_PQSPAR_QSPI_CS0_GPIO (0)
|
||||
#define MCF_GPIO_PQSPAR_QSPI_CS0_CS0 (0x40)
|
||||
#define MCF_GPIO_PQSPAR_QSPI_CS0_SDA (0x80)
|
||||
#define MCF_GPIO_PQSPAR_QSPI_CS0_UCTS1 (0xC0)
|
||||
#define MCF_GPIO_PQSPAR_PQSPAR4(x) (((x)&0x3)<<0x8)
|
||||
#define MCF_GPIO_PQSPAR_QSPI_CS1_GPIO (0)
|
||||
#define MCF_GPIO_PQSPAR_QSPI_CS1_CS1 (0x100)
|
||||
#define MCF_GPIO_PQSPAR_QSPI_CS1_FEC_TXEN (0x300)
|
||||
#define MCF_GPIO_PQSPAR_PQSPAR5(x) (((x)&0x3)<<0xA)
|
||||
#define MCF_GPIO_PQSPAR_QSPI_CS2_GPIO (0)
|
||||
#define MCF_GPIO_PQSPAR_QSPI_CS2_CS2 (0x400)
|
||||
#define MCF_GPIO_PQSPAR_QSPI_CS2_FEC_TXCLK (0xC00)
|
||||
#define MCF_GPIO_PQSPAR_PQSPAR6(x) (((x)&0x3)<<0xC)
|
||||
#define MCF_GPIO_PQSPAR_QSPI_CS3_GPIO (0)
|
||||
#define MCF_GPIO_PQSPAR_QSPI_CS3_CS3 (0x1000)
|
||||
#define MCF_GPIO_PQSPAR_QSPI_CS3_SYNCA (0x2000)
|
||||
#define MCF_GPIO_PQSPAR_QSPI_CS3_SYNCB (0x3000)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PORTTA */
|
||||
#define MCF_GPIO_PORTTA_PORTTA0 (0x1)
|
||||
#define MCF_GPIO_PORTTA_PORTTA1 (0x2)
|
||||
#define MCF_GPIO_PORTTA_PORTTA2 (0x4)
|
||||
#define MCF_GPIO_PORTTA_PORTTA3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_DDRTA */
|
||||
#define MCF_GPIO_DDRTA_DDRTA0 (0x1)
|
||||
#define MCF_GPIO_DDRTA_DDRTA1 (0x2)
|
||||
#define MCF_GPIO_DDRTA_DDRTA2 (0x4)
|
||||
#define MCF_GPIO_DDRTA_DDRTA3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_SETTA */
|
||||
#define MCF_GPIO_SETTA_SETTA0 (0x1)
|
||||
#define MCF_GPIO_SETTA_SETTA1 (0x2)
|
||||
#define MCF_GPIO_SETTA_SETTA2 (0x4)
|
||||
#define MCF_GPIO_SETTA_SETTA3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_CLRTA */
|
||||
#define MCF_GPIO_CLRTA_CLRTA0 (0x1)
|
||||
#define MCF_GPIO_CLRTA_CLRTA1 (0x2)
|
||||
#define MCF_GPIO_CLRTA_CLRTA2 (0x4)
|
||||
#define MCF_GPIO_CLRTA_CLRTA3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PTAPAR */
|
||||
#define MCF_GPIO_PTAPAR_PTAPAR0(x) (((x)&0x3)<<0)
|
||||
#define MCF_GPIO_PTAPAR_GPT0_GPIO (0)
|
||||
#define MCF_GPIO_PTAPAR_GPT0_GPT0 (0x1)
|
||||
#define MCF_GPIO_PTAPAR_GPT0_FEC_TXER (0x2)
|
||||
#define MCF_GPIO_PTAPAR_GPT0_PWM1 (0x3)
|
||||
#define MCF_GPIO_PTAPAR_PTAPAR1(x) (((x)&0x3)<<0x2)
|
||||
#define MCF_GPIO_PTAPAR_GPT1_GPIO (0)
|
||||
#define MCF_GPIO_PTAPAR_GPT1_GPT1 (0x4)
|
||||
#define MCF_GPIO_PTAPAR_GPT1_FEC_TXD1 (0x8)
|
||||
#define MCF_GPIO_PTAPAR_GPT1_PWM3 (0xC)
|
||||
#define MCF_GPIO_PTAPAR_PTAPAR2(x) (((x)&0x3)<<0x4)
|
||||
#define MCF_GPIO_PTAPAR_GPT2_GPIO (0)
|
||||
#define MCF_GPIO_PTAPAR_GPT2_GPT2 (0x10)
|
||||
#define MCF_GPIO_PTAPAR_GPT2_FEC_TXD2 (0x20)
|
||||
#define MCF_GPIO_PTAPAR_GPT2_PWM5 (0x30)
|
||||
#define MCF_GPIO_PTAPAR_PTAPAR3(x) (((x)&0x3)<<0x6)
|
||||
#define MCF_GPIO_PTAPAR_GPT3_GPIO (0)
|
||||
#define MCF_GPIO_PTAPAR_GPT3_GPT3 (0x40)
|
||||
#define MCF_GPIO_PTAPAR_GPT3_FEC_TXD3 (0x80)
|
||||
#define MCF_GPIO_PTAPAR_GPT3_PWM7 (0xC0)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PORTTC */
|
||||
#define MCF_GPIO_PORTTC_PORTTC0 (0x1)
|
||||
#define MCF_GPIO_PORTTC_PORTTC1 (0x2)
|
||||
#define MCF_GPIO_PORTTC_PORTTC2 (0x4)
|
||||
#define MCF_GPIO_PORTTC_PORTTC3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_DDRTC */
|
||||
#define MCF_GPIO_DDRTC_DDRTC0 (0x1)
|
||||
#define MCF_GPIO_DDRTC_DDRTC1 (0x2)
|
||||
#define MCF_GPIO_DDRTC_DDRTC2 (0x4)
|
||||
#define MCF_GPIO_DDRTC_DDRTC3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_SETTC */
|
||||
#define MCF_GPIO_SETTC_SETTC0 (0x1)
|
||||
#define MCF_GPIO_SETTC_SETTC1 (0x2)
|
||||
#define MCF_GPIO_SETTC_SETTC2 (0x4)
|
||||
#define MCF_GPIO_SETTC_SETTC3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_CLRTC */
|
||||
#define MCF_GPIO_CLRTC_CLRTC0 (0x1)
|
||||
#define MCF_GPIO_CLRTC_CLRTC1 (0x2)
|
||||
#define MCF_GPIO_CLRTC_CLRTC2 (0x4)
|
||||
#define MCF_GPIO_CLRTC_CLRTC3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PTCPAR */
|
||||
#define MCF_GPIO_PTCPAR_PTCPAR0(x) (((x)&0x3)<<0)
|
||||
#define MCF_GPIO_PTCPAR_DTIN0_GPIO (0)
|
||||
#define MCF_GPIO_PTCPAR_DTIN0_DTIN0 (0x1)
|
||||
#define MCF_GPIO_PTCPAR_DTIN0_DTOUT0 (0x2)
|
||||
#define MCF_GPIO_PTCPAR_DTIN0_PWM0 (0x3)
|
||||
#define MCF_GPIO_PTCPAR_PTCPAR1(x) (((x)&0x3)<<0x2)
|
||||
#define MCF_GPIO_PTCPAR_DTIN1_GPIO (0)
|
||||
#define MCF_GPIO_PTCPAR_DTIN1_DTIN1 (0x4)
|
||||
#define MCF_GPIO_PTCPAR_DTIN1_DTOUT1 (0x8)
|
||||
#define MCF_GPIO_PTCPAR_DTIN1_PWM2 (0xC)
|
||||
#define MCF_GPIO_PTCPAR_PTCPAR2(x) (((x)&0x3)<<0x4)
|
||||
#define MCF_GPIO_PTCPAR_DTIN2_GPIO (0)
|
||||
#define MCF_GPIO_PTCPAR_DTIN2_DTIN2 (0x10)
|
||||
#define MCF_GPIO_PTCPAR_DTIN2_DTOUT2 (0x20)
|
||||
#define MCF_GPIO_PTCPAR_DTIN2_PWM4 (0x30)
|
||||
#define MCF_GPIO_PTCPAR_PTCPAR3(x) (((x)&0x3)<<0x6)
|
||||
#define MCF_GPIO_PTCPAR_DTIN3_GPIO (0)
|
||||
#define MCF_GPIO_PTCPAR_DTIN3_DTIN3 (0x40)
|
||||
#define MCF_GPIO_PTCPAR_DTIN3_DTOUT3 (0x80)
|
||||
#define MCF_GPIO_PTCPAR_DTIN3_PWM6 (0xC0)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PORTTD */
|
||||
#define MCF_GPIO_PORTTD_PORTTD0 (0x1)
|
||||
#define MCF_GPIO_PORTTD_PORTTD1 (0x2)
|
||||
#define MCF_GPIO_PORTTD_PORTTD2 (0x4)
|
||||
#define MCF_GPIO_PORTTD_PORTTD3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_DDRTD */
|
||||
#define MCF_GPIO_DDRTD_DDRTD0 (0x1)
|
||||
#define MCF_GPIO_DDRTD_DDRTD1 (0x2)
|
||||
#define MCF_GPIO_DDRTD_DDRTD2 (0x4)
|
||||
#define MCF_GPIO_DDRTD_DDRTD3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_SETTD */
|
||||
#define MCF_GPIO_SETTD_SETTD0 (0x1)
|
||||
#define MCF_GPIO_SETTD_SETTD1 (0x2)
|
||||
#define MCF_GPIO_SETTD_SETTD2 (0x4)
|
||||
#define MCF_GPIO_SETTD_SETTD3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_CLRTD */
|
||||
#define MCF_GPIO_CLRTD_CLRTD0 (0x1)
|
||||
#define MCF_GPIO_CLRTD_CLRTD1 (0x2)
|
||||
#define MCF_GPIO_CLRTD_CLRTD2 (0x4)
|
||||
#define MCF_GPIO_CLRTD_CLRTD3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PTDPAR */
|
||||
#define MCF_GPIO_PTDPAR_PTDPAR0 (0x1)
|
||||
#define MCF_GPIO_PTDPAR_PWM1_GPIO (0)
|
||||
#define MCF_GPIO_PTDPAR_PWM1_PWM1 (0x1)
|
||||
#define MCF_GPIO_PTDPAR_PTDPAR1 (0x2)
|
||||
#define MCF_GPIO_PTDPAR_PWM3_GPIO (0)
|
||||
#define MCF_GPIO_PTDPAR_PWM3_PWM3 (0x2)
|
||||
#define MCF_GPIO_PTDPAR_PTDPAR2 (0x4)
|
||||
#define MCF_GPIO_PTDPAR_PWM5_GPIO (0)
|
||||
#define MCF_GPIO_PTDPAR_PWM5_PWM5 (0x4)
|
||||
#define MCF_GPIO_PTDPAR_PTDPAR3 (0x8)
|
||||
#define MCF_GPIO_PTDPAR_PWM7_GPIO (0)
|
||||
#define MCF_GPIO_PTDPAR_PWM7_PWM7 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PORTUA */
|
||||
#define MCF_GPIO_PORTUA_PORTUA0 (0x1)
|
||||
#define MCF_GPIO_PORTUA_PORTUA1 (0x2)
|
||||
#define MCF_GPIO_PORTUA_PORTUA2 (0x4)
|
||||
#define MCF_GPIO_PORTUA_PORTUA3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_DDRUA */
|
||||
#define MCF_GPIO_DDRUA_DDRUA0 (0x1)
|
||||
#define MCF_GPIO_DDRUA_DDRUA1 (0x2)
|
||||
#define MCF_GPIO_DDRUA_DDRUA2 (0x4)
|
||||
#define MCF_GPIO_DDRUA_DDRUA3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_SETUA */
|
||||
#define MCF_GPIO_SETUA_SETUA0 (0x1)
|
||||
#define MCF_GPIO_SETUA_SETUA1 (0x2)
|
||||
#define MCF_GPIO_SETUA_SETUA2 (0x4)
|
||||
#define MCF_GPIO_SETUA_SETUA3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_CLRUA */
|
||||
#define MCF_GPIO_CLRUA_CLRUA0 (0x1)
|
||||
#define MCF_GPIO_CLRUA_CLRUA1 (0x2)
|
||||
#define MCF_GPIO_CLRUA_CLRUA2 (0x4)
|
||||
#define MCF_GPIO_CLRUA_CLRUA3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PUAPAR */
|
||||
#define MCF_GPIO_PUAPAR_PUAPAR0(x) (((x)&0x3)<<0)
|
||||
#define MCF_GPIO_PUAPAR_UTXD0_GPIO (0)
|
||||
#define MCF_GPIO_PUAPAR_UTXD0_UTXD0 (0x1)
|
||||
#define MCF_GPIO_PUAPAR_UTXD0_FEC_CRS (0x3)
|
||||
#define MCF_GPIO_PUAPAR_PUAPAR1(x) (((x)&0x3)<<0x2)
|
||||
#define MCF_GPIO_PUAPAR_URXD0_GPIO (0)
|
||||
#define MCF_GPIO_PUAPAR_URXD0_URXD0 (0x4)
|
||||
#define MCF_GPIO_PUAPAR_URXD0_FEC_RXD0 (0xC)
|
||||
#define MCF_GPIO_PUAPAR_PUAPAR2(x) (((x)&0x3)<<0x4)
|
||||
#define MCF_GPIO_PUAPAR_URTS0_GPIO (0)
|
||||
#define MCF_GPIO_PUAPAR_URTS0_URTS0 (0x10)
|
||||
#define MCF_GPIO_PUAPAR_URTS0_CANTX (0x20)
|
||||
#define MCF_GPIO_PUAPAR_URTS0_FEC_RXDV (0x30)
|
||||
#define MCF_GPIO_PUAPAR_PUAPAR3(x) (((x)&0x3)<<0x6)
|
||||
#define MCF_GPIO_PUAPAR_UCTS0_GPIO (0)
|
||||
#define MCF_GPIO_PUAPAR_UCTS0_UCTS0 (0x40)
|
||||
#define MCF_GPIO_PUAPAR_UCTS0_CANRX (0x80)
|
||||
#define MCF_GPIO_PUAPAR_UCTS0_FEC_RXCLK (0xC0)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PORTUB */
|
||||
#define MCF_GPIO_PORTUB_PORTUB0 (0x1)
|
||||
#define MCF_GPIO_PORTUB_PORTUB1 (0x2)
|
||||
#define MCF_GPIO_PORTUB_PORTUB2 (0x4)
|
||||
#define MCF_GPIO_PORTUB_PORTUB3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_DDRUB */
|
||||
#define MCF_GPIO_DDRUB_DDRUB0 (0x1)
|
||||
#define MCF_GPIO_DDRUB_DDRUB1 (0x2)
|
||||
#define MCF_GPIO_DDRUB_DDRUB2 (0x4)
|
||||
#define MCF_GPIO_DDRUB_DDRUB3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_SETUB */
|
||||
#define MCF_GPIO_SETUB_SETUB0 (0x1)
|
||||
#define MCF_GPIO_SETUB_SETUB1 (0x2)
|
||||
#define MCF_GPIO_SETUB_SETUB2 (0x4)
|
||||
#define MCF_GPIO_SETUB_SETUB3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_CLRUB */
|
||||
#define MCF_GPIO_CLRUB_CLRUB0 (0x1)
|
||||
#define MCF_GPIO_CLRUB_CLRUB1 (0x2)
|
||||
#define MCF_GPIO_CLRUB_CLRUB2 (0x4)
|
||||
#define MCF_GPIO_CLRUB_CLRUB3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PUBPAR */
|
||||
#define MCF_GPIO_PUBPAR_PUBPAR0(x) (((x)&0x3)<<0)
|
||||
#define MCF_GPIO_PUBPAR_UTXD1_GPIO (0)
|
||||
#define MCF_GPIO_PUBPAR_UTXD1_UTXD1 (0x1)
|
||||
#define MCF_GPIO_PUBPAR_UTXD1_FEC_COL (0x3)
|
||||
#define MCF_GPIO_PUBPAR_PUBPAR1(x) (((x)&0x3)<<0x2)
|
||||
#define MCF_GPIO_PUBPAR_URXD1_GPIO (0)
|
||||
#define MCF_GPIO_PUBPAR_URXD1_URXD1 (0x4)
|
||||
#define MCF_GPIO_PUBPAR_URXD1_FEC_TXD0 (0xC)
|
||||
#define MCF_GPIO_PUBPAR_PUBPAR2(x) (((x)&0x3)<<0x4)
|
||||
#define MCF_GPIO_PUBPAR_URTS1_GPIO (0)
|
||||
#define MCF_GPIO_PUBPAR_URTS1_URTS1 (0x10)
|
||||
#define MCF_GPIO_PUBPAR_URTS1_SYNCB (0x20)
|
||||
#define MCF_GPIO_PUBPAR_URTS1_UTXD2 (0x30)
|
||||
#define MCF_GPIO_PUBPAR_PUBPAR3(x) (((x)&0x3)<<0x6)
|
||||
#define MCF_GPIO_PUBPAR_UCTS1_GPIO (0)
|
||||
#define MCF_GPIO_PUBPAR_UCTS1_UCTS1 (0x40)
|
||||
#define MCF_GPIO_PUBPAR_UCTS1_SYNCA (0x80)
|
||||
#define MCF_GPIO_PUBPAR_UCTS1_URXD2 (0xC0)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PORTUC */
|
||||
#define MCF_GPIO_PORTUC_PORTUC0 (0x1)
|
||||
#define MCF_GPIO_PORTUC_PORTUC1 (0x2)
|
||||
#define MCF_GPIO_PORTUC_PORTUC2 (0x4)
|
||||
#define MCF_GPIO_PORTUC_PORTUC3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_DDRUC */
|
||||
#define MCF_GPIO_DDRUC_DDRUC0 (0x1)
|
||||
#define MCF_GPIO_DDRUC_DDRUC1 (0x2)
|
||||
#define MCF_GPIO_DDRUC_DDRUC2 (0x4)
|
||||
#define MCF_GPIO_DDRUC_DDRUC3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_SETUC */
|
||||
#define MCF_GPIO_SETUC_SETUC0 (0x1)
|
||||
#define MCF_GPIO_SETUC_SETUC1 (0x2)
|
||||
#define MCF_GPIO_SETUC_SETUC2 (0x4)
|
||||
#define MCF_GPIO_SETUC_SETUC3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_CLRUC */
|
||||
#define MCF_GPIO_CLRUC_CLRUC0 (0x1)
|
||||
#define MCF_GPIO_CLRUC_CLRUC1 (0x2)
|
||||
#define MCF_GPIO_CLRUC_CLRUC2 (0x4)
|
||||
#define MCF_GPIO_CLRUC_CLRUC3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PUCPAR */
|
||||
#define MCF_GPIO_PUCPAR_PUCPAR0 (0x1)
|
||||
#define MCF_GPIO_PUCPAR_UTXD2_GPIO (0)
|
||||
#define MCF_GPIO_PUCPAR_UTXD2_UTXD2 (0x1)
|
||||
#define MCF_GPIO_PUCPAR_PUCPAR1 (0x2)
|
||||
#define MCF_GPIO_PUCPAR_URXD2_GPIO (0)
|
||||
#define MCF_GPIO_PUCPAR_URXD2_URXD2 (0x2)
|
||||
#define MCF_GPIO_PUCPAR_PUCPAR2 (0x4)
|
||||
#define MCF_GPIO_PUCPAR_URTS2_GPIO (0)
|
||||
#define MCF_GPIO_PUCPAR_URTS2_URTS2 (0x4)
|
||||
#define MCF_GPIO_PUCPAR_PUCPAR3 (0x8)
|
||||
#define MCF_GPIO_PUCPAR_UCTS2_GPIO (0)
|
||||
#define MCF_GPIO_PUCPAR_UCTS2_UCTS2 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PORTDD */
|
||||
#define MCF_GPIO_PORTDD_PORTDD0 (0x1)
|
||||
#define MCF_GPIO_PORTDD_PORTDD1 (0x2)
|
||||
#define MCF_GPIO_PORTDD_PORTDD2 (0x4)
|
||||
#define MCF_GPIO_PORTDD_PORTDD3 (0x8)
|
||||
#define MCF_GPIO_PORTDD_PORTDD4 (0x10)
|
||||
#define MCF_GPIO_PORTDD_PORTDD5 (0x20)
|
||||
#define MCF_GPIO_PORTDD_PORTDD6 (0x40)
|
||||
#define MCF_GPIO_PORTDD_PORTDD7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_DDRDD */
|
||||
#define MCF_GPIO_DDRDD_DDRDD0 (0x1)
|
||||
#define MCF_GPIO_DDRDD_DDRDD1 (0x2)
|
||||
#define MCF_GPIO_DDRDD_DDRDD2 (0x4)
|
||||
#define MCF_GPIO_DDRDD_DDRDD3 (0x8)
|
||||
#define MCF_GPIO_DDRDD_DDRDD4 (0x10)
|
||||
#define MCF_GPIO_DDRDD_DDRDD5 (0x20)
|
||||
#define MCF_GPIO_DDRDD_DDRDD6 (0x40)
|
||||
#define MCF_GPIO_DDRDD_DDRDD7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_SETDD */
|
||||
#define MCF_GPIO_SETDD_SETDD0 (0x1)
|
||||
#define MCF_GPIO_SETDD_SETDD1 (0x2)
|
||||
#define MCF_GPIO_SETDD_SETDD2 (0x4)
|
||||
#define MCF_GPIO_SETDD_SETDD3 (0x8)
|
||||
#define MCF_GPIO_SETDD_SETDD4 (0x10)
|
||||
#define MCF_GPIO_SETDD_SETDD5 (0x20)
|
||||
#define MCF_GPIO_SETDD_SETDD6 (0x40)
|
||||
#define MCF_GPIO_SETDD_SETDD7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_CLRDD */
|
||||
#define MCF_GPIO_CLRDD_CLRDD0 (0x1)
|
||||
#define MCF_GPIO_CLRDD_CLRDD1 (0x2)
|
||||
#define MCF_GPIO_CLRDD_CLRDD2 (0x4)
|
||||
#define MCF_GPIO_CLRDD_CLRDD3 (0x8)
|
||||
#define MCF_GPIO_CLRDD_CLRDD4 (0x10)
|
||||
#define MCF_GPIO_CLRDD_CLRDD5 (0x20)
|
||||
#define MCF_GPIO_CLRDD_CLRDD6 (0x40)
|
||||
#define MCF_GPIO_CLRDD_CLRDD7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PDDPAR */
|
||||
#define MCF_GPIO_PDDPAR_PDDPAR0 (0x1)
|
||||
#define MCF_GPIO_PDDPAR_PDD0_GPIO (0)
|
||||
#define MCF_GPIO_PDDPAR_PDD0_PST0 (0x1)
|
||||
#define MCF_GPIO_PDDPAR_PDDPAR1 (0x2)
|
||||
#define MCF_GPIO_PDDPAR_PDD1_GPIO (0)
|
||||
#define MCF_GPIO_PDDPAR_PDD1_PST1 (0x2)
|
||||
#define MCF_GPIO_PDDPAR_PDDPAR2 (0x4)
|
||||
#define MCF_GPIO_PDDPAR_PDD2_GPIO (0)
|
||||
#define MCF_GPIO_PDDPAR_PDD2_PST2 (0x4)
|
||||
#define MCF_GPIO_PDDPAR_PDDPAR3 (0x8)
|
||||
#define MCF_GPIO_PDDPAR_PDD3_GPIO (0)
|
||||
#define MCF_GPIO_PDDPAR_PDD3_PST3 (0x8)
|
||||
#define MCF_GPIO_PDDPAR_PDDPAR4 (0x10)
|
||||
#define MCF_GPIO_PDDPAR_PDD4_GPIO (0)
|
||||
#define MCF_GPIO_PDDPAR_PDD4_DDATA0 (0x10)
|
||||
#define MCF_GPIO_PDDPAR_PDDPAR5 (0x20)
|
||||
#define MCF_GPIO_PDDPAR_PDD5_GPIO (0)
|
||||
#define MCF_GPIO_PDDPAR_PDD5_DDATA1 (0x20)
|
||||
#define MCF_GPIO_PDDPAR_PDDPAR6 (0x40)
|
||||
#define MCF_GPIO_PDDPAR_PDD6_GPIO (0)
|
||||
#define MCF_GPIO_PDDPAR_PDD6_DDATA2 (0x40)
|
||||
#define MCF_GPIO_PDDPAR_PDDPAR7 (0x80)
|
||||
#define MCF_GPIO_PDDPAR_PDD7_GPIO (0)
|
||||
#define MCF_GPIO_PDDPAR_PDD7_DDATA3 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PORTLD */
|
||||
#define MCF_GPIO_PORTLD_PORTLD0 (0x1)
|
||||
#define MCF_GPIO_PORTLD_PORTLD1 (0x2)
|
||||
#define MCF_GPIO_PORTLD_PORTLD2 (0x4)
|
||||
#define MCF_GPIO_PORTLD_PORTLD3 (0x8)
|
||||
#define MCF_GPIO_PORTLD_PORTLD4 (0x10)
|
||||
#define MCF_GPIO_PORTLD_PORTLD5 (0x20)
|
||||
#define MCF_GPIO_PORTLD_PORTLD6 (0x40)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_DDRLD */
|
||||
#define MCF_GPIO_DDRLD_DDRLD0 (0x1)
|
||||
#define MCF_GPIO_DDRLD_DDRLD1 (0x2)
|
||||
#define MCF_GPIO_DDRLD_DDRLD2 (0x4)
|
||||
#define MCF_GPIO_DDRLD_DDRLD3 (0x8)
|
||||
#define MCF_GPIO_DDRLD_DDRLD4 (0x10)
|
||||
#define MCF_GPIO_DDRLD_DDRLD5 (0x20)
|
||||
#define MCF_GPIO_DDRLD_DDRLD6 (0x40)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_SETLD */
|
||||
#define MCF_GPIO_SETLD_SETLD0 (0x1)
|
||||
#define MCF_GPIO_SETLD_SETLD1 (0x2)
|
||||
#define MCF_GPIO_SETLD_SETLD2 (0x4)
|
||||
#define MCF_GPIO_SETLD_SETLD3 (0x8)
|
||||
#define MCF_GPIO_SETLD_SETLD4 (0x10)
|
||||
#define MCF_GPIO_SETLD_SETLD5 (0x20)
|
||||
#define MCF_GPIO_SETLD_SETLD6 (0x40)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_CLRLD */
|
||||
#define MCF_GPIO_CLRLD_CLRLD0 (0x1)
|
||||
#define MCF_GPIO_CLRLD_CLRLD1 (0x2)
|
||||
#define MCF_GPIO_CLRLD_CLRLD2 (0x4)
|
||||
#define MCF_GPIO_CLRLD_CLRLD3 (0x8)
|
||||
#define MCF_GPIO_CLRLD_CLRLD4 (0x10)
|
||||
#define MCF_GPIO_CLRLD_CLRLD5 (0x20)
|
||||
#define MCF_GPIO_CLRLD_CLRLD6 (0x40)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PLDPAR */
|
||||
#define MCF_GPIO_PLDPAR_PLDPAR0 (0x1)
|
||||
#define MCF_GPIO_PLDPAR_ACTLED_GPIO (0)
|
||||
#define MCF_GPIO_PLDPAR_ACTLED_ACTLED (0x1)
|
||||
#define MCF_GPIO_PLDPAR_PLDPAR1 (0x2)
|
||||
#define MCF_GPIO_PLDPAR_LINKLED_GPIO (0)
|
||||
#define MCF_GPIO_PLDPAR_LINKLED_LINKLED (0x2)
|
||||
#define MCF_GPIO_PLDPAR_PLDPAR2 (0x4)
|
||||
#define MCF_GPIO_PLDPAR_SPDLED_GPIO (0)
|
||||
#define MCF_GPIO_PLDPAR_SPDLED_SPDLED (0x4)
|
||||
#define MCF_GPIO_PLDPAR_PLDPAR3 (0x8)
|
||||
#define MCF_GPIO_PLDPAR_DUPLED_GPIO (0)
|
||||
#define MCF_GPIO_PLDPAR_DUPLED_DUPLED (0x8)
|
||||
#define MCF_GPIO_PLDPAR_PLDPAR4 (0x10)
|
||||
#define MCF_GPIO_PLDPAR_COLLED_GPIO (0)
|
||||
#define MCF_GPIO_PLDPAR_COLLED_COLLED (0x10)
|
||||
#define MCF_GPIO_PLDPAR_PLDPAR5 (0x20)
|
||||
#define MCF_GPIO_PLDPAR_RXLED_GPIO (0)
|
||||
#define MCF_GPIO_PLDPAR_RXLED_RXLED (0x20)
|
||||
#define MCF_GPIO_PLDPAR_PLDPAR6 (0x40)
|
||||
#define MCF_GPIO_PLDPAR_TXLED_GPIO (0)
|
||||
#define MCF_GPIO_PLDPAR_TXLED_TXLED (0x40)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PORTGP */
|
||||
#define MCF_GPIO_PORTGP_PORTGP0 (0x1)
|
||||
#define MCF_GPIO_PORTGP_PORTGP1 (0x2)
|
||||
#define MCF_GPIO_PORTGP_PORTGP2 (0x4)
|
||||
#define MCF_GPIO_PORTGP_PORTGP3 (0x8)
|
||||
#define MCF_GPIO_PORTGP_PORTGP4 (0x10)
|
||||
#define MCF_GPIO_PORTGP_PORTGP5 (0x20)
|
||||
#define MCF_GPIO_PORTGP_PORTGP6 (0x40)
|
||||
#define MCF_GPIO_PORTGP_PORTGP7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_DDRGP */
|
||||
#define MCF_GPIO_DDRGP_DDRGP0 (0x1)
|
||||
#define MCF_GPIO_DDRGP_DDRGP1 (0x2)
|
||||
#define MCF_GPIO_DDRGP_DDRGP2 (0x4)
|
||||
#define MCF_GPIO_DDRGP_DDRGP3 (0x8)
|
||||
#define MCF_GPIO_DDRGP_DDRGP4 (0x10)
|
||||
#define MCF_GPIO_DDRGP_DDRGP5 (0x20)
|
||||
#define MCF_GPIO_DDRGP_DDRGP6 (0x40)
|
||||
#define MCF_GPIO_DDRGP_DDRGP7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_SETGP */
|
||||
#define MCF_GPIO_SETGP_SETGP0 (0x1)
|
||||
#define MCF_GPIO_SETGP_SETGP1 (0x2)
|
||||
#define MCF_GPIO_SETGP_SETGP2 (0x4)
|
||||
#define MCF_GPIO_SETGP_SETGP3 (0x8)
|
||||
#define MCF_GPIO_SETGP_SETGP4 (0x10)
|
||||
#define MCF_GPIO_SETGP_SETGP5 (0x20)
|
||||
#define MCF_GPIO_SETGP_SETGP6 (0x40)
|
||||
#define MCF_GPIO_SETGP_SETGP7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_CLRGP */
|
||||
#define MCF_GPIO_CLRGP_CLRGP0 (0x1)
|
||||
#define MCF_GPIO_CLRGP_CLRGP1 (0x2)
|
||||
#define MCF_GPIO_CLRGP_CLRGP2 (0x4)
|
||||
#define MCF_GPIO_CLRGP_CLRGP3 (0x8)
|
||||
#define MCF_GPIO_CLRGP_CLRGP4 (0x10)
|
||||
#define MCF_GPIO_CLRGP_CLRGP5 (0x20)
|
||||
#define MCF_GPIO_CLRGP_CLRGP6 (0x40)
|
||||
#define MCF_GPIO_CLRGP_CLRGP7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PGPPAR */
|
||||
#define MCF_GPIO_PGPPAR_PGPPAR0 (0x1)
|
||||
#define MCF_GPIO_PGPPAR_IRQ8_GPIO (0)
|
||||
#define MCF_GPIO_PGPPAR_IRQ8_IRQ8 (0x1)
|
||||
#define MCF_GPIO_PGPPAR_PGPPAR1 (0x2)
|
||||
#define MCF_GPIO_PGPPAR_IRQ9_GPIO (0)
|
||||
#define MCF_GPIO_PGPPAR_IRQ9_IRQ9 (0x2)
|
||||
#define MCF_GPIO_PGPPAR_PGPPAR2 (0x4)
|
||||
#define MCF_GPIO_PGPPAR_IRQ10_GPIO (0)
|
||||
#define MCF_GPIO_PGPPAR_IRQ10_IRQ10 (0x4)
|
||||
#define MCF_GPIO_PGPPAR_PGPPAR3 (0x8)
|
||||
#define MCF_GPIO_PGPPAR_IRQ11_GPIO (0)
|
||||
#define MCF_GPIO_PGPPAR_IRQ11_IRQ11 (0x8)
|
||||
#define MCF_GPIO_PGPPAR_PGPPAR4 (0x10)
|
||||
#define MCF_GPIO_PGPPAR_IRQ12_GPIO (0)
|
||||
#define MCF_GPIO_PGPPAR_IRQ12_IRQ12 (0x10)
|
||||
#define MCF_GPIO_PGPPAR_PGPPAR5 (0x20)
|
||||
#define MCF_GPIO_PGPPAR_IRQ13_GPIO (0)
|
||||
#define MCF_GPIO_PGPPAR_IRQ13_IRQ13 (0x20)
|
||||
#define MCF_GPIO_PGPPAR_PGPPAR6 (0x40)
|
||||
#define MCF_GPIO_PGPPAR_IRQ14_GPIO (0)
|
||||
#define MCF_GPIO_PGPPAR_IRQ14_IRQ14 (0x40)
|
||||
#define MCF_GPIO_PGPPAR_PGPPAR7 (0x80)
|
||||
#define MCF_GPIO_PGPPAR_IRQ15_GPIO (0)
|
||||
#define MCF_GPIO_PGPPAR_IRQ15_IRQ15 (0x80)
|
||||
|
||||
|
||||
#endif /* __MCF52235_GPIO_H__ */
|
||||
198
Demo/ColdFire_MCF52233_Eclipse/RTOSDemo/MCF5223x/MCF52235_GPTA.h
Normal file
198
Demo/ColdFire_MCF52233_Eclipse/RTOSDemo/MCF5223x/MCF52235_GPTA.h
Normal file
|
|
@ -0,0 +1,198 @@
|
|||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2007/03/19 Revision: 0.91
|
||||
*/
|
||||
|
||||
#ifndef __MCF52235_GPTA_H__
|
||||
#define __MCF52235_GPTA_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* General Purpose Timer Module (GPT)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_GPTA_GPTIOS (*(vuint8 *)(&__IPSBAR[0x1A0000]))
|
||||
#define MCF_GPTA_GPTCFORC (*(vuint8 *)(&__IPSBAR[0x1A0001]))
|
||||
#define MCF_GPTA_GPTOC3M (*(vuint8 *)(&__IPSBAR[0x1A0002]))
|
||||
#define MCF_GPTA_GPTOC3D (*(vuint8 *)(&__IPSBAR[0x1A0003]))
|
||||
#define MCF_GPTA_GPTCNT (*(vuint16*)(&__IPSBAR[0x1A0004]))
|
||||
#define MCF_GPTA_GPTSCR1 (*(vuint8 *)(&__IPSBAR[0x1A0006]))
|
||||
#define MCF_GPTA_GPTTOV (*(vuint8 *)(&__IPSBAR[0x1A0008]))
|
||||
#define MCF_GPTA_GPTCTL1 (*(vuint8 *)(&__IPSBAR[0x1A0009]))
|
||||
#define MCF_GPTA_GPTCTL2 (*(vuint8 *)(&__IPSBAR[0x1A000B]))
|
||||
#define MCF_GPTA_GPTIE (*(vuint8 *)(&__IPSBAR[0x1A000C]))
|
||||
#define MCF_GPTA_GPTSCR2 (*(vuint8 *)(&__IPSBAR[0x1A000D]))
|
||||
#define MCF_GPTA_GPTFLG1 (*(vuint8 *)(&__IPSBAR[0x1A000E]))
|
||||
#define MCF_GPTA_GPTFLG2 (*(vuint8 *)(&__IPSBAR[0x1A000F]))
|
||||
#define MCF_GPTA_GPTC0 (*(vuint16*)(&__IPSBAR[0x1A0010]))
|
||||
#define MCF_GPTA_GPTC1 (*(vuint16*)(&__IPSBAR[0x1A0012]))
|
||||
#define MCF_GPTA_GPTC2 (*(vuint16*)(&__IPSBAR[0x1A0014]))
|
||||
#define MCF_GPTA_GPTC3 (*(vuint16*)(&__IPSBAR[0x1A0016]))
|
||||
#define MCF_GPTA_GPTPACTL (*(vuint8 *)(&__IPSBAR[0x1A0018]))
|
||||
#define MCF_GPTA_GPTPAFLG (*(vuint8 *)(&__IPSBAR[0x1A0019]))
|
||||
#define MCF_GPTA_GPTPACNT (*(vuint16*)(&__IPSBAR[0x1A001A]))
|
||||
#define MCF_GPTA_GPTPORT (*(vuint8 *)(&__IPSBAR[0x1A001D]))
|
||||
#define MCF_GPTA_GPTDDR (*(vuint8 *)(&__IPSBAR[0x1A001E]))
|
||||
#define MCF_GPTA_GPTC(x) (*(vuint16*)(&__IPSBAR[0x1A0010 + ((x)*0x2)]))
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_GPTA_GPTIOS */
|
||||
#define MCF_GPTA_GPTIOS_IOS0 (0x1)
|
||||
#define MCF_GPTA_GPTIOS_IOS1 (0x2)
|
||||
#define MCF_GPTA_GPTIOS_IOS2 (0x4)
|
||||
#define MCF_GPTA_GPTIOS_IOS3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPTA_GPTCFORC */
|
||||
#define MCF_GPTA_GPTCFORC_FOC0 (0x1)
|
||||
#define MCF_GPTA_GPTCFORC_FOC1 (0x2)
|
||||
#define MCF_GPTA_GPTCFORC_FOC2 (0x4)
|
||||
#define MCF_GPTA_GPTCFORC_FOC3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPTA_GPTOC3M */
|
||||
#define MCF_GPTA_GPTOC3M_OC3M0 (0x1)
|
||||
#define MCF_GPTA_GPTOC3M_OC3M1 (0x2)
|
||||
#define MCF_GPTA_GPTOC3M_OC3M2 (0x4)
|
||||
#define MCF_GPTA_GPTOC3M_OC3M3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPTA_GPTOC3D */
|
||||
#define MCF_GPTA_GPTOC3D_OC3D0 (0x1)
|
||||
#define MCF_GPTA_GPTOC3D_OC3D1 (0x2)
|
||||
#define MCF_GPTA_GPTOC3D_OC3D2 (0x4)
|
||||
#define MCF_GPTA_GPTOC3D_OC3D3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPTA_GPTCNT */
|
||||
#define MCF_GPTA_GPTCNT_CNTR(x) (((x)&0xFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPTA_GPTSCR1 */
|
||||
#define MCF_GPTA_GPTSCR1_TFFCA (0x10)
|
||||
#define MCF_GPTA_GPTSCR1_GPTEN (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPTA_GPTTOV */
|
||||
#define MCF_GPTA_GPTTOV_TOV0 (0x1)
|
||||
#define MCF_GPTA_GPTTOV_TOV1 (0x2)
|
||||
#define MCF_GPTA_GPTTOV_TOV2 (0x4)
|
||||
#define MCF_GPTA_GPTTOV_TOV3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPTA_GPTCTL1 */
|
||||
#define MCF_GPTA_GPTCTL1_OL0 (0x1)
|
||||
#define MCF_GPTA_GPTCTL1_OM0 (0x2)
|
||||
#define MCF_GPTA_GPTCTL1_OL1 (0x4)
|
||||
#define MCF_GPTA_GPTCTL1_OM1 (0x8)
|
||||
#define MCF_GPTA_GPTCTL1_OL2 (0x10)
|
||||
#define MCF_GPTA_GPTCTL1_OM2 (0x20)
|
||||
#define MCF_GPTA_GPTCTL1_OL3 (0x40)
|
||||
#define MCF_GPTA_GPTCTL1_OM3 (0x80)
|
||||
#define MCF_GPTA_GPTCTL1_OUTPUT0_NOTHING (0)
|
||||
#define MCF_GPTA_GPTCTL1_OUTPUT0_TOGGLE (0x1)
|
||||
#define MCF_GPTA_GPTCTL1_OUTPUT0_CLEAR (0x2)
|
||||
#define MCF_GPTA_GPTCTL1_OUTPUT0_SET (0x3)
|
||||
#define MCF_GPTA_GPTCTL1_OUTPUT1_NOTHING (0)
|
||||
#define MCF_GPTA_GPTCTL1_OUTPUT1_TOGGLE (0x4)
|
||||
#define MCF_GPTA_GPTCTL1_OUTPUT1_CLEAR (0x8)
|
||||
#define MCF_GPTA_GPTCTL1_OUTPUT1_SET (0xC)
|
||||
#define MCF_GPTA_GPTCTL1_OUTPUT2_NOTHING (0)
|
||||
#define MCF_GPTA_GPTCTL1_OUTPUT2_TOGGLE (0x10)
|
||||
#define MCF_GPTA_GPTCTL1_OUTPUT2_CLEAR (0x20)
|
||||
#define MCF_GPTA_GPTCTL1_OUTPUT2_SET (0x30)
|
||||
#define MCF_GPTA_GPTCTL1_OUTPUT3_NOTHING (0)
|
||||
#define MCF_GPTA_GPTCTL1_OUTPUT3_TOGGLE (0x40)
|
||||
#define MCF_GPTA_GPTCTL1_OUTPUT3_CLEAR (0x80)
|
||||
#define MCF_GPTA_GPTCTL1_OUTPUT3_SET (0xC0)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPTA_GPTCTL2 */
|
||||
#define MCF_GPTA_GPTCTL2_EDG0A (0x1)
|
||||
#define MCF_GPTA_GPTCTL2_EDG0B (0x2)
|
||||
#define MCF_GPTA_GPTCTL2_EDG1A (0x4)
|
||||
#define MCF_GPTA_GPTCTL2_EDG1B (0x8)
|
||||
#define MCF_GPTA_GPTCTL2_EDG2A (0x10)
|
||||
#define MCF_GPTA_GPTCTL2_EDG2B (0x20)
|
||||
#define MCF_GPTA_GPTCTL2_EDG3A (0x40)
|
||||
#define MCF_GPTA_GPTCTL2_EDG3B (0x80)
|
||||
#define MCF_GPTA_GPTCTL2_INPUT0_DISABLED (0)
|
||||
#define MCF_GPTA_GPTCTL2_INPUT0_RISING (0x1)
|
||||
#define MCF_GPTA_GPTCTL2_INPUT0_FALLING (0x2)
|
||||
#define MCF_GPTA_GPTCTL2_INPUT0_ANY (0x3)
|
||||
#define MCF_GPTA_GPTCTL2_INPUT1_DISABLED (0)
|
||||
#define MCF_GPTA_GPTCTL2_INPUT1_RISING (0x4)
|
||||
#define MCF_GPTA_GPTCTL2_INPUT1_FALLING (0x8)
|
||||
#define MCF_GPTA_GPTCTL2_INPUT1_ANY (0xC)
|
||||
#define MCF_GPTA_GPTCTL2_INPUT2_DISABLED (0)
|
||||
#define MCF_GPTA_GPTCTL2_INPUT2_RISING (0x10)
|
||||
#define MCF_GPTA_GPTCTL2_INPUT2_FALLING (0x20)
|
||||
#define MCF_GPTA_GPTCTL2_INPUT2_ANY (0x30)
|
||||
#define MCF_GPTA_GPTCTL2_INPUT3_DISABLED (0)
|
||||
#define MCF_GPTA_GPTCTL2_INPUT3_RISING (0x40)
|
||||
#define MCF_GPTA_GPTCTL2_INPUT3_FALLING (0x80)
|
||||
#define MCF_GPTA_GPTCTL2_INPUT3_ANY (0xC0)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPTA_GPTIE */
|
||||
#define MCF_GPTA_GPTIE_CI0 (0x1)
|
||||
#define MCF_GPTA_GPTIE_CI1 (0x2)
|
||||
#define MCF_GPTA_GPTIE_CI2 (0x4)
|
||||
#define MCF_GPTA_GPTIE_CI3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPTA_GPTSCR2 */
|
||||
#define MCF_GPTA_GPTSCR2_PR(x) (((x)&0x7)<<0)
|
||||
#define MCF_GPTA_GPTSCR2_PR_1 (0)
|
||||
#define MCF_GPTA_GPTSCR2_PR_2 (0x1)
|
||||
#define MCF_GPTA_GPTSCR2_PR_4 (0x2)
|
||||
#define MCF_GPTA_GPTSCR2_PR_8 (0x3)
|
||||
#define MCF_GPTA_GPTSCR2_PR_16 (0x4)
|
||||
#define MCF_GPTA_GPTSCR2_PR_32 (0x5)
|
||||
#define MCF_GPTA_GPTSCR2_PR_64 (0x6)
|
||||
#define MCF_GPTA_GPTSCR2_PR_128 (0x7)
|
||||
#define MCF_GPTA_GPTSCR2_TCRE (0x8)
|
||||
#define MCF_GPTA_GPTSCR2_RDPT (0x10)
|
||||
#define MCF_GPTA_GPTSCR2_PUPT (0x20)
|
||||
#define MCF_GPTA_GPTSCR2_TOI (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPTA_GPTFLG1 */
|
||||
#define MCF_GPTA_GPTFLG1_CF0 (0x1)
|
||||
#define MCF_GPTA_GPTFLG1_CF1 (0x2)
|
||||
#define MCF_GPTA_GPTFLG1_CF2 (0x4)
|
||||
#define MCF_GPTA_GPTFLG1_CF3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPTA_GPTFLG2 */
|
||||
#define MCF_GPTA_GPTFLG2_TOF (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPTA_GPTC */
|
||||
#define MCF_GPTA_GPTC_CCNT(x) (((x)&0xFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPTA_GPTPACTL */
|
||||
#define MCF_GPTA_GPTPACTL_PAI (0x1)
|
||||
#define MCF_GPTA_GPTPACTL_PAOVI (0x2)
|
||||
#define MCF_GPTA_GPTPACTL_CLK(x) (((x)&0x3)<<0x2)
|
||||
#define MCF_GPTA_GPTPACTL_CLK_GPTPR (0)
|
||||
#define MCF_GPTA_GPTPACTL_CLK_PACLK (0x1)
|
||||
#define MCF_GPTA_GPTPACTL_CLK_PACLK_256 (0x2)
|
||||
#define MCF_GPTA_GPTPACTL_CLK_PACLK_65536 (0x3)
|
||||
#define MCF_GPTA_GPTPACTL_PEDGE (0x10)
|
||||
#define MCF_GPTA_GPTPACTL_PAMOD (0x20)
|
||||
#define MCF_GPTA_GPTPACTL_PAE (0x40)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPTA_GPTPAFLG */
|
||||
#define MCF_GPTA_GPTPAFLG_PAIF (0x1)
|
||||
#define MCF_GPTA_GPTPAFLG_PAOVF (0x2)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPTA_GPTPACNT */
|
||||
#define MCF_GPTA_GPTPACNT_PACNT(x) (((x)&0xFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPTA_GPTPORT */
|
||||
#define MCF_GPTA_GPTPORT_PORTT0 (0x1)
|
||||
#define MCF_GPTA_GPTPORT_PORTT1 (0x2)
|
||||
#define MCF_GPTA_GPTPORT_PORTT2 (0x4)
|
||||
#define MCF_GPTA_GPTPORT_PORTT3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPTA_GPTDDR */
|
||||
#define MCF_GPTA_GPTDDR_DDRT0 (0x1)
|
||||
#define MCF_GPTA_GPTDDR_DDRT1 (0x2)
|
||||
#define MCF_GPTA_GPTDDR_DDRT2 (0x4)
|
||||
#define MCF_GPTA_GPTDDR_DDRT3 (0x8)
|
||||
|
||||
|
||||
#endif /* __MCF52235_GPTA_H__ */
|
||||
|
|
@ -0,0 +1,54 @@
|
|||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2007/03/19 Revision: 0.91
|
||||
*/
|
||||
|
||||
#ifndef __MCF52235_I2C_H__
|
||||
#define __MCF52235_I2C_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* I2C Module (I2C)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_I2C_I2ADR (*(vuint8 *)(&__IPSBAR[0x300]))
|
||||
#define MCF_I2C_I2FDR (*(vuint8 *)(&__IPSBAR[0x304]))
|
||||
#define MCF_I2C_I2CR (*(vuint8 *)(&__IPSBAR[0x308]))
|
||||
#define MCF_I2C_I2SR (*(vuint8 *)(&__IPSBAR[0x30C]))
|
||||
#define MCF_I2C_I2DR (*(vuint8 *)(&__IPSBAR[0x310]))
|
||||
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_I2C_I2ADR */
|
||||
#define MCF_I2C_I2ADR_ADR(x) (((x)&0x7F)<<0x1)
|
||||
|
||||
/* Bit definitions and macros for MCF_I2C_I2FDR */
|
||||
#define MCF_I2C_I2FDR_IC(x) (((x)&0x3F)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_I2C_I2CR */
|
||||
#define MCF_I2C_I2CR_RSTA (0x4)
|
||||
#define MCF_I2C_I2CR_TXAK (0x8)
|
||||
#define MCF_I2C_I2CR_MTX (0x10)
|
||||
#define MCF_I2C_I2CR_MSTA (0x20)
|
||||
#define MCF_I2C_I2CR_IIEN (0x40)
|
||||
#define MCF_I2C_I2CR_IEN (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_I2C_I2SR */
|
||||
#define MCF_I2C_I2SR_RXAK (0x1)
|
||||
#define MCF_I2C_I2SR_IIF (0x2)
|
||||
#define MCF_I2C_I2SR_SRW (0x4)
|
||||
#define MCF_I2C_I2SR_IAL (0x10)
|
||||
#define MCF_I2C_I2SR_IBB (0x20)
|
||||
#define MCF_I2C_I2SR_IAAS (0x40)
|
||||
#define MCF_I2C_I2SR_ICF (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_I2C_I2DR */
|
||||
#define MCF_I2C_I2DR_DATA(x) (((x)&0xFF)<<0)
|
||||
|
||||
|
||||
#endif /* __MCF52235_I2C_H__ */
|
||||
484
Demo/ColdFire_MCF52233_Eclipse/RTOSDemo/MCF5223x/MCF52235_INTC.h
Normal file
484
Demo/ColdFire_MCF52233_Eclipse/RTOSDemo/MCF5223x/MCF52235_INTC.h
Normal file
|
|
@ -0,0 +1,484 @@
|
|||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2007/03/19 Revision: 0.91
|
||||
*/
|
||||
|
||||
#ifndef __MCF52235_INTC_H__
|
||||
#define __MCF52235_INTC_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Interrupt Controller (INTC)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_INTC0_IPRH (*(vuint32*)(&__IPSBAR[0xC00]))
|
||||
#define MCF_INTC0_IPRL (*(vuint32*)(&__IPSBAR[0xC04]))
|
||||
#define MCF_INTC0_IMRH (*(vuint32*)(&__IPSBAR[0xC08]))
|
||||
#define MCF_INTC0_IMRL (*(vuint32*)(&__IPSBAR[0xC0C]))
|
||||
#define MCF_INTC0_INTFRCH (*(vuint32*)(&__IPSBAR[0xC10]))
|
||||
#define MCF_INTC0_INTFRCL (*(vuint32*)(&__IPSBAR[0xC14]))
|
||||
#define MCF_INTC0_IRLR (*(vuint8 *)(&__IPSBAR[0xC18]))
|
||||
#define MCF_INTC0_IACKLPR (*(vuint8 *)(&__IPSBAR[0xC19]))
|
||||
#define MCF_INTC0_ICR01 (*(vuint8 *)(&__IPSBAR[0xC41]))
|
||||
#define MCF_INTC0_ICR02 (*(vuint8 *)(&__IPSBAR[0xC42]))
|
||||
#define MCF_INTC0_ICR03 (*(vuint8 *)(&__IPSBAR[0xC43]))
|
||||
#define MCF_INTC0_ICR04 (*(vuint8 *)(&__IPSBAR[0xC44]))
|
||||
#define MCF_INTC0_ICR05 (*(vuint8 *)(&__IPSBAR[0xC45]))
|
||||
#define MCF_INTC0_ICR06 (*(vuint8 *)(&__IPSBAR[0xC46]))
|
||||
#define MCF_INTC0_ICR07 (*(vuint8 *)(&__IPSBAR[0xC47]))
|
||||
#define MCF_INTC0_ICR08 (*(vuint8 *)(&__IPSBAR[0xC48]))
|
||||
#define MCF_INTC0_ICR09 (*(vuint8 *)(&__IPSBAR[0xC49]))
|
||||
#define MCF_INTC0_ICR10 (*(vuint8 *)(&__IPSBAR[0xC4A]))
|
||||
#define MCF_INTC0_ICR11 (*(vuint8 *)(&__IPSBAR[0xC4B]))
|
||||
#define MCF_INTC0_ICR12 (*(vuint8 *)(&__IPSBAR[0xC4C]))
|
||||
#define MCF_INTC0_ICR13 (*(vuint8 *)(&__IPSBAR[0xC4D]))
|
||||
#define MCF_INTC0_ICR14 (*(vuint8 *)(&__IPSBAR[0xC4E]))
|
||||
#define MCF_INTC0_ICR15 (*(vuint8 *)(&__IPSBAR[0xC4F]))
|
||||
#define MCF_INTC0_ICR16 (*(vuint8 *)(&__IPSBAR[0xC50]))
|
||||
#define MCF_INTC0_ICR17 (*(vuint8 *)(&__IPSBAR[0xC51]))
|
||||
#define MCF_INTC0_ICR18 (*(vuint8 *)(&__IPSBAR[0xC52]))
|
||||
#define MCF_INTC0_ICR19 (*(vuint8 *)(&__IPSBAR[0xC53]))
|
||||
#define MCF_INTC0_ICR20 (*(vuint8 *)(&__IPSBAR[0xC54]))
|
||||
#define MCF_INTC0_ICR21 (*(vuint8 *)(&__IPSBAR[0xC55]))
|
||||
#define MCF_INTC0_ICR22 (*(vuint8 *)(&__IPSBAR[0xC56]))
|
||||
#define MCF_INTC0_ICR23 (*(vuint8 *)(&__IPSBAR[0xC57]))
|
||||
#define MCF_INTC0_ICR24 (*(vuint8 *)(&__IPSBAR[0xC58]))
|
||||
#define MCF_INTC0_ICR25 (*(vuint8 *)(&__IPSBAR[0xC59]))
|
||||
#define MCF_INTC0_ICR26 (*(vuint8 *)(&__IPSBAR[0xC5A]))
|
||||
#define MCF_INTC0_ICR27 (*(vuint8 *)(&__IPSBAR[0xC5B]))
|
||||
#define MCF_INTC0_ICR28 (*(vuint8 *)(&__IPSBAR[0xC5C]))
|
||||
#define MCF_INTC0_ICR29 (*(vuint8 *)(&__IPSBAR[0xC5D]))
|
||||
#define MCF_INTC0_ICR30 (*(vuint8 *)(&__IPSBAR[0xC5E]))
|
||||
#define MCF_INTC0_ICR31 (*(vuint8 *)(&__IPSBAR[0xC5F]))
|
||||
#define MCF_INTC0_ICR32 (*(vuint8 *)(&__IPSBAR[0xC60]))
|
||||
#define MCF_INTC0_ICR33 (*(vuint8 *)(&__IPSBAR[0xC61]))
|
||||
#define MCF_INTC0_ICR34 (*(vuint8 *)(&__IPSBAR[0xC62]))
|
||||
#define MCF_INTC0_ICR35 (*(vuint8 *)(&__IPSBAR[0xC63]))
|
||||
#define MCF_INTC0_ICR36 (*(vuint8 *)(&__IPSBAR[0xC64]))
|
||||
#define MCF_INTC0_ICR37 (*(vuint8 *)(&__IPSBAR[0xC65]))
|
||||
#define MCF_INTC0_ICR38 (*(vuint8 *)(&__IPSBAR[0xC66]))
|
||||
#define MCF_INTC0_ICR39 (*(vuint8 *)(&__IPSBAR[0xC67]))
|
||||
#define MCF_INTC0_ICR40 (*(vuint8 *)(&__IPSBAR[0xC68]))
|
||||
#define MCF_INTC0_ICR41 (*(vuint8 *)(&__IPSBAR[0xC69]))
|
||||
#define MCF_INTC0_ICR42 (*(vuint8 *)(&__IPSBAR[0xC6A]))
|
||||
#define MCF_INTC0_ICR43 (*(vuint8 *)(&__IPSBAR[0xC6B]))
|
||||
#define MCF_INTC0_ICR44 (*(vuint8 *)(&__IPSBAR[0xC6C]))
|
||||
#define MCF_INTC0_ICR45 (*(vuint8 *)(&__IPSBAR[0xC6D]))
|
||||
#define MCF_INTC0_ICR46 (*(vuint8 *)(&__IPSBAR[0xC6E]))
|
||||
#define MCF_INTC0_ICR47 (*(vuint8 *)(&__IPSBAR[0xC6F]))
|
||||
#define MCF_INTC0_ICR48 (*(vuint8 *)(&__IPSBAR[0xC70]))
|
||||
#define MCF_INTC0_ICR49 (*(vuint8 *)(&__IPSBAR[0xC71]))
|
||||
#define MCF_INTC0_ICR50 (*(vuint8 *)(&__IPSBAR[0xC72]))
|
||||
#define MCF_INTC0_ICR51 (*(vuint8 *)(&__IPSBAR[0xC73]))
|
||||
#define MCF_INTC0_ICR52 (*(vuint8 *)(&__IPSBAR[0xC74]))
|
||||
#define MCF_INTC0_ICR53 (*(vuint8 *)(&__IPSBAR[0xC75]))
|
||||
#define MCF_INTC0_ICR54 (*(vuint8 *)(&__IPSBAR[0xC76]))
|
||||
#define MCF_INTC0_ICR55 (*(vuint8 *)(&__IPSBAR[0xC77]))
|
||||
#define MCF_INTC0_ICR56 (*(vuint8 *)(&__IPSBAR[0xC78]))
|
||||
#define MCF_INTC0_ICR57 (*(vuint8 *)(&__IPSBAR[0xC79]))
|
||||
#define MCF_INTC0_ICR58 (*(vuint8 *)(&__IPSBAR[0xC7A]))
|
||||
#define MCF_INTC0_ICR59 (*(vuint8 *)(&__IPSBAR[0xC7B]))
|
||||
#define MCF_INTC0_ICR60 (*(vuint8 *)(&__IPSBAR[0xC7C]))
|
||||
#define MCF_INTC0_ICR61 (*(vuint8 *)(&__IPSBAR[0xC7D]))
|
||||
#define MCF_INTC0_ICR62 (*(vuint8 *)(&__IPSBAR[0xC7E]))
|
||||
#define MCF_INTC0_ICR63 (*(vuint8 *)(&__IPSBAR[0xC7F]))
|
||||
#define MCF_INTC0_SWIACK (*(vuint8 *)(&__IPSBAR[0xCE0]))
|
||||
#define MCF_INTC0_L1IACK (*(vuint8 *)(&__IPSBAR[0xCE4]))
|
||||
#define MCF_INTC0_L2IACK (*(vuint8 *)(&__IPSBAR[0xCE8]))
|
||||
#define MCF_INTC0_L3IACK (*(vuint8 *)(&__IPSBAR[0xCEC]))
|
||||
#define MCF_INTC0_L4IACK (*(vuint8 *)(&__IPSBAR[0xCF0]))
|
||||
#define MCF_INTC0_L5IACK (*(vuint8 *)(&__IPSBAR[0xCF4]))
|
||||
#define MCF_INTC0_L6IACK (*(vuint8 *)(&__IPSBAR[0xCF8]))
|
||||
#define MCF_INTC0_L7IACK (*(vuint8 *)(&__IPSBAR[0xCFC]))
|
||||
#define MCF_INTC0_ICR(x) (*(vuint8 *)(&__IPSBAR[0xC41 + ((x-1)*0x1)]))
|
||||
#define MCF_INTC0_LIACK(x) (*(vuint8 *)(&__IPSBAR[0xCE4 + ((x-1)*0x4)]))
|
||||
|
||||
#define MCF_INTC1_IPRH (*(vuint32*)(&__IPSBAR[0xD00]))
|
||||
#define MCF_INTC1_IPRL (*(vuint32*)(&__IPSBAR[0xD04]))
|
||||
#define MCF_INTC1_IMRH (*(vuint32*)(&__IPSBAR[0xD08]))
|
||||
#define MCF_INTC1_IMRL (*(vuint32*)(&__IPSBAR[0xD0C]))
|
||||
#define MCF_INTC1_INTFRCH (*(vuint32*)(&__IPSBAR[0xD10]))
|
||||
#define MCF_INTC1_INTFRCL (*(vuint32*)(&__IPSBAR[0xD14]))
|
||||
#define MCF_INTC1_IRLR (*(vuint8 *)(&__IPSBAR[0xD18]))
|
||||
#define MCF_INTC1_IACKLPR (*(vuint8 *)(&__IPSBAR[0xD19]))
|
||||
#define MCF_INTC1_ICR01 (*(vuint8 *)(&__IPSBAR[0xD41]))
|
||||
#define MCF_INTC1_ICR02 (*(vuint8 *)(&__IPSBAR[0xD42]))
|
||||
#define MCF_INTC1_ICR03 (*(vuint8 *)(&__IPSBAR[0xD43]))
|
||||
#define MCF_INTC1_ICR04 (*(vuint8 *)(&__IPSBAR[0xD44]))
|
||||
#define MCF_INTC1_ICR05 (*(vuint8 *)(&__IPSBAR[0xD45]))
|
||||
#define MCF_INTC1_ICR06 (*(vuint8 *)(&__IPSBAR[0xD46]))
|
||||
#define MCF_INTC1_ICR07 (*(vuint8 *)(&__IPSBAR[0xD47]))
|
||||
#define MCF_INTC1_ICR08 (*(vuint8 *)(&__IPSBAR[0xD48]))
|
||||
#define MCF_INTC1_ICR09 (*(vuint8 *)(&__IPSBAR[0xD49]))
|
||||
#define MCF_INTC1_ICR10 (*(vuint8 *)(&__IPSBAR[0xD4A]))
|
||||
#define MCF_INTC1_ICR11 (*(vuint8 *)(&__IPSBAR[0xD4B]))
|
||||
#define MCF_INTC1_ICR12 (*(vuint8 *)(&__IPSBAR[0xD4C]))
|
||||
#define MCF_INTC1_ICR13 (*(vuint8 *)(&__IPSBAR[0xD4D]))
|
||||
#define MCF_INTC1_ICR14 (*(vuint8 *)(&__IPSBAR[0xD4E]))
|
||||
#define MCF_INTC1_ICR15 (*(vuint8 *)(&__IPSBAR[0xD4F]))
|
||||
#define MCF_INTC1_ICR16 (*(vuint8 *)(&__IPSBAR[0xD50]))
|
||||
#define MCF_INTC1_ICR17 (*(vuint8 *)(&__IPSBAR[0xD51]))
|
||||
#define MCF_INTC1_ICR18 (*(vuint8 *)(&__IPSBAR[0xD52]))
|
||||
#define MCF_INTC1_ICR19 (*(vuint8 *)(&__IPSBAR[0xD53]))
|
||||
#define MCF_INTC1_ICR20 (*(vuint8 *)(&__IPSBAR[0xD54]))
|
||||
#define MCF_INTC1_ICR21 (*(vuint8 *)(&__IPSBAR[0xD55]))
|
||||
#define MCF_INTC1_ICR22 (*(vuint8 *)(&__IPSBAR[0xD56]))
|
||||
#define MCF_INTC1_ICR23 (*(vuint8 *)(&__IPSBAR[0xD57]))
|
||||
#define MCF_INTC1_ICR24 (*(vuint8 *)(&__IPSBAR[0xD58]))
|
||||
#define MCF_INTC1_ICR25 (*(vuint8 *)(&__IPSBAR[0xD59]))
|
||||
#define MCF_INTC1_ICR26 (*(vuint8 *)(&__IPSBAR[0xD5A]))
|
||||
#define MCF_INTC1_ICR27 (*(vuint8 *)(&__IPSBAR[0xD5B]))
|
||||
#define MCF_INTC1_ICR28 (*(vuint8 *)(&__IPSBAR[0xD5C]))
|
||||
#define MCF_INTC1_ICR29 (*(vuint8 *)(&__IPSBAR[0xD5D]))
|
||||
#define MCF_INTC1_ICR30 (*(vuint8 *)(&__IPSBAR[0xD5E]))
|
||||
#define MCF_INTC1_ICR31 (*(vuint8 *)(&__IPSBAR[0xD5F]))
|
||||
#define MCF_INTC1_ICR32 (*(vuint8 *)(&__IPSBAR[0xD60]))
|
||||
#define MCF_INTC1_ICR33 (*(vuint8 *)(&__IPSBAR[0xD61]))
|
||||
#define MCF_INTC1_ICR34 (*(vuint8 *)(&__IPSBAR[0xD62]))
|
||||
#define MCF_INTC1_ICR35 (*(vuint8 *)(&__IPSBAR[0xD63]))
|
||||
#define MCF_INTC1_ICR36 (*(vuint8 *)(&__IPSBAR[0xD64]))
|
||||
#define MCF_INTC1_ICR37 (*(vuint8 *)(&__IPSBAR[0xD65]))
|
||||
#define MCF_INTC1_ICR38 (*(vuint8 *)(&__IPSBAR[0xD66]))
|
||||
#define MCF_INTC1_ICR39 (*(vuint8 *)(&__IPSBAR[0xD67]))
|
||||
#define MCF_INTC1_ICR40 (*(vuint8 *)(&__IPSBAR[0xD68]))
|
||||
#define MCF_INTC1_ICR41 (*(vuint8 *)(&__IPSBAR[0xD69]))
|
||||
#define MCF_INTC1_ICR42 (*(vuint8 *)(&__IPSBAR[0xD6A]))
|
||||
#define MCF_INTC1_ICR43 (*(vuint8 *)(&__IPSBAR[0xD6B]))
|
||||
#define MCF_INTC1_ICR44 (*(vuint8 *)(&__IPSBAR[0xD6C]))
|
||||
#define MCF_INTC1_ICR45 (*(vuint8 *)(&__IPSBAR[0xD6D]))
|
||||
#define MCF_INTC1_ICR46 (*(vuint8 *)(&__IPSBAR[0xD6E]))
|
||||
#define MCF_INTC1_ICR47 (*(vuint8 *)(&__IPSBAR[0xD6F]))
|
||||
#define MCF_INTC1_ICR48 (*(vuint8 *)(&__IPSBAR[0xD70]))
|
||||
#define MCF_INTC1_ICR49 (*(vuint8 *)(&__IPSBAR[0xD71]))
|
||||
#define MCF_INTC1_ICR50 (*(vuint8 *)(&__IPSBAR[0xD72]))
|
||||
#define MCF_INTC1_ICR51 (*(vuint8 *)(&__IPSBAR[0xD73]))
|
||||
#define MCF_INTC1_ICR52 (*(vuint8 *)(&__IPSBAR[0xD74]))
|
||||
#define MCF_INTC1_ICR53 (*(vuint8 *)(&__IPSBAR[0xD75]))
|
||||
#define MCF_INTC1_ICR54 (*(vuint8 *)(&__IPSBAR[0xD76]))
|
||||
#define MCF_INTC1_ICR55 (*(vuint8 *)(&__IPSBAR[0xD77]))
|
||||
#define MCF_INTC1_ICR56 (*(vuint8 *)(&__IPSBAR[0xD78]))
|
||||
#define MCF_INTC1_ICR57 (*(vuint8 *)(&__IPSBAR[0xD79]))
|
||||
#define MCF_INTC1_ICR58 (*(vuint8 *)(&__IPSBAR[0xD7A]))
|
||||
#define MCF_INTC1_ICR59 (*(vuint8 *)(&__IPSBAR[0xD7B]))
|
||||
#define MCF_INTC1_ICR60 (*(vuint8 *)(&__IPSBAR[0xD7C]))
|
||||
#define MCF_INTC1_ICR61 (*(vuint8 *)(&__IPSBAR[0xD7D]))
|
||||
#define MCF_INTC1_ICR62 (*(vuint8 *)(&__IPSBAR[0xD7E]))
|
||||
#define MCF_INTC1_ICR63 (*(vuint8 *)(&__IPSBAR[0xD7F]))
|
||||
#define MCF_INTC1_SWIACK (*(vuint8 *)(&__IPSBAR[0xDE0]))
|
||||
#define MCF_INTC1_L1IACK (*(vuint8 *)(&__IPSBAR[0xDE4]))
|
||||
#define MCF_INTC1_L2IACK (*(vuint8 *)(&__IPSBAR[0xDE8]))
|
||||
#define MCF_INTC1_L3IACK (*(vuint8 *)(&__IPSBAR[0xDEC]))
|
||||
#define MCF_INTC1_L4IACK (*(vuint8 *)(&__IPSBAR[0xDF0]))
|
||||
#define MCF_INTC1_L5IACK (*(vuint8 *)(&__IPSBAR[0xDF4]))
|
||||
#define MCF_INTC1_L6IACK (*(vuint8 *)(&__IPSBAR[0xDF8]))
|
||||
#define MCF_INTC1_L7IACK (*(vuint8 *)(&__IPSBAR[0xDFC]))
|
||||
#define MCF_INTC1_ICR(x) (*(vuint8 *)(&__IPSBAR[0xD41 + ((x-1)*0x1)]))
|
||||
#define MCF_INTC1_LIACK(x) (*(vuint8 *)(&__IPSBAR[0xDE4 + ((x-1)*0x4)]))
|
||||
|
||||
#define MCF_INTC_IPRH(x) (*(vuint32*)(&__IPSBAR[0xC00 + ((x)*0x100)]))
|
||||
#define MCF_INTC_IPRL(x) (*(vuint32*)(&__IPSBAR[0xC04 + ((x)*0x100)]))
|
||||
#define MCF_INTC_IMRH(x) (*(vuint32*)(&__IPSBAR[0xC08 + ((x)*0x100)]))
|
||||
#define MCF_INTC_IMRL(x) (*(vuint32*)(&__IPSBAR[0xC0C + ((x)*0x100)]))
|
||||
#define MCF_INTC_INTFRCH(x) (*(vuint32*)(&__IPSBAR[0xC10 + ((x)*0x100)]))
|
||||
#define MCF_INTC_INTFRCL(x) (*(vuint32*)(&__IPSBAR[0xC14 + ((x)*0x100)]))
|
||||
#define MCF_INTC_IRLR(x) (*(vuint8 *)(&__IPSBAR[0xC18 + ((x)*0x100)]))
|
||||
#define MCF_INTC_IACKLPR(x) (*(vuint8 *)(&__IPSBAR[0xC19 + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR01(x) (*(vuint8 *)(&__IPSBAR[0xC41 + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR02(x) (*(vuint8 *)(&__IPSBAR[0xC42 + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR03(x) (*(vuint8 *)(&__IPSBAR[0xC43 + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR04(x) (*(vuint8 *)(&__IPSBAR[0xC44 + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR05(x) (*(vuint8 *)(&__IPSBAR[0xC45 + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR06(x) (*(vuint8 *)(&__IPSBAR[0xC46 + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR07(x) (*(vuint8 *)(&__IPSBAR[0xC47 + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR08(x) (*(vuint8 *)(&__IPSBAR[0xC48 + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR09(x) (*(vuint8 *)(&__IPSBAR[0xC49 + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR10(x) (*(vuint8 *)(&__IPSBAR[0xC4A + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR11(x) (*(vuint8 *)(&__IPSBAR[0xC4B + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR12(x) (*(vuint8 *)(&__IPSBAR[0xC4C + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR13(x) (*(vuint8 *)(&__IPSBAR[0xC4D + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR14(x) (*(vuint8 *)(&__IPSBAR[0xC4E + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR15(x) (*(vuint8 *)(&__IPSBAR[0xC4F + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR16(x) (*(vuint8 *)(&__IPSBAR[0xC50 + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR17(x) (*(vuint8 *)(&__IPSBAR[0xC51 + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR18(x) (*(vuint8 *)(&__IPSBAR[0xC52 + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR19(x) (*(vuint8 *)(&__IPSBAR[0xC53 + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR20(x) (*(vuint8 *)(&__IPSBAR[0xC54 + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR21(x) (*(vuint8 *)(&__IPSBAR[0xC55 + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR22(x) (*(vuint8 *)(&__IPSBAR[0xC56 + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR23(x) (*(vuint8 *)(&__IPSBAR[0xC57 + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR24(x) (*(vuint8 *)(&__IPSBAR[0xC58 + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR25(x) (*(vuint8 *)(&__IPSBAR[0xC59 + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR26(x) (*(vuint8 *)(&__IPSBAR[0xC5A + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR27(x) (*(vuint8 *)(&__IPSBAR[0xC5B + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR28(x) (*(vuint8 *)(&__IPSBAR[0xC5C + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR29(x) (*(vuint8 *)(&__IPSBAR[0xC5D + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR30(x) (*(vuint8 *)(&__IPSBAR[0xC5E + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR31(x) (*(vuint8 *)(&__IPSBAR[0xC5F + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR32(x) (*(vuint8 *)(&__IPSBAR[0xC60 + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR33(x) (*(vuint8 *)(&__IPSBAR[0xC61 + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR34(x) (*(vuint8 *)(&__IPSBAR[0xC62 + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR35(x) (*(vuint8 *)(&__IPSBAR[0xC63 + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR36(x) (*(vuint8 *)(&__IPSBAR[0xC64 + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR37(x) (*(vuint8 *)(&__IPSBAR[0xC65 + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR38(x) (*(vuint8 *)(&__IPSBAR[0xC66 + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR39(x) (*(vuint8 *)(&__IPSBAR[0xC67 + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR40(x) (*(vuint8 *)(&__IPSBAR[0xC68 + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR41(x) (*(vuint8 *)(&__IPSBAR[0xC69 + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR42(x) (*(vuint8 *)(&__IPSBAR[0xC6A + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR43(x) (*(vuint8 *)(&__IPSBAR[0xC6B + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR44(x) (*(vuint8 *)(&__IPSBAR[0xC6C + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR45(x) (*(vuint8 *)(&__IPSBAR[0xC6D + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR46(x) (*(vuint8 *)(&__IPSBAR[0xC6E + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR47(x) (*(vuint8 *)(&__IPSBAR[0xC6F + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR48(x) (*(vuint8 *)(&__IPSBAR[0xC70 + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR49(x) (*(vuint8 *)(&__IPSBAR[0xC71 + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR50(x) (*(vuint8 *)(&__IPSBAR[0xC72 + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR51(x) (*(vuint8 *)(&__IPSBAR[0xC73 + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR52(x) (*(vuint8 *)(&__IPSBAR[0xC74 + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR53(x) (*(vuint8 *)(&__IPSBAR[0xC75 + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR54(x) (*(vuint8 *)(&__IPSBAR[0xC76 + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR55(x) (*(vuint8 *)(&__IPSBAR[0xC77 + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR56(x) (*(vuint8 *)(&__IPSBAR[0xC78 + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR57(x) (*(vuint8 *)(&__IPSBAR[0xC79 + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR58(x) (*(vuint8 *)(&__IPSBAR[0xC7A + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR59(x) (*(vuint8 *)(&__IPSBAR[0xC7B + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR60(x) (*(vuint8 *)(&__IPSBAR[0xC7C + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR61(x) (*(vuint8 *)(&__IPSBAR[0xC7D + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR62(x) (*(vuint8 *)(&__IPSBAR[0xC7E + ((x)*0x100)]))
|
||||
#define MCF_INTC_ICR63(x) (*(vuint8 *)(&__IPSBAR[0xC7F + ((x)*0x100)]))
|
||||
#define MCF_INTC_SWIACK(x) (*(vuint8 *)(&__IPSBAR[0xCE0 + ((x)*0x100)]))
|
||||
#define MCF_INTC_L1IACK(x) (*(vuint8 *)(&__IPSBAR[0xCE4 + ((x)*0x100)]))
|
||||
#define MCF_INTC_L2IACK(x) (*(vuint8 *)(&__IPSBAR[0xCE8 + ((x)*0x100)]))
|
||||
#define MCF_INTC_L3IACK(x) (*(vuint8 *)(&__IPSBAR[0xCEC + ((x)*0x100)]))
|
||||
#define MCF_INTC_L4IACK(x) (*(vuint8 *)(&__IPSBAR[0xCF0 + ((x)*0x100)]))
|
||||
#define MCF_INTC_L5IACK(x) (*(vuint8 *)(&__IPSBAR[0xCF4 + ((x)*0x100)]))
|
||||
#define MCF_INTC_L6IACK(x) (*(vuint8 *)(&__IPSBAR[0xCF8 + ((x)*0x100)]))
|
||||
#define MCF_INTC_L7IACK(x) (*(vuint8 *)(&__IPSBAR[0xCFC + ((x)*0x100)]))
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC_IPRH */
|
||||
#define MCF_INTC_IPRH_INT32 (0x1)
|
||||
#define MCF_INTC_IPRH_INT33 (0x2)
|
||||
#define MCF_INTC_IPRH_INT34 (0x4)
|
||||
#define MCF_INTC_IPRH_INT35 (0x8)
|
||||
#define MCF_INTC_IPRH_INT36 (0x10)
|
||||
#define MCF_INTC_IPRH_INT37 (0x20)
|
||||
#define MCF_INTC_IPRH_INT38 (0x40)
|
||||
#define MCF_INTC_IPRH_INT39 (0x80)
|
||||
#define MCF_INTC_IPRH_INT40 (0x100)
|
||||
#define MCF_INTC_IPRH_INT41 (0x200)
|
||||
#define MCF_INTC_IPRH_INT42 (0x400)
|
||||
#define MCF_INTC_IPRH_INT43 (0x800)
|
||||
#define MCF_INTC_IPRH_INT44 (0x1000)
|
||||
#define MCF_INTC_IPRH_INT45 (0x2000)
|
||||
#define MCF_INTC_IPRH_INT46 (0x4000)
|
||||
#define MCF_INTC_IPRH_INT47 (0x8000)
|
||||
#define MCF_INTC_IPRH_INT48 (0x10000)
|
||||
#define MCF_INTC_IPRH_INT49 (0x20000)
|
||||
#define MCF_INTC_IPRH_INT50 (0x40000)
|
||||
#define MCF_INTC_IPRH_INT51 (0x80000)
|
||||
#define MCF_INTC_IPRH_INT52 (0x100000)
|
||||
#define MCF_INTC_IPRH_INT53 (0x200000)
|
||||
#define MCF_INTC_IPRH_INT54 (0x400000)
|
||||
#define MCF_INTC_IPRH_INT55 (0x800000)
|
||||
#define MCF_INTC_IPRH_INT56 (0x1000000)
|
||||
#define MCF_INTC_IPRH_INT57 (0x2000000)
|
||||
#define MCF_INTC_IPRH_INT58 (0x4000000)
|
||||
#define MCF_INTC_IPRH_INT59 (0x8000000)
|
||||
#define MCF_INTC_IPRH_INT60 (0x10000000)
|
||||
#define MCF_INTC_IPRH_INT61 (0x20000000)
|
||||
#define MCF_INTC_IPRH_INT62 (0x40000000)
|
||||
#define MCF_INTC_IPRH_INT63 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC_IPRL */
|
||||
#define MCF_INTC_IPRL_INT1 (0x2)
|
||||
#define MCF_INTC_IPRL_INT2 (0x4)
|
||||
#define MCF_INTC_IPRL_INT3 (0x8)
|
||||
#define MCF_INTC_IPRL_INT4 (0x10)
|
||||
#define MCF_INTC_IPRL_INT5 (0x20)
|
||||
#define MCF_INTC_IPRL_INT6 (0x40)
|
||||
#define MCF_INTC_IPRL_INT7 (0x80)
|
||||
#define MCF_INTC_IPRL_INT8 (0x100)
|
||||
#define MCF_INTC_IPRL_INT9 (0x200)
|
||||
#define MCF_INTC_IPRL_INT10 (0x400)
|
||||
#define MCF_INTC_IPRL_INT11 (0x800)
|
||||
#define MCF_INTC_IPRL_INT12 (0x1000)
|
||||
#define MCF_INTC_IPRL_INT13 (0x2000)
|
||||
#define MCF_INTC_IPRL_INT14 (0x4000)
|
||||
#define MCF_INTC_IPRL_INT15 (0x8000)
|
||||
#define MCF_INTC_IPRL_INT16 (0x10000)
|
||||
#define MCF_INTC_IPRL_INT17 (0x20000)
|
||||
#define MCF_INTC_IPRL_INT18 (0x40000)
|
||||
#define MCF_INTC_IPRL_INT19 (0x80000)
|
||||
#define MCF_INTC_IPRL_INT20 (0x100000)
|
||||
#define MCF_INTC_IPRL_INT21 (0x200000)
|
||||
#define MCF_INTC_IPRL_INT22 (0x400000)
|
||||
#define MCF_INTC_IPRL_INT23 (0x800000)
|
||||
#define MCF_INTC_IPRL_INT24 (0x1000000)
|
||||
#define MCF_INTC_IPRL_INT25 (0x2000000)
|
||||
#define MCF_INTC_IPRL_INT26 (0x4000000)
|
||||
#define MCF_INTC_IPRL_INT27 (0x8000000)
|
||||
#define MCF_INTC_IPRL_INT28 (0x10000000)
|
||||
#define MCF_INTC_IPRL_INT29 (0x20000000)
|
||||
#define MCF_INTC_IPRL_INT30 (0x40000000)
|
||||
#define MCF_INTC_IPRL_INT31 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC_IMRH */
|
||||
#define MCF_INTC_IMRH_INT_MASK32 (0x1)
|
||||
#define MCF_INTC_IMRH_INT_MASK33 (0x2)
|
||||
#define MCF_INTC_IMRH_INT_MASK34 (0x4)
|
||||
#define MCF_INTC_IMRH_INT_MASK35 (0x8)
|
||||
#define MCF_INTC_IMRH_INT_MASK36 (0x10)
|
||||
#define MCF_INTC_IMRH_INT_MASK37 (0x20)
|
||||
#define MCF_INTC_IMRH_INT_MASK38 (0x40)
|
||||
#define MCF_INTC_IMRH_INT_MASK39 (0x80)
|
||||
#define MCF_INTC_IMRH_INT_MASK40 (0x100)
|
||||
#define MCF_INTC_IMRH_INT_MASK41 (0x200)
|
||||
#define MCF_INTC_IMRH_INT_MASK42 (0x400)
|
||||
#define MCF_INTC_IMRH_INT_MASK43 (0x800)
|
||||
#define MCF_INTC_IMRH_INT_MASK44 (0x1000)
|
||||
#define MCF_INTC_IMRH_INT_MASK45 (0x2000)
|
||||
#define MCF_INTC_IMRH_INT_MASK46 (0x4000)
|
||||
#define MCF_INTC_IMRH_INT_MASK47 (0x8000)
|
||||
#define MCF_INTC_IMRH_INT_MASK48 (0x10000)
|
||||
#define MCF_INTC_IMRH_INT_MASK49 (0x20000)
|
||||
#define MCF_INTC_IMRH_INT_MASK50 (0x40000)
|
||||
#define MCF_INTC_IMRH_INT_MASK51 (0x80000)
|
||||
#define MCF_INTC_IMRH_INT_MASK52 (0x100000)
|
||||
#define MCF_INTC_IMRH_INT_MASK53 (0x200000)
|
||||
#define MCF_INTC_IMRH_INT_MASK54 (0x400000)
|
||||
#define MCF_INTC_IMRH_INT_MASK55 (0x800000)
|
||||
#define MCF_INTC_IMRH_INT_MASK56 (0x1000000)
|
||||
#define MCF_INTC_IMRH_INT_MASK57 (0x2000000)
|
||||
#define MCF_INTC_IMRH_INT_MASK58 (0x4000000)
|
||||
#define MCF_INTC_IMRH_INT_MASK59 (0x8000000)
|
||||
#define MCF_INTC_IMRH_INT_MASK60 (0x10000000)
|
||||
#define MCF_INTC_IMRH_INT_MASK61 (0x20000000)
|
||||
#define MCF_INTC_IMRH_INT_MASK62 (0x40000000)
|
||||
#define MCF_INTC_IMRH_INT_MASK63 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC_IMRL */
|
||||
#define MCF_INTC_IMRL_MASKALL (0x1)
|
||||
#define MCF_INTC_IMRL_INT_MASK1 (0x2)
|
||||
#define MCF_INTC_IMRL_INT_MASK2 (0x4)
|
||||
#define MCF_INTC_IMRL_INT_MASK3 (0x8)
|
||||
#define MCF_INTC_IMRL_INT_MASK4 (0x10)
|
||||
#define MCF_INTC_IMRL_INT_MASK5 (0x20)
|
||||
#define MCF_INTC_IMRL_INT_MASK6 (0x40)
|
||||
#define MCF_INTC_IMRL_INT_MASK7 (0x80)
|
||||
#define MCF_INTC_IMRL_INT_MASK8 (0x100)
|
||||
#define MCF_INTC_IMRL_INT_MASK9 (0x200)
|
||||
#define MCF_INTC_IMRL_INT_MASK10 (0x400)
|
||||
#define MCF_INTC_IMRL_INT_MASK11 (0x800)
|
||||
#define MCF_INTC_IMRL_INT_MASK12 (0x1000)
|
||||
#define MCF_INTC_IMRL_INT_MASK13 (0x2000)
|
||||
#define MCF_INTC_IMRL_INT_MASK14 (0x4000)
|
||||
#define MCF_INTC_IMRL_INT_MASK15 (0x8000)
|
||||
#define MCF_INTC_IMRL_INT_MASK16 (0x10000)
|
||||
#define MCF_INTC_IMRL_INT_MASK17 (0x20000)
|
||||
#define MCF_INTC_IMRL_INT_MASK18 (0x40000)
|
||||
#define MCF_INTC_IMRL_INT_MASK19 (0x80000)
|
||||
#define MCF_INTC_IMRL_INT_MASK20 (0x100000)
|
||||
#define MCF_INTC_IMRL_INT_MASK21 (0x200000)
|
||||
#define MCF_INTC_IMRL_INT_MASK22 (0x400000)
|
||||
#define MCF_INTC_IMRL_INT_MASK23 (0x800000)
|
||||
#define MCF_INTC_IMRL_INT_MASK24 (0x1000000)
|
||||
#define MCF_INTC_IMRL_INT_MASK25 (0x2000000)
|
||||
#define MCF_INTC_IMRL_INT_MASK26 (0x4000000)
|
||||
#define MCF_INTC_IMRL_INT_MASK27 (0x8000000)
|
||||
#define MCF_INTC_IMRL_INT_MASK28 (0x10000000)
|
||||
#define MCF_INTC_IMRL_INT_MASK29 (0x20000000)
|
||||
#define MCF_INTC_IMRL_INT_MASK30 (0x40000000)
|
||||
#define MCF_INTC_IMRL_INT_MASK31 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC_INTFRCH */
|
||||
#define MCF_INTC_INTFRCH_INTFRC32 (0x1)
|
||||
#define MCF_INTC_INTFRCH_INTFRC33 (0x2)
|
||||
#define MCF_INTC_INTFRCH_INTFRC34 (0x4)
|
||||
#define MCF_INTC_INTFRCH_INTFRC35 (0x8)
|
||||
#define MCF_INTC_INTFRCH_INTFRC36 (0x10)
|
||||
#define MCF_INTC_INTFRCH_INTFRC37 (0x20)
|
||||
#define MCF_INTC_INTFRCH_INTFRC38 (0x40)
|
||||
#define MCF_INTC_INTFRCH_INTFRC39 (0x80)
|
||||
#define MCF_INTC_INTFRCH_INTFRC40 (0x100)
|
||||
#define MCF_INTC_INTFRCH_INTFRC41 (0x200)
|
||||
#define MCF_INTC_INTFRCH_INTFRC42 (0x400)
|
||||
#define MCF_INTC_INTFRCH_INTFRC43 (0x800)
|
||||
#define MCF_INTC_INTFRCH_INTFRC44 (0x1000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC45 (0x2000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC46 (0x4000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC47 (0x8000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC48 (0x10000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC49 (0x20000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC50 (0x40000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC51 (0x80000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC52 (0x100000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC53 (0x200000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC54 (0x400000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC55 (0x800000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC56 (0x1000000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC57 (0x2000000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC58 (0x4000000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC59 (0x8000000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC60 (0x10000000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC61 (0x20000000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC62 (0x40000000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC63 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC_INTFRCL */
|
||||
#define MCF_INTC_INTFRCL_INTFRC1 (0x2)
|
||||
#define MCF_INTC_INTFRCL_INTFRC2 (0x4)
|
||||
#define MCF_INTC_INTFRCL_INTFRC3 (0x8)
|
||||
#define MCF_INTC_INTFRCL_INTFRC4 (0x10)
|
||||
#define MCF_INTC_INTFRCL_INTFRC5 (0x20)
|
||||
#define MCF_INTC_INTFRCL_INTFRC6 (0x40)
|
||||
#define MCF_INTC_INTFRCL_INTFRC7 (0x80)
|
||||
#define MCF_INTC_INTFRCL_INTFRC8 (0x100)
|
||||
#define MCF_INTC_INTFRCL_INTFRC9 (0x200)
|
||||
#define MCF_INTC_INTFRCL_INTFRC10 (0x400)
|
||||
#define MCF_INTC_INTFRCL_INTFRC11 (0x800)
|
||||
#define MCF_INTC_INTFRCL_INTFRC12 (0x1000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC13 (0x2000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC14 (0x4000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC15 (0x8000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC16 (0x10000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC17 (0x20000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC18 (0x40000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC19 (0x80000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC20 (0x100000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC21 (0x200000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC22 (0x400000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC23 (0x800000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC24 (0x1000000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC25 (0x2000000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC26 (0x4000000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC27 (0x8000000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC28 (0x10000000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC29 (0x20000000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC30 (0x40000000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC31 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC_IRLR */
|
||||
#define MCF_INTC_IRLR_IRQ(x) (((x)&0x7F)<<0x1)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC_IACKLPR */
|
||||
#define MCF_INTC_IACKLPR_PRI(x) (((x)&0xF)<<0)
|
||||
#define MCF_INTC_IACKLPR_LEVEL(x) (((x)&0x7)<<0x4)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC_ICR */
|
||||
#define MCF_INTC_ICR_IP(x) (((x)&0x7)<<0)
|
||||
#define MCF_INTC_ICR_IL(x) (((x)&0x7)<<0x3)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC_SWIACK */
|
||||
#define MCF_INTC_SWIACK_VECTOR(x) (((x)&0xFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC_LIACK */
|
||||
#define MCF_INTC_LIACK_VECTOR(x) (((x)&0xFF)<<0)
|
||||
|
||||
|
||||
#endif /* __MCF52235_INTC_H__ */
|
||||
|
|
@ -0,0 +1,95 @@
|
|||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2007/03/19 Revision: 0.91
|
||||
*/
|
||||
|
||||
#ifndef __MCF52235_PAD_H__
|
||||
#define __MCF52235_PAD_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Common GPIO Registers
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_PAD_PWOR (*(vuint16*)(&__IPSBAR[0x100078]))
|
||||
#define MCF_PAD_PDSR1 (*(vuint16*)(&__IPSBAR[0x10007A]))
|
||||
#define MCF_PAD_PDSR0 (*(vuint32*)(&__IPSBAR[0x10007C]))
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_PAD_PWOR */
|
||||
#define MCF_PAD_PWOR_PWOR0 (0x1)
|
||||
#define MCF_PAD_PWOR_PWOR1 (0x2)
|
||||
#define MCF_PAD_PWOR_PWOR2 (0x4)
|
||||
#define MCF_PAD_PWOR_PWOR3 (0x8)
|
||||
#define MCF_PAD_PWOR_PWOR4 (0x10)
|
||||
#define MCF_PAD_PWOR_PWOR5 (0x20)
|
||||
#define MCF_PAD_PWOR_PWOR6 (0x40)
|
||||
#define MCF_PAD_PWOR_PWOR7 (0x80)
|
||||
#define MCF_PAD_PWOR_PWOR8 (0x100)
|
||||
#define MCF_PAD_PWOR_PWOR9 (0x200)
|
||||
#define MCF_PAD_PWOR_PWOR10 (0x400)
|
||||
#define MCF_PAD_PWOR_PWOR11 (0x800)
|
||||
#define MCF_PAD_PWOR_PWOR12 (0x1000)
|
||||
#define MCF_PAD_PWOR_PWOR13 (0x2000)
|
||||
#define MCF_PAD_PWOR_PWOR14 (0x4000)
|
||||
#define MCF_PAD_PWOR_PWOR15 (0x8000)
|
||||
|
||||
/* Bit definitions and macros for MCF_PAD_PDSR1 */
|
||||
#define MCF_PAD_PDSR1_PDSR32 (0x1)
|
||||
#define MCF_PAD_PDSR1_PDSR33 (0x2)
|
||||
#define MCF_PAD_PDSR1_PDSR34 (0x4)
|
||||
#define MCF_PAD_PDSR1_PDSR35 (0x8)
|
||||
#define MCF_PAD_PDSR1_PDSR36 (0x10)
|
||||
#define MCF_PAD_PDSR1_PDSR37 (0x20)
|
||||
#define MCF_PAD_PDSR1_PDSR38 (0x40)
|
||||
#define MCF_PAD_PDSR1_PDSR39 (0x80)
|
||||
#define MCF_PAD_PDSR1_PDSR40 (0x100)
|
||||
#define MCF_PAD_PDSR1_PDSR41 (0x200)
|
||||
#define MCF_PAD_PDSR1_PDSR42 (0x400)
|
||||
#define MCF_PAD_PDSR1_PDSR43 (0x800)
|
||||
#define MCF_PAD_PDSR1_PDSR44 (0x1000)
|
||||
#define MCF_PAD_PDSR1_PDSR45 (0x2000)
|
||||
#define MCF_PAD_PDSR1_PDSR46 (0x4000)
|
||||
#define MCF_PAD_PDSR1_PDSR47 (0x8000)
|
||||
|
||||
/* Bit definitions and macros for MCF_PAD_PDSR0 */
|
||||
#define MCF_PAD_PDSR0_PDSR0 (0x1)
|
||||
#define MCF_PAD_PDSR0_PDSR1 (0x2)
|
||||
#define MCF_PAD_PDSR0_PDSR2 (0x4)
|
||||
#define MCF_PAD_PDSR0_PDSR3 (0x8)
|
||||
#define MCF_PAD_PDSR0_PDSR4 (0x10)
|
||||
#define MCF_PAD_PDSR0_PDSR5 (0x20)
|
||||
#define MCF_PAD_PDSR0_PDSR6 (0x40)
|
||||
#define MCF_PAD_PDSR0_PDSR7 (0x80)
|
||||
#define MCF_PAD_PDSR0_PDSR8 (0x100)
|
||||
#define MCF_PAD_PDSR0_PDSR9 (0x200)
|
||||
#define MCF_PAD_PDSR0_PDSR10 (0x400)
|
||||
#define MCF_PAD_PDSR0_PDSR11 (0x800)
|
||||
#define MCF_PAD_PDSR0_PDSR12 (0x1000)
|
||||
#define MCF_PAD_PDSR0_PDSR13 (0x2000)
|
||||
#define MCF_PAD_PDSR0_PDSR14 (0x4000)
|
||||
#define MCF_PAD_PDSR0_PDSR15 (0x8000)
|
||||
#define MCF_PAD_PDSR0_PDSR16 (0x10000)
|
||||
#define MCF_PAD_PDSR0_PDSR17 (0x20000)
|
||||
#define MCF_PAD_PDSR0_PDSR18 (0x40000)
|
||||
#define MCF_PAD_PDSR0_PDSR19 (0x80000)
|
||||
#define MCF_PAD_PDSR0_PDSR20 (0x100000)
|
||||
#define MCF_PAD_PDSR0_PDSR21 (0x200000)
|
||||
#define MCF_PAD_PDSR0_PDSR22 (0x400000)
|
||||
#define MCF_PAD_PDSR0_PDSR23 (0x800000)
|
||||
#define MCF_PAD_PDSR0_PDSR24 (0x1000000)
|
||||
#define MCF_PAD_PDSR0_PDSR25 (0x2000000)
|
||||
#define MCF_PAD_PDSR0_PDSR26 (0x4000000)
|
||||
#define MCF_PAD_PDSR0_PDSR27 (0x8000000)
|
||||
#define MCF_PAD_PDSR0_PDSR28 (0x10000000)
|
||||
#define MCF_PAD_PDSR0_PDSR29 (0x20000000)
|
||||
#define MCF_PAD_PDSR0_PDSR30 (0x40000000)
|
||||
#define MCF_PAD_PDSR0_PDSR31 (0x80000000)
|
||||
|
||||
|
||||
#endif /* __MCF52235_PAD_H__ */
|
||||
|
|
@ -0,0 +1,49 @@
|
|||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2007/03/19 Revision: 0.91
|
||||
*/
|
||||
|
||||
#ifndef __MCF52235_PIT_H__
|
||||
#define __MCF52235_PIT_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Programmable Interrupt Timer (PIT)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_PIT0_PCSR (*(vuint16*)(&__IPSBAR[0x150000]))
|
||||
#define MCF_PIT0_PMR (*(vuint16*)(&__IPSBAR[0x150002]))
|
||||
#define MCF_PIT0_PCNTR (*(vuint16*)(&__IPSBAR[0x150004]))
|
||||
|
||||
#define MCF_PIT1_PCSR (*(vuint16*)(&__IPSBAR[0x160000]))
|
||||
#define MCF_PIT1_PMR (*(vuint16*)(&__IPSBAR[0x160002]))
|
||||
#define MCF_PIT1_PCNTR (*(vuint16*)(&__IPSBAR[0x160004]))
|
||||
|
||||
#define MCF_PIT_PCSR(x) (*(vuint16*)(&__IPSBAR[0x150000 + ((x)*0x10000)]))
|
||||
#define MCF_PIT_PMR(x) (*(vuint16*)(&__IPSBAR[0x150002 + ((x)*0x10000)]))
|
||||
#define MCF_PIT_PCNTR(x) (*(vuint16*)(&__IPSBAR[0x150004 + ((x)*0x10000)]))
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_PIT_PCSR */
|
||||
#define MCF_PIT_PCSR_EN (0x1)
|
||||
#define MCF_PIT_PCSR_RLD (0x2)
|
||||
#define MCF_PIT_PCSR_PIF (0x4)
|
||||
#define MCF_PIT_PCSR_PIE (0x8)
|
||||
#define MCF_PIT_PCSR_OVW (0x10)
|
||||
#define MCF_PIT_PCSR_DBG (0x20)
|
||||
#define MCF_PIT_PCSR_DOZE (0x40)
|
||||
#define MCF_PIT_PCSR_PRE(x) (((x)&0xF)<<0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_PIT_PMR */
|
||||
#define MCF_PIT_PMR_PM(x) (((x)&0xFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_PIT_PCNTR */
|
||||
#define MCF_PIT_PCNTR_PC(x) (((x)&0xFFFF)<<0)
|
||||
|
||||
|
||||
#endif /* __MCF52235_PIT_H__ */
|
||||
|
|
@ -0,0 +1,41 @@
|
|||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2007/03/19 Revision: 0.91
|
||||
*/
|
||||
|
||||
#ifndef __MCF52235_PMM_H__
|
||||
#define __MCF52235_PMM_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Power Management (PMM)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_PMM_LPICR (*(vuint8 *)(&__IPSBAR[0x12]))
|
||||
#define MCF_PMM_LPCR (*(vuint8 *)(&__IPSBAR[0x110007]))
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_PMM_LPICR */
|
||||
#define MCF_PMM_LPICR_XLPM_IPL(x) (((x)&0x7)<<0x4)
|
||||
#define MCF_PMM_LPICR_ENBSTOP (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_PMM_LPCR */
|
||||
#define MCF_PMM_LPCR_LVDSE (0x2)
|
||||
#define MCF_PMM_LPCR_STPMD(x) (((x)&0x3)<<0x3)
|
||||
#define MCF_PMM_LPCR_STPMD_SYS_DISABLED (0)
|
||||
#define MCF_PMM_LPCR_STPMD_SYS_CLKOUT_DISABLED (0x8)
|
||||
#define MCF_PMM_LPCR_STPMD_ONLY_OSC_ENABLED (0x10)
|
||||
#define MCF_PMM_LPCR_STPMD_ALL_DISABLED (0x18)
|
||||
#define MCF_PMM_LPCR_LPMD(x) (((x)&0x3)<<0x6)
|
||||
#define MCF_PMM_LPCR_LPMD_RUN (0)
|
||||
#define MCF_PMM_LPCR_LPMD_DOZE (0x40)
|
||||
#define MCF_PMM_LPCR_LPMD_WAIT (0x80)
|
||||
#define MCF_PMM_LPCR_LPMD_STOP (0xC0)
|
||||
|
||||
|
||||
#endif /* __MCF52235_PMM_H__ */
|
||||
134
Demo/ColdFire_MCF52233_Eclipse/RTOSDemo/MCF5223x/MCF52235_PWM.h
Normal file
134
Demo/ColdFire_MCF52233_Eclipse/RTOSDemo/MCF5223x/MCF52235_PWM.h
Normal file
|
|
@ -0,0 +1,134 @@
|
|||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2007/03/19 Revision: 0.91
|
||||
*/
|
||||
|
||||
#ifndef __MCF52235_PWM_H__
|
||||
#define __MCF52235_PWM_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Pulse Width Modulation (PWM)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_PWM_PWME (*(vuint8 *)(&__IPSBAR[0x1B0000]))
|
||||
#define MCF_PWM_PWMPOL (*(vuint8 *)(&__IPSBAR[0x1B0001]))
|
||||
#define MCF_PWM_PWMCLK (*(vuint8 *)(&__IPSBAR[0x1B0002]))
|
||||
#define MCF_PWM_PWMPRCLK (*(vuint8 *)(&__IPSBAR[0x1B0003]))
|
||||
#define MCF_PWM_PWMCAE (*(vuint8 *)(&__IPSBAR[0x1B0004]))
|
||||
#define MCF_PWM_PWMCTL (*(vuint8 *)(&__IPSBAR[0x1B0005]))
|
||||
#define MCF_PWM_PWMSCLA (*(vuint8 *)(&__IPSBAR[0x1B0008]))
|
||||
#define MCF_PWM_PWMSCLB (*(vuint8 *)(&__IPSBAR[0x1B0009]))
|
||||
#define MCF_PWM_PWMCNT0 (*(vuint8 *)(&__IPSBAR[0x1B000C]))
|
||||
#define MCF_PWM_PWMCNT1 (*(vuint8 *)(&__IPSBAR[0x1B000D]))
|
||||
#define MCF_PWM_PWMCNT2 (*(vuint8 *)(&__IPSBAR[0x1B000E]))
|
||||
#define MCF_PWM_PWMCNT3 (*(vuint8 *)(&__IPSBAR[0x1B000F]))
|
||||
#define MCF_PWM_PWMCNT4 (*(vuint8 *)(&__IPSBAR[0x1B0010]))
|
||||
#define MCF_PWM_PWMCNT5 (*(vuint8 *)(&__IPSBAR[0x1B0011]))
|
||||
#define MCF_PWM_PWMCNT6 (*(vuint8 *)(&__IPSBAR[0x1B0012]))
|
||||
#define MCF_PWM_PWMCNT7 (*(vuint8 *)(&__IPSBAR[0x1B0013]))
|
||||
#define MCF_PWM_PWMPER0 (*(vuint8 *)(&__IPSBAR[0x1B0014]))
|
||||
#define MCF_PWM_PWMPER1 (*(vuint8 *)(&__IPSBAR[0x1B0015]))
|
||||
#define MCF_PWM_PWMPER2 (*(vuint8 *)(&__IPSBAR[0x1B0016]))
|
||||
#define MCF_PWM_PWMPER3 (*(vuint8 *)(&__IPSBAR[0x1B0017]))
|
||||
#define MCF_PWM_PWMPER4 (*(vuint8 *)(&__IPSBAR[0x1B0018]))
|
||||
#define MCF_PWM_PWMPER5 (*(vuint8 *)(&__IPSBAR[0x1B0019]))
|
||||
#define MCF_PWM_PWMPER6 (*(vuint8 *)(&__IPSBAR[0x1B001A]))
|
||||
#define MCF_PWM_PWMPER7 (*(vuint8 *)(&__IPSBAR[0x1B001B]))
|
||||
#define MCF_PWM_PWMDTY0 (*(vuint8 *)(&__IPSBAR[0x1B001C]))
|
||||
#define MCF_PWM_PWMDTY1 (*(vuint8 *)(&__IPSBAR[0x1B001D]))
|
||||
#define MCF_PWM_PWMDTY2 (*(vuint8 *)(&__IPSBAR[0x1B001E]))
|
||||
#define MCF_PWM_PWMDTY3 (*(vuint8 *)(&__IPSBAR[0x1B001F]))
|
||||
#define MCF_PWM_PWMDTY4 (*(vuint8 *)(&__IPSBAR[0x1B0020]))
|
||||
#define MCF_PWM_PWMDTY5 (*(vuint8 *)(&__IPSBAR[0x1B0021]))
|
||||
#define MCF_PWM_PWMDTY6 (*(vuint8 *)(&__IPSBAR[0x1B0022]))
|
||||
#define MCF_PWM_PWMDTY7 (*(vuint8 *)(&__IPSBAR[0x1B0023]))
|
||||
#define MCF_PWM_PWMSDN (*(vuint8 *)(&__IPSBAR[0x1B0024]))
|
||||
#define MCF_PWM_PWMCNT(x) (*(vuint8 *)(&__IPSBAR[0x1B000C + ((x)*0x1)]))
|
||||
#define MCF_PWM_PWMPER(x) (*(vuint8 *)(&__IPSBAR[0x1B0014 + ((x)*0x1)]))
|
||||
#define MCF_PWM_PWMDTY(x) (*(vuint8 *)(&__IPSBAR[0x1B001C + ((x)*0x1)]))
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_PWM_PWME */
|
||||
#define MCF_PWM_PWME_PWME0 (0x1)
|
||||
#define MCF_PWM_PWME_PWME1 (0x2)
|
||||
#define MCF_PWM_PWME_PWME2 (0x4)
|
||||
#define MCF_PWM_PWME_PWME3 (0x8)
|
||||
#define MCF_PWM_PWME_PWME4 (0x10)
|
||||
#define MCF_PWM_PWME_PWME5 (0x20)
|
||||
#define MCF_PWM_PWME_PWME6 (0x40)
|
||||
#define MCF_PWM_PWME_PWME7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_PWM_PWMPOL */
|
||||
#define MCF_PWM_PWMPOL_PPOL0 (0x1)
|
||||
#define MCF_PWM_PWMPOL_PPOL1 (0x2)
|
||||
#define MCF_PWM_PWMPOL_PPOL2 (0x4)
|
||||
#define MCF_PWM_PWMPOL_PPOL3 (0x8)
|
||||
#define MCF_PWM_PWMPOL_PPOL4 (0x10)
|
||||
#define MCF_PWM_PWMPOL_PPOL5 (0x20)
|
||||
#define MCF_PWM_PWMPOL_PPOL6 (0x40)
|
||||
#define MCF_PWM_PWMPOL_PPOL7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_PWM_PWMCLK */
|
||||
#define MCF_PWM_PWMCLK_PCLK0 (0x1)
|
||||
#define MCF_PWM_PWMCLK_PCLK1 (0x2)
|
||||
#define MCF_PWM_PWMCLK_PCLK2 (0x4)
|
||||
#define MCF_PWM_PWMCLK_PCLK3 (0x8)
|
||||
#define MCF_PWM_PWMCLK_PCLK4 (0x10)
|
||||
#define MCF_PWM_PWMCLK_PCLK5 (0x20)
|
||||
#define MCF_PWM_PWMCLK_PCLK6 (0x40)
|
||||
#define MCF_PWM_PWMCLK_PCLK7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_PWM_PWMPRCLK */
|
||||
#define MCF_PWM_PWMPRCLK_PCKA(x) (((x)&0x7)<<0)
|
||||
#define MCF_PWM_PWMPRCLK_PCKB(x) (((x)&0x7)<<0x4)
|
||||
|
||||
/* Bit definitions and macros for MCF_PWM_PWMCAE */
|
||||
#define MCF_PWM_PWMCAE_CAE0 (0x1)
|
||||
#define MCF_PWM_PWMCAE_CAE1 (0x2)
|
||||
#define MCF_PWM_PWMCAE_CAE2 (0x4)
|
||||
#define MCF_PWM_PWMCAE_CAE3 (0x8)
|
||||
#define MCF_PWM_PWMCAE_CAE4 (0x10)
|
||||
#define MCF_PWM_PWMCAE_CAE5 (0x20)
|
||||
#define MCF_PWM_PWMCAE_CAE6 (0x40)
|
||||
#define MCF_PWM_PWMCAE_CAE7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_PWM_PWMCTL */
|
||||
#define MCF_PWM_PWMCTL_PFRZ (0x4)
|
||||
#define MCF_PWM_PWMCTL_PSWAI (0x8)
|
||||
#define MCF_PWM_PWMCTL_CON01 (0x10)
|
||||
#define MCF_PWM_PWMCTL_CON23 (0x20)
|
||||
#define MCF_PWM_PWMCTL_CON45 (0x40)
|
||||
#define MCF_PWM_PWMCTL_CON67 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_PWM_PWMSCLA */
|
||||
#define MCF_PWM_PWMSCLA_SCALEA(x) (((x)&0xFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_PWM_PWMSCLB */
|
||||
#define MCF_PWM_PWMSCLB_SCALEB(x) (((x)&0xFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_PWM_PWMCNT */
|
||||
#define MCF_PWM_PWMCNT_COUNT(x) (((x)&0xFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_PWM_PWMPER */
|
||||
#define MCF_PWM_PWMPER_PERIOD(x) (((x)&0xFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_PWM_PWMDTY */
|
||||
#define MCF_PWM_PWMDTY_DUTY(x) (((x)&0xFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_PWM_PWMSDN */
|
||||
#define MCF_PWM_PWMSDN_SDNEN (0x1)
|
||||
#define MCF_PWM_PWMSDN_PWM7IL (0x2)
|
||||
#define MCF_PWM_PWMSDN_PWM7IN (0x4)
|
||||
#define MCF_PWM_PWMSDN_LVL (0x10)
|
||||
#define MCF_PWM_PWMSDN_RESTART (0x20)
|
||||
#define MCF_PWM_PWMSDN_IE (0x40)
|
||||
#define MCF_PWM_PWMSDN_IF (0x80)
|
||||
|
||||
|
||||
#endif /* __MCF52235_PWM_H__ */
|
||||
|
|
@ -0,0 +1,78 @@
|
|||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2007/03/19 Revision: 0.91
|
||||
*/
|
||||
|
||||
#ifndef __MCF52235_QSPI_H__
|
||||
#define __MCF52235_QSPI_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Queued Serial Peripheral Interface (QSPI)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_QSPI_QMR (*(vuint16*)(&__IPSBAR[0x340]))
|
||||
#define MCF_QSPI_QDLYR (*(vuint16*)(&__IPSBAR[0x344]))
|
||||
#define MCF_QSPI_QWR (*(vuint16*)(&__IPSBAR[0x348]))
|
||||
#define MCF_QSPI_QIR (*(vuint16*)(&__IPSBAR[0x34C]))
|
||||
#define MCF_QSPI_QAR (*(vuint16*)(&__IPSBAR[0x350]))
|
||||
#define MCF_QSPI_QDR (*(vuint16*)(&__IPSBAR[0x354]))
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_QSPI_QMR */
|
||||
#define MCF_QSPI_QMR_BAUD(x) (((x)&0xFF)<<0)
|
||||
#define MCF_QSPI_QMR_CPHA (0x100)
|
||||
#define MCF_QSPI_QMR_CPOL (0x200)
|
||||
#define MCF_QSPI_QMR_BITS(x) (((x)&0xF)<<0xA)
|
||||
#define MCF_QSPI_QMR_DOHIE (0x4000)
|
||||
#define MCF_QSPI_QMR_MSTR (0x8000)
|
||||
|
||||
/* Bit definitions and macros for MCF_QSPI_QDLYR */
|
||||
#define MCF_QSPI_QDLYR_DTL(x) (((x)&0xFF)<<0)
|
||||
#define MCF_QSPI_QDLYR_QCD(x) (((x)&0x7F)<<0x8)
|
||||
#define MCF_QSPI_QDLYR_SPE (0x8000)
|
||||
|
||||
/* Bit definitions and macros for MCF_QSPI_QWR */
|
||||
#define MCF_QSPI_QWR_NEWQP(x) (((x)&0xF)<<0)
|
||||
#define MCF_QSPI_QWR_CPTQP(x) (((x)&0xF)<<0x4)
|
||||
#define MCF_QSPI_QWR_ENDQP(x) (((x)&0xF)<<0x8)
|
||||
#define MCF_QSPI_QWR_CSIV (0x1000)
|
||||
#define MCF_QSPI_QWR_WRTO (0x2000)
|
||||
#define MCF_QSPI_QWR_WREN (0x4000)
|
||||
#define MCF_QSPI_QWR_HALT (0x8000)
|
||||
|
||||
/* Bit definitions and macros for MCF_QSPI_QIR */
|
||||
#define MCF_QSPI_QIR_SPIF (0x1)
|
||||
#define MCF_QSPI_QIR_ABRT (0x4)
|
||||
#define MCF_QSPI_QIR_WCEF (0x8)
|
||||
#define MCF_QSPI_QIR_SPIFE (0x100)
|
||||
#define MCF_QSPI_QIR_ABRTE (0x400)
|
||||
#define MCF_QSPI_QIR_WCEFE (0x800)
|
||||
#define MCF_QSPI_QIR_ABRTL (0x1000)
|
||||
#define MCF_QSPI_QIR_ABRTB (0x4000)
|
||||
#define MCF_QSPI_QIR_WCEFB (0x8000)
|
||||
|
||||
/* Bit definitions and macros for MCF_QSPI_QAR */
|
||||
#define MCF_QSPI_QAR_ADDR(x) (((x)&0x3F)<<0)
|
||||
#define MCF_QSPI_QAR_TRANS (0)
|
||||
#define MCF_QSPI_QAR_RECV (0x10)
|
||||
#define MCF_QSPI_QAR_CMD (0x20)
|
||||
|
||||
/* Bit definitions and macros for MCF_QSPI_QDR */
|
||||
#define MCF_QSPI_QDR_DATA(x) (((x)&0xFFFF)<<0)
|
||||
#define MCF_QSPI_QDR_CONT (0x8000)
|
||||
#define MCF_QSPI_QDR_BITSE (0x4000)
|
||||
#define MCF_QSPI_QDR_DT (0x2000)
|
||||
#define MCF_QSPI_QDR_DSCK (0x1000)
|
||||
#define MCF_QSPI_QDR_QSPI_CS3 (0x800)
|
||||
#define MCF_QSPI_QDR_QSPI_CS2 (0x400)
|
||||
#define MCF_QSPI_QDR_QSPI_CS1 (0x200)
|
||||
#define MCF_QSPI_QDR_QSPI_CS0 (0x100)
|
||||
|
||||
|
||||
#endif /* __MCF52235_QSPI_H__ */
|
||||
|
|
@ -0,0 +1,45 @@
|
|||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2007/03/19 Revision: 0.91
|
||||
*/
|
||||
|
||||
#ifndef __MCF52235_RCM_H__
|
||||
#define __MCF52235_RCM_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Reset Controller Module (RCM)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_RCM_RCR (*(vuint8 *)(&__IPSBAR[0x110000]))
|
||||
#define MCF_RCM_RSR (*(vuint8 *)(&__IPSBAR[0x110001]))
|
||||
#define MCF_RCM_CCR (*(vuint16*)(&__IPSBAR[0x110004]))
|
||||
#define MCF_RCM_CIR (*(vuint16*)(&__IPSBAR[0x11000A]))
|
||||
|
||||
/* Bit definitions and macros for MCF_RCM_RCR */
|
||||
#define MCF_RCM_RCR_LVDE (0x1)
|
||||
#define MCF_RCM_RCR_LVDRE (0x4)
|
||||
#define MCF_RCM_RCR_LVDIE (0x8)
|
||||
#define MCF_RCM_RCR_LVDF (0x10)
|
||||
#define MCF_RCM_RCR_FRCRSTOUT (0x40)
|
||||
#define MCF_RCM_RCR_SOFTRST (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_RCM_RSR */
|
||||
#define MCF_RCM_RSR_LOL (0x1)
|
||||
#define MCF_RCM_RSR_LOC (0x2)
|
||||
#define MCF_RCM_RSR_EXT (0x4)
|
||||
#define MCF_RCM_RSR_POR (0x8)
|
||||
#define MCF_RCM_RSR_WDR (0x10)
|
||||
#define MCF_RCM_RSR_SOFT (0x20)
|
||||
#define MCF_RCM_RSR_LVD (0x40)
|
||||
|
||||
/* Bit definitions and macros for MCF_RCM_CCR */
|
||||
#define MCF_RCM_CCR_LOAD (0x8000)
|
||||
|
||||
|
||||
#endif /* __MCF52235_RCM_H__ */
|
||||
|
|
@ -0,0 +1,48 @@
|
|||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2007/03/19 Revision: 0.91
|
||||
*/
|
||||
|
||||
#ifndef __MCF52235_RNGA_H__
|
||||
#define __MCF52235_RNGA_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Random Number Generator (RNG)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_RNGA_RNGCR (*(vuint32*)(&__IPSBAR[0x1F0000]))
|
||||
#define MCF_RNGA_RNGSR (*(vuint32*)(&__IPSBAR[0x1F0004]))
|
||||
#define MCF_RNGA_RNGER (*(vuint32*)(&__IPSBAR[0x1F0008]))
|
||||
#define MCF_RNGA_RNGOUT (*(vuint32*)(&__IPSBAR[0x1F000C]))
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_RNGA_RNGCR */
|
||||
#define MCF_RNGA_RNGCR_GO (0x1)
|
||||
#define MCF_RNGA_RNGCR_HA (0x2)
|
||||
#define MCF_RNGA_RNGCR_IM (0x4)
|
||||
#define MCF_RNGA_RNGCR_CI (0x8)
|
||||
#define MCF_RNGA_RNGCR_SLM (0x10)
|
||||
|
||||
/* Bit definitions and macros for MCF_RNGA_RNGSR */
|
||||
#define MCF_RNGA_RNGSR_SV (0x1)
|
||||
#define MCF_RNGA_RNGSR_LRS (0x2)
|
||||
#define MCF_RNGA_RNGSR_OUF (0x4)
|
||||
#define MCF_RNGA_RNGSR_EI (0x8)
|
||||
#define MCF_RNGA_RNGSR_SLP (0x10)
|
||||
#define MCF_RNGA_RNGSR_ORL(x) (((x)&0xFF)<<0x8)
|
||||
#define MCF_RNGA_RNGSR_ORS(x) (((x)&0xFF)<<0x10)
|
||||
|
||||
/* Bit definitions and macros for MCF_RNGA_RNGER */
|
||||
#define MCF_RNGA_RNGER_ENT(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_RNGA_RNGOUT */
|
||||
#define MCF_RNGA_RNGOUT_RANDOM_OUTPUT(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
|
||||
#endif /* __MCF52235_RNGA_H__ */
|
||||
|
|
@ -0,0 +1,75 @@
|
|||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2007/03/19 Revision: 0.91
|
||||
*/
|
||||
|
||||
#ifndef __MCF52235_RTC_H__
|
||||
#define __MCF52235_RTC_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Real-Time Clock (RTC)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_RTC_HOURMIN (*(vuint32*)(&__IPSBAR[0x3C0]))
|
||||
#define MCF_RTC_SECONDS (*(vuint32*)(&__IPSBAR[0x3C4]))
|
||||
#define MCF_RTC_ALRM_HM (*(vuint32*)(&__IPSBAR[0x3C8]))
|
||||
#define MCF_RTC_ALRM_SEC (*(vuint32*)(&__IPSBAR[0x3CC]))
|
||||
#define MCF_RTC_RTCCTL (*(vuint32*)(&__IPSBAR[0x3D0]))
|
||||
#define MCF_RTC_RTCISR (*(vuint32*)(&__IPSBAR[0x3D4]))
|
||||
#define MCF_RTC_RTCIENR (*(vuint32*)(&__IPSBAR[0x3D8]))
|
||||
#define MCF_RTC_STPWCH (*(vuint32*)(&__IPSBAR[0x3DC]))
|
||||
#define MCF_RTC_DAYS (*(vuint32*)(&__IPSBAR[0x3E0]))
|
||||
#define MCF_RTC_ALRM_DAY (*(vuint32*)(&__IPSBAR[0x3E4]))
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_RTC_HOURMIN */
|
||||
#define MCF_RTC_HOURMIN_MINUTES(x) (((x)&0x3F)<<0)
|
||||
#define MCF_RTC_HOURMIN_HOURS(x) (((x)&0x1F)<<0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_RTC_SECONDS */
|
||||
#define MCF_RTC_SECONDS_SECONDS(x) (((x)&0x3F)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_RTC_ALRM_HM */
|
||||
#define MCF_RTC_ALRM_HM_MINUTES(x) (((x)&0x3F)<<0)
|
||||
#define MCF_RTC_ALRM_HM_HOURS(x) (((x)&0x1F)<<0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_RTC_ALRM_SEC */
|
||||
#define MCF_RTC_ALRM_SEC_SECONDS(x) (((x)&0x3F)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_RTC_RTCCTL */
|
||||
#define MCF_RTC_RTCCTL_SWR (0x1)
|
||||
#define MCF_RTC_RTCCTL_EN (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_RTC_RTCISR */
|
||||
#define MCF_RTC_RTCISR_SW (0x1)
|
||||
#define MCF_RTC_RTCISR_MIN (0x2)
|
||||
#define MCF_RTC_RTCISR_ALM (0x4)
|
||||
#define MCF_RTC_RTCISR_DAY (0x8)
|
||||
#define MCF_RTC_RTCISR_1HZ (0x10)
|
||||
#define MCF_RTC_RTCISR_HR (0x20)
|
||||
|
||||
/* Bit definitions and macros for MCF_RTC_RTCIENR */
|
||||
#define MCF_RTC_RTCIENR_SW (0x1)
|
||||
#define MCF_RTC_RTCIENR_MIN (0x2)
|
||||
#define MCF_RTC_RTCIENR_ALM (0x4)
|
||||
#define MCF_RTC_RTCIENR_DAY (0x8)
|
||||
#define MCF_RTC_RTCIENR_1HZ (0x10)
|
||||
#define MCF_RTC_RTCIENR_HR (0x20)
|
||||
|
||||
/* Bit definitions and macros for MCF_RTC_STPWCH */
|
||||
#define MCF_RTC_STPWCH_CNT(x) (((x)&0x3F)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_RTC_DAYS */
|
||||
#define MCF_RTC_DAYS_DAYS(x) (((x)&0xFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_RTC_ALRM_DAY */
|
||||
#define MCF_RTC_ALRM_DAY_DAYSAL(x) (((x)&0xFFFF)<<0)
|
||||
|
||||
|
||||
#endif /* __MCF52235_RTC_H__ */
|
||||
201
Demo/ColdFire_MCF52233_Eclipse/RTOSDemo/MCF5223x/MCF52235_SCM.h
Normal file
201
Demo/ColdFire_MCF52233_Eclipse/RTOSDemo/MCF5223x/MCF52235_SCM.h
Normal file
|
|
@ -0,0 +1,201 @@
|
|||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2007/03/19 Revision: 0.91
|
||||
*/
|
||||
|
||||
#ifndef __MCF52235_SCM_H__
|
||||
#define __MCF52235_SCM_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* System Control Module (SCM)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_SCM_RAMBAR (*(vuint32*)(&__IPSBAR[0x8]))
|
||||
#define MCF_SCM_PPMRH (*(vuint32*)(&__IPSBAR[0xC]))
|
||||
#define MCF_SCM_CRSR (*(vuint8 *)(&__IPSBAR[0x10]))
|
||||
#define MCF_SCM_CWCR (*(vuint8 *)(&__IPSBAR[0x11]))
|
||||
#define MCF_SCM_CWSR (*(vuint8 *)(&__IPSBAR[0x13]))
|
||||
#define MCF_SCM_DMAREQC (*(vuint32*)(&__IPSBAR[0x14]))
|
||||
#define MCF_SCM_PPMRL (*(vuint32*)(&__IPSBAR[0x18]))
|
||||
#define MCF_SCM_MPARK (*(vuint32*)(&__IPSBAR[0x1C]))
|
||||
#define MCF_SCM_MPR (*(vuint8 *)(&__IPSBAR[0x20]))
|
||||
#define MCF_SCM_PPMRS (*(vuint8 *)(&__IPSBAR[0x21]))
|
||||
#define MCF_SCM_PPMRC (*(vuint8 *)(&__IPSBAR[0x22]))
|
||||
#define MCF_SCM_IPSBMT (*(vuint8 *)(&__IPSBAR[0x23]))
|
||||
#define MCF_SCM_PACR0 (*(vuint8 *)(&__IPSBAR[0x24]))
|
||||
#define MCF_SCM_PACR1 (*(vuint8 *)(&__IPSBAR[0x25]))
|
||||
#define MCF_SCM_PACR2 (*(vuint8 *)(&__IPSBAR[0x26]))
|
||||
#define MCF_SCM_PACR3 (*(vuint8 *)(&__IPSBAR[0x27]))
|
||||
#define MCF_SCM_PACR4 (*(vuint8 *)(&__IPSBAR[0x28]))
|
||||
#define MCF_SCM_PACR5 (*(vuint8 *)(&__IPSBAR[0x29]))
|
||||
#define MCF_SCM_PACR6 (*(vuint8 *)(&__IPSBAR[0x2A]))
|
||||
#define MCF_SCM_PACR7 (*(vuint8 *)(&__IPSBAR[0x2B]))
|
||||
#define MCF_SCM_PACR8 (*(vuint8 *)(&__IPSBAR[0x2C]))
|
||||
#define MCF_SCM_GPACR0 (*(vuint8 *)(&__IPSBAR[0x30]))
|
||||
#define MCF_SCM_GPACR1 (*(vuint8 *)(&__IPSBAR[0x31]))
|
||||
#define MCF_SCM_PACR(x) (*(vuint8 *)(&__IPSBAR[0x24 + ((x)*0x1)]))
|
||||
#define MCF_SCM_GPACR(x) (*(vuint8 *)(&__IPSBAR[0x30 + ((x)*0x1)]))
|
||||
|
||||
/* Other macros */
|
||||
#define MCF_SCM_IPSBAR (*(vuint32*)(&__IPSBAR[0x0]))
|
||||
#define MCF_SCM_IPSBAR_V (0x1)
|
||||
#define MCF_SCM_IPSBAR_BA(x) ((x)&0xC0000000)
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_SCM_RAMBAR */
|
||||
#define MCF_SCM_RAMBAR_BDE (0x200)
|
||||
#define MCF_SCM_RAMBAR_BA(x) ((x)&0xFFFF0000)
|
||||
|
||||
/* Bit definitions and macros for MCF_SCM_PPMRH */
|
||||
#define MCF_SCM_PPMRH_CDPORTS (0x1)
|
||||
#define MCF_SCM_PPMRH_CDEPORT (0x2)
|
||||
#define MCF_SCM_PPMRH_CDPIT0 (0x8)
|
||||
#define MCF_SCM_PPMRH_CDPIT1 (0x10)
|
||||
#define MCF_SCM_PPMRH_CDADC (0x80)
|
||||
#define MCF_SCM_PPMRH_CDGPT (0x100)
|
||||
#define MCF_SCM_PPMRH_CDPWM (0x200)
|
||||
#define MCF_SCM_PPMRH_CDFCAN (0x400)
|
||||
#define MCF_SCM_PPMRH_CDCFM (0x800)
|
||||
#define MCF_SCM_PPMRH_CDEPHY (0x1000)
|
||||
#define MCF_SCM_PPMRH_CDRNGA (0x2000)
|
||||
|
||||
/* Bit definitions and macros for MCF_SCM_CRSR */
|
||||
#define MCF_SCM_CRSR_CWDR (0x20)
|
||||
#define MCF_SCM_CRSR_EXT (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_SCM_CWCR */
|
||||
#define MCF_SCM_CWCR_CWTIF (0x1)
|
||||
#define MCF_SCM_CWCR_CWTAVAL (0x2)
|
||||
#define MCF_SCM_CWCR_CWTA (0x4)
|
||||
#define MCF_SCM_CWCR_CWT(x) (((x)&0x7)<<0x3)
|
||||
#define MCF_SCM_CWCR_CWT_2_9 (0)
|
||||
#define MCF_SCM_CWCR_CWT_2_11 (0x8)
|
||||
#define MCF_SCM_CWCR_CWT_2_13 (0x10)
|
||||
#define MCF_SCM_CWCR_CWT_2_15 (0x18)
|
||||
#define MCF_SCM_CWCR_CWT_2_19 (0x20)
|
||||
#define MCF_SCM_CWCR_CWT_2_23 (0x28)
|
||||
#define MCF_SCM_CWCR_CWT_2_27 (0x30)
|
||||
#define MCF_SCM_CWCR_CWT_2_31 (0x38)
|
||||
#define MCF_SCM_CWCR_CWRI (0x40)
|
||||
#define MCF_SCM_CWCR_CWE (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_SCM_CWSR */
|
||||
#define MCF_SCM_CWSR_CWSR(x) (((x)&0xFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_SCM_DMAREQC */
|
||||
#define MCF_SCM_DMAREQC_DMAC0(x) (((x)&0xF)<<0)
|
||||
#define MCF_SCM_DMAREQC_DMAC1(x) (((x)&0xF)<<0x4)
|
||||
#define MCF_SCM_DMAREQC_DMAC2(x) (((x)&0xF)<<0x8)
|
||||
#define MCF_SCM_DMAREQC_DMAC3(x) (((x)&0xF)<<0xC)
|
||||
|
||||
/* Bit definitions and macros for MCF_SCM_PPMRL */
|
||||
#define MCF_SCM_PPMRL_CDG (0x2)
|
||||
#define MCF_SCM_PPMRL_CDDMA (0x10)
|
||||
#define MCF_SCM_PPMRL_CDUART0 (0x20)
|
||||
#define MCF_SCM_PPMRL_CDUART1 (0x40)
|
||||
#define MCF_SCM_PPMRL_CDUART2 (0x80)
|
||||
#define MCF_SCM_PPMRL_CDI2C (0x200)
|
||||
#define MCF_SCM_PPMRL_CDQSPI (0x400)
|
||||
#define MCF_SCM_PPMRL_CDRTC (0x1000)
|
||||
#define MCF_SCM_PPMRL_CDTMR0 (0x2000)
|
||||
#define MCF_SCM_PPMRL_CDTMR1 (0x4000)
|
||||
#define MCF_SCM_PPMRL_CDTMR2 (0x8000)
|
||||
#define MCF_SCM_PPMRL_CDTMR3 (0x10000)
|
||||
#define MCF_SCM_PPMRL_CDINTC0 (0x20000)
|
||||
#define MCF_SCM_PPMRL_CDINTC1 (0x40000)
|
||||
#define MCF_SCM_PPMRL_CDFEC0 (0x200000)
|
||||
|
||||
/* Bit definitions and macros for MCF_SCM_MPARK */
|
||||
#define MCF_SCM_MPARK_LCKOUT_TIME(x) (((x)&0xF)<<0x8)
|
||||
#define MCF_SCM_MPARK_PRKLAST (0x1000)
|
||||
#define MCF_SCM_MPARK_TIMEOUT (0x2000)
|
||||
#define MCF_SCM_MPARK_FIXED (0x4000)
|
||||
#define MCF_SCM_MPARK_M1_PRTY(x) (((x)&0x3)<<0x10)
|
||||
#define MCF_SCM_MPARK_M0_PRTY(x) (((x)&0x3)<<0x12)
|
||||
#define MCF_SCM_MPARK_M2_PRTY(x) (((x)&0x3)<<0x14)
|
||||
#define MCF_SCM_MPARK_BCR24BIT (0x1000000)
|
||||
#define MCF_SCM_MPARK_M2_P_EN (0x2000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_SCM_MPR */
|
||||
#define MCF_SCM_MPR_MPR(x) (((x)&0xF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_SCM_PPMRS */
|
||||
#define MCF_SCM_PPMRS_PPMRS(x) (((x)&0x7F)<<0)
|
||||
#define MCF_SCM_PPMRS_DISABLE_ALL (0x40)
|
||||
#define MCF_SCM_PPMRS_DISABLE_CFM (0x2B)
|
||||
#define MCF_SCM_PPMRS_DISABLE_CAN (0x2A)
|
||||
#define MCF_SCM_PPMRS_DISABLE_PWM (0x29)
|
||||
#define MCF_SCM_PPMRS_DISABLE_GPT (0x28)
|
||||
#define MCF_SCM_PPMRS_DISABLE_ADC (0x27)
|
||||
#define MCF_SCM_PPMRS_DISABLE_PIT1 (0x24)
|
||||
#define MCF_SCM_PPMRS_DISABLE_PIT0 (0x23)
|
||||
#define MCF_SCM_PPMRS_DISABLE_EPORT (0x21)
|
||||
#define MCF_SCM_PPMRS_DISABLE_PORTS (0x20)
|
||||
#define MCF_SCM_PPMRS_DISABLE_INTC (0x11)
|
||||
#define MCF_SCM_PPMRS_DISABLE_DTIM3 (0x10)
|
||||
#define MCF_SCM_PPMRS_DISABLE_DTIM2 (0xF)
|
||||
#define MCF_SCM_PPMRS_DISABLE_DTIM1 (0xE)
|
||||
#define MCF_SCM_PPMRS_DISABLE_DTIM0 (0xD)
|
||||
#define MCF_SCM_PPMRS_DISABLE_QSPI (0xA)
|
||||
#define MCF_SCM_PPMRS_DISABLE_I2C (0x9)
|
||||
#define MCF_SCM_PPMRS_DISABLE_UART2 (0x7)
|
||||
#define MCF_SCM_PPMRS_DISABLE_UART1 (0x6)
|
||||
#define MCF_SCM_PPMRS_DISABLE_UART0 (0x5)
|
||||
#define MCF_SCM_PPMRS_DISABLE_DMA (0x4)
|
||||
#define MCF_SCM_PPMRS_SET_CDG (0x1)
|
||||
|
||||
/* Bit definitions and macros for MCF_SCM_PPMRC */
|
||||
#define MCF_SCM_PPMRC_PPMRC(x) (((x)&0x7F)<<0)
|
||||
#define MCF_SCM_PPMRC_ENABLE_ALL (0x40)
|
||||
#define MCF_SCM_PPMRC_ENABLE_CFM (0x2B)
|
||||
#define MCF_SCM_PPMRC_ENABLE_CAN (0x2A)
|
||||
#define MCF_SCM_PPMRC_ENABLE_PWM (0x29)
|
||||
#define MCF_SCM_PPMRC_ENABLE_GPT (0x28)
|
||||
#define MCF_SCM_PPMRC_ENABLE_ADC (0x27)
|
||||
#define MCF_SCM_PPMRC_ENABLE_PIT1 (0x24)
|
||||
#define MCF_SCM_PPMRC_ENABLE_PIT0 (0x23)
|
||||
#define MCF_SCM_PPMRC_ENABLE_EPORT (0x21)
|
||||
#define MCF_SCM_PPMRC_ENABLE_PORTS (0x20)
|
||||
#define MCF_SCM_PPMRC_ENABLE_INTC (0x11)
|
||||
#define MCF_SCM_PPMRC_ENABLE_DTIM3 (0x10)
|
||||
#define MCF_SCM_PPMRC_ENABLE_DTIM2 (0xF)
|
||||
#define MCF_SCM_PPMRC_ENABLE_DTIM1 (0xE)
|
||||
#define MCF_SCM_PPMRC_ENABLE_DTIM0 (0xD)
|
||||
#define MCF_SCM_PPMRC_ENABLE_QSPI (0xA)
|
||||
#define MCF_SCM_PPMRC_ENABLE_I2C (0x9)
|
||||
#define MCF_SCM_PPMRC_ENABLE_UART2 (0x7)
|
||||
#define MCF_SCM_PPMRC_ENABLE_UART1 (0x6)
|
||||
#define MCF_SCM_PPMRC_ENABLE_UART0 (0x5)
|
||||
#define MCF_SCM_PPMRC_ENABLE_DMA (0x4)
|
||||
#define MCF_SCM_PPMRC_CLEAR_CDG (0x1)
|
||||
|
||||
/* Bit definitions and macros for MCF_SCM_IPSBMT */
|
||||
#define MCF_SCM_IPSBMT_BMT(x) (((x)&0x7)<<0)
|
||||
#define MCF_SCM_IPSBMT_BMT_CYCLES_1024 (0)
|
||||
#define MCF_SCM_IPSBMT_BMT_CYCLES_512 (0x1)
|
||||
#define MCF_SCM_IPSBMT_BMT_CYCLES_256 (0x2)
|
||||
#define MCF_SCM_IPSBMT_BMT_CYCLES_128 (0x3)
|
||||
#define MCF_SCM_IPSBMT_BMT_CYCLES_64 (0x4)
|
||||
#define MCF_SCM_IPSBMT_BMT_CYCLES_32 (0x5)
|
||||
#define MCF_SCM_IPSBMT_BMT_CYCLES_16 (0x6)
|
||||
#define MCF_SCM_IPSBMT_BMT_CYCLES_8 (0x7)
|
||||
#define MCF_SCM_IPSBMT_BME (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_SCM_PACR */
|
||||
#define MCF_SCM_PACR_ACCESS_CTRL0(x) (((x)&0x7)<<0)
|
||||
#define MCF_SCM_PACR_LOCK0 (0x8)
|
||||
#define MCF_SCM_PACR_ACCESS_CTRL1(x) (((x)&0x7)<<0x4)
|
||||
#define MCF_SCM_PACR_LOCK1 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_SCM_GPACR */
|
||||
#define MCF_SCM_GPACR_ACCESS_CTRL(x) (((x)&0xF)<<0)
|
||||
#define MCF_SCM_GPACR_LOCK (0x80)
|
||||
|
||||
|
||||
#endif /* __MCF52235_SCM_H__ */
|
||||
194
Demo/ColdFire_MCF52233_Eclipse/RTOSDemo/MCF5223x/MCF52235_UART.h
Normal file
194
Demo/ColdFire_MCF52233_Eclipse/RTOSDemo/MCF5223x/MCF52235_UART.h
Normal file
|
|
@ -0,0 +1,194 @@
|
|||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2007/03/19 Revision: 0.91
|
||||
*/
|
||||
|
||||
#ifndef __MCF52235_UART_H__
|
||||
#define __MCF52235_UART_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Universal Asynchronous Receiver Transmitter (UART)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_UART0_UMR1 (*(vuint8 *)(&__IPSBAR[0x200]))
|
||||
#define MCF_UART0_UMR2 (*(vuint8 *)(&__IPSBAR[0x200]))
|
||||
#define MCF_UART0_USR (*(vuint8 *)(&__IPSBAR[0x204]))
|
||||
#define MCF_UART0_UCSR (*(vuint8 *)(&__IPSBAR[0x204]))
|
||||
#define MCF_UART0_UCR (*(vuint8 *)(&__IPSBAR[0x208]))
|
||||
#define MCF_UART0_URB (*(vuint8 *)(&__IPSBAR[0x20C]))
|
||||
#define MCF_UART0_UTB (*(vuint8 *)(&__IPSBAR[0x20C]))
|
||||
#define MCF_UART0_UIPCR (*(vuint8 *)(&__IPSBAR[0x210]))
|
||||
#define MCF_UART0_UACR (*(vuint8 *)(&__IPSBAR[0x210]))
|
||||
#define MCF_UART0_UIMR (*(vuint8 *)(&__IPSBAR[0x214]))
|
||||
#define MCF_UART0_UISR (*(vuint8 *)(&__IPSBAR[0x214]))
|
||||
#define MCF_UART0_UBG1 (*(vuint8 *)(&__IPSBAR[0x218]))
|
||||
#define MCF_UART0_UBG2 (*(vuint8 *)(&__IPSBAR[0x21C]))
|
||||
#define MCF_UART0_UIP (*(vuint8 *)(&__IPSBAR[0x234]))
|
||||
#define MCF_UART0_UOP1 (*(vuint8 *)(&__IPSBAR[0x238]))
|
||||
#define MCF_UART0_UOP0 (*(vuint8 *)(&__IPSBAR[0x23C]))
|
||||
|
||||
#define MCF_UART1_UMR1 (*(vuint8 *)(&__IPSBAR[0x240]))
|
||||
#define MCF_UART1_UMR2 (*(vuint8 *)(&__IPSBAR[0x240]))
|
||||
#define MCF_UART1_USR (*(vuint8 *)(&__IPSBAR[0x244]))
|
||||
#define MCF_UART1_UCSR (*(vuint8 *)(&__IPSBAR[0x244]))
|
||||
#define MCF_UART1_UCR (*(vuint8 *)(&__IPSBAR[0x248]))
|
||||
#define MCF_UART1_URB (*(vuint8 *)(&__IPSBAR[0x24C]))
|
||||
#define MCF_UART1_UTB (*(vuint8 *)(&__IPSBAR[0x24C]))
|
||||
#define MCF_UART1_UIPCR (*(vuint8 *)(&__IPSBAR[0x250]))
|
||||
#define MCF_UART1_UACR (*(vuint8 *)(&__IPSBAR[0x250]))
|
||||
#define MCF_UART1_UIMR (*(vuint8 *)(&__IPSBAR[0x254]))
|
||||
#define MCF_UART1_UISR (*(vuint8 *)(&__IPSBAR[0x254]))
|
||||
#define MCF_UART1_UBG1 (*(vuint8 *)(&__IPSBAR[0x258]))
|
||||
#define MCF_UART1_UBG2 (*(vuint8 *)(&__IPSBAR[0x25C]))
|
||||
#define MCF_UART1_UIP (*(vuint8 *)(&__IPSBAR[0x274]))
|
||||
#define MCF_UART1_UOP1 (*(vuint8 *)(&__IPSBAR[0x278]))
|
||||
#define MCF_UART1_UOP0 (*(vuint8 *)(&__IPSBAR[0x27C]))
|
||||
|
||||
#define MCF_UART2_UMR1 (*(vuint8 *)(&__IPSBAR[0x280]))
|
||||
#define MCF_UART2_UMR2 (*(vuint8 *)(&__IPSBAR[0x280]))
|
||||
#define MCF_UART2_USR (*(vuint8 *)(&__IPSBAR[0x284]))
|
||||
#define MCF_UART2_UCSR (*(vuint8 *)(&__IPSBAR[0x284]))
|
||||
#define MCF_UART2_UCR (*(vuint8 *)(&__IPSBAR[0x288]))
|
||||
#define MCF_UART2_URB (*(vuint8 *)(&__IPSBAR[0x28C]))
|
||||
#define MCF_UART2_UTB (*(vuint8 *)(&__IPSBAR[0x28C]))
|
||||
#define MCF_UART2_UIPCR (*(vuint8 *)(&__IPSBAR[0x290]))
|
||||
#define MCF_UART2_UACR (*(vuint8 *)(&__IPSBAR[0x290]))
|
||||
#define MCF_UART2_UIMR (*(vuint8 *)(&__IPSBAR[0x294]))
|
||||
#define MCF_UART2_UISR (*(vuint8 *)(&__IPSBAR[0x294]))
|
||||
#define MCF_UART2_UBG1 (*(vuint8 *)(&__IPSBAR[0x298]))
|
||||
#define MCF_UART2_UBG2 (*(vuint8 *)(&__IPSBAR[0x29C]))
|
||||
#define MCF_UART2_UIP (*(vuint8 *)(&__IPSBAR[0x2B4]))
|
||||
#define MCF_UART2_UOP1 (*(vuint8 *)(&__IPSBAR[0x2B8]))
|
||||
#define MCF_UART2_UOP0 (*(vuint8 *)(&__IPSBAR[0x2BC]))
|
||||
|
||||
#define MCF_UART_UMR(x) (*(vuint8 *)(&__IPSBAR[0x200 + ((x)*0x40)]))
|
||||
#define MCF_UART_USR(x) (*(vuint8 *)(&__IPSBAR[0x204 + ((x)*0x40)]))
|
||||
#define MCF_UART_UCSR(x) (*(vuint8 *)(&__IPSBAR[0x204 + ((x)*0x40)]))
|
||||
#define MCF_UART_UCR(x) (*(vuint8 *)(&__IPSBAR[0x208 + ((x)*0x40)]))
|
||||
#define MCF_UART_URB(x) (*(vuint8 *)(&__IPSBAR[0x20C + ((x)*0x40)]))
|
||||
#define MCF_UART_UTB(x) (*(vuint8 *)(&__IPSBAR[0x20C + ((x)*0x40)]))
|
||||
#define MCF_UART_UIPCR(x) (*(vuint8 *)(&__IPSBAR[0x210 + ((x)*0x40)]))
|
||||
#define MCF_UART_UACR(x) (*(vuint8 *)(&__IPSBAR[0x210 + ((x)*0x40)]))
|
||||
#define MCF_UART_UIMR(x) (*(vuint8 *)(&__IPSBAR[0x214 + ((x)*0x40)]))
|
||||
#define MCF_UART_UISR(x) (*(vuint8 *)(&__IPSBAR[0x214 + ((x)*0x40)]))
|
||||
#define MCF_UART_UBG1(x) (*(vuint8 *)(&__IPSBAR[0x218 + ((x)*0x40)]))
|
||||
#define MCF_UART_UBG2(x) (*(vuint8 *)(&__IPSBAR[0x21C + ((x)*0x40)]))
|
||||
#define MCF_UART_UIP(x) (*(vuint8 *)(&__IPSBAR[0x234 + ((x)*0x40)]))
|
||||
#define MCF_UART_UOP1(x) (*(vuint8 *)(&__IPSBAR[0x238 + ((x)*0x40)]))
|
||||
#define MCF_UART_UOP0(x) (*(vuint8 *)(&__IPSBAR[0x23C + ((x)*0x40)]))
|
||||
|
||||
/* Bit definitions and macros for MCF_UART_UMR */
|
||||
#define MCF_UART_UMR_BC(x) (((x)&0x3)<<0)
|
||||
#define MCF_UART_UMR_BC_5 (0)
|
||||
#define MCF_UART_UMR_BC_6 (0x1)
|
||||
#define MCF_UART_UMR_BC_7 (0x2)
|
||||
#define MCF_UART_UMR_BC_8 (0x3)
|
||||
#define MCF_UART_UMR_PT (0x4)
|
||||
#define MCF_UART_UMR_PM(x) (((x)&0x3)<<0x3)
|
||||
#define MCF_UART_UMR_ERR (0x20)
|
||||
#define MCF_UART_UMR_RXIRQ (0x40)
|
||||
#define MCF_UART_UMR_RXRTS (0x80)
|
||||
#define MCF_UART_UMR_PM_MULTI_ADDR (0x1C)
|
||||
#define MCF_UART_UMR_PM_MULTI_DATA (0x18)
|
||||
#define MCF_UART_UMR_PM_NONE (0x10)
|
||||
#define MCF_UART_UMR_PM_FORCE_HI (0xC)
|
||||
#define MCF_UART_UMR_PM_FORCE_LO (0x8)
|
||||
#define MCF_UART_UMR_PM_ODD (0x4)
|
||||
#define MCF_UART_UMR_PM_EVEN (0)
|
||||
#define MCF_UART_UMR_SB(x) (((x)&0xF)<<0)
|
||||
#define MCF_UART_UMR_SB_STOP_BITS_1 (0x7)
|
||||
#define MCF_UART_UMR_SB_STOP_BITS_15 (0x8)
|
||||
#define MCF_UART_UMR_SB_STOP_BITS_2 (0xF)
|
||||
#define MCF_UART_UMR_TXCTS (0x10)
|
||||
#define MCF_UART_UMR_TXRTS (0x20)
|
||||
#define MCF_UART_UMR_CM(x) (((x)&0x3)<<0x6)
|
||||
#define MCF_UART_UMR_CM_NORMAL (0)
|
||||
#define MCF_UART_UMR_CM_ECHO (0x40)
|
||||
#define MCF_UART_UMR_CM_LOCAL_LOOP (0x80)
|
||||
#define MCF_UART_UMR_CM_REMOTE_LOOP (0xC0)
|
||||
|
||||
/* Bit definitions and macros for MCF_UART_USR */
|
||||
#define MCF_UART_USR_RXRDY (0x1)
|
||||
#define MCF_UART_USR_FFULL (0x2)
|
||||
#define MCF_UART_USR_TXRDY (0x4)
|
||||
#define MCF_UART_USR_TXEMP (0x8)
|
||||
#define MCF_UART_USR_OE (0x10)
|
||||
#define MCF_UART_USR_PE (0x20)
|
||||
#define MCF_UART_USR_FE (0x40)
|
||||
#define MCF_UART_USR_RB (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_UART_UCSR */
|
||||
#define MCF_UART_UCSR_TCS(x) (((x)&0xF)<<0)
|
||||
#define MCF_UART_UCSR_TCS_SYS_CLK (0xD)
|
||||
#define MCF_UART_UCSR_TCS_CTM16 (0xE)
|
||||
#define MCF_UART_UCSR_TCS_CTM (0xF)
|
||||
#define MCF_UART_UCSR_RCS(x) (((x)&0xF)<<0x4)
|
||||
#define MCF_UART_UCSR_RCS_SYS_CLK (0xD0)
|
||||
#define MCF_UART_UCSR_RCS_CTM16 (0xE0)
|
||||
#define MCF_UART_UCSR_RCS_CTM (0xF0)
|
||||
|
||||
/* Bit definitions and macros for MCF_UART_UCR */
|
||||
#define MCF_UART_UCR_RC(x) (((x)&0x3)<<0)
|
||||
#define MCF_UART_UCR_RX_ENABLED (0x1)
|
||||
#define MCF_UART_UCR_RX_DISABLED (0x2)
|
||||
#define MCF_UART_UCR_TC(x) (((x)&0x3)<<0x2)
|
||||
#define MCF_UART_UCR_TX_ENABLED (0x4)
|
||||
#define MCF_UART_UCR_TX_DISABLED (0x8)
|
||||
#define MCF_UART_UCR_MISC(x) (((x)&0x7)<<0x4)
|
||||
#define MCF_UART_UCR_NONE (0)
|
||||
#define MCF_UART_UCR_RESET_MR (0x10)
|
||||
#define MCF_UART_UCR_RESET_RX (0x20)
|
||||
#define MCF_UART_UCR_RESET_TX (0x30)
|
||||
#define MCF_UART_UCR_RESET_ERROR (0x40)
|
||||
#define MCF_UART_UCR_RESET_BKCHGINT (0x50)
|
||||
#define MCF_UART_UCR_START_BREAK (0x60)
|
||||
#define MCF_UART_UCR_STOP_BREAK (0x70)
|
||||
|
||||
/* Bit definitions and macros for MCF_UART_URB */
|
||||
#define MCF_UART_URB_RB(x) (((x)&0xFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_UART_UTB */
|
||||
#define MCF_UART_UTB_TB(x) (((x)&0xFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_UART_UIPCR */
|
||||
#define MCF_UART_UIPCR_CTS (0x1)
|
||||
#define MCF_UART_UIPCR_COS (0x10)
|
||||
|
||||
/* Bit definitions and macros for MCF_UART_UACR */
|
||||
#define MCF_UART_UACR_IEC (0x1)
|
||||
|
||||
/* Bit definitions and macros for MCF_UART_UIMR */
|
||||
#define MCF_UART_UIMR_TXRDY (0x1)
|
||||
#define MCF_UART_UIMR_FFULL_RXRDY (0x2)
|
||||
#define MCF_UART_UIMR_DB (0x4)
|
||||
#define MCF_UART_UIMR_COS (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_UART_UISR */
|
||||
#define MCF_UART_UISR_TXRDY (0x1)
|
||||
#define MCF_UART_UISR_FFULL_RXRDY (0x2)
|
||||
#define MCF_UART_UISR_DB (0x4)
|
||||
#define MCF_UART_UISR_COS (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_UART_UBG1 */
|
||||
#define MCF_UART_UBG1_Divider_MSB(x) (((x)&0xFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_UART_UBG2 */
|
||||
#define MCF_UART_UBG2_Divider_LSB(x) (((x)&0xFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_UART_UIP */
|
||||
#define MCF_UART_UIP_CTS (0x1)
|
||||
|
||||
/* Bit definitions and macros for MCF_UART_UOP1 */
|
||||
#define MCF_UART_UOP1_RTS (0x1)
|
||||
|
||||
/* Bit definitions and macros for MCF_UART_UOP0 */
|
||||
#define MCF_UART_UOP0_RTS (0x1)
|
||||
|
||||
|
||||
#endif /* __MCF52235_UART_H__ */
|
||||
Loading…
Add table
Add a link
Reference in a new issue