Add MPU demo project for LPC54018 board.

FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/Config/FreeRTOSConfig.h

@@ -0,0 +1,161 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+#define configUSE_PREEMPTION						1
+#define configUSE_TICKLESS_IDLE						0
+#define configCPU_CLOCK_HZ							( SystemCoreClock )
+#define configTICK_RATE_HZ							( ( TickType_t ) 200 )
+#define configMAX_PRIORITIES						5
+#define configMINIMAL_STACK_SIZE					( ( unsigned short ) 256 )
+#define configMAX_TASK_NAME_LEN						20
+#define configUSE_16_BIT_TICKS						0
+#define configIDLE_SHOULD_YIELD						1
+#define configUSE_TASK_NOTIFICATIONS				1
+#define configUSE_MUTEXES							1
+#define configUSE_RECURSIVE_MUTEXES					1
+#define configUSE_COUNTING_SEMAPHORES				1
+#define configUSE_ALTERNATIVE_API					0 /* Deprecated! */
+#define configQUEUE_REGISTRY_SIZE					8
+#define configUSE_QUEUE_SETS						0
+#define configUSE_TIME_SLICING						0
+#define configUSE_NEWLIB_REENTRANT					0
+#define configENABLE_BACKWARD_COMPATIBILITY			0
+#define configNUM_THREAD_LOCAL_STORAGE_POINTERS		5
+
+/* Used memory allocation (heap_x.c). */
+#define configFRTOS_MEMORY_SCHEME					4
+
+/* Tasks.c additions (e.g. Thread Aware Debug capability). */
+#define configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H	1
+
+/* Memory allocation related definitions. */
+#define configSUPPORT_STATIC_ALLOCATION				0
+#define configSUPPORT_DYNAMIC_ALLOCATION			1
+#define configTOTAL_HEAP_SIZE						( ( size_t )( 10 * 1024 ) )
+#define configAPPLICATION_ALLOCATED_HEAP			0
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK							0
+#define configUSE_TICK_HOOK							0
+#define configCHECK_FOR_STACK_OVERFLOW				0
+#define configUSE_MALLOC_FAILED_HOOK				0
+#define configUSE_DAEMON_TASK_STARTUP_HOOK			0
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS				0
+#define configUSE_TRACE_FACILITY					1
+#define configUSE_STATS_FORMATTING_FUNCTIONS		0
+
+/* Task aware debugging. */
+#define configRECORD_STACK_HIGH_ADDRESS				1
+
+/* Co-routine related definitions. */
+#define configUSE_CO_ROUTINES						0
+#define configMAX_CO_ROUTINE_PRIORITIES				2
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS						1
+#define configTIMER_TASK_PRIORITY				( configMAX_PRIORITIES - 1 )
+#define configTIMER_QUEUE_LENGTH				10
+#define configTIMER_TASK_STACK_DEPTH			( configMINIMAL_STACK_SIZE * 2 )
+
+/* Define to trap errors during development. */
+#define configASSERT(x)							if(( x) == 0) {taskDISABLE_INTERRUPTS(); for (;;);}
+
+/* Optional functions - most linkers will remove unused functions anyway. */
+#define INCLUDE_vTaskPrioritySet				1
+#define INCLUDE_uxTaskPriorityGet				1
+#define INCLUDE_vTaskDelete						1
+#define INCLUDE_vTaskSuspend					1
+#define INCLUDE_vTaskDelayUntil					1
+#define INCLUDE_vTaskDelay						1
+#define INCLUDE_xTaskGetSchedulerState			1
+#define INCLUDE_xTaskGetCurrentTaskHandle		1
+#define INCLUDE_uxTaskGetStackHighWaterMark		0
+#define INCLUDE_xTaskGetIdleTaskHandle			0
+#define INCLUDE_eTaskGetState					0
+#define INCLUDE_xTimerPendFunctionCall			1
+#define INCLUDE_xTaskAbortDelay					0
+#define INCLUDE_xTaskGetHandle					0
+#define INCLUDE_xTaskResumeFromISR				1
+
+#if defined(__ICCARM__)||defined(__CC_ARM)||defined(__GNUC__)
+	/* Clock manager provides in this variable system core clock frequency. */
+	#include <stdint.h>
+	extern uint32_t SystemCoreClock;
+#endif
+
+/* Interrupt nesting behaviour configuration. Cortex-M specific. */
+#ifdef __NVIC_PRIO_BITS
+/* __BVIC_PRIO_BITS will be specified when CMSIS is being used. */
+#define configPRIO_BITS __NVIC_PRIO_BITS
+#else
+#define configPRIO_BITS 3 /* 8 priority levels */
+#endif
+
+/* The lowest interrupt priority that can be used in a call to a "set priority"
+function. */
+#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY ((1U << (configPRIO_BITS)) - 1)
+
+/* The highest interrupt priority that can be used by any interrupt service
+routine that makes calls to interrupt safe FreeRTOS API functions.  DO NOT CALL
+INTERRUPT SAFE FREERTOS API FUNCTIONS FROM ANY INTERRUPT THAT HAS A HIGHER
+PRIORITY THAN THIS! (higher priorities are lower numeric values. */
+#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 2
+
+/* Interrupt priorities used by the kernel port layer itself.  These are generic
+to all Cortex-M ports, and do not rely on any particular library functions. */
+#define configKERNEL_INTERRUPT_PRIORITY (configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS))
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS))
+
+/* Definitions that map the FreeRTOS port interrupt handlers to their CMSIS
+standard names. */
+#define vPortSVCHandler			SVC_Handler
+#define xPortPendSVHandler		PendSV_Handler
+#define xPortSysTickHandler		SysTick_Handler
+
+/* Ensure that system calls can only be made from kernel code. */
+#define configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY		1
+
+#endif /* FREERTOS_CONFIG_H */

FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/Demo/main.c

@@ -0,0 +1,138 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* BSP includes. */
+#include "board.h"
+#include "pin_mux.h"
+
+/* Demo includes. */
+#include "mpu_demo.h"
+
+/**
+ * @brief Performs board specific initialization.
+ */
+static void prvInitHardware( void );
+/*-----------------------------------------------------------*/
+
+static void prvInitHardware( void )
+{
+	/* Attach 12 MHz clock to FLEXCOMM0 (debug console). */
+	CLOCK_AttachClk(BOARD_DEBUG_UART_CLK_ATTACH);
+
+	BOARD_InitPins();
+	BOARD_BootClockPLL180M();
+	BOARD_InitDebugConsole();
+}
+/*-----------------------------------------------------------*/
+
+int main( void )
+{
+	/* Initialize hardware. */
+	prvInitHardware();
+
+	/* Start the MPU demo. */
+	vStartMPUDemo();
+
+	/* Start the scheduler. */
+	vTaskStartScheduler();
+
+	/* Should not get here. */
+	for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName )
+{
+	/* If configCHECK_FOR_STACK_OVERFLOW is set to either 1 or 2 then this
+	function will automatically get called if a task overflows its stack. */
+	( void ) pxTask;
+	( void ) pcTaskName;
+	for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+void vApplicationMallocFailedHook( void )
+{
+	/* If configUSE_MALLOC_FAILED_HOOK is set to 1 then this function will
+	be called automatically if a call to pvPortMalloc() fails.  pvPortMalloc()
+	is called automatically when a task, queue or semaphore is created. */
+	for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+/* configUSE_STATIC_ALLOCATION is set to 1, so the application must provide an
+implementation of vApplicationGetIdleTaskMemory() to provide the memory that is
+used by the Idle task. */
+void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize )
+{
+/* If the buffers to be provided to the Idle task are declared inside this
+function then they must be declared static - otherwise they will be allocated on
+the stack and so not exists after this function exits. */
+static StaticTask_t xIdleTaskTCB;
+static StackType_t uxIdleTaskStack[ configMINIMAL_STACK_SIZE ];
+
+	/* Pass out a pointer to the StaticTask_t structure in which the Idle task's
+	state will be stored. */
+	*ppxIdleTaskTCBBuffer = &xIdleTaskTCB;
+
+	/* Pass out the array that will be used as the Idle task's stack. */
+	*ppxIdleTaskStackBuffer = uxIdleTaskStack;
+
+	/* Pass out the size of the array pointed to by *ppxIdleTaskStackBuffer.
+	Note that, as the array is necessarily of type StackType_t,
+	configMINIMAL_STACK_SIZE is specified in words, not bytes. */
+	*pulIdleTaskStackSize = configMINIMAL_STACK_SIZE;
+}
+/*-----------------------------------------------------------*/
+
+/* configUSE_STATIC_ALLOCATION and configUSE_TIMERS are both set to 1, so the
+application must provide an implementation of vApplicationGetTimerTaskMemory()
+to provide the memory that is used by the Timer service task. */
+void vApplicationGetTimerTaskMemory( StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize )
+{
+/* If the buffers to be provided to the Timer task are declared inside this
+function then they must be declared static - otherwise they will be allocated on
+the stack and so not exists after this function exits. */
+static StaticTask_t xTimerTaskTCB;
+static StackType_t uxTimerTaskStack[ configTIMER_TASK_STACK_DEPTH ];
+
+	/* Pass out a pointer to the StaticTask_t structure in which the Timer
+	task's state will be stored. */
+	*ppxTimerTaskTCBBuffer = &xTimerTaskTCB;
+
+	/* Pass out the array that will be used as the Timer task's stack. */
+	*ppxTimerTaskStackBuffer = uxTimerTaskStack;
+
+	/* Pass out the size of the array pointed to by *ppxTimerTaskStackBuffer.
+	Note that, as the array is necessarily of type StackType_t,
+	configMINIMAL_STACK_SIZE is specified in words, not bytes. */
+	*pulTimerTaskStackSize = configTIMER_TASK_STACK_DEPTH;
+}
+/*-----------------------------------------------------------*/

FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/Demo/mpu_demo.c

@@ -0,0 +1,301 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* FreeRTOS includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/** ARMv7 MPU Details:
+ *
+ * - ARMv7 MPU requires that the size of a MPU region is a power of 2.
+ * - Smallest supported region size is 32 bytes.
+ * - Start address of a region must be aligned to an integer multiple of the
+ *   region size. For example, if the region size is 4 KB(0x1000), the starting
+ *   address must be N x 0x1000, where N is an integer.
+ */
+
+/**
+ * @brief Size of the shared memory region.
+ */
+#define SHARED_MEMORY_SIZE 32
+
+/**
+ * @brief Memory region shared between two tasks.
+ */
+static uint8_t ucSharedMemory[ SHARED_MEMORY_SIZE ] __attribute__( ( aligned( SHARED_MEMORY_SIZE ) ) );
+
+/**
+ * @brief Memory region used to track Memory Fault intentionally caused by the
+ * RO Access task.
+ *
+ * RO Access task sets ucROTaskFaultTracker[ 0 ] to 1 before accessing illegal
+ * memory. Illegal memory access causes Memory Fault and the fault handler
+ * checks ucROTaskFaultTracker[ 0 ] to see if this is an expected fault. We
+ * recover gracefully from an expected fault by jumping to the next instruction.
+ *
+ * @note We are declaring a region of 32 bytes even though we need only one.
+ * The reason is that the smallest supported MPU region size is 32 bytes.
+ */
+static volatile uint8_t ucROTaskFaultTracker[ SHARED_MEMORY_SIZE ] __attribute__( ( aligned( SHARED_MEMORY_SIZE ) ) ) = { 0 };
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Implements the task which has Read Only access to the memory region
+ * ucSharedMemory.
+ *
+ * @param pvParameters[in] Parameters as passed during task creation.
+ */
+static void prvROAccessTask( void * pvParameters );
+
+/**
+ * @brief Implements the task which has Read Write access to the memory region
+ * ucSharedMemory.
+ *
+ * @param pvParameters[in] Parameters as passed during task creation.
+ */
+static void prvRWAccessTask( void * pvParameters );
+
+/*-----------------------------------------------------------*/
+
+static void prvROAccessTask( void * pvParameters )
+{
+uint8_t ucVal;
+
+	/* Unused parameters. */
+	( void ) pvParameters;
+
+	for( ; ; )
+	{
+		/* This task has RO access to ucSharedMemory and therefore it can read
+		 * it but cannot modify it. */
+		ucVal = ucSharedMemory[ 0 ];
+
+		/* Silent compiler warnings about unused variables. */
+		( void ) ucVal;
+
+		/* Since this task has Read Only access to the ucSharedMemory region,
+		 * writing to it results in Memory Fault. Set ucROTaskFaultTracker[ 0 ]
+		 * to 1 to tell the Memory Fault Handler that this is an expected fault.
+		 * The handler will recover from this fault gracefully by jumping to the
+		 * next instruction. */
+		ucROTaskFaultTracker[ 0 ] = 1;
+
+		/* Illegal access to generate Memory Fault. */
+		ucSharedMemory[ 0 ] = 0;
+
+		/* Ensure that the above line did generate MemFault and the fault
+		 * handler did clear the  ucROTaskFaultTracker[ 0 ]. */
+		configASSERT( ucROTaskFaultTracker[ 0 ] == 0 );
+
+		#if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 )
+		{
+			/* Generate an SVC to raise the privilege. Since privilege
+			 * escalation is only allowed from kernel code, this request must
+			 * get rejected and the task must remain unprivileged. As a result,
+			 * trying to write to ucSharedMemory will still result in Memory
+			 * Fault. */
+			portRAISE_PRIVILEGE();
+
+			/* Set ucROTaskFaultTracker[ 0 ] to 1 to tell the Memory Fault
+			 * Handler that this is an expected fault. The handler will then be
+			 * able to recover from this fault gracefully by jumping to the
+			 * next instruction.*/
+			ucROTaskFaultTracker[ 0 ] = 1;
+
+			/* The following must still result in Memory Fault since the task
+			 * is still running unprivileged. */
+			ucSharedMemory[ 0 ] = 0;
+
+			/* Ensure that the above line did generate MemFault and the fault
+		 	 * handler did clear the  ucROTaskFaultTracker[ 0 ]. */
+			configASSERT( ucROTaskFaultTracker[ 0 ] == 0 );
+		}
+		#else
+		{
+			/* Generate an SVC to raise the privilege. Since
+			 * configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY is not enabled, the
+			 * task will be able to escalate privilege. */
+			portRAISE_PRIVILEGE();
+
+			/* At this point, the task is running privileged. The following
+			 * access must not result in Memory Fault. If something goes
+			 * wrong and we do get a fault, the execution will stop in fault
+			 * handler as ucROTaskFaultTracker[ 0 ] is not set (i.e.
+			 * un-expected fault). */
+			ucSharedMemory[ 0 ] = 0;
+
+			/* Lower down the privilege. */
+			portSWITCH_TO_USER_MODE();
+
+			/* Now the task is running unprivileged and therefore an attempt to
+			 * write to ucSharedMemory will result in a Memory Fault. Set
+			 * ucROTaskFaultTracker[ 0 ] to 1 to tell the Memory Fault Handler
+			 * that this is an expected fault. The handler will then be able to
+			 * recover from this fault gracefully by jumping to the next
+			 * instruction.*/
+			ucROTaskFaultTracker[ 0 ] = 1;
+
+			/* The following must result in Memory Fault since the task is now
+			 * running unprivileged. */
+			ucSharedMemory[ 0 ] = 0;
+
+			/* Ensure that the above line did generate MemFault and the fault
+			 * handler did clear the  ucROTaskFaultTracker[ 0 ]. */
+			configASSERT( ucROTaskFaultTracker[ 0 ] == 0 );
+		}
+		#endif /* #if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */
+
+		/* Wait for a second. */
+		vTaskDelay( pdMS_TO_TICKS( 1000 ) );
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvRWAccessTask( void * pvParameters )
+{
+	/* Unused parameters. */
+	( void ) pvParameters;
+
+	for( ; ; )
+	{
+		/* This task has RW access to ucSharedMemory and therefore can write to
+		 * it. */
+		ucSharedMemory[ 0 ] = 0;
+
+		/* Wait for a second. */
+		vTaskDelay( pdMS_TO_TICKS( 1000 ) );
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vStartMPUDemo( void )
+{
+/**
+ * Since stack of a task is protected using MPU, it must satisfy MPU
+ * requirements as mentioned at the top of this file.
+ */
+static StackType_t xROAccessTaskStack[ configMINIMAL_STACK_SIZE ] __attribute__( ( aligned( configMINIMAL_STACK_SIZE * sizeof( StackType_t ) ) ) );
+static StackType_t xRWAccessTaskStack[ configMINIMAL_STACK_SIZE ] __attribute__( ( aligned( configMINIMAL_STACK_SIZE * sizeof( StackType_t ) ) ) );
+TaskParameters_t xROAccessTaskParameters =
+{
+	.pvTaskCode		= prvROAccessTask,
+	.pcName			= "ROAccess",
+	.usStackDepth	= configMINIMAL_STACK_SIZE,
+	.pvParameters	= NULL,
+	.uxPriority		= tskIDLE_PRIORITY,
+	.puxStackBuffer	= xROAccessTaskStack,
+	.xRegions		=	{
+							{ ucSharedMemory,					SHARED_MEMORY_SIZE,	portMPU_REGION_PRIVILEGED_READ_WRITE_UNPRIV_READ_ONLY | portMPU_REGION_EXECUTE_NEVER	},
+							{ ( void * ) ucROTaskFaultTracker,	SHARED_MEMORY_SIZE,	portMPU_REGION_READ_WRITE | portMPU_REGION_EXECUTE_NEVER								},
+							{ 0,								0,					0																						},
+						}
+};
+TaskParameters_t xRWAccessTaskParameters =
+{
+	.pvTaskCode		= prvRWAccessTask,
+	.pcName			= "RWAccess",
+	.usStackDepth	= configMINIMAL_STACK_SIZE,
+	.pvParameters	= NULL,
+	.uxPriority		= tskIDLE_PRIORITY,
+	.puxStackBuffer	= xRWAccessTaskStack,
+	.xRegions		=	{
+							{ ucSharedMemory,	SHARED_MEMORY_SIZE,	portMPU_REGION_READ_WRITE | portMPU_REGION_EXECUTE_NEVER},
+							{ 0,				0,					0														},
+							{ 0,				0,					0														},
+						}
+};
+
+	/* Create an unprivileged task with RO access to ucSharedMemory. */
+	xTaskCreateRestricted( &( xROAccessTaskParameters ), NULL );
+
+	/* Create an unprivileged task with RW access to ucSharedMemory. */
+	xTaskCreateRestricted( &( xRWAccessTaskParameters ), NULL );
+}
+/*-----------------------------------------------------------*/
+
+portDONT_DISCARD void vHandleMemoryFault( uint32_t * pulFaultStackAddress )
+{
+uint32_t ulPC;
+uint16_t usOffendingInstruction;
+
+	/* Is this an expected fault? */
+	if( ucROTaskFaultTracker[ 0 ] == 1 )
+	{
+		/* Read program counter. */
+		ulPC = pulFaultStackAddress[ 6 ];
+
+		/* Read the offending instruction. */
+		usOffendingInstruction = *( uint16_t * )ulPC;
+
+		/* From ARM docs:
+		 * If the value of bits[15:11] of the halfword being decoded is one of
+		 * the following, the halfword is the first halfword of a 32-bit
+		 * instruction:
+		 * - 0b11101.
+		 * - 0b11110.
+		 * - 0b11111.
+		 * Otherwise, the halfword is a 16-bit instruction.
+		 */
+
+		/* Extract bits[15:11] of the offending instruction. */
+		usOffendingInstruction = usOffendingInstruction & 0xF800;
+		usOffendingInstruction = ( usOffendingInstruction >> 11 );
+
+		/* Determine if the offending instruction is a 32-bit instruction or
+		 * a 16-bit instruction. */
+		if( usOffendingInstruction == 0x001F ||
+			usOffendingInstruction == 0x001E ||
+			usOffendingInstruction == 0x001D )
+		{
+			/* Since the offending instruction is a 32-bit instruction,
+			 * increment the program counter by 4 to move to the next
+			 * instruction. */
+			ulPC += 4;
+		}
+		else
+		{
+			/* Since the offending instruction is a 16-bit instruction,
+			 * increment the program counter by 2 to move to the next
+			 * instruction. */
+			ulPC += 2;
+		}
+
+		/* Save the new program counter on the stack. */
+		pulFaultStackAddress[ 6 ] = ulPC;
+
+		/* Mark the fault as handled. */
+		ucROTaskFaultTracker[ 0 ] = 0;
+	}
+	else
+	{
+		/* This is an unexpected fault - loop forever. */
+		for( ; ; )
+		{
+		}
+	}
+}
+/*-----------------------------------------------------------*/

FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/Demo/mpu_demo.h

@@ -0,0 +1,45 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __MPU_DEMO_H__
+#define __MPU_DEMO_H__
+
+/**
+ * @brief Creates all the tasks for MPU demo.
+ *
+ * The MPU demo creates 2 unprivileged tasks - One of which has Read Only access
+ * to a shared memory region while the other has Read Write access. The task
+ * with Read Only access then tries to write to the shared memory which results
+ * in a Memory fault. The fault handler examines that it is the fault generated
+ * by the task with Read Only access and if so, it recovers from the fault
+ * greacefully by moving the Program Counter to the next instruction to the one
+ * which generated the fault. If any other memory access violation occurs, the
+ * fault handler will get stuck in an inifinite loop.
+ */
+void vStartMPUDemo( void );
+
+#endif /* __MPU_DEMO_H__ */

FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/CMSIS/arm_common_tables.h

@@ -0,0 +1,121 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_common_tables.h
+ * Description:  Extern declaration for common tables
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef _ARM_COMMON_TABLES_H
+#define _ARM_COMMON_TABLES_H
+
+#include "arm_math.h"
+
+extern const uint16_t armBitRevTable[1024];
+extern const q15_t armRecipTableQ15[64];
+extern const q31_t armRecipTableQ31[64];
+extern const float32_t twiddleCoef_16[32];
+extern const float32_t twiddleCoef_32[64];
+extern const float32_t twiddleCoef_64[128];
+extern const float32_t twiddleCoef_128[256];
+extern const float32_t twiddleCoef_256[512];
+extern const float32_t twiddleCoef_512[1024];
+extern const float32_t twiddleCoef_1024[2048];
+extern const float32_t twiddleCoef_2048[4096];
+extern const float32_t twiddleCoef_4096[8192];
+#define twiddleCoef twiddleCoef_4096
+extern const q31_t twiddleCoef_16_q31[24];
+extern const q31_t twiddleCoef_32_q31[48];
+extern const q31_t twiddleCoef_64_q31[96];
+extern const q31_t twiddleCoef_128_q31[192];
+extern const q31_t twiddleCoef_256_q31[384];
+extern const q31_t twiddleCoef_512_q31[768];
+extern const q31_t twiddleCoef_1024_q31[1536];
+extern const q31_t twiddleCoef_2048_q31[3072];
+extern const q31_t twiddleCoef_4096_q31[6144];
+extern const q15_t twiddleCoef_16_q15[24];
+extern const q15_t twiddleCoef_32_q15[48];
+extern const q15_t twiddleCoef_64_q15[96];
+extern const q15_t twiddleCoef_128_q15[192];
+extern const q15_t twiddleCoef_256_q15[384];
+extern const q15_t twiddleCoef_512_q15[768];
+extern const q15_t twiddleCoef_1024_q15[1536];
+extern const q15_t twiddleCoef_2048_q15[3072];
+extern const q15_t twiddleCoef_4096_q15[6144];
+extern const float32_t twiddleCoef_rfft_32[32];
+extern const float32_t twiddleCoef_rfft_64[64];
+extern const float32_t twiddleCoef_rfft_128[128];
+extern const float32_t twiddleCoef_rfft_256[256];
+extern const float32_t twiddleCoef_rfft_512[512];
+extern const float32_t twiddleCoef_rfft_1024[1024];
+extern const float32_t twiddleCoef_rfft_2048[2048];
+extern const float32_t twiddleCoef_rfft_4096[4096];
+
+/* floating-point bit reversal tables */
+#define ARMBITREVINDEXTABLE_16_TABLE_LENGTH ((uint16_t)20)
+#define ARMBITREVINDEXTABLE_32_TABLE_LENGTH ((uint16_t)48)
+#define ARMBITREVINDEXTABLE_64_TABLE_LENGTH ((uint16_t)56)
+#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208)
+#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440)
+#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448)
+#define ARMBITREVINDEXTABLE_1024_TABLE_LENGTH ((uint16_t)1800)
+#define ARMBITREVINDEXTABLE_2048_TABLE_LENGTH ((uint16_t)3808)
+#define ARMBITREVINDEXTABLE_4096_TABLE_LENGTH ((uint16_t)4032)
+
+extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE_16_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE_32_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE_64_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE_1024_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE_2048_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE_4096_TABLE_LENGTH];
+
+/* fixed-point bit reversal tables */
+#define ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH ((uint16_t)12)
+#define ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH ((uint16_t)24)
+#define ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH ((uint16_t)56)
+#define ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH ((uint16_t)112)
+#define ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH ((uint16_t)240)
+#define ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH ((uint16_t)480)
+#define ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH ((uint16_t)992)
+#define ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH ((uint16_t)1984)
+#define ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH ((uint16_t)4032)
+
+extern const uint16_t armBitRevIndexTable_fixed_16[ARMBITREVINDEXTABLE_FIXED_16_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_32[ARMBITREVINDEXTABLE_FIXED_32_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_64[ARMBITREVINDEXTABLE_FIXED_64_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_128[ARMBITREVINDEXTABLE_FIXED_128_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_256[ARMBITREVINDEXTABLE_FIXED_256_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_512[ARMBITREVINDEXTABLE_FIXED_512_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_1024[ARMBITREVINDEXTABLE_FIXED_1024_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_2048[ARMBITREVINDEXTABLE_FIXED_2048_TABLE_LENGTH];
+extern const uint16_t armBitRevIndexTable_fixed_4096[ARMBITREVINDEXTABLE_FIXED_4096_TABLE_LENGTH];
+
+/* Tables for Fast Math Sine and Cosine */
+extern const float32_t sinTable_f32[FAST_MATH_TABLE_SIZE + 1];
+extern const q31_t sinTable_q31[FAST_MATH_TABLE_SIZE + 1];
+extern const q15_t sinTable_q15[FAST_MATH_TABLE_SIZE + 1];
+
+#endif /*  ARM_COMMON_TABLES_H */

FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/CMSIS/arm_const_structs.h

@@ -0,0 +1,66 @@
+/* ----------------------------------------------------------------------
+ * Project:      CMSIS DSP Library
+ * Title:        arm_const_structs.h
+ * Description:  Constant structs that are initialized for user convenience.
+ *               For example, some can be given as arguments to the arm_cfft_f32() function.
+ *
+ * $Date:        27. January 2017
+ * $Revision:    V.1.5.1
+ *
+ * Target Processor: Cortex-M cores
+ * -------------------------------------------------------------------- */
+/*
+ * Copyright (C) 2010-2017 ARM Limited or its affiliates. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef _ARM_CONST_STRUCTS_H
+#define _ARM_CONST_STRUCTS_H
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len16;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len32;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len64;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len128;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len256;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len512;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048;
+   extern const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096;
+
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len16;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len32;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len64;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len128;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len256;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len512;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len1024;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len2048;
+   extern const arm_cfft_instance_q31 arm_cfft_sR_q31_len4096;
+
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len16;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len32;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len64;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len128;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len256;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len512;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len1024;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len2048;
+   extern const arm_cfft_instance_q15 arm_cfft_sR_q15_len4096;
+
+#endif

FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/CMSIS/cmsis_armcc.h

@@ -0,0 +1,869 @@
+/**************************************************************************//**
+ * @file     cmsis_armcc.h
+ * @brief    CMSIS compiler ARMCC (Arm Compiler 5) header file
+ * @version  V5.0.5
+ * @date     14. December 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_ARMCC_H
+#define __CMSIS_ARMCC_H
+
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
+  #error "Please use Arm Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* CMSIS compiler control architecture macros */
+#if ((defined (__TARGET_ARCH_6_M  ) && (__TARGET_ARCH_6_M   == 1)) || \
+     (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M  == 1))   )
+  #define __ARM_ARCH_6M__           1
+#endif
+
+#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M  == 1))
+  #define __ARM_ARCH_7M__           1
+#endif
+
+#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1))
+  #define __ARM_ARCH_7EM__          1
+#endif
+
+  /* __ARM_ARCH_8M_BASE__  not applicable */
+  /* __ARM_ARCH_8M_MAIN__  not applicable */
+
+/* CMSIS compiler control DSP macros */
+#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+  #define __ARM_FEATURE_DSP         1
+#endif
+
+/* CMSIS compiler specific defines */
+#ifndef   __ASM
+  #define __ASM                                  __asm
+#endif
+#ifndef   __INLINE
+  #define __INLINE                               __inline
+#endif
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE                        static __inline
+#endif
+#ifndef   __STATIC_FORCEINLINE                 
+  #define __STATIC_FORCEINLINE                   static __forceinline
+#endif           
+#ifndef   __NO_RETURN
+  #define __NO_RETURN                            __declspec(noreturn)
+#endif
+#ifndef   __USED
+  #define __USED                                 __attribute__((used))
+#endif
+#ifndef   __WEAK
+  #define __WEAK                                 __attribute__((weak))
+#endif
+#ifndef   __PACKED
+  #define __PACKED                               __attribute__((packed))
+#endif
+#ifndef   __PACKED_STRUCT
+  #define __PACKED_STRUCT                        __packed struct
+#endif
+#ifndef   __PACKED_UNION
+  #define __PACKED_UNION                         __packed union
+#endif
+#ifndef   __UNALIGNED_UINT32        /* deprecated */
+  #define __UNALIGNED_UINT32(x)                  (*((__packed uint32_t *)(x)))
+#endif
+#ifndef   __UNALIGNED_UINT16_WRITE
+  #define __UNALIGNED_UINT16_WRITE(addr, val)    ((*((__packed uint16_t *)(addr))) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT16_READ
+  #define __UNALIGNED_UINT16_READ(addr)          (*((const __packed uint16_t *)(addr)))
+#endif
+#ifndef   __UNALIGNED_UINT32_WRITE
+  #define __UNALIGNED_UINT32_WRITE(addr, val)    ((*((__packed uint32_t *)(addr))) = (val))
+#endif
+#ifndef   __UNALIGNED_UINT32_READ
+  #define __UNALIGNED_UINT32_READ(addr)          (*((const __packed uint32_t *)(addr)))
+#endif
+#ifndef   __ALIGNED
+  #define __ALIGNED(x)                           __attribute__((aligned(x)))
+#endif
+#ifndef   __RESTRICT
+  #define __RESTRICT                             __restrict
+#endif
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+/**
+  \brief   Enable IRQ Interrupts
+  \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __enable_irq();     */
+
+
+/**
+  \brief   Disable IRQ Interrupts
+  \details Disables IRQ interrupts by setting the I-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+/* intrinsic void __disable_irq();    */
+
+/**
+  \brief   Get Control Register
+  \details Returns the content of the Control Register.
+  \return               Control Register value
+ */
+__STATIC_INLINE uint32_t __get_CONTROL(void)
+{
+  register uint32_t __regControl         __ASM("control");
+  return(__regControl);
+}
+
+
+/**
+  \brief   Set Control Register
+  \details Writes the given value to the Control Register.
+  \param [in]    control  Control Register value to set
+ */
+__STATIC_INLINE void __set_CONTROL(uint32_t control)
+{
+  register uint32_t __regControl         __ASM("control");
+  __regControl = control;
+}
+
+
+/**
+  \brief   Get IPSR Register
+  \details Returns the content of the IPSR Register.
+  \return               IPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_IPSR(void)
+{
+  register uint32_t __regIPSR          __ASM("ipsr");
+  return(__regIPSR);
+}
+
+
+/**
+  \brief   Get APSR Register
+  \details Returns the content of the APSR Register.
+  \return               APSR Register value
+ */
+__STATIC_INLINE uint32_t __get_APSR(void)
+{
+  register uint32_t __regAPSR          __ASM("apsr");
+  return(__regAPSR);
+}
+
+
+/**
+  \brief   Get xPSR Register
+  \details Returns the content of the xPSR Register.
+  \return               xPSR Register value
+ */
+__STATIC_INLINE uint32_t __get_xPSR(void)
+{
+  register uint32_t __regXPSR          __ASM("xpsr");
+  return(__regXPSR);
+}
+
+
+/**
+  \brief   Get Process Stack Pointer
+  \details Returns the current value of the Process Stack Pointer (PSP).
+  \return               PSP Register value
+ */
+__STATIC_INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  return(__regProcessStackPointer);
+}
+
+
+/**
+  \brief   Set Process Stack Pointer
+  \details Assigns the given value to the Process Stack Pointer (PSP).
+  \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  __regProcessStackPointer = topOfProcStack;
+}
+
+
+/**
+  \brief   Get Main Stack Pointer
+  \details Returns the current value of the Main Stack Pointer (MSP).
+  \return               MSP Register value
+ */
+__STATIC_INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  return(__regMainStackPointer);
+}
+
+
+/**
+  \brief   Set Main Stack Pointer
+  \details Assigns the given value to the Main Stack Pointer (MSP).
+  \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  __regMainStackPointer = topOfMainStack;
+}
+
+
+/**
+  \brief   Get Priority Mask
+  \details Returns the current state of the priority mask bit from the Priority Mask Register.
+  \return               Priority Mask value
+ */
+__STATIC_INLINE uint32_t __get_PRIMASK(void)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  return(__regPriMask);
+}
+
+
+/**
+  \brief   Set Priority Mask
+  \details Assigns the given value to the Priority Mask Register.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  __regPriMask = (priMask);
+}
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+
+/**
+  \brief   Enable FIQ
+  \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq
+
+
+/**
+  \brief   Disable FIQ
+  \details Disables FIQ interrupts by setting the F-bit in the CPSR.
+           Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq
+
+
+/**
+  \brief   Get Base Priority
+  \details Returns the current value of the Base Priority register.
+  \return               Base Priority register value
+ */
+__STATIC_INLINE uint32_t  __get_BASEPRI(void)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  return(__regBasePri);
+}
+
+
+/**
+  \brief   Set Base Priority
+  \details Assigns the given value to the Base Priority register.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  __regBasePri = (basePri & 0xFFU);
+}
+
+
+/**
+  \brief   Set Base Priority with condition
+  \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
+           or the new value increases the BASEPRI priority level.
+  \param [in]    basePri  Base Priority value to set
+ */
+__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
+{
+  register uint32_t __regBasePriMax      __ASM("basepri_max");
+  __regBasePriMax = (basePri & 0xFFU);
+}
+
+
+/**
+  \brief   Get Fault Mask
+  \details Returns the current value of the Fault Mask register.
+  \return               Fault Mask register value
+ */
+__STATIC_INLINE uint32_t __get_FAULTMASK(void)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  return(__regFaultMask);
+}
+
+
+/**
+  \brief   Set Fault Mask
+  \details Assigns the given value to the Fault Mask register.
+  \param [in]    faultMask  Fault Mask value to set
+ */
+__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  __regFaultMask = (faultMask & (uint32_t)1U);
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+
+
+/**
+  \brief   Get FPSCR
+  \details Returns the current value of the Floating Point Status/Control register.
+  \return               Floating Point Status/Control register value
+ */
+__STATIC_INLINE uint32_t __get_FPSCR(void)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+  register uint32_t __regfpscr         __ASM("fpscr");
+  return(__regfpscr);
+#else
+   return(0U);
+#endif
+}
+
+
+/**
+  \brief   Set FPSCR
+  \details Assigns the given value to the Floating Point Status/Control register.
+  \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+     (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+  register uint32_t __regfpscr         __ASM("fpscr");
+  __regfpscr = (fpscr);
+#else
+  (void)fpscr;
+#endif
+}
+
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+/**
+  \brief   No Operation
+  \details No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP                             __nop
+
+
+/**
+  \brief   Wait For Interrupt
+  \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
+ */
+#define __WFI                             __wfi
+
+
+/**
+  \brief   Wait For Event
+  \details Wait For Event is a hint instruction that permits the processor to enter
+           a low-power state until one of a number of events occurs.
+ */
+#define __WFE                             __wfe
+
+
+/**
+  \brief   Send Event
+  \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV                             __sev
+
+
+/**
+  \brief   Instruction Synchronization Barrier
+  \details Instruction Synchronization Barrier flushes the pipeline in the processor,
+           so that all instructions following the ISB are fetched from cache or memory,
+           after the instruction has been completed.
+ */
+#define __ISB() do {\
+                   __schedule_barrier();\
+                   __isb(0xF);\
+                   __schedule_barrier();\
+                } while (0U)
+
+/**
+  \brief   Data Synchronization Barrier
+  \details Acts as a special kind of Data Memory Barrier.
+           It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() do {\
+                   __schedule_barrier();\
+                   __dsb(0xF);\
+                   __schedule_barrier();\
+                } while (0U)
+
+/**
+  \brief   Data Memory Barrier
+  \details Ensures the apparent order of the explicit memory operations before
+           and after the instruction, without ensuring their completion.
+ */
+#define __DMB() do {\
+                   __schedule_barrier();\
+                   __dmb(0xF);\
+                   __schedule_barrier();\
+                } while (0U)
+
+                  
+/**
+  \brief   Reverse byte order (32 bit)
+  \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#define __REV                             __rev
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+  rev16 r0, r0
+  bx lr
+}
+#endif
+
+
+/**
+  \brief   Reverse byte order (16 bit)
+  \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value)
+{
+  revsh r0, r0
+  bx lr
+}
+#endif
+
+
+/**
+  \brief   Rotate Right in unsigned value (32 bit)
+  \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
+  \param [in]    op1  Value to rotate
+  \param [in]    op2  Number of Bits to rotate
+  \return               Rotated value
+ */
+#define __ROR                             __ror
+
+
+/**
+  \brief   Breakpoint
+  \details Causes the processor to enter Debug state.
+           Debug tools can use this to investigate system state when the instruction at a particular address is reached.
+  \param [in]    value  is ignored by the processor.
+                 If required, a debugger can use it to store additional information about the breakpoint.
+ */
+#define __BKPT(value)                       __breakpoint(value)
+
+
+/**
+  \brief   Reverse bit order of value
+  \details Reverses the bit order of the given value.
+  \param [in]    value  Value to reverse
+  \return               Reversed value
+ */
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+  #define __RBIT                          __rbit
+#else
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+  uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
+
+  result = value;                      /* r will be reversed bits of v; first get LSB of v */
+  for (value >>= 1U; value != 0U; value >>= 1U)
+  {
+    result <<= 1U;
+    result |= value & 1U;
+    s--;
+  }
+  result <<= s;                        /* shift when v's highest bits are zero */
+  return result;
+}
+#endif
+
+
+/**
+  \brief   Count leading zeros
+  \details Counts the number of leading zeros of a data value.
+  \param [in]  value  Value to count the leading zeros
+  \return             number of leading zeros in value
+ */
+#define __CLZ                             __clz
+
+
+#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+     (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+
+/**
+  \brief   LDR Exclusive (8 bit)
+  \details Executes a exclusive LDR instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __LDREXB(ptr)                                                        ((uint8_t ) __ldrex(ptr))
+#else
+  #define __LDREXB(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+
+/**
+  \brief   LDR Exclusive (16 bit)
+  \details Executes a exclusive LDR instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __LDREXH(ptr)                                                        ((uint16_t) __ldrex(ptr))
+#else
+  #define __LDREXH(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+
+/**
+  \brief   LDR Exclusive (32 bit)
+  \details Executes a exclusive LDR instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __LDREXW(ptr)                                                        ((uint32_t ) __ldrex(ptr))
+#else
+  #define __LDREXW(ptr)          _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr))  _Pragma("pop")
+#endif
+
+
+/**
+  \brief   STR Exclusive (8 bit)
+  \details Executes a exclusive STR instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __STREXB(value, ptr)                                                 __strex(value, ptr)
+#else
+  #define __STREXB(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+
+/**
+  \brief   STR Exclusive (16 bit)
+  \details Executes a exclusive STR instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __STREXH(value, ptr)                                                 __strex(value, ptr)
+#else
+  #define __STREXH(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+
+/**
+  \brief   STR Exclusive (32 bit)
+  \details Executes a exclusive STR instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+  \return          0  Function succeeded
+  \return          1  Function failed
+ */
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
+  #define __STREXW(value, ptr)                                                 __strex(value, ptr)
+#else
+  #define __STREXW(value, ptr)   _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr)        _Pragma("pop")
+#endif
+
+
+/**
+  \brief   Remove the exclusive lock
+  \details Removes the exclusive lock which is created by LDREX.
+ */
+#define __CLREX                           __clrex
+
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+#define __SSAT                            __ssat
+
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+#define __USAT                            __usat
+
+
+/**
+  \brief   Rotate Right with Extend (32 bit)
+  \details Moves each bit of a bitstring right by one bit.
+           The carry input is shifted in at the left end of the bitstring.
+  \param [in]    value  Value to rotate
+  \return               Rotated value
+ */
+#ifndef __NO_EMBEDDED_ASM
+__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
+{
+  rrx r0, r0
+  bx lr
+}
+#endif
+
+
+/**
+  \brief   LDRT Unprivileged (8 bit)
+  \details Executes a Unprivileged LDRT instruction for 8 bit value.
+  \param [in]    ptr  Pointer to data
+  \return             value of type uint8_t at (*ptr)
+ */
+#define __LDRBT(ptr)                      ((uint8_t )  __ldrt(ptr))
+
+
+/**
+  \brief   LDRT Unprivileged (16 bit)
+  \details Executes a Unprivileged LDRT instruction for 16 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint16_t at (*ptr)
+ */
+#define __LDRHT(ptr)                      ((uint16_t)  __ldrt(ptr))
+
+
+/**
+  \brief   LDRT Unprivileged (32 bit)
+  \details Executes a Unprivileged LDRT instruction for 32 bit values.
+  \param [in]    ptr  Pointer to data
+  \return        value of type uint32_t at (*ptr)
+ */
+#define __LDRT(ptr)                       ((uint32_t ) __ldrt(ptr))
+
+
+/**
+  \brief   STRT Unprivileged (8 bit)
+  \details Executes a Unprivileged STRT instruction for 8 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRBT(value, ptr)               __strt(value, ptr)
+
+
+/**
+  \brief   STRT Unprivileged (16 bit)
+  \details Executes a Unprivileged STRT instruction for 16 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRHT(value, ptr)               __strt(value, ptr)
+
+
+/**
+  \brief   STRT Unprivileged (32 bit)
+  \details Executes a Unprivileged STRT instruction for 32 bit values.
+  \param [in]  value  Value to store
+  \param [in]    ptr  Pointer to location
+ */
+#define __STRT(value, ptr)                __strt(value, ptr)
+
+#else  /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+
+/**
+  \brief   Signed Saturate
+  \details Saturates a signed value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (1..32)
+  \return             Saturated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
+{
+  if ((sat >= 1U) && (sat <= 32U))
+  {
+    const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+    const int32_t min = -1 - max ;
+    if (val > max)
+    {
+      return max;
+    }
+    else if (val < min)
+    {
+      return min;
+    }
+  }
+  return val;
+}
+
+/**
+  \brief   Unsigned Saturate
+  \details Saturates an unsigned value.
+  \param [in]  value  Value to be saturated
+  \param [in]    sat  Bit position to saturate to (0..31)
+  \return             Saturated value
+ */
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
+{
+  if (sat <= 31U)
+  {
+    const uint32_t max = ((1U << sat) - 1U);
+    if (val > (int32_t)max)
+    {
+      return max;
+    }
+    else if (val < 0)
+    {
+      return 0U;
+    }
+  }
+  return (uint32_t)val;
+}
+
+#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
+           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
+
+#define __SADD8                           __sadd8
+#define __QADD8                           __qadd8
+#define __SHADD8                          __shadd8
+#define __UADD8                           __uadd8
+#define __UQADD8                          __uqadd8
+#define __UHADD8                          __uhadd8
+#define __SSUB8                           __ssub8
+#define __QSUB8                           __qsub8
+#define __SHSUB8                          __shsub8
+#define __USUB8                           __usub8
+#define __UQSUB8                          __uqsub8
+#define __UHSUB8                          __uhsub8
+#define __SADD16                          __sadd16
+#define __QADD16                          __qadd16
+#define __SHADD16                         __shadd16
+#define __UADD16                          __uadd16
+#define __UQADD16                         __uqadd16
+#define __UHADD16                         __uhadd16
+#define __SSUB16                          __ssub16
+#define __QSUB16                          __qsub16
+#define __SHSUB16                         __shsub16
+#define __USUB16                          __usub16
+#define __UQSUB16                         __uqsub16
+#define __UHSUB16                         __uhsub16
+#define __SASX                            __sasx
+#define __QASX                            __qasx
+#define __SHASX                           __shasx
+#define __UASX                            __uasx
+#define __UQASX                           __uqasx
+#define __UHASX                           __uhasx
+#define __SSAX                            __ssax
+#define __QSAX                            __qsax
+#define __SHSAX                           __shsax
+#define __USAX                            __usax
+#define __UQSAX                           __uqsax
+#define __UHSAX                           __uhsax
+#define __USAD8                           __usad8
+#define __USADA8                          __usada8
+#define __SSAT16                          __ssat16
+#define __USAT16                          __usat16
+#define __UXTB16                          __uxtb16
+#define __UXTAB16                         __uxtab16
+#define __SXTB16                          __sxtb16
+#define __SXTAB16                         __sxtab16
+#define __SMUAD                           __smuad
+#define __SMUADX                          __smuadx
+#define __SMLAD                           __smlad
+#define __SMLADX                          __smladx
+#define __SMLALD                          __smlald
+#define __SMLALDX                         __smlaldx
+#define __SMUSD                           __smusd
+#define __SMUSDX                          __smusdx
+#define __SMLSD                           __smlsd
+#define __SMLSDX                          __smlsdx
+#define __SMLSLD                          __smlsld
+#define __SMLSLDX                         __smlsldx
+#define __SEL                             __sel
+#define __QADD                            __qadd
+#define __QSUB                            __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+#define __SMMLA(ARG1,ARG2,ARG3)          ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
+                                                      ((int64_t)(ARG3) << 32U)     ) >> 32U))
+
+#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CMSIS_ARMCC_H */

FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/CMSIS/cmsis_compiler.h

@@ -0,0 +1,271 @@
+/**************************************************************************//**
+ * @file     cmsis_compiler.h
+ * @brief    CMSIS compiler generic header file
+ * @version  V5.1.0
+ * @date     09. October 2018
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __CMSIS_COMPILER_H
+#define __CMSIS_COMPILER_H
+
+#include <stdint.h>
+
+/*
+ * Arm Compiler 4/5
+ */
+#if   defined ( __CC_ARM )
+  #include "cmsis_armcc.h"
+
+
+/*
+ * Arm Compiler 6.6 LTM (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100)
+  #include "cmsis_armclang_ltm.h"
+
+  /*
+ * Arm Compiler above 6.10.1 (armclang)
+ */
+#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
+  #include "cmsis_armclang.h"
+
+
+/*
+ * GNU Compiler
+ */
+#elif defined ( __GNUC__ )
+  #include "cmsis_gcc.h"
+
+
+/*
+ * IAR Compiler
+ */
+#elif defined ( __ICCARM__ )
+  #include <cmsis_iccarm.h>
+
+
+/*
+ * TI Arm Compiler
+ */
+#elif defined ( __TI_ARM__ )
+  #include <cmsis_ccs.h>
+
+  #ifndef   __ASM
+    #define __ASM                                  __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN                            __attribute__((noreturn))
+  #endif
+  #ifndef   __USED
+    #define __USED                                 __attribute__((used))
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __attribute__((weak))
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               __attribute__((packed))
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        struct __attribute__((packed))
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         union __attribute__((packed))
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    struct __attribute__((packed)) T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #define __ALIGNED(x)                           __attribute__((aligned(x)))
+  #endif
+  #ifndef   __RESTRICT
+    #define __RESTRICT                             __restrict
+  #endif
+
+
+/*
+ * TASKING Compiler
+ */
+#elif defined ( __TASKING__ )
+  /*
+   * The CMSIS functions have been implemented as intrinsics in the compiler.
+   * Please use "carm -?i" to get an up to date list of all intrinsics,
+   * Including the CMSIS ones.
+   */
+
+  #ifndef   __ASM
+    #define __ASM                                  __asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    #define __NO_RETURN                            __attribute__((noreturn))
+  #endif
+  #ifndef   __USED
+    #define __USED                                 __attribute__((used))
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __attribute__((weak))
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               __packed__
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        struct __packed__
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         union __packed__
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    struct __packed__ T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #define __ALIGNED(x)              __align(x)
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+
+
+/*
+ * COSMIC Compiler
+ */
+#elif defined ( __CSMC__ )
+   #include <cmsis_csm.h>
+
+ #ifndef   __ASM
+    #define __ASM                                  _asm
+  #endif
+  #ifndef   __INLINE
+    #define __INLINE                               inline
+  #endif
+  #ifndef   __STATIC_INLINE
+    #define __STATIC_INLINE                        static inline
+  #endif
+  #ifndef   __STATIC_FORCEINLINE
+    #define __STATIC_FORCEINLINE                   __STATIC_INLINE
+  #endif
+  #ifndef   __NO_RETURN
+    // NO RETURN is automatically detected hence no warning here
+    #define __NO_RETURN
+  #endif
+  #ifndef   __USED
+    #warning No compiler specific solution for __USED. __USED is ignored.
+    #define __USED
+  #endif
+  #ifndef   __WEAK
+    #define __WEAK                                 __weak
+  #endif
+  #ifndef   __PACKED
+    #define __PACKED                               @packed
+  #endif
+  #ifndef   __PACKED_STRUCT
+    #define __PACKED_STRUCT                        @packed struct
+  #endif
+  #ifndef   __PACKED_UNION
+    #define __PACKED_UNION                         @packed union
+  #endif
+  #ifndef   __UNALIGNED_UINT32        /* deprecated */
+    @packed struct T_UINT32 { uint32_t v; };
+    #define __UNALIGNED_UINT32(x)                  (((struct T_UINT32 *)(x))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT16_WRITE
+    __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
+    #define __UNALIGNED_UINT16_WRITE(addr, val)    (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT16_READ
+    __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
+    #define __UNALIGNED_UINT16_READ(addr)          (((const struct T_UINT16_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __UNALIGNED_UINT32_WRITE
+    __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
+    #define __UNALIGNED_UINT32_WRITE(addr, val)    (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
+  #endif
+  #ifndef   __UNALIGNED_UINT32_READ
+    __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
+    #define __UNALIGNED_UINT32_READ(addr)          (((const struct T_UINT32_READ *)(const void *)(addr))->v)
+  #endif
+  #ifndef   __ALIGNED
+    #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
+    #define __ALIGNED(x)
+  #endif
+  #ifndef   __RESTRICT
+    #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
+    #define __RESTRICT
+  #endif
+
+
+#else
+  #error Unknown compiler.
+#endif
+
+
+#endif /* __CMSIS_COMPILER_H */
+

FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/CMSIS/cmsis_iccarm.h

@@ -0,0 +1,940 @@
+/**************************************************************************//**
+ * @file     cmsis_iccarm.h
+ * @brief    CMSIS compiler ICCARM (IAR Compiler for Arm) header file
+ * @version  V5.0.8
+ * @date     04. September 2018
+ ******************************************************************************/
+
+//------------------------------------------------------------------------------
+//
+// Copyright (c) 2017-2018 IAR Systems
+//
+// Licensed under the Apache License, Version 2.0 (the "License")
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+//
+//------------------------------------------------------------------------------
+
+
+#ifndef __CMSIS_ICCARM_H__
+#define __CMSIS_ICCARM_H__
+
+#ifndef __ICCARM__
+  #error This file should only be compiled by ICCARM
+#endif
+
+#pragma system_include
+
+#define __IAR_FT _Pragma("inline=forced") __intrinsic
+
+#if (__VER__ >= 8000000)
+  #define __ICCARM_V8 1
+#else
+  #define __ICCARM_V8 0
+#endif
+
+#ifndef __ALIGNED
+  #if __ICCARM_V8
+    #define __ALIGNED(x) __attribute__((aligned(x)))
+  #elif (__VER__ >= 7080000)
+    /* Needs IAR language extensions */
+    #define __ALIGNED(x) __attribute__((aligned(x)))
+  #else
+    #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored.
+    #define __ALIGNED(x)
+  #endif
+#endif
+
+
+/* Define compiler macros for CPU architecture, used in CMSIS 5.
+ */
+#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__
+/* Macros already defined */
+#else
+  #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
+    #define __ARM_ARCH_8M_MAIN__ 1
+  #elif defined(__ARM8M_BASELINE__)
+    #define __ARM_ARCH_8M_BASE__ 1
+  #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M'
+    #if __ARM_ARCH == 6
+      #define __ARM_ARCH_6M__ 1
+    #elif __ARM_ARCH == 7
+      #if __ARM_FEATURE_DSP
+        #define __ARM_ARCH_7EM__ 1
+      #else
+        #define __ARM_ARCH_7M__ 1
+      #endif
+    #endif /* __ARM_ARCH */
+  #endif /* __ARM_ARCH_PROFILE == 'M' */
+#endif
+
+/* Alternativ core deduction for older ICCARM's */
+#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \
+    !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__)
+  #if defined(__ARM6M__) && (__CORE__ == __ARM6M__)
+    #define __ARM_ARCH_6M__ 1
+  #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__)
+    #define __ARM_ARCH_7M__ 1
+  #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__)
+    #define __ARM_ARCH_7EM__  1
+  #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__)
+    #define __ARM_ARCH_8M_BASE__ 1
+  #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__)
+    #define __ARM_ARCH_8M_MAIN__ 1
+  #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__)
+    #define __ARM_ARCH_8M_MAIN__ 1
+  #else
+    #error "Unknown target."
+  #endif
+#endif
+
+
+
+#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1
+  #define __IAR_M0_FAMILY  1
+#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1
+  #define __IAR_M0_FAMILY  1
+#else
+  #define __IAR_M0_FAMILY  0
+#endif
+
+
+#ifndef __ASM
+  #define __ASM __asm
+#endif
+
+#ifndef __INLINE
+  #define __INLINE inline
+#endif
+
+#ifndef   __NO_RETURN
+  #if __ICCARM_V8
+    #define __NO_RETURN __attribute__((__noreturn__))
+  #else
+    #define __NO_RETURN _Pragma("object_attribute=__noreturn")
+  #endif
+#endif
+
+#ifndef   __PACKED
+  #if __ICCARM_V8
+    #define __PACKED __attribute__((packed, aligned(1)))
+  #else
+    /* Needs IAR language extensions */
+    #define __PACKED __packed
+  #endif
+#endif
+
+#ifndef   __PACKED_STRUCT
+  #if __ICCARM_V8
+    #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
+  #else
+    /* Needs IAR language extensions */
+    #define __PACKED_STRUCT __packed struct
+  #endif
+#endif
+
+#ifndef   __PACKED_UNION
+  #if __ICCARM_V8
+    #define __PACKED_UNION union __attribute__((packed, aligned(1)))
+  #else
+    /* Needs IAR language extensions */
+    #define __PACKED_UNION __packed union
+  #endif
+#endif
+
+#ifndef   __RESTRICT
+  #if __ICCARM_V8
+    #define __RESTRICT            __restrict
+  #else
+    /* Needs IAR language extensions */
+    #define __RESTRICT            restrict
+  #endif
+#endif
+
+#ifndef   __STATIC_INLINE
+  #define __STATIC_INLINE       static inline
+#endif
+
+#ifndef   __FORCEINLINE
+  #define __FORCEINLINE         _Pragma("inline=forced")
+#endif
+
+#ifndef   __STATIC_FORCEINLINE
+  #define __STATIC_FORCEINLINE  __FORCEINLINE __STATIC_INLINE
+#endif
+
+#ifndef __UNALIGNED_UINT16_READ
+#pragma language=save
+#pragma language=extended
+__IAR_FT uint16_t __iar_uint16_read(void const *ptr)
+{
+  return *(__packed uint16_t*)(ptr);
+}
+#pragma language=restore
+#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR)
+#endif
+
+
+#ifndef __UNALIGNED_UINT16_WRITE
+#pragma language=save
+#pragma language=extended
+__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val)
+{
+  *(__packed uint16_t*)(ptr) = val;;
+}
+#pragma language=restore
+#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL)
+#endif
+
+#ifndef __UNALIGNED_UINT32_READ
+#pragma language=save
+#pragma language=extended
+__IAR_FT uint32_t __iar_uint32_read(void const *ptr)
+{
+  return *(__packed uint32_t*)(ptr);
+}
+#pragma language=restore
+#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR)
+#endif
+
+#ifndef __UNALIGNED_UINT32_WRITE
+#pragma language=save
+#pragma language=extended
+__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val)
+{
+  *(__packed uint32_t*)(ptr) = val;;
+}
+#pragma language=restore
+#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL)
+#endif
+
+#ifndef __UNALIGNED_UINT32   /* deprecated */
+#pragma language=save
+#pragma language=extended
+__packed struct  __iar_u32 { uint32_t v; };
+#pragma language=restore
+#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v)
+#endif
+
+#ifndef   __USED
+  #if __ICCARM_V8
+    #define __USED __attribute__((used))
+  #else
+    #define __USED _Pragma("__root")
+  #endif
+#endif
+
+#ifndef   __WEAK
+  #if __ICCARM_V8
+    #define __WEAK __attribute__((weak))
+  #else
+    #define __WEAK _Pragma("__weak")
+  #endif
+#endif
+
+
+#ifndef __ICCARM_INTRINSICS_VERSION__
+  #define __ICCARM_INTRINSICS_VERSION__  0
+#endif
+
+#if __ICCARM_INTRINSICS_VERSION__ == 2
+
+  #if defined(__CLZ)
+    #undef __CLZ
+  #endif
+  #if defined(__REVSH)
+    #undef __REVSH
+  #endif
+  #if defined(__RBIT)
+    #undef __RBIT
+  #endif
+  #if defined(__SSAT)
+    #undef __SSAT
+  #endif
+  #if defined(__USAT)
+    #undef __USAT
+  #endif
+
+  #include "iccarm_builtin.h"
+
+  #define __disable_fault_irq __iar_builtin_disable_fiq
+  #define __disable_irq       __iar_builtin_disable_interrupt
+  #define __enable_fault_irq  __iar_builtin_enable_fiq
+  #define __enable_irq        __iar_builtin_enable_interrupt
+  #define __arm_rsr           __iar_builtin_rsr
+  #define __arm_wsr           __iar_builtin_wsr
+
+
+  #define __get_APSR()                (__arm_rsr("APSR"))
+  #define __get_BASEPRI()             (__arm_rsr("BASEPRI"))
+  #define __get_CONTROL()             (__arm_rsr("CONTROL"))
+  #define __get_FAULTMASK()           (__arm_rsr("FAULTMASK"))
+
+  #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+       (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     )
+    #define __get_FPSCR()             (__arm_rsr("FPSCR"))
+    #define __set_FPSCR(VALUE)        (__arm_wsr("FPSCR", (VALUE)))
+  #else
+    #define __get_FPSCR()             ( 0 )
+    #define __set_FPSCR(VALUE)        ((void)VALUE)
+  #endif
+
+  #define __get_IPSR()                (__arm_rsr("IPSR"))
+  #define __get_MSP()                 (__arm_rsr("MSP"))
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure MSPLIM is RAZ/WI
+    #define __get_MSPLIM()            (0U)
+  #else
+    #define __get_MSPLIM()            (__arm_rsr("MSPLIM"))
+  #endif
+  #define __get_PRIMASK()             (__arm_rsr("PRIMASK"))
+  #define __get_PSP()                 (__arm_rsr("PSP"))
+
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+    #define __get_PSPLIM()            (0U)
+  #else
+    #define __get_PSPLIM()            (__arm_rsr("PSPLIM"))
+  #endif
+
+  #define __get_xPSR()                (__arm_rsr("xPSR"))
+
+  #define __set_BASEPRI(VALUE)        (__arm_wsr("BASEPRI", (VALUE)))
+  #define __set_BASEPRI_MAX(VALUE)    (__arm_wsr("BASEPRI_MAX", (VALUE)))
+  #define __set_CONTROL(VALUE)        (__arm_wsr("CONTROL", (VALUE)))
+  #define __set_FAULTMASK(VALUE)      (__arm_wsr("FAULTMASK", (VALUE)))
+  #define __set_MSP(VALUE)            (__arm_wsr("MSP", (VALUE)))
+
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure MSPLIM is RAZ/WI
+    #define __set_MSPLIM(VALUE)       ((void)(VALUE))
+  #else
+    #define __set_MSPLIM(VALUE)       (__arm_wsr("MSPLIM", (VALUE)))
+  #endif
+  #define __set_PRIMASK(VALUE)        (__arm_wsr("PRIMASK", (VALUE)))
+  #define __set_PSP(VALUE)            (__arm_wsr("PSP", (VALUE)))
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+    #define __set_PSPLIM(VALUE)       ((void)(VALUE))
+  #else
+    #define __set_PSPLIM(VALUE)       (__arm_wsr("PSPLIM", (VALUE)))
+  #endif
+
+  #define __TZ_get_CONTROL_NS()       (__arm_rsr("CONTROL_NS"))
+  #define __TZ_set_CONTROL_NS(VALUE)  (__arm_wsr("CONTROL_NS", (VALUE)))
+  #define __TZ_get_PSP_NS()           (__arm_rsr("PSP_NS"))
+  #define __TZ_set_PSP_NS(VALUE)      (__arm_wsr("PSP_NS", (VALUE)))
+  #define __TZ_get_MSP_NS()           (__arm_rsr("MSP_NS"))
+  #define __TZ_set_MSP_NS(VALUE)      (__arm_wsr("MSP_NS", (VALUE)))
+  #define __TZ_get_SP_NS()            (__arm_rsr("SP_NS"))
+  #define __TZ_set_SP_NS(VALUE)       (__arm_wsr("SP_NS", (VALUE)))
+  #define __TZ_get_PRIMASK_NS()       (__arm_rsr("PRIMASK_NS"))
+  #define __TZ_set_PRIMASK_NS(VALUE)  (__arm_wsr("PRIMASK_NS", (VALUE)))
+  #define __TZ_get_BASEPRI_NS()       (__arm_rsr("BASEPRI_NS"))
+  #define __TZ_set_BASEPRI_NS(VALUE)  (__arm_wsr("BASEPRI_NS", (VALUE)))
+  #define __TZ_get_FAULTMASK_NS()     (__arm_rsr("FAULTMASK_NS"))
+  #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE)))
+
+  #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+       (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3)))
+    // without main extensions, the non-secure PSPLIM is RAZ/WI
+    #define __TZ_get_PSPLIM_NS()      (0U)
+    #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE))
+  #else
+    #define __TZ_get_PSPLIM_NS()      (__arm_rsr("PSPLIM_NS"))
+    #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE)))
+  #endif
+
+  #define __TZ_get_MSPLIM_NS()        (__arm_rsr("MSPLIM_NS"))
+  #define __TZ_set_MSPLIM_NS(VALUE)   (__arm_wsr("MSPLIM_NS", (VALUE)))
+
+  #define __NOP     __iar_builtin_no_operation
+
+  #define __CLZ     __iar_builtin_CLZ
+  #define __CLREX   __iar_builtin_CLREX
+
+  #define __DMB     __iar_builtin_DMB
+  #define __DSB     __iar_builtin_DSB
+  #define __ISB     __iar_builtin_ISB
+
+  #define __LDREXB  __iar_builtin_LDREXB
+  #define __LDREXH  __iar_builtin_LDREXH
+  #define __LDREXW  __iar_builtin_LDREX
+
+  #define __RBIT    __iar_builtin_RBIT
+  #define __REV     __iar_builtin_REV
+  #define __REV16   __iar_builtin_REV16
+
+  __IAR_FT int16_t __REVSH(int16_t val)
+  {
+    return (int16_t) __iar_builtin_REVSH(val);
+  }
+
+  #define __ROR     __iar_builtin_ROR
+  #define __RRX     __iar_builtin_RRX
+
+  #define __SEV     __iar_builtin_SEV
+
+  #if !__IAR_M0_FAMILY
+    #define __SSAT    __iar_builtin_SSAT
+  #endif
+
+  #define __STREXB  __iar_builtin_STREXB
+  #define __STREXH  __iar_builtin_STREXH
+  #define __STREXW  __iar_builtin_STREX
+
+  #if !__IAR_M0_FAMILY
+    #define __USAT    __iar_builtin_USAT
+  #endif
+
+  #define __WFE     __iar_builtin_WFE
+  #define __WFI     __iar_builtin_WFI
+
+  #if __ARM_MEDIA__
+    #define __SADD8   __iar_builtin_SADD8
+    #define __QADD8   __iar_builtin_QADD8
+    #define __SHADD8  __iar_builtin_SHADD8
+    #define __UADD8   __iar_builtin_UADD8
+    #define __UQADD8  __iar_builtin_UQADD8
+    #define __UHADD8  __iar_builtin_UHADD8
+    #define __SSUB8   __iar_builtin_SSUB8
+    #define __QSUB8   __iar_builtin_QSUB8
+    #define __SHSUB8  __iar_builtin_SHSUB8
+    #define __USUB8   __iar_builtin_USUB8
+    #define __UQSUB8  __iar_builtin_UQSUB8
+    #define __UHSUB8  __iar_builtin_UHSUB8
+    #define __SADD16  __iar_builtin_SADD16
+    #define __QADD16  __iar_builtin_QADD16
+    #define __SHADD16 __iar_builtin_SHADD16
+    #define __UADD16  __iar_builtin_UADD16
+    #define __UQADD16 __iar_builtin_UQADD16
+    #define __UHADD16 __iar_builtin_UHADD16
+    #define __SSUB16  __iar_builtin_SSUB16
+    #define __QSUB16  __iar_builtin_QSUB16
+    #define __SHSUB16 __iar_builtin_SHSUB16
+    #define __USUB16  __iar_builtin_USUB16
+    #define __UQSUB16 __iar_builtin_UQSUB16
+    #define __UHSUB16 __iar_builtin_UHSUB16
+    #define __SASX    __iar_builtin_SASX
+    #define __QASX    __iar_builtin_QASX
+    #define __SHASX   __iar_builtin_SHASX
+    #define __UASX    __iar_builtin_UASX
+    #define __UQASX   __iar_builtin_UQASX
+    #define __UHASX   __iar_builtin_UHASX
+    #define __SSAX    __iar_builtin_SSAX
+    #define __QSAX    __iar_builtin_QSAX
+    #define __SHSAX   __iar_builtin_SHSAX
+    #define __USAX    __iar_builtin_USAX
+    #define __UQSAX   __iar_builtin_UQSAX
+    #define __UHSAX   __iar_builtin_UHSAX
+    #define __USAD8   __iar_builtin_USAD8
+    #define __USADA8  __iar_builtin_USADA8
+    #define __SSAT16  __iar_builtin_SSAT16
+    #define __USAT16  __iar_builtin_USAT16
+    #define __UXTB16  __iar_builtin_UXTB16
+    #define __UXTAB16 __iar_builtin_UXTAB16
+    #define __SXTB16  __iar_builtin_SXTB16
+    #define __SXTAB16 __iar_builtin_SXTAB16
+    #define __SMUAD   __iar_builtin_SMUAD
+    #define __SMUADX  __iar_builtin_SMUADX
+    #define __SMMLA   __iar_builtin_SMMLA
+    #define __SMLAD   __iar_builtin_SMLAD
+    #define __SMLADX  __iar_builtin_SMLADX
+    #define __SMLALD  __iar_builtin_SMLALD
+    #define __SMLALDX __iar_builtin_SMLALDX
+    #define __SMUSD   __iar_builtin_SMUSD
+    #define __SMUSDX  __iar_builtin_SMUSDX
+    #define __SMLSD   __iar_builtin_SMLSD
+    #define __SMLSDX  __iar_builtin_SMLSDX
+    #define __SMLSLD  __iar_builtin_SMLSLD
+    #define __SMLSLDX __iar_builtin_SMLSLDX
+    #define __SEL     __iar_builtin_SEL
+    #define __QADD    __iar_builtin_QADD
+    #define __QSUB    __iar_builtin_QSUB
+    #define __PKHBT   __iar_builtin_PKHBT
+    #define __PKHTB   __iar_builtin_PKHTB
+  #endif
+
+#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */
+
+  #if __IAR_M0_FAMILY
+   /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
+    #define __CLZ  __cmsis_iar_clz_not_active
+    #define __SSAT __cmsis_iar_ssat_not_active
+    #define __USAT __cmsis_iar_usat_not_active
+    #define __RBIT __cmsis_iar_rbit_not_active
+    #define __get_APSR  __cmsis_iar_get_APSR_not_active
+  #endif
+
+
+  #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+         (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     ))
+    #define __get_FPSCR __cmsis_iar_get_FPSR_not_active
+    #define __set_FPSCR __cmsis_iar_set_FPSR_not_active
+  #endif
+
+  #ifdef __INTRINSICS_INCLUDED
+  #error intrinsics.h is already included previously!
+  #endif
+
+  #include <intrinsics.h>
+
+  #if __IAR_M0_FAMILY
+   /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
+    #undef __CLZ
+    #undef __SSAT
+    #undef __USAT
+    #undef __RBIT
+    #undef __get_APSR
+
+    __STATIC_INLINE uint8_t __CLZ(uint32_t data)
+    {
+      if (data == 0U) { return 32U; }
+
+      uint32_t count = 0U;
+      uint32_t mask = 0x80000000U;
+
+      while ((data & mask) == 0U)
+      {
+        count += 1U;
+        mask = mask >> 1U;
+      }
+      return count;
+    }
+
+    __STATIC_INLINE uint32_t __RBIT(uint32_t v)
+    {
+      uint8_t sc = 31U;
+      uint32_t r = v;
+      for (v >>= 1U; v; v >>= 1U)
+      {
+        r <<= 1U;
+        r |= v & 1U;
+        sc--;
+      }
+      return (r << sc);
+    }
+
+    __STATIC_INLINE  uint32_t __get_APSR(void)
+    {
+      uint32_t res;
+      __asm("MRS      %0,APSR" : "=r" (res));
+      return res;
+    }
+
+  #endif
+
+  #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
+         (defined (__FPU_USED   ) && (__FPU_USED    == 1U))     ))
+    #undef __get_FPSCR
+    #undef __set_FPSCR
+    #define __get_FPSCR()       (0)
+    #define __set_FPSCR(VALUE)  ((void)VALUE)
+  #endif
+
+  #pragma diag_suppress=Pe940
+  #pragma diag_suppress=Pe177
+
+  #define __enable_irq    __enable_interrupt
+  #define __disable_irq   __disable_interrupt
+  #define __NOP           __no_operation
+
+  #define __get_xPSR      __get_PSR
+
+  #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0)
+
+    __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr)
+    {
+      return __LDREX((unsigned long *)ptr);
+    }
+
+    __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr)
+    {
+      return __STREX(value, (unsigned long *)ptr);
+    }
+  #endif
+
+
+  /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
+  #if (__CORTEX_M >= 0x03)
+
+    __IAR_FT uint32_t __RRX(uint32_t value)
+    {
+      uint32_t result;
+      __ASM("RRX      %0, %1" : "=r"(result) : "r" (value) : "cc");
+      return(result);
+    }
+
+    __IAR_FT void __set_BASEPRI_MAX(uint32_t value)
+    {
+      __asm volatile("MSR      BASEPRI_MAX,%0"::"r" (value));
+    }
+
+
+    #define __enable_fault_irq  __enable_fiq
+    #define __disable_fault_irq __disable_fiq
+
+
+  #endif /* (__CORTEX_M >= 0x03) */
+
+  __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2)
+  {
+    return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
+  }
+
+  #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+       (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+
+   __IAR_FT uint32_t __get_MSPLIM(void)
+    {
+      uint32_t res;
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure MSPLIM is RAZ/WI
+      res = 0U;
+    #else
+      __asm volatile("MRS      %0,MSPLIM" : "=r" (res));
+    #endif
+      return res;
+    }
+
+    __IAR_FT void   __set_MSPLIM(uint32_t value)
+    {
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure MSPLIM is RAZ/WI
+      (void)value;
+    #else
+      __asm volatile("MSR      MSPLIM,%0" :: "r" (value));
+    #endif
+    }
+
+    __IAR_FT uint32_t __get_PSPLIM(void)
+    {
+      uint32_t res;
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure PSPLIM is RAZ/WI
+      res = 0U;
+    #else
+      __asm volatile("MRS      %0,PSPLIM" : "=r" (res));
+    #endif
+      return res;
+    }
+
+    __IAR_FT void   __set_PSPLIM(uint32_t value)
+    {
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure PSPLIM is RAZ/WI
+      (void)value;
+    #else
+      __asm volatile("MSR      PSPLIM,%0" :: "r" (value));
+    #endif
+    }
+
+    __IAR_FT uint32_t __TZ_get_CONTROL_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,CONTROL_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_CONTROL_NS(uint32_t value)
+    {
+      __asm volatile("MSR      CONTROL_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_PSP_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,PSP_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_PSP_NS(uint32_t value)
+    {
+      __asm volatile("MSR      PSP_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_MSP_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,MSP_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_MSP_NS(uint32_t value)
+    {
+      __asm volatile("MSR      MSP_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_SP_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,SP_NS" : "=r" (res));
+      return res;
+    }
+    __IAR_FT void   __TZ_set_SP_NS(uint32_t value)
+    {
+      __asm volatile("MSR      SP_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_PRIMASK_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,PRIMASK_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_PRIMASK_NS(uint32_t value)
+    {
+      __asm volatile("MSR      PRIMASK_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_BASEPRI_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,BASEPRI_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_BASEPRI_NS(uint32_t value)
+    {
+      __asm volatile("MSR      BASEPRI_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_FAULTMASK_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,FAULTMASK_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_FAULTMASK_NS(uint32_t value)
+    {
+      __asm volatile("MSR      FAULTMASK_NS,%0" :: "r" (value));
+    }
+
+    __IAR_FT uint32_t   __TZ_get_PSPLIM_NS(void)
+    {
+      uint32_t res;
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure PSPLIM is RAZ/WI
+      res = 0U;
+    #else
+      __asm volatile("MRS      %0,PSPLIM_NS" : "=r" (res));
+    #endif
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_PSPLIM_NS(uint32_t value)
+    {
+    #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \
+         (!defined (__ARM_FEATURE_CMSE  ) || (__ARM_FEATURE_CMSE   < 3)))
+      // without main extensions, the non-secure PSPLIM is RAZ/WI
+      (void)value;
+    #else
+      __asm volatile("MSR      PSPLIM_NS,%0" :: "r" (value));
+    #endif
+    }
+
+    __IAR_FT uint32_t   __TZ_get_MSPLIM_NS(void)
+    {
+      uint32_t res;
+      __asm volatile("MRS      %0,MSPLIM_NS" : "=r" (res));
+      return res;
+    }
+
+    __IAR_FT void   __TZ_set_MSPLIM_NS(uint32_t value)
+    {
+      __asm volatile("MSR      MSPLIM_NS,%0" :: "r" (value));
+    }
+
+  #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
+
+#endif   /* __ICCARM_INTRINSICS_VERSION__ == 2 */
+
+#define __BKPT(value)    __asm volatile ("BKPT     %0" : : "i"(value))
+
+#if __IAR_M0_FAMILY
+  __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
+  {
+    if ((sat >= 1U) && (sat <= 32U))
+    {
+      const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
+      const int32_t min = -1 - max ;
+      if (val > max)
+      {
+        return max;
+      }
+      else if (val < min)
+      {
+        return min;
+      }
+    }
+    return val;
+  }
+
+  __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
+  {
+    if (sat <= 31U)
+    {
+      const uint32_t max = ((1U << sat) - 1U);
+      if (val > (int32_t)max)
+      {
+        return max;
+      }
+      else if (val < 0)
+      {
+        return 0U;
+      }
+    }
+    return (uint32_t)val;
+  }
+#endif
+
+#if (__CORTEX_M >= 0x03)   /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
+
+  __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr)
+  {
+    uint32_t res;
+    __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+    return ((uint8_t)res);
+  }
+
+  __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr)
+  {
+    uint32_t res;
+    __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+    return ((uint16_t)res);
+  }
+
+  __IAR_FT uint32_t __LDRT(volatile uint32_t *addr)
+  {
+    uint32_t res;
+    __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory");
+    return res;
+  }
+
+  __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr)
+  {
+    __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
+  }
+
+  __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr)
+  {
+    __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory");
+  }
+
+  __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr)
+  {
+    __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory");
+  }
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
+     (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1))    )
+
+
+  __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return ((uint8_t)res);
+  }
+
+  __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return ((uint16_t)res);
+  }
+
+  __IAR_FT uint32_t __LDA(volatile uint32_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return res;
+  }
+
+  __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr)
+  {
+    __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+  }
+
+  __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr)
+  {
+    __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+  }
+
+  __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr)
+  {
+    __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory");
+  }
+
+  __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return ((uint8_t)res);
+  }
+
+  __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return ((uint16_t)res);
+  }
+
+  __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory");
+    return res;
+  }
+
+  __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+    return res;
+  }
+
+  __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+    return res;
+  }
+
+  __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
+  {
+    uint32_t res;
+    __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory");
+    return res;
+  }
+
+#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */
+
+#undef __IAR_FT
+#undef __IAR_M0_FAMILY
+#undef __ICCARM_V8
+
+#pragma diag_default=Pe940
+#pragma diag_default=Pe177
+
+#endif /* __CMSIS_ICCARM_H__ */

FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/CMSIS/cmsis_version.h

@@ -0,0 +1,39 @@
+/**************************************************************************//**
+ * @file     cmsis_version.h
+ * @brief    CMSIS Core(M) Version definitions
+ * @version  V5.0.2
+ * @date     19. April 2017
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CMSIS_VERSION_H
+#define __CMSIS_VERSION_H
+
+/*  CMSIS Version definitions */
+#define __CM_CMSIS_VERSION_MAIN  ( 5U)                                      /*!< [31:16] CMSIS Core(M) main version */
+#define __CM_CMSIS_VERSION_SUB   ( 1U)                                      /*!< [15:0]  CMSIS Core(M) sub version */
+#define __CM_CMSIS_VERSION       ((__CM_CMSIS_VERSION_MAIN << 16U) | \
+                                   __CM_CMSIS_VERSION_SUB           )       /*!< CMSIS Core(M) version number */
+#endif

FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/CMSIS/mpu_armv7.h

@@ -0,0 +1,272 @@
+/******************************************************************************
+ * @file     mpu_armv7.h
+ * @brief    CMSIS MPU API for Armv7-M MPU
+ * @version  V5.1.0
+ * @date     08. March 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+ 
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header    /* treat file as system include file */
+#endif
+ 
+#ifndef ARM_MPU_ARMV7_H
+#define ARM_MPU_ARMV7_H
+
+#define ARM_MPU_REGION_SIZE_32B      ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
+#define ARM_MPU_REGION_SIZE_64B      ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
+#define ARM_MPU_REGION_SIZE_128B     ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
+#define ARM_MPU_REGION_SIZE_256B     ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
+#define ARM_MPU_REGION_SIZE_512B     ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
+#define ARM_MPU_REGION_SIZE_1KB      ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
+#define ARM_MPU_REGION_SIZE_2KB      ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
+#define ARM_MPU_REGION_SIZE_4KB      ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
+#define ARM_MPU_REGION_SIZE_8KB      ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
+#define ARM_MPU_REGION_SIZE_16KB     ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
+#define ARM_MPU_REGION_SIZE_32KB     ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
+#define ARM_MPU_REGION_SIZE_64KB     ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
+#define ARM_MPU_REGION_SIZE_128KB    ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
+#define ARM_MPU_REGION_SIZE_256KB    ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
+#define ARM_MPU_REGION_SIZE_512KB    ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
+#define ARM_MPU_REGION_SIZE_1MB      ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
+#define ARM_MPU_REGION_SIZE_2MB      ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
+#define ARM_MPU_REGION_SIZE_4MB      ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
+#define ARM_MPU_REGION_SIZE_8MB      ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
+#define ARM_MPU_REGION_SIZE_16MB     ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
+#define ARM_MPU_REGION_SIZE_32MB     ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
+#define ARM_MPU_REGION_SIZE_64MB     ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
+#define ARM_MPU_REGION_SIZE_128MB    ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
+#define ARM_MPU_REGION_SIZE_256MB    ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
+#define ARM_MPU_REGION_SIZE_512MB    ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
+#define ARM_MPU_REGION_SIZE_1GB      ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
+#define ARM_MPU_REGION_SIZE_2GB      ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
+#define ARM_MPU_REGION_SIZE_4GB      ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
+
+#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
+#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
+#define ARM_MPU_AP_URO  2U ///!< MPU Access Permission unprivileged access read-only
+#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
+#define ARM_MPU_AP_PRO  5U ///!< MPU Access Permission privileged access read-only
+#define ARM_MPU_AP_RO   6U ///!< MPU Access Permission read-only access
+
+/** MPU Region Base Address Register Value
+*
+* \param Region The region to be configured, number 0 to 15.
+* \param BaseAddress The base address for the region.
+*/
+#define ARM_MPU_RBAR(Region, BaseAddress) \
+  (((BaseAddress) & MPU_RBAR_ADDR_Msk) |  \
+   ((Region) & MPU_RBAR_REGION_Msk)    |  \
+   (MPU_RBAR_VALID_Msk))
+
+/**
+* MPU Memory Access Attributes
+* 
+* \param TypeExtField      Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
+* \param IsShareable       Region is shareable between multiple bus masters.
+* \param IsCacheable       Region is cacheable, i.e. its value may be kept in cache.
+* \param IsBufferable      Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
+*/  
+#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable)   \
+  ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk)                  | \
+   (((IsShareable)  << MPU_RASR_S_Pos)   & MPU_RASR_S_Msk)                    | \
+   (((IsCacheable)  << MPU_RASR_C_Pos)   & MPU_RASR_C_Msk)                    | \
+   (((IsBufferable) << MPU_RASR_B_Pos)   & MPU_RASR_B_Msk))
+
+/**
+* MPU Region Attribute and Size Register Value
+* 
+* \param DisableExec       Instruction access disable bit, 1= disable instruction fetches.
+* \param AccessPermission  Data access permissions, allows you to configure read/write access for User and Privileged mode.
+* \param AccessAttributes  Memory access attribution, see \ref ARM_MPU_ACCESS_.
+* \param SubRegionDisable  Sub-region disable field.
+* \param Size              Region size of the region to be configured, for example 4K, 8K.
+*/
+#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size)    \
+  ((((DisableExec)      << MPU_RASR_XN_Pos)   & MPU_RASR_XN_Msk)                                  | \
+   (((AccessPermission) << MPU_RASR_AP_Pos)   & MPU_RASR_AP_Msk)                                  | \
+   (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \
+   (((SubRegionDisable) << MPU_RASR_SRD_Pos)  & MPU_RASR_SRD_Msk)                                 | \
+   (((Size)             << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk)                                | \
+   (((MPU_RASR_ENABLE_Msk))))
+
+/**
+* MPU Region Attribute and Size Register Value
+* 
+* \param DisableExec       Instruction access disable bit, 1= disable instruction fetches.
+* \param AccessPermission  Data access permissions, allows you to configure read/write access for User and Privileged mode.
+* \param TypeExtField      Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
+* \param IsShareable       Region is shareable between multiple bus masters.
+* \param IsCacheable       Region is cacheable, i.e. its value may be kept in cache.
+* \param IsBufferable      Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
+* \param SubRegionDisable  Sub-region disable field.
+* \param Size              Region size of the region to be configured, for example 4K, 8K.
+*/                         
+#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
+  ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
+
+/**
+* MPU Memory Access Attribute for strongly ordered memory.
+*  - TEX: 000b
+*  - Shareable
+*  - Non-cacheable
+*  - Non-bufferable
+*/ 
+#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
+
+/**
+* MPU Memory Access Attribute for device memory.
+*  - TEX: 000b (if shareable) or 010b (if non-shareable)
+*  - Shareable or non-shareable
+*  - Non-cacheable
+*  - Bufferable (if shareable) or non-bufferable (if non-shareable)
+*
+* \param IsShareable Configures the device memory as shareable or non-shareable.
+*/ 
+#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
+
+/**
+* MPU Memory Access Attribute for normal memory.
+*  - TEX: 1BBb (reflecting outer cacheability rules)
+*  - Shareable or non-shareable
+*  - Cacheable or non-cacheable (reflecting inner cacheability rules)
+*  - Bufferable or non-bufferable (reflecting inner cacheability rules)
+*
+* \param OuterCp Configures the outer cache policy.
+* \param InnerCp Configures the inner cache policy.
+* \param IsShareable Configures the memory as shareable or non-shareable.
+*/ 
+#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U))
+
+/**
+* MPU Memory Access Attribute non-cacheable policy.
+*/
+#define ARM_MPU_CACHEP_NOCACHE 0U
+
+/**
+* MPU Memory Access Attribute write-back, write and read allocate policy.
+*/
+#define ARM_MPU_CACHEP_WB_WRA 1U
+
+/**
+* MPU Memory Access Attribute write-through, no write allocate policy.
+*/
+#define ARM_MPU_CACHEP_WT_NWA 2U
+
+/**
+* MPU Memory Access Attribute write-back, no write allocate policy.
+*/
+#define ARM_MPU_CACHEP_WB_NWA 3U
+
+
+/**
+* Struct for a single MPU Region
+*/
+typedef struct {
+  uint32_t RBAR; //!< The region base address register value (RBAR)
+  uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
+} ARM_MPU_Region_t;
+    
+/** Enable the MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
+{
+  MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  __DSB();
+  __ISB();
+}
+
+/** Disable the MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable(void)
+{
+  __DMB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
+}
+
+/** Clear and disable the given MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
+{
+  MPU->RNR = rnr;
+  MPU->RASR = 0U;
+}
+
+/** Configure an MPU region.
+* \param rbar Value for RBAR register.
+* \param rsar Value for RSAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
+{
+  MPU->RBAR = rbar;
+  MPU->RASR = rasr;
+}
+
+/** Configure the given MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rsar Value for RSAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
+{
+  MPU->RNR = rnr;
+  MPU->RBAR = rbar;
+  MPU->RASR = rasr;
+}
+
+/** Memcopy with strictly ordered memory access, e.g. for register targets.
+* \param dst Destination data is copied to.
+* \param src Source data is copied from.
+* \param len Amount of data words to be copied.
+*/
+__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
+{
+  uint32_t i;
+  for (i = 0U; i < len; ++i) 
+  {
+    dst[i] = src[i];
+  }
+}
+
+/** Load the given number of MPU regions from a table.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) 
+{
+  const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
+  while (cnt > MPU_TYPE_RALIASES) {
+    ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
+    table += MPU_TYPE_RALIASES;
+    cnt -= MPU_TYPE_RALIASES;
+  }
+  ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
+}
+
+#endif

FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/CMSIS/mpu_armv8.h

@@ -0,0 +1,346 @@
+/******************************************************************************
+ * @file     mpu_armv8.h
+ * @brief    CMSIS MPU API for Armv8-M and Armv8.1-M MPU
+ * @version  V5.1.0
+ * @date     08. March 2019
+ ******************************************************************************/
+/*
+ * Copyright (c) 2017-2019 Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header    /* treat file as system include file */
+#endif
+
+#ifndef ARM_MPU_ARMV8_H
+#define ARM_MPU_ARMV8_H
+
+/** \brief Attribute for device memory (outer only) */
+#define ARM_MPU_ATTR_DEVICE                           ( 0U )
+
+/** \brief Attribute for non-cacheable, normal memory */
+#define ARM_MPU_ATTR_NON_CACHEABLE                    ( 4U )
+
+/** \brief Attribute for normal memory (outer and inner)
+* \param NT Non-Transient: Set to 1 for non-transient data.
+* \param WB Write-Back: Set to 1 to use write-back update policy.
+* \param RA Read Allocation: Set to 1 to use cache allocation on read miss.
+* \param WA Write Allocation: Set to 1 to use cache allocation on write miss.
+*/
+#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \
+  (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U))
+
+/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U)
+
+/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_nGnRE  (1U)
+
+/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_nGRE   (2U)
+
+/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */
+#define ARM_MPU_ATTR_DEVICE_GRE    (3U)
+
+/** \brief Memory Attribute
+* \param O Outer memory attributes
+* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes
+*/
+#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U)))
+
+/** \brief Normal memory non-shareable  */
+#define ARM_MPU_SH_NON   (0U)
+
+/** \brief Normal memory outer shareable  */
+#define ARM_MPU_SH_OUTER (2U)
+
+/** \brief Normal memory inner shareable  */
+#define ARM_MPU_SH_INNER (3U)
+
+/** \brief Memory access permissions
+* \param RO Read-Only: Set to 1 for read-only memory.
+* \param NP Non-Privileged: Set to 1 for non-privileged memory.
+*/
+#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U))
+
+/** \brief Region Base Address Register value
+* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned.
+* \param SH Defines the Shareability domain for this memory region.
+* \param RO Read-Only: Set to 1 for a read-only memory region.
+* \param NP Non-Privileged: Set to 1 for a non-privileged memory region.
+* \oaram XN eXecute Never: Set to 1 for a non-executable memory region.
+*/
+#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \
+  ((BASE & MPU_RBAR_BASE_Msk) | \
+  ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \
+  ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \
+  ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk))
+
+/** \brief Region Limit Address Register value
+* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
+* \param IDX The attribute index to be associated with this memory region.
+*/
+#define ARM_MPU_RLAR(LIMIT, IDX) \
+  ((LIMIT & MPU_RLAR_LIMIT_Msk) | \
+  ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
+  (MPU_RLAR_EN_Msk))
+
+#if defined(MPU_RLAR_PXN_Pos)
+  
+/** \brief Region Limit Address Register with PXN value
+* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended.
+* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region.
+* \param IDX The attribute index to be associated with this memory region.
+*/
+#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \
+  ((LIMIT & MPU_RLAR_LIMIT_Msk) | \
+  ((PXN << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \
+  ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \
+  (MPU_RLAR_EN_Msk))
+  
+#endif
+
+/**
+* Struct for a single MPU Region
+*/
+typedef struct {
+  uint32_t RBAR;                   /*!< Region Base Address Register value */
+  uint32_t RLAR;                   /*!< Region Limit Address Register value */
+} ARM_MPU_Region_t;
+    
+/** Enable the MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
+{
+  MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  __DSB();
+  __ISB();
+}
+
+/** Disable the MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable(void)
+{
+  __DMB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  MPU->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
+}
+
+#ifdef MPU_NS
+/** Enable the Non-secure MPU.
+* \param MPU_Control Default access permissions for unconfigured regions.
+*/
+__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control)
+{
+  MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  __DSB();
+  __ISB();
+}
+
+/** Disable the Non-secure MPU.
+*/
+__STATIC_INLINE void ARM_MPU_Disable_NS(void)
+{
+  __DMB();
+#ifdef SCB_SHCSR_MEMFAULTENA_Msk
+  SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
+#endif
+  MPU_NS->CTRL  &= ~MPU_CTRL_ENABLE_Msk;
+}
+#endif
+
+/** Set the memory attribute encoding to the given MPU.
+* \param mpu Pointer to the MPU to be configured.
+* \param idx The attribute index to be set [0-7]
+* \param attr The attribute value to be set.
+*/
+__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr)
+{
+  const uint8_t reg = idx / 4U;
+  const uint32_t pos = ((idx % 4U) * 8U);
+  const uint32_t mask = 0xFFU << pos;
+  
+  if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) {
+    return; // invalid index
+  }
+  
+  mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask));
+}
+
+/** Set the memory attribute encoding.
+* \param idx The attribute index to be set [0-7]
+* \param attr The attribute value to be set.
+*/
+__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr)
+{
+  ARM_MPU_SetMemAttrEx(MPU, idx, attr);
+}
+
+#ifdef MPU_NS
+/** Set the memory attribute encoding to the Non-secure MPU.
+* \param idx The attribute index to be set [0-7]
+* \param attr The attribute value to be set.
+*/
+__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr)
+{
+  ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr);
+}
+#endif
+
+/** Clear and disable the given MPU region of the given MPU.
+* \param mpu Pointer to MPU to be used.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr)
+{
+  mpu->RNR = rnr;
+  mpu->RLAR = 0U;
+}
+
+/** Clear and disable the given MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
+{
+  ARM_MPU_ClrRegionEx(MPU, rnr);
+}
+
+#ifdef MPU_NS
+/** Clear and disable the given Non-secure MPU region.
+* \param rnr Region number to be cleared.
+*/
+__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr)
+{  
+  ARM_MPU_ClrRegionEx(MPU_NS, rnr);
+}
+#endif
+
+/** Configure the given MPU region of the given MPU.
+* \param mpu Pointer to MPU to be used.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rlar Value for RLAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar)
+{
+  mpu->RNR = rnr;
+  mpu->RBAR = rbar;
+  mpu->RLAR = rlar;
+}
+
+/** Configure the given MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rlar Value for RLAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar)
+{
+  ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar);
+}
+
+#ifdef MPU_NS
+/** Configure the given Non-secure MPU region.
+* \param rnr Region number to be configured.
+* \param rbar Value for RBAR register.
+* \param rlar Value for RLAR register.
+*/   
+__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar)
+{
+  ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar);  
+}
+#endif
+
+/** Memcopy with strictly ordered memory access, e.g. for register targets.
+* \param dst Destination data is copied to.
+* \param src Source data is copied from.
+* \param len Amount of data words to be copied.
+*/
+__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
+{
+  uint32_t i;
+  for (i = 0U; i < len; ++i) 
+  {
+    dst[i] = src[i];
+  }
+}
+
+/** Load the given number of MPU regions from a table to the given MPU.
+* \param mpu Pointer to the MPU registers to be used.
+* \param rnr First region number to be configured.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 
+{
+  const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
+  if (cnt == 1U) {
+    mpu->RNR = rnr;
+    ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize);
+  } else {
+    uint32_t rnrBase   = rnr & ~(MPU_TYPE_RALIASES-1U);
+    uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES;
+    
+    mpu->RNR = rnrBase;
+    while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) {
+      uint32_t c = MPU_TYPE_RALIASES - rnrOffset;
+      ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize);
+      table += c;
+      cnt -= c;
+      rnrOffset = 0U;
+      rnrBase += MPU_TYPE_RALIASES;
+      mpu->RNR = rnrBase;
+    }
+    
+    ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize);
+  }
+}
+
+/** Load the given number of MPU regions from a table.
+* \param rnr First region number to be configured.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 
+{
+  ARM_MPU_LoadEx(MPU, rnr, table, cnt);
+}
+
+#ifdef MPU_NS
+/** Load the given number of MPU regions from a table to the Non-secure MPU.
+* \param rnr First region number to be configured.
+* \param table Pointer to the MPU configuration table.
+* \param cnt Amount of regions to be configured.
+*/
+__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) 
+{
+  ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt);
+}
+#endif
+
+#endif
+

FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/board/board.c

@@ -0,0 +1,227 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "board.h"
+#include <stdint.h>
+#include "clock_config.h"
+#include "fsl_common.h"
+#include "fsl_debug_console.h"
+#include "fsl_emc.h"
+#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
+#include "fsl_i2c.h"
+#endif /* SDK_I2C_BASED_COMPONENT_USED */
+#if defined BOARD_USE_CODEC
+#include "fsl_wm8904.h"
+#endif
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* The SDRAM timing. */
+
+#define W9812G6JB6I
+
+#ifdef MTL48LC8M16A2B
+#define SDRAM_REFRESHPERIOD_NS (64 * 1000000 / 4096) /* 4096 rows/ 64ms */
+#define SDRAM_TRP_NS (18u)
+#define SDRAM_TRAS_NS (42u)
+#define SDRAM_TSREX_NS (67u)
+#define SDRAM_TAPR_NS (18u)
+#define SDRAM_TWRDELT_NS (6u)
+#define SDRAM_TRC_NS (60u)
+#define SDRAM_RFC_NS (60u)
+#define SDRAM_XSR_NS (67u)
+#define SDRAM_RRD_NS (12u)
+#define SDRAM_MRD_NCLK (2u)
+#define SDRAM_RAS_NCLK (2u)
+#define SDRAM_MODEREG_VALUE (0x23u)
+#define SDRAM_DEV_MEMORYMAP (0x09u) /* 128Mbits (8M*16, 4banks, 12 rows, 9 columns)*/
+#endif
+
+#ifdef W9812G6JB6I
+#define SDRAM_REFRESHPERIOD_NS (64 * 1000000 / 4096) /* 4096 rows/ 64ms */
+#define SDRAM_TRP_NS (20u)
+#define SDRAM_TRAS_NS (42u)
+#define SDRAM_TSREX_NS (72u)
+#define SDRAM_TAPR_NS (18u)
+#define SDRAM_TWRDELT_NS (12u)
+#define SDRAM_TRC_NS (60u)
+#define SDRAM_RFC_NS (60u)
+#define SDRAM_XSR_NS (67u)
+#define SDRAM_RRD_NS (12u)
+#define SDRAM_MRD_NCLK (2u)
+#define SDRAM_RAS_NCLK (2u)
+#define SDRAM_MODEREG_VALUE (0x23u)
+#define SDRAM_DEV_MEMORYMAP (0x09u) /* 128Mbits (8M*16, 4banks, 12 rows, 9 columns)*/
+#endif
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/* Clock rate on the CLKIN pin */
+const uint32_t ExtClockIn = BOARD_EXTCLKINRATE;
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/* Initialize debug console. */
+status_t BOARD_InitDebugConsole(void)
+{
+#if ((SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK) || defined(SDK_DEBUGCONSOLE_UART))
+    status_t result;
+    uint8_t instance = BOARD_DEBUG_UART_INSTANCE;
+
+#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))
+    if (BOARD_DEBUG_UART_TYPE == kSerialPort_UsbCdc)
+    {
+        instance = kSerialManager_UsbControllerLpcIp3511Hs0;
+    }
+#endif
+
+    /* attach 12 MHz clock to FLEXCOMM0 (debug console) */
+    CLOCK_AttachClk(BOARD_DEBUG_UART_CLK_ATTACH);
+    RESET_PeripheralReset(BOARD_DEBUG_UART_RST);
+    result = DbgConsole_Init(instance, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, BOARD_DEBUG_UART_CLK_FREQ);
+    assert(kStatus_Success == result);
+    return result;
+#else
+    return kStatus_Success;
+#endif
+}
+
+/* Initialize the external memory. */
+void BOARD_InitSDRAM(void)
+{
+    uint32_t emcFreq;
+    emc_basic_config_t basicConfig;
+    emc_dynamic_timing_config_t dynTiming;
+    emc_dynamic_chip_config_t dynChipConfig;
+
+    emcFreq = CLOCK_GetEmcClkFreq();
+    assert(emcFreq != 0); /* Check the clock of emc */
+    /* Basic configuration. */
+    basicConfig.endian   = kEMC_LittleEndian;
+    basicConfig.fbClkSrc = kEMC_IntloopbackEmcclk;
+    /* EMC Clock = CPU FREQ/2 here can fit CPU freq from 12M ~ 180M.
+     * If you change the divide to 0 and EMC clock is larger than 100M
+     * please take refer to emc.dox to adjust EMC clock delay.
+     */
+    basicConfig.emcClkDiv = 1;
+    /* Dynamic memory timing configuration. */
+    dynTiming.readConfig            = kEMC_Cmddelay;
+    dynTiming.refreshPeriod_Nanosec = SDRAM_REFRESHPERIOD_NS;
+    dynTiming.tRp_Ns                = SDRAM_TRP_NS;
+    dynTiming.tRas_Ns               = SDRAM_TRAS_NS;
+    dynTiming.tSrex_Ns              = SDRAM_TSREX_NS;
+    dynTiming.tApr_Ns               = SDRAM_TAPR_NS;
+    dynTiming.tWr_Ns                = (1000000000 / emcFreq + SDRAM_TWRDELT_NS); /* one clk + 6ns */
+    dynTiming.tDal_Ns               = dynTiming.tWr_Ns + dynTiming.tRp_Ns;
+    dynTiming.tRc_Ns                = SDRAM_TRC_NS;
+    dynTiming.tRfc_Ns               = SDRAM_RFC_NS;
+    dynTiming.tXsr_Ns               = SDRAM_XSR_NS;
+    dynTiming.tRrd_Ns               = SDRAM_RRD_NS;
+    dynTiming.tMrd_Nclk             = SDRAM_MRD_NCLK;
+    /* Dynamic memory chip specific configuration: Chip 0 - W9812G6JB-6I */
+    dynChipConfig.chipIndex       = 0;
+    dynChipConfig.dynamicDevice   = kEMC_Sdram;
+    dynChipConfig.rAS_Nclk        = SDRAM_RAS_NCLK;
+    dynChipConfig.sdramModeReg    = SDRAM_MODEREG_VALUE;
+    dynChipConfig.sdramExtModeReg = 0; /* it has no use for normal sdram */
+    dynChipConfig.devAddrMap      = SDRAM_DEV_MEMORYMAP;
+    /* EMC Basic configuration. */
+    EMC_Init(EMC, &basicConfig);
+    /* EMC Dynamc memory configuration. */
+    EMC_DynamicMemInit(EMC, &dynTiming, &dynChipConfig, 1);
+}
+#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
+void BOARD_I2C_Init(I2C_Type *base, uint32_t clkSrc_Hz)
+{
+    i2c_master_config_t i2cConfig = {0};
+
+    I2C_MasterGetDefaultConfig(&i2cConfig);
+    I2C_MasterInit(base, &i2cConfig, clkSrc_Hz);
+}
+
+status_t BOARD_I2C_Send(I2C_Type *base,
+                        uint8_t deviceAddress,
+                        uint32_t subAddress,
+                        uint8_t subaddressSize,
+                        uint8_t *txBuff,
+                        uint8_t txBuffSize)
+{
+    i2c_master_transfer_t masterXfer;
+
+    /* Prepare transfer structure. */
+    masterXfer.slaveAddress   = deviceAddress;
+    masterXfer.direction      = kI2C_Write;
+    masterXfer.subaddress     = subAddress;
+    masterXfer.subaddressSize = subaddressSize;
+    masterXfer.data           = txBuff;
+    masterXfer.dataSize       = txBuffSize;
+    masterXfer.flags          = kI2C_TransferDefaultFlag;
+
+    return I2C_MasterTransferBlocking(base, &masterXfer);
+}
+
+status_t BOARD_I2C_Receive(I2C_Type *base,
+                           uint8_t deviceAddress,
+                           uint32_t subAddress,
+                           uint8_t subaddressSize,
+                           uint8_t *rxBuff,
+                           uint8_t rxBuffSize)
+{
+    i2c_master_transfer_t masterXfer;
+
+    /* Prepare transfer structure. */
+    masterXfer.slaveAddress   = deviceAddress;
+    masterXfer.subaddress     = subAddress;
+    masterXfer.subaddressSize = subaddressSize;
+    masterXfer.data           = rxBuff;
+    masterXfer.dataSize       = rxBuffSize;
+    masterXfer.direction      = kI2C_Read;
+    masterXfer.flags          = kI2C_TransferDefaultFlag;
+
+    return I2C_MasterTransferBlocking(base, &masterXfer);
+}
+
+void BOARD_Accel_I2C_Init(void)
+{
+    BOARD_I2C_Init(BOARD_ACCEL_I2C_BASEADDR, BOARD_ACCEL_I2C_CLOCK_FREQ);
+}
+
+status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff)
+{
+    uint8_t data = (uint8_t)txBuff;
+
+    return BOARD_I2C_Send(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, &data, 1);
+}
+
+status_t BOARD_Accel_I2C_Receive(
+    uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
+{
+    return BOARD_I2C_Receive(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, rxBuff, rxBuffSize);
+}
+
+void BOARD_Codec_I2C_Init(void)
+{
+    BOARD_I2C_Init(BOARD_CODEC_I2C_BASEADDR, BOARD_CODEC_I2C_CLOCK_FREQ);
+}
+
+status_t BOARD_Codec_I2C_Send(
+    uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
+{
+    return BOARD_I2C_Send(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
+                          txBuffSize);
+}
+
+status_t BOARD_Codec_I2C_Receive(
+    uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
+{
+    return BOARD_I2C_Receive(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff, rxBuffSize);
+}
+#endif /* SDK_I2C_BASED_COMPONENT_USED */

FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/board/board.h

@@ -0,0 +1,232 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2018 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+#include "clock_config.h"
+#include "fsl_common.h"
+#include "fsl_gpio.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief The board name */
+#define BOARD_NAME "LPC54018-IoT-Module"
+
+#define BOARD_EXTCLKINRATE (0)
+
+/*! @brief The UART to use for debug messages. */
+/* TODO: rename UART to USART */
+#ifndef BOARD_DEBUG_UART_TYPE
+#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
+#endif
+
+#define BOARD_DEBUG_UART_BASEADDR (uint32_t) USART0
+#define BOARD_DEBUG_UART_INSTANCE 0U
+#define BOARD_DEBUG_UART_CLK_FREQ CLOCK_GetFlexCommClkFreq(0U)
+#define BOARD_DEBUG_UART_CLK_ATTACH kFRO12M_to_FLEXCOMM0
+#define BOARD_DEBUG_UART_RST kFC0_RST_SHIFT_RSTn
+#define BOARD_UART_IRQ_HANDLER FLEXCOMM0_IRQHandler
+#define BOARD_UART_IRQ FLEXCOMM0_IRQn
+/* TODO: obsolete */
+#define BOARD_DEBUG_SPI_CLK_FREQ 12000000
+
+#ifndef BOARD_DEBUG_UART_BAUDRATE
+#define BOARD_DEBUG_UART_BAUDRATE 115200
+#endif /* BOARD_DEBUG_UART_BAUDRATE */
+
+#define BOARD_ACCEL_I2C_BASEADDR I2C2
+#define BOARD_ACCEL_I2C_CLOCK_FREQ 12000000
+
+#define BOARD_CODEC_I2C_BASEADDR I2C2
+#define BOARD_CODEC_I2C_INSTANCE 2U
+#define BOARD_CODEC_I2C_CLOCK_FREQ 12000000
+
+/*! @brief The ENET PHY address. */
+#define BOARD_ENET0_PHY_ADDRESS (0x00U) /* Phy address of enet port 0. */
+
+#ifndef BOARD_LED1_GPIO
+#define BOARD_LED1_GPIO GPIO
+#endif
+#define BOARD_LED1_GPIO_PORT 3U
+#ifndef BOARD_LED1_GPIO_PIN
+#define BOARD_LED1_GPIO_PIN 14U
+#endif
+
+#ifndef BOARD_LED2_GPIO
+#define BOARD_LED2_GPIO GPIO
+#endif
+#define BOARD_LED2_GPIO_PORT 3U
+#ifndef BOARD_LED2_GPIO_PIN
+#define BOARD_LED2_GPIO_PIN 3U
+#endif
+#ifndef BOARD_LED3_GPIO
+#define BOARD_LED3_GPIO GPIO
+#endif
+#define BOARD_LED3_GPIO_PORT 3U
+#ifndef BOARD_LED3_GPIO_PIN
+#define BOARD_LED3_GPIO_PIN 13U
+#endif
+
+#ifndef BOARD_SW1_GPIO
+#define BOARD_SW1_GPIO GPIO
+#endif
+#define BOARD_SW1_GPIO_PORT 0U
+#ifndef BOARD_SW1_GPIO_PIN
+#define BOARD_SW1_GPIO_PIN 4U
+#endif
+#define BOARD_SW1_NAME "SW1"
+#define BOARD_SW3_IRQ PIN_INT0_IRQn
+#define BOARD_SW3_IRQ_HANDLER PIN_INT0_IRQHandler
+
+#ifndef BOARD_SW2_GPIO
+#define BOARD_SW2_GPIO GPIO
+#endif
+#define BOARD_SW2_GPIO_PORT 0U
+#ifndef BOARD_SW2_GPIO_PIN
+#define BOARD_SW2_GPIO_PIN 6U
+#endif
+#define BOARD_SW2_NAME "SW2"
+#define BOARD_SW2_IRQ PIN_INT0_IRQn
+#define BOARD_SW2_IRQ_HANDLER PIN_INT0_IRQHandler
+
+#ifndef BOARD_SW3_GPIO
+#define BOARD_SW3_GPIO GPIO
+#endif
+#define BOARD_SW3_GPIO_PORT 0U
+#ifndef BOARD_SW3_GPIO_PIN
+#define BOARD_SW3_GPIO_PIN 5U
+#endif
+#define BOARD_SW3_NAME "SW3"
+#define BOARD_SW3_IRQ PIN_INT0_IRQn
+#define BOARD_SW3_IRQ_HANDLER PIN_INT0_IRQHandler
+#define BOARD_SW3_GPIO_PININT_INDEX 0
+
+#ifndef BOARD_SW4_GPIO
+#define BOARD_SW4_GPIO GPIO
+#endif
+#ifndef BOARD_SW4_GPIO_PORT
+#define BOARD_SW4_GPIO_PORT 0U
+#endif
+#ifndef BOARD_SW4_GPIO_PIN
+#define BOARD_SW4_GPIO_PIN 4U
+#endif
+#define BOARD_SW4_NAME "SW4"
+#define BOARD_SW4_IRQ PIN_INT0_IRQn
+#define BOARD_SW4_IRQ_HANDLER PIN_INT0_IRQHandler
+#define BOARD_SW4_GPIO_PININT_INDEX 0
+
+#ifndef BOARD_SW5_GPIO
+#define BOARD_SW5_GPIO GPIO
+#endif
+#ifndef BOARD_SW5_GPIO_PORT
+#define BOARD_SW5_GPIO_PORT 1U
+#endif
+#ifndef BOARD_SW5_GPIO_PIN
+#define BOARD_SW5_GPIO_PIN 1U
+#endif
+#define BOARD_SW5_NAME "SW5"
+#define BOARD_SW5_IRQ PIN_INT1_IRQn
+#define BOARD_SW5_IRQ_HANDLER PIN_INT1_IRQHandler
+#define BOARD_SW5_GPIO_PININT_INDEX 0
+
+#define BOARD_SDIF_BASEADDR SDIF
+#define BOARD_SDIF_CLK_FREQ CLOCK_GetSdioClkFreq()
+#define BOARD_SDIF_CLK_ATTACH kMAIN_CLK_to_SDIO_CLK
+#define BOARD_SDIF_IRQ SDIO_IRQn
+
+#define BOARD_MMC_VCC_SUPPLY kMMC_VoltageWindows270to360
+#define BOARD_SD_CARD_DETECT_PIN 10
+#define BOARD_SD_CARD_DETECT_PORT 2
+#define BOARD_SD_CARD_DETECT_GPIO GPIO
+#define BOARD_SD_DETECT_TYPE kSDMMCHOST_DetectCardByHostCD
+
+#define BOARD_SDIF_CD_GPIO_INIT()                                                                    \
+    {                                                                                                \
+        CLOCK_EnableClock(kCLOCK_Gpio2);                                                             \
+        GPIO_PinInit(BOARD_SD_CARD_DETECT_GPIO, BOARD_SD_CARD_DETECT_PORT, BOARD_SD_CARD_DETECT_PIN, \
+                     &(gpio_pin_config_t){kGPIO_DigitalInput, 0U});                                  \
+    }
+#define BOARD_SDIF_CD_STATUS() \
+    GPIO_PinRead(BOARD_SD_CARD_DETECT_GPIO, BOARD_SD_CARD_DETECT_PORT, BOARD_SD_CARD_DETECT_PIN)
+
+/* Board led color mapping */
+#define LOGIC_LED_ON 0U
+#define LOGIC_LED_OFF 1U
+
+#define LED1_INIT(output)                                                    \
+    GPIO_PinInit(BOARD_LED1_GPIO, BOARD_LED1_GPIO_PORT, BOARD_LED1_GPIO_PIN, \
+                 &(gpio_pin_config_t){kGPIO_DigitalOutput, (output)}) /*!< Enable target LED1 */
+#define LED1_ON() \
+    GPIO_PortClear(BOARD_LED1_GPIO, BOARD_LED1_GPIO_PORT, 1U << BOARD_LED1_GPIO_PIN) /*!< Turn on target LED1 */
+#define LED1_OFF() \
+    GPIO_PortSet(BOARD_LED1_GPIO, BOARD_LED1_GPIO_PORT, 1U << BOARD_LED1_GPIO_PIN) /*!< Turn off target LED1 */
+#define LED1_TOGGLE() \
+    GPIO_PortToggle(BOARD_LED1_GPIO, BOARD_LED1_GPIO_PORT, 1U << BOARD_LED1_GPIO_PIN) /*!< Toggle on target LED1 */
+#define LED2_INIT(output)                                                    \
+    GPIO_PinInit(BOARD_LED2_GPIO, BOARD_LED2_GPIO_PORT, BOARD_LED2_GPIO_PIN, \
+                 &(gpio_pin_config_t){kGPIO_DigitalOutput, (output)}) /*!< Enable target LED2 */
+#define LED2_ON() \
+    GPIO_PortClear(BOARD_LED2_GPIO, BOARD_LED2_GPIO_PORT, 1U << BOARD_LED2_GPIO_PIN) /*!< Turn on target LED2 */
+#define LED2_OFF() \
+    GPIO_PortSet(BOARD_LED2_GPIO, BOARD_LED2_GPIO_PORT, 1U << BOARD_LED2_GPIO_PIN) /*!< Turn off target LED2 */
+#define LED2_TOGGLE() \
+    GPIO_PortToggle(BOARD_LED2_GPIO, BOARD_LED2_GPIO_PORT, 1U << BOARD_LED2_GPIO_PIN) /*!< Toggle on target LED2 */
+
+#define LED3_INIT(output)                                                    \
+    GPIO_PinInit(BOARD_LED3_GPIO, BOARD_LED3_GPIO_PORT, BOARD_LED3_GPIO_PIN, \
+                 &(gpio_pin_config_t){kGPIO_DigitalOutput, (output)}) /*!< Enable target LED3 */
+#define LED3_ON() \
+    GPIO_PortClear(BOARD_LED3_GPIO, BOARD_LED3_GPIO_PORT, 1U << BOARD_LED3_GPIO_PIN) /*!< Turn on target LED3 */
+#define LED3_OFF() \
+    GPIO_PortSet(BOARD_LED3_GPIO, BOARD_LED3_GPIO_PORT, 1U << BOARD_LED3_GPIO_PIN) /*!< Turn off target LED3 */
+#define LED3_TOGGLE() \
+    GPIO_PortToggle(BOARD_LED3_GPIO, BOARD_LED3_GPIO_PORT, 1U << BOARD_LED3_GPIO_PIN) /*!< Toggle on target LED3 */
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+status_t BOARD_InitDebugConsole(void);
+void BOARD_InitSDRAM(void);
+#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
+void BOARD_I2C_Init(I2C_Type *base, uint32_t clkSrc_Hz);
+status_t BOARD_I2C_Send(I2C_Type *base,
+                        uint8_t deviceAddress,
+                        uint32_t subAddress,
+                        uint8_t subaddressSize,
+                        uint8_t *txBuff,
+                        uint8_t txBuffSize);
+status_t BOARD_I2C_Receive(I2C_Type *base,
+                           uint8_t deviceAddress,
+                           uint32_t subAddress,
+                           uint8_t subaddressSize,
+                           uint8_t *rxBuff,
+                           uint8_t rxBuffSize);
+void BOARD_Accel_I2C_Init(void);
+status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff);
+status_t BOARD_Accel_I2C_Receive(
+    uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
+void BOARD_Codec_I2C_Init(void);
+status_t BOARD_Codec_I2C_Send(
+    uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize);
+status_t BOARD_Codec_I2C_Receive(
+    uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
+#endif /* SDK_I2C_BASED_COMPONENT_USED */
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+#endif /* _BOARD_H_ */

FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/board/clock_config.c

@@ -0,0 +1,269 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017,2019 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+/*
+ * How to set up clock using clock driver functions:
+ *
+ * 1. Setup clock sources.
+ *
+ * 2. Setup voltage for the fastest of the clock outputs
+ *
+ * 3. Set up wait states of the flash.
+ *
+ * 4. Set up all dividers.
+ *
+ * 5. Set up all selectors to provide selected clocks.
+ */
+
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Clocks v7.0
+processor: LPC54018
+package_id: LPC54018JET180
+mcu_data: ksdk2_0
+processor_version: 0.7.1
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+#include "fsl_power.h"
+#include "fsl_clock.h"
+#include "clock_config.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/* System clock frequency. */
+extern uint32_t SystemCoreClock;
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+void BOARD_InitBootClocks(void)
+{
+    BOARD_BootClockPLL180M();
+}
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockFRO12M **********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockFRO12M
+outputs:
+- {id: FRO12M_clock.outFreq, value: 12 MHz}
+- {id: FROHF_clock.outFreq, value: 48 MHz}
+- {id: MAIN_clock.outFreq, value: 12 MHz}
+- {id: System_clock.outFreq, value: 12 MHz}
+settings:
+- {id: SYSCON.EMCCLKDIV.scale, value: '1', locked: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+void BOARD_BootClockFRO12M(void)
+{
+    /*!< Set up the clock sources */
+    /*!< Set up FRO */
+    POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on  */
+    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without
+                                             accidentally being below the voltage for current speed */
+    /*!< Need to make sure ROM and OTP has power(PDRUNCFG0[17,29]= 0U)
+         before calling this API since this API is implemented in ROM code */
+    CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */
+    POWER_SetVoltageForFreq(
+        12000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
+
+    /*!< Set up dividers */
+    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Reset divider counter and set divider to value 1 */
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO12M */
+    /* Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK;
+}
+
+/*******************************************************************************
+ ******************* Configuration BOARD_BootClockFROHF48M *********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockFROHF48M
+outputs:
+- {id: FRO12M_clock.outFreq, value: 12 MHz}
+- {id: FROHF_clock.outFreq, value: 48 MHz}
+- {id: MAIN_clock.outFreq, value: 48 MHz}
+- {id: System_clock.outFreq, value: 48 MHz}
+settings:
+- {id: SYSCON.MAINCLKSELA.sel, value: SYSCON.fro_hf}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockFROHF48M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockFROHF48M configuration
+ ******************************************************************************/
+void BOARD_BootClockFROHF48M(void)
+{
+    /*!< Set up the clock sources */
+    /*!< Set up FRO */
+    POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on  */
+    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without
+                                             accidentally being below the voltage for current speed */
+    POWER_SetVoltageForFreq(
+        48000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
+    /*!< Need to make sure ROM and OTP has power(PDRUNCFG0[17,29]= 0U)
+         before calling this API since this API is implemented in ROM code */
+    CLOCK_SetupFROClocking(48000000U); /*!< Set up high frequency FRO output to selected frequency */
+
+    /*!< Set up dividers */
+    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Reset divider counter and set divider to value 1 */
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+    CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */
+    /* Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKFROHF48M_CORE_CLOCK;
+}
+
+/*******************************************************************************
+ ******************* Configuration BOARD_BootClockFROHF96M *********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockFROHF96M
+outputs:
+- {id: FRO12M_clock.outFreq, value: 12 MHz}
+- {id: FROHF_clock.outFreq, value: 96 MHz}
+- {id: MAIN_clock.outFreq, value: 96 MHz}
+- {id: System_clock.outFreq, value: 96 MHz}
+settings:
+- {id: SYSCON.MAINCLKSELA.sel, value: SYSCON.fro_hf}
+sources:
+- {id: SYSCON.fro_hf.outFreq, value: 96 MHz}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockFROHF96M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockFROHF96M configuration
+ ******************************************************************************/
+void BOARD_BootClockFROHF96M(void)
+{
+    /*!< Set up the clock sources */
+    /*!< Set up FRO */
+    POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on  */
+    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without
+                                             accidentally being below the voltage for current speed */
+    POWER_SetVoltageForFreq(
+        96000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
+    /*!< Need to make sure ROM and OTP has power(PDRUNCFG0[17,29]= 0U)
+         before calling this API since this API is implemented in ROM code */
+    CLOCK_SetupFROClocking(96000000U); /*!< Set up high frequency FRO output to selected frequency */
+
+    /*!< Set up dividers */
+    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Reset divider counter and set divider to value 1 */
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+    CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */
+    /* Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK;
+}
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockPLL180M *********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockPLL180M
+called_from_default_init: true
+outputs:
+- {id: FRO12M_clock.outFreq, value: 12 MHz}
+- {id: FROHF_clock.outFreq, value: 96 MHz}
+- {id: MAIN_clock.outFreq, value: 180 MHz}
+- {id: SYSPLL_clock.outFreq, value: 180 MHz}
+- {id: System_clock.outFreq, value: 180 MHz}
+- {id: USB0_clock.outFreq, value: 96 MHz}
+settings:
+- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL_BYPASS}
+- {id: SYSCON.M_MULT.scale, value: '30', locked: true}
+- {id: SYSCON.N_DIV.scale, value: '1', locked: true}
+- {id: SYSCON.PDEC.scale, value: '2', locked: true}
+- {id: SYSCON.USB0CLKSEL.sel, value: SYSCON.fro_hf}
+- {id: SYSCON_PDRUNCFG0_PDEN_SYS_PLL_CFG, value: Power_up}
+sources:
+- {id: SYSCON._clk_in.outFreq, value: 12 MHz, enabled: true}
+- {id: SYSCON.fro_hf.outFreq, value: 96 MHz}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockPLL180M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockPLL180M configuration
+ ******************************************************************************/
+void BOARD_BootClockPLL180M(void)
+{
+    /*!< Set up the clock sources */
+    /*!< Set up FRO */
+    POWER_DisablePD(kPDRUNCFG_PD_FRO_EN);  /*!< Ensure FRO is on  */
+    CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);  /*!< Switch to FRO 12MHz first to ensure we can change voltage without
+                                              accidentally  being below the voltage for current speed */
+    POWER_DisablePD(kPDRUNCFG_PD_SYS_OSC); /*!< Enable System Oscillator Power */
+    SYSCON->SYSOSCCTRL = ((SYSCON->SYSOSCCTRL & ~SYSCON_SYSOSCCTRL_FREQRANGE_MASK) |
+                          SYSCON_SYSOSCCTRL_FREQRANGE(0U)); /*!< Set system oscillator range */
+    POWER_SetVoltageForFreq(
+        180000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
+    /*!< Set up SYS PLL */
+    const pll_setup_t pllSetup = {
+        .pllctrl = SYSCON_SYSPLLCTRL_SELI(32U) | SYSCON_SYSPLLCTRL_SELP(16U) | SYSCON_SYSPLLCTRL_SELR(0U),
+        .pllmdec = (SYSCON_SYSPLLMDEC_MDEC(8191U)),
+        .pllndec = (SYSCON_SYSPLLNDEC_NDEC(770U)),
+        .pllpdec = (SYSCON_SYSPLLPDEC_PDEC(98U)),
+        .pllRate = 180000000U,
+        .flags   = PLL_SETUPFLAG_WAITLOCK | PLL_SETUPFLAG_POWERUP};
+    CLOCK_AttachClk(kFRO12M_to_SYS_PLL); /*!< Set sys pll clock source*/
+    CLOCK_SetPLLFreq(&pllSetup);         /*!< Configure PLL to the desired value */
+    /*!< Need to make sure ROM and OTP has power(PDRUNCFG0[17,29]= 0U)
+         before calling this API since this API is implemented in ROM code */
+    CLOCK_SetupFROClocking(96000000U); /*!< Set up high frequency FRO output to selected frequency */
+
+    /*!< Set up dividers */
+    CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false);  /*!< Reset divider counter and set divider to value 1 */
+    CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 0U, true);  /*!< Reset USB0CLKDIV divider counter and halt it */
+    CLOCK_SetClkDiv(kCLOCK_DivUsb0Clk, 1U, false); /*!< Set USB0CLKDIV divider to value 1 */
+
+    /*!< Set up clock selectors - Attach clocks to the peripheries */
+    CLOCK_AttachClk(kSYS_PLL_to_MAIN_CLK); /*!< Switch MAIN_CLK to SYS_PLL */
+    CLOCK_AttachClk(kFRO_HF_to_USB0_CLK);  /*!< Switch USB0_CLK to FRO_HF */
+    SYSCON->MAINCLKSELA =
+        ((SYSCON->MAINCLKSELA & ~SYSCON_MAINCLKSELA_SEL_MASK) |
+         SYSCON_MAINCLKSELA_SEL(0U)); /*!< Switch MAINCLKSELA to FRO12M even it is not used for MAINCLKSELB */
+    /* Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKPLL180M_CORE_CLOCK;
+}

FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/board/clock_config.h

@@ -0,0 +1,142 @@
+/*
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017,2019 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define BOARD_XTAL0_CLK_HZ 12000000U /*!< Board xtal0 frequency in Hz */
+#define BOARD_XTAL32K_CLK_HZ 32768U  /*!< Board xtal32K frequency in Hz */
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes default configuration of clocks.
+ *
+ */
+void BOARD_InitBootClocks(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockFRO12M **********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKFRO12M_CORE_CLOCK 12000000U /*!< Core clock frequency:12000000Hz */
+
+/*******************************************************************************
+ * API for BOARD_BootClockFRO12M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockFRO12M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************* Configuration BOARD_BootClockFROHF48M *********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockFROHF48M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKFROHF48M_CORE_CLOCK 48000000U /*!< Core clock frequency:48000000Hz */
+
+/*******************************************************************************
+ * API for BOARD_BootClockFROHF48M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockFROHF48M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************* Configuration BOARD_BootClockFROHF96M *********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockFROHF96M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK 96000000U /*!< Core clock frequency:96000000Hz */
+
+/*******************************************************************************
+ * API for BOARD_BootClockFROHF96M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockFROHF96M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockPLL180M *********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockPLL180M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKPLL180M_CORE_CLOCK 180000000U /*!< Core clock frequency:180000000Hz */
+
+/*******************************************************************************
+ * API for BOARD_BootClockPLL180M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockPLL180M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */

FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/board/pin_mux.c

@@ -0,0 +1,90 @@
+/*
+ * Copyright 2017, NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Pins v3.0
+processor: LPC54018
+package_id: LPC54018JET180
+mcu_data: ksdk2_0
+processor_version: 0.0.0
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+#include "fsl_common.h"
+#include "fsl_iocon.h"
+#include "pin_mux.h"
+
+/*FUNCTION**********************************************************************
+ * 
+ * Function Name : BOARD_InitBootPins
+ * Description   : Calls initialization functions.
+ * 
+ *END**************************************************************************/
+void BOARD_InitBootPins(void) {
+    BOARD_InitPins();
+}
+
+#define IOCON_PIO_DIGITAL_EN        0x0100u   /*!< Enables digital function */
+#define IOCON_PIO_FUNC1               0x01u   /*!< Selects pin function 1 */
+#define IOCON_PIO_INPFILT_OFF       0x0200u   /*!< Input filter disabled */
+#define IOCON_PIO_INV_DI              0x00u   /*!< Input function is not inverted */
+#define IOCON_PIO_MODE_INACT          0x00u   /*!< No addition pin function */
+#define IOCON_PIO_OPENDRAIN_DI        0x00u   /*!< Open drain is disabled */
+#define IOCON_PIO_SLEW_STANDARD       0x00u   /*!< Standard mode, output slew rate control is enabled */
+#define PIN29_IDX                       29u   /*!< Pin number for pin 29 in a port 0 */
+#define PIN30_IDX                       30u   /*!< Pin number for pin 30 in a port 0 */
+#define PORT0_IDX                        0u   /*!< Port index */
+
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitPins:
+- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'}
+- pin_list:
+  - {pin_num: B13, peripheral: FLEXCOMM0, signal: RXD_SDA_MOSI, pin_signal: PIO0_29/FC0_RXD_SDA_MOSI/CTIMER2_MAT3/SCT0_OUT8/TRACEDATA(2), mode: inactive, invert: disabled,
+    glitch_filter: disabled, slew_rate: standard, open_drain: disabled}
+  - {pin_num: A2, peripheral: FLEXCOMM0, signal: TXD_SCL_MISO, pin_signal: PIO0_30/FC0_TXD_SCL_MISO/CTIMER0_MAT0/SCT0_OUT9/TRACEDATA(1), mode: inactive, invert: disabled,
+    glitch_filter: disabled, slew_rate: standard, open_drain: disabled}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : BOARD_InitPins
+ *
+ *END**************************************************************************/
+void BOARD_InitPins(void) { /* Function assigned for the Core #0 (ARM Cortex-M4) */
+  CLOCK_EnableClock(kCLOCK_Iocon);                           /* Enables the clock for the IOCON block. 0 = Disable; 1 = Enable.: 0x01u */
+
+  const uint32_t port0_pin29_config = (
+    IOCON_PIO_FUNC1 |                                        /* Pin is configured as FC0_RXD_SDA_MOSI */
+    IOCON_PIO_MODE_INACT |                                   /* No addition pin function */
+    IOCON_PIO_INV_DI |                                       /* Input function is not inverted */
+    IOCON_PIO_DIGITAL_EN |                                   /* Enables digital function */
+    IOCON_PIO_INPFILT_OFF |                                  /* Input filter disabled */
+    IOCON_PIO_SLEW_STANDARD |                                /* Standard mode, output slew rate control is enabled */
+    IOCON_PIO_OPENDRAIN_DI                                   /* Open drain is disabled */
+  );
+  IOCON_PinMuxSet(IOCON, PORT0_IDX, PIN29_IDX, port0_pin29_config); /* PORT0 PIN29 (coords: B13) is configured as FC0_RXD_SDA_MOSI */
+  const uint32_t port0_pin30_config = (
+    IOCON_PIO_FUNC1 |                                        /* Pin is configured as FC0_TXD_SCL_MISO */
+    IOCON_PIO_MODE_INACT |                                   /* No addition pin function */
+    IOCON_PIO_INV_DI |                                       /* Input function is not inverted */
+    IOCON_PIO_DIGITAL_EN |                                   /* Enables digital function */
+    IOCON_PIO_INPFILT_OFF |                                  /* Input filter disabled */
+    IOCON_PIO_SLEW_STANDARD |                                /* Standard mode, output slew rate control is enabled */
+    IOCON_PIO_OPENDRAIN_DI                                   /* Open drain is disabled */
+  );
+  IOCON_PinMuxSet(IOCON, PORT0_IDX, PIN30_IDX, port0_pin30_config); /* PORT0 PIN30 (coords: A2) is configured as FC0_TXD_SCL_MISO */
+}
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/

FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/board/pin_mux.h

@@ -0,0 +1,61 @@
+/*
+ * Copyright 2017, NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief Direction type  */
+typedef enum _pin_mux_direction
+{
+  kPIN_MUX_DirectionInput = 0U,         /* Input direction */
+  kPIN_MUX_DirectionOutput = 1U,        /* Output direction */
+  kPIN_MUX_DirectionInputOrOutput = 2U  /* Input or output direction */
+} pin_mux_direction_t;
+
+/*!
+ * @addtogroup pin_mux
+ * @{
+ */
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Calls initialization functions.
+ *
+ */
+void BOARD_InitBootPins(void);
+
+/*!
+ *
+ */
+void BOARD_InitPins(void); /* Function assigned for the Cortex-M4F */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* _PIN_MUX_H_ */
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/

FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/component/lists/generic_list.c

@@ -0,0 +1,423 @@
+/*
+ * Copyright 2018-2019 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/*! *********************************************************************************
+*************************************************************************************
+* Include
+*************************************************************************************
+********************************************************************************** */
+#include "fsl_common.h"
+#include "generic_list.h"
+
+static list_status_t LIST_Scan(list_handle_t list, list_element_handle_t newElement)
+{
+    list_element_handle_t element = list->head;
+
+    while (element != NULL)
+    {
+        if (element == newElement)
+        {
+            return kLIST_DuplicateError;
+        }
+        element = element->next;
+    }
+    return kLIST_Ok;
+}
+
+/*! *********************************************************************************
+*************************************************************************************
+* Public functions
+*************************************************************************************
+********************************************************************************** */
+/*! *********************************************************************************
+ * \brief     Initialises the list descriptor.
+ *
+ * \param[in] list - LIST_ handle to init.
+ *            max - Maximum number of elements in list. 0 for unlimited.
+ *
+ * \return void.
+ *
+ * \pre
+ *
+ * \post
+ *
+ * \remarks
+ *
+ ********************************************************************************** */
+void LIST_Init(list_handle_t list, uint32_t max)
+{
+    list->head = NULL;
+    list->tail = NULL;
+    list->max  = (uint16_t)max;
+    list->size = 0;
+}
+
+/*! *********************************************************************************
+ * \brief     Gets the list that contains the given element.
+ *
+ * \param[in] element - Handle of the element.
+ *
+ * \return NULL if element is orphan.
+ *         Handle of the list the element is inserted into.
+ *
+ * \pre
+ *
+ * \post
+ *
+ * \remarks
+ *
+ ********************************************************************************** */
+list_handle_t LIST_GetList(list_element_handle_t element)
+{
+    return element->list;
+}
+
+/*! *********************************************************************************
+ * \brief     Links element to the tail of the list.
+ *
+ * \param[in] list - ID of list to insert into.
+ *            element - element to add
+ *
+ * \return kLIST_Full if list is full.
+ *         kLIST_Ok if insertion was successful.
+ *
+ * \pre
+ *
+ * \post
+ *
+ * \remarks
+ *
+ ********************************************************************************** */
+list_status_t LIST_AddTail(list_handle_t list, list_element_handle_t element)
+{
+    uint32_t regPrimask = DisableGlobalIRQ();
+
+    if ((list->max != 0U) && (list->max == list->size))
+    {
+        EnableGlobalIRQ(regPrimask);
+        return kLIST_Full;
+    }
+
+    if (kLIST_DuplicateError == LIST_Scan(list, element))
+    {
+        EnableGlobalIRQ(regPrimask);
+        return kLIST_DuplicateError;
+    }
+
+    if (list->size == 0U)
+    {
+        list->head = element;
+    }
+    else
+    {
+        list->tail->next = element;
+    }
+    element->prev = list->tail;
+    element->next = NULL;
+    element->list = list;
+    list->tail    = element;
+    list->size++;
+
+    EnableGlobalIRQ(regPrimask);
+    return kLIST_Ok;
+}
+
+/*! *********************************************************************************
+ * \brief     Links element to the head of the list.
+ *
+ * \param[in] list - ID of list to insert into.
+ *            element - element to add
+ *
+ * \return kLIST_Full if list is full.
+ *         kLIST_Ok if insertion was successful.
+ *
+ * \pre
+ *
+ * \post
+ *
+ * \remarks
+ *
+ ********************************************************************************** */
+list_status_t LIST_AddHead(list_handle_t list, list_element_handle_t element)
+{
+    uint32_t regPrimask = DisableGlobalIRQ();
+
+    if ((list->max != 0U) && (list->max == list->size))
+    {
+        EnableGlobalIRQ(regPrimask);
+        return kLIST_Full;
+    }
+
+    if (kLIST_DuplicateError == LIST_Scan(list, element))
+    {
+        EnableGlobalIRQ(regPrimask);
+        return kLIST_DuplicateError;
+    }
+
+    if (list->size == 0U)
+    {
+        list->tail = element;
+    }
+    else
+    {
+        list->head->prev = element;
+    }
+    element->next = list->head;
+    element->prev = NULL;
+    element->list = list;
+    list->head    = element;
+    list->size++;
+
+    EnableGlobalIRQ(regPrimask);
+    return kLIST_Ok;
+}
+
+/*! *********************************************************************************
+ * \brief     Unlinks element from the head of the list.
+ *
+ * \param[in] list - ID of list to remove from.
+ *
+ * \return NULL if list is empty.
+ *         ID of removed element(pointer) if removal was successful.
+ *
+ * \pre
+ *
+ * \post
+ *
+ * \remarks
+ *
+ ********************************************************************************** */
+list_element_handle_t LIST_RemoveHead(list_handle_t list)
+{
+    list_element_handle_t element;
+
+    uint32_t regPrimask = DisableGlobalIRQ();
+
+    if ((NULL == list) || (list->size == 0U))
+    {
+        EnableGlobalIRQ(regPrimask);
+        return NULL; /*LIST_ is empty*/
+    }
+
+    element = list->head;
+    list->size--;
+    if (list->size == 0U)
+    {
+        list->tail = NULL;
+    }
+    else
+    {
+        element->next->prev = NULL;
+    }
+    list->head    = element->next; /*Is NULL if element is head*/
+    element->list = NULL;
+
+    EnableGlobalIRQ(regPrimask);
+    return element;
+}
+
+/*! *********************************************************************************
+ * \brief     Gets head element ID.
+ *
+ * \param[in] list - ID of list.
+ *
+ * \return NULL if list is empty.
+ *         ID of head element if list is not empty.
+ *
+ * \pre
+ *
+ * \post
+ *
+ * \remarks
+ *
+ ********************************************************************************** */
+list_element_handle_t LIST_GetHead(list_handle_t list)
+{
+    return list->head;
+}
+
+/*! *********************************************************************************
+ * \brief     Gets next element ID.
+ *
+ * \param[in] element - ID of the element.
+ *
+ * \return NULL if element is tail.
+ *         ID of next element if exists.
+ *
+ * \pre
+ *
+ * \post
+ *
+ * \remarks
+ *
+ ********************************************************************************** */
+list_element_handle_t LIST_GetNext(list_element_handle_t element)
+{
+    return element->next;
+}
+
+/*! *********************************************************************************
+ * \brief     Gets previous element ID.
+ *
+ * \param[in] element - ID of the element.
+ *
+ * \return NULL if element is head.
+ *         ID of previous element if exists.
+ *
+ * \pre
+ *
+ * \post
+ *
+ * \remarks
+ *
+ ********************************************************************************** */
+list_element_handle_t LIST_GetPrev(list_element_handle_t element)
+{
+    return element->prev;
+}
+
+/*! *********************************************************************************
+ * \brief     Unlinks an element from its list.
+ *
+ * \param[in] element - ID of the element to remove.
+ *
+ * \return kLIST_OrphanElement if element is not part of any list.
+ *         kLIST_Ok if removal was successful.
+ *
+ * \pre
+ *
+ * \post
+ *
+ * \remarks
+ *
+ ********************************************************************************** */
+list_status_t LIST_RemoveElement(list_element_handle_t element)
+{
+    if (element->list == NULL)
+    {
+        return kLIST_OrphanElement; /*Element was previusly removed or never added*/
+    }
+
+    uint32_t regPrimask = DisableGlobalIRQ();
+
+    if (element->prev == NULL) /*Element is head or solo*/
+    {
+        element->list->head = element->next; /*is null if solo*/
+    }
+    if (element->next == NULL) /*Element is tail or solo*/
+    {
+        element->list->tail = element->prev; /*is null if solo*/
+    }
+    if (element->prev != NULL) /*Element is not head*/
+    {
+        element->prev->next = element->next;
+    }
+    if (element->next != NULL) /*Element is not tail*/
+    {
+        element->next->prev = element->prev;
+    }
+    element->list->size--;
+    element->list = NULL;
+
+    EnableGlobalIRQ(regPrimask);
+    return kLIST_Ok;
+}
+
+/*! *********************************************************************************
+ * \brief     Links an element in the previous position relative to a given member
+ *            of a list.
+ *
+ * \param[in] element - ID of a member of a list.
+ *            newElement - new element to insert before the given member.
+ *
+ * \return kLIST_OrphanElement if element is not part of any list.
+ *         kLIST_Full if list is full.
+ *         kLIST_Ok if insertion was successful.
+ *
+ * \pre
+ *
+ * \post
+ *
+ * \remarks
+ *
+ ********************************************************************************** */
+list_status_t LIST_AddPrevElement(list_element_handle_t element, list_element_handle_t newElement)
+{
+    if (element->list == NULL)
+    {
+        return kLIST_OrphanElement; /*Element was previusly removed or never added*/
+    }
+    uint32_t regPrimask = DisableGlobalIRQ();
+
+    if ((element->list->max != 0U) && (element->list->max == element->list->size))
+    {
+        EnableGlobalIRQ(regPrimask);
+        return kLIST_Full;
+    }
+
+    if (kLIST_DuplicateError == LIST_Scan(element->list, newElement))
+    {
+        EnableGlobalIRQ(regPrimask);
+        return kLIST_DuplicateError;
+    }
+
+    if (element->prev == NULL) /*Element is list head*/
+    {
+        element->list->head = newElement;
+    }
+    else
+    {
+        element->prev->next = newElement;
+    }
+    newElement->list = element->list;
+    element->list->size++;
+    newElement->next = element;
+    newElement->prev = element->prev;
+    element->prev    = newElement;
+
+    EnableGlobalIRQ(regPrimask);
+    return kLIST_Ok;
+}
+
+/*! *********************************************************************************
+ * \brief     Gets the current size of a list.
+ *
+ * \param[in] list - ID of the list.
+ *
+ * \return Current size of the list.
+ *
+ * \pre
+ *
+ * \post
+ *
+ * \remarks
+ *
+ ********************************************************************************** */
+uint32_t LIST_GetSize(list_handle_t list)
+{
+    return list->size;
+}
+
+/*! *********************************************************************************
+ * \brief     Gets the number of free places in the list.
+ *
+ * \param[in] list - ID of the list.
+ *
+ * \return Available size of the list.
+ *
+ * \pre
+ *
+ * \post
+ *
+ * \remarks
+ *
+ ********************************************************************************** */
+uint32_t LIST_GetAvailableSize(list_handle_t list)
+{
+    return ((uint32_t)list->max - (uint32_t)list->size);
+}

FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/component/lists/generic_list.h

@@ -0,0 +1,191 @@
+/*
+ * Copyright 2018-2019 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _GENERIC_LIST_H_
+#define _GENERIC_LIST_H_
+
+/*!
+ * @addtogroup GenericList
+ * @{
+ */
+
+/*!*********************************************************************************
+*************************************************************************************
+* Include
+*************************************************************************************
+********************************************************************************** */
+
+/*! *********************************************************************************
+*************************************************************************************
+* Public macro definitions
+*************************************************************************************
+********************************************************************************** */
+
+/*! *********************************************************************************
+*************************************************************************************
+* Public type definitions
+*************************************************************************************
+********************************************************************************** */
+/*! @brief The list status */
+typedef enum _list_status
+{
+    kLIST_Ok             = kStatus_Success,                   /*!< Success */
+    kLIST_DuplicateError = MAKE_STATUS(kStatusGroup_LIST, 1), /*!< Duplicate Error */
+    kLIST_Full           = MAKE_STATUS(kStatusGroup_LIST, 2), /*!< FULL */
+    kLIST_Empty          = MAKE_STATUS(kStatusGroup_LIST, 3), /*!< Empty */
+    kLIST_OrphanElement  = MAKE_STATUS(kStatusGroup_LIST, 4), /*!< Orphan Element */
+} list_status_t;
+
+/*! @brief The list structure*/
+typedef struct list_label
+{
+    struct list_element_tag *head; /*!< list head */
+    struct list_element_tag *tail; /*!< list tail */
+    uint16_t size;                 /*!< list size */
+    uint16_t max;                  /*!< list max number of elements */
+} list_label_t, *list_handle_t;
+
+/*! @brief The list element*/
+typedef struct list_element_tag
+{
+    struct list_element_tag *next; /*!< next list element   */
+    struct list_element_tag *prev; /*!< previous list element */
+    struct list_label *list;       /*!< pointer to the list */
+} list_element_t, *list_element_handle_t;
+
+/*! *********************************************************************************
+*************************************************************************************
+* Public prototypes
+*************************************************************************************
+********************************************************************************** */
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* _cplusplus */
+/*!
+ * @brief Initialize the list.
+ *
+ * This function initialize the list.
+ *
+ * @param list - List handle to initialize.
+ * @param max - Maximum number of elements in list. 0 for unlimited.
+ */
+void LIST_Init(list_handle_t list, uint32_t max);
+
+/*!
+ * @brief Gets the list that contains the given element.
+ *
+ *
+ * @param element - Handle of the element.
+ * @retval NULL if element is orphan, Handle of the list the element is inserted into.
+ */
+list_handle_t LIST_GetList(list_element_handle_t element);
+
+/*!
+ * @brief Links element to the head of the list.
+ *
+ * @param list - Handle of the list.
+ * @param element - Handle of the element.
+ * @retval kLIST_Full if list is full, kLIST_Ok if insertion was successful.
+ */
+list_status_t LIST_AddHead(list_handle_t list, list_element_handle_t element);
+
+/*!
+ * @brief Links element to the tail of the list.
+ *
+ * @param list - Handle of the list.
+ * @param element - Handle of the element.
+ * @retval kLIST_Full if list is full, kLIST_Ok if insertion was successful.
+ */
+list_status_t LIST_AddTail(list_handle_t list, list_element_handle_t element);
+
+/*!
+ * @brief Unlinks element from the head of the list.
+ *
+ * @param list - Handle of the list.
+ *
+ * @retval NULL if list is empty, handle of removed element(pointer) if removal was successful.
+ */
+list_element_handle_t LIST_RemoveHead(list_handle_t list);
+
+/*!
+ * @brief Gets head element handle.
+ *
+ * @param list - Handle of the list.
+ *
+ * @retval NULL if list is empty, handle of removed element(pointer) if removal was successful.
+ */
+list_element_handle_t LIST_GetHead(list_handle_t list);
+
+/*!
+ * @brief Gets next element handle for given element handle.
+ *
+ * @param element - Handle of the element.
+ *
+ * @retval NULL if list is empty, handle of removed element(pointer) if removal was successful.
+ */
+list_element_handle_t LIST_GetNext(list_element_handle_t element);
+
+/*!
+ * @brief Gets previous element handle for given element handle.
+ *
+ * @param element - Handle of the element.
+ *
+ * @retval NULL if list is empty, handle of removed element(pointer) if removal was successful.
+ */
+list_element_handle_t LIST_GetPrev(list_element_handle_t element);
+
+/*!
+ * @brief Unlinks an element from its list.
+ *
+ * @param element - Handle of the element.
+ *
+ * @retval kLIST_OrphanElement if element is not part of any list.
+ * @retval kLIST_Ok if removal was successful.
+ */
+list_status_t LIST_RemoveElement(list_element_handle_t element);
+
+/*!
+ * @brief Links an element in the previous position relative to a given member of a list.
+ *
+ * @param element - Handle of the element.
+ * @param newElement - New element to insert before the given member.
+ *
+ * @retval kLIST_OrphanElement if element is not part of any list.
+ * @retval kLIST_Ok if removal was successful.
+ */
+list_status_t LIST_AddPrevElement(list_element_handle_t element, list_element_handle_t newElement);
+
+/*!
+ * @brief Gets the current size of a list.
+ *
+ * @param list - Handle of the list.
+ *
+ * @retval Current size of the list.
+ */
+uint32_t LIST_GetSize(list_handle_t list);
+
+/*!
+ * @brief Gets the number of free places in the list.
+ *
+ * @param list - Handle of the list.
+ *
+ * @retval Available size of the list.
+ */
+uint32_t LIST_GetAvailableSize(list_handle_t list);
+
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif
+/*! @}*/
+#endif /*_GENERIC_LIST_H_*/

FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/component/serial_manager/serial_manager.h

@@ -0,0 +1,553 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __SERIAL_MANAGER_H__
+#define __SERIAL_MANAGER_H__
+
+/*!
+ * @addtogroup serialmanager
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+/*! @brief Enable or disable serial manager non-blocking mode (1 - enable, 0 - disable) */
+#define SERIAL_MANAGER_NON_BLOCKING_MODE (1U)
+#else
+#ifndef SERIAL_MANAGER_NON_BLOCKING_MODE
+#define SERIAL_MANAGER_NON_BLOCKING_MODE (0U)
+#endif
+#endif
+
+/*! @brief Enable or disable uart port (1 - enable, 0 - disable) */
+#ifndef SERIAL_PORT_TYPE_UART
+#define SERIAL_PORT_TYPE_UART (0U)
+#endif
+
+/*! @brief Enable or disable USB CDC port (1 - enable, 0 - disable) */
+#ifndef SERIAL_PORT_TYPE_USBCDC
+#define SERIAL_PORT_TYPE_USBCDC (0U)
+#endif
+
+/*! @brief Enable or disable SWO port (1 - enable, 0 - disable) */
+#ifndef SERIAL_PORT_TYPE_SWO
+#define SERIAL_PORT_TYPE_SWO (0U)
+#endif
+
+/*! @brief Enable or disable USB CDC virtual port (1 - enable, 0 - disable) */
+#ifndef SERIAL_PORT_TYPE_USBCDC_VIRTUAL
+#define SERIAL_PORT_TYPE_USBCDC_VIRTUAL (0U)
+#endif
+
+/*! @brief Set serial manager write handle size */
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+#define SERIAL_MANAGER_WRITE_HANDLE_SIZE (44U)
+#define SERIAL_MANAGER_READ_HANDLE_SIZE (44U)
+#else
+#define SERIAL_MANAGER_WRITE_HANDLE_SIZE (4U)
+#define SERIAL_MANAGER_READ_HANDLE_SIZE (4U)
+#endif
+
+#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))
+#include "serial_port_uart.h"
+#endif
+
+#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))
+
+#if !(defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+#error The serial manager blocking mode cannot be supported for USB CDC.
+#endif
+
+#include "serial_port_usb.h"
+#endif
+
+#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))
+#include "serial_port_swo.h"
+#endif
+
+#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U))
+
+#if !(defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+#error The serial manager blocking mode cannot be supported for USB CDC.
+#endif
+
+#include "serial_port_usb_virtual.h"
+#endif
+
+#define SERIAL_MANAGER_HANDLE_SIZE_TEMP 0U
+#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))
+
+#if (SERIAL_PORT_UART_HANDLE_SIZE > SERIAL_MANAGER_HANDLE_SIZE_TEMP)
+#undef SERIAL_MANAGER_HANDLE_SIZE_TEMP
+#define SERIAL_MANAGER_HANDLE_SIZE_TEMP SERIAL_PORT_UART_HANDLE_SIZE
+#endif
+
+#endif
+
+#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))
+
+#if (SERIAL_PORT_USB_CDC_HANDLE_SIZE > SERIAL_MANAGER_HANDLE_SIZE_TEMP)
+#undef SERIAL_MANAGER_HANDLE_SIZE_TEMP
+#define SERIAL_MANAGER_HANDLE_SIZE_TEMP SERIAL_PORT_USB_CDC_HANDLE_SIZE
+#endif
+
+#endif
+
+#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))
+
+#if (SERIAL_PORT_SWO_HANDLE_SIZE > SERIAL_MANAGER_HANDLE_SIZE_TEMP)
+#undef SERIAL_MANAGER_HANDLE_SIZE_TEMP
+#define SERIAL_MANAGER_HANDLE_SIZE_TEMP SERIAL_PORT_SWO_HANDLE_SIZE
+#endif
+
+#endif
+
+#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U))
+
+#if (SERIAL_PORT_USB_VIRTUAL_HANDLE_SIZE > SERIAL_MANAGER_HANDLE_SIZE_TEMP)
+#undef SERIAL_MANAGER_HANDLE_SIZE_TEMP
+#define SERIAL_MANAGER_HANDLE_SIZE_TEMP SERIAL_PORT_USB_VIRTUAL_HANDLE_SIZE
+#endif
+
+#endif
+
+/*! @brief SERIAL_PORT_UART_HANDLE_SIZE/SERIAL_PORT_USB_CDC_HANDLE_SIZE + serial manager dedicated size */
+#if ((defined(SERIAL_MANAGER_HANDLE_SIZE_TEMP) && (SERIAL_MANAGER_HANDLE_SIZE_TEMP > 0U)))
+#else
+#error SERIAL_PORT_TYPE_UART, SERIAL_PORT_TYPE_USBCDC, SERIAL_PORT_TYPE_SWO and SERIAL_PORT_TYPE_USBCDC_VIRTUAL should not be cleared at same time.
+#endif
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+#define SERIAL_MANAGER_HANDLE_SIZE (SERIAL_MANAGER_HANDLE_SIZE_TEMP + 120U)
+#else
+#define SERIAL_MANAGER_HANDLE_SIZE (SERIAL_MANAGER_HANDLE_SIZE_TEMP + 12U)
+#endif
+
+#define SERIAL_MANAGER_USE_COMMON_TASK (1U)
+#define SERIAL_MANAGER_TASK_PRIORITY (2U)
+#define SERIAL_MANAGER_TASK_STACK_SIZE (1000U)
+
+typedef void *serial_handle_t;
+typedef void *serial_write_handle_t;
+typedef void *serial_read_handle_t;
+
+/*! @brief serial port type*/
+typedef enum _serial_port_type
+{
+    kSerialPort_Uart = 1U,     /*!< Serial port UART */
+    kSerialPort_UsbCdc,        /*!< Serial port USB CDC */
+    kSerialPort_Swo,           /*!< Serial port SWO */
+    kSerialPort_UsbCdcVirtual, /*!< Serial port USB CDC Virtual */
+} serial_port_type_t;
+
+/*! @brief serial manager config structure*/
+typedef struct _serial_manager_config
+{
+    uint8_t *ringBuffer;     /*!< Ring buffer address, it is used to buffer data received by the hardware.
+                                  Besides, the memory space cannot be free during the lifetime of the serial
+                                  manager module. */
+    uint32_t ringBufferSize; /*!< The size of the ring buffer */
+    serial_port_type_t type; /*!< Serial port type */
+    void *portConfig;        /*!< Serial port configuration */
+} serial_manager_config_t;
+
+/*! @brief serial manager error code*/
+typedef enum _serial_manager_status
+{
+    kStatus_SerialManager_Success = kStatus_Success,                            /*!< Success */
+    kStatus_SerialManager_Error   = MAKE_STATUS(kStatusGroup_SERIALMANAGER, 1), /*!< Failed */
+    kStatus_SerialManager_Busy    = MAKE_STATUS(kStatusGroup_SERIALMANAGER, 2), /*!< Busy */
+    kStatus_SerialManager_Notify  = MAKE_STATUS(kStatusGroup_SERIALMANAGER, 3), /*!< Ring buffer is not empty */
+    kStatus_SerialManager_Canceled =
+        MAKE_STATUS(kStatusGroup_SERIALMANAGER, 4), /*!< the non-blocking request is canceled */
+    kStatus_SerialManager_HandleConflict = MAKE_STATUS(kStatusGroup_SERIALMANAGER, 5), /*!< The handle is opened */
+    kStatus_SerialManager_RingBufferOverflow =
+        MAKE_STATUS(kStatusGroup_SERIALMANAGER, 6), /*!< The ring buffer is overflowed */
+} serial_manager_status_t;
+
+/*! @brief Callback message structure */
+typedef struct _serial_manager_callback_message
+{
+    uint8_t *buffer; /*!< Transferred buffer */
+    uint32_t length; /*!< Transferred data length */
+} serial_manager_callback_message_t;
+
+/*! @brief callback function */
+typedef void (*serial_manager_callback_t)(void *callbackParam,
+                                          serial_manager_callback_message_t *message,
+                                          serial_manager_status_t status);
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* _cplusplus */
+
+/*!
+ * @brief Initializes a serial manager module with the serial manager handle and the user configuration structure.
+ *
+ * This function configures the Serial Manager module with user-defined settings. The user can configure the
+ * configuration
+ * structure. The parameter serialHandle is a pointer to point to a memory space of size #SERIAL_MANAGER_HANDLE_SIZE
+ * allocated by the caller.
+ * The Serial Manager module supports two types of serial port, UART (includes UART, USART, LPSCI, LPUART, etc) and USB
+ * CDC.
+ * Please refer to #serial_port_type_t for serial port setting. These two types can be set by using
+ * #serial_manager_config_t.
+ *
+ * Example below shows how to use this API to configure the Serial Manager.
+ * For UART,
+ *  @code
+ *   #define SERIAL_MANAGER_RING_BUFFER_SIZE          (256U)
+ *   static uint32_t s_serialHandleBuffer[((SERIAL_MANAGER_HANDLE_SIZE + sizeof(uint32_t) - 1) / sizeof(uitn32_t))];
+ *   static serial_handle_t s_serialHandle = (serial_handle_t)&s_serialHandleBuffer[0];
+ *   static uint8_t s_ringBuffer[SERIAL_MANAGER_RING_BUFFER_SIZE];
+ *
+ *   serial_manager_config_t config;
+ *   serial_port_uart_config_t uartConfig;
+ *   config.type = kSerialPort_Uart;
+ *   config.ringBuffer = &s_ringBuffer[0];
+ *   config.ringBufferSize = SERIAL_MANAGER_RING_BUFFER_SIZE;
+ *   uartConfig.instance = 0;
+ *   uartConfig.clockRate = 24000000;
+ *   uartConfig.baudRate = 115200;
+ *   uartConfig.parityMode = kSerialManager_UartParityDisabled;
+ *   uartConfig.stopBitCount = kSerialManager_UartOneStopBit;
+ *   uartConfig.enableRx = 1;
+ *   uartConfig.enableTx = 1;
+ *   config.portConfig = &uartConfig;
+ *   SerialManager_Init(s_serialHandle, &config);
+ *  @endcode
+ * For USB CDC,
+ *  @code
+ *   #define SERIAL_MANAGER_RING_BUFFER_SIZE          (256U)
+ *   static uint32_t s_serialHandleBuffer[((SERIAL_MANAGER_HANDLE_SIZE + sizeof(uint32_t) - 1) / sizeof(uitn32_t))];
+ *   static serial_handle_t s_serialHandle = (serial_handle_t)&s_serialHandleBuffer[0];
+ *   static uint8_t s_ringBuffer[SERIAL_MANAGER_RING_BUFFER_SIZE];
+ *
+ *   serial_manager_config_t config;
+ *   serial_port_usb_cdc_config_t usbCdcConfig;
+ *   config.type = kSerialPort_UsbCdc;
+ *   config.ringBuffer = &s_ringBuffer[0];
+ *   config.ringBufferSize = SERIAL_MANAGER_RING_BUFFER_SIZE;
+ *   usbCdcConfig.controllerIndex = kSerialManager_UsbControllerKhci0;
+ *   config.portConfig = &usbCdcConfig;
+ *   SerialManager_Init(s_serialHandle, &config);
+ *  @endcode
+ *
+ * @param serialHandle Pointer to point to a memory space of size #SERIAL_MANAGER_HANDLE_SIZE allocated by the caller.
+ * The handle should be 4 byte aligned, because unaligned access does not support on some devices.
+ * @param config Pointer to user-defined configuration structure.
+ * @retval kStatus_SerialManager_Error An error occurred.
+ * @retval kStatus_SerialManager_Success The Serial Manager module initialization succeed.
+ */
+serial_manager_status_t SerialManager_Init(serial_handle_t serialHandle, serial_manager_config_t *config);
+
+/*!
+ * @brief De-initializes the serial manager module instance.
+ *
+ * This function de-initializes the serial manager module instance. If the opened writing or
+ * reading handle is not closed, the function will return kStatus_SerialManager_Busy.
+ *
+ * @param serialHandle The serial manager module handle pointer.
+ * @retval kStatus_SerialManager_Success The serial manager de-initialization succeed.
+ * @retval kStatus_SerialManager_Busy Opened reading or writing handle is not closed.
+ */
+serial_manager_status_t SerialManager_Deinit(serial_handle_t serialHandle);
+
+/*!
+ * @brief Opens a writing handle for the serial manager module.
+ *
+ * This function Opens a writing handle for the serial manager module. If the serial manager needs to
+ * be used in different tasks, the task should open a dedicated write handle for itself by calling
+ * #SerialManager_OpenWriteHandle. Since there can only one buffer for transmission for the writing
+ * handle at the same time, multiple writing handles need to be opened when the multiple transmission
+ * is needed for a task.
+ *
+ * @param serialHandle The serial manager module handle pointer.
+ * The handle should be 4 byte aligned, because unaligned access does not support on some devices.
+ * @param writeHandle The serial manager module writing handle pointer.
+ * The handle should be 4 byte aligned, because unaligned access does not support on some devices.
+ * @retval kStatus_SerialManager_Error An error occurred.
+ * @retval kStatus_SerialManager_HandleConflict The writing handle was opened.
+ * @retval kStatus_SerialManager_Success The writing handle is opened.
+ *
+ * Example below shows how to use this API to write data.
+ * For task 1,
+ *  @code
+ *   static uint32_t s_serialWriteHandleBuffer1[((SERIAL_MANAGER_WRITE_HANDLE_SIZE + sizeof(uint32_t) - 1) /
+ * sizeof(uitn32_t))]; static serial_write_handle_t s_serialWriteHandle1 =
+ * (serial_write_handle_t)&s_serialWriteHandleBuffer1[0]; static uint8_t s_nonBlockingWelcome1[] = "This is non-blocking
+ * writing log for task1!\r\n"; SerialManager_OpenWriteHandle(serialHandle, s_serialWriteHandle1);
+ *   SerialManager_InstallTxCallback(s_serialWriteHandle1, Task1_SerialManagerTxCallback, s_serialWriteHandle1);
+ *   SerialManager_WriteNonBlocking(s_serialWriteHandle1, s_nonBlockingWelcome1, sizeof(s_nonBlockingWelcome1) - 1);
+ *  @endcode
+ * For task 2,
+ *  @code
+ *   static uint32_t s_serialWriteHandleBuffer2[((SERIAL_MANAGER_WRITE_HANDLE_SIZE + sizeof(uint32_t) - 1) /
+ * sizeof(uitn32_t))]; static serial_write_handle_t s_serialWriteHandle2 =
+ * (serial_write_handle_t)&s_serialWriteHandleBuffer2[0]; static uint8_t s_nonBlockingWelcome2[] = "This is non-blocking
+ * writing log for task2!\r\n"; SerialManager_OpenWriteHandle(serialHandle, s_serialWriteHandle2);
+ *   SerialManager_InstallTxCallback(s_serialWriteHandle2, Task2_SerialManagerTxCallback, s_serialWriteHandle2);
+ *   SerialManager_WriteNonBlocking(s_serialWriteHandle2, s_nonBlockingWelcome2, sizeof(s_nonBlockingWelcome2) - 1);
+ *  @endcode
+ */
+serial_manager_status_t SerialManager_OpenWriteHandle(serial_handle_t serialHandle, serial_write_handle_t writeHandle);
+
+/*!
+ * @brief Closes a writing handle for the serial manager module.
+ *
+ * This function Closes a writing handle for the serial manager module.
+ *
+ * @param writeHandle The serial manager module writing handle pointer.
+ * @retval kStatus_SerialManager_Success The writing handle is closed.
+ */
+serial_manager_status_t SerialManager_CloseWriteHandle(serial_write_handle_t writeHandle);
+
+/*!
+ * @brief Opens a reading handle for the serial manager module.
+ *
+ * This function Opens a reading handle for the serial manager module. The reading handle can not be
+ * opened multiple at the same time. The error code kStatus_SerialManager_Busy would be returned when
+ * the previous reading handle is not closed. And There can only be one buffer for receiving for the
+ * reading handle at the same time.
+ *
+ * @param serialHandle The serial manager module handle pointer.
+ * The handle should be 4 byte aligned, because unaligned access does not support on some devices.
+ * @param readHandle The serial manager module reading handle pointer.
+ * The handle should be 4 byte aligned, because unaligned access does not support on some devices.
+ * @retval kStatus_SerialManager_Error An error occurred.
+ * @retval kStatus_SerialManager_Success The reading handle is opened.
+ * @retval kStatus_SerialManager_Busy Previous reading handle is not closed.
+ *
+ * Example below shows how to use this API to read data.
+ *  @code
+ *   static uint32_t s_serialReadHandleBuffer[((SERIAL_MANAGER_READ_HANDLE_SIZE + sizeof(uint32_t) - 1) /
+ * sizeof(uitn32_t))]; static serial_read_handle_t s_serialReadHandle =
+ * (serial_read_handle_t)&s_serialReadHandleBuffer[0]; SerialManager_OpenReadHandle(serialHandle, s_serialReadHandle);
+ *   static uint8_t s_nonBlockingBuffer[64];
+ *   SerialManager_InstallRxCallback(s_serialReadHandle, APP_SerialManagerRxCallback, s_serialReadHandle);
+ *   SerialManager_ReadNonBlocking(s_serialReadHandle, s_nonBlockingBuffer, sizeof(s_nonBlockingBuffer));
+ *  @endcode
+ */
+serial_manager_status_t SerialManager_OpenReadHandle(serial_handle_t serialHandle, serial_read_handle_t readHandle);
+
+/*!
+ * @brief Closes a reading for the serial manager module.
+ *
+ * This function Closes a reading for the serial manager module.
+ *
+ * @param readHandle The serial manager module reading handle pointer.
+ * @retval kStatus_SerialManager_Success The reading handle is closed.
+ */
+serial_manager_status_t SerialManager_CloseReadHandle(serial_read_handle_t readHandle);
+
+/*!
+ * @brief Transmits data with the blocking mode.
+ *
+ * This is a blocking function, which polls the sending queue, waits for the sending queue to be empty.
+ * This function sends data using an interrupt method. The interrupt of the hardware could not be disabled.
+ * And There can only one buffer for transmission for the writing handle at the same time.
+ *
+ * @note The function #SerialManager_WriteBlocking and the function #SerialManager_WriteNonBlocking
+ * cannot be used at the same time.
+ * And, the function #SerialManager_CancelWriting cannot be used to abort the transmission of this function.
+ *
+ * @param writeHandle The serial manager module handle pointer.
+ * @param buffer Start address of the data to write.
+ * @param length Length of the data to write.
+ * @retval kStatus_SerialManager_Success Successfully sent all data.
+ * @retval kStatus_SerialManager_Busy Previous transmission still not finished; data not all sent yet.
+ * @retval kStatus_SerialManager_Error An error occurred.
+ */
+serial_manager_status_t SerialManager_WriteBlocking(serial_write_handle_t writeHandle,
+                                                    uint8_t *buffer,
+                                                    uint32_t length);
+
+/*!
+ * @brief Reads data with the blocking mode.
+ *
+ * This is a blocking function, which polls the receiving buffer, waits for the receiving buffer to be full.
+ * This function receives data using an interrupt method. The interrupt of the hardware could not be disabled.
+ * And There can only one buffer for receiving for the reading handle at the same time.
+ *
+ * @note The function #SerialManager_ReadBlocking and the function #SerialManager_ReadNonBlocking
+ * cannot be used at the same time.
+ * And, the function #SerialManager_CancelReading cannot be used to abort the transmission of this function.
+ *
+ * @param readHandle The serial manager module handle pointer.
+ * @param buffer Start address of the data to store the received data.
+ * @param length The length of the data to be received.
+ * @retval kStatus_SerialManager_Success Successfully received all data.
+ * @retval kStatus_SerialManager_Busy Previous transmission still not finished; data not all received yet.
+ * @retval kStatus_SerialManager_Error An error occurred.
+ */
+serial_manager_status_t SerialManager_ReadBlocking(serial_read_handle_t readHandle, uint8_t *buffer, uint32_t length);
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+/*!
+ * @brief Transmits data with the non-blocking mode.
+ *
+ * This is a non-blocking function, which returns directly without waiting for all data to be sent.
+ * When all data is sent, the module notifies the upper layer through a TX callback function and passes
+ * the status parameter @ref kStatus_SerialManager_Success.
+ * This function sends data using an interrupt method. The interrupt of the hardware could not be disabled.
+ * And There can only one buffer for transmission for the writing handle at the same time.
+ *
+ * @note The function #SerialManager_WriteBlocking and the function #SerialManager_WriteNonBlocking
+ * cannot be used at the same time. And, the TX callback is mandatory before the function could be used.
+ *
+ * @param writeHandle The serial manager module handle pointer.
+ * @param buffer Start address of the data to write.
+ * @param length Length of the data to write.
+ * @retval kStatus_SerialManager_Success Successfully sent all data.
+ * @retval kStatus_SerialManager_Busy Previous transmission still not finished; data not all sent yet.
+ * @retval kStatus_SerialManager_Error An error occurred.
+ */
+serial_manager_status_t SerialManager_WriteNonBlocking(serial_write_handle_t writeHandle,
+                                                       uint8_t *buffer,
+                                                       uint32_t length);
+
+/*!
+ * @brief Reads data with the non-blocking mode.
+ *
+ * This is a non-blocking function, which returns directly without waiting for all data to be received.
+ * When all data is received, the module driver notifies the upper layer
+ * through a RX callback function and passes the status parameter @ref kStatus_SerialManager_Success.
+ * This function receives data using an interrupt method. The interrupt of the hardware could not be disabled.
+ * And There can only one buffer for receiving for the reading handle at the same time.
+ *
+ * @note The function #SerialManager_ReadBlocking and the function #SerialManager_ReadNonBlocking
+ * cannot be used at the same time. And, the RX callback is mandatory before the function could be used.
+ *
+ * @param readHandle The serial manager module handle pointer.
+ * @param buffer Start address of the data to store the received data.
+ * @param length The length of the data to be received.
+ * @retval kStatus_SerialManager_Success Successfully received all data.
+ * @retval kStatus_SerialManager_Busy Previous transmission still not finished; data not all received yet.
+ * @retval kStatus_SerialManager_Error An error occurred.
+ */
+serial_manager_status_t SerialManager_ReadNonBlocking(serial_read_handle_t readHandle,
+                                                      uint8_t *buffer,
+                                                      uint32_t length);
+
+/*!
+ * @brief Tries to read data.
+ *
+ * The function tries to read data from internal ring buffer. If the ring buffer is not empty, the data will be
+ * copied from ring buffer to up layer buffer. The copied length is the minimum of the ring buffer and up layer length.
+ * After the data is copied, the actual data length is passed by the parameter length.
+ * And There can only one buffer for receiving for the reading handle at the same time.
+ *
+ * @param readHandle The serial manager module handle pointer.
+ * @param buffer Start address of the data to store the received data.
+ * @param length The length of the data to be received.
+ * @param receivedLength Length received from the ring buffer directly.
+ * @retval kStatus_SerialManager_Success Successfully received all data.
+ * @retval kStatus_SerialManager_Busy Previous transmission still not finished; data not all received yet.
+ * @retval kStatus_SerialManager_Error An error occurred.
+ */
+serial_manager_status_t SerialManager_TryRead(serial_read_handle_t readHandle,
+                                              uint8_t *buffer,
+                                              uint32_t length,
+                                              uint32_t *receivedLength);
+
+/*!
+ * @brief Cancels unfinished send transmission.
+ *
+ * The function cancels unfinished send transmission. When the transfer is canceled, the module notifies the upper layer
+ * through a TX callback function and passes the status parameter @ref kStatus_SerialManager_Canceled.
+ *
+ * @note The function #SerialManager_CancelWriting cannot be used to abort the transmission of
+ * the function #SerialManager_WriteBlocking.
+ *
+ * @param writeHandle The serial manager module handle pointer.
+ * @retval kStatus_SerialManager_Success Get successfully abort the sending.
+ * @retval kStatus_SerialManager_Error An error occurred.
+ */
+serial_manager_status_t SerialManager_CancelWriting(serial_write_handle_t writeHandle);
+
+/*!
+ * @brief Cancels unfinished receive transmission.
+ *
+ * The function cancels unfinished receive transmission. When the transfer is canceled, the module notifies the upper
+ * layer
+ * through a RX callback function and passes the status parameter @ref kStatus_SerialManager_Canceled.
+ *
+ * @note The function #SerialManager_CancelReading cannot be used to abort the transmission of
+ * the function #SerialManager_ReadBlocking.
+ *
+ * @param readHandle The serial manager module handle pointer.
+ * @retval kStatus_SerialManager_Success Get successfully abort the receiving.
+ * @retval kStatus_SerialManager_Error An error occurred.
+ */
+serial_manager_status_t SerialManager_CancelReading(serial_read_handle_t readHandle);
+
+/*!
+ * @brief Installs a TX callback and callback parameter.
+ *
+ * This function is used to install the TX callback and callback parameter for the serial manager module.
+ * When any status of TX transmission changed, the driver will notify the upper layer by the installed callback
+ * function. And the status is also passed as status parameter when the callback is called.
+ *
+ * @param writeHandle The serial manager module handle pointer.
+ * @param callback The callback function.
+ * @param callbackParam The parameter of the callback function.
+ * @retval kStatus_SerialManager_Success Successfully install the callback.
+ */
+serial_manager_status_t SerialManager_InstallTxCallback(serial_write_handle_t writeHandle,
+                                                        serial_manager_callback_t callback,
+                                                        void *callbackParam);
+
+/*!
+ * @brief Installs a RX callback and callback parameter.
+ *
+ * This function is used to install the RX callback and callback parameter for the serial manager module.
+ * When any status of RX transmission changed, the driver will notify the upper layer by the installed callback
+ * function. And the status is also passed as status parameter when the callback is called.
+ *
+ * @param readHandle The serial manager module handle pointer.
+ * @param callback The callback function.
+ * @param callbackParam The parameter of the callback function.
+ * @retval kStatus_SerialManager_Success Successfully install the callback.
+ */
+serial_manager_status_t SerialManager_InstallRxCallback(serial_read_handle_t readHandle,
+                                                        serial_manager_callback_t callback,
+                                                        void *callbackParam);
+
+#endif
+
+/*!
+ * @brief Prepares to enter low power consumption.
+ *
+ * This function is used to prepare to enter low power consumption.
+ *
+ * @param serialHandle The serial manager module handle pointer.
+ * @retval kStatus_SerialManager_Success Successful operation.
+ */
+serial_manager_status_t SerialManager_EnterLowpower(serial_handle_t serialHandle);
+
+/*!
+ * @brief Restores from low power consumption.
+ *
+ * This function is used to restore from low power consumption.
+ *
+ * @param serialHandle The serial manager module handle pointer.
+ * @retval kStatus_SerialManager_Success Successful operation.
+ */
+serial_manager_status_t SerialManager_ExitLowpower(serial_handle_t serialHandle);
+
+#if defined(__cplusplus)
+}
+#endif
+/*! @} */
+#endif /* __SERIAL_MANAGER_H__ */

FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/component/serial_manager/serial_port_internal.h

@@ -0,0 +1,99 @@
+/*
+ * Copyright 2019 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __SERIAL_PORT_INTERNAL_H__
+#define __SERIAL_PORT_INTERNAL_H__
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* _cplusplus */
+
+#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))
+serial_manager_status_t Serial_UartInit(serial_handle_t serialHandle, void *serialConfig);
+serial_manager_status_t Serial_UartDeinit(serial_handle_t serialHandle);
+serial_manager_status_t Serial_UartWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
+#if !(defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+serial_manager_status_t Serial_UartRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
+#endif
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+serial_manager_status_t Serial_UartCancelWrite(serial_handle_t serialHandle);
+serial_manager_status_t Serial_UartInstallTxCallback(serial_handle_t serialHandle,
+                                                     serial_manager_callback_t callback,
+                                                     void *callbackParam);
+serial_manager_status_t Serial_UartInstallRxCallback(serial_handle_t serialHandle,
+                                                     serial_manager_callback_t callback,
+                                                     void *callbackParam);
+void Serial_UartIsrFunction(serial_handle_t serialHandle);
+#endif
+serial_manager_status_t Serial_UartEnterLowpower(serial_handle_t serialHandle);
+serial_manager_status_t Serial_UartExitLowpower(serial_handle_t serialHandle);
+#endif
+
+#if (defined(SERIAL_PORT_TYPE_USBCDC) && (SERIAL_PORT_TYPE_USBCDC > 0U))
+serial_manager_status_t Serial_UsbCdcInit(serial_handle_t serialHandle, void *config);
+serial_manager_status_t Serial_UsbCdcDeinit(serial_handle_t serialHandle);
+serial_manager_status_t Serial_UsbCdcWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
+serial_manager_status_t Serial_UsbCdcRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
+serial_manager_status_t Serial_UsbCdcCancelWrite(serial_handle_t serialHandle);
+serial_manager_status_t Serial_UsbCdcInstallTxCallback(serial_handle_t serialHandle,
+                                                       serial_manager_callback_t callback,
+                                                       void *callbackParam);
+serial_manager_status_t Serial_UsbCdcInstallRxCallback(serial_handle_t serialHandle,
+                                                       serial_manager_callback_t callback,
+                                                       void *callbackParam);
+void Serial_UsbCdcIsrFunction(serial_handle_t serialHandle);
+#endif
+
+#if (defined(SERIAL_PORT_TYPE_SWO) && (SERIAL_PORT_TYPE_SWO > 0U))
+serial_manager_status_t Serial_SwoInit(serial_handle_t serialHandle, void *config);
+serial_manager_status_t Serial_SwoDeinit(serial_handle_t serialHandle);
+serial_manager_status_t Serial_SwoWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
+#if !(defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+serial_manager_status_t Serial_SwoRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
+#endif
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+serial_manager_status_t Serial_SwoCancelWrite(serial_handle_t serialHandle);
+serial_manager_status_t Serial_SwoInstallTxCallback(serial_handle_t serialHandle,
+                                                    serial_manager_callback_t callback,
+                                                    void *callbackParam);
+serial_manager_status_t Serial_SwoInstallRxCallback(serial_handle_t serialHandle,
+                                                    serial_manager_callback_t callback,
+                                                    void *callbackParam);
+void Serial_SwoIsrFunction(serial_handle_t serialHandle);
+#endif
+#endif
+
+#if (defined(SERIAL_PORT_TYPE_USBCDC_VIRTUAL) && (SERIAL_PORT_TYPE_USBCDC_VIRTUAL > 0U))
+serial_manager_status_t Serial_UsbCdcVirtualInit(serial_handle_t serialHandle, void *config);
+serial_manager_status_t Serial_UsbCdcVirtualDeinit(serial_handle_t serialHandle);
+serial_manager_status_t Serial_UsbCdcVirtualWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
+serial_manager_status_t Serial_UsbCdcVirtualRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length);
+serial_manager_status_t Serial_UsbCdcVirtualCancelWrite(serial_handle_t serialHandle);
+serial_manager_status_t Serial_UsbCdcVirtualInstallTxCallback(serial_handle_t serialHandle,
+                                                              serial_manager_callback_t callback,
+                                                              void *callbackParam);
+serial_manager_status_t Serial_UsbCdcVirtualInstallRxCallback(serial_handle_t serialHandle,
+                                                              serial_manager_callback_t callback,
+                                                              void *callbackParam);
+void Serial_UsbCdcVirtualIsrFunction(serial_handle_t serialHandle);
+#endif
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __SERIAL_PORT_INTERNAL_H__ */

FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/component/serial_manager/serial_port_uart.c

@@ -0,0 +1,403 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "serial_manager.h"
+#include "serial_port_internal.h"
+
+#if (defined(SERIAL_PORT_TYPE_UART) && (SERIAL_PORT_TYPE_UART > 0U))
+#include "uart.h"
+
+#include "serial_port_uart.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#ifndef NDEBUG
+#if (defined(DEBUG_CONSOLE_ASSERT_DISABLE) && (DEBUG_CONSOLE_ASSERT_DISABLE > 0U))
+#undef assert
+#define assert(n)
+#endif
+#endif
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+#define SERIAL_PORT_UART_RECEIVE_DATA_LENGTH 1U
+
+typedef struct _serial_uart_send_state
+{
+    serial_manager_callback_t callback;
+    void *callbackParam;
+    uint8_t *buffer;
+    uint32_t length;
+    volatile uint8_t busy;
+} serial_uart_send_state_t;
+
+typedef struct _serial_uart_recv_state
+{
+    serial_manager_callback_t callback;
+    void *callbackParam;
+    volatile uint8_t busy;
+    uint8_t readBuffer[SERIAL_PORT_UART_RECEIVE_DATA_LENGTH];
+} serial_uart_recv_state_t;
+#endif
+
+typedef struct _serial_uart_state
+{
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+    serial_uart_send_state_t tx;
+    serial_uart_recv_state_t rx;
+#endif
+    uint8_t usartHandleBuffer[HAL_UART_HANDLE_SIZE];
+} serial_uart_state_t;
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+/* UART user callback */
+static void Serial_UartCallback(hal_uart_handle_t handle, hal_uart_status_t status, void *userData)
+{
+    serial_uart_state_t *serialUartHandle;
+    serial_manager_callback_message_t msg;
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
+    hal_uart_transfer_t transfer;
+#endif
+
+    if (NULL == userData)
+    {
+        return;
+    }
+
+    serialUartHandle = (serial_uart_state_t *)userData;
+
+    if ((hal_uart_status_t)kStatus_HAL_UartRxIdle == status)
+    {
+        if ((NULL != serialUartHandle->rx.callback))
+        {
+            msg.buffer = &serialUartHandle->rx.readBuffer[0];
+            msg.length = sizeof(serialUartHandle->rx.readBuffer);
+            serialUartHandle->rx.callback(serialUartHandle->rx.callbackParam, &msg, kStatus_SerialManager_Success);
+        }
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
+        transfer.data     = &serialUartHandle->rx.readBuffer[0];
+        transfer.dataSize = sizeof(serialUartHandle->rx.readBuffer);
+        if (kStatus_HAL_UartSuccess ==
+            HAL_UartTransferReceiveNonBlocking(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), &transfer))
+#else
+        if ((hal_uart_status_t)kStatus_HAL_UartSuccess ==
+            HAL_UartReceiveNonBlocking(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]),
+                                       &serialUartHandle->rx.readBuffer[0], sizeof(serialUartHandle->rx.readBuffer)))
+#endif
+        {
+            serialUartHandle->rx.busy = 1U;
+        }
+        else
+        {
+            serialUartHandle->rx.busy = 0U;
+        }
+    }
+    else if ((hal_uart_status_t)kStatus_HAL_UartTxIdle == status)
+    {
+        if (0U != serialUartHandle->tx.busy)
+        {
+            serialUartHandle->tx.busy = 0U;
+            if ((NULL != serialUartHandle->tx.callback))
+            {
+                msg.buffer = serialUartHandle->tx.buffer;
+                msg.length = serialUartHandle->tx.length;
+                serialUartHandle->tx.callback(serialUartHandle->tx.callbackParam, &msg, kStatus_SerialManager_Success);
+            }
+        }
+    }
+    else
+    {
+    }
+}
+#endif
+
+serial_manager_status_t Serial_UartInit(serial_handle_t serialHandle, void *serialConfig)
+{
+    serial_uart_state_t *serialUartHandle;
+    serial_port_uart_config_t *uartConfig;
+    hal_uart_config_t config;
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
+    hal_uart_transfer_t transfer;
+#endif
+#endif
+
+    assert(serialConfig);
+    assert(serialHandle);
+    assert(SERIAL_PORT_UART_HANDLE_SIZE >= sizeof(serial_uart_state_t));
+
+    uartConfig       = (serial_port_uart_config_t *)serialConfig;
+    serialUartHandle = (serial_uart_state_t *)serialHandle;
+
+    config.baudRate_Bps = uartConfig->baudRate;
+    config.parityMode   = (hal_uart_parity_mode_t)uartConfig->parityMode;
+    config.stopBitCount = (hal_uart_stop_bit_count_t)uartConfig->stopBitCount;
+    config.enableRx     = uartConfig->enableRx;
+    config.enableTx     = uartConfig->enableTx;
+    config.srcClock_Hz  = uartConfig->clockRate;
+    config.instance     = uartConfig->instance;
+
+    if (kStatus_HAL_UartSuccess != HAL_UartInit(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), &config))
+    {
+        return kStatus_SerialManager_Error;
+    }
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
+    if (kStatus_HAL_UartSuccess !=
+        HAL_UartTransferInstallCallback(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]),
+                                        Serial_UartCallback, serialUartHandle))
+#else
+    if (kStatus_HAL_UartSuccess != HAL_UartInstallCallback(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]),
+                                                           Serial_UartCallback, serialUartHandle))
+#endif
+    {
+        return kStatus_SerialManager_Error;
+    }
+
+    if (0U != uartConfig->enableRx)
+    {
+        serialUartHandle->rx.busy = 1U;
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
+        transfer.data     = &serialUartHandle->rx.readBuffer[0];
+        transfer.dataSize = sizeof(serialUartHandle->rx.readBuffer);
+        if (kStatus_HAL_UartSuccess !=
+            HAL_UartTransferReceiveNonBlocking(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), &transfer))
+#else
+        if (kStatus_HAL_UartSuccess !=
+            HAL_UartReceiveNonBlocking(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]),
+                                       &serialUartHandle->rx.readBuffer[0], sizeof(serialUartHandle->rx.readBuffer)))
+#endif
+        {
+            serialUartHandle->rx.busy = 0U;
+            return kStatus_SerialManager_Error;
+        }
+    }
+#endif
+
+    return kStatus_SerialManager_Success;
+}
+
+serial_manager_status_t Serial_UartDeinit(serial_handle_t serialHandle)
+{
+    serial_uart_state_t *serialUartHandle;
+
+    assert(serialHandle);
+
+    serialUartHandle = (serial_uart_state_t *)serialHandle;
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
+    (void)HAL_UartTransferAbortReceive(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]));
+#else
+    (void)HAL_UartAbortReceive(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]));
+#endif
+#endif
+    (void)HAL_UartDeinit(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]));
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+    serialUartHandle->tx.busy = 0U;
+    serialUartHandle->rx.busy = 0U;
+#endif
+
+    return kStatus_SerialManager_Success;
+}
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+
+serial_manager_status_t Serial_UartWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length)
+{
+    serial_uart_state_t *serialUartHandle;
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
+    hal_uart_transfer_t transfer;
+#endif
+
+    assert(serialHandle);
+    assert(buffer);
+    assert(length);
+
+    serialUartHandle = (serial_uart_state_t *)serialHandle;
+
+    if (0U != serialUartHandle->tx.busy)
+    {
+        return kStatus_SerialManager_Busy;
+    }
+    serialUartHandle->tx.busy = 1U;
+
+    serialUartHandle->tx.buffer = buffer;
+    serialUartHandle->tx.length = length;
+
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
+    transfer.data     = buffer;
+    transfer.dataSize = length;
+    if (kStatus_HAL_UartSuccess !=
+        HAL_UartTransferSendNonBlocking(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), &transfer))
+#else
+    if (kStatus_HAL_UartSuccess !=
+        HAL_UartSendNonBlocking(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), buffer, length))
+#endif
+    {
+        serialUartHandle->tx.busy = 0U;
+        return kStatus_SerialManager_Error;
+    }
+    return kStatus_SerialManager_Success;
+}
+
+#else
+
+serial_manager_status_t Serial_UartWrite(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length)
+{
+    serial_uart_state_t *serialUartHandle;
+
+    assert(serialHandle);
+    assert(buffer);
+    assert(length);
+
+    serialUartHandle = (serial_uart_state_t *)serialHandle;
+
+    return (serial_manager_status_t)HAL_UartSendBlocking(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]),
+                                                         buffer, length);
+}
+
+serial_manager_status_t Serial_UartRead(serial_handle_t serialHandle, uint8_t *buffer, uint32_t length)
+{
+    serial_uart_state_t *serialUartHandle;
+
+    assert(serialHandle);
+    assert(buffer);
+    assert(length);
+
+    serialUartHandle = (serial_uart_state_t *)serialHandle;
+
+    return (serial_manager_status_t)HAL_UartReceiveBlocking(
+        ((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]), buffer, length);
+}
+
+#endif
+
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+serial_manager_status_t Serial_UartCancelWrite(serial_handle_t serialHandle)
+{
+    serial_uart_state_t *serialUartHandle;
+    serial_manager_callback_message_t msg;
+    uint32_t primask;
+    uint8_t isBusy = 0U;
+
+    assert(serialHandle);
+
+    serialUartHandle = (serial_uart_state_t *)serialHandle;
+
+    primask                   = DisableGlobalIRQ();
+    isBusy                    = serialUartHandle->tx.busy;
+    serialUartHandle->tx.busy = 0U;
+    EnableGlobalIRQ(primask);
+
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
+    (void)HAL_UartTransferAbortSend(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]));
+#else
+    (void)HAL_UartAbortSend(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]));
+#endif
+    if (0U != isBusy)
+    {
+        if ((NULL != serialUartHandle->tx.callback))
+        {
+            msg.buffer = serialUartHandle->tx.buffer;
+            msg.length = serialUartHandle->tx.length;
+            serialUartHandle->tx.callback(serialUartHandle->tx.callbackParam, &msg, kStatus_SerialManager_Canceled);
+        }
+    }
+    return kStatus_SerialManager_Success;
+}
+
+serial_manager_status_t Serial_UartInstallTxCallback(serial_handle_t serialHandle,
+                                                     serial_manager_callback_t callback,
+                                                     void *callbackParam)
+{
+    serial_uart_state_t *serialUartHandle;
+
+    assert(serialHandle);
+
+    serialUartHandle = (serial_uart_state_t *)serialHandle;
+
+    serialUartHandle->tx.callback      = callback;
+    serialUartHandle->tx.callbackParam = callbackParam;
+
+    return kStatus_SerialManager_Success;
+}
+
+serial_manager_status_t Serial_UartInstallRxCallback(serial_handle_t serialHandle,
+                                                     serial_manager_callback_t callback,
+                                                     void *callbackParam)
+{
+    serial_uart_state_t *serialUartHandle;
+
+    assert(serialHandle);
+
+    serialUartHandle = (serial_uart_state_t *)serialHandle;
+
+    serialUartHandle->rx.callback      = callback;
+    serialUartHandle->rx.callbackParam = callbackParam;
+
+    return kStatus_SerialManager_Success;
+}
+
+void Serial_UartIsrFunction(serial_handle_t serialHandle)
+{
+    serial_uart_state_t *serialUartHandle;
+
+    assert(serialHandle);
+
+    serialUartHandle = (serial_uart_state_t *)serialHandle;
+
+    HAL_UartIsrFunction(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0]));
+}
+#endif
+
+serial_manager_status_t Serial_UartEnterLowpower(serial_handle_t serialHandle)
+{
+    serial_uart_state_t *serialUartHandle;
+
+    assert(serialHandle);
+
+    serialUartHandle = (serial_uart_state_t *)serialHandle;
+
+    if (kStatus_HAL_UartSuccess != HAL_UartEnterLowpower(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0])))
+    {
+        return kStatus_SerialManager_Error;
+    }
+
+    return kStatus_SerialManager_Success;
+}
+
+serial_manager_status_t Serial_UartExitLowpower(serial_handle_t serialHandle)
+{
+    serial_uart_state_t *serialUartHandle;
+
+    assert(serialHandle);
+
+    serialUartHandle = (serial_uart_state_t *)serialHandle;
+
+    if (kStatus_HAL_UartSuccess != HAL_UartExitLowpower(((hal_uart_handle_t)&serialUartHandle->usartHandleBuffer[0])))
+    {
+        return kStatus_SerialManager_Error;
+    }
+
+    return kStatus_SerialManager_Success;
+}
+
+#endif

FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/component/serial_manager/serial_port_uart.h

@@ -0,0 +1,57 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __SERIAL_PORT_UART_H__
+#define __SERIAL_PORT_UART_H__
+
+#include "uart.h"
+
+/*!
+ * @addtogroup serial_port_uart
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/*! @brief serial port uart handle size*/
+#if (defined(SERIAL_MANAGER_NON_BLOCKING_MODE) && (SERIAL_MANAGER_NON_BLOCKING_MODE > 0U))
+#define SERIAL_PORT_UART_HANDLE_SIZE (76U + HAL_UART_HANDLE_SIZE)
+#else
+#define SERIAL_PORT_UART_HANDLE_SIZE (HAL_UART_HANDLE_SIZE)
+#endif
+
+/*! @brief serial port uart parity mode*/
+typedef enum _serial_port_uart_parity_mode
+{
+    kSerialManager_UartParityDisabled = 0x0U, /*!< Parity disabled */
+    kSerialManager_UartParityEven     = 0x1U, /*!< Parity even enabled */
+    kSerialManager_UartParityOdd      = 0x2U, /*!< Parity odd enabled */
+} serial_port_uart_parity_mode_t;
+
+/*! @brief serial port uart stop bit count*/
+typedef enum _serial_port_uart_stop_bit_count
+{
+    kSerialManager_UartOneStopBit = 0U, /*!< One stop bit */
+    kSerialManager_UartTwoStopBit = 1U, /*!< Two stop bits */
+} serial_port_uart_stop_bit_count_t;
+
+/*! @brief serial port uart config struct*/
+typedef struct _serial_port_uart_config
+{
+    uint32_t clockRate;                             /*!< clock rate  */
+    uint32_t baudRate;                              /*!< baud rate  */
+    serial_port_uart_parity_mode_t parityMode;      /*!< Parity mode, disabled (default), even, odd */
+    serial_port_uart_stop_bit_count_t stopBitCount; /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits  */
+    uint8_t instance;                               /*!< Instance (0 - UART0, 1 - UART1, ...), detail information
+                                                         please refer to the SOC corresponding RM. */
+    uint8_t enableRx;                               /*!< Enable RX */
+    uint8_t enableTx;                               /*!< Enable TX */
+} serial_port_uart_config_t;
+/*! @} */
+#endif /* __SERIAL_PORT_UART_H__ */

FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/component/uart/uart.h

@@ -0,0 +1,502 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __HAL_UART_ADAPTER_H__
+#define __HAL_UART_ADAPTER_H__
+
+#if defined(FSL_RTOS_FREE_RTOS)
+#include "FreeRTOS.h"
+#endif
+
+/*!
+ * @addtogroup UART_Adapter
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief Enable or disable UART adapter non-blocking mode (1 - enable, 0 - disable) */
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+#define UART_ADAPTER_NON_BLOCKING_MODE (1U)
+#else
+#ifndef SERIAL_MANAGER_NON_BLOCKING_MODE
+#define UART_ADAPTER_NON_BLOCKING_MODE (0U)
+#else
+#define UART_ADAPTER_NON_BLOCKING_MODE SERIAL_MANAGER_NON_BLOCKING_MODE
+#endif
+#endif
+
+#if defined(__GIC_PRIO_BITS)
+#define HAL_UART_ISR_PRIORITY (25U)
+#else
+#if defined(configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY)
+#define HAL_UART_ISR_PRIORITY (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY)
+#else
+/* The default value 3 is used to support different ARM Core, such as CM0P, CM4, CM7, and CM33, etc.
+ * The minimum number of priority bits implemented in the NVIC is 2 on these SOCs. The value of mininum
+ * priority is 3 (2^2 - 1). So, the default value is 3.
+ */
+#define HAL_UART_ISR_PRIORITY (3U)
+#endif
+#endif
+
+#ifndef HAL_UART_ADAPTER_LOWPOWER
+#define HAL_UART_ADAPTER_LOWPOWER (0U)
+#endif /* HAL_UART_ADAPTER_LOWPOWER */
+
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
+#define HAL_UART_HANDLE_SIZE (90U + HAL_UART_ADAPTER_LOWPOWER * 16U)
+#else
+#define HAL_UART_HANDLE_SIZE (4U + HAL_UART_ADAPTER_LOWPOWER * 16U)
+#endif
+
+/*! @brief Whether enable transactional function of the UART. (0 - disable, 1 - enable) */
+#define HAL_UART_TRANSFER_MODE (0U)
+
+typedef void *hal_uart_handle_t;
+
+/*! @brief UART status */
+typedef enum _hal_uart_status
+{
+    kStatus_HAL_UartSuccess = kStatus_Success,                       /*!< Successfully */
+    kStatus_HAL_UartTxBusy  = MAKE_STATUS(kStatusGroup_HAL_UART, 1), /*!< TX busy */
+    kStatus_HAL_UartRxBusy  = MAKE_STATUS(kStatusGroup_HAL_UART, 2), /*!< RX busy */
+    kStatus_HAL_UartTxIdle  = MAKE_STATUS(kStatusGroup_HAL_UART, 3), /*!< HAL UART transmitter is idle. */
+    kStatus_HAL_UartRxIdle  = MAKE_STATUS(kStatusGroup_HAL_UART, 4), /*!< HAL UART receiver is idle */
+    kStatus_HAL_UartBaudrateNotSupport =
+        MAKE_STATUS(kStatusGroup_HAL_UART, 5), /*!< Baudrate is not support in current clock source */
+    kStatus_HAL_UartProtocolError = MAKE_STATUS(
+        kStatusGroup_HAL_UART,
+        6),                                                        /*!< Error occurs for Noise, Framing, Parity, etc.
+                                                                        For transactional transfer, The up layer needs to abort the transfer and then starts again */
+    kStatus_HAL_UartError = MAKE_STATUS(kStatusGroup_HAL_UART, 7), /*!< Error occurs on HAL UART */
+} hal_uart_status_t;
+
+/*! @brief UART parity mode. */
+typedef enum _hal_uart_parity_mode
+{
+    kHAL_UartParityDisabled = 0x0U, /*!< Parity disabled */
+    kHAL_UartParityEven     = 0x1U, /*!< Parity even enabled */
+    kHAL_UartParityOdd      = 0x2U, /*!< Parity odd enabled */
+} hal_uart_parity_mode_t;
+
+/*! @brief UART stop bit count. */
+typedef enum _hal_uart_stop_bit_count
+{
+    kHAL_UartOneStopBit = 0U, /*!< One stop bit */
+    kHAL_UartTwoStopBit = 1U, /*!< Two stop bits */
+} hal_uart_stop_bit_count_t;
+
+/*! @brief UART configuration structure. */
+typedef struct _hal_uart_config
+{
+    uint32_t srcClock_Hz;                   /*!< Source clock */
+    uint32_t baudRate_Bps;                  /*!< Baud rate  */
+    hal_uart_parity_mode_t parityMode;      /*!< Parity mode, disabled (default), even, odd */
+    hal_uart_stop_bit_count_t stopBitCount; /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits  */
+    uint8_t enableRx;                       /*!< Enable RX */
+    uint8_t enableTx;                       /*!< Enable TX */
+    uint8_t instance; /*!< Instance (0 - UART0, 1 - UART1, ...), detail information please refer to the
+                           SOC corresponding RM.
+                           Invalid instance value will cause initialization failure. */
+} hal_uart_config_t;
+
+/*! @brief UART transfer callback function. */
+typedef void (*hal_uart_transfer_callback_t)(hal_uart_handle_t handle, hal_uart_status_t status, void *callbackParam);
+
+/*! @brief UART transfer structure. */
+typedef struct _hal_uart_transfer
+{
+    uint8_t *data;   /*!< The buffer of data to be transfer.*/
+    size_t dataSize; /*!< The byte count to be transfer. */
+} hal_uart_transfer_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* _cplusplus */
+
+/*!
+ * @name Initialization and deinitialization
+ * @{
+ */
+
+/*!
+ * @brief Initializes a UART instance with the UART handle and the user configuration structure.
+ *
+ * This function configures the UART module with user-defined settings. The user can configure the configuration
+ * structure. The parameter handle is a pointer to point to a memory space of size #HAL_UART_HANDLE_SIZE allocated by
+ * the caller. Example below shows how to use this API to configure the UART.
+ *  @code
+ *   uint32_t g_UartHandleBuffer[((HAL_UART_HANDLE_SIZE + sizeof(uint32_t) - 1) / sizeof(uitn32_t))];
+ *   hal_uart_handle_t g_UartHandle = (hal_uart_handle_t)&g_UartHandleBuffer[0];
+ *   hal_uart_config_t config;
+ *   config.srcClock_Hz = 48000000;
+ *   config.baudRate_Bps = 115200U;
+ *   config.parityMode = kHAL_UartParityDisabled;
+ *   config.stopBitCount = kHAL_UartOneStopBit;
+ *   config.enableRx = 1;
+ *   config.enableTx = 1;
+ *   config.instance = 0;
+ *   HAL_UartInit(g_UartHandle, &config);
+ *  @endcode
+ *
+ * @param handle Pointer to point to a memory space of size #HAL_UART_HANDLE_SIZE allocated by the caller.
+ * The handle should be 4 byte aligned, because unaligned access does not support on some devices.
+ * @param config Pointer to user-defined configuration structure.
+ * @retval kStatus_HAL_UartBaudrateNotSupport Baudrate is not support in current clock source.
+ * @retval kStatus_HAL_UartSuccess UART initialization succeed
+ */
+hal_uart_status_t HAL_UartInit(hal_uart_handle_t handle, hal_uart_config_t *config);
+
+/*!
+ * @brief Deinitializes a UART instance.
+ *
+ * This function waits for TX complete, disables TX and RX, and disables the UART clock.
+ *
+ * @param handle UART handle pointer.
+ * @retval kStatus_HAL_UartSuccess UART de-initialization succeed
+ */
+hal_uart_status_t HAL_UartDeinit(hal_uart_handle_t handle);
+
+/*! @}*/
+
+/*!
+ * @name Blocking bus Operations
+ * @{
+ */
+
+/*!
+ * @brief Reads RX data register using a blocking method.
+ *
+ * This function polls the RX register, waits for the RX register to be full or for RX FIFO to
+ * have data, and reads data from the RX register.
+ *
+ * @note The function #HAL_UartReceiveBlocking and the function #HAL_UartTransferReceiveNonBlocking
+ * cannot be used at the same time.
+ * And, the function #HAL_UartTransferAbortReceive cannot be used to abort the transmission of this function.
+ *
+ * @param handle UART handle pointer.
+ * @param data Start address of the buffer to store the received data.
+ * @param length Size of the buffer.
+ * @retval kStatus_HAL_UartError An error occurred while receiving data.
+ * @retval kStatus_HAL_UartParityError A parity error occurred while receiving data.
+ * @retval kStatus_HAL_UartSuccess Successfully received all data.
+ */
+hal_uart_status_t HAL_UartReceiveBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length);
+
+/*!
+ * @brief Writes to the TX register using a blocking method.
+ *
+ * This function polls the TX register, waits for the TX register to be empty or for the TX FIFO
+ * to have room and writes data to the TX buffer.
+ *
+ * @note The function #HAL_UartSendBlocking and the function #HAL_UartTransferSendNonBlocking
+ * cannot be used at the same time.
+ * And, the function #HAL_UartTransferAbortSend cannot be used to abort the transmission of this function.
+ *
+ * @param handle UART handle pointer.
+ * @param data Start address of the data to write.
+ * @param length Size of the data to write.
+ * @retval kStatus_HAL_UartSuccess Successfully sent all data.
+ */
+hal_uart_status_t HAL_UartSendBlocking(hal_uart_handle_t handle, const uint8_t *data, size_t length);
+
+/*! @}*/
+
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
+
+/*!
+ * @name Transactional
+ * @note The transactional API and the functional API cannot be used at the same time. The macro
+ * #HAL_UART_TRANSFER_MODE is used to set which one will be used. If #HAL_UART_TRANSFER_MODE is zero, the
+ * functional API with non-blocking mode will be used. Otherwise, transactional API will be used.
+ * @{
+ */
+
+/*!
+ * @brief Installs a callback and callback parameter.
+ *
+ * This function is used to install the callback and callback parameter for UART module.
+ * When any status of the UART changed, the driver will notify the upper layer by the installed callback
+ * function. And the status is also passed as status parameter when the callback is called.
+ *
+ * @param handle UART handle pointer.
+ * @param callback The callback function.
+ * @param callbackParam The parameter of the callback function.
+ * @retval kStatus_HAL_UartSuccess Successfully install the callback.
+ */
+hal_uart_status_t HAL_UartTransferInstallCallback(hal_uart_handle_t handle,
+                                                  hal_uart_transfer_callback_t callback,
+                                                  void *callbackParam);
+
+/*!
+ * @brief Receives a buffer of data using an interrupt method.
+ *
+ * This function receives data using an interrupt method. This is a non-blocking function, which
+ * returns directly without waiting for all data to be received.
+ * The receive request is saved by the UART driver.
+ * When the new data arrives, the receive request is serviced first.
+ * When all data is received, the UART driver notifies the upper layer
+ * through a callback function and passes the status parameter @ref kStatus_UART_RxIdle.
+ *
+ * @note The function #HAL_UartReceiveBlocking and the function #HAL_UartTransferReceiveNonBlocking
+ * cannot be used at the same time.
+ *
+ * @param handle UART handle pointer.
+ * @param transfer UART transfer structure, see #hal_uart_transfer_t.
+ * @retval kStatus_HAL_UartSuccess Successfully queue the transfer into transmit queue.
+ * @retval kStatus_HAL_UartRxBusy Previous receive request is not finished.
+ * @retval kStatus_HAL_UartError An error occurred.
+ */
+hal_uart_status_t HAL_UartTransferReceiveNonBlocking(hal_uart_handle_t handle, hal_uart_transfer_t *transfer);
+
+/*!
+ * @brief Transmits a buffer of data using the interrupt method.
+ *
+ * This function sends data using an interrupt method. This is a non-blocking function, which
+ * returns directly without waiting for all data to be written to the TX register. When
+ * all data is written to the TX register in the ISR, the UART driver calls the callback
+ * function and passes the @ref kStatus_UART_TxIdle as status parameter.
+ *
+ * @note The function #HAL_UartSendBlocking and the function #HAL_UartTransferSendNonBlocking
+ * cannot be used at the same time.
+ *
+ * @param handle UART handle pointer.
+ * @param transfer UART transfer structure. See #hal_uart_transfer_t.
+ * @retval kStatus_HAL_UartSuccess Successfully start the data transmission.
+ * @retval kStatus_HAL_UartTxBusy Previous transmission still not finished; data not all written to TX register yet.
+ * @retval kStatus_HAL_UartError An error occurred.
+ */
+hal_uart_status_t HAL_UartTransferSendNonBlocking(hal_uart_handle_t handle, hal_uart_transfer_t *transfer);
+
+/*!
+ * @brief Gets the number of bytes that have been received.
+ *
+ * This function gets the number of bytes that have been received.
+ *
+ * @param handle UART handle pointer.
+ * @param count Receive bytes count.
+ * @retval kStatus_HAL_UartError An error occurred.
+ * @retval kStatus_Success Get successfully through the parameter \p count.
+ */
+hal_uart_status_t HAL_UartTransferGetReceiveCount(hal_uart_handle_t handle, uint32_t *count);
+
+/*!
+ * @brief Gets the number of bytes written to the UART TX register.
+ *
+ * This function gets the number of bytes written to the UART TX
+ * register by using the interrupt method.
+ *
+ * @param handle UART handle pointer.
+ * @param count Send bytes count.
+ * @retval kStatus_HAL_UartError An error occurred.
+ * @retval kStatus_Success Get successfully through the parameter \p count.
+ */
+hal_uart_status_t HAL_UartTransferGetSendCount(hal_uart_handle_t handle, uint32_t *count);
+
+/*!
+ * @brief Aborts the interrupt-driven data receiving.
+ *
+ * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to know
+ * how many bytes are not received yet.
+ *
+ * @note The function #HAL_UartTransferAbortReceive cannot be used to abort the transmission of
+ * the function #HAL_UartReceiveBlocking.
+ *
+ * @param handle UART handle pointer.
+ * @retval kStatus_Success Get successfully abort the receiving.
+ */
+hal_uart_status_t HAL_UartTransferAbortReceive(hal_uart_handle_t handle);
+
+/*!
+ * @brief Aborts the interrupt-driven data sending.
+ *
+ * This function aborts the interrupt-driven data sending. The user can get the remainBytes to find out
+ * how many bytes are not sent out.
+ *
+ * @note The function #HAL_UartTransferAbortSend cannot be used to abort the transmission of
+ * the function #HAL_UartSendBlocking.
+ *
+ * @param handle UART handle pointer.
+ * @retval kStatus_Success Get successfully abort the sending.
+ */
+hal_uart_status_t HAL_UartTransferAbortSend(hal_uart_handle_t handle);
+
+/*! @}*/
+
+#else
+
+/*!
+ * @name Functional API with non-blocking mode.
+ * @note The functional API and the transactional API cannot be used at the same time. The macro
+ * #HAL_UART_TRANSFER_MODE is used to set which one will be used. If #HAL_UART_TRANSFER_MODE is zero, the
+ * functional API with non-blocking mode will be used. Otherwise, transactional API will be used.
+ * @{
+ */
+
+/*!
+ * @brief Installs a callback and callback parameter.
+ *
+ * This function is used to install the callback and callback parameter for UART module.
+ * When non-blocking sending or receiving finished, the adapter will notify the upper layer by the installed callback
+ * function. And the status is also passed as status parameter when the callback is called.
+ *
+ * @param handle UART handle pointer.
+ * @param callback The callback function.
+ * @param callbackParam The parameter of the callback function.
+ * @retval kStatus_HAL_UartSuccess Successfully install the callback.
+ */
+hal_uart_status_t HAL_UartInstallCallback(hal_uart_handle_t handle,
+                                          hal_uart_transfer_callback_t callback,
+                                          void *callbackParam);
+
+/*!
+ * @brief Receives a buffer of data using an interrupt method.
+ *
+ * This function receives data using an interrupt method. This is a non-blocking function, which
+ * returns directly without waiting for all data to be received.
+ * The receive request is saved by the UART adapter.
+ * When the new data arrives, the receive request is serviced first.
+ * When all data is received, the UART adapter notifies the upper layer
+ * through a callback function and passes the status parameter @ref kStatus_UART_RxIdle.
+ *
+ * @note The function #HAL_UartReceiveBlocking and the function #HAL_UartReceiveNonBlocking
+ * cannot be used at the same time.
+ *
+ * @param handle UART handle pointer.
+ * @param data Start address of the data to write.
+ * @param length Size of the data to write.
+ * @retval kStatus_HAL_UartSuccess Successfully queue the transfer into transmit queue.
+ * @retval kStatus_HAL_UartRxBusy Previous receive request is not finished.
+ * @retval kStatus_HAL_UartError An error occurred.
+ */
+hal_uart_status_t HAL_UartReceiveNonBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length);
+
+/*!
+ * @brief Transmits a buffer of data using the interrupt method.
+ *
+ * This function sends data using an interrupt method. This is a non-blocking function, which
+ * returns directly without waiting for all data to be written to the TX register. When
+ * all data is written to the TX register in the ISR, the UART driver calls the callback
+ * function and passes the @ref kStatus_UART_TxIdle as status parameter.
+ *
+ * @note The function #HAL_UartSendBlocking and the function #HAL_UartSendNonBlocking
+ * cannot be used at the same time.
+ *
+ * @param handle UART handle pointer.
+ * @param data Start address of the data to write.
+ * @param length Size of the data to write.
+ * @retval kStatus_HAL_UartSuccess Successfully start the data transmission.
+ * @retval kStatus_HAL_UartTxBusy Previous transmission still not finished; data not all written to TX register yet.
+ * @retval kStatus_HAL_UartError An error occurred.
+ */
+hal_uart_status_t HAL_UartSendNonBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length);
+
+/*!
+ * @brief Gets the number of bytes that have been received.
+ *
+ * This function gets the number of bytes that have been received.
+ *
+ * @param handle UART handle pointer.
+ * @param count Receive bytes count.
+ * @retval kStatus_HAL_UartError An error occurred.
+ * @retval kStatus_Success Get successfully through the parameter \p count.
+ */
+hal_uart_status_t HAL_UartGetReceiveCount(hal_uart_handle_t handle, uint32_t *reCount);
+
+/*!
+ * @brief Gets the number of bytes written to the UART TX register.
+ *
+ * This function gets the number of bytes written to the UART TX
+ * register by using the interrupt method.
+ *
+ * @param handle UART handle pointer.
+ * @param count Send bytes count.
+ * @retval kStatus_HAL_UartError An error occurred.
+ * @retval kStatus_Success Get successfully through the parameter \p count.
+ */
+hal_uart_status_t HAL_UartGetSendCount(hal_uart_handle_t handle, uint32_t *seCount);
+
+/*!
+ * @brief Aborts the interrupt-driven data receiving.
+ *
+ * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to know
+ * how many bytes are not received yet.
+ *
+ * @note The function #HAL_UartAbortReceive cannot be used to abort the transmission of
+ * the function #HAL_UartReceiveBlocking.
+ *
+ * @param handle UART handle pointer.
+ * @retval kStatus_Success Get successfully abort the receiving.
+ */
+hal_uart_status_t HAL_UartAbortReceive(hal_uart_handle_t handle);
+
+/*!
+ * @brief Aborts the interrupt-driven data sending.
+ *
+ * This function aborts the interrupt-driven data sending. The user can get the remainBytes to find out
+ * how many bytes are not sent out.
+ *
+ * @note The function #HAL_UartAbortSend cannot be used to abort the transmission of
+ * the function #HAL_UartSendBlocking.
+ *
+ * @param handle UART handle pointer.
+ * @retval kStatus_Success Get successfully abort the sending.
+ */
+hal_uart_status_t HAL_UartAbortSend(hal_uart_handle_t handle);
+
+/*! @}*/
+
+#endif
+#endif
+
+/*!
+ * @brief Prepares to enter low power consumption.
+ *
+ * This function is used to prepare to enter low power consumption.
+ *
+ * @param handle UART handle pointer.
+ * @retval kStatus_HAL_UartSuccess Successful operation.
+ * @retval kStatus_HAL_UartError An error occurred.
+ */
+hal_uart_status_t HAL_UartEnterLowpower(hal_uart_handle_t handle);
+
+/*!
+ * @brief Restores from low power consumption.
+ *
+ * This function is used to restore from low power consumption.
+ *
+ * @param handle UART handle pointer.
+ * @retval kStatus_HAL_UartSuccess Successful operation.
+ * @retval kStatus_HAL_UartError An error occurred.
+ */
+hal_uart_status_t HAL_UartExitLowpower(hal_uart_handle_t handle);
+
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
+/*!
+ * @brief UART IRQ handle function.
+ *
+ * This function handles the UART transmit and receive IRQ request.
+ *
+ * @param handle UART handle pointer.
+ */
+void HAL_UartIsrFunction(hal_uart_handle_t handle);
+#endif
+
+#if defined(__cplusplus)
+}
+#endif
+/*! @}*/
+#endif /* __HAL_UART_ADAPTER_H__ */

FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/component/uart/usart_adapter.c

@@ -0,0 +1,643 @@
+/*
+ * Copyright 2018 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "fsl_usart.h"
+#include "fsl_flexcomm.h"
+
+#include "uart.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#ifndef NDEBUG
+#if (defined(DEBUG_CONSOLE_ASSERT_DISABLE) && (DEBUG_CONSOLE_ASSERT_DISABLE > 0U))
+#undef assert
+#define assert(n)
+#endif
+#endif
+
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
+/*! @brief uart RX state structure. */
+typedef struct _hal_uart_receive_state
+{
+    volatile uint8_t *buffer;
+    volatile uint32_t bufferLength;
+    volatile uint32_t bufferSofar;
+} hal_uart_receive_state_t;
+
+/*! @brief uart TX state structure. */
+typedef struct _hal_uart_send_state
+{
+    volatile uint8_t *buffer;
+    volatile uint32_t bufferLength;
+    volatile uint32_t bufferSofar;
+} hal_uart_send_state_t;
+#endif
+/*! @brief uart state structure. */
+typedef struct _hal_uart_state
+{
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
+    hal_uart_transfer_callback_t callback;
+    void *callbackParam;
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
+    usart_handle_t hardwareHandle;
+#endif
+    hal_uart_receive_state_t rx;
+    hal_uart_send_state_t tx;
+#endif
+    uint8_t instance;
+} hal_uart_state_t;
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+static USART_Type *const s_UsartAdapterBase[] = USART_BASE_PTRS;
+
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
+
+#if !(defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
+/* Array of USART IRQ number. */
+static const IRQn_Type s_UsartIRQ[] = USART_IRQS;
+#endif
+
+#endif
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
+static hal_uart_status_t HAL_UartGetStatus(status_t status)
+{
+    hal_uart_status_t uartStatus = kStatus_HAL_UartError;
+    switch (status)
+    {
+        case kStatus_Success:
+            uartStatus = kStatus_HAL_UartSuccess;
+            break;
+        case kStatus_USART_TxBusy:
+            uartStatus = kStatus_HAL_UartTxBusy;
+            break;
+        case kStatus_USART_RxBusy:
+            uartStatus = kStatus_HAL_UartRxBusy;
+            break;
+        case kStatus_USART_TxIdle:
+            uartStatus = kStatus_HAL_UartTxIdle;
+            break;
+        case kStatus_USART_RxIdle:
+            uartStatus = kStatus_HAL_UartRxIdle;
+            break;
+        case kStatus_USART_BaudrateNotSupport:
+            uartStatus = kStatus_HAL_UartBaudrateNotSupport;
+            break;
+        case kStatus_USART_NoiseError:
+        case kStatus_USART_FramingError:
+        case kStatus_USART_ParityError:
+            uartStatus = kStatus_HAL_UartProtocolError;
+            break;
+        default:
+            break;
+    }
+    return uartStatus;
+}
+#else
+static hal_uart_status_t HAL_UartGetStatus(status_t status)
+{
+    if (kStatus_Success == status)
+    {
+        return kStatus_HAL_UartSuccess;
+    }
+    else
+    {
+        return kStatus_HAL_UartError;
+    }
+}
+#endif
+
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
+
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
+static void HAL_UartCallback(USART_Type *base, usart_handle_t *handle, status_t status, void *callbackParam)
+{
+    hal_uart_state_t *uartHandle;
+    hal_uart_status_t uartStatus = HAL_UartGetStatus(status);
+    assert(callbackParam);
+
+    uartHandle = (hal_uart_state_t *)callbackParam;
+
+    if (kStatus_HAL_UartProtocolError == uartStatus)
+    {
+        if (uartHandle->hardwareHandle.rxDataSize)
+        {
+            uartStatus = kStatus_HAL_UartError;
+        }
+    }
+
+    if (uartHandle->callback)
+    {
+        uartHandle->callback(uartHandle, uartStatus, uartHandle->callbackParam);
+    }
+}
+
+#else
+
+static void HAL_UartInterruptHandle(USART_Type *base, void *handle)
+{
+    hal_uart_state_t *uartHandle = (hal_uart_state_t *)handle;
+    uint32_t status;
+    uint8_t instance;
+
+    if (NULL == uartHandle)
+    {
+        return;
+    }
+    instance = uartHandle->instance;
+
+    status = USART_GetStatusFlags(s_UsartAdapterBase[instance]);
+
+    /* Receive data register full */
+    if ((USART_FIFOSTAT_RXNOTEMPTY_MASK & status) &&
+        (USART_GetEnabledInterrupts(s_UsartAdapterBase[instance]) & USART_FIFOINTENSET_RXLVL_MASK))
+    {
+        if (uartHandle->rx.buffer)
+        {
+            uartHandle->rx.buffer[uartHandle->rx.bufferSofar++] = USART_ReadByte(s_UsartAdapterBase[instance]);
+            if (uartHandle->rx.bufferSofar >= uartHandle->rx.bufferLength)
+            {
+                USART_DisableInterrupts(s_UsartAdapterBase[instance],
+                                        USART_FIFOINTENCLR_RXLVL_MASK | USART_FIFOINTENCLR_RXERR_MASK);
+                uartHandle->rx.buffer = NULL;
+                if (uartHandle->callback)
+                {
+                    uartHandle->callback(uartHandle, kStatus_HAL_UartRxIdle, uartHandle->callbackParam);
+                }
+            }
+        }
+    }
+
+    /* Send data register empty and the interrupt is enabled. */
+    if ((USART_FIFOSTAT_TXNOTFULL_MASK & status) &&
+        (USART_GetEnabledInterrupts(s_UsartAdapterBase[instance]) & USART_FIFOINTENSET_TXLVL_MASK))
+    {
+        if (uartHandle->tx.buffer)
+        {
+            USART_WriteByte(s_UsartAdapterBase[instance], uartHandle->tx.buffer[uartHandle->tx.bufferSofar++]);
+            if (uartHandle->tx.bufferSofar >= uartHandle->tx.bufferLength)
+            {
+                USART_DisableInterrupts(s_UsartAdapterBase[instance], USART_FIFOINTENCLR_TXLVL_MASK);
+                uartHandle->tx.buffer = NULL;
+                if (uartHandle->callback)
+                {
+                    uartHandle->callback(uartHandle, kStatus_HAL_UartTxIdle, uartHandle->callbackParam);
+                }
+            }
+        }
+    }
+
+#if 1
+    USART_ClearStatusFlags(s_UsartAdapterBase[instance], status);
+#endif
+}
+#endif
+
+#endif
+
+hal_uart_status_t HAL_UartInit(hal_uart_handle_t handle, hal_uart_config_t *config)
+{
+    hal_uart_state_t *uartHandle;
+    usart_config_t usartConfig;
+    status_t status;
+    assert(handle);
+    assert(config);
+    assert(config->instance < (sizeof(s_UsartAdapterBase) / sizeof(USART_Type *)));
+    assert(s_UsartAdapterBase[config->instance]);
+
+    if (HAL_UART_HANDLE_SIZE < sizeof(hal_uart_state_t))
+    {
+        return kStatus_HAL_UartError;
+    }
+
+    USART_GetDefaultConfig(&usartConfig);
+    usartConfig.baudRate_Bps = config->baudRate_Bps;
+
+    if (kHAL_UartParityEven == config->parityMode)
+    {
+        usartConfig.parityMode = kUSART_ParityEven;
+    }
+    else if (kHAL_UartParityOdd == config->parityMode)
+    {
+        usartConfig.parityMode = kUSART_ParityOdd;
+    }
+    else
+    {
+        usartConfig.parityMode = kUSART_ParityDisabled;
+    }
+
+    if (kHAL_UartTwoStopBit == config->stopBitCount)
+    {
+        usartConfig.stopBitCount = kUSART_TwoStopBit;
+    }
+    else
+    {
+        usartConfig.stopBitCount = kUSART_OneStopBit;
+    }
+    usartConfig.enableRx    = config->enableRx;
+    usartConfig.enableTx    = config->enableTx;
+    usartConfig.txWatermark = kUSART_TxFifo0;
+    usartConfig.rxWatermark = kUSART_RxFifo1;
+
+    status = USART_Init(s_UsartAdapterBase[config->instance], &usartConfig, config->srcClock_Hz);
+
+    if (kStatus_Success != status)
+    {
+        return HAL_UartGetStatus(status);
+    }
+
+    uartHandle           = (hal_uart_state_t *)handle;
+    uartHandle->instance = config->instance;
+
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
+
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
+    USART_TransferCreateHandle(s_UsartAdapterBase[config->instance], &uartHandle->hardwareHandle,
+                               (usart_transfer_callback_t)HAL_UartCallback, handle);
+#else
+    /* Enable interrupt in NVIC. */
+    FLEXCOMM_SetIRQHandler(s_UsartAdapterBase[config->instance], (flexcomm_irq_handler_t)HAL_UartInterruptHandle,
+                           handle);
+    NVIC_SetPriority((IRQn_Type)s_UsartIRQ[config->instance], HAL_UART_ISR_PRIORITY);
+    EnableIRQ(s_UsartIRQ[config->instance]);
+#endif
+
+#endif
+
+    return kStatus_HAL_UartSuccess;
+}
+
+hal_uart_status_t HAL_UartDeinit(hal_uart_handle_t handle)
+{
+    hal_uart_state_t *uartHandle;
+
+    assert(handle);
+
+    uartHandle = (hal_uart_state_t *)handle;
+
+    USART_Deinit(s_UsartAdapterBase[uartHandle->instance]);
+
+    return kStatus_HAL_UartSuccess;
+}
+
+hal_uart_status_t HAL_UartReceiveBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length)
+{
+    hal_uart_state_t *uartHandle;
+    status_t status;
+    assert(handle);
+    assert(data);
+    assert(length);
+
+    uartHandle = (hal_uart_state_t *)handle;
+
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
+    if (uartHandle->rx.buffer)
+    {
+        return kStatus_HAL_UartRxBusy;
+    }
+#endif
+
+    status = USART_ReadBlocking(s_UsartAdapterBase[uartHandle->instance], data, length);
+
+    return HAL_UartGetStatus(status);
+}
+
+hal_uart_status_t HAL_UartSendBlocking(hal_uart_handle_t handle, const uint8_t *data, size_t length)
+{
+    hal_uart_state_t *uartHandle;
+    assert(handle);
+    assert(data);
+    assert(length);
+
+    uartHandle = (hal_uart_state_t *)handle;
+
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
+    if (uartHandle->tx.buffer)
+    {
+        return kStatus_HAL_UartTxBusy;
+    }
+#endif
+
+    USART_WriteBlocking(s_UsartAdapterBase[uartHandle->instance], data, length);
+
+    return kStatus_HAL_UartSuccess;
+}
+
+hal_uart_status_t HAL_UartEnterLowpower(hal_uart_handle_t handle)
+{
+    assert(handle);
+
+    return kStatus_HAL_UartSuccess;
+}
+
+hal_uart_status_t HAL_UartExitLowpower(hal_uart_handle_t handle)
+{
+    assert(handle);
+
+    return kStatus_HAL_UartSuccess;
+}
+
+#if (defined(UART_ADAPTER_NON_BLOCKING_MODE) && (UART_ADAPTER_NON_BLOCKING_MODE > 0U))
+
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
+
+hal_uart_status_t HAL_UartTransferInstallCallback(hal_uart_handle_t handle,
+                                                  hal_uart_transfer_callback_t callback,
+                                                  void *callbackParam)
+{
+    hal_uart_state_t *uartHandle;
+
+    assert(handle);
+    assert(HAL_UART_TRANSFER_MODE);
+
+    uartHandle = (hal_uart_state_t *)handle;
+
+    uartHandle->callbackParam = callbackParam;
+    uartHandle->callback      = callback;
+
+    return kStatus_HAL_UartSuccess;
+}
+
+hal_uart_status_t HAL_UartTransferReceiveNonBlocking(hal_uart_handle_t handle, hal_uart_transfer_t *transfer)
+{
+    hal_uart_state_t *uartHandle;
+    status_t status;
+    assert(handle);
+    assert(transfer);
+    assert(HAL_UART_TRANSFER_MODE);
+
+    uartHandle = (hal_uart_state_t *)handle;
+
+    status = USART_TransferReceiveNonBlocking(s_UsartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle,
+                                              (usart_transfer_t *)transfer, NULL);
+
+    return HAL_UartGetStatus(status);
+}
+
+hal_uart_status_t HAL_UartTransferSendNonBlocking(hal_uart_handle_t handle, hal_uart_transfer_t *transfer)
+{
+    hal_uart_state_t *uartHandle;
+    status_t status;
+    assert(handle);
+    assert(transfer);
+    assert(HAL_UART_TRANSFER_MODE);
+
+    uartHandle = (hal_uart_state_t *)handle;
+
+    status = USART_TransferSendNonBlocking(s_UsartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle,
+                                           (usart_transfer_t *)transfer);
+
+    return HAL_UartGetStatus(status);
+}
+
+hal_uart_status_t HAL_UartTransferGetReceiveCount(hal_uart_handle_t handle, uint32_t *count)
+{
+    hal_uart_state_t *uartHandle;
+    status_t status;
+    assert(handle);
+    assert(count);
+    assert(HAL_UART_TRANSFER_MODE);
+
+    uartHandle = (hal_uart_state_t *)handle;
+
+    status =
+        USART_TransferGetReceiveCount(s_UsartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle, count);
+
+    return HAL_UartGetStatus(status);
+}
+
+hal_uart_status_t HAL_UartTransferGetSendCount(hal_uart_handle_t handle, uint32_t *count)
+{
+    hal_uart_state_t *uartHandle;
+    status_t status;
+    assert(handle);
+    assert(count);
+    assert(HAL_UART_TRANSFER_MODE);
+
+    uartHandle = (hal_uart_state_t *)handle;
+
+    status = USART_TransferGetSendCount(s_UsartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle, count);
+
+    return HAL_UartGetStatus(status);
+}
+
+hal_uart_status_t HAL_UartTransferAbortReceive(hal_uart_handle_t handle)
+{
+    hal_uart_state_t *uartHandle;
+    assert(handle);
+    assert(HAL_UART_TRANSFER_MODE);
+
+    uartHandle = (hal_uart_state_t *)handle;
+
+    USART_TransferAbortReceive(s_UsartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle);
+
+    return kStatus_HAL_UartSuccess;
+}
+
+hal_uart_status_t HAL_UartTransferAbortSend(hal_uart_handle_t handle)
+{
+    hal_uart_state_t *uartHandle;
+    assert(handle);
+    assert(HAL_UART_TRANSFER_MODE);
+
+    uartHandle = (hal_uart_state_t *)handle;
+
+    USART_TransferAbortSend(s_UsartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle);
+
+    return kStatus_HAL_UartSuccess;
+}
+
+#else
+
+/* None transactional API with non-blocking mode. */
+hal_uart_status_t HAL_UartInstallCallback(hal_uart_handle_t handle,
+                                          hal_uart_transfer_callback_t callback,
+                                          void *callbackParam)
+{
+    hal_uart_state_t *uartHandle;
+
+    assert(handle);
+    assert(!HAL_UART_TRANSFER_MODE);
+
+    uartHandle = (hal_uart_state_t *)handle;
+
+    uartHandle->callbackParam = callbackParam;
+    uartHandle->callback      = callback;
+
+    return kStatus_HAL_UartSuccess;
+}
+
+hal_uart_status_t HAL_UartReceiveNonBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length)
+{
+    hal_uart_state_t *uartHandle;
+    assert(handle);
+    assert(data);
+    assert(length);
+    assert(!HAL_UART_TRANSFER_MODE);
+
+    uartHandle = (hal_uart_state_t *)handle;
+
+    if (uartHandle->rx.buffer)
+    {
+        return kStatus_HAL_UartRxBusy;
+    }
+
+    uartHandle->rx.bufferLength = length;
+    uartHandle->rx.bufferSofar  = 0;
+    uartHandle->rx.buffer       = data;
+    USART_EnableInterrupts(s_UsartAdapterBase[uartHandle->instance], USART_FIFOINTENSET_RXLVL_MASK);
+    return kStatus_HAL_UartSuccess;
+}
+
+hal_uart_status_t HAL_UartSendNonBlocking(hal_uart_handle_t handle, uint8_t *data, size_t length)
+{
+    hal_uart_state_t *uartHandle;
+    assert(handle);
+    assert(data);
+    assert(length);
+    assert(!HAL_UART_TRANSFER_MODE);
+
+    uartHandle = (hal_uart_state_t *)handle;
+
+    if (uartHandle->tx.buffer)
+    {
+        return kStatus_HAL_UartTxBusy;
+    }
+    uartHandle->tx.bufferLength = length;
+    uartHandle->tx.bufferSofar  = 0;
+    uartHandle->tx.buffer       = (volatile uint8_t *)data;
+    USART_EnableInterrupts(s_UsartAdapterBase[uartHandle->instance], USART_FIFOINTENSET_TXLVL_MASK);
+    return kStatus_HAL_UartSuccess;
+}
+
+hal_uart_status_t HAL_UartGetReceiveCount(hal_uart_handle_t handle, uint32_t *reCount)
+{
+    hal_uart_state_t *uartHandle;
+    assert(handle);
+    assert(reCount);
+    assert(!HAL_UART_TRANSFER_MODE);
+
+    uartHandle = (hal_uart_state_t *)handle;
+
+    if (uartHandle->rx.buffer)
+    {
+        *reCount = uartHandle->rx.bufferSofar;
+        return kStatus_HAL_UartSuccess;
+    }
+    return kStatus_HAL_UartError;
+}
+
+hal_uart_status_t HAL_UartGetSendCount(hal_uart_handle_t handle, uint32_t *seCount)
+{
+    hal_uart_state_t *uartHandle;
+    assert(handle);
+    assert(seCount);
+    assert(!HAL_UART_TRANSFER_MODE);
+
+    uartHandle = (hal_uart_state_t *)handle;
+
+    if (uartHandle->tx.buffer)
+    {
+        *seCount = uartHandle->tx.bufferSofar;
+        return kStatus_HAL_UartSuccess;
+    }
+    return kStatus_HAL_UartError;
+}
+
+hal_uart_status_t HAL_UartAbortReceive(hal_uart_handle_t handle)
+{
+    hal_uart_state_t *uartHandle;
+    assert(handle);
+    assert(!HAL_UART_TRANSFER_MODE);
+
+    uartHandle = (hal_uart_state_t *)handle;
+
+    if (uartHandle->rx.buffer)
+    {
+        USART_DisableInterrupts(s_UsartAdapterBase[uartHandle->instance],
+                                USART_FIFOINTENCLR_RXLVL_MASK | USART_FIFOINTENCLR_RXERR_MASK);
+        uartHandle->rx.buffer = NULL;
+    }
+
+    return kStatus_HAL_UartSuccess;
+}
+
+hal_uart_status_t HAL_UartAbortSend(hal_uart_handle_t handle)
+{
+    hal_uart_state_t *uartHandle;
+    assert(handle);
+    assert(!HAL_UART_TRANSFER_MODE);
+
+    uartHandle = (hal_uart_state_t *)handle;
+
+    if (uartHandle->tx.buffer)
+    {
+        USART_DisableInterrupts(s_UsartAdapterBase[uartHandle->instance], USART_FIFOINTENCLR_TXLVL_MASK);
+        uartHandle->tx.buffer = NULL;
+    }
+
+    return kStatus_HAL_UartSuccess;
+}
+
+#endif
+
+#if (defined(HAL_UART_TRANSFER_MODE) && (HAL_UART_TRANSFER_MODE > 0U))
+
+void HAL_UartIsrFunction(hal_uart_handle_t handle)
+{
+    hal_uart_state_t *uartHandle;
+    assert(handle);
+    assert(HAL_UART_TRANSFER_MODE);
+
+    uartHandle = (hal_uart_state_t *)handle;
+
+#if 0
+    DisableIRQ(s_UsartIRQ[uartHandle->instance]);
+#endif
+    USART_TransferHandleIRQ(s_UsartAdapterBase[uartHandle->instance], &uartHandle->hardwareHandle);
+#if 0
+    NVIC_SetPriority((IRQn_Type)s_UsartIRQ[uartHandle->instance], HAL_UART_ISR_PRIORITY);
+    EnableIRQ(s_UsartIRQ[uartHandle->instance]);
+#endif
+}
+
+#else
+
+void HAL_UartIsrFunction(hal_uart_handle_t handle)
+{
+    hal_uart_state_t *uartHandle;
+    assert(handle);
+    assert(!HAL_UART_TRANSFER_MODE);
+
+    uartHandle = (hal_uart_state_t *)handle;
+
+#if 0
+    DisableIRQ(s_UsartIRQ[uartHandle->instance]);
+#endif
+    HAL_UartInterruptHandle(s_UsartAdapterBase[uartHandle->instance], (void *)uartHandle);
+#if 0
+    NVIC_SetPriority((IRQn_Type)s_UsartIRQ[uartHandle->instance], HAL_UART_ISR_PRIORITY);
+    EnableIRQ(s_UsartIRQ[uartHandle->instance]);
+#endif
+}
+
+#endif
+
+#endif

FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/device/LPC54018_features.h

@@ -0,0 +1,348 @@
+/*
+** ###################################################################
+**     Version:             rev. 1.2, 2017-06-08
+**     Build:               b191115
+**
+**     Abstract:
+**         Chip specific module features.
+**
+**     Copyright 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2019 NXP
+**     All rights reserved.
+**
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+**     Revisions:
+**     - rev. 1.0 (2016-08-12)
+**         Initial version.
+**     - rev. 1.1 (2016-11-25)
+**         Update CANFD and Classic CAN register.
+**         Add MAC TIMERSTAMP registers.
+**     - rev. 1.2 (2017-06-08)
+**         Remove RTC_CTRL_RTC_OSC_BYPASS.
+**         SYSCON_ARMTRCLKDIV rename to SYSCON_ARMTRACECLKDIV.
+**         Remove RESET and HALT from SYSCON_AHBCLKDIV.
+**
+** ###################################################################
+*/
+
+#ifndef _LPC54018_FEATURES_H_
+#define _LPC54018_FEATURES_H_
+
+/* SOC module features */
+
+/* @brief ADC availability on the SoC. */
+#define FSL_FEATURE_SOC_ADC_COUNT (1)
+/* @brief ASYNC_SYSCON availability on the SoC. */
+#define FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT (1)
+/* @brief CAN availability on the SoC. */
+#define FSL_FEATURE_SOC_LPC_CAN_COUNT (2)
+/* @brief CRC availability on the SoC. */
+#define FSL_FEATURE_SOC_CRC_COUNT (1)
+/* @brief CTIMER availability on the SoC. */
+#define FSL_FEATURE_SOC_CTIMER_COUNT (5)
+/* @brief DMA availability on the SoC. */
+#define FSL_FEATURE_SOC_DMA_COUNT (1)
+/* @brief DMIC availability on the SoC. */
+#define FSL_FEATURE_SOC_DMIC_COUNT (1)
+/* @brief EMC availability on the SoC. */
+#define FSL_FEATURE_SOC_EMC_COUNT (1)
+/* @brief ENET availability on the SoC. */
+#define FSL_FEATURE_SOC_LPC_ENET_COUNT (1)
+/* @brief FLEXCOMM availability on the SoC. */
+#define FSL_FEATURE_SOC_FLEXCOMM_COUNT (11)
+/* @brief GINT availability on the SoC. */
+#define FSL_FEATURE_SOC_GINT_COUNT (2)
+/* @brief GPIO availability on the SoC. */
+#define FSL_FEATURE_SOC_GPIO_COUNT (1)
+/* @brief I2C availability on the SoC. */
+#define FSL_FEATURE_SOC_I2C_COUNT (10)
+/* @brief I2S availability on the SoC. */
+#define FSL_FEATURE_SOC_I2S_COUNT (2)
+/* @brief INPUTMUX availability on the SoC. */
+#define FSL_FEATURE_SOC_INPUTMUX_COUNT (1)
+/* @brief IOCON availability on the SoC. */
+#define FSL_FEATURE_SOC_IOCON_COUNT (1)
+/* @brief LCD availability on the SoC. */
+#define FSL_FEATURE_SOC_LCD_COUNT (1)
+/* @brief MRT availability on the SoC. */
+#define FSL_FEATURE_SOC_MRT_COUNT (1)
+/* @brief PINT availability on the SoC. */
+#define FSL_FEATURE_SOC_PINT_COUNT (1)
+/* @brief RIT availability on the SoC. */
+#define FSL_FEATURE_SOC_RIT_COUNT (1)
+/* @brief RNG availability on the SoC. */
+#define FSL_FEATURE_SOC_LPC_RNG_COUNT (1)
+/* @brief RTC availability on the SoC. */
+#define FSL_FEATURE_SOC_RTC_COUNT (1)
+/* @brief SCT availability on the SoC. */
+#define FSL_FEATURE_SOC_SCT_COUNT (1)
+/* @brief SDIF availability on the SoC. */
+#define FSL_FEATURE_SOC_SDIF_COUNT (1)
+/* @brief SHA availability on the SoC. */
+#define FSL_FEATURE_SOC_SHA_COUNT (1)
+/* @brief SMARTCARD availability on the SoC. */
+#define FSL_FEATURE_SOC_SMARTCARD_COUNT (2)
+/* @brief SPI availability on the SoC. */
+#define FSL_FEATURE_SOC_SPI_COUNT (11)
+/* @brief SPIFI availability on the SoC. */
+#define FSL_FEATURE_SOC_SPIFI_COUNT (1)
+/* @brief SYSCON availability on the SoC. */
+#define FSL_FEATURE_SOC_SYSCON_COUNT (1)
+/* @brief USART availability on the SoC. */
+#define FSL_FEATURE_SOC_USART_COUNT (10)
+/* @brief USB availability on the SoC. */
+#define FSL_FEATURE_SOC_USB_COUNT (1)
+/* @brief USBFSH availability on the SoC. */
+#define FSL_FEATURE_SOC_USBFSH_COUNT (1)
+/* @brief USBHSD availability on the SoC. */
+#define FSL_FEATURE_SOC_USBHSD_COUNT (1)
+/* @brief USBHSH availability on the SoC. */
+#define FSL_FEATURE_SOC_USBHSH_COUNT (1)
+/* @brief UTICK availability on the SoC. */
+#define FSL_FEATURE_SOC_UTICK_COUNT (1)
+/* @brief WWDT availability on the SoC. */
+#define FSL_FEATURE_SOC_WWDT_COUNT (1)
+
+/* ADC module features */
+
+/* @brief Do not has input select (register INSEL). */
+#define FSL_FEATURE_ADC_HAS_NO_INSEL  (0)
+/* @brief Has ASYNMODE bitfile in CTRL reigster. */
+#define FSL_FEATURE_ADC_HAS_CTRL_ASYNMODE (1)
+/* @brief Has ASYNMODE bitfile in CTRL reigster. */
+#define FSL_FEATURE_ADC_HAS_CTRL_RESOL (1)
+/* @brief Has ASYNMODE bitfile in CTRL reigster. */
+#define FSL_FEATURE_ADC_HAS_CTRL_BYPASSCAL (1)
+/* @brief Has ASYNMODE bitfile in CTRL reigster. */
+#define FSL_FEATURE_ADC_HAS_CTRL_TSAMP (1)
+/* @brief Has ASYNMODE bitfile in CTRL reigster. */
+#define FSL_FEATURE_ADC_HAS_CTRL_LPWRMODE (0)
+/* @brief Has ASYNMODE bitfile in CTRL reigster. */
+#define FSL_FEATURE_ADC_HAS_CTRL_CALMODE (0)
+/* @brief Has startup register. */
+#define FSL_FEATURE_ADC_HAS_STARTUP_REG (1)
+/* @brief Has ADTrim register */
+#define FSL_FEATURE_ADC_HAS_TRIM_REG (0)
+/* @brief Has Calibration register. */
+#define FSL_FEATURE_ADC_HAS_CALIB_REG (1)
+
+/* CAN module features */
+
+/* @brief Support CANFD or not */
+#define FSL_FEATURE_CAN_SUPPORT_CANFD (1)
+
+/* DMA module features */
+
+/* @brief Number of channels */
+#define FSL_FEATURE_DMA_NUMBER_OF_CHANNELS (30)
+/* @brief Align size of DMA descriptor */
+#define FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE (512)
+/* @brief DMA head link descriptor table align size */
+#define FSL_FEATURE_DMA_LINK_DESCRIPTOR_ALIGN_SIZE (16U)
+
+/* FLEXCOMM module features */
+
+/* @brief FLEXCOMM0 USART INDEX 0 */
+#define FSL_FEATURE_FLEXCOMM0_USART_INDEX  (0)
+/* @brief FLEXCOMM0 SPI INDEX 0 */
+#define FSL_FEATURE_FLEXCOMM0_SPI_INDEX  (0)
+/* @brief FLEXCOMM0 I2C INDEX 0 */
+#define FSL_FEATURE_FLEXCOMM0_I2C_INDEX  (0)
+/* @brief FLEXCOMM1 USART INDEX 1 */
+#define FSL_FEATURE_FLEXCOMM1_USART_INDEX  (1)
+/* @brief FLEXCOMM1 SPI INDEX 1 */
+#define FSL_FEATURE_FLEXCOMM1_SPI_INDEX  (1)
+/* @brief FLEXCOMM1 I2C INDEX 1 */
+#define FSL_FEATURE_FLEXCOMM1_I2C_INDEX  (1)
+/* @brief FLEXCOMM2 USART INDEX 2 */
+#define FSL_FEATURE_FLEXCOMM2_USART_INDEX  (2)
+/* @brief FLEXCOMM2 SPI INDEX 2 */
+#define FSL_FEATURE_FLEXCOMM2_SPI_INDEX  (2)
+/* @brief FLEXCOMM2 I2C INDEX 2 */
+#define FSL_FEATURE_FLEXCOMM2_I2C_INDEX  (2)
+/* @brief FLEXCOMM3 USART INDEX 3 */
+#define FSL_FEATURE_FLEXCOMM3_USART_INDEX  (3)
+/* @brief FLEXCOMM3 SPI INDEX 3 */
+#define FSL_FEATURE_FLEXCOMM3_SPI_INDEX  (3)
+/* @brief FLEXCOMM3 I2C INDEX 3 */
+#define FSL_FEATURE_FLEXCOMM3_I2C_INDEX  (3)
+/* @brief FLEXCOMM4 USART INDEX 4 */
+#define FSL_FEATURE_FLEXCOMM4_USART_INDEX  (4)
+/* @brief FLEXCOMM4 SPI INDEX 4 */
+#define FSL_FEATURE_FLEXCOMM4_SPI_INDEX  (4)
+/* @brief FLEXCOMM4 I2C INDEX 4 */
+#define FSL_FEATURE_FLEXCOMM4_I2C_INDEX  (4)
+/* @brief FLEXCOMM5 USART INDEX 5 */
+#define FSL_FEATURE_FLEXCOMM5_USART_INDEX  (5)
+/* @brief FLEXCOMM5 SPI INDEX 5 */
+#define FSL_FEATURE_FLEXCOMM5_SPI_INDEX  (5)
+/* @brief FLEXCOMM5 I2C INDEX 5 */
+#define FSL_FEATURE_FLEXCOMM5_I2C_INDEX  (5)
+/* @brief FLEXCOMM6 USART INDEX 6 */
+#define FSL_FEATURE_FLEXCOMM6_USART_INDEX  (6)
+/* @brief FLEXCOMM6 SPI INDEX 6 */
+#define FSL_FEATURE_FLEXCOMM6_SPI_INDEX  (6)
+/* @brief FLEXCOMM6 I2C INDEX 6 */
+#define FSL_FEATURE_FLEXCOMM6_I2C_INDEX  (6)
+/* @brief FLEXCOMM7 I2S INDEX 0 */
+#define FSL_FEATURE_FLEXCOMM6_I2S_INDEX  (0)
+/* @brief FLEXCOMM7 USART INDEX 7 */
+#define FSL_FEATURE_FLEXCOMM7_USART_INDEX  (7)
+/* @brief FLEXCOMM7 SPI INDEX 7 */
+#define FSL_FEATURE_FLEXCOMM7_SPI_INDEX  (7)
+/* @brief FLEXCOMM7 I2C INDEX 7 */
+#define FSL_FEATURE_FLEXCOMM7_I2C_INDEX  (7)
+/* @brief FLEXCOMM7 I2S INDEX 1 */
+#define FSL_FEATURE_FLEXCOMM7_I2S_INDEX  (1)
+/* @brief FLEXCOMM4 USART INDEX 8 */
+#define FSL_FEATURE_FLEXCOMM8_USART_INDEX  (8)
+/* @brief FLEXCOMM4 SPI INDEX 8 */
+#define FSL_FEATURE_FLEXCOMM8_SPI_INDEX  (8)
+/* @brief FLEXCOMM4 I2C INDEX 8 */
+#define FSL_FEATURE_FLEXCOMM8_I2C_INDEX  (8)
+/* @brief FLEXCOMM5 USART INDEX 9 */
+#define FSL_FEATURE_FLEXCOMM9_USART_INDEX  (9)
+/* @brief FLEXCOMM5 SPI INDEX 9 */
+#define FSL_FEATURE_FLEXCOMM9_SPI_INDEX  (9)
+/* @brief FLEXCOMM5 I2C INDEX 9 */
+#define FSL_FEATURE_FLEXCOMM9_I2C_INDEX  (9)
+/* @brief I2S has DMIC interconnection */
+#define FSL_FEATURE_FLEXCOMM_INSTANCE_I2S_HAS_DMIC_INTERCONNECTIONn(x) \
+    (((x) == FLEXCOMM0) ? (0) : \
+    (((x) == FLEXCOMM1) ? (0) : \
+    (((x) == FLEXCOMM2) ? (0) : \
+    (((x) == FLEXCOMM3) ? (0) : \
+    (((x) == FLEXCOMM4) ? (0) : \
+    (((x) == FLEXCOMM5) ? (0) : \
+    (((x) == FLEXCOMM6) ? (0) : \
+    (((x) == FLEXCOMM7) ? (1) : \
+    (((x) == FLEXCOMM8) ? (0) : \
+    (((x) == FLEXCOMM9) ? (0) : \
+    (((x) == FLEXCOMM10) ? (0) : (-1))))))))))))
+
+/* I2S module features */
+
+/* @brief I2S support dual channel transfer */
+#define FSL_FEATURE_I2S_SUPPORT_SECONDARY_CHANNEL (1)
+/* @brief I2S has DMIC interconnection */
+#define FSL_FEATURE_FLEXCOMM_I2S_HAS_DMIC_INTERCONNECTION  (1)
+
+/* IOCON module features */
+
+/* @brief Func bit field width */
+#define FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH (4)
+
+/* MRT module features */
+
+/* @brief number of channels. */
+#define FSL_FEATURE_MRT_NUMBER_OF_CHANNELS  (4)
+
+/* interrupt module features */
+
+/* @brief Lowest interrupt request number. */
+#define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14)
+/* @brief Highest interrupt request number. */
+#define FSL_FEATURE_INTERRUPT_IRQ_MAX (105)
+
+/* PINT module features */
+
+/* @brief Number of connected outputs */
+#define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (8)
+
+/* RIT module features */
+
+/* @brief RIT has no reset control */
+#define FSL_FEATURE_RIT_HAS_NO_RESET (1)
+
+/* RTC module features */
+
+/* @brief RTC has no reset control */
+#define FSL_FEATURE_RTC_HAS_NO_RESET (1)
+
+/* SCT module features */
+
+/* @brief Number of events */
+#define FSL_FEATURE_SCT_NUMBER_OF_EVENTS (16)
+/* @brief Number of states */
+#define FSL_FEATURE_SCT_NUMBER_OF_STATES (16)
+/* @brief Number of match capture */
+#define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16)
+/* @brief Number of outputs */
+#define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10)
+
+/* SDIF module features */
+
+/* @brief FIFO depth, every location is a WORD */
+#define FSL_FEATURE_SDIF_FIFO_DEPTH_64_32BITS  (64)
+/* @brief Max DMA buffer size */
+#define FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE  (4096)
+/* @brief Max source clock in HZ */
+#define FSL_FEATURE_SDIF_MAX_SOURCE_CLOCK  (52000000)
+
+/* SPIFI module features */
+
+/* @brief SPIFI start address */
+#define FSL_FEATURE_SPIFI_START_ADDR (0x10000000)
+/* @brief SPIFI end address */
+#define FSL_FEATURE_SPIFI_END_ADDR (0x17FFFFFF)
+
+/* SYSCON module features */
+
+/* @brief Pointer to ROM IAP entry functions */
+#define FSL_FEATURE_SYSCON_IAP_ENTRY_LOCATION (0x03000205)
+
+/* SysTick module features */
+
+/* @brief Systick has external reference clock. */
+#define FSL_FEATURE_SYSTICK_HAS_EXT_REF (0)
+/* @brief Systick external reference clock is core clock divided by this value. */
+#define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (0)
+
+/* USB module features */
+
+/* @brief Size of the USB dedicated RAM */
+#define FSL_FEATURE_USB_USB_RAM (0x00002000)
+/* @brief Base address of the USB dedicated RAM */
+#define FSL_FEATURE_USB_USB_RAM_BASE_ADDRESS (0x40100000)
+/* @brief USB version */
+#define FSL_FEATURE_USB_VERSION (200)
+/* @brief Number of the endpoint in USB FS */
+#define FSL_FEATURE_USB_EP_NUM (5)
+
+/* USBFSH module features */
+
+/* @brief Size of the USB dedicated RAM */
+#define FSL_FEATURE_USBFSH_USB_RAM (0x00002000)
+/* @brief Base address of the USB dedicated RAM */
+#define FSL_FEATURE_USBFSH_USB_RAM_BASE_ADDRESS (0x40100000)
+/* @brief USBFSH version */
+#define FSL_FEATURE_USBFSH_VERSION (200)
+
+/* USBHSD module features */
+
+/* @brief Size of the USB dedicated RAM */
+#define FSL_FEATURE_USBHSD_USB_RAM (0x00002000)
+/* @brief Base address of the USB dedicated RAM */
+#define FSL_FEATURE_USBHSD_USB_RAM_BASE_ADDRESS (0x40100000)
+/* @brief USBHSD version */
+#define FSL_FEATURE_USBHSD_VERSION (300)
+/* @brief Number of the endpoint in USB HS */
+#define FSL_FEATURE_USBHSD_EP_NUM (6)
+/* @brief Resetting interrupt endpoint resets DATAx sequence to DATA.1 */
+#define FSL_FEATURE_USBHSD_INTERRUPT_DATAX_ISSUE_VERSION_CHECK (1)
+
+/* USBHSH module features */
+
+/* @brief Size of the USB dedicated RAM */
+#define FSL_FEATURE_USBHSH_USB_RAM (0x00002000)
+/* @brief Base address of the USB dedicated RAM */
+#define FSL_FEATURE_USBHSH_USB_RAM_BASE_ADDRESS (0x40100000)
+/* @brief USBHSH version */
+#define FSL_FEATURE_USBHSH_VERSION (300)
+
+#endif /* _LPC54018_FEATURES_H_ */
+

FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/device/fsl_device_registers.h

@@ -0,0 +1,34 @@
+/*
+ * Copyright 2014-2016 Freescale Semiconductor, Inc.
+ * Copyright 2016-2018 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef __FSL_DEVICE_REGISTERS_H__
+#define __FSL_DEVICE_REGISTERS_H__
+
+/*
+ * Include the cpu specific register header files.
+ *
+ * The CPU macro should be declared in the project or makefile.
+ */
+#if (defined(CPU_LPC54018JBD208) || defined(CPU_LPC54018JET180))
+
+#define LPC54018_SERIES
+
+/* CMSIS-style register definitions */
+#include "LPC54018.h"
+/* CPU specific feature definitions */
+#include "LPC54018_features.h"
+
+#else
+    #error "No valid CPU defined!"
+#endif
+
+#endif /* __FSL_DEVICE_REGISTERS_H__ */
+
+/*******************************************************************************
+ * EOF
+ ******************************************************************************/

FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/device/system_LPC54018.c

@@ -0,0 +1,368 @@
+/*
+** ###################################################################
+**     Processors:          LPC54018JBD208
+**                          LPC54018JET180
+**
+**     Compilers:           GNU C Compiler
+**                          IAR ANSI C/C++ Compiler for ARM
+**                          Keil ARM C/C++ Compiler
+**                          MCUXpresso Compiler
+**
+**     Reference manual:    LPC540xx/LPC54S0xx User manual Rev.0.8 5 June 2018
+**     Version:             rev. 1.2, 2017-06-08
+**     Build:               b191014
+**
+**     Abstract:
+**         Provides a system configuration function and a global variable that
+**         contains the system frequency. It configures the device and initializes
+**         the oscillator (PLL) that is part of the microcontroller device.
+**
+**     Copyright 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2019 NXP
+**     All rights reserved.
+**
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+**     Revisions:
+**     - rev. 1.0 (2016-08-12)
+**         Initial version.
+**     - rev. 1.1 (2016-11-25)
+**         Update CANFD and Classic CAN register.
+**         Add MAC TIMERSTAMP registers.
+**     - rev. 1.2 (2017-06-08)
+**         Remove RTC_CTRL_RTC_OSC_BYPASS.
+**         SYSCON_ARMTRCLKDIV rename to SYSCON_ARMTRACECLKDIV.
+**         Remove RESET and HALT from SYSCON_AHBCLKDIV.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file LPC54018
+ * @version 1.2
+ * @date 2017-06-08
+ * @brief Device specific configuration file for LPC54018 (implementation file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#include <stdint.h>
+#include "fsl_device_registers.h"
+
+#define NVALMAX (0x100)
+#define PVALMAX (0x20)
+#define MVALMAX (0x8000)
+#define PLL_MDEC_VAL_P (0)                                       /* MDEC is in bits  16:0 */
+#define PLL_MDEC_VAL_M (0x1FFFFUL << PLL_MDEC_VAL_P)
+#define PLL_NDEC_VAL_P (0)                                       /* NDEC is in bits  9:0 */
+#define PLL_NDEC_VAL_M (0x3FFUL << PLL_NDEC_VAL_P)
+#define PLL_PDEC_VAL_P (0)                                       /* PDEC is in bits  6:0 */
+#define PLL_PDEC_VAL_M (0x7FUL << PLL_PDEC_VAL_P)
+
+extern void *__Vectors;
+
+static const uint8_t wdtFreqLookup[32] = {0, 8, 12, 15, 18, 20, 24, 26, 28, 30, 32, 34, 36, 38, 40, 41, 42, 44, 45, 46,
+                                            48, 49, 50, 52, 53, 54, 56, 57, 58, 59, 60, 61};
+/* Get WATCH DOG Clk */
+static uint32_t getWdtOscFreq(void)
+{
+    uint8_t freq_sel, div_sel;
+    if (SYSCON->PDRUNCFG[0] & SYSCON_PDRUNCFG_PDEN_WDT_OSC_MASK)
+    {
+        return 0U;
+    }
+    else
+    {
+        div_sel = (uint8_t)((SYSCON->WDTOSCCTRL & SYSCON_WDTOSCCTRL_DIVSEL_MASK) + 1UL) << 1UL;
+        freq_sel = wdtFreqLookup[((SYSCON->WDTOSCCTRL & SYSCON_WDTOSCCTRL_FREQSEL_MASK) >> SYSCON_WDTOSCCTRL_FREQSEL_SHIFT)];
+        return ((uint32_t) freq_sel * 50000U)/((uint32_t)div_sel);
+    }
+}
+/* Find decoded N value for raw NDEC value */
+static uint32_t pllDecodeN(uint32_t NDEC)
+{
+    uint32_t n, x, i;
+
+    /* Find NDec */
+    switch (NDEC)
+    {
+        case 0x3FF:
+            n = 0UL;
+            break;
+        case 0x302:
+            n = 1UL;
+            break;
+        case 0x202:
+            n = 2UL;
+            break;
+        default:
+            x = 0x080UL;
+            n = 0xFFFFFFFFUL;
+            for (i = NVALMAX; i >= 3UL; i--)
+            {
+                x = (((x ^ (x >> 2UL) ^ (x >> 3UL) ^ (x >> 4UL)) & 1UL) << 7UL) | ((x >> 1UL) & 0x7FUL);
+                if ((x & (PLL_NDEC_VAL_M >> PLL_NDEC_VAL_P)) == NDEC)
+                {
+                    /* Decoded value of NDEC */
+                    n = i;
+                }
+                if (n != 0xFFFFFFFFUL)
+                {
+                    break;
+                }
+            }
+            break;
+    }
+    return n;
+}
+
+/* Find decoded P value for raw PDEC value */
+static uint32_t pllDecodeP(uint32_t PDEC)
+{
+    uint32_t p, x, i;
+    /* Find PDec */
+    switch (PDEC)
+    {
+        case 0x7F:
+            p = 0UL;
+            break;
+        case 0x62:
+            p = 1UL;
+            break;
+        case 0x42:
+            p = 2UL;
+            break;
+        default:
+            x = 0x10UL;
+            p = 0xFFFFFFFFUL;
+            for (i = PVALMAX; i >= 3UL; i--)
+            {
+                x = (((x ^ (x >> 2UL)) & 1UL) << 4UL) | ((x >> 1UL) & 0xFUL);
+                if ((x & (PLL_PDEC_VAL_M >> PLL_PDEC_VAL_P)) == PDEC)
+                {
+                    /* Decoded value of PDEC */
+                    p = i;
+                }
+                if (p != 0xFFFFFFFFUL)
+                {
+                    break;
+                }
+            }
+            break;
+    }
+    return p;
+}
+
+/* Find decoded M value for raw MDEC value */
+static uint32_t pllDecodeM(uint32_t MDEC)
+{
+    uint32_t m, i, x;
+
+    /* Find MDec */
+    switch (MDEC)
+    {
+        case 0x1FFFF:
+            m = 0UL;
+            break;
+        case 0x18003:
+            m = 1UL;
+            break;
+        case 0x10003:
+            m = 2UL;
+            break;
+        default:
+            x = 0x04000UL;
+            m = 0xFFFFFFFFUL;
+            for (i = MVALMAX; i >= 3UL; i--)
+            {
+                x = (((x ^ (x >> 1UL)) & 1UL) << 14UL) | ((x >> 1UL) & 0x3FFFUL);
+                if ((x & (PLL_MDEC_VAL_M >> PLL_MDEC_VAL_P)) == MDEC)
+                {
+                    /* Decoded value of MDEC */
+                    m = i;
+                }
+                if (m != 0xFFFFFFFFUL)
+                {
+                    break;
+                }
+            }
+            break;
+    }
+    return m;
+}
+
+/* Get predivider (N) from PLL NDEC setting */
+static uint32_t findPllPreDiv(uint32_t ctrlReg, uint32_t nDecReg)
+{
+    uint32_t preDiv = 1;
+
+    /* Direct input is not used? */
+    if ((ctrlReg & SYSCON_SYSPLLCTRL_DIRECTI_MASK) == 0UL)
+    {
+        /* Decode NDEC value to get (N) pre divider */
+        preDiv = pllDecodeN(nDecReg & 0x3FFUL);
+        if (preDiv == 0UL)
+        {
+            preDiv = 1;
+        }
+    }
+    /* Adjusted by 1, directi is used to bypass */
+    return preDiv;
+}
+
+/* Get postdivider (P) from PLL PDEC setting */
+static uint32_t findPllPostDiv(uint32_t ctrlReg, uint32_t pDecReg)
+{
+    uint32_t postDiv = 1;
+
+    /* Direct input is not used? */
+    if ((ctrlReg & SYSCON_SYSPLLCTRL_DIRECTO_MASK) == 0UL)
+    {
+        /* Decode PDEC value to get (P) post divider */
+        postDiv = 2UL * pllDecodeP(pDecReg & 0x7FUL);
+        if (postDiv == 0UL)
+        {
+            postDiv = 2;
+        }
+    }
+    /* Adjusted by 1, directo is used to bypass */
+    return postDiv;
+}
+
+/* Get multiplier (M) from PLL MDEC and BYPASS_FBDIV2 settings */
+static uint32_t findPllMMult(uint32_t ctrlReg, uint32_t mDecReg)
+{
+    uint32_t mMult = 1;
+
+    /* Decode MDEC value to get (M) multiplier */
+    mMult = pllDecodeM(mDecReg & 0x1FFFFUL);
+    if (mMult == 0UL)
+    {
+        mMult = 1;
+    }
+    return mMult;
+}
+
+
+
+/* ----------------------------------------------------------------------------
+   -- Core clock
+   ---------------------------------------------------------------------------- */
+
+uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
+
+/* ----------------------------------------------------------------------------
+   -- SystemInit()
+   ---------------------------------------------------------------------------- */
+
+void SystemInit (void) {
+#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
+  SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2));    /* set CP10, CP11 Full Access */
+#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
+
+#if defined(__MCUXPRESSO)
+    extern void(*const g_pfnVectors[]) (void);
+    SCB->VTOR = (uint32_t) &g_pfnVectors;
+#else
+    extern void *__Vectors;
+    SCB->VTOR = (uint32_t) &__Vectors;
+#endif
+    SYSCON->ARMTRACECLKDIV = 0;
+/* Optionally enable RAM banks that may be off by default at reset */
+#if !defined(DONT_ENABLE_DISABLED_RAMBANKS)
+    SYSCON->AHBCLKCTRLSET[0] = SYSCON_AHBCLKCTRL_SRAM1_MASK | SYSCON_AHBCLKCTRL_SRAM2_MASK | SYSCON_AHBCLKCTRL_SRAM3_MASK;
+
+#endif
+    SYSCON->MAINCLKSELA = 0U;
+    SYSCON->MAINCLKSELB = 0U;
+  SystemInitHook();
+}
+
+/* ----------------------------------------------------------------------------
+   -- SystemCoreClockUpdate()
+   ---------------------------------------------------------------------------- */
+
+void SystemCoreClockUpdate (void) {
+uint32_t clkRate = 0;
+    uint32_t prediv, postdiv;
+    uint64_t workRate;
+
+    switch (SYSCON->MAINCLKSELB & SYSCON_MAINCLKSELB_SEL_MASK)
+    {
+        case 0x00: /* MAINCLKSELA clock (main_clk_a)*/
+            switch (SYSCON->MAINCLKSELA & SYSCON_MAINCLKSELA_SEL_MASK)
+            {
+                case 0x00: /* FRO 12 MHz (fro_12m) */
+                    clkRate = CLK_FRO_12MHZ;
+                    break;
+                case 0x01: /* CLKIN Source (clk_in) */
+                    clkRate = CLK_CLK_IN;
+                    break;
+                case 0x02: /* Watchdog oscillator (wdt_clk) */
+                    clkRate = getWdtOscFreq();
+                    break;
+                default: /* = 0x03 = FRO 96 or 48 MHz (fro_hf) */
+                    if ((SYSCON->FROCTRL & SYSCON_FROCTRL_SEL_MASK) == SYSCON_FROCTRL_SEL_MASK)
+                    {
+                        clkRate = CLK_FRO_96MHZ;
+                    }
+                    else
+                    {
+                        clkRate = CLK_FRO_48MHZ;
+                    }
+                    break;
+            }
+            break;
+        case 0x02: /* System PLL clock (pll_clk)*/
+            switch (SYSCON->SYSPLLCLKSEL & SYSCON_SYSPLLCLKSEL_SEL_MASK)
+            {
+                case 0x00: /* FRO 12 MHz (fro_12m) */
+                    clkRate = CLK_FRO_12MHZ;
+                    break;
+                case 0x01: /* CLKIN Source (clk_in) */
+                    clkRate = CLK_CLK_IN;
+                    break;
+                case 0x02: /* Watchdog oscillator (wdt_clk) */
+                    clkRate = getWdtOscFreq();
+                    break;
+                case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */
+                    clkRate = CLK_RTC_32K_CLK;
+                    break;
+                default:
+                    break;
+            }
+            if ((SYSCON->SYSPLLCTRL & SYSCON_SYSPLLCTRL_BYPASS_MASK) == 0UL)
+            {
+                /* PLL is not in bypass mode, get pre-divider, post-divider, and M divider */
+                prediv = findPllPreDiv(SYSCON->SYSPLLCTRL, SYSCON->SYSPLLNDEC);
+                postdiv = findPllPostDiv(SYSCON->SYSPLLCTRL, SYSCON->SYSPLLPDEC);
+                /* Adjust input clock */
+                clkRate = clkRate / prediv;
+
+                /* MDEC used for rate */
+                workRate = (uint64_t)(clkRate) * (uint64_t)findPllMMult(SYSCON->SYSPLLCTRL, SYSCON->SYSPLLMDEC);
+                clkRate = (uint32_t)(workRate / ((uint64_t)postdiv));
+                clkRate = clkRate * 2; /* PLL CCO output is divided by 2 before to M-Divider */
+            }
+            break;
+        case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */
+            clkRate = CLK_RTC_32K_CLK;
+            break;
+        default:
+            break;
+    }
+    SystemCoreClock = clkRate / ((SYSCON->AHBCLKDIV & 0xFFUL) + 1UL);
+}
+
+/* ----------------------------------------------------------------------------
+   -- SystemInitHook()
+   ---------------------------------------------------------------------------- */
+
+__attribute__ ((weak)) void SystemInitHook (void) {
+  /* Void implementation of the weak function. */
+}

FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/device/system_LPC54018.h

@@ -0,0 +1,116 @@
+/*
+** ###################################################################
+**     Processors:          LPC54018JBD208
+**                          LPC54018JET180
+**
+**     Compilers:           GNU C Compiler
+**                          IAR ANSI C/C++ Compiler for ARM
+**                          Keil ARM C/C++ Compiler
+**                          MCUXpresso Compiler
+**
+**     Reference manual:    LPC540xx/LPC54S0xx User manual Rev.0.8 5 June 2018
+**     Version:             rev. 1.2, 2017-06-08
+**     Build:               b191014
+**
+**     Abstract:
+**         Provides a system configuration function and a global variable that
+**         contains the system frequency. It configures the device and initializes
+**         the oscillator (PLL) that is part of the microcontroller device.
+**
+**     Copyright 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2019 NXP
+**     All rights reserved.
+**
+**     SPDX-License-Identifier: BSD-3-Clause
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+**     Revisions:
+**     - rev. 1.0 (2016-08-12)
+**         Initial version.
+**     - rev. 1.1 (2016-11-25)
+**         Update CANFD and Classic CAN register.
+**         Add MAC TIMERSTAMP registers.
+**     - rev. 1.2 (2017-06-08)
+**         Remove RTC_CTRL_RTC_OSC_BYPASS.
+**         SYSCON_ARMTRCLKDIV rename to SYSCON_ARMTRACECLKDIV.
+**         Remove RESET and HALT from SYSCON_AHBCLKDIV.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file LPC54018
+ * @version 1.2
+ * @date 2017-06-08
+ * @brief Device specific configuration file for LPC54018 (header file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#ifndef _SYSTEM_LPC54018_H_
+#define _SYSTEM_LPC54018_H_                      /**< Symbol preventing repeated inclusion */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+#define DEFAULT_SYSTEM_CLOCK           12000000u           /* Default System clock value */
+#define CLK_RTC_32K_CLK                   32768u           /* RTC oscillator 32 kHz output (32k_clk */
+#define CLK_FRO_12MHZ                  12000000u           /* FRO 12 MHz (fro_12m) */
+#define CLK_FRO_48MHZ                  48000000u           /* FRO 48 MHz (fro_48m) */
+#define CLK_FRO_96MHZ                  96000000u           /* FRO 96 MHz (fro_96m) */
+#define CLK_CLK_IN                            0u           /* Default CLK_IN pin clock */
+
+
+/**
+ * @brief System clock frequency (core clock)
+ *
+ * The system clock frequency supplied to the SysTick timer and the processor
+ * core clock. This variable can be used by the user application to setup the
+ * SysTick timer or configure other parameters. It may also be used by debugger to
+ * query the frequency of the debug timer or configure the trace clock speed
+ * SystemCoreClock is initialized with a correct predefined value.
+ */
+extern uint32_t SystemCoreClock;
+
+/**
+ * @brief Setup the microcontroller system.
+ *
+ * Typically this function configures the oscillator (PLL) that is part of the
+ * microcontroller device. For systems with variable clock speed it also updates
+ * the variable SystemCoreClock. SystemInit is called from startup_device file.
+ */
+void SystemInit (void);
+
+/**
+ * @brief Updates the SystemCoreClock variable.
+ *
+ * It must be called whenever the core clock is changed during program
+ * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
+ * the current core clock.
+ */
+void SystemCoreClockUpdate (void);
+
+/**
+ * @brief SystemInit function hook.
+ *
+ * This weak function allows to call specific initialization code during the
+ * SystemInit() execution.This can be used when an application specific code needs
+ * to be called as close to the reset entry as possible (for example the Multicore
+ * Manager MCMGR_EarlyInit() function call).
+ * NOTE: No global r/w variables can be used in this hook function because the
+ * initialization of these variables happens after this function.
+ */
+void SystemInitHook (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* _SYSTEM_LPC54018_H_ */

FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/drivers/fsl_common.c

@@ -0,0 +1,225 @@
+/*
+ * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2019 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#define SDK_MEM_MAGIC_NUMBER 12345U
+
+typedef struct _mem_align_control_block
+{
+    uint16_t identifier; /*!< Identifier for the memory control block. */
+    uint16_t offset;     /*!< offset from aligned address to real address */
+} mem_align_cb_t;
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.common"
+#endif
+
+#ifndef __GIC_PRIO_BITS
+#if defined(ENABLE_RAM_VECTOR_TABLE)
+uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler)
+{
+/* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */
+#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
+    extern uint32_t Image$$VECTOR_ROM$$Base[];
+    extern uint32_t Image$$VECTOR_RAM$$Base[];
+    extern uint32_t Image$$RW_m_data$$Base[];
+
+#define __VECTOR_TABLE Image$$VECTOR_ROM$$Base
+#define __VECTOR_RAM Image$$VECTOR_RAM$$Base
+#define __RAM_VECTOR_TABLE_SIZE (((uint32_t)Image$$RW_m_data$$Base - (uint32_t)Image$$VECTOR_RAM$$Base))
+#elif defined(__ICCARM__)
+    extern uint32_t __RAM_VECTOR_TABLE_SIZE[];
+    extern uint32_t __VECTOR_TABLE[];
+    extern uint32_t __VECTOR_RAM[];
+#elif defined(__GNUC__)
+    extern uint32_t __VECTOR_TABLE[];
+    extern uint32_t __VECTOR_RAM[];
+    extern uint32_t __RAM_VECTOR_TABLE_SIZE_BYTES[];
+    uint32_t __RAM_VECTOR_TABLE_SIZE = (uint32_t)(__RAM_VECTOR_TABLE_SIZE_BYTES);
+#endif /* defined(__CC_ARM) || defined(__ARMCC_VERSION) */
+    uint32_t n;
+    uint32_t ret;
+    uint32_t irqMaskValue;
+
+    irqMaskValue = DisableGlobalIRQ();
+    if (SCB->VTOR != (uint32_t)__VECTOR_RAM)
+    {
+        /* Copy the vector table from ROM to RAM */
+        for (n = 0; n < ((uint32_t)__RAM_VECTOR_TABLE_SIZE) / sizeof(uint32_t); n++)
+        {
+            __VECTOR_RAM[n] = __VECTOR_TABLE[n];
+        }
+        /* Point the VTOR to the position of vector table */
+        SCB->VTOR = (uint32_t)__VECTOR_RAM;
+    }
+
+    ret = __VECTOR_RAM[irq + 16];
+    /* make sure the __VECTOR_RAM is noncachable */
+    __VECTOR_RAM[irq + 16] = irqHandler;
+
+    EnableGlobalIRQ(irqMaskValue);
+
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+    __DSB();
+#endif
+
+    return ret;
+}
+#endif /* ENABLE_RAM_VECTOR_TABLE. */
+#endif /* __GIC_PRIO_BITS. */
+
+#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0))
+#if !(defined(FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS) && FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS)
+
+void EnableDeepSleepIRQ(IRQn_Type interrupt)
+{
+    uint32_t intNumber = (uint32_t)interrupt;
+
+    uint32_t index = 0;
+
+    while (intNumber >= 32u)
+    {
+        index++;
+        intNumber -= 32u;
+    }
+
+    SYSCON->STARTERSET[index] = 1u << intNumber;
+    EnableIRQ(interrupt); /* also enable interrupt at NVIC */
+}
+
+void DisableDeepSleepIRQ(IRQn_Type interrupt)
+{
+    uint32_t intNumber = (uint32_t)interrupt;
+
+    DisableIRQ(interrupt); /* also disable interrupt at NVIC */
+    uint32_t index = 0;
+
+    while (intNumber >= 32u)
+    {
+        index++;
+        intNumber -= 32u;
+    }
+
+    SYSCON->STARTERCLR[index] = 1u << intNumber;
+}
+#endif /* FSL_FEATURE_SYSCON_STARTER_DISCONTINUOUS */
+#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */
+
+void *SDK_Malloc(size_t size, size_t alignbytes)
+{
+    mem_align_cb_t *p_cb = NULL;
+    uint32_t alignedsize = SDK_SIZEALIGN(size, alignbytes) + alignbytes + sizeof(mem_align_cb_t);
+    union
+    {
+        void *pointer_value;
+        uint32_t unsigned_value;
+    } p_align_addr, p_addr;
+
+    p_addr.pointer_value = malloc(alignedsize);
+
+    if (p_addr.pointer_value == NULL)
+    {
+        return NULL;
+    }
+
+    p_align_addr.unsigned_value = SDK_SIZEALIGN(p_addr.unsigned_value + sizeof(mem_align_cb_t), alignbytes);
+
+    p_cb             = (mem_align_cb_t *)(p_align_addr.unsigned_value - 4U);
+    p_cb->identifier = SDK_MEM_MAGIC_NUMBER;
+    p_cb->offset     = (uint16_t)(p_align_addr.unsigned_value - p_addr.unsigned_value);
+
+    return p_align_addr.pointer_value;
+}
+
+void SDK_Free(void *ptr)
+{
+    union
+    {
+        void *pointer_value;
+        uint32_t unsigned_value;
+    } p_free;
+    p_free.pointer_value = ptr;
+    mem_align_cb_t *p_cb = (mem_align_cb_t *)(p_free.unsigned_value - 4U);
+
+    if (p_cb->identifier != SDK_MEM_MAGIC_NUMBER)
+    {
+        return;
+    }
+
+    p_free.unsigned_value = p_free.unsigned_value - p_cb->offset;
+
+    free(p_free.pointer_value);
+}
+
+/*!
+ * @brief Delay function bases on while loop, every loop includes three instructions.
+ *
+ * @param count  Counts of loop needed for dalay.
+ */
+#ifndef __XCC__
+#if defined(__CC_ARM) /* This macro is arm v5 specific */
+/* clang-format off */
+__ASM static void DelayLoop(uint32_t count)
+{
+loop
+    SUBS R0, R0, #1
+    CMP  R0, #0
+    BNE  loop
+    BX   LR
+}
+/* clang-format on */
+#elif defined(__ARMCC_VERSION) || defined(__ICCARM__) || defined(__GNUC__)
+/* Cortex-M0 has a smaller instruction set, SUBS isn't supported in thumb-16 mode reported from __GNUC__ compiler,
+ * use SUB and CMP here for compatibility */
+static void DelayLoop(uint32_t count)
+{
+    __ASM volatile("    MOV    R0, %0" : : "r"(count));
+    __ASM volatile(
+        "loop:                          \n"
+#if defined(__GNUC__) && !defined(__ARMCC_VERSION)
+        "    SUB    R0, R0, #1          \n"
+#else
+        "    SUBS   R0, R0, #1          \n"
+#endif
+        "    CMP    R0, #0              \n"
+
+        "    BNE    loop                \n");
+}
+#endif /* defined(__CC_ARM) */
+
+/*!
+ * @brief Delay at least for some time.
+ *  Please note that, this API uses while loop for delay, different run-time environments make the time not precise,
+ *  if precise delay count was needed, please implement a new delay function with hardware timer.
+ *
+ * @param delay_us  Delay time in unit of microsecond.
+ * @param coreClock_Hz  Core clock frequency with Hz.
+ */
+void SDK_DelayAtLeastUs(uint32_t delay_us, uint32_t coreClock_Hz)
+{
+    assert(0U != delay_us);
+    uint64_t count = USEC_TO_COUNT(delay_us, coreClock_Hz);
+    assert(count <= UINT32_MAX);
+
+    /* Divide value may be different in various environment to ensure delay is precise.
+     * Every loop count includes three instructions, due to Cortex-M7 sometimes executes
+     * two instructions in one period, through test here set divide 2. Other M cores use
+     * divide 4. By the way, divide 2 or 4 could let odd count lost precision, but it does
+     * not matter because other instructions outside while loop is enough to fill the time.
+     */
+#if (__CORTEX_M == 7)
+    count = count / 2U;
+#else
+    count = count / 4U;
+#endif
+    DelayLoop((uint32_t)count);
+}
+#endif

FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/drivers/fsl_common.h

@@ -0,0 +1,648 @@
+/*
+ * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2019 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_COMMON_H_
+#define _FSL_COMMON_H_
+
+#include <assert.h>
+#include <stdbool.h>
+#include <stdint.h>
+#include <string.h>
+#include <stdlib.h>
+
+#if defined(__ICCARM__)
+#include <stddef.h>
+#endif
+
+/*
+ * For CMSIS pack RTE.
+ * CMSIS pack RTE generates "RTC_Components.h" which contains the statements
+ * of the related <RTE_Components_h> element for all selected software components.
+ */
+#ifdef _RTE_
+#include "RTE_Components.h"
+#endif
+
+#include "fsl_device_registers.h"
+
+/*!
+ * @addtogroup ksdk_common
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @brief Construct a status code value from a group and code number. */
+#define MAKE_STATUS(group, code) ((((group)*100) + (code)))
+
+/*! @brief Construct the version number for drivers. */
+#define MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix))
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief common driver version 2.2.2. */
+#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 2, 2))
+/*@}*/
+
+/* Debug console type definition. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_NONE          0U      /*!< No debug console.             */
+#define DEBUG_CONSOLE_DEVICE_TYPE_UART          1U      /*!< Debug console based on UART.   */
+#define DEBUG_CONSOLE_DEVICE_TYPE_LPUART        2U      /*!< Debug console based on LPUART. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_LPSCI         3U      /*!< Debug console based on LPSCI.  */
+#define DEBUG_CONSOLE_DEVICE_TYPE_USBCDC        4U      /*!< Debug console based on USBCDC. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM      5U      /*!< Debug console based on FLEXCOMM. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_IUART         6U      /*!< Debug console based on i.MX UART. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_VUSART        7U      /*!< Debug console based on LPC_VUSART. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_MINI_USART    8U      /*!< Debug console based on LPC_USART. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_SWO           9U      /*!< Debug console based on SWO. */
+
+/*! @brief Status group numbers. */
+enum _status_groups
+{
+    kStatusGroup_Generic = 0,                 /*!< Group number for generic status codes. */
+    kStatusGroup_FLASH = 1,                   /*!< Group number for FLASH status codes. */
+    kStatusGroup_LPSPI = 4,                   /*!< Group number for LPSPI status codes. */
+    kStatusGroup_FLEXIO_SPI = 5,              /*!< Group number for FLEXIO SPI status codes. */
+    kStatusGroup_DSPI = 6,                    /*!< Group number for DSPI status codes. */
+    kStatusGroup_FLEXIO_UART = 7,             /*!< Group number for FLEXIO UART status codes. */
+    kStatusGroup_FLEXIO_I2C = 8,              /*!< Group number for FLEXIO I2C status codes. */
+    kStatusGroup_LPI2C = 9,                   /*!< Group number for LPI2C status codes. */
+    kStatusGroup_UART = 10,                   /*!< Group number for UART status codes. */
+    kStatusGroup_I2C = 11,                    /*!< Group number for UART status codes. */
+    kStatusGroup_LPSCI = 12,                  /*!< Group number for LPSCI status codes. */
+    kStatusGroup_LPUART = 13,                 /*!< Group number for LPUART status codes. */
+    kStatusGroup_SPI = 14,                    /*!< Group number for SPI status code.*/
+    kStatusGroup_XRDC = 15,                   /*!< Group number for XRDC status code.*/
+    kStatusGroup_SEMA42 = 16,                 /*!< Group number for SEMA42 status code.*/
+    kStatusGroup_SDHC = 17,                   /*!< Group number for SDHC status code */
+    kStatusGroup_SDMMC = 18,                  /*!< Group number for SDMMC status code */
+    kStatusGroup_SAI = 19,                    /*!< Group number for SAI status code */
+    kStatusGroup_MCG = 20,                    /*!< Group number for MCG status codes. */
+    kStatusGroup_SCG = 21,                    /*!< Group number for SCG status codes. */
+    kStatusGroup_SDSPI = 22,                  /*!< Group number for SDSPI status codes. */
+    kStatusGroup_FLEXIO_I2S = 23,             /*!< Group number for FLEXIO I2S status codes */
+    kStatusGroup_FLEXIO_MCULCD = 24,          /*!< Group number for FLEXIO LCD status codes */
+    kStatusGroup_FLASHIAP = 25,               /*!< Group number for FLASHIAP status codes */
+    kStatusGroup_FLEXCOMM_I2C = 26,           /*!< Group number for FLEXCOMM I2C status codes */
+    kStatusGroup_I2S = 27,                    /*!< Group number for I2S status codes */
+    kStatusGroup_IUART = 28,                  /*!< Group number for IUART status codes */
+    kStatusGroup_CSI = 29,                    /*!< Group number for CSI status codes */
+    kStatusGroup_MIPI_DSI = 30,               /*!< Group number for MIPI DSI status codes */
+    kStatusGroup_SDRAMC = 35,                 /*!< Group number for SDRAMC status codes. */
+    kStatusGroup_POWER = 39,                  /*!< Group number for POWER status codes. */
+    kStatusGroup_ENET = 40,                   /*!< Group number for ENET status codes. */
+    kStatusGroup_PHY = 41,                    /*!< Group number for PHY status codes. */
+    kStatusGroup_TRGMUX = 42,                 /*!< Group number for TRGMUX status codes. */
+    kStatusGroup_SMARTCARD = 43,              /*!< Group number for SMARTCARD status codes. */
+    kStatusGroup_LMEM = 44,                   /*!< Group number for LMEM status codes. */
+    kStatusGroup_QSPI = 45,                   /*!< Group number for QSPI status codes. */
+    kStatusGroup_DMA = 50,                    /*!< Group number for DMA status codes. */
+    kStatusGroup_EDMA = 51,                   /*!< Group number for EDMA status codes. */
+    kStatusGroup_DMAMGR = 52,                 /*!< Group number for DMAMGR status codes. */
+    kStatusGroup_FLEXCAN = 53,                /*!< Group number for FlexCAN status codes. */
+    kStatusGroup_LTC = 54,                    /*!< Group number for LTC status codes. */
+    kStatusGroup_FLEXIO_CAMERA = 55,          /*!< Group number for FLEXIO CAMERA status codes. */
+    kStatusGroup_LPC_SPI = 56,                /*!< Group number for LPC_SPI status codes. */
+    kStatusGroup_LPC_USART = 57,              /*!< Group number for LPC_USART status codes. */
+    kStatusGroup_DMIC = 58,                   /*!< Group number for DMIC status codes. */
+    kStatusGroup_SDIF = 59,                   /*!< Group number for SDIF status codes.*/
+    kStatusGroup_SPIFI = 60,                  /*!< Group number for SPIFI status codes. */
+    kStatusGroup_OTP = 61,                    /*!< Group number for OTP status codes. */
+    kStatusGroup_MCAN = 62,                   /*!< Group number for MCAN status codes. */
+    kStatusGroup_CAAM = 63,                   /*!< Group number for CAAM status codes. */
+    kStatusGroup_ECSPI = 64,                  /*!< Group number for ECSPI status codes. */
+    kStatusGroup_USDHC = 65,                  /*!< Group number for USDHC status codes.*/
+    kStatusGroup_LPC_I2C = 66,                /*!< Group number for LPC_I2C status codes.*/
+    kStatusGroup_DCP = 67,                    /*!< Group number for DCP status codes.*/
+    kStatusGroup_MSCAN = 68,                  /*!< Group number for MSCAN status codes.*/
+    kStatusGroup_ESAI = 69,                   /*!< Group number for ESAI status codes. */
+    kStatusGroup_FLEXSPI = 70,                /*!< Group number for FLEXSPI status codes. */
+    kStatusGroup_MMDC = 71,                   /*!< Group number for MMDC status codes. */
+    kStatusGroup_PDM = 72,                    /*!< Group number for MIC status codes. */
+    kStatusGroup_SDMA = 73,                   /*!< Group number for SDMA status codes. */
+    kStatusGroup_ICS = 74,                    /*!< Group number for ICS status codes. */
+    kStatusGroup_SPDIF = 75,                  /*!< Group number for SPDIF status codes. */
+    kStatusGroup_LPC_MINISPI = 76,            /*!< Group number for LPC_MINISPI status codes. */
+    kStatusGroup_HASHCRYPT = 77,              /*!< Group number for Hashcrypt status codes */
+    kStatusGroup_LPC_SPI_SSP = 78,            /*!< Group number for LPC_SPI_SSP status codes. */
+    kStatusGroup_I3C = 79,                    /*!< Group number for I3C status codes */
+    kStatusGroup_LPC_I2C_1 = 97,              /*!< Group number for LPC_I2C_1 status codes. */
+    kStatusGroup_NOTIFIER = 98,               /*!< Group number for NOTIFIER status codes. */
+    kStatusGroup_DebugConsole = 99,           /*!< Group number for debug console status codes. */
+    kStatusGroup_SEMC = 100,                  /*!< Group number for SEMC status codes. */
+    kStatusGroup_ApplicationRangeStart = 101, /*!< Starting number for application groups. */
+    kStatusGroup_IAP = 102,                   /*!< Group number for IAP status codes */
+
+    kStatusGroup_HAL_GPIO = 121,              /*!< Group number for HAL GPIO status codes. */
+    kStatusGroup_HAL_UART = 122,              /*!< Group number for HAL UART status codes. */
+    kStatusGroup_HAL_TIMER = 123,             /*!< Group number for HAL TIMER status codes. */
+    kStatusGroup_HAL_SPI = 124,               /*!< Group number for HAL SPI status codes. */
+    kStatusGroup_HAL_I2C = 125,               /*!< Group number for HAL I2C status codes. */
+    kStatusGroup_HAL_FLASH = 126,             /*!< Group number for HAL FLASH status codes. */
+    kStatusGroup_HAL_PWM = 127,               /*!< Group number for HAL PWM status codes. */
+    kStatusGroup_HAL_RNG = 128,               /*!< Group number for HAL RNG status codes. */
+    kStatusGroup_TIMERMANAGER = 135,          /*!< Group number for TiMER MANAGER status codes. */
+    kStatusGroup_SERIALMANAGER = 136,         /*!< Group number for SERIAL MANAGER status codes. */
+    kStatusGroup_LED = 137,                   /*!< Group number for LED status codes. */
+    kStatusGroup_BUTTON = 138,                /*!< Group number for BUTTON status codes. */
+    kStatusGroup_EXTERN_EEPROM = 139,         /*!< Group number for EXTERN EEPROM status codes. */
+    kStatusGroup_SHELL = 140,                 /*!< Group number for SHELL status codes. */
+    kStatusGroup_MEM_MANAGER = 141,           /*!< Group number for MEM MANAGER status codes. */
+    kStatusGroup_LIST = 142,                  /*!< Group number for List status codes. */
+    kStatusGroup_OSA = 143,                   /*!< Group number for OSA status codes. */
+    kStatusGroup_COMMON_TASK = 144,           /*!< Group number for Common task status codes. */
+    kStatusGroup_MSG = 145,                   /*!< Group number for messaging status codes. */
+    kStatusGroup_SDK_OCOTP = 146,             /*!< Group number for OCOTP status codes. */
+    kStatusGroup_SDK_FLEXSPINOR = 147,        /*!< Group number for FLEXSPINOR status codes.*/
+    kStatusGroup_CODEC = 148,                 /*!< Group number for codec status codes. */
+    kStatusGroup_ASRC = 149,                 /*!< Group number for codec status ASRC. */
+    kStatusGroup_OTFAD = 150,                 /*!< Group number for codec status codes. */
+};
+
+/*! @brief Generic status return codes. */
+enum
+{
+    kStatus_Success = MAKE_STATUS(kStatusGroup_Generic, 0),
+    kStatus_Fail = MAKE_STATUS(kStatusGroup_Generic, 1),
+    kStatus_ReadOnly = MAKE_STATUS(kStatusGroup_Generic, 2),
+    kStatus_OutOfRange = MAKE_STATUS(kStatusGroup_Generic, 3),
+    kStatus_InvalidArgument = MAKE_STATUS(kStatusGroup_Generic, 4),
+    kStatus_Timeout = MAKE_STATUS(kStatusGroup_Generic, 5),
+    kStatus_NoTransferInProgress = MAKE_STATUS(kStatusGroup_Generic, 6),
+};
+
+/*! @brief Type used for all status and error return values. */
+typedef int32_t status_t;
+
+/*
+ * Macro guard for whether to use default weak IRQ implementation in drivers
+ */
+#ifndef FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ
+#define FSL_DRIVER_TRANSFER_DOUBLE_WEAK_IRQ 1
+#endif
+
+/*! @name Min/max macros */
+/* @{ */
+#if !defined(MIN)
+#define MIN(a, b) (((a) < (b)) ? (a) : (b))
+#endif
+
+#if !defined(MAX)
+#define MAX(a, b) (((a) > (b)) ? (a) : (b))
+#endif
+/* @} */
+
+/*! @brief Computes the number of elements in an array. */
+#if !defined(ARRAY_SIZE)
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+#endif
+
+/*! @name UINT16_MAX/UINT32_MAX value */
+/* @{ */
+#if !defined(UINT16_MAX)
+#define UINT16_MAX ((uint16_t)-1)
+#endif
+
+#if !defined(UINT32_MAX)
+#define UINT32_MAX ((uint32_t)-1)
+#endif
+/* @} */
+
+/*! @name Timer utilities */
+/* @{ */
+/*! Macro to convert a microsecond period to raw count value */
+#define USEC_TO_COUNT(us, clockFreqInHz) (uint64_t)(((uint64_t)(us) * (clockFreqInHz)) / 1000000U)
+/*! Macro to convert a raw count value to microsecond */
+#define COUNT_TO_USEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000000U / clockFreqInHz)
+
+/*! Macro to convert a millisecond period to raw count value */
+#define MSEC_TO_COUNT(ms, clockFreqInHz) (uint64_t)((uint64_t)ms * clockFreqInHz / 1000U)
+/*! Macro to convert a raw count value to millisecond */
+#define COUNT_TO_MSEC(count, clockFreqInHz) (uint64_t)((uint64_t)count * 1000U / clockFreqInHz)
+/* @} */
+
+/*! @name Alignment variable definition macros */
+/* @{ */
+#if (defined(__ICCARM__))
+/**
+ * Workaround to disable MISRA C message suppress warnings for IAR compiler.
+ * http:/ /supp.iar.com/Support/?note=24725
+ */
+_Pragma("diag_suppress=Pm120")
+#define SDK_PRAGMA(x) _Pragma(#x)
+    _Pragma("diag_error=Pm120")
+/*! Macro to define a variable with alignbytes alignment */
+#define SDK_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var
+/*! Macro to define a variable with L1 d-cache line size alignment */
+#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
+#define SDK_L1DCACHE_ALIGN(var) SDK_PRAGMA(data_alignment = FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) var
+#endif
+/*! Macro to define a variable with L2 cache line size alignment */
+#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
+#define SDK_L2CACHE_ALIGN(var) SDK_PRAGMA(data_alignment = FSL_FEATURE_L2CACHE_LINESIZE_BYTE) var
+#endif
+#elif defined(__CC_ARM) || defined(__ARMCC_VERSION)
+/*! Macro to define a variable with alignbytes alignment */
+#define SDK_ALIGN(var, alignbytes) __attribute__((aligned(alignbytes))) var
+/*! Macro to define a variable with L1 d-cache line size alignment */
+#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
+#define SDK_L1DCACHE_ALIGN(var) __attribute__((aligned(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE))) var
+#endif
+/*! Macro to define a variable with L2 cache line size alignment */
+#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
+#define SDK_L2CACHE_ALIGN(var) __attribute__((aligned(FSL_FEATURE_L2CACHE_LINESIZE_BYTE))) var
+#endif
+#elif defined(__GNUC__)
+/*! Macro to define a variable with alignbytes alignment */
+#define SDK_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes)))
+/*! Macro to define a variable with L1 d-cache line size alignment */
+#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
+#define SDK_L1DCACHE_ALIGN(var) var __attribute__((aligned(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)))
+#endif
+/*! Macro to define a variable with L2 cache line size alignment */
+#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
+#define SDK_L2CACHE_ALIGN(var) var __attribute__((aligned(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)))
+#endif
+#else
+#error Toolchain not supported
+#define SDK_ALIGN(var, alignbytes) var
+#if defined(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE)
+#define SDK_L1DCACHE_ALIGN(var) var
+#endif
+#if defined(FSL_FEATURE_L2CACHE_LINESIZE_BYTE)
+#define SDK_L2CACHE_ALIGN(var) var
+#endif
+#endif
+
+/*! Macro to change a value to a given size aligned value */
+#define SDK_SIZEALIGN(var, alignbytes) \
+    ((unsigned int)((var) + ((alignbytes)-1U)) & (unsigned int)(~(unsigned int)((alignbytes)-1U)))
+/* @} */
+
+/*! @name Non-cacheable region definition macros */
+/* For initialized non-zero non-cacheable variables, please using "AT_NONCACHEABLE_SECTION_INIT(var) ={xx};" or
+ * "AT_NONCACHEABLE_SECTION_ALIGN_INIT(var) ={xx};" in your projects to define them, for zero-inited non-cacheable variables,
+ * please using "AT_NONCACHEABLE_SECTION(var);" or "AT_NONCACHEABLE_SECTION_ALIGN(var);" to define them, these zero-inited variables
+ * will be initialized to zero in system startup.
+ */
+/* @{ */
+#if (defined(__ICCARM__))
+#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE))
+#define AT_NONCACHEABLE_SECTION(var) var @"NonCacheable"
+#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable"
+#define AT_NONCACHEABLE_SECTION_INIT(var) var @"NonCacheable.init"
+#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var @"NonCacheable.init"
+#else
+#define AT_NONCACHEABLE_SECTION(var) var
+#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var
+#define AT_NONCACHEABLE_SECTION_INIT(var) var
+#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) SDK_PRAGMA(data_alignment = alignbytes) var
+#endif
+#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION))
+#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE))
+#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var
+#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \
+    __attribute__((section("NonCacheable.init"))) __attribute__((aligned(alignbytes))) var
+#if(defined(__CC_ARM))
+#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable"), zero_init)) var
+#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \
+    __attribute__((section("NonCacheable"), zero_init)) __attribute__((aligned(alignbytes))) var
+#else
+#define AT_NONCACHEABLE_SECTION(var) __attribute__((section(".bss.NonCacheable"))) var
+#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \
+    __attribute__((section(".bss.NonCacheable"))) __attribute__((aligned(alignbytes))) var
+#endif
+#else
+#define AT_NONCACHEABLE_SECTION(var) var
+#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) __attribute__((aligned(alignbytes))) var
+#define AT_NONCACHEABLE_SECTION_INIT(var) var
+#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) __attribute__((aligned(alignbytes))) var
+#endif
+#elif(defined(__XCC__))
+#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var
+#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \
+    __attribute__((section("NonCacheable.init"))) var __attribute__((aligned(alignbytes)))
+#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable"))) var
+#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \
+    __attribute__((section("NonCacheable"))) var __attribute__((aligned(alignbytes)))
+#elif(defined(__GNUC__))
+/* For GCC, when the non-cacheable section is required, please define "__STARTUP_INITIALIZE_NONCACHEDATA"
+ * in your projects to make sure the non-cacheable section variables will be initialized in system startup.
+ */
+#if ((!(defined(FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION) && FSL_FEATURE_HAS_NO_NONCACHEABLE_SECTION)) && defined(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE))
+#define AT_NONCACHEABLE_SECTION_INIT(var) __attribute__((section("NonCacheable.init"))) var
+#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) \
+    __attribute__((section("NonCacheable.init"))) var __attribute__((aligned(alignbytes)))
+#define AT_NONCACHEABLE_SECTION(var) __attribute__((section("NonCacheable,\"aw\",%nobits @"))) var
+#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) \
+    __attribute__((section("NonCacheable,\"aw\",%nobits @"))) var __attribute__((aligned(alignbytes)))
+#else
+#define AT_NONCACHEABLE_SECTION(var) var
+#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) var __attribute__((aligned(alignbytes)))
+#define AT_NONCACHEABLE_SECTION_INIT(var) var
+#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) var __attribute__((aligned(alignbytes)))
+#endif
+#else
+#error Toolchain not supported.
+#define AT_NONCACHEABLE_SECTION(var) var
+#define AT_NONCACHEABLE_SECTION_ALIGN(var, alignbytes) var
+#define AT_NONCACHEABLE_SECTION_INIT(var) var
+#define AT_NONCACHEABLE_SECTION_ALIGN_INIT(var, alignbytes) var
+#endif
+/* @} */
+
+/*! @name Time sensitive region */
+/* @{ */
+#if defined(FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE) && FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE
+#if (defined(__ICCARM__))
+#define AT_QUICKACCESS_SECTION_CODE(func) func @"CodeQuickAccess"
+#define AT_QUICKACCESS_SECTION_DATA(func) func @"DataQuickAccess"
+#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION))
+#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"), __noinline__)) func
+#define AT_QUICKACCESS_SECTION_DATA(func) __attribute__((section("DataQuickAccess"))) func
+#elif(defined(__GNUC__))
+#define AT_QUICKACCESS_SECTION_CODE(func) __attribute__((section("CodeQuickAccess"), __noinline__)) func
+#define AT_QUICKACCESS_SECTION_DATA(func) __attribute__((section("DataQuickAccess"))) func
+#else
+#error Toolchain not supported.
+#endif /* defined(__ICCARM__) */
+#else
+#if (defined(__ICCARM__))
+#define AT_QUICKACCESS_SECTION_CODE(func) func
+#define AT_QUICKACCESS_SECTION_DATA(func) func
+#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION))
+#define AT_QUICKACCESS_SECTION_CODE(func) func
+#define AT_QUICKACCESS_SECTION_DATA(func) func
+#elif(defined(__GNUC__))
+#define AT_QUICKACCESS_SECTION_CODE(func) func
+#define AT_QUICKACCESS_SECTION_DATA(func) func
+#else
+#error Toolchain not supported.
+#endif
+#endif /* __FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE */
+/* @} */
+
+/*! @name Ram Function */
+#if (defined(__ICCARM__))
+#define RAMFUNCTION_SECTION_CODE(func) func @"RamFunction"
+#elif(defined(__CC_ARM) || defined(__ARMCC_VERSION))
+#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func
+#elif(defined(__GNUC__))
+#define RAMFUNCTION_SECTION_CODE(func) __attribute__((section("RamFunction"))) func
+#else
+#error Toolchain not supported.
+#endif /* defined(__ICCARM__) */
+/* @} */
+
+/*! @name Suppress fallthrough warning macro */
+/* For switch case code block, if case section ends without "break;" statement, there wil be
+ fallthrough warning with compiler flag -Wextra or -Wimplicit-fallthrough=n when using armgcc.
+ To suppress this warning, "SUPPRESS_FALL_THROUGH_WARNING();" need to be added at the end of each
+ case section which misses "break;"statement.
+ */
+/* @{ */
+#if defined(__GNUC__) && !defined(__ARMCC_VERSION)
+#define SUPPRESS_FALL_THROUGH_WARNING() __attribute__ ((fallthrough))
+#else
+#define SUPPRESS_FALL_THROUGH_WARNING()
+#endif
+/* @} */
+
+#if defined ( __ARMCC_VERSION ) && ( __ARMCC_VERSION >= 6010050 )
+void DefaultISR(void);
+#endif
+/*
+ * The fsl_clock.h is included here because it needs MAKE_VERSION/MAKE_STATUS/status_t
+ * defined in previous of this file.
+ */
+#include "fsl_clock.h"
+
+/*
+ * Chip level peripheral reset API, for MCUs that implement peripheral reset control external to a peripheral
+ */
+#if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) || \
+     (defined(FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT) && (FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT > 0)))
+#include "fsl_reset.h"
+#endif
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+        extern "C"
+{
+#endif
+
+    /*!
+     * @brief Enable specific interrupt.
+     *
+     * Enable LEVEL1 interrupt. For some devices, there might be multiple interrupt
+     * levels. For example, there are NVIC and intmux. Here the interrupts connected
+     * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly.
+     * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed
+     * to NVIC first then routed to core.
+     *
+     * This function only enables the LEVEL1 interrupts. The number of LEVEL1 interrupts
+     * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.
+     *
+     * @param interrupt The IRQ number.
+     * @retval kStatus_Success Interrupt enabled successfully
+     * @retval kStatus_Fail Failed to enable the interrupt
+     */
+    static inline status_t EnableIRQ(IRQn_Type interrupt)
+    {
+        if (NotAvail_IRQn == interrupt)
+        {
+            return kStatus_Fail;
+        }
+
+#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0)
+        if (interrupt >= FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS)
+        {
+            return kStatus_Fail;
+        }
+#endif
+
+#if defined(__GIC_PRIO_BITS)
+        GIC_EnableIRQ(interrupt);
+#else
+        NVIC_EnableIRQ(interrupt);
+#endif
+        return kStatus_Success;
+    }
+
+    /*!
+     * @brief Disable specific interrupt.
+     *
+     * Disable LEVEL1 interrupt. For some devices, there might be multiple interrupt
+     * levels. For example, there are NVIC and intmux. Here the interrupts connected
+     * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly.
+     * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed
+     * to NVIC first then routed to core.
+     *
+     * This function only disables the LEVEL1 interrupts. The number of LEVEL1 interrupts
+     * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.
+     *
+     * @param interrupt The IRQ number.
+     * @retval kStatus_Success Interrupt disabled successfully
+     * @retval kStatus_Fail Failed to disable the interrupt
+     */
+    static inline status_t DisableIRQ(IRQn_Type interrupt)
+    {
+        if (NotAvail_IRQn == interrupt)
+        {
+            return kStatus_Fail;
+        }
+
+#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0)
+        if (interrupt >= FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS)
+        {
+            return kStatus_Fail;
+        }
+#endif
+
+#if defined(__GIC_PRIO_BITS)
+        GIC_DisableIRQ(interrupt);
+#else
+    NVIC_DisableIRQ(interrupt);
+#endif
+        return kStatus_Success;
+    }
+
+    /*!
+     * @brief Disable the global IRQ
+     *
+     * Disable the global interrupt and return the current primask register. User is required to provided the primask
+     * register for the EnableGlobalIRQ().
+     *
+     * @return Current primask value.
+     */
+    static inline uint32_t DisableGlobalIRQ(void)
+    {
+#if defined (__XCC__)
+        return 0;
+#else
+#if defined(CPSR_I_Msk)
+        uint32_t cpsr = __get_CPSR() & CPSR_I_Msk;
+
+        __disable_irq();
+
+        return cpsr;
+#else
+    uint32_t regPrimask = __get_PRIMASK();
+
+    __disable_irq();
+
+    return regPrimask;
+#endif
+#endif
+    }
+
+    /*!
+     * @brief Enable the global IRQ
+     *
+     * Set the primask register with the provided primask value but not just enable the primask. The idea is for the
+     * convenience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to
+     * use the EnableGlobalIRQ() and DisableGlobalIRQ() in pair.
+     *
+     * @param primask value of primask register to be restored. The primask value is supposed to be provided by the
+     * DisableGlobalIRQ().
+     */
+    static inline void EnableGlobalIRQ(uint32_t primask)
+    {
+#if defined (__XCC__)
+#else
+#if defined(CPSR_I_Msk)
+        __set_CPSR((__get_CPSR() & ~CPSR_I_Msk) | primask);
+#else
+    __set_PRIMASK(primask);
+#endif
+#endif
+    }
+
+#if defined(ENABLE_RAM_VECTOR_TABLE)
+    /*!
+     * @brief install IRQ handler
+     *
+     * @param irq IRQ number
+     * @param irqHandler IRQ handler address
+     * @return The old IRQ handler address
+     */
+    uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler);
+#endif /* ENABLE_RAM_VECTOR_TABLE. */
+
+#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0))
+    /*!
+     * @brief Enable specific interrupt for wake-up from deep-sleep mode.
+     *
+     * Enable the interrupt for wake-up from deep sleep mode.
+     * Some interrupts are typically used in sleep mode only and will not occur during
+     * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable
+     * those clocks (significantly increasing power consumption in the reduced power mode),
+     * making these wake-ups possible.
+     *
+     * @note This function also enables the interrupt in the NVIC (EnableIRQ() is called internaly).
+     *
+     * @param interrupt The IRQ number.
+     */
+    void EnableDeepSleepIRQ(IRQn_Type interrupt);
+
+    /*!
+     * @brief Disable specific interrupt for wake-up from deep-sleep mode.
+     *
+     * Disable the interrupt for wake-up from deep sleep mode.
+     * Some interrupts are typically used in sleep mode only and will not occur during
+     * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable
+     * those clocks (significantly increasing power consumption in the reduced power mode),
+     * making these wake-ups possible.
+     *
+     * @note This function also disables the interrupt in the NVIC (DisableIRQ() is called internaly).
+     *
+     * @param interrupt The IRQ number.
+     */
+    void DisableDeepSleepIRQ(IRQn_Type interrupt);
+#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */
+
+    /*!
+     * @brief Allocate memory with given alignment and aligned size.
+     *
+     * This is provided to support the dynamically allocated memory
+     * used in cache-able region.
+     * @param size The length required to malloc.
+     * @param alignbytes The alignment size.
+     * @retval The allocated memory.
+     */
+    void *SDK_Malloc(size_t size, size_t alignbytes);
+
+    /*!
+     * @brief Free memory.
+     *
+     * @param ptr The memory to be release.
+     */
+    void SDK_Free(void *ptr);
+
+    /*!
+    * @brief Delay at least for some time.
+    *  Please note that, this API uses while loop for delay, different run-time environments make the time not precise,
+    *  if precise delay count was needed, please implement a new delay function with hardware timer.
+    *
+    * @param delay_us  Delay time in unit of microsecond.
+    * @param coreClock_Hz  Core clock frequency with Hz.
+    */
+    void SDK_DelayAtLeastUs(uint32_t delay_us, uint32_t coreClock_Hz);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @} */
+
+#endif /* _FSL_COMMON_H_ */

FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/drivers/fsl_emc.c

@@ -0,0 +1,445 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2019 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_emc.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.emc"
+#endif
+
+/*! @brief Define macros for EMC driver. */
+#define EMC_REFRESH_CLOCK_PARAM (16U)
+#define EMC_SDRAM_WAIT_CYCLES (2000U)
+#define EMC_DYNCTL_COLUMNBASE_OFFSET (0U)
+#define EMC_DYNCTL_COLUMNBASE_MASK (0x3U)
+#define EMC_DYNCTL_COLUMNPLUS_OFFSET (3U)
+#define EMC_DYNCTL_COLUMNPLUS_MASK (0x18U)
+#define EMC_DYNCTL_BUSWIDTH_MASK (0x80U)
+#define EMC_DYNCTL_BUSADDRMAP_MASK (0x20U)
+#define EMC_DYNCTL_DEVBANKS_BITS_MASK (0x1cU)
+#define EMC_SDRAM_BANKCS_BA0_MASK (uint32_t)(0x2000)
+#define EMC_SDRAM_BANKCS_BA1_MASK (uint32_t)(0x4000)
+#define EMC_SDRAM_BANKCS_BA_MASK (EMC_SDRAM_BANKCS_BA0_MASK | EMC_SDRAM_BANKCS_BA1_MASK)
+#define EMC_DIV_ROUND_UP(n, m) (((n) + (m)-1U) / (m))
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+/*!
+ * @brief Get instance number for EMC module.
+ *
+ * @param base EMC peripheral base address
+ */
+static uint32_t EMC_GetInstance(EMC_Type *base);
+
+/*!
+ * @brief Get the clock cycles of EMC clock.
+ * The function is used to calculate the multiple of the
+ * 16 EMCCLKs between the timer_Ns period.
+ *
+ * @param base EMC peripheral base address
+ * @param timer_Ns The timer/period in unit of nanosecond
+ * @param plus The plus added to the register settings to reach the calculated cycles.
+ * @return The calculated cycles.
+ */
+static uint32_t EMC_CalculateTimerCycles(EMC_Type *base, uint32_t timer_Ns, uint32_t plus);
+
+/*!
+ * @brief Get the shift value to shift the mode register content by.
+ *
+ * @param addrMap EMC address map for the dynamic memory configuration.
+ *                It is the bit 14 ~ bit 7 of the EMC_DYNAMICCONFIG.
+ * @return The offset value to shift the mode register content by.
+ */
+static uint32_t EMC_ModeOffset(uint32_t addrMap);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+/*! @brief Pointers to EMC clocks for each instance. */
+static const clock_ip_name_t s_EMCClock[FSL_FEATURE_SOC_EMC_COUNT] = EMC_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+#if !(defined(FSL_FEATURE_EMC_HAS_NO_RESET) && FSL_FEATURE_EMC_HAS_NO_RESET)
+/*! @brief Pointers to EMC resets for each instance. */
+static const reset_ip_name_t s_emcResets[] = EMC_RSTS;
+#endif
+
+/*! @brief Pointers to EMC bases for each instance. */
+static const EMC_Type *const s_EMCBases[] = EMC_BASE_PTRS;
+
+/*! @brief Define the start address for each chip controlled by EMC. */
+static const uint32_t s_EMCDYCSBases[] = EMC_DYCS_ADDRESS;
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+static uint32_t EMC_GetInstance(EMC_Type *base)
+{
+    uint32_t instance;
+
+    /* Find the instance index from base address mappings. */
+    for (instance = 0; instance < ARRAY_SIZE(s_EMCBases); instance++)
+    {
+        if (s_EMCBases[instance] == base)
+        {
+            break;
+        }
+    }
+
+    assert(instance < ARRAY_SIZE(s_EMCBases));
+
+    return instance;
+}
+
+static uint32_t EMC_CalculateTimerCycles(EMC_Type *base, uint32_t timer_Ns, uint32_t plus)
+{
+    uint32_t cycles;
+
+    cycles = CLOCK_GetEmcClkFreq() / EMC_HZ_ONEMHZ * timer_Ns;
+    cycles = EMC_DIV_ROUND_UP(cycles, EMC_MILLISECS_ONESEC); /* Round up. */
+
+    /* Decrese according to the plus. */
+    if (cycles >= plus)
+    {
+        cycles = cycles - plus;
+    }
+    else
+    {
+        cycles = 0;
+    }
+
+    return cycles;
+}
+
+static uint32_t EMC_ModeOffset(uint32_t addrMap)
+{
+    uint8_t offset     = 0;
+    uint32_t columbase = addrMap & EMC_DYNCTL_COLUMNBASE_MASK;
+
+    /* First calculate the column length. */
+    if (columbase == 2U)
+    {
+        offset = 8;
+    }
+    else
+    {
+        if (0U == columbase)
+        {
+            offset = 9;
+        }
+        else
+        {
+            offset = 8;
+        }
+
+        /* Add column length increase check. */
+        offset += (uint8_t)((addrMap & EMC_DYNCTL_COLUMNPLUS_MASK) >> EMC_DYNCTL_COLUMNPLUS_OFFSET);
+    }
+
+    /* Add Buswidth/16. */
+    if (0U != (addrMap & EMC_DYNCTL_BUSWIDTH_MASK))
+    {
+        offset += 2U;
+    }
+    else
+    {
+        offset += 1U;
+    }
+
+    /* Add bank select bit if the sdram address map mode is RBC(row-bank-column) mode. */
+    if (0U == (addrMap & EMC_DYNCTL_BUSADDRMAP_MASK))
+    {
+        if (0U == (addrMap & EMC_DYNCTL_DEVBANKS_BITS_MASK))
+        {
+            offset += 1U;
+        }
+        else
+        {
+            offset += 2U;
+        }
+    }
+
+    return offset;
+}
+
+/*!
+ * brief Initializes the basic for EMC.
+ * This function ungates the EMC clock, initializes the emc system configure
+ * and enable the EMC module. This function must be called in the first step to initialize
+ * the external memory.
+ *
+ * param base EMC peripheral base address.
+ * param config The EMC basic configuration.
+ */
+void EMC_Init(EMC_Type *base, emc_basic_config_t *config)
+{
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Enable the clock. */
+    CLOCK_EnableClock((s_EMCClock[EMC_GetInstance(base)]));
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+#if !(defined(FSL_FEATURE_EMC_HAS_NO_RESET) && FSL_FEATURE_EMC_HAS_NO_RESET)
+    /* Reset the EMC module */
+    RESET_PeripheralReset(s_emcResets[EMC_GetInstance(base)]);
+#endif
+
+    /* Reset the EMC. */
+    SYSCON->PRESETCTRL[2] |= SYSCON_PRESETCTRL_EMC_RESET_MASK;
+    SYSCON->PRESETCTRL[2] &= ~SYSCON_PRESETCTRL_EMC_RESET_MASK;
+
+    /* Set the EMC sytem configure. */
+    SYSCON->EMCCLKDIV = SYSCON_EMCCLKDIV_DIV(config->emcClkDiv);
+
+    SYSCON->EMCSYSCTRL = SYSCON_EMCSYSCTRL_EMCFBCLKINSEL(config->fbClkSrc);
+
+    /* Set the endian mode. */
+    base->CONFIG = (uint32_t)config->endian;
+    /* Enable the EMC module with normal memory map mode and normal work mode. */
+    base->CONTROL = EMC_CONTROL_E_MASK;
+}
+
+/*!
+ * brief Initializes the dynamic memory controller.
+ * This function initializes the dynamic memory controller in external memory controller.
+ * This function must be called after EMC_Init and before accessing the external dynamic memory.
+ *
+ * param base EMC peripheral base address.
+ * param timing The timing and latency for dynamica memory controller setting. It shall
+ *        be used for all dynamica memory chips, threfore the worst timing value for all
+ *        used chips must be given.
+ * param configure The EMC dynamic memory controller chip independent configuration pointer.
+ *       This configuration pointer is actually pointer to a configration array. the array number
+ *       depends on the "totalChips".
+ * param totalChips The total dynamic memory chip numbers been used or the length of the
+ *        "emc_dynamic_chip_config_t" type memory.
+ */
+void EMC_DynamicMemInit(EMC_Type *base,
+                        emc_dynamic_timing_config_t *timing,
+                        emc_dynamic_chip_config_t *config,
+                        uint32_t totalChips)
+{
+    assert(NULL != config);
+    assert(NULL != timing);
+    assert(totalChips <= EMC_DYNAMIC_MEMDEV_NUM);
+
+    uint32_t count;
+    uint32_t casLatency;
+    uint32_t addr;
+    uint32_t offset;
+    uint32_t data;
+    emc_dynamic_chip_config_t *dynamicConfig = config;
+
+    /* Setting for dynamic memory controller chip independent configuration. */
+    for (count = 0; (count < totalChips); count++)
+    {
+        if (NULL == dynamicConfig)
+        {
+            break;
+        }
+        else
+        {
+            base->DYNAMIC[dynamicConfig->chipIndex].DYNAMICCONFIG =
+                EMC_DYNAMIC_DYNAMICCONFIG_MD(dynamicConfig->dynamicDevice) | EMC_ADDRMAP(dynamicConfig->devAddrMap);
+            /* Abstract CAS latency from the sdram mode reigster setting values. */
+            casLatency = ((uint32_t)dynamicConfig->sdramModeReg & EMC_SDRAM_MODE_CL_MASK) >> EMC_SDRAM_MODE_CL_SHIFT;
+            base->DYNAMIC[dynamicConfig->chipIndex].DYNAMICRASCAS =
+                EMC_DYNAMIC_DYNAMICRASCAS_RAS(dynamicConfig->rAS_Nclk) | EMC_DYNAMIC_DYNAMICRASCAS_CAS(casLatency);
+
+            dynamicConfig++;
+        }
+    }
+
+    /* Configure the Dynamic Memory controller timing/latency for all chips. */
+    base->DYNAMICREADCONFIG = EMC_DYNAMICREADCONFIG_RD(timing->readConfig);
+    base->DYNAMICRP         = EMC_CalculateTimerCycles(base, timing->tRp_Ns, 1) & EMC_DYNAMICRP_TRP_MASK;
+    base->DYNAMICRAS        = EMC_CalculateTimerCycles(base, timing->tRas_Ns, 1) & EMC_DYNAMICRAS_TRAS_MASK;
+    base->DYNAMICSREX       = EMC_CalculateTimerCycles(base, timing->tSrex_Ns, 1) & EMC_DYNAMICSREX_TSREX_MASK;
+    base->DYNAMICAPR        = EMC_CalculateTimerCycles(base, timing->tApr_Ns, 1) & EMC_DYNAMICAPR_TAPR_MASK;
+    base->DYNAMICDAL        = EMC_CalculateTimerCycles(base, timing->tDal_Ns, 0) & EMC_DYNAMICDAL_TDAL_MASK;
+    base->DYNAMICWR         = EMC_CalculateTimerCycles(base, timing->tWr_Ns, 1) & EMC_DYNAMICWR_TWR_MASK;
+    base->DYNAMICRC         = EMC_CalculateTimerCycles(base, timing->tRc_Ns, 1) & EMC_DYNAMICRC_TRC_MASK;
+    base->DYNAMICRFC        = EMC_CalculateTimerCycles(base, timing->tRfc_Ns, 1) & EMC_DYNAMICRFC_TRFC_MASK;
+    base->DYNAMICXSR        = EMC_CalculateTimerCycles(base, timing->tXsr_Ns, 1) & EMC_DYNAMICXSR_TXSR_MASK;
+    base->DYNAMICRRD        = EMC_CalculateTimerCycles(base, timing->tRrd_Ns, 1) & EMC_DYNAMICRRD_TRRD_MASK;
+    base->DYNAMICMRD        = EMC_DYNAMICMRD_TMRD((timing->tMrd_Nclk > 0U) ? timing->tMrd_Nclk - 1UL : 0UL);
+
+    SDK_DelayAtLeastUs(EMC_SDRAM_NOP_DELAY_US, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
+    /* Step 2. issue nop command. */
+    base->DYNAMICCONTROL = 0x00000183;
+
+    SDK_DelayAtLeastUs(EMC_SDRAM_PRECHARGE_DELAY_US, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
+    /* Step 3. issue precharge all command. */
+    base->DYNAMICCONTROL = 0x00000103;
+
+    /* Step 4. issue two auto-refresh command. */
+    base->DYNAMICREFRESH = 2;
+    SDK_DelayAtLeastUs(EMC_SDRAM_AUTO_REFRESH_DELAY_US, SDK_DEVICE_MAXIMUM_CPU_CLOCK_FREQUENCY);
+
+    base->DYNAMICREFRESH = EMC_CalculateTimerCycles(base, timing->refreshPeriod_Nanosec, 0) / EMC_REFRESH_CLOCK_PARAM;
+
+    /* Step 5. issue a mode command and set the mode value. */
+    base->DYNAMICCONTROL = 0x00000083;
+
+    /* Calculate the mode settings here and to reach the 8 auto-refresh time requirement. */
+    dynamicConfig = config;
+    for (count = 0; (count < totalChips); count++)
+    {
+        if (NULL == dynamicConfig)
+        {
+            break;
+        }
+        else
+        {
+            /* Get the shift value first. */
+            offset = EMC_ModeOffset(dynamicConfig->devAddrMap);
+            addr   = (s_EMCDYCSBases[dynamicConfig->chipIndex] |
+                    ((uint32_t)(dynamicConfig->sdramModeReg & ~EMC_SDRAM_BANKCS_BA_MASK) << offset));
+            /* Set the right mode setting value. */
+            data = *(volatile uint32_t *)addr;
+            data = data;
+            dynamicConfig++;
+        }
+    }
+
+    if (kEMC_Sdram != config->dynamicDevice)
+    {
+        /* Add extended mode register if the low-power sdram is used. */
+        base->DYNAMICCONTROL = 0x00000083;
+        /* Calculate the mode settings for extended mode register. */
+        dynamicConfig = config;
+        for (count = 0; (count < totalChips); count++)
+        {
+            if (NULL == dynamicConfig)
+            {
+                break;
+            }
+            else
+            {
+                /* Get the shift value first. */
+                offset = EMC_ModeOffset(dynamicConfig->devAddrMap);
+                addr   = (s_EMCDYCSBases[dynamicConfig->chipIndex] |
+                        (((uint32_t)(dynamicConfig->sdramExtModeReg & ~EMC_SDRAM_BANKCS_BA_MASK) |
+                          EMC_SDRAM_BANKCS_BA1_MASK)
+                         << offset));
+                /* Set the right mode setting value. */
+                data = *(volatile uint32_t *)addr;
+                data = data;
+                dynamicConfig++;
+            }
+        }
+    }
+
+    /* Step 6. issue normal operation command. */
+    base->DYNAMICCONTROL = 0x00000000; /* Issue NORMAL command */
+
+    /* The buffer shall be disabled when do the sdram initialization and
+     * enabled after the initialization during normal opeation.
+     */
+    dynamicConfig = config;
+    for (count = 0; (count < totalChips); count++)
+    {
+        if (NULL == dynamicConfig)
+        {
+            break;
+        }
+        else
+        {
+            base->DYNAMIC[dynamicConfig->chipIndex].DYNAMICCONFIG |= EMC_DYNAMIC_DYNAMICCONFIG_B_MASK;
+            dynamicConfig++;
+        }
+    }
+}
+
+/*!
+ * brief Initializes the static memory controller.
+ * This function initializes the static memory controller in external memory controller.
+ * This function must be called after EMC_Init and before accessing the external static memory.
+ *
+ * param base EMC peripheral base address.
+ * param extWait_Ns The extended wait timeout or the read/write transfer time.
+ *        This is common for all static memory chips and set with NULL if not required.
+ * param configure The EMC static memory controller chip independent configuration pointer.
+ *       This configuration pointer is actually pointer to a configration array. the array number
+ *       depends on the "totalChips".
+ * param totalChips The total static memory chip numbers been used or the length of the
+ *        "emc_static_chip_config_t" type memory.
+ */
+void EMC_StaticMemInit(EMC_Type *base, uint32_t *extWait_Ns, emc_static_chip_config_t *config, uint32_t totalChips)
+{
+    assert(NULL != config);
+
+    uint32_t count;
+    emc_static_chip_config_t *staticConfig = config;
+
+    /* Initialize extended wait. */
+    if (NULL != extWait_Ns)
+    {
+        for (count = 0; (count < totalChips) && (staticConfig != NULL); count++)
+        {
+            assert(0U != (staticConfig->specailConfig & (uint32_t)kEMC_AsynchronosPageEnable));
+        }
+
+        base->STATICEXTENDEDWAIT = EMC_CalculateTimerCycles(base, *extWait_Ns, 1);
+        staticConfig++;
+    }
+
+    /* Initialize the static memory chip specific configure. */
+    staticConfig = config;
+    for (count = 0; (count < totalChips); count++)
+    {
+        if (NULL == staticConfig)
+        {
+            break;
+        }
+        else
+        {
+            base->STATIC[staticConfig->chipIndex].STATICCONFIG =
+                (staticConfig->specailConfig | (uint32_t)staticConfig->memWidth);
+            base->STATIC[staticConfig->chipIndex].STATICWAITWEN =
+                EMC_CalculateTimerCycles(base, staticConfig->tWaitWriteEn_Ns, 1);
+            base->STATIC[staticConfig->chipIndex].STATICWAITOEN =
+                EMC_CalculateTimerCycles(base, staticConfig->tWaitOutEn_Ns, 0);
+            base->STATIC[staticConfig->chipIndex].STATICWAITRD =
+                EMC_CalculateTimerCycles(base, staticConfig->tWaitReadNoPage_Ns, 1);
+            base->STATIC[staticConfig->chipIndex].STATICWAITPAGE =
+                EMC_CalculateTimerCycles(base, staticConfig->tWaitReadPage_Ns, 1);
+            base->STATIC[staticConfig->chipIndex].STATICWAITWR =
+                EMC_CalculateTimerCycles(base, staticConfig->tWaitWrite_Ns, 2);
+            base->STATIC[staticConfig->chipIndex].STATICWAITTURN =
+                EMC_CalculateTimerCycles(base, staticConfig->tWaitTurn_Ns, 1);
+
+            staticConfig++;
+        }
+    }
+}
+
+/*!
+ * brief Deinitializes the EMC module and gates the clock.
+ * This function gates the EMC controller clock. As a result, the EMC
+ * module doesn't work after calling this function.
+ *
+ * param base EMC peripheral base address.
+ */
+void EMC_Deinit(EMC_Type *base)
+{
+    /* Deinit the EMC. */
+    base->CONTROL &= ~EMC_CONTROL_E_MASK;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Disable the clock. */
+    CLOCK_DisableClock(s_EMCClock[EMC_GetInstance(base)]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}

FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/drivers/fsl_emc.h

@@ -0,0 +1,364 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2019 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _FSL_EMC_H_
+#define _FSL_EMC_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup emc
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief EMC driver version. */
+#define FSL_EMC_DRIVER_VERSION (MAKE_VERSION(2, 0, 4))
+/*@}*/
+
+/*! @brief Define the chip numbers for dynamic and static memory devices. */
+#define EMC_STATIC_MEMDEV_NUM (4U)
+#define EMC_DYNAMIC_MEMDEV_NUM (4U)
+#define EMC_ADDRMAP_SHIFT EMC_DYNAMIC_DYNAMICCONFIG_AM0_SHIFT
+#define EMC_ADDRMAP_MASK (EMC_DYNAMIC_DYNAMICCONFIG_AM0_MASK | EMC_DYNAMIC_DYNAMICCONFIG_AM1_MASK)
+#define EMC_ADDRMAP(x) (((uint32_t)(((uint32_t)(x)) << EMC_ADDRMAP_SHIFT)) & EMC_ADDRMAP_MASK)
+#define EMC_HZ_ONEMHZ (1000000U)
+#define EMC_MILLISECS_ONESEC (1000U)
+#define EMC_SDRAM_MODE_CL_SHIFT (4U)
+#define EMC_SDRAM_MODE_CL_MASK (0x70U)
+/*! @brief EDMA_SDRAM NOP command wait us */
+#ifndef EMC_SDRAM_NOP_DELAY_US
+#define EMC_SDRAM_NOP_DELAY_US (100U)
+#endif
+/*! @brief EDMA_SDRAM precharge command wait us */
+#ifndef EMC_SDRAM_PRECHARGE_DELAY_US
+#define EMC_SDRAM_PRECHARGE_DELAY_US (100U)
+#endif
+/*! @brief EDMA_SDRAM auto refresh wait us */
+#ifndef EMC_SDRAM_AUTO_REFRESH_DELAY_US
+#define EMC_SDRAM_AUTO_REFRESH_DELAY_US (50U)
+#endif
+/*!
+ * @brief Define EMC memory width for static memory device.
+ */
+typedef enum _emc_static_memwidth
+{
+    kEMC_8BitWidth = 0x0U, /*!< 8 bit memory width. */
+    kEMC_16BitWidth,       /*!< 16 bit memory width. */
+    kEMC_32BitWidth        /*!< 32 bit memory width. */
+} emc_static_memwidth_t;
+
+/*!
+ * @brief Define EMC static configuration.
+ */
+typedef enum _emc_static_special_config
+{
+    kEMC_AsynchronosPageEnable = 0x0008U, /*!< Enable the asynchronous page mode. page length four. */
+    kEMC_ActiveHighChipSelect  = 0x0040U, /*!< Chip select active high. */
+    kEMC_ByteLaneStateAllLow   = 0x0080U, /*!< Reads/writes the respective valuie bits in BLS3:0 are low. */
+    kEMC_ExtWaitEnable         = 0x0100U, /*!< Extended wait enable. */
+    kEMC_BufferEnable          = 0x80000U /*!< Buffer enable. */
+} emc_static_special_config_t;
+
+/*! @brief EMC dynamic memory device. */
+typedef enum _emc_dynamic_device
+{
+    kEMC_Sdram = 0x0U, /*!< Dynamic memory device: SDRAM. */
+    kEMC_Lpsdram,      /*!< Dynamic memory device: Low-power SDRAM. */
+} emc_dynamic_device_t;
+
+/*! @brief EMC dynamic read strategy. */
+typedef enum _emc_dynamic_read
+{
+    kEMC_NoDelay = 0x0U,      /*!< No delay. */
+    kEMC_Cmddelay,            /*!< Command delayed strategy, using EMCCLKDELAY. */
+    kEMC_CmdDelayPulseOneclk, /*!< Command delayed strategy pluse one clock cycle using EMCCLKDELAY. */
+    kEMC_CmddelayPulsetwoclk, /*!< Command delayed strategy pulse two clock cycle using EMCCLKDELAY. */
+} emc_dynamic_read_t;
+
+/*! @brief EMC endian mode. */
+typedef enum _emc_endian_mode
+{
+    kEMC_LittleEndian = 0x0U, /*!< Little endian mode. */
+    kEMC_BigEndian,           /*!< Big endian mode. */
+} emc_endian_mode_t;
+
+/*! @brief EMC Feedback clock input source select. */
+typedef enum _emc_fbclk_src
+{
+    kEMC_IntloopbackEmcclk = 0U, /*!< Use the internal loop back from EMC_CLK output. */
+    kEMC_EMCFbclkInput           /*!< Use the external EMC_FBCLK input. */
+} emc_fbclk_src_t;
+
+/*! @brief EMC dynamic timing/delay configure structure. */
+typedef struct _emc_dynamic_timing_config
+{
+    emc_dynamic_read_t readConfig;  /* Dynamic read strategy. */
+    uint32_t refreshPeriod_Nanosec; /*!< The refresh period in unit of nanosecond. */
+    uint32_t tRp_Ns;                /*!< Precharge command period in unit of nanosecond. */
+    uint32_t tRas_Ns;               /*!< Active to precharge command period in unit of nanosecond. */
+    uint32_t tSrex_Ns;              /*!< Self-refresh exit time in unit of nanosecond. */
+    uint32_t tApr_Ns;               /*!< Last data out to active command time in unit of nanosecond. */
+    uint32_t tDal_Ns;               /*!< Data-in to active command in unit of nanosecond. */
+    uint32_t tWr_Ns;                /*!< Write recovery time in unit of nanosecond. */
+    uint32_t tRc_Ns;                /*!< Active to active command period in unit of nanosecond. */
+    uint32_t tRfc_Ns;  /*!< Auto-refresh period and auto-refresh to active command period in unit of nanosecond. */
+    uint32_t tXsr_Ns;  /*!< Exit self-refresh to active command time in unit of nanosecond. */
+    uint32_t tRrd_Ns;  /*!< Active bank A to active bank B latency in unit of nanosecond. */
+    uint8_t tMrd_Nclk; /*!< Load mode register to active command time in unit of EMCCLK cycles.*/
+} emc_dynamic_timing_config_t;
+
+/*!
+ * @brief EMC dynamic memory controller independent chip configuration structure.
+ * Please take refer to the address mapping table in the RM in EMC chapter when you
+ * set the "devAddrMap". Choose the right Bit 14 Bit12 ~ Bit 7 group in the table
+ * according to the bus width/banks/row/colum length for you device.
+ * Set devAddrMap with the value make up with the seven bits (bit14 bit12 ~ bit 7)
+ * and inset the bit 13 with 0.
+ * for example, if the bit 14 and bit12 ~ bit7 is 1000001 is choosen according to the
+ * 32bit high-performance bus width with 2 banks, 11 row lwngth, 8 column length.
+ * Set devAddrMap with 0x81.
+ */
+typedef struct _emc_dynamic_chip_config
+{
+    uint8_t chipIndex; /*!< Chip Index, range from 0 ~ EMC_DYNAMIC_MEMDEV_NUM - 1. */
+    emc_dynamic_device_t
+        dynamicDevice;        /*!< All chips shall use the same device setting. mixed use are not supported. */
+    uint8_t rAS_Nclk;         /*!< Active to read/write delay tRCD. */
+    uint16_t sdramModeReg;    /*!< Sdram mode register setting. */
+    uint16_t sdramExtModeReg; /*!< Used for low-power sdram device. The extended mode register. */
+    uint8_t devAddrMap; /*!< dynamic device address mapping, choose the address mapping for your specific device. */
+} emc_dynamic_chip_config_t;
+
+/*!
+ * @brief EMC static memory controller independent chip configuration structure.
+ */
+typedef struct _emc_static_chip_config
+{
+    uint8_t chipIndex;
+    emc_static_memwidth_t memWidth; /*!< Memory width. */
+    uint32_t specailConfig;         /*!< Static configuration,a logical OR of "emc_static_special_config_t". */
+    uint32_t tWaitWriteEn_Ns;       /*!< The delay form chip select to write enable in unit of nanosecond. */
+    uint32_t tWaitOutEn_Ns;         /*!< The delay from chip selcet to output enable in unit of nanosecond. */
+    uint32_t
+        tWaitReadNoPage_Ns;    /*!< In No-page mode, the delay from chip select to read access in unit of nanosecond. */
+    uint32_t tWaitReadPage_Ns; /*!< In page mode, the read after the first read wait states in unit of nanosecond. */
+    uint32_t tWaitWrite_Ns;    /*!< The delay from chip select to write access in unit of nanosecond. */
+    uint32_t tWaitTurn_Ns;     /*!< The Bus turn-around time in unit of nanosecond. */
+} emc_static_chip_config_t;
+
+/*!
+ * @brief EMC module basic configuration structure.
+ *
+ * Defines the static memory controller configure structure and
+ * uses the EMC_Init() function to make necessary initializations.
+ *
+ */
+typedef struct _emc_basic_config
+{
+    emc_endian_mode_t endian; /*!< Endian mode . */
+    emc_fbclk_src_t fbClkSrc; /*!< The feedback clock source. */
+    uint8_t emcClkDiv;        /*!< EMC_CLK = AHB_CLK / (emc_clkDiv + 1). */
+} emc_basic_config_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @name EMC Initialize and de-initialize opeartion
+ * @{
+ */
+/*!
+ * @brief Initializes the basic for EMC.
+ * This function ungates the EMC clock, initializes the emc system configure
+ * and enable the EMC module. This function must be called in the first step to initialize
+ * the external memory.
+ *
+ * @param base EMC peripheral base address.
+ * @param config The EMC basic configuration.
+ */
+void EMC_Init(EMC_Type *base, emc_basic_config_t *config);
+
+/*!
+ * @brief Initializes the dynamic memory controller.
+ * This function initializes the dynamic memory controller in external memory controller.
+ * This function must be called after EMC_Init and before accessing the external dynamic memory.
+ *
+ * @param base EMC peripheral base address.
+ * @param timing The timing and latency for dynamica memory controller setting. It shall
+ *        be used for all dynamica memory chips, threfore the worst timing value for all
+ *        used chips must be given.
+ * @param configure The EMC dynamic memory controller chip independent configuration pointer.
+ *       This configuration pointer is actually pointer to a configration array. the array number
+ *       depends on the "totalChips".
+ * @param totalChips The total dynamic memory chip numbers been used or the length of the
+ *        "emc_dynamic_chip_config_t" type memory.
+ */
+void EMC_DynamicMemInit(EMC_Type *base,
+                        emc_dynamic_timing_config_t *timing,
+                        emc_dynamic_chip_config_t *config,
+                        uint32_t totalChips);
+
+/*!
+ * @brief Initializes the static memory controller.
+ * This function initializes the static memory controller in external memory controller.
+ * This function must be called after EMC_Init and before accessing the external static memory.
+ *
+ * @param base EMC peripheral base address.
+ * @param extWait_Ns The extended wait timeout or the read/write transfer time.
+ *        This is common for all static memory chips and set with NULL if not required.
+ * @param configure The EMC static memory controller chip independent configuration pointer.
+ *       This configuration pointer is actually pointer to a configration array. the array number
+ *       depends on the "totalChips".
+ * @param totalChips The total static memory chip numbers been used or the length of the
+ *        "emc_static_chip_config_t" type memory.
+ */
+void EMC_StaticMemInit(EMC_Type *base, uint32_t *extWait_Ns, emc_static_chip_config_t *config, uint32_t totalChips);
+
+/*!
+ * @brief Deinitializes the EMC module and gates the clock.
+ * This function gates the EMC controller clock. As a result, the EMC
+ * module doesn't work after calling this function.
+ *
+ * @param base EMC peripheral base address.
+ */
+void EMC_Deinit(EMC_Type *base);
+
+/* @} */
+
+/*!
+ * @name EMC Basic Operation
+ * @{
+ */
+
+/*!
+ * @brief Enables/disables the EMC module.
+ *
+ * @param base EMC peripheral base address.
+ * @param enable True enable EMC module, false disable.
+ */
+static inline void EMC_Enable(EMC_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->CONTROL |= EMC_CONTROL_E_MASK;
+    }
+    else
+    {
+        base->CONTROL &= ~EMC_CONTROL_E_MASK;
+    }
+}
+
+/*!
+ * @brief Enables/disables the EMC Dynaimc memory controller.
+ *
+ * @param base EMC peripheral base address.
+ * @param enable True enable EMC dynamic memory controller, false disable.
+ */
+static inline void EMC_EnableDynamicMemControl(EMC_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->DYNAMICCONTROL |= (EMC_DYNAMICCONTROL_CE_MASK | EMC_DYNAMICCONTROL_CS_MASK);
+    }
+    else
+    {
+        base->DYNAMICCONTROL &= ~(EMC_DYNAMICCONTROL_CE_MASK | EMC_DYNAMICCONTROL_CS_MASK);
+    }
+}
+
+/*!
+ * @brief Enables/disables the EMC address mirror.
+ * Enable the address mirror the EMC_CS1is mirrored to both EMC_CS0
+ * and EMC_DYCS0 memory areas. Disable the address mirror enables
+ * EMC_cS0 and EMC_DYCS0 memory to be accessed.
+ *
+ * @param base EMC peripheral base address.
+ * @param enable True enable the address mirror, false disable the address mirror.
+ */
+static inline void EMC_MirrorChipAddr(EMC_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->CONTROL |= EMC_CONTROL_M_MASK;
+    }
+    else
+    {
+        base->CONTROL &= ~EMC_CONTROL_M_MASK;
+    }
+}
+
+/*!
+ * @brief Enter the self-refresh mode for dynamic memory controller.
+ * This function provided self-refresh mode enter or exit for application.
+ *
+ * @param base EMC peripheral base address.
+ * @param enable   True enter the self-refresh mode, false to exit self-refresh
+ *                 and enter the normal mode.
+ */
+static inline void EMC_EnterSelfRefreshCommand(EMC_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->DYNAMICCONTROL |= EMC_DYNAMICCONTROL_SR_MASK;
+    }
+    else
+    {
+        base->DYNAMICCONTROL &= ~EMC_DYNAMICCONTROL_SR_MASK;
+    }
+}
+
+/*!
+ * @brief Get the operating mode of the EMC.
+ * This function can be used to get the operating mode of the EMC.
+ *
+ * @param base EMC peripheral base address.
+ * @return The EMC in self-refresh mode if true, else in normal mode.
+ */
+static inline bool EMC_IsInSelfrefreshMode(EMC_Type *base)
+{
+    return (0U != (base->STATUS & EMC_STATUS_SA_MASK));
+}
+
+/*!
+ * @brief Enter/exit the low-power mode.
+ *
+ * @param base EMC peripheral base address.
+ * @param enable True Enter the low-power mode, false exit low-power mode
+ *        and return to normal mode.
+ */
+static inline void EMC_EnterLowPowerMode(EMC_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->CONTROL |= EMC_CONTROL_L_MASK;
+    }
+    else
+    {
+        base->CONTROL &= ~EMC_CONTROL_L_MASK;
+    }
+}
+
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* _FSL_EMC_H_*/

FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/drivers/fsl_flexcomm.c

@@ -0,0 +1,411 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2019 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "fsl_flexcomm.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.flexcomm"
+#endif
+
+/*!
+ * @brief Used for conversion between `void*` and `uint32_t`.
+ */
+typedef union pvoid_to_u32
+{
+    void *pvoid;
+    uint32_t u32;
+} pvoid_to_u32_t;
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+/*! @brief Set the FLEXCOMM mode . */
+static status_t FLEXCOMM_SetPeriph(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph, int lock);
+
+/*! @brief check whether flexcomm supports peripheral type */
+static bool FLEXCOMM_PeripheralIsPresent(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph);
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*! @brief Pointers to real IRQ handlers installed by drivers for each instance. */
+static flexcomm_irq_handler_t s_flexcommIrqHandler[FSL_FEATURE_SOC_FLEXCOMM_COUNT];
+
+/*! @brief Pointers to handles for each instance to provide context to interrupt routines */
+static void *s_flexcommHandle[FSL_FEATURE_SOC_FLEXCOMM_COUNT];
+
+/*! @brief Array to map FLEXCOMM instance number to IRQ number. */
+IRQn_Type const kFlexcommIrqs[] = FLEXCOMM_IRQS;
+
+/*! @brief Array to map FLEXCOMM instance number to base address. */
+static const uint32_t s_flexcommBaseAddrs[FSL_FEATURE_SOC_FLEXCOMM_COUNT] = FLEXCOMM_BASE_ADDRS;
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+/*! @brief IDs of clock for each FLEXCOMM module */
+static const clock_ip_name_t s_flexcommClocks[] = FLEXCOMM_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+#if !(defined(FSL_FEATURE_FLEXCOMM_HAS_NO_RESET) && FSL_FEATURE_FLEXCOMM_HAS_NO_RESET)
+/*! @brief Pointers to FLEXCOMM resets for each instance. */
+static const reset_ip_name_t s_flexcommResets[] = FLEXCOMM_RSTS;
+#endif
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/* check whether flexcomm supports peripheral type */
+static bool FLEXCOMM_PeripheralIsPresent(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph)
+{
+    if (periph == FLEXCOMM_PERIPH_NONE)
+    {
+        return true;
+    }
+    else if (periph <= FLEXCOMM_PERIPH_I2S_TX)
+    {
+        return (base->PSELID & (1UL << ((uint32_t)periph + 3U))) > 0UL ? true : false;
+    }
+    else if (periph == FLEXCOMM_PERIPH_I2S_RX)
+    {
+        return (base->PSELID & (1U << 7U)) > (uint32_t)0U ? true : false;
+    }
+    else
+    {
+        return false;
+    }
+}
+
+/* Get the index corresponding to the FLEXCOMM */
+/*! brief Returns instance number for FLEXCOMM module with given base address. */
+uint32_t FLEXCOMM_GetInstance(void *base)
+{
+    uint32_t i;
+    pvoid_to_u32_t BaseAddr;
+    BaseAddr.pvoid = base;
+
+    for (i = 0U; i < (uint32_t)FSL_FEATURE_SOC_FLEXCOMM_COUNT; i++)
+    {
+        if (BaseAddr.u32 == s_flexcommBaseAddrs[i])
+        {
+            break;
+        }
+    }
+
+    assert(i < FSL_FEATURE_SOC_FLEXCOMM_COUNT);
+    return i;
+}
+
+/* Changes FLEXCOMM mode */
+static status_t FLEXCOMM_SetPeriph(FLEXCOMM_Type *base, FLEXCOMM_PERIPH_T periph, int lock)
+{
+    /* Check whether peripheral type is present */
+    if (!FLEXCOMM_PeripheralIsPresent(base, periph))
+    {
+        return kStatus_OutOfRange;
+    }
+
+    /* Flexcomm is locked to different peripheral type than expected  */
+    if (((base->PSELID & FLEXCOMM_PSELID_LOCK_MASK) != 0U) &&
+        ((base->PSELID & FLEXCOMM_PSELID_PERSEL_MASK) != (uint32_t)periph))
+    {
+        return kStatus_Fail;
+    }
+
+    /* Check if we are asked to lock */
+    if (lock != 0)
+    {
+        base->PSELID = (uint32_t)periph | FLEXCOMM_PSELID_LOCK_MASK;
+    }
+    else
+    {
+        base->PSELID = (uint32_t)periph;
+    }
+
+    return kStatus_Success;
+}
+
+/*! brief Initializes FLEXCOMM and selects peripheral mode according to the second parameter. */
+status_t FLEXCOMM_Init(void *base, FLEXCOMM_PERIPH_T periph)
+{
+    uint32_t idx = FLEXCOMM_GetInstance(base);
+
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    /* Enable the peripheral clock */
+    CLOCK_EnableClock(s_flexcommClocks[idx]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+#if !(defined(FSL_FEATURE_FLEXCOMM_HAS_NO_RESET) && FSL_FEATURE_FLEXCOMM_HAS_NO_RESET)
+    /* Reset the FLEXCOMM module */
+    RESET_PeripheralReset(s_flexcommResets[idx]);
+#endif
+
+    /* Set the FLEXCOMM to given peripheral */
+    return FLEXCOMM_SetPeriph((FLEXCOMM_Type *)base, periph, 0);
+}
+
+/*! brief Sets IRQ handler for given FLEXCOMM module. It is used by drivers register IRQ handler according to FLEXCOMM
+ * mode */
+void FLEXCOMM_SetIRQHandler(void *base, flexcomm_irq_handler_t handler, void *handle)
+{
+    uint32_t instance;
+
+    /* Look up instance number */
+    instance = FLEXCOMM_GetInstance(base);
+
+    /* Clear handler first to avoid execution of the handler with wrong handle */
+    s_flexcommIrqHandler[instance] = NULL;
+    s_flexcommHandle[instance]     = handle;
+    s_flexcommIrqHandler[instance] = handler;
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+    __DSB();
+#endif
+}
+
+/* IRQ handler functions overloading weak symbols in the startup */
+#if defined(FLEXCOMM0)
+void FLEXCOMM0_DriverIRQHandler(void)
+{
+    assert(s_flexcommIrqHandler[0]);
+    s_flexcommIrqHandler[0]((uint32_t *)s_flexcommBaseAddrs[0], s_flexcommHandle[0]);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+    __DSB();
+#endif
+}
+#endif
+
+#if defined(FLEXCOMM1)
+void FLEXCOMM1_DriverIRQHandler(void)
+{
+    assert(s_flexcommIrqHandler[1]);
+    s_flexcommIrqHandler[1]((uint32_t *)s_flexcommBaseAddrs[1], s_flexcommHandle[1]);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+    __DSB();
+#endif
+}
+#endif
+
+#if defined(FLEXCOMM2)
+void FLEXCOMM2_DriverIRQHandler(void)
+{
+    assert(s_flexcommIrqHandler[2]);
+    s_flexcommIrqHandler[2]((uint32_t *)s_flexcommBaseAddrs[2], s_flexcommHandle[2]);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+    __DSB();
+#endif
+}
+#endif
+
+#if defined(FLEXCOMM3)
+void FLEXCOMM3_DriverIRQHandler(void)
+{
+    assert(s_flexcommIrqHandler[3]);
+    s_flexcommIrqHandler[3]((uint32_t *)s_flexcommBaseAddrs[3], s_flexcommHandle[3]);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+    __DSB();
+#endif
+}
+#endif
+
+#if defined(FLEXCOMM4)
+void FLEXCOMM4_DriverIRQHandler(void)
+{
+    assert(s_flexcommIrqHandler[4]);
+    s_flexcommIrqHandler[4]((uint32_t *)s_flexcommBaseAddrs[4], s_flexcommHandle[4]);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+    __DSB();
+#endif
+}
+
+#endif
+
+#if defined(FLEXCOMM5)
+void FLEXCOMM5_DriverIRQHandler(void)
+{
+    assert(s_flexcommIrqHandler[5]);
+    s_flexcommIrqHandler[5]((uint32_t *)s_flexcommBaseAddrs[5], s_flexcommHandle[5]);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+    __DSB();
+#endif
+}
+#endif
+
+#if defined(FLEXCOMM6)
+void FLEXCOMM6_DriverIRQHandler(void)
+{
+    assert(s_flexcommIrqHandler[6]);
+    s_flexcommIrqHandler[6]((uint32_t *)s_flexcommBaseAddrs[6], s_flexcommHandle[6]);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+    __DSB();
+#endif
+}
+#endif
+
+#if defined(FLEXCOMM7)
+void FLEXCOMM7_DriverIRQHandler(void)
+{
+    assert(s_flexcommIrqHandler[7]);
+    s_flexcommIrqHandler[7]((uint32_t *)s_flexcommBaseAddrs[7], s_flexcommHandle[7]);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+    __DSB();
+#endif
+}
+#endif
+
+#if defined(FLEXCOMM8)
+void FLEXCOMM8_DriverIRQHandler(void)
+{
+    assert(s_flexcommIrqHandler[8]);
+    s_flexcommIrqHandler[8]((uint32_t *)s_flexcommBaseAddrs[8], s_flexcommHandle[8]);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+    __DSB();
+#endif
+}
+#endif
+
+#if defined(FLEXCOMM9)
+void FLEXCOMM9_DriverIRQHandler(void)
+{
+    assert(s_flexcommIrqHandler[9]);
+    s_flexcommIrqHandler[9]((uint32_t *)s_flexcommBaseAddrs[9], s_flexcommHandle[9]);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+    __DSB();
+#endif
+}
+#endif
+
+#if defined(FLEXCOMM10)
+void FLEXCOMM10_DriverIRQHandler(void)
+{
+    assert(s_flexcommIrqHandler[10]);
+    s_flexcommIrqHandler[10]((uint32_t *)s_flexcommBaseAddrs[10], s_flexcommHandle[10]);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+    __DSB();
+#endif
+}
+#endif
+
+#if defined(FLEXCOMM11)
+void FLEXCOMM11_DriverIRQHandler(void)
+{
+    assert(s_flexcommIrqHandler[11]);
+    s_flexcommIrqHandler[11]((uint32_t *)s_flexcommBaseAddrs[11], s_flexcommHandle[11]);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+    __DSB();
+#endif
+}
+#endif
+
+#if defined(FLEXCOMM12)
+void FLEXCOMM12_DriverIRQHandler(void)
+{
+    assert(s_flexcommIrqHandler[12]);
+    s_flexcommIrqHandler[12]((uint32_t *)s_flexcommBaseAddrs[12], s_flexcommHandle[12]);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+    __DSB();
+#endif
+}
+#endif
+
+#if defined(FLEXCOMM13)
+void FLEXCOMM13_DriverIRQHandler(void)
+{
+    assert(s_flexcommIrqHandler[13]);
+    s_flexcommIrqHandler[13]((uint32_t *)s_flexcommBaseAddrs[13], s_flexcommHandle[13]);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+    __DSB();
+#endif
+}
+#endif
+
+#if defined(FLEXCOMM14)
+void FLEXCOMM14_DriverIRQHandler(void)
+{
+    uint32_t instance;
+
+    /* Look up instance number */
+    instance = FLEXCOMM_GetInstance(FLEXCOMM14);
+    assert(s_flexcommIrqHandler[instance]);
+    s_flexcommIrqHandler[instance]((void *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+    __DSB();
+#endif
+}
+#endif
+
+#if defined(FLEXCOMM15)
+void FLEXCOMM15_DriverIRQHandler(void)
+{
+    uint32_t instance;
+
+    /* Look up instance number */
+    instance = FLEXCOMM_GetInstance(FLEXCOMM15);
+    assert(s_flexcommIrqHandler[instance]);
+    s_flexcommIrqHandler[instance]((void *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+    __DSB();
+#endif
+}
+#endif
+
+#if defined(FLEXCOMM16)
+void FLEXCOMM16_DriverIRQHandler(void)
+{
+    uint32_t instance;
+
+    /* Look up instance number */
+    instance = FLEXCOMM_GetInstance(FLEXCOMM16);
+    assert(s_flexcommIrqHandler[instance]);
+    s_flexcommIrqHandler[instance]((void *)s_flexcommBaseAddrs[instance], s_flexcommHandle[instance]);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+  exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+    __DSB();
+#endif
+}
+#endif

FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/drivers/fsl_flexcomm.h

@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2019 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _FSL_FLEXCOMM_H_
+#define _FSL_FLEXCOMM_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup flexcomm_driver
+ * @{
+ */
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief FlexCOMM driver version 2.0.2. */
+#define FSL_FLEXCOMM_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
+/*@}*/
+
+/*! @brief FLEXCOMM peripheral modes. */
+typedef enum
+{
+    FLEXCOMM_PERIPH_NONE,   /*!< No peripheral */
+    FLEXCOMM_PERIPH_USART,  /*!< USART peripheral */
+    FLEXCOMM_PERIPH_SPI,    /*!< SPI Peripheral */
+    FLEXCOMM_PERIPH_I2C,    /*!< I2C Peripheral */
+    FLEXCOMM_PERIPH_I2S_TX, /*!< I2S TX Peripheral */
+    FLEXCOMM_PERIPH_I2S_RX, /*!< I2S RX Peripheral */
+} FLEXCOMM_PERIPH_T;
+
+/*! @brief Typedef for interrupt handler. */
+typedef void (*flexcomm_irq_handler_t)(void *base, void *handle);
+
+/*! @brief Array with IRQ number for each FLEXCOMM module. */
+extern IRQn_Type const kFlexcommIrqs[];
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*! @brief Returns instance number for FLEXCOMM module with given base address. */
+uint32_t FLEXCOMM_GetInstance(void *base);
+
+/*! @brief Initializes FLEXCOMM and selects peripheral mode according to the second parameter. */
+status_t FLEXCOMM_Init(void *base, FLEXCOMM_PERIPH_T periph);
+
+/*! @brief Sets IRQ handler for given FLEXCOMM module. It is used by drivers register IRQ handler according to FLEXCOMM
+ * mode */
+void FLEXCOMM_SetIRQHandler(void *base, flexcomm_irq_handler_t handler, void *handle);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*@}*/
+
+#endif /* _FSL_FLEXCOMM_H_*/

FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/drivers/fsl_gpio.c

@@ -0,0 +1,302 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2019 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_gpio.h"
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.lpc_gpio"
+#endif
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+/*! @brief Array to map FGPIO instance number to clock name. */
+static const clock_ip_name_t s_gpioClockName[] = GPIO_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+
+#if !(defined(FSL_FEATURE_GPIO_HAS_NO_RESET) && FSL_FEATURE_GPIO_HAS_NO_RESET)
+/*! @brief Pointers to GPIO resets for each instance. */
+static const reset_ip_name_t s_gpioResets[] = GPIO_RSTS_N;
+#endif
+/*******************************************************************************
+ * Prototypes
+ ************ ******************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/*!
+ * brief Initializes the GPIO peripheral.
+ *
+ * This function ungates the GPIO clock.
+ *
+ * param base   GPIO peripheral base pointer.
+ * param port   GPIO port number.
+ */
+void GPIO_PortInit(GPIO_Type *base, uint32_t port)
+{
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+    assert(port < ARRAY_SIZE(s_gpioClockName));
+
+    /* Upgate the GPIO clock */
+    CLOCK_EnableClock(s_gpioClockName[port]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+#if !(defined(FSL_FEATURE_GPIO_HAS_NO_RESET) && FSL_FEATURE_GPIO_HAS_NO_RESET)
+    /* Reset the GPIO module */
+    RESET_PeripheralReset(s_gpioResets[port]);
+#endif
+}
+
+/*!
+ * brief Initializes a GPIO pin used by the board.
+ *
+ * To initialize the GPIO, define a pin configuration, either input or output, in the user file.
+ * Then, call the GPIO_PinInit() function.
+ *
+ * This is an example to define an input pin or output pin configuration:
+ * code
+ * Define a digital input pin configuration,
+ * gpio_pin_config_t config =
+ * {
+ *   kGPIO_DigitalInput,
+ *   0,
+ * }
+ * Define a digital output pin configuration,
+ * gpio_pin_config_t config =
+ * {
+ *   kGPIO_DigitalOutput,
+ *   0,
+ * }
+ * endcode
+ *
+ * param base   GPIO peripheral base pointer(Typically GPIO)
+ * param port   GPIO port number
+ * param pin    GPIO pin number
+ * param config GPIO pin configuration pointer
+ */
+void GPIO_PinInit(GPIO_Type *base, uint32_t port, uint32_t pin, const gpio_pin_config_t *config)
+{
+    if (config->pinDirection == kGPIO_DigitalInput)
+    {
+#if defined(FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR) && (FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR)
+        base->DIRCLR[port] = 1UL << pin;
+#else
+        base->DIR[port] &= ~(1UL << pin);
+#endif /*FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR*/
+    }
+    else
+    {
+        /* Set default output value */
+        if (config->outputLogic == 0U)
+        {
+            base->CLR[port] = (1UL << pin);
+        }
+        else
+        {
+            base->SET[port] = (1UL << pin);
+        }
+/* Set pin direction */
+#if defined(FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR) && (FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR)
+        base->DIRSET[port] = 1UL << pin;
+#else
+        base->DIR[port] |= 1UL << pin;
+#endif /*FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR*/
+    }
+}
+
+#if defined(FSL_FEATURE_GPIO_HAS_INTERRUPT) && FSL_FEATURE_GPIO_HAS_INTERRUPT
+/*!
+ * @brief Configures the gpio pin interrupt.
+ *
+ * @param base GPIO base pointer.
+ * @param port GPIO port number
+ * @param pin GPIO pin number.
+ * @param config GPIO pin interrupt configuration..
+ */
+void GPIO_SetPinInterruptConfig(GPIO_Type *base, uint32_t port, uint32_t pin, gpio_interrupt_config_t *config)
+{
+    base->INTEDG[port] = base->INTEDG[port] | ((uint32_t)config->mode << pin);
+
+    base->INTPOL[port] = base->INTPOL[port] | ((uint32_t)config->polarity << pin);
+}
+
+/*!
+ * @brief Enables multiple pins interrupt.
+ *
+ * @param base GPIO base pointer.
+ * @param port   GPIO port number.
+ * @param index GPIO interrupt number.
+ * @param mask GPIO pin number macro.
+ */
+void GPIO_PortEnableInterrupts(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask)
+{
+    if ((uint32_t)kGPIO_InterruptA == index)
+    {
+        base->INTENA[port] = base->INTENA[port] | mask;
+    }
+    else if ((uint32_t)kGPIO_InterruptB == index)
+    {
+        base->INTENB[port] = base->INTENB[port] | mask;
+    }
+    else
+    {
+        /*Should not enter here*/
+    }
+}
+
+/*!
+ * @brief Disables multiple pins interrupt.
+ *
+ * @param base GPIO base pointer.
+ * @param port   GPIO port number.
+ * @param index GPIO interrupt number.
+ * @param mask GPIO pin number macro.
+ */
+void GPIO_PortDisableInterrupts(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask)
+{
+    if ((uint32_t)kGPIO_InterruptA == index)
+    {
+        base->INTENA[port] = base->INTENA[port] & ~mask;
+    }
+    else if ((uint32_t)kGPIO_InterruptB == index)
+    {
+        base->INTENB[port] = base->INTENB[port] & ~mask;
+    }
+    else
+    {
+        /*Should not enter here*/
+    }
+}
+
+/*!
+ * @brief Clears multiple pins interrupt flag. Status flags are cleared by
+ *        writing a 1 to the corresponding bit position.
+ *
+ * @param base GPIO base pointer.
+ * @param port GPIO port number.
+ * @param index GPIO interrupt number.
+ * @param mask GPIO pin number macro.
+ */
+void GPIO_PortClearInterruptFlags(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask)
+{
+    if ((uint32_t)kGPIO_InterruptA == index)
+    {
+        base->INTSTATA[port] = mask;
+    }
+    else if ((uint32_t)kGPIO_InterruptB == index)
+    {
+        base->INTSTATB[port] = mask;
+    }
+    else
+    {
+        /*Should not enter here*/
+    }
+}
+
+/*!
+ * @ Read port interrupt status.
+ *
+ * @param base GPIO base pointer.
+ * @param port GPIO port number
+ * @param index GPIO interrupt number.
+ * @retval masked GPIO status value
+ */
+uint32_t GPIO_PortGetInterruptStatus(GPIO_Type *base, uint32_t port, uint32_t index)
+{
+    uint32_t status = 0U;
+
+    if ((uint32_t)kGPIO_InterruptA == index)
+    {
+        status = base->INTSTATA[port];
+    }
+    else if ((uint32_t)kGPIO_InterruptB == index)
+    {
+        status = base->INTSTATB[port];
+    }
+    else
+    {
+        /*Should not enter here*/
+    }
+    return status;
+}
+
+/*!
+ * @brief Enables the specific pin interrupt.
+ *
+ * @param base GPIO base pointer.
+ * @param port   GPIO port number.
+ * @param pin GPIO pin number.
+ * @param index GPIO interrupt number.
+ */
+void GPIO_PinEnableInterrupt(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index)
+{
+    if ((uint32_t)kGPIO_InterruptA == index)
+    {
+        base->INTENA[port] = base->INTENA[port] | (1UL << pin);
+    }
+    else if ((uint32_t)kGPIO_InterruptB == index)
+    {
+        base->INTENB[port] = base->INTENB[port] | (1UL << pin);
+    }
+    else
+    {
+        /*Should not enter here*/
+    }
+}
+
+/*!
+ * @brief Disables the specific pin interrupt.
+ *
+ * @param base GPIO base pointer.
+ * @param port   GPIO port number.
+ * @param pin GPIO pin number.
+ * @param index GPIO interrupt number.
+ */
+void GPIO_PinDisableInterrupt(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index)
+{
+    if ((uint32_t)kGPIO_InterruptA == index)
+    {
+        base->INTENA[port] = base->INTENA[port] & ~(1UL << pin);
+    }
+    else if ((uint32_t)kGPIO_InterruptB == index)
+    {
+        base->INTENB[port] = base->INTENB[port] & ~(1UL << pin);
+    }
+    else
+    {
+        /*Should not enter here*/
+    }
+}
+
+/*!
+ * @brief Clears the specific pin interrupt flag. Status flags are cleared by
+ *        writing a 1 to the corresponding bit position.
+ *
+ * @param base GPIO base pointer.
+ * @param port GPIO port number.
+ * @param index GPIO interrupt number.
+ * @param mask GPIO pin number macro.
+ */
+void GPIO_PinClearInterruptFlag(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index)
+{
+    if ((uint32_t)kGPIO_InterruptA == index)
+    {
+        base->INTSTATA[port] = 1UL << pin;
+    }
+    else if ((uint32_t)kGPIO_InterruptB == index)
+    {
+        base->INTSTATB[port] = 1UL << pin;
+    }
+    else
+    {
+        /*Should not enter here*/
+    }
+}
+#endif /* FSL_FEATURE_GPIO_HAS_INTERRUPT */

FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/drivers/fsl_gpio.h

@@ -0,0 +1,364 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2019 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _LPC_GPIO_H_
+#define _LPC_GPIO_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup lpc_gpio
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief LPC GPIO driver version. */
+#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 1, 5))
+/*@}*/
+
+/*! @brief LPC GPIO direction definition */
+typedef enum _gpio_pin_direction
+{
+    kGPIO_DigitalInput  = 0U, /*!< Set current pin as digital input*/
+    kGPIO_DigitalOutput = 1U, /*!< Set current pin as digital output*/
+} gpio_pin_direction_t;
+
+/*!
+ * @brief The GPIO pin configuration structure.
+ *
+ * Every pin can only be configured as either output pin or input pin at a time.
+ * If configured as a input pin, then leave the outputConfig unused.
+ */
+typedef struct _gpio_pin_config
+{
+    gpio_pin_direction_t pinDirection; /*!< GPIO direction, input or output */
+    /* Output configurations, please ignore if configured as a input one */
+    uint8_t outputLogic; /*!< Set default output logic, no use in input */
+} gpio_pin_config_t;
+
+#if (defined(FSL_FEATURE_GPIO_HAS_INTERRUPT) && FSL_FEATURE_GPIO_HAS_INTERRUPT)
+#define GPIO_PIN_INT_LEVEL 0x00U
+#define GPIO_PIN_INT_EDGE 0x01U
+
+#define PINT_PIN_INT_HIGH_OR_RISE_TRIGGER 0x00U
+#define PINT_PIN_INT_LOW_OR_FALL_TRIGGER 0x01U
+
+/*! @brief GPIO Pin Interrupt enable mode */
+typedef enum _gpio_pin_enable_mode
+{
+    kGPIO_PinIntEnableLevel = GPIO_PIN_INT_LEVEL, /*!< Generate Pin Interrupt on level mode */
+    kGPIO_PinIntEnableEdge  = GPIO_PIN_INT_EDGE   /*!< Generate Pin Interrupt on edge mode */
+} gpio_pin_enable_mode_t;
+
+/*! @brief GPIO Pin Interrupt enable polarity */
+typedef enum _gpio_pin_enable_polarity
+{
+    kGPIO_PinIntEnableHighOrRise =
+        PINT_PIN_INT_HIGH_OR_RISE_TRIGGER, /*!< Generate Pin Interrupt on high level or rising edge */
+    kGPIO_PinIntEnableLowOrFall =
+        PINT_PIN_INT_LOW_OR_FALL_TRIGGER /*!< Generate Pin Interrupt on low level or falling edge */
+} gpio_pin_enable_polarity_t;
+
+/*! @brief LPC GPIO interrupt index definition */
+typedef enum _gpio_interrupt_index
+{
+    kGPIO_InterruptA = 0U, /*!< Set current pin as interrupt A*/
+    kGPIO_InterruptB = 1U, /*!< Set current pin as interrupt B*/
+} gpio_interrupt_index_t;
+
+/*! @brief Configures the interrupt generation condition. */
+typedef struct _gpio_interrupt_config
+{
+    uint8_t mode;     /* The trigger mode of GPIO interrupts */
+    uint8_t polarity; /* The polarity of GPIO interrupts */
+} gpio_interrupt_config_t;
+#endif
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*! @name GPIO Configuration */
+/*@{*/
+
+/*!
+ * @brief Initializes the GPIO peripheral.
+ *
+ * This function ungates the GPIO clock.
+ *
+ * @param base   GPIO peripheral base pointer.
+ * @param port   GPIO port number.
+ */
+void GPIO_PortInit(GPIO_Type *base, uint32_t port);
+
+/*!
+ * @brief Initializes a GPIO pin used by the board.
+ *
+ * To initialize the GPIO, define a pin configuration, either input or output, in the user file.
+ * Then, call the GPIO_PinInit() function.
+ *
+ * This is an example to define an input pin or output pin configuration:
+ * @code
+ * Define a digital input pin configuration,
+ * gpio_pin_config_t config =
+ * {
+ *   kGPIO_DigitalInput,
+ *   0,
+ * }
+ * Define a digital output pin configuration,
+ * gpio_pin_config_t config =
+ * {
+ *   kGPIO_DigitalOutput,
+ *   0,
+ * }
+ * @endcode
+ *
+ * @param base   GPIO peripheral base pointer(Typically GPIO)
+ * @param port   GPIO port number
+ * @param pin    GPIO pin number
+ * @param config GPIO pin configuration pointer
+ */
+void GPIO_PinInit(GPIO_Type *base, uint32_t port, uint32_t pin, const gpio_pin_config_t *config);
+
+/*@}*/
+
+/*! @name GPIO Output Operations */
+/*@{*/
+
+/*!
+ * @brief Sets the output level of the one GPIO pin to the logic 1 or 0.
+ *
+ * @param base    GPIO peripheral base pointer(Typically GPIO)
+ * @param port   GPIO port number
+ * @param pin    GPIO pin number
+ * @param output  GPIO pin output logic level.
+ *        - 0: corresponding pin output low-logic level.
+ *        - 1: corresponding pin output high-logic level.
+ */
+static inline void GPIO_PinWrite(GPIO_Type *base, uint32_t port, uint32_t pin, uint8_t output)
+{
+    base->B[port][pin] = output;
+}
+
+/*@}*/
+/*! @name GPIO Input Operations */
+/*@{*/
+
+/*!
+ * @brief Reads the current input value of the GPIO PIN.
+ *
+ * @param base GPIO peripheral base pointer(Typically GPIO)
+ * @param port   GPIO port number
+ * @param pin    GPIO pin number
+ * @retval GPIO port input value
+ *        - 0: corresponding pin input low-logic level.
+ *        - 1: corresponding pin input high-logic level.
+ */
+static inline uint32_t GPIO_PinRead(GPIO_Type *base, uint32_t port, uint32_t pin)
+{
+    return (uint32_t)base->B[port][pin];
+}
+
+/*@}*/
+
+/*!
+ * @brief Sets the output level of the multiple GPIO pins to the logic 1.
+ *
+ * @param base GPIO peripheral base pointer(Typically GPIO)
+ * @param port GPIO port number
+ * @param mask GPIO pin number macro
+ */
+static inline void GPIO_PortSet(GPIO_Type *base, uint32_t port, uint32_t mask)
+{
+    base->SET[port] = mask;
+}
+
+/*!
+ * @brief Sets the output level of the multiple GPIO pins to the logic 0.
+ *
+ * @param base GPIO peripheral base pointer(Typically GPIO)
+ * @param port GPIO port number
+ * @param mask GPIO pin number macro
+ */
+static inline void GPIO_PortClear(GPIO_Type *base, uint32_t port, uint32_t mask)
+{
+    base->CLR[port] = mask;
+}
+
+/*!
+ * @brief Reverses current output logic of the multiple GPIO pins.
+ *
+ * @param base GPIO peripheral base pointer(Typically GPIO)
+ * @param port GPIO port number
+ * @param mask GPIO pin number macro
+ */
+static inline void GPIO_PortToggle(GPIO_Type *base, uint32_t port, uint32_t mask)
+{
+    base->NOT[port] = mask;
+}
+
+/*@}*/
+
+/*!
+ * @brief Reads the current input value of the whole GPIO port.
+ *
+ * @param base GPIO peripheral base pointer(Typically GPIO)
+ * @param port GPIO port number
+ */
+static inline uint32_t GPIO_PortRead(GPIO_Type *base, uint32_t port)
+{
+    return (uint32_t)base->PIN[port];
+}
+
+/*@}*/
+/*! @name GPIO Mask Operations */
+/*@{*/
+
+/*!
+ * @brief Sets port mask, 0 - enable pin, 1 - disable pin.
+ *
+ * @param base GPIO peripheral base pointer(Typically GPIO)
+ * @param port GPIO port number
+ * @param mask GPIO pin number macro
+ */
+static inline void GPIO_PortMaskedSet(GPIO_Type *base, uint32_t port, uint32_t mask)
+{
+    base->MASK[port] = mask;
+}
+
+/*!
+ * @brief Sets the output level of the masked GPIO port. Only pins enabled by GPIO_SetPortMask() will be affected.
+ *
+ * @param base    GPIO peripheral base pointer(Typically GPIO)
+ * @param port   GPIO port number
+ * @param output  GPIO port output value.
+ */
+static inline void GPIO_PortMaskedWrite(GPIO_Type *base, uint32_t port, uint32_t output)
+{
+    base->MPIN[port] = output;
+}
+
+/*!
+ * @brief Reads the current input value of the masked GPIO port. Only pins enabled by GPIO_SetPortMask() will be
+ * affected.
+ *
+ * @param base   GPIO peripheral base pointer(Typically GPIO)
+ * @param port   GPIO port number
+ * @retval       masked GPIO port value
+ */
+static inline uint32_t GPIO_PortMaskedRead(GPIO_Type *base, uint32_t port)
+{
+    return (uint32_t)base->MPIN[port];
+}
+
+#if defined(FSL_FEATURE_GPIO_HAS_INTERRUPT) && FSL_FEATURE_GPIO_HAS_INTERRUPT
+/*!
+ * @brief Configures the gpio pin interrupt.
+ *
+ * @param base GPIO base pointer.
+ * @param port GPIO port number
+ * @param pin GPIO pin number.
+ * @param config GPIO pin interrupt configuration..
+ */
+void GPIO_SetPinInterruptConfig(GPIO_Type *base, uint32_t port, uint32_t pin, gpio_interrupt_config_t *config);
+
+/*!
+ * @brief Enables multiple pins interrupt.
+ *
+ * @param base GPIO base pointer.
+ * @param port GPIO port number.
+ * @param index GPIO interrupt number.
+ * @param mask GPIO pin number macro.
+ */
+void GPIO_PortEnableInterrupts(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask);
+
+/*!
+ * @brief Disables multiple pins interrupt.
+ *
+ * @param base GPIO base pointer.
+ * @param port GPIO port number.
+ * @param index GPIO interrupt number.
+ * @param mask GPIO pin number macro.
+ */
+void GPIO_PortDisableInterrupts(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask);
+
+/*!
+ * @brief Clears pin interrupt flag. Status flags are cleared by
+ *        writing a 1 to the corresponding bit position.
+ *
+ * @param base GPIO base pointer.
+ * @param port   GPIO port number.
+ * @param index GPIO interrupt number.
+ * @param mask GPIO pin number macro.
+ */
+void GPIO_PortClearInterruptFlags(GPIO_Type *base, uint32_t port, uint32_t index, uint32_t mask);
+
+/*!
+ * @ Read port interrupt status.
+ *
+ * @param base GPIO base pointer.
+ * @param port GPIO port number
+ * @param index GPIO interrupt number.
+ * @retval masked GPIO status value
+ */
+uint32_t GPIO_PortGetInterruptStatus(GPIO_Type *base, uint32_t port, uint32_t index);
+
+/*!
+ * @brief Enables the specific pin interrupt.
+ *
+ * @param base GPIO base pointer.
+ * @param port GPIO port number.
+ * @param pin GPIO pin number.
+ * @param index GPIO interrupt number.
+ */
+void GPIO_PinEnableInterrupt(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index);
+
+/*!
+ * @brief Disables the specific pin interrupt.
+ *
+ * @param base GPIO base pointer.
+ * @param port GPIO port number.
+ * @param pin GPIO pin number.
+ * @param index GPIO interrupt number.
+ */
+void GPIO_PinDisableInterrupt(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index);
+
+/*!
+ * @brief Clears the specific pin interrupt flag. Status flags are cleared by
+ *        writing a 1 to the corresponding bit position.
+ *
+ * @param base GPIO base pointer.
+ * @param port GPIO port number.
+ * @param pin GPIO pin number.
+ * @param index GPIO interrupt number.
+ */
+void GPIO_PinClearInterruptFlag(GPIO_Type *base, uint32_t port, uint32_t pin, uint32_t index);
+
+#endif /* FSL_FEATURE_GPIO_HAS_INTERRUPT */
+
+/*@}*/
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+
+#endif /* _LPC_GPIO_H_*/

FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/drivers/fsl_iocon.h

@@ -0,0 +1,288 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2019 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_IOCON_H_
+#define _FSL_IOCON_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup lpc_iocon
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.lpc_iocon"
+#endif
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief IOCON driver version 2.1.1. */
+#define FSL_IOCON_DRIVER_VERSION (MAKE_VERSION(2, 1, 1))
+/*@}*/
+
+/**
+ * @brief Array of IOCON pin definitions passed to IOCON_SetPinMuxing() must be in this format
+ */
+typedef struct _iocon_group
+{
+    uint32_t port : 8;      /* Pin port */
+    uint32_t pin : 8;       /* Pin number */
+    uint32_t ionumber : 8;  /* IO number */
+    uint32_t modefunc : 16; /* Function and mode */
+} iocon_group_t;
+
+/**
+ * @brief IOCON function and mode selection definitions
+ * @note See the User Manual for specific modes and functions supported by the various pins.
+ */
+#if defined(FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH) && (FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH == 4)
+#define IOCON_FUNC0 0x0  /*!< Selects pin function 0 */
+#define IOCON_FUNC1 0x1  /*!< Selects pin function 1 */
+#define IOCON_FUNC2 0x2  /*!< Selects pin function 2 */
+#define IOCON_FUNC3 0x3  /*!< Selects pin function 3 */
+#define IOCON_FUNC4 0x4  /*!< Selects pin function 4 */
+#define IOCON_FUNC5 0x5  /*!< Selects pin function 5 */
+#define IOCON_FUNC6 0x6  /*!< Selects pin function 6 */
+#define IOCON_FUNC7 0x7  /*!< Selects pin function 7 */
+#define IOCON_FUNC8 0x8  /*!< Selects pin function 8 */
+#define IOCON_FUNC9 0x9  /*!< Selects pin function 9 */
+#define IOCON_FUNC10 0xA /*!< Selects pin function 10 */
+#define IOCON_FUNC11 0xB /*!< Selects pin function 11 */
+#define IOCON_FUNC12 0xC /*!< Selects pin function 12 */
+#define IOCON_FUNC13 0xD /*!< Selects pin function 13 */
+#define IOCON_FUNC14 0xE /*!< Selects pin function 14 */
+#define IOCON_FUNC15 0xF /*!< Selects pin function 15 */
+#if defined(IOCON_PIO_MODE_SHIFT)
+#define IOCON_MODE_INACT (0x0 << IOCON_PIO_MODE_SHIFT)    /*!< No addition pin function */
+#define IOCON_MODE_PULLDOWN (0x1 << IOCON_PIO_MODE_SHIFT) /*!< Selects pull-down function */
+#define IOCON_MODE_PULLUP (0x2 << IOCON_PIO_MODE_SHIFT)   /*!< Selects pull-up function */
+#define IOCON_MODE_REPEATER (0x3 << IOCON_PIO_MODE_SHIFT) /*!< Selects pin repeater function */
+#endif
+
+#if defined(IOCON_PIO_I2CSLEW_SHIFT)
+#define IOCON_GPIO_MODE (0x1 << IOCON_PIO_I2CSLEW_SHIFT) /*!< GPIO Mode */
+#define IOCON_I2C_SLEW (0x0 << IOCON_PIO_I2CSLEW_SHIFT)  /*!< I2C Slew Rate Control */
+#endif
+
+#if defined(IOCON_PIO_EGP_SHIFT)
+#define IOCON_GPIO_MODE (0x1 << IOCON_PIO_EGP_SHIFT) /*!< GPIO Mode */
+#define IOCON_I2C_SLEW (0x0 << IOCON_PIO_EGP_SHIFT)  /*!< I2C Slew Rate Control */
+#endif
+
+#if defined(IOCON_PIO_SLEW_SHIFT)
+#define IOCON_SLEW_STANDARD (0x0 << IOCON_PIO_SLEW_SHIFT) /*!< Driver Slew Rate Control */
+#define IOCON_SLEW_FAST (0x1 << IOCON_PIO_SLEW_SHIFT)     /*!< Driver Slew Rate Control */
+#endif
+
+#if defined(IOCON_PIO_INVERT_SHIFT)
+#define IOCON_INV_EN (0x1 << IOCON_PIO_INVERT_SHIFT) /*!< Enables invert function on input */
+#endif
+
+#if defined(IOCON_PIO_DIGIMODE_SHIFT)
+#define IOCON_ANALOG_EN (0x0 << IOCON_PIO_DIGIMODE_SHIFT) /*!< Enables analog function by setting 0 to bit 7 */
+#define IOCON_DIGITAL_EN \
+    (0x1 << IOCON_PIO_DIGIMODE_SHIFT) /*!< Enables digital function by setting 1 to bit 7(default) */
+#endif
+
+#if defined(IOCON_PIO_FILTEROFF_SHIFT)
+#define IOCON_INPFILT_OFF (0x1 << IOCON_PIO_FILTEROFF_SHIFT) /*!< Input filter Off for GPIO pins */
+#define IOCON_INPFILT_ON (0x0 << IOCON_PIO_FILTEROFF_SHIFT)  /*!< Input filter On for GPIO pins */
+#endif
+
+#if defined(IOCON_PIO_I2CDRIVE_SHIFT)
+#define IOCON_I2C_LOWDRIVER (0x0 << IOCON_PIO_I2CDRIVE_SHIFT)  /*!< Low drive, Output drive sink is 4 mA */
+#define IOCON_I2C_HIGHDRIVER (0x1 << IOCON_PIO_I2CDRIVE_SHIFT) /*!< High drive, Output drive sink is 20 mA */
+#endif
+
+#if defined(IOCON_PIO_OD_SHIFT)
+#define IOCON_OPENDRAIN_EN (0x1 << IOCON_PIO_OD_SHIFT) /*!< Enables open-drain function */
+#endif
+
+#if defined(IOCON_PIO_I2CFILTER_SHIFT)
+#define IOCON_I2CFILTER_OFF (0x1 << IOCON_PIO_I2CFILTER_SHIFT) /*!<  I2C 50 ns glitch filter enabled */
+#define IOCON_I2CFILTER_ON (0x0 << IOCON_PIO_I2CFILTER_SHIFT)  /*!<  I2C 50 ns glitch filter not enabled,  */
+#endif
+
+#if defined(IOCON_PIO_ASW_SHIFT)
+#define IOCON_AWS_EN (0x1 << IOCON_PIO_ASW_SHIFT) /*!< Enables analog switch function */
+#endif
+
+#if defined(IOCON_PIO_SSEL_SHIFT)
+#define IOCON_SSEL_3V3 (0x0 << IOCON_PIO_SSEL_SHIFT) /*!< 3V3 signaling in I2C mode */
+#define IOCON_SSEL_1V8 (0x1 << IOCON_PIO_SSEL_SHIFT) /*!< 1V8 signaling in I2C mode */
+#endif
+
+#if defined(IOCON_PIO_ECS_SHIFT)
+#define IOCON_ECS_OFF (0x0 << IOCON_PIO_ECS_SHIFT) /*!< IO is an open drain cell */
+#define IOCON_ECS_ON (0x1 << IOCON_PIO_ECS_SHIFT)  /*!< Pull-up resistor is connected */
+#endif
+
+#if defined(IOCON_PIO_S_MODE_SHIFT)
+#define IOCON_S_MODE_0CLK (0x0 << IOCON_PIO_S_MODE_SHIFT) /*!< Bypass input filter */
+#define IOCON_S_MODE_1CLK                                                                              \
+    (0x1 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 1 filter clock are rejected \ \ \ \ \
+                                     */
+#define IOCON_S_MODE_2CLK                                                                               \
+    (0x2 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 2 filter clock2 are rejected \ \ \ \ \
+                                     */
+#define IOCON_S_MODE_3CLK                                                                               \
+    (0x3 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 3 filter clock2 are rejected \ \ \ \ \
+                                     */
+#define IOCON_S_MODE(clks) ((clks) << IOCON_PIO_S_MODE_SHIFT) /*!< Select clocks for digital input filter mode */
+#endif
+
+#if defined(IOCON_PIO_CLK_DIV_SHIFT)
+#define IOCON_CLKDIV(div) \
+    ((div)                \
+     << IOCON_PIO_CLK_DIV_SHIFT) /*!< Select peripheral clock divider for input filter sampling clock, 2^n, n=0-6 */
+#endif
+
+#else
+#define IOCON_FUNC0 0x0 /*!< Selects pin function 0 */
+#define IOCON_FUNC1 0x1 /*!< Selects pin function 1 */
+#define IOCON_FUNC2 0x2 /*!< Selects pin function 2 */
+#define IOCON_FUNC3 0x3 /*!< Selects pin function 3 */
+#define IOCON_FUNC4 0x4 /*!< Selects pin function 4 */
+#define IOCON_FUNC5 0x5 /*!< Selects pin function 5 */
+#define IOCON_FUNC6 0x6 /*!< Selects pin function 6 */
+#define IOCON_FUNC7 0x7 /*!< Selects pin function 7 */
+
+#if defined(IOCON_PIO_MODE_SHIFT)
+#define IOCON_MODE_INACT (0x0 << IOCON_PIO_MODE_SHIFT)    /*!< No addition pin function */
+#define IOCON_MODE_PULLDOWN (0x1 << IOCON_PIO_MODE_SHIFT) /*!< Selects pull-down function */
+#define IOCON_MODE_PULLUP (0x2 << IOCON_PIO_MODE_SHIFT)   /*!< Selects pull-up function */
+#define IOCON_MODE_REPEATER (0x3 << IOCON_PIO_MODE_SHIFT) /*!< Selects pin repeater function */
+#endif
+
+#if defined(IOCON_PIO_I2CSLEW_SHIFT)
+#define IOCON_GPIO_MODE (0x1 << IOCON_PIO_I2CSLEW_SHIFT) /*!< GPIO Mode */
+#define IOCON_I2C_SLEW (0x0 << IOCON_PIO_I2CSLEW_SHIFT)  /*!< I2C Slew Rate Control */
+#endif
+
+#if defined(IOCON_PIO_EGP_SHIFT)
+#define IOCON_GPIO_MODE (0x1 << IOCON_PIO_EGP_SHIFT) /*!< GPIO Mode */
+#define IOCON_I2C_SLEW (0x0 << IOCON_PIO_EGP_SHIFT)  /*!< I2C Slew Rate Control */
+#endif
+
+#if defined(IOCON_PIO_INVERT_SHIFT)
+#define IOCON_INV_EN (0x1 << IOCON_PIO_INVERT_SHIFT) /*!< Enables invert function on input */
+#endif
+
+#if defined(IOCON_PIO_DIGIMODE_SHIFT)
+#define IOCON_ANALOG_EN (0x0 << IOCON_PIO_DIGIMODE_SHIFT) /*!< Enables analog function by setting 0 to bit 7 */
+#define IOCON_DIGITAL_EN \
+    (0x1 << IOCON_PIO_DIGIMODE_SHIFT) /*!< Enables digital function by setting 1 to bit 7(default) */
+#endif
+
+#if defined(IOCON_PIO_FILTEROFF_SHIFT)
+#define IOCON_INPFILT_OFF (0x1 << IOCON_PIO_FILTEROFF_SHIFT) /*!< Input filter Off for GPIO pins */
+#define IOCON_INPFILT_ON (0x0 << IOCON_PIO_FILTEROFF_SHIFT)  /*!< Input filter On for GPIO pins */
+#endif
+
+#if defined(IOCON_PIO_I2CDRIVE_SHIFT)
+#define IOCON_I2C_LOWDRIVER (0x0 << IOCON_PIO_I2CDRIVE_SHIFT)  /*!< Low drive, Output drive sink is 4 mA */
+#define IOCON_I2C_HIGHDRIVER (0x1 << IOCON_PIO_I2CDRIVE_SHIFT) /*!< High drive, Output drive sink is 20 mA */
+#endif
+
+#if defined(IOCON_PIO_OD_SHIFT)
+#define IOCON_OPENDRAIN_EN (0x1 << IOCON_PIO_OD_SHIFT) /*!< Enables open-drain function */
+#endif
+
+#if defined(IOCON_PIO_I2CFILTER_SHIFT)
+#define IOCON_I2CFILTER_OFF (0x1 << IOCON_PIO_I2CFILTER_SHIFT) /*!<  I2C 50 ns glitch filter enabled */
+#define IOCON_I2CFILTER_ON (0x0 << IOCON_PIO_I2CFILTER_SHIFT)  /*!<  I2C 50 ns glitch filter not enabled */
+#endif
+
+#if defined(IOCON_PIO_S_MODE_SHIFT)
+#define IOCON_S_MODE_0CLK (0x0 << IOCON_PIO_S_MODE_SHIFT) /*!< Bypass input filter */
+#define IOCON_S_MODE_1CLK                                                                              \
+    (0x1 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 1 filter clock are rejected \ \ \ \ \
+                                     */
+#define IOCON_S_MODE_2CLK                                                                               \
+    (0x2 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 2 filter clock2 are rejected \ \ \ \ \
+                                     */
+#define IOCON_S_MODE_3CLK                                                                               \
+    (0x3 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 3 filter clock2 are rejected \ \ \ \ \
+                                     */
+#define IOCON_S_MODE(clks) ((clks) << IOCON_PIO_S_MODE_SHIFT) /*!< Select clocks for digital input filter mode */
+#endif
+
+#if defined(IOCON_PIO_CLK_DIV_SHIFT)
+#define IOCON_CLKDIV(div) \
+    ((div)                \
+     << IOCON_PIO_CLK_DIV_SHIFT) /*!< Select peripheral clock divider for input filter sampling clock, 2^n, n=0-6 */
+#endif
+
+#endif
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+#if (defined(FSL_FEATURE_IOCON_ONE_DIMENSION) && (FSL_FEATURE_IOCON_ONE_DIMENSION == 1))
+/**
+ * @brief   Sets I/O Control pin mux
+ * @param   base        : The base of IOCON peripheral on the chip
+ * @param   ionumber    : GPIO number to mux
+ * @param   modefunc    : OR'ed values of type IOCON_*
+ * @return  Nothing
+ */
+__STATIC_INLINE void IOCON_PinMuxSet(IOCON_Type *base, uint8_t ionumber, uint32_t modefunc)
+{
+    base->PIO[ionumber] = modefunc;
+}
+#else
+/**
+ * @brief   Sets I/O Control pin mux
+ * @param   base        : The base of IOCON peripheral on the chip
+ * @param   port        : GPIO port to mux
+ * @param   pin         : GPIO pin to mux
+ * @param   modefunc    : OR'ed values of type IOCON_*
+ * @return  Nothing
+ */
+__STATIC_INLINE void IOCON_PinMuxSet(IOCON_Type *base, uint8_t port, uint8_t pin, uint32_t modefunc)
+{
+    base->PIO[port][pin] = modefunc;
+}
+#endif
+
+/**
+ * @brief   Set all I/O Control pin muxing
+ * @param   base        : The base of IOCON peripheral on the chip
+ * @param   pinArray    : Pointer to array of pin mux selections
+ * @param   arrayLength : Number of entries in pinArray
+ * @return  Nothing
+ */
+__STATIC_INLINE void IOCON_SetPinMuxing(IOCON_Type *base, const iocon_group_t *pinArray, uint32_t arrayLength)
+{
+    uint32_t i;
+
+    for (i = 0; i < arrayLength; i++)
+    {
+#if (defined(FSL_FEATURE_IOCON_ONE_DIMENSION) && (FSL_FEATURE_IOCON_ONE_DIMENSION == 1))
+        IOCON_PinMuxSet(base, pinArray[i].ionumber, pinArray[i].modefunc);
+#else
+        IOCON_PinMuxSet(base, pinArray[i].port, pinArray[i].pin, pinArray[i].modefunc);
+#endif /* FSL_FEATURE_IOCON_ONE_DIMENSION */
+    }
+}
+
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* _FSL_IOCON_H_ */

FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/drivers/fsl_power.c

@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016, NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#include "fsl_common.h"
+#include "fsl_power.h"
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.power"
+#endif
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/* Empty file since implementation is in header file and power library */

FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/drivers/fsl_power.h

@@ -0,0 +1,225 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016, NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _FSL_POWER_H_
+#define _FSL_POWER_H_
+
+#include "fsl_common.h"
+
+/*! @addtogroup power */
+/*! @{ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief power driver version 2.0.0. */
+#define FSL_POWER_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*@}*/
+
+#define MAKE_PD_BITS(reg, slot) (((reg) << 8) | (slot))
+#define PDRCFG0 0x0U
+#define PDRCFG1 0x1U
+
+typedef enum pd_bits
+{
+    kPDRUNCFG_LP_REG = MAKE_PD_BITS(PDRCFG0, 2U),
+    kPDRUNCFG_PD_FRO_EN = MAKE_PD_BITS(PDRCFG0, 4U),
+    kPDRUNCFG_PD_TS = MAKE_PD_BITS(PDRCFG0, 6U),
+    kPDRUNCFG_PD_BOD_RESET = MAKE_PD_BITS(PDRCFG0, 7U),
+    kPDRUNCFG_PD_BOD_INTR = MAKE_PD_BITS(PDRCFG0, 8U),
+    kPDRUNCFG_PD_VD2_ANA = MAKE_PD_BITS(PDRCFG0, 9U),
+    kPDRUNCFG_PD_ADC0 = MAKE_PD_BITS(PDRCFG0, 10U),
+    kPDRUNCFG_PD_RAM0 = MAKE_PD_BITS(PDRCFG0, 13U),
+    kPDRUNCFG_PD_RAM1 = MAKE_PD_BITS(PDRCFG0, 14U),
+    kPDRUNCFG_PD_RAM2 = MAKE_PD_BITS(PDRCFG0, 15U),
+    kPDRUNCFG_PD_RAM3 = MAKE_PD_BITS(PDRCFG0, 16U),
+    kPDRUNCFG_PD_ROM = MAKE_PD_BITS(PDRCFG0, 17U),
+    kPDRUNCFG_PD_VDDA = MAKE_PD_BITS(PDRCFG0, 19U),
+    kPDRUNCFG_PD_WDT_OSC = MAKE_PD_BITS(PDRCFG0, 20U),
+    kPDRUNCFG_PD_USB0_PHY = MAKE_PD_BITS(PDRCFG0, 21U),
+    kPDRUNCFG_PD_SYS_PLL0 = MAKE_PD_BITS(PDRCFG0, 22U),
+    kPDRUNCFG_PD_VREFP = MAKE_PD_BITS(PDRCFG0, 23U),
+    kPDRUNCFG_PD_FLASH_BG = MAKE_PD_BITS(PDRCFG0, 25U),
+    kPDRUNCFG_PD_VD3 = MAKE_PD_BITS(PDRCFG0, 26U),
+    kPDRUNCFG_PD_VD4 = MAKE_PD_BITS(PDRCFG0, 27U),
+    kPDRUNCFG_PD_VD5 = MAKE_PD_BITS(PDRCFG0, 28U),
+    kPDRUNCFG_PD_VD6 = MAKE_PD_BITS(PDRCFG0, 29U),
+    kPDRUNCFG_REQ_DELAY = MAKE_PD_BITS(PDRCFG0, 30U),
+    kPDRUNCFG_FORCE_RBB = MAKE_PD_BITS(PDRCFG0, 31U),
+
+    kPDRUNCFG_PD_USB1_PHY = MAKE_PD_BITS(PDRCFG1, 0U),
+    kPDRUNCFG_PD_USB_PLL = MAKE_PD_BITS(PDRCFG1, 1U),
+    kPDRUNCFG_PD_AUDIO_PLL = MAKE_PD_BITS(PDRCFG1, 2U),
+    kPDRUNCFG_PD_SYS_OSC = MAKE_PD_BITS(PDRCFG1, 3U),
+    kPDRUNCFG_PD_EEPROM = MAKE_PD_BITS(PDRCFG1, 5U),
+    kPDRUNCFG_PD_rng = MAKE_PD_BITS(PDRCFG1, 6U),
+
+    /*
+    This enum member has no practical meaning,it is used to avoid MISRA issue,
+    user should not trying to use it.
+    */
+    kPDRUNCFG_ForceUnsigned = (int)0x80000000U,
+} pd_bit_t;
+
+/* Power mode configuration API parameter */
+typedef enum _power_mode_config
+{
+    kPmu_Sleep = 0U,
+    kPmu_Deep_Sleep = 1U,
+    kPmu_Deep_PowerDown = 2U,
+} power_mode_cfg_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*!
+* @name Power Configuration
+* @{
+*/
+
+/*!
+ * @brief API to enable PDRUNCFG bit in the Syscon. Note that enabling the bit powers down the peripheral
+ *
+ * @param en    peripheral for which to enable the PDRUNCFG bit
+ * @return none
+ */
+static inline void POWER_EnablePD(pd_bit_t en)
+{
+    /* PDRUNCFGSET */
+    SYSCON->PDRUNCFGSET[((uint32_t)en >> 8UL)] = (1UL << ((uint32_t)en & 0xffU));
+}
+
+/*!
+ * @brief API to disable PDRUNCFG bit in the Syscon. Note that disabling the bit powers up the peripheral
+ *
+ * @param en    peripheral for which to disable the PDRUNCFG bit
+ * @return none
+ */
+static inline void POWER_DisablePD(pd_bit_t en)
+{
+    /* PDRUNCFGCLR */
+    SYSCON->PDRUNCFGCLR[((uint32_t)en >> 8UL)] = (1UL << ((uint32_t)en & 0xffU));
+}
+
+/*!
+ * @brief API to enable deep sleep bit in the ARM Core.
+ *
+ * @param none
+ * @return none
+ */
+static inline void POWER_EnableDeepSleep(void)
+{
+    SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+}
+
+/*!
+ * @brief API to disable deep sleep bit in the ARM Core.
+ *
+ * @param none
+ * @return none
+ */
+static inline void POWER_DisableDeepSleep(void)
+{
+    SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+}
+
+/*!
+ * @brief Power Library API to reload OTP.
+ *        This API must be called if VD6 is power down
+ *        and power back again since FROHF TRIM value
+ *        is store in OTP. If not, when calling FROHF settng
+ *        API in clock driver then the FROHF clock out put
+ *        will be inaccurate.
+ * @return none
+ */
+void POWER_OtpReload(void);
+
+/*!
+ * @brief Power Library API to power the PLLs.
+ *
+ * @param none
+ * @return none
+ */
+void POWER_SetPLL(void);
+
+/*!
+ * @brief Power Library API to power the USB PHY.
+ *
+ * @param none
+ * @return none
+ */
+void POWER_SetUsbPhy(void);
+
+/*!
+ * @brief Power Library API to enter different power mode.
+ *
+ * @param exclude_from_pd  Bit mask of the PDRUNCFG0(low 32bits) and PDRUNCFG1(high 32bits) that needs to be powered on
+ * during power mode selected.
+ * @return none
+ */
+void POWER_EnterPowerMode(power_mode_cfg_t mode, uint64_t exclude_from_pd);
+
+/*!
+ * @brief Power Library API to enter sleep mode.
+ *
+ * @return none
+ */
+void POWER_EnterSleep(void);
+
+/*!
+ * @brief Power Library API to enter deep sleep mode.
+ *
+ * @param exclude_from_pd  Bit mask of the PDRUNCFG0(low 32bits) and PDRUNCFG1(high 32bits) bits that needs to be
+ * powered on during deep sleep
+ * @return none
+ */
+void POWER_EnterDeepSleep(uint64_t exclude_from_pd);
+
+/*!
+ * @brief Power Library API to enter deep power down mode.
+ *
+ * @param exclude_from_pd   Bit mask of the PDRUNCFG0(low 32bits) and PDRUNCFG1(high 32bits) that needs to be powered on
+ during deep power
+ *                          down mode, but this is has no effect as the voltages are cut off.
+
+ * @return none
+ */
+void POWER_EnterDeepPowerDown(uint64_t exclude_from_pd);
+
+/*!
+ * @brief Power Library API to choose normal regulation and set the voltage for the desired operating frequency.
+ *
+ * @param freq  - The desired frequency at which the part would like to operate,
+ *                note that the voltage and flash wait states should be set before changing frequency
+ * @return none
+ */
+void POWER_SetVoltageForFreq(uint32_t freq);
+
+/*!
+ * @brief Power Library API to return the library version.
+ *
+ * @param none
+ * @return version number of the power library
+ */
+uint32_t POWER_GetLibVersion(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _FSL_POWER_H_ */

FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/drivers/fsl_reset.c

@@ -0,0 +1,132 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016, NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "fsl_reset.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.reset"
+#endif
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+#if ((defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0)) || \
+     (defined(FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT) && (FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT > 0)))
+
+/*!
+ * brief Assert reset to peripheral.
+ *
+ * Asserts reset signal to specified peripheral module.
+ *
+ * param peripheral Assert reset to this peripheral. The enum argument contains encoding of reset register
+ *                   and reset bit position in the reset register.
+ */
+void RESET_SetPeripheralReset(reset_ip_name_t peripheral)
+{
+    const uint32_t regIndex = ((uint32_t)peripheral & 0xFFFF0000u) >> 16;
+    const uint32_t bitPos = ((uint32_t)peripheral & 0x0000FFFFu);
+    const uint32_t bitMask = 1UL << bitPos;
+
+    assert(bitPos < 32UL);
+
+    /* ASYNC_SYSCON registers have offset 1024 */
+    if (regIndex >= SYSCON_PRESETCTRL_COUNT)
+    {
+        /* reset register is in ASYNC_SYSCON */
+
+        /* set bit */
+        ASYNC_SYSCON->ASYNCPRESETCTRLSET = bitMask;
+        /* wait until it reads 0b1 */
+        while (0u == (ASYNC_SYSCON->ASYNCPRESETCTRL & bitMask))
+        {
+        }
+    }
+    else
+    {
+        /* reset register is in SYSCON */
+
+        /* set bit */
+        SYSCON->PRESETCTRLSET[regIndex] = bitMask;
+        /* wait until it reads 0b1 */
+        while (0u == (SYSCON->PRESETCTRL[regIndex] & bitMask))
+        {
+        }
+    }
+}
+
+/*!
+ * brief Clear reset to peripheral.
+ *
+ * Clears reset signal to specified peripheral module, allows it to operate.
+ *
+ * param peripheral Clear reset to this peripheral. The enum argument contains encoding of reset register
+ *                   and reset bit position in the reset register.
+ */
+void RESET_ClearPeripheralReset(reset_ip_name_t peripheral)
+{
+    const uint32_t regIndex = ((uint32_t)peripheral & 0xFFFF0000u) >> 16;
+    const uint32_t bitPos = ((uint32_t)peripheral & 0x0000FFFFu);
+    const uint32_t bitMask = 1UL << bitPos;
+
+    assert(bitPos < 32UL);
+
+    /* ASYNC_SYSCON registers have offset 1024 */
+    if (regIndex >= SYSCON_PRESETCTRL_COUNT)
+    {
+        /* reset register is in ASYNC_SYSCON */
+
+        /* clear bit */
+        ASYNC_SYSCON->ASYNCPRESETCTRLCLR = bitMask;
+        /* wait until it reads 0b0 */
+        while (bitMask == (ASYNC_SYSCON->ASYNCPRESETCTRL & bitMask))
+        {
+        }
+    }
+    else
+    {
+        /* reset register is in SYSCON */
+
+        /* clear bit */
+        SYSCON->PRESETCTRLCLR[regIndex] = bitMask;
+        /* wait until it reads 0b0 */
+        while (bitMask == (SYSCON->PRESETCTRL[regIndex] & bitMask))
+        {
+        }
+    }
+}
+
+/*!
+ * brief Reset peripheral module.
+ *
+ * Reset peripheral module.
+ *
+ * param peripheral Peripheral to reset. The enum argument contains encoding of reset register
+ *                   and reset bit position in the reset register.
+ */
+void RESET_PeripheralReset(reset_ip_name_t peripheral)
+{
+    RESET_SetPeripheralReset(peripheral);
+    RESET_ClearPeripheralReset(peripheral);
+}
+
+#endif /* FSL_FEATURE_SOC_SYSCON_COUNT || FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT */

FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/drivers/fsl_reset.h

@@ -0,0 +1,277 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016, NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _FSL_RESET_H_
+#define _FSL_RESET_H_
+
+#include <assert.h>
+#include <stdbool.h>
+#include <stdint.h>
+#include <string.h>
+#include "fsl_device_registers.h"
+
+/*! @addtogroup reset */
+/*! @{ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief reset driver version 2.0.1. */
+#define FSL_RESET_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
+/*@}*/
+
+/*!
+ * @brief Enumeration for peripheral reset control bits
+ *
+ * Defines the enumeration for peripheral reset control bits in PRESETCTRL/ASYNCPRESETCTRL registers
+ */
+typedef enum _SYSCON_RSTn
+{
+    kSPIFI_RST_SHIFT_RSTn = 0 | 10U,         /**< SPIFI reset control */
+    kMUX_RST_SHIFT_RSTn = 0 | 11U,           /**< Input mux reset control */
+    kIOCON_RST_SHIFT_RSTn = 0 | 13U,         /**< IOCON reset control */
+    kGPIO0_RST_SHIFT_RSTn = 0 | 14U,         /**< GPIO0 reset control */
+    kGPIO1_RST_SHIFT_RSTn = 0 | 15U,         /**< GPIO1 reset control */
+    kGPIO2_RST_SHIFT_RSTn = 0 | 16U,         /**< GPIO2 reset control */
+    kGPIO3_RST_SHIFT_RSTn = 0 | 17U,         /**< GPIO3 reset control */
+    kPINT_RST_SHIFT_RSTn = 0 | 18U,          /**< Pin interrupt (PINT) reset control */
+    kGINT_RST_SHIFT_RSTn = 0 | 19U,          /**< Grouped interrupt (PINT) reset control. */
+    kDMA_RST_SHIFT_RSTn = 0 | 20U,           /**< DMA reset control */
+    kCRC_RST_SHIFT_RSTn = 0 | 21U,           /**< CRC reset control */
+    kWWDT_RST_SHIFT_RSTn = 0 | 22U,          /**< Watchdog timer reset control */
+    kADC0_RST_SHIFT_RSTn = 0 | 27U,          /**< ADC0 reset control */
+
+    kMRT_RST_SHIFT_RSTn = 65536 | 0U,        /**< Multi-rate timer (MRT) reset control */
+    kSCT0_RST_SHIFT_RSTn = 65536 | 2U,       /**< SCTimer/PWM 0 (SCT0) reset control */
+    kMCAN0_RST_SHIFT_RSTn = 65536 | 7U,      /**< MCAN0 reset control */
+    kMCAN1_RST_SHIFT_RSTn = 65536 | 8U,      /**< MCAN1 reset control */
+    kUTICK_RST_SHIFT_RSTn = 65536 | 10U,     /**< Micro-tick timer reset control */
+    kFC0_RST_SHIFT_RSTn = 65536 | 11U,       /**< Flexcomm Interface 0 reset control */
+    kFC1_RST_SHIFT_RSTn = 65536 | 12U,       /**< Flexcomm Interface 1 reset control */
+    kFC2_RST_SHIFT_RSTn = 65536 | 13U,       /**< Flexcomm Interface 2 reset control */
+    kFC3_RST_SHIFT_RSTn = 65536 | 14U,       /**< Flexcomm Interface 3 reset control */
+    kFC4_RST_SHIFT_RSTn = 65536 | 15U,       /**< Flexcomm Interface 4 reset control */
+    kFC5_RST_SHIFT_RSTn = 65536 | 16U,       /**< Flexcomm Interface 5 reset control */
+    kFC6_RST_SHIFT_RSTn = 65536 | 17U,       /**< Flexcomm Interface 6 reset control */
+    kFC7_RST_SHIFT_RSTn = 65536 | 18U,       /**< Flexcomm Interface 7 reset control */
+    kDMIC_RST_SHIFT_RSTn = 65536 | 19U,      /**< Digital microphone interface reset control */
+    kCT32B2_RST_SHIFT_RSTn = 65536 | 22U,    /**< CT32B2 reset control */
+    kUSB0D_RST_SHIFT_RSTn = 65536 | 25U,     /**< USB0D reset control */
+    kCT32B0_RST_SHIFT_RSTn = 65536 | 26U,    /**< CT32B0 reset control */
+    kCT32B1_RST_SHIFT_RSTn = 65536 | 27U,    /**< CT32B1 reset control */
+
+    kLCD_RST_SHIFT_RSTn = 131072 | 2U,       /**< LCD reset control */
+    kSDIO_RST_SHIFT_RSTn = 131072 | 3U,      /**< SDIO reset control */
+    kUSB1H_RST_SHIFT_RSTn = 131072 | 4U,     /**< USB1H reset control */
+    kUSB1D_RST_SHIFT_RSTn = 131072 | 5U,     /**< USB1D reset control */
+    kUSB1RAM_RST_SHIFT_RSTn = 131072 | 6U,   /**< USB1RAM reset control */
+    kEMC_RST_SHIFT_RSTn = 131072 | 7U,       /**< EMC reset control */
+    kETH_RST_SHIFT_RSTn = 131072 | 8U,       /**< ETH reset control */
+    kGPIO4_RST_SHIFT_RSTn = 131072 | 9U,     /**< GPIO4 reset control */
+    kGPIO5_RST_SHIFT_RSTn = 131072 | 10U,    /**< GPIO5 reset control */
+    kAES_RST_SHIFT_RSTn = 131072 | 11U,      /**< AES reset control */
+    kOTP_RST_SHIFT_RSTn = 131072 | 12U,      /**< OTP reset control */
+    kRNG_RST_SHIFT_RSTn = 131072 | 13U,      /**< RNG  reset control */
+    kFC8_RST_SHIFT_RSTn = 131072 | 14U,      /**< Flexcomm Interface 8 reset control */
+    kFC9_RST_SHIFT_RSTn = 131072 | 15U,      /**< Flexcomm Interface 9 reset control */
+    kUSB0HMR_RST_SHIFT_RSTn = 131072 | 16U,  /**< USB0HMR reset control */
+    kUSB0HSL_RST_SHIFT_RSTn = 131072 | 17U,  /**< USB0HSL reset control */
+    kSHA_RST_SHIFT_RSTn = 131072 | 18U,      /**< SHA reset control */
+    kSC0_RST_SHIFT_RSTn = 131072 | 19U,      /**< SC0 reset control */
+    kSC1_RST_SHIFT_RSTn = 131072 | 20U,      /**< SC1 reset control */
+    kFC10_RST_SHIFT_RSTn = 131072 | 21U,     /**< Flexcomm Interface 10 reset control */
+
+    kCT32B3_RST_SHIFT_RSTn = 67108864 | 13U, /**< CT32B3 reset control */
+    kCT32B4_RST_SHIFT_RSTn = 67108864 | 14U, /**< CT32B4 reset control */
+} SYSCON_RSTn_t;
+
+/** Array initializers with peripheral reset bits **/
+#define ADC_RSTS             \
+    {                        \
+        kADC0_RST_SHIFT_RSTn \
+    } /* Reset bits for ADC peripheral */
+#define AES_RSTS             \
+    {                        \
+        kAES_RST_SHIFT_RSTn  \
+    } /* Reset bits for AES peripheral */
+#define CRC_RSTS            \
+    {                       \
+        kCRC_RST_SHIFT_RSTn \
+    } /* Reset bits for CRC peripheral */
+#define CTIMER_RSTS                                                                                     \
+    {                                                                                                   \
+        kCT32B0_RST_SHIFT_RSTn, kCT32B1_RST_SHIFT_RSTn, kCT32B2_RST_SHIFT_RSTn, kCT32B3_RST_SHIFT_RSTn, \
+            kCT32B4_RST_SHIFT_RSTn                                                                      \
+    } /* Reset bits for CTIMER peripheral */
+#define DMA_RSTS_N            \
+    {                       \
+        kDMA_RST_SHIFT_RSTn \
+    } /* Reset bits for DMA peripheral */
+#define DMIC_RSTS            \
+    {                        \
+        kDMIC_RST_SHIFT_RSTn \
+    } /* Reset bits for DMIC peripheral */
+#define EMC_RSTS             \
+    {                        \
+        kEMC_RST_SHIFT_RSTn  \
+    } /* Reset bits for EMC peripheral */
+#define ETH_RST              \
+    {                        \
+        kETH_RST_SHIFT_RSTn  \
+    } /* Reset bits for EMC peripheral */
+#define FLEXCOMM_RSTS                                                                                            \
+    {                                                                                                            \
+        kFC0_RST_SHIFT_RSTn, kFC1_RST_SHIFT_RSTn, kFC2_RST_SHIFT_RSTn, kFC3_RST_SHIFT_RSTn, kFC4_RST_SHIFT_RSTn, \
+            kFC5_RST_SHIFT_RSTn, kFC6_RST_SHIFT_RSTn, kFC7_RST_SHIFT_RSTn, kFC8_RST_SHIFT_RSTn, kFC9_RST_SHIFT_RSTn, kFC9_RST_SHIFT_RSTn   \
+    } /* Reset bits for FLEXCOMM peripheral */
+#define GINT_RSTS                                  \
+    {                                              \
+        kGINT_RST_SHIFT_RSTn, kGINT_RST_SHIFT_RSTn \
+    } /* Reset bits for GINT peripheral. GINT0 & GINT1 share same slot */
+#define GPIO_RSTS_N                                    \
+    {                                                \
+        kGPIO0_RST_SHIFT_RSTn, kGPIO1_RST_SHIFT_RSTn, kGPIO2_RST_SHIFT_RSTn, kGPIO3_RST_SHIFT_RSTn,  \
+        kGPIO4_RST_SHIFT_RSTn, kGPIO5_RST_SHIFT_RSTn                                                 \
+    } /* Reset bits for GPIO peripheral */
+#define INPUTMUX_RSTS       \
+    {                       \
+        kMUX_RST_SHIFT_RSTn \
+    } /* Reset bits for INPUTMUX peripheral */
+#define IOCON_RSTS            \
+    {                         \
+        kIOCON_RST_SHIFT_RSTn \
+    } /* Reset bits for IOCON peripheral */
+#define FLASH_RSTS                                 \
+    {                                              \
+        kFLASH_RST_SHIFT_RSTn, kFMC_RST_SHIFT_RSTn \
+    } /* Reset bits for Flash peripheral */
+#define LCD_RSTS                                 \
+    {                                            \
+        kLCD_RST_SHIFT_RSTn                      \
+    } /* Reset bits for LCD peripheral */
+#define MRT_RSTS            \
+    {                       \
+        kMRT_RST_SHIFT_RSTn \
+    } /* Reset bits for MRT peripheral */
+#define MCAN_RSTS                                   \
+    {                                               \
+        kMCAN0_RST_SHIFT_RSTn,kMCAN1_RST_SHIFT_RSTn \
+    } /* Reset bits for MCAN0&MACN1 peripheral */
+#define OTP_RSTS            \
+    {                       \
+        kOTP_RST_SHIFT_RSTn \
+    } /* Reset bits for OTP peripheral */
+#define PINT_RSTS            \
+    {                        \
+        kPINT_RST_SHIFT_RSTn \
+    } /* Reset bits for PINT peripheral */
+#define RNG_RSTS             \
+    {                        \
+        kRNG_RST_SHIFT_RSTn  \
+    } /* Reset bits for RNG peripheral */
+#define SDIO_RST             \
+    {                        \
+        kSDIO_RST_SHIFT_RSTn \
+    } /* Reset bits for SDIO peripheral */
+#define SCT_RSTS             \
+    {                        \
+        kSCT0_RST_SHIFT_RSTn \
+    } /* Reset bits for SCT peripheral */
+#define SHA_RST              \
+    {                        \
+        kSHA_RST_SHIFT_RSTn  \
+    } /* Reset bits for SHA peripheral */
+#define SPIFI_RSTS            \
+    {                         \
+        kSPIFI_RST_SHIFT_RSTn \
+    } /* Reset bits for SPIFI peripheral */
+#define USB0D_RST             \
+    {                         \
+        kUSB0D_RST_SHIFT_RSTn \
+    } /* Reset bits for USB0D peripheral */
+#define USB0HMR_RST             \
+    {                           \
+        kUSB0HMR_RST_SHIFT_RSTn \
+    } /* Reset bits for USB0HMR peripheral */
+#define USB0HSL_RST             \
+    {                           \
+        kUSB0HSL_RST_SHIFT_RSTn \
+    } /* Reset bits for USB0HSL peripheral */
+#define USB1H_RST             \
+    {                         \
+        kUSB1H_RST_SHIFT_RSTn \
+    } /* Reset bits for USB1H peripheral */
+#define USB1D_RST             \
+    {                         \
+        kUSB1D_RST_SHIFT_RSTn \
+    } /* Reset bits for USB1D peripheral */
+#define USB1RAM_RST             \
+    {                           \
+        kUSB1RAM_RST_SHIFT_RSTn \
+    } /* Reset bits for USB1RAM peripheral */
+#define UTICK_RSTS            \
+    {                         \
+        kUTICK_RST_SHIFT_RSTn \
+    } /* Reset bits for UTICK peripheral */
+#define WWDT_RSTS            \
+    {                        \
+        kWWDT_RST_SHIFT_RSTn \
+    } /* Reset bits for WWDT peripheral */
+
+typedef SYSCON_RSTn_t reset_ip_name_t;
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Assert reset to peripheral.
+ *
+ * Asserts reset signal to specified peripheral module.
+ *
+ * @param peripheral Assert reset to this peripheral. The enum argument contains encoding of reset register
+ *                   and reset bit position in the reset register.
+ */
+void RESET_SetPeripheralReset(reset_ip_name_t peripheral);
+
+/*!
+ * @brief Clear reset to peripheral.
+ *
+ * Clears reset signal to specified peripheral module, allows it to operate.
+ *
+ * @param peripheral Clear reset to this peripheral. The enum argument contains encoding of reset register
+ *                   and reset bit position in the reset register.
+ */
+void RESET_ClearPeripheralReset(reset_ip_name_t peripheral);
+
+/*!
+ * @brief Reset peripheral module.
+ *
+ * Reset peripheral module.
+ *
+ * @param peripheral Peripheral to reset. The enum argument contains encoding of reset register
+ *                   and reset bit position in the reset register.
+ */
+void RESET_PeripheralReset(reset_ip_name_t peripheral);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @} */
+
+#endif /* _FSL_RESET_H_ */

FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/drivers/fsl_usart.c

@@ -0,0 +1,981 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2019 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_usart.h"
+#include "fsl_device_registers.h"
+#include "fsl_flexcomm.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/* Component ID definition, used by tools. */
+#ifndef FSL_COMPONENT_ID
+#define FSL_COMPONENT_ID "platform.drivers.flexcomm_usart"
+#endif
+
+/*!
+ * @brief Used for conversion from `flexcomm_usart_irq_handler_t` to `flexcomm_irq_handler_t`
+ */
+typedef union usart_to_flexcomm
+{
+    flexcomm_usart_irq_handler_t usart_master_handler;
+    flexcomm_irq_handler_t flexcomm_handler;
+} usart_to_flexcomm_t;
+
+enum
+{
+    kUSART_TxIdle, /* TX idle. */
+    kUSART_TxBusy, /* TX busy. */
+    kUSART_RxIdle, /* RX idle. */
+    kUSART_RxBusy  /* RX busy. */
+};
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+
+/*! @brief IRQ name array */
+static const IRQn_Type s_usartIRQ[] = USART_IRQS;
+
+/*! @brief Array to map USART instance number to base address. */
+static const uint32_t s_usartBaseAddrs[FSL_FEATURE_SOC_USART_COUNT] = USART_BASE_ADDRS;
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/* Get the index corresponding to the USART */
+/*! brief Returns instance number for USART peripheral base address. */
+uint32_t USART_GetInstance(USART_Type *base)
+{
+    uint32_t i;
+
+    for (i = 0; i < (uint32_t)FSL_FEATURE_SOC_USART_COUNT; i++)
+    {
+        if ((uint32_t)base == s_usartBaseAddrs[i])
+        {
+            break;
+        }
+    }
+
+    assert(i < FSL_FEATURE_SOC_USART_COUNT);
+    return i;
+}
+
+/*!
+ * brief Get the length of received data in RX ring buffer.
+ *
+ * param handle USART handle pointer.
+ * return Length of received data in RX ring buffer.
+ */
+size_t USART_TransferGetRxRingBufferLength(usart_handle_t *handle)
+{
+    size_t size;
+
+    /* Check arguments */
+    assert(NULL != handle);
+    uint16_t rxRingBufferHead = handle->rxRingBufferHead;
+    uint16_t rxRingBufferTail = handle->rxRingBufferTail;
+
+    if (rxRingBufferTail > rxRingBufferHead)
+    {
+        size = (size_t)rxRingBufferHead + handle->rxRingBufferSize - (size_t)rxRingBufferTail;
+    }
+    else
+    {
+        size = (size_t)rxRingBufferHead - (size_t)rxRingBufferTail;
+    }
+    return size;
+}
+
+static bool USART_TransferIsRxRingBufferFull(usart_handle_t *handle)
+{
+    bool full;
+
+    /* Check arguments */
+    assert(NULL != handle);
+
+    if (USART_TransferGetRxRingBufferLength(handle) == (handle->rxRingBufferSize - 1U))
+    {
+        full = true;
+    }
+    else
+    {
+        full = false;
+    }
+    return full;
+}
+
+/*!
+ * brief Sets up the RX ring buffer.
+ *
+ * This function sets up the RX ring buffer to a specific USART handle.
+ *
+ * When the RX ring buffer is used, data received are stored into the ring buffer even when the
+ * user doesn't call the USART_TransferReceiveNonBlocking() API. If there is already data received
+ * in the ring buffer, the user can get the received data from the ring buffer directly.
+ *
+ * note When using the RX ring buffer, one byte is reserved for internal use. In other
+ * words, if p ringBufferSize is 32, then only 31 bytes are used for saving data.
+ *
+ * param base USART peripheral base address.
+ * param handle USART handle pointer.
+ * param ringBuffer Start address of the ring buffer for background receiving. Pass NULL to disable the ring buffer.
+ * param ringBufferSize size of the ring buffer.
+ */
+void USART_TransferStartRingBuffer(USART_Type *base, usart_handle_t *handle, uint8_t *ringBuffer, size_t ringBufferSize)
+{
+    /* Check arguments */
+    assert(NULL != base);
+    assert(NULL != handle);
+    assert(NULL != ringBuffer);
+
+    /* Setup the ringbuffer address */
+    handle->rxRingBuffer     = ringBuffer;
+    handle->rxRingBufferSize = ringBufferSize;
+    handle->rxRingBufferHead = 0U;
+    handle->rxRingBufferTail = 0U;
+    /* ring buffer is ready we can start receiving data */
+    base->FIFOINTENSET |= USART_FIFOINTENSET_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK;
+}
+
+/*!
+ * brief Aborts the background transfer and uninstalls the ring buffer.
+ *
+ * This function aborts the background transfer and uninstalls the ring buffer.
+ *
+ * param base USART peripheral base address.
+ * param handle USART handle pointer.
+ */
+void USART_TransferStopRingBuffer(USART_Type *base, usart_handle_t *handle)
+{
+    /* Check arguments */
+    assert(NULL != base);
+    assert(NULL != handle);
+
+    if (handle->rxState == (uint8_t)kUSART_RxIdle)
+    {
+        base->FIFOINTENCLR = USART_FIFOINTENCLR_RXLVL_MASK | USART_FIFOINTENCLR_RXERR_MASK;
+    }
+    handle->rxRingBuffer     = NULL;
+    handle->rxRingBufferSize = 0U;
+    handle->rxRingBufferHead = 0U;
+    handle->rxRingBufferTail = 0U;
+}
+
+/*!
+ * brief Initializes a USART instance with user configuration structure and peripheral clock.
+ *
+ * This function configures the USART module with the user-defined settings. The user can configure the configuration
+ * structure and also get the default configuration by using the USART_GetDefaultConfig() function.
+ * Example below shows how to use this API to configure USART.
+ * code
+ *  usart_config_t usartConfig;
+ *  usartConfig.baudRate_Bps = 115200U;
+ *  usartConfig.parityMode = kUSART_ParityDisabled;
+ *  usartConfig.stopBitCount = kUSART_OneStopBit;
+ *  USART_Init(USART1, &usartConfig, 20000000U);
+ * endcode
+ *
+ * param base USART peripheral base address.
+ * param config Pointer to user-defined configuration structure.
+ * param srcClock_Hz USART clock source frequency in HZ.
+ * retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source.
+ * retval kStatus_InvalidArgument USART base address is not valid
+ * retval kStatus_Success Status USART initialize succeed
+ */
+status_t USART_Init(USART_Type *base, const usart_config_t *config, uint32_t srcClock_Hz)
+{
+    int result;
+
+    /* check arguments */
+    assert(!((NULL == base) || (NULL == config) || (0U == srcClock_Hz)));
+    if ((NULL == base) || (NULL == config) || (0U == srcClock_Hz))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* initialize flexcomm to USART mode */
+    result = FLEXCOMM_Init(base, FLEXCOMM_PERIPH_USART);
+    if (kStatus_Success != result)
+    {
+        return result;
+    }
+
+    if (config->enableTx)
+    {
+        /* empty and enable txFIFO */
+        base->FIFOCFG |= USART_FIFOCFG_EMPTYTX_MASK | USART_FIFOCFG_ENABLETX_MASK;
+        /* setup trigger level */
+        base->FIFOTRIG &= ~(USART_FIFOTRIG_TXLVL_MASK);
+        base->FIFOTRIG |= USART_FIFOTRIG_TXLVL(config->txWatermark);
+        /* enable trigger interrupt */
+        base->FIFOTRIG |= USART_FIFOTRIG_TXLVLENA_MASK;
+    }
+
+    /* empty and enable rxFIFO */
+    if (config->enableRx)
+    {
+        base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK | USART_FIFOCFG_ENABLERX_MASK;
+        /* setup trigger level */
+        base->FIFOTRIG &= ~(USART_FIFOTRIG_RXLVL_MASK);
+        base->FIFOTRIG |= USART_FIFOTRIG_RXLVL(config->rxWatermark);
+        /* enable trigger interrupt */
+        base->FIFOTRIG |= USART_FIFOTRIG_RXLVLENA_MASK;
+    }
+    /* setup configuration and enable USART */
+    base->CFG = USART_CFG_PARITYSEL(config->parityMode) | USART_CFG_STOPLEN(config->stopBitCount) |
+                USART_CFG_DATALEN(config->bitCountPerChar) | USART_CFG_LOOP(config->loopback) |
+                USART_CFG_SYNCEN((uint32_t)config->syncMode >> 1) | USART_CFG_SYNCMST((uint8_t)config->syncMode) |
+                USART_CFG_CLKPOL(config->clockPolarity) | USART_CFG_ENABLE_MASK;
+
+    /* Setup baudrate */
+    result = USART_SetBaudRate(base, config->baudRate_Bps, srcClock_Hz);
+    if (kStatus_Success != result)
+    {
+        return result;
+    }
+    /* Setting continuous Clock configuration. used for synchronous mode. */
+    USART_EnableContinuousSCLK(base, config->enableContinuousSCLK);
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Deinitializes a USART instance.
+ *
+ * This function waits for TX complete, disables TX and RX, and disables the USART clock.
+ *
+ * param base USART peripheral base address.
+ */
+void USART_Deinit(USART_Type *base)
+{
+    /* Check arguments */
+    assert(NULL != base);
+    while (0U == (base->STAT & USART_STAT_TXIDLE_MASK))
+    {
+    }
+    /* Disable interrupts, disable dma requests, disable peripheral */
+    base->FIFOINTENCLR = USART_FIFOINTENCLR_TXERR_MASK | USART_FIFOINTENCLR_RXERR_MASK | USART_FIFOINTENCLR_TXLVL_MASK |
+                         USART_FIFOINTENCLR_RXLVL_MASK;
+    base->FIFOCFG &= ~(USART_FIFOCFG_DMATX_MASK | USART_FIFOCFG_DMARX_MASK);
+    base->CFG &= ~(USART_CFG_ENABLE_MASK);
+}
+
+/*!
+ * brief Gets the default configuration structure.
+ *
+ * This function initializes the USART configuration structure to a default value. The default
+ * values are:
+ *   usartConfig->baudRate_Bps = 115200U;
+ *   usartConfig->parityMode = kUSART_ParityDisabled;
+ *   usartConfig->stopBitCount = kUSART_OneStopBit;
+ *   usartConfig->bitCountPerChar = kUSART_8BitsPerChar;
+ *   usartConfig->loopback = false;
+ *   usartConfig->enableTx = false;
+ *   usartConfig->enableRx = false;
+ *
+ * param config Pointer to configuration structure.
+ */
+void USART_GetDefaultConfig(usart_config_t *config)
+{
+    /* Check arguments */
+    assert(NULL != config);
+
+    /* Initializes the configure structure to zero. */
+    (void)memset(config, 0, sizeof(*config));
+
+    /* Set always all members ! */
+    config->baudRate_Bps         = 115200U;
+    config->parityMode           = kUSART_ParityDisabled;
+    config->stopBitCount         = kUSART_OneStopBit;
+    config->bitCountPerChar      = kUSART_8BitsPerChar;
+    config->loopback             = false;
+    config->enableRx             = false;
+    config->enableTx             = false;
+    config->txWatermark          = kUSART_TxFifo0;
+    config->rxWatermark          = kUSART_RxFifo1;
+    config->syncMode             = kUSART_SyncModeDisabled;
+    config->enableContinuousSCLK = false;
+    config->clockPolarity        = kUSART_RxSampleOnFallingEdge;
+}
+
+/*!
+ * brief Sets the USART instance baud rate.
+ *
+ * This function configures the USART module baud rate. This function is used to update
+ * the USART module baud rate after the USART module is initialized by the USART_Init.
+ * code
+ *  USART_SetBaudRate(USART1, 115200U, 20000000U);
+ * endcode
+ *
+ * param base USART peripheral base address.
+ * param baudrate_Bps USART baudrate to be set.
+ * param srcClock_Hz USART clock source frequency in HZ.
+ * retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source.
+ * retval kStatus_Success Set baudrate succeed.
+ * retval kStatus_InvalidArgument One or more arguments are invalid.
+ */
+status_t USART_SetBaudRate(USART_Type *base, uint32_t baudrate_Bps, uint32_t srcClock_Hz)
+{
+    uint32_t best_diff = (uint32_t)-1, best_osrval = 0xf, best_brgval = (uint32_t)-1;
+    uint32_t osrval, brgval, diff, baudrate;
+
+    /* check arguments */
+    assert(!((NULL == base) || (0 == baudrate_Bps) || (0 == srcClock_Hz)));
+    if ((NULL == base) || (0U == baudrate_Bps) || (0U == srcClock_Hz))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* If synchronous master mode is enabled, only configure the BRG value. */
+    if ((base->CFG & USART_CFG_SYNCEN_MASK) != 0U)
+    {
+        if ((base->CFG & USART_CFG_SYNCMST_MASK) != 0U)
+        {
+            brgval    = srcClock_Hz / baudrate_Bps;
+            base->BRG = brgval - 1U;
+        }
+    }
+    else
+    {
+        /*
+         * Smaller values of OSR can make the sampling position within a data bit less accurate and may
+         * potentially cause more noise errors or incorrect data.
+         */
+        for (osrval = best_osrval; osrval >= 8U; osrval--)
+        {
+            brgval = (((srcClock_Hz * 10U) / ((osrval + 1U) * baudrate_Bps)) - 5U) / 10U;
+            if (brgval > 0xFFFFU)
+            {
+                continue;
+            }
+            baudrate = srcClock_Hz / ((osrval + 1U) * (brgval + 1U));
+            diff     = baudrate_Bps < baudrate ? baudrate - baudrate_Bps : baudrate_Bps - baudrate;
+            if (diff < best_diff)
+            {
+                best_diff   = diff;
+                best_osrval = osrval;
+                best_brgval = brgval;
+            }
+        }
+
+        /* value over range */
+        if (best_brgval > 0xFFFFU)
+        {
+            return kStatus_USART_BaudrateNotSupport;
+        }
+
+        base->OSR = best_osrval;
+        base->BRG = best_brgval;
+    }
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Writes to the TX register using a blocking method.
+ *
+ * This function polls the TX register, waits for the TX register to be empty or for the TX FIFO
+ * to have room and writes data to the TX buffer.
+ *
+ * param base USART peripheral base address.
+ * param data Start address of the data to write.
+ * param length Size of the data to write.
+ */
+void USART_WriteBlocking(USART_Type *base, const uint8_t *data, size_t length)
+{
+    /* Check arguments */
+    assert(!((NULL == base) || (NULL == data)));
+    if ((NULL == base) || (NULL == data))
+    {
+        return;
+    }
+    /* Check whether txFIFO is enabled */
+    if (0U == (base->FIFOCFG & USART_FIFOCFG_ENABLETX_MASK))
+    {
+        return;
+    }
+    for (; length > 0U; length--)
+    {
+        /* Loop until txFIFO get some space for new data */
+        while (0U == (base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK))
+        {
+        }
+        base->FIFOWR = *data;
+        data++;
+    }
+    /* Wait to finish transfer */
+    while (0U == (base->STAT & USART_STAT_TXIDLE_MASK))
+    {
+    }
+}
+
+/*!
+ * brief Read RX data register using a blocking method.
+ *
+ * This function polls the RX register, waits for the RX register to be full or for RX FIFO to
+ * have data and read data from the TX register.
+ *
+ * param base USART peripheral base address.
+ * param data Start address of the buffer to store the received data.
+ * param length Size of the buffer.
+ * retval kStatus_USART_FramingError Receiver overrun happened while receiving data.
+ * retval kStatus_USART_ParityError Noise error happened while receiving data.
+ * retval kStatus_USART_NoiseError Framing error happened while receiving data.
+ * retval kStatus_USART_RxError Overflow or underflow rxFIFO happened.
+ * retval kStatus_Success Successfully received all data.
+ */
+status_t USART_ReadBlocking(USART_Type *base, uint8_t *data, size_t length)
+{
+    uint32_t statusFlag;
+    status_t status = kStatus_Success;
+
+    /* check arguments */
+    assert(!((NULL == base) || (NULL == data)));
+    if ((NULL == base) || (NULL == data))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* Check whether rxFIFO is enabled */
+    if ((base->FIFOCFG & USART_FIFOCFG_ENABLERX_MASK) == 0U)
+    {
+        return kStatus_Fail;
+    }
+    for (; length > 0U; length--)
+    {
+        /* loop until rxFIFO have some data to read */
+        while ((base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK) == 0U)
+        {
+        }
+        /* check rxFIFO statusFlag */
+        if ((base->FIFOSTAT & USART_FIFOSTAT_RXERR_MASK) != 0U)
+        {
+            base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK;
+            base->FIFOSTAT |= USART_FIFOSTAT_RXERR_MASK;
+            status = kStatus_USART_RxError;
+            break;
+        }
+        /* check receive statusFlag */
+        statusFlag = base->STAT;
+        /* Clear all status flags */
+        base->STAT |= statusFlag;
+        if ((statusFlag & USART_STAT_PARITYERRINT_MASK) != 0U)
+        {
+            status = kStatus_USART_ParityError;
+        }
+        if ((statusFlag & USART_STAT_FRAMERRINT_MASK) != 0U)
+        {
+            status = kStatus_USART_FramingError;
+        }
+        if ((statusFlag & USART_STAT_RXNOISEINT_MASK) != 0U)
+        {
+            status = kStatus_USART_NoiseError;
+        }
+
+        if (kStatus_Success == status)
+        {
+            *data = (uint8_t)base->FIFORD;
+            data++;
+        }
+        else
+        {
+            break;
+        }
+    }
+    return status;
+}
+
+/*!
+ * brief Initializes the USART handle.
+ *
+ * This function initializes the USART handle which can be used for other USART
+ * transactional APIs. Usually, for a specified USART instance,
+ * call this API once to get the initialized handle.
+ *
+ * param base USART peripheral base address.
+ * param handle USART handle pointer.
+ * param callback The callback function.
+ * param userData The parameter of the callback function.
+ */
+status_t USART_TransferCreateHandle(USART_Type *base,
+                                    usart_handle_t *handle,
+                                    usart_transfer_callback_t callback,
+                                    void *userData)
+{
+    /* Check 'base' */
+    assert(!((NULL == base) || (NULL == handle)));
+
+    uint32_t instance = 0;
+    usart_to_flexcomm_t handler;
+    handler.usart_master_handler = USART_TransferHandleIRQ;
+
+    if ((NULL == base) || (NULL == handle))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    instance = USART_GetInstance(base);
+
+    (void)memset(handle, 0, sizeof(*handle));
+    /* Set the TX/RX state. */
+    handle->rxState = (uint8_t)kUSART_RxIdle;
+    handle->txState = (uint8_t)kUSART_TxIdle;
+    /* Set the callback and user data. */
+    handle->callback    = callback;
+    handle->userData    = userData;
+    handle->rxWatermark = (uint8_t)USART_FIFOTRIG_RXLVL_GET(base);
+    handle->txWatermark = (uint8_t)USART_FIFOTRIG_TXLVL_GET(base);
+
+    FLEXCOMM_SetIRQHandler(base, handler.flexcomm_handler, handle);
+
+    /* Enable interrupt in NVIC. */
+    (void)EnableIRQ(s_usartIRQ[instance]);
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Transmits a buffer of data using the interrupt method.
+ *
+ * This function sends data using an interrupt method. This is a non-blocking function, which
+ * returns directly without waiting for all data to be written to the TX register. When
+ * all data is written to the TX register in the IRQ handler, the USART driver calls the callback
+ * function and passes the ref kStatus_USART_TxIdle as status parameter.
+ *
+ * note The kStatus_USART_TxIdle is passed to the upper layer when all data is written
+ * to the TX register. However it does not ensure that all data are sent out. Before disabling the TX,
+ * check the kUSART_TransmissionCompleteFlag to ensure that the TX is finished.
+ *
+ * param base USART peripheral base address.
+ * param handle USART handle pointer.
+ * param xfer USART transfer structure. See  #usart_transfer_t.
+ * retval kStatus_Success Successfully start the data transmission.
+ * retval kStatus_USART_TxBusy Previous transmission still not finished, data not all written to TX register yet.
+ * retval kStatus_InvalidArgument Invalid argument.
+ */
+status_t USART_TransferSendNonBlocking(USART_Type *base, usart_handle_t *handle, usart_transfer_t *xfer)
+{
+    /* Check arguments */
+    assert(!((NULL == base) || (NULL == handle) || (NULL == xfer)));
+    if ((NULL == base) || (NULL == handle) || (NULL == xfer))
+    {
+        return kStatus_InvalidArgument;
+    }
+    /* Check xfer members */
+    assert(!((0 == xfer->dataSize) || (NULL == xfer->data)));
+    if ((0U == xfer->dataSize) || (NULL == xfer->data))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* Return error if current TX busy. */
+    if ((uint8_t)kUSART_TxBusy == handle->txState)
+    {
+        return kStatus_USART_TxBusy;
+    }
+    else
+    {
+        handle->txData        = xfer->data;
+        handle->txDataSize    = xfer->dataSize;
+        handle->txDataSizeAll = xfer->dataSize;
+        handle->txState       = (uint8_t)kUSART_TxBusy;
+        /* Enable transmiter interrupt. */
+        base->FIFOINTENSET |= USART_FIFOINTENSET_TXLVL_MASK;
+    }
+    return kStatus_Success;
+}
+
+/*!
+ * brief Aborts the interrupt-driven data transmit.
+ *
+ * This function aborts the interrupt driven data sending. The user can get the remainBtyes to find out
+ * how many bytes are still not sent out.
+ *
+ * param base USART peripheral base address.
+ * param handle USART handle pointer.
+ */
+void USART_TransferAbortSend(USART_Type *base, usart_handle_t *handle)
+{
+    assert(NULL != handle);
+
+    /* Disable interrupts */
+    USART_DisableInterrupts(base, (uint32_t)kUSART_TxLevelInterruptEnable);
+    /* Empty txFIFO */
+    base->FIFOCFG |= USART_FIFOCFG_EMPTYTX_MASK;
+
+    handle->txDataSize = 0U;
+    handle->txState    = (uint8_t)kUSART_TxIdle;
+}
+
+/*!
+ * brief Get the number of bytes that have been written to USART TX register.
+ *
+ * This function gets the number of bytes that have been written to USART TX
+ * register by interrupt method.
+ *
+ * param base USART peripheral base address.
+ * param handle USART handle pointer.
+ * param count Send bytes count.
+ * retval kStatus_NoTransferInProgress No send in progress.
+ * retval kStatus_InvalidArgument Parameter is invalid.
+ * retval kStatus_Success Get successfully through the parameter \p count;
+ */
+status_t USART_TransferGetSendCount(USART_Type *base, usart_handle_t *handle, uint32_t *count)
+{
+    assert(NULL != handle);
+    assert(NULL != count);
+
+    if ((uint8_t)kUSART_TxIdle == handle->txState)
+    {
+        return kStatus_NoTransferInProgress;
+    }
+
+    *count = handle->txDataSizeAll - handle->txDataSize;
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief Receives a buffer of data using an interrupt method.
+ *
+ * This function receives data using an interrupt method. This is a non-blocking function, which
+ *  returns without waiting for all data to be received.
+ * If the RX ring buffer is used and not empty, the data in the ring buffer is copied and
+ * the parameter p receivedBytes shows how many bytes are copied from the ring buffer.
+ * After copying, if the data in the ring buffer is not enough to read, the receive
+ * request is saved by the USART driver. When the new data arrives, the receive request
+ * is serviced first. When all data is received, the USART driver notifies the upper layer
+ * through a callback function and passes the status parameter ref kStatus_USART_RxIdle.
+ * For example, the upper layer needs 10 bytes but there are only 5 bytes in the ring buffer.
+ * The 5 bytes are copied to the xfer->data and this function returns with the
+ * parameter p receivedBytes set to 5. For the left 5 bytes, newly arrived data is
+ * saved from the xfer->data[5]. When 5 bytes are received, the USART driver notifies the upper layer.
+ * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt
+ * to receive data to the xfer->data. When all data is received, the upper layer is notified.
+ *
+ * param base USART peripheral base address.
+ * param handle USART handle pointer.
+ * param xfer USART transfer structure, see #usart_transfer_t.
+ * param receivedBytes Bytes received from the ring buffer directly.
+ * retval kStatus_Success Successfully queue the transfer into transmit queue.
+ * retval kStatus_USART_RxBusy Previous receive request is not finished.
+ * retval kStatus_InvalidArgument Invalid argument.
+ */
+status_t USART_TransferReceiveNonBlocking(USART_Type *base,
+                                          usart_handle_t *handle,
+                                          usart_transfer_t *xfer,
+                                          size_t *receivedBytes)
+{
+    uint32_t i;
+    /* How many bytes to copy from ring buffer to user memory. */
+    size_t bytesToCopy = 0U;
+    /* How many bytes to receive. */
+    size_t bytesToReceive;
+    /* How many bytes currently have received. */
+    size_t bytesCurrentReceived;
+    uint32_t regPrimask = 0U;
+
+    /* Check arguments */
+    assert(!((NULL == base) || (NULL == handle) || (NULL == xfer)));
+    if ((NULL == base) || (NULL == handle) || (NULL == xfer))
+    {
+        return kStatus_InvalidArgument;
+    }
+    /* Check xfer members */
+    assert(!((0 == xfer->dataSize) || (NULL == xfer->data)));
+    if ((0U == xfer->dataSize) || (NULL == xfer->data))
+    {
+        return kStatus_InvalidArgument;
+    }
+
+    /* How to get data:
+       1. If RX ring buffer is not enabled, then save xfer->data and xfer->dataSize
+          to uart handle, enable interrupt to store received data to xfer->data. When
+          all data received, trigger callback.
+       2. If RX ring buffer is enabled and not empty, get data from ring buffer first.
+          If there are enough data in ring buffer, copy them to xfer->data and return.
+          If there are not enough data in ring buffer, copy all of them to xfer->data,
+          save the xfer->data remained empty space to uart handle, receive data
+          to this empty space and trigger callback when finished. */
+    if ((uint8_t)kUSART_RxBusy == handle->rxState)
+    {
+        return kStatus_USART_RxBusy;
+    }
+    else
+    {
+        bytesToReceive       = xfer->dataSize;
+        bytesCurrentReceived = 0U;
+        /* If RX ring buffer is used. */
+        if (handle->rxRingBuffer != NULL)
+        {
+            /* Disable IRQ, protect ring buffer. */
+            regPrimask = DisableGlobalIRQ();
+            /* How many bytes in RX ring buffer currently. */
+            bytesToCopy = USART_TransferGetRxRingBufferLength(handle);
+            if (bytesToCopy != 0U)
+            {
+                bytesToCopy = MIN(bytesToReceive, bytesToCopy);
+                bytesToReceive -= bytesToCopy;
+                /* Copy data from ring buffer to user memory. */
+                for (i = 0U; i < bytesToCopy; i++)
+                {
+                    xfer->data[bytesCurrentReceived++] = handle->rxRingBuffer[handle->rxRingBufferTail];
+                    /* Wrap to 0. Not use modulo (%) because it might be large and slow. */
+                    if ((size_t)handle->rxRingBufferTail + 1U == handle->rxRingBufferSize)
+                    {
+                        handle->rxRingBufferTail = 0U;
+                    }
+                    else
+                    {
+                        handle->rxRingBufferTail++;
+                    }
+                }
+            }
+            /* If ring buffer does not have enough data, still need to read more data. */
+            if (bytesToReceive != 0U)
+            {
+                /* No data in ring buffer, save the request to UART handle. */
+                handle->rxData        = xfer->data + bytesCurrentReceived;
+                handle->rxDataSize    = bytesToReceive;
+                handle->rxDataSizeAll = bytesToReceive;
+                handle->rxState       = (uint8_t)kUSART_RxBusy;
+            }
+            /* Enable IRQ if previously enabled. */
+            EnableGlobalIRQ(regPrimask);
+            /* Call user callback since all data are received. */
+            if (0U == bytesToReceive)
+            {
+                if (handle->callback != NULL)
+                {
+                    handle->callback(base, handle, kStatus_USART_RxIdle, handle->userData);
+                }
+            }
+        }
+        /* Ring buffer not used. */
+        else
+        {
+            handle->rxData        = xfer->data + bytesCurrentReceived;
+            handle->rxDataSize    = bytesToReceive;
+            handle->rxDataSizeAll = bytesToReceive;
+            handle->rxState       = (uint8_t)kUSART_RxBusy;
+
+            /* Enable RX interrupt. */
+            base->FIFOINTENSET |= USART_FIFOINTENSET_RXLVL_MASK;
+        }
+        /* Return the how many bytes have read. */
+        if (receivedBytes != NULL)
+        {
+            *receivedBytes = bytesCurrentReceived;
+        }
+    }
+    return kStatus_Success;
+}
+
+/*!
+ * brief Aborts the interrupt-driven data receiving.
+ *
+ * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to find out
+ * how many bytes not received yet.
+ *
+ * param base USART peripheral base address.
+ * param handle USART handle pointer.
+ */
+void USART_TransferAbortReceive(USART_Type *base, usart_handle_t *handle)
+{
+    assert(NULL != handle);
+
+    /* Only abort the receive to handle->rxData, the RX ring buffer is still working. */
+    if (NULL == handle->rxRingBuffer)
+    {
+        /* Disable interrupts */
+        USART_DisableInterrupts(base, (uint32_t)kUSART_RxLevelInterruptEnable);
+        /* Empty rxFIFO */
+        base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK;
+    }
+
+    handle->rxDataSize = 0U;
+    handle->rxState    = (uint8_t)kUSART_RxIdle;
+}
+
+/*!
+ * brief Get the number of bytes that have been received.
+ *
+ * This function gets the number of bytes that have been received.
+ *
+ * param base USART peripheral base address.
+ * param handle USART handle pointer.
+ * param count Receive bytes count.
+ * retval kStatus_NoTransferInProgress No receive in progress.
+ * retval kStatus_InvalidArgument Parameter is invalid.
+ * retval kStatus_Success Get successfully through the parameter \p count;
+ */
+status_t USART_TransferGetReceiveCount(USART_Type *base, usart_handle_t *handle, uint32_t *count)
+{
+    assert(NULL != handle);
+    assert(NULL != count);
+
+    if ((uint8_t)kUSART_RxIdle == handle->rxState)
+    {
+        return kStatus_NoTransferInProgress;
+    }
+
+    *count = handle->rxDataSizeAll - handle->rxDataSize;
+
+    return kStatus_Success;
+}
+
+/*!
+ * brief USART IRQ handle function.
+ *
+ * This function handles the USART transmit and receive IRQ request.
+ *
+ * param base USART peripheral base address.
+ * param handle USART handle pointer.
+ */
+void USART_TransferHandleIRQ(USART_Type *base, usart_handle_t *handle)
+{
+    /* Check arguments */
+    assert((NULL != base) && (NULL != handle));
+
+    bool receiveEnabled = ((handle->rxDataSize != 0U) || (handle->rxRingBuffer != NULL));
+    bool sendEnabled    = (handle->txDataSize != 0U);
+    uint8_t rxdata;
+    size_t tmpsize;
+
+    /* If RX overrun. */
+    if ((base->FIFOSTAT & USART_FIFOSTAT_RXERR_MASK) != 0U)
+    {
+        /* Clear rx error state. */
+        base->FIFOSTAT |= USART_FIFOSTAT_RXERR_MASK;
+        /* clear rxFIFO */
+        base->FIFOCFG |= USART_FIFOCFG_EMPTYRX_MASK;
+        /* Trigger callback. */
+        if (handle->callback != NULL)
+        {
+            handle->callback(base, handle, kStatus_USART_RxError, handle->userData);
+        }
+    }
+    while ((receiveEnabled && ((base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK) != 0U)) ||
+           (sendEnabled && ((base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK) != 0U)))
+    {
+        /* Receive data */
+        if (receiveEnabled && ((base->FIFOSTAT & USART_FIFOSTAT_RXNOTEMPTY_MASK) != 0U))
+        {
+            /* Receive to app bufffer if app buffer is present */
+            if (handle->rxDataSize != 0U)
+            {
+                rxdata          = (uint8_t)base->FIFORD;
+                *handle->rxData = rxdata;
+                handle->rxDataSize--;
+                handle->rxData++;
+                receiveEnabled = ((handle->rxDataSize != 0U) || (handle->rxRingBuffer != NULL));
+                if (0U == handle->rxDataSize)
+                {
+                    if (NULL == handle->rxRingBuffer)
+                    {
+                        base->FIFOINTENCLR = USART_FIFOINTENCLR_RXLVL_MASK | USART_FIFOINTENSET_RXERR_MASK;
+                    }
+                    handle->rxState = (uint8_t)kUSART_RxIdle;
+                    if (handle->callback != NULL)
+                    {
+                        handle->callback(base, handle, kStatus_USART_RxIdle, handle->userData);
+                    }
+                }
+            }
+            /* Otherwise receive to ring buffer if ring buffer is present */
+            else
+            {
+                if (handle->rxRingBuffer != NULL)
+                {
+                    /* If RX ring buffer is full, trigger callback to notify over run. */
+                    if (USART_TransferIsRxRingBufferFull(handle))
+                    {
+                        if (handle->callback != NULL)
+                        {
+                            handle->callback(base, handle, kStatus_USART_RxRingBufferOverrun, handle->userData);
+                        }
+                    }
+                    /* If ring buffer is still full after callback function, the oldest data is overridden. */
+                    if (USART_TransferIsRxRingBufferFull(handle))
+                    {
+                        /* Increase handle->rxRingBufferTail to make room for new data. */
+                        if ((size_t)handle->rxRingBufferTail + 1U == handle->rxRingBufferSize)
+                        {
+                            handle->rxRingBufferTail = 0U;
+                        }
+                        else
+                        {
+                            handle->rxRingBufferTail++;
+                        }
+                    }
+                    /* Read data. */
+                    rxdata                                         = (uint8_t)base->FIFORD;
+                    handle->rxRingBuffer[handle->rxRingBufferHead] = rxdata;
+                    /* Increase handle->rxRingBufferHead. */
+                    if ((size_t)handle->rxRingBufferHead + 1U == handle->rxRingBufferSize)
+                    {
+                        handle->rxRingBufferHead = 0U;
+                    }
+                    else
+                    {
+                        handle->rxRingBufferHead++;
+                    }
+                }
+            }
+        }
+        /* Send data */
+        if (sendEnabled && ((base->FIFOSTAT & USART_FIFOSTAT_TXNOTFULL_MASK) != 0U))
+        {
+            base->FIFOWR = *handle->txData;
+            handle->txDataSize--;
+            handle->txData++;
+            sendEnabled = handle->txDataSize != 0U;
+            if (!sendEnabled)
+            {
+                base->FIFOINTENCLR = USART_FIFOINTENCLR_TXLVL_MASK;
+                handle->txState    = (uint8_t)kUSART_TxIdle;
+
+                base->INTENSET |= USART_INTENSET_TXIDLEEN_MASK;
+            }
+        }
+    }
+
+    /* Tx idle and the interrupt is enabled. */
+    if ((0U != (base->INTENSET & USART_INTENSET_TXIDLEEN_MASK)) &&
+        (0U != (base->INTSTAT & USART_INTSTAT_TXIDLE_MASK)) && (handle->txState == (uint8_t)kUSART_TxIdle))
+    {
+        /* Disable tx idle interrupt */
+        base->INTENCLR |= USART_INTENCLR_TXIDLECLR_MASK;
+        /* Trigger callback. */
+        if (handle->callback != NULL)
+        {
+            handle->callback(base, handle, kStatus_USART_TxIdle, handle->userData);
+        }
+    }
+
+    /* ring buffer is not used */
+    if (NULL == handle->rxRingBuffer)
+    {
+        tmpsize = handle->rxDataSize;
+
+        /* restore if rx transfer ends and rxLevel is different from default value */
+        if ((tmpsize == 0U) && (USART_FIFOTRIG_RXLVL_GET(base) != handle->rxWatermark))
+        {
+            base->FIFOTRIG =
+                (base->FIFOTRIG & (~USART_FIFOTRIG_RXLVL_MASK)) | USART_FIFOTRIG_RXLVL(handle->rxWatermark);
+        }
+        /* decrease level if rx transfer is bellow */
+        if ((tmpsize != 0U) && (tmpsize < (USART_FIFOTRIG_RXLVL_GET(base) + 1U)))
+        {
+            base->FIFOTRIG = (base->FIFOTRIG & (~USART_FIFOTRIG_RXLVL_MASK)) | (USART_FIFOTRIG_RXLVL(tmpsize - 1U));
+        }
+    }
+}

FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/drivers/fsl_usart.h

@@ -0,0 +1,721 @@
+/*
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2019 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _FSL_USART_H_
+#define _FSL_USART_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup usart_driver
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief USART driver version 2.1.1. */
+#define FSL_USART_DRIVER_VERSION (MAKE_VERSION(2, 1, 1))
+/*@}*/
+
+#define USART_FIFOTRIG_TXLVL_GET(base) (((base)->FIFOTRIG & USART_FIFOTRIG_TXLVL_MASK) >> USART_FIFOTRIG_TXLVL_SHIFT)
+#define USART_FIFOTRIG_RXLVL_GET(base) (((base)->FIFOTRIG & USART_FIFOTRIG_RXLVL_MASK) >> USART_FIFOTRIG_RXLVL_SHIFT)
+
+/*! @brief Error codes for the USART driver. */
+enum
+{
+    kStatus_USART_TxBusy              = MAKE_STATUS(kStatusGroup_LPC_USART, 0),  /*!< Transmitter is busy. */
+    kStatus_USART_RxBusy              = MAKE_STATUS(kStatusGroup_LPC_USART, 1),  /*!< Receiver is busy. */
+    kStatus_USART_TxIdle              = MAKE_STATUS(kStatusGroup_LPC_USART, 2),  /*!< USART transmitter is idle. */
+    kStatus_USART_RxIdle              = MAKE_STATUS(kStatusGroup_LPC_USART, 3),  /*!< USART receiver is idle. */
+    kStatus_USART_TxError             = MAKE_STATUS(kStatusGroup_LPC_USART, 7),  /*!< Error happens on txFIFO. */
+    kStatus_USART_RxError             = MAKE_STATUS(kStatusGroup_LPC_USART, 9),  /*!< Error happens on rxFIFO. */
+    kStatus_USART_RxRingBufferOverrun = MAKE_STATUS(kStatusGroup_LPC_USART, 8),  /*!< Error happens on rx ring buffer */
+    kStatus_USART_NoiseError          = MAKE_STATUS(kStatusGroup_LPC_USART, 10), /*!< USART noise error. */
+    kStatus_USART_FramingError        = MAKE_STATUS(kStatusGroup_LPC_USART, 11), /*!< USART framing error. */
+    kStatus_USART_ParityError         = MAKE_STATUS(kStatusGroup_LPC_USART, 12), /*!< USART parity error. */
+    kStatus_USART_BaudrateNotSupport =
+        MAKE_STATUS(kStatusGroup_LPC_USART, 13), /*!< Baudrate is not support in current clock source */
+};
+
+/*! @brief USART synchronous mode. */
+typedef enum _usart_sync_mode
+{
+    kUSART_SyncModeDisabled = 0x0U, /*!< Asynchronous mode.       */
+    kUSART_SyncModeSlave    = 0x2U, /*!< Synchronous slave mode.  */
+    kUSART_SyncModeMaster   = 0x3U, /*!< Synchronous master mode. */
+} usart_sync_mode_t;
+
+/*! @brief USART parity mode. */
+typedef enum _usart_parity_mode
+{
+    kUSART_ParityDisabled = 0x0U, /*!< Parity disabled */
+    kUSART_ParityEven     = 0x2U, /*!< Parity enabled, type even, bit setting: PE|PT = 10 */
+    kUSART_ParityOdd      = 0x3U, /*!< Parity enabled, type odd,  bit setting: PE|PT = 11 */
+} usart_parity_mode_t;
+
+/*! @brief USART stop bit count. */
+typedef enum _usart_stop_bit_count
+{
+    kUSART_OneStopBit = 0U, /*!< One stop bit */
+    kUSART_TwoStopBit = 1U, /*!< Two stop bits */
+} usart_stop_bit_count_t;
+
+/*! @brief USART data size. */
+typedef enum _usart_data_len
+{
+    kUSART_7BitsPerChar = 0U, /*!< Seven bit mode */
+    kUSART_8BitsPerChar = 1U, /*!< Eight bit mode */
+} usart_data_len_t;
+
+/*! @brief USART clock polarity configuration, used in sync mode.*/
+typedef enum _usart_clock_polarity
+{
+    kUSART_RxSampleOnFallingEdge = 0x0U, /*!< Un_RXD is sampled on the falling edge of SCLK. */
+    kUSART_RxSampleOnRisingEdge  = 0x1U, /*!< Un_RXD is sampled on the rising edge of SCLK. */
+} usart_clock_polarity_t;
+
+/*! @brief txFIFO watermark values */
+typedef enum _usart_txfifo_watermark
+{
+    kUSART_TxFifo0 = 0, /*!< USART tx watermark is empty */
+    kUSART_TxFifo1 = 1, /*!< USART tx watermark at 1 item */
+    kUSART_TxFifo2 = 2, /*!< USART tx watermark at 2 items */
+    kUSART_TxFifo3 = 3, /*!< USART tx watermark at 3 items */
+    kUSART_TxFifo4 = 4, /*!< USART tx watermark at 4 items */
+    kUSART_TxFifo5 = 5, /*!< USART tx watermark at 5 items */
+    kUSART_TxFifo6 = 6, /*!< USART tx watermark at 6 items */
+    kUSART_TxFifo7 = 7, /*!< USART tx watermark at 7 items */
+} usart_txfifo_watermark_t;
+
+/*! @brief rxFIFO watermark values */
+typedef enum _usart_rxfifo_watermark
+{
+    kUSART_RxFifo1 = 0, /*!< USART rx watermark at 1 item */
+    kUSART_RxFifo2 = 1, /*!< USART rx watermark at 2 items */
+    kUSART_RxFifo3 = 2, /*!< USART rx watermark at 3 items */
+    kUSART_RxFifo4 = 3, /*!< USART rx watermark at 4 items */
+    kUSART_RxFifo5 = 4, /*!< USART rx watermark at 5 items */
+    kUSART_RxFifo6 = 5, /*!< USART rx watermark at 6 items */
+    kUSART_RxFifo7 = 6, /*!< USART rx watermark at 7 items */
+    kUSART_RxFifo8 = 7, /*!< USART rx watermark at 8 items */
+} usart_rxfifo_watermark_t;
+
+/*!
+ * @brief USART interrupt configuration structure, default settings all disabled.
+ */
+enum _usart_interrupt_enable
+{
+    kUSART_TxErrorInterruptEnable = (USART_FIFOINTENSET_TXERR_MASK),
+    kUSART_RxErrorInterruptEnable = (USART_FIFOINTENSET_RXERR_MASK),
+    kUSART_TxLevelInterruptEnable = (USART_FIFOINTENSET_TXLVL_MASK),
+    kUSART_RxLevelInterruptEnable = (USART_FIFOINTENSET_RXLVL_MASK),
+};
+
+/*!
+ * @brief USART status flags.
+ *
+ * This provides constants for the USART status flags for use in the USART functions.
+ */
+enum _usart_flags
+{
+    kUSART_TxError            = (USART_FIFOSTAT_TXERR_MASK),      /*!< TEERR bit, sets if TX buffer is error */
+    kUSART_RxError            = (USART_FIFOSTAT_RXERR_MASK),      /*!< RXERR bit, sets if RX buffer is error */
+    kUSART_TxFifoEmptyFlag    = (USART_FIFOSTAT_TXEMPTY_MASK),    /*!< TXEMPTY bit, sets if TX buffer is empty */
+    kUSART_TxFifoNotFullFlag  = (USART_FIFOSTAT_TXNOTFULL_MASK),  /*!< TXNOTFULL bit, sets if TX buffer is not full */
+    kUSART_RxFifoNotEmptyFlag = (USART_FIFOSTAT_RXNOTEMPTY_MASK), /*!< RXNOEMPTY bit, sets if RX buffer is not empty */
+    kUSART_RxFifoFullFlag     = (USART_FIFOSTAT_RXFULL_MASK),     /*!< RXFULL bit, sets if RX buffer is full */
+};
+
+/*! @brief USART configuration structure. */
+typedef struct _usart_config
+{
+    uint32_t baudRate_Bps;                /*!< USART baud rate  */
+    usart_parity_mode_t parityMode;       /*!< Parity mode, disabled (default), even, odd */
+    usart_stop_bit_count_t stopBitCount;  /*!< Number of stop bits, 1 stop bit (default) or 2 stop bits  */
+    usart_data_len_t bitCountPerChar;     /*!< Data length - 7 bit, 8 bit  */
+    bool loopback;                        /*!< Enable peripheral loopback */
+    bool enableRx;                        /*!< Enable RX */
+    bool enableTx;                        /*!< Enable TX */
+    bool enableContinuousSCLK;            /*!< USART continuous Clock generation enable in synchronous master mode. */
+    usart_txfifo_watermark_t txWatermark; /*!< txFIFO watermark */
+    usart_rxfifo_watermark_t rxWatermark; /*!< rxFIFO watermark */
+    usart_sync_mode_t syncMode; /*!< Transfer mode select - asynchronous, synchronous master, synchronous slave. */
+    usart_clock_polarity_t clockPolarity; /*!< Selects the clock polarity and sampling edge in synchronous mode. */
+} usart_config_t;
+
+/*! @brief USART transfer structure. */
+typedef struct _usart_transfer
+{
+    uint8_t *data;   /*!< The buffer of data to be transfer.*/
+    size_t dataSize; /*!< The byte count to be transfer. */
+} usart_transfer_t;
+
+/* Forward declaration of the handle typedef. */
+typedef struct _usart_handle usart_handle_t;
+
+/*! @brief USART transfer callback function. */
+typedef void (*usart_transfer_callback_t)(USART_Type *base, usart_handle_t *handle, status_t status, void *userData);
+
+/*! @brief USART handle structure. */
+struct _usart_handle
+{
+    uint8_t *volatile txData;   /*!< Address of remaining data to send. */
+    volatile size_t txDataSize; /*!< Size of the remaining data to send. */
+    size_t txDataSizeAll;       /*!< Size of the data to send out. */
+    uint8_t *volatile rxData;   /*!< Address of remaining data to receive. */
+    volatile size_t rxDataSize; /*!< Size of the remaining data to receive. */
+    size_t rxDataSizeAll;       /*!< Size of the data to receive. */
+
+    uint8_t *rxRingBuffer;              /*!< Start address of the receiver ring buffer. */
+    size_t rxRingBufferSize;            /*!< Size of the ring buffer. */
+    volatile uint16_t rxRingBufferHead; /*!< Index for the driver to store received data into ring buffer. */
+    volatile uint16_t rxRingBufferTail; /*!< Index for the user to get data from the ring buffer. */
+
+    usart_transfer_callback_t callback; /*!< Callback function. */
+    void *userData;                     /*!< USART callback function parameter.*/
+
+    volatile uint8_t txState; /*!< TX transfer state. */
+    volatile uint8_t rxState; /*!< RX transfer state */
+
+    uint8_t txWatermark; /*!< txFIFO watermark */
+    uint8_t rxWatermark; /*!< rxFIFO watermark */
+};
+
+/*! @brief Typedef for usart interrupt handler. */
+typedef void (*flexcomm_usart_irq_handler_t)(USART_Type *base, usart_handle_t *handle);
+
+/*******************************************************************************
+ * API
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* _cplusplus */
+
+/*! @brief Returns instance number for USART peripheral base address. */
+uint32_t USART_GetInstance(USART_Type *base);
+
+/*!
+ * @name Initialization and deinitialization
+ * @{
+ */
+
+/*!
+ * @brief Initializes a USART instance with user configuration structure and peripheral clock.
+ *
+ * This function configures the USART module with the user-defined settings. The user can configure the configuration
+ * structure and also get the default configuration by using the USART_GetDefaultConfig() function.
+ * Example below shows how to use this API to configure USART.
+ * @code
+ *  usart_config_t usartConfig;
+ *  usartConfig.baudRate_Bps = 115200U;
+ *  usartConfig.parityMode = kUSART_ParityDisabled;
+ *  usartConfig.stopBitCount = kUSART_OneStopBit;
+ *  USART_Init(USART1, &usartConfig, 20000000U);
+ * @endcode
+ *
+ * @param base USART peripheral base address.
+ * @param config Pointer to user-defined configuration structure.
+ * @param srcClock_Hz USART clock source frequency in HZ.
+ * @retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source.
+ * @retval kStatus_InvalidArgument USART base address is not valid
+ * @retval kStatus_Success Status USART initialize succeed
+ */
+status_t USART_Init(USART_Type *base, const usart_config_t *config, uint32_t srcClock_Hz);
+
+/*!
+ * @brief Deinitializes a USART instance.
+ *
+ * This function waits for TX complete, disables TX and RX, and disables the USART clock.
+ *
+ * @param base USART peripheral base address.
+ */
+void USART_Deinit(USART_Type *base);
+
+/*!
+ * @brief Gets the default configuration structure.
+ *
+ * This function initializes the USART configuration structure to a default value. The default
+ * values are:
+ *   usartConfig->baudRate_Bps = 115200U;
+ *   usartConfig->parityMode = kUSART_ParityDisabled;
+ *   usartConfig->stopBitCount = kUSART_OneStopBit;
+ *   usartConfig->bitCountPerChar = kUSART_8BitsPerChar;
+ *   usartConfig->loopback = false;
+ *   usartConfig->enableTx = false;
+ *   usartConfig->enableRx = false;
+ *
+ * @param config Pointer to configuration structure.
+ */
+void USART_GetDefaultConfig(usart_config_t *config);
+
+/*!
+ * @brief Sets the USART instance baud rate.
+ *
+ * This function configures the USART module baud rate. This function is used to update
+ * the USART module baud rate after the USART module is initialized by the USART_Init.
+ * @code
+ *  USART_SetBaudRate(USART1, 115200U, 20000000U);
+ * @endcode
+ *
+ * @param base USART peripheral base address.
+ * @param baudrate_Bps USART baudrate to be set.
+ * @param srcClock_Hz USART clock source frequency in HZ.
+ * @retval kStatus_USART_BaudrateNotSupport Baudrate is not support in current clock source.
+ * @retval kStatus_Success Set baudrate succeed.
+ * @retval kStatus_InvalidArgument One or more arguments are invalid.
+ */
+status_t USART_SetBaudRate(USART_Type *base, uint32_t baudrate_Bps, uint32_t srcClock_Hz);
+
+/* @} */
+
+/*!
+ * @name Status
+ * @{
+ */
+
+/*!
+ * @brief Get USART status flags.
+ *
+ * This function get all USART status flags, the flags are returned as the logical
+ * OR value of the enumerators @ref _usart_flags. To check a specific status,
+ * compare the return value with enumerators in @ref _usart_flags.
+ * For example, to check whether the TX is empty:
+ * @code
+ *     if (kUSART_TxFifoNotFullFlag & USART_GetStatusFlags(USART1))
+ *     {
+ *         ...
+ *     }
+ * @endcode
+ *
+ * @param base USART peripheral base address.
+ * @return USART status flags which are ORed by the enumerators in the _usart_flags.
+ */
+static inline uint32_t USART_GetStatusFlags(USART_Type *base)
+{
+    return base->FIFOSTAT;
+}
+
+/*!
+ * @brief Clear USART status flags.
+ *
+ * This function clear supported USART status flags
+ * Flags that can be cleared or set are:
+ *      kUSART_TxError
+ *      kUSART_RxError
+ * For example:
+ * @code
+ *     USART_ClearStatusFlags(USART1, kUSART_TxError | kUSART_RxError)
+ * @endcode
+ *
+ * @param base USART peripheral base address.
+ * @param mask status flags to be cleared.
+ */
+static inline void USART_ClearStatusFlags(USART_Type *base, uint32_t mask)
+{
+    /* Only TXERR, RXERR fields support write. Remaining fields should be set to zero */
+    base->FIFOSTAT = mask & (USART_FIFOSTAT_TXERR_MASK | USART_FIFOSTAT_RXERR_MASK);
+}
+
+/* @} */
+
+/*!
+ * @name Interrupts
+ * @{
+ */
+
+/*!
+ * @brief Enables USART interrupts according to the provided mask.
+ *
+ * This function enables the USART interrupts according to the provided mask. The mask
+ * is a logical OR of enumeration members. See @ref _usart_interrupt_enable.
+ * For example, to enable TX empty interrupt and RX full interrupt:
+ * @code
+ *     USART_EnableInterrupts(USART1, kUSART_TxLevelInterruptEnable | kUSART_RxLevelInterruptEnable);
+ * @endcode
+ *
+ * @param base USART peripheral base address.
+ * @param mask The interrupts to enable. Logical OR of @ref _usart_interrupt_enable.
+ */
+static inline void USART_EnableInterrupts(USART_Type *base, uint32_t mask)
+{
+    base->FIFOINTENSET = mask & 0xFUL;
+}
+
+/*!
+ * @brief Disables USART interrupts according to a provided mask.
+ *
+ * This function disables the USART interrupts according to a provided mask. The mask
+ * is a logical OR of enumeration members. See @ref _usart_interrupt_enable.
+ * This example shows how to disable the TX empty interrupt and RX full interrupt:
+ * @code
+ *     USART_DisableInterrupts(USART1, kUSART_TxLevelInterruptEnable | kUSART_RxLevelInterruptEnable);
+ * @endcode
+ *
+ * @param base USART peripheral base address.
+ * @param mask The interrupts to disable. Logical OR of @ref _usart_interrupt_enable.
+ */
+static inline void USART_DisableInterrupts(USART_Type *base, uint32_t mask)
+{
+    base->FIFOINTENCLR = mask & 0xFUL;
+}
+
+/*!
+ * @brief Returns enabled USART interrupts.
+ *
+ * This function returns the enabled USART interrupts.
+ *
+ * @param base USART peripheral base address.
+ */
+static inline uint32_t USART_GetEnabledInterrupts(USART_Type *base)
+{
+    return base->FIFOINTENSET;
+}
+
+/*!
+ * @brief Enable DMA for Tx
+ */
+static inline void USART_EnableTxDMA(USART_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->FIFOCFG |= USART_FIFOCFG_DMATX_MASK;
+    }
+    else
+    {
+        base->FIFOCFG &= ~(USART_FIFOCFG_DMATX_MASK);
+    }
+}
+
+/*!
+ * @brief Enable DMA for Rx
+ */
+static inline void USART_EnableRxDMA(USART_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->FIFOCFG |= USART_FIFOCFG_DMARX_MASK;
+    }
+    else
+    {
+        base->FIFOCFG &= ~(USART_FIFOCFG_DMARX_MASK);
+    }
+}
+
+/*!
+ * @brief Enable CTS.
+ * This function will determine whether CTS is used for flow control.
+ *
+ * @param base    USART peripheral base address.
+ * @param enable  Enable CTS or not, true for enable and false for disable.
+ */
+static inline void USART_EnableCTS(USART_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->CFG |= USART_CFG_CTSEN_MASK;
+    }
+    else
+    {
+        base->CFG &= ~USART_CFG_CTSEN_MASK;
+    }
+}
+
+/*!
+ * @brief Continuous Clock generation.
+ * By default, SCLK is only output while data is being transmitted in synchronous mode.
+ * Enable this funciton, SCLK will run continuously in synchronous mode, allowing
+ * characters to be received on Un_RxD independently from transmission on Un_TXD).
+ *
+ * @param base    USART peripheral base address.
+ * @param enable  Enable Continuous Clock generation mode or not, true for enable and false for disable.
+ */
+static inline void USART_EnableContinuousSCLK(USART_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->CTL |= USART_CTL_CC_MASK;
+    }
+    else
+    {
+        base->CTL &= ~USART_CTL_CC_MASK;
+    }
+}
+
+/*!
+ * @brief Enable Continuous Clock generation bit auto clear.
+ * While enable this cuntion, the Continuous Clock bit is automatically cleared when a complete
+ * character has been received. This bit is cleared at the same time.
+ *
+ * @param base    USART peripheral base address.
+ * @param enable  Enable auto clear or not, true for enable and false for disable.
+ */
+static inline void USART_EnableAutoClearSCLK(USART_Type *base, bool enable)
+{
+    if (enable)
+    {
+        base->CTL |= USART_CTL_CLRCCONRX_MASK;
+    }
+    else
+    {
+        base->CTL &= ~USART_CTL_CLRCCONRX_MASK;
+    }
+}
+/* @} */
+
+/*!
+ * @name Bus Operations
+ * @{
+ */
+
+/*!
+ * @brief Writes to the FIFOWR register.
+ *
+ * This function writes data to the txFIFO directly. The upper layer must ensure
+ * that txFIFO has space for data to write before calling this function.
+ *
+ * @param base USART peripheral base address.
+ * @param data The byte to write.
+ */
+static inline void USART_WriteByte(USART_Type *base, uint8_t data)
+{
+    base->FIFOWR = data;
+}
+
+/*!
+ * @brief Reads the FIFORD register directly.
+ *
+ * This function reads data from the rxFIFO directly. The upper layer must
+ * ensure that the rxFIFO is not empty before calling this function.
+ *
+ * @param base USART peripheral base address.
+ * @return The byte read from USART data register.
+ */
+static inline uint8_t USART_ReadByte(USART_Type *base)
+{
+    return (uint8_t)base->FIFORD;
+}
+
+/*!
+ * @brief Writes to the TX register using a blocking method.
+ *
+ * This function polls the TX register, waits for the TX register to be empty or for the TX FIFO
+ * to have room and writes data to the TX buffer.
+ *
+ * @param base USART peripheral base address.
+ * @param data Start address of the data to write.
+ * @param length Size of the data to write.
+ */
+void USART_WriteBlocking(USART_Type *base, const uint8_t *data, size_t length);
+
+/*!
+ * @brief Read RX data register using a blocking method.
+ *
+ * This function polls the RX register, waits for the RX register to be full or for RX FIFO to
+ * have data and read data from the TX register.
+ *
+ * @param base USART peripheral base address.
+ * @param data Start address of the buffer to store the received data.
+ * @param length Size of the buffer.
+ * @retval kStatus_USART_FramingError Receiver overrun happened while receiving data.
+ * @retval kStatus_USART_ParityError Noise error happened while receiving data.
+ * @retval kStatus_USART_NoiseError Framing error happened while receiving data.
+ * @retval kStatus_USART_RxError Overflow or underflow rxFIFO happened.
+ * @retval kStatus_Success Successfully received all data.
+ */
+status_t USART_ReadBlocking(USART_Type *base, uint8_t *data, size_t length);
+
+/* @} */
+
+/*!
+ * @name Transactional
+ * @{
+ */
+
+/*!
+ * @brief Initializes the USART handle.
+ *
+ * This function initializes the USART handle which can be used for other USART
+ * transactional APIs. Usually, for a specified USART instance,
+ * call this API once to get the initialized handle.
+ *
+ * @param base USART peripheral base address.
+ * @param handle USART handle pointer.
+ * @param callback The callback function.
+ * @param userData The parameter of the callback function.
+ */
+status_t USART_TransferCreateHandle(USART_Type *base,
+                                    usart_handle_t *handle,
+                                    usart_transfer_callback_t callback,
+                                    void *userData);
+
+/*!
+ * @brief Transmits a buffer of data using the interrupt method.
+ *
+ * This function sends data using an interrupt method. This is a non-blocking function, which
+ * returns directly without waiting for all data to be written to the TX register. When
+ * all data is written to the TX register in the IRQ handler, the USART driver calls the callback
+ * function and passes the @ref kStatus_USART_TxIdle as status parameter.
+ *
+ * @note The kStatus_USART_TxIdle is passed to the upper layer when all data is written
+ * to the TX register. However it does not ensure that all data are sent out. Before disabling the TX,
+ * check the kUSART_TransmissionCompleteFlag to ensure that the TX is finished.
+ *
+ * @param base USART peripheral base address.
+ * @param handle USART handle pointer.
+ * @param xfer USART transfer structure. See  #usart_transfer_t.
+ * @retval kStatus_Success Successfully start the data transmission.
+ * @retval kStatus_USART_TxBusy Previous transmission still not finished, data not all written to TX register yet.
+ * @retval kStatus_InvalidArgument Invalid argument.
+ */
+status_t USART_TransferSendNonBlocking(USART_Type *base, usart_handle_t *handle, usart_transfer_t *xfer);
+
+/*!
+ * @brief Sets up the RX ring buffer.
+ *
+ * This function sets up the RX ring buffer to a specific USART handle.
+ *
+ * When the RX ring buffer is used, data received are stored into the ring buffer even when the
+ * user doesn't call the USART_TransferReceiveNonBlocking() API. If there is already data received
+ * in the ring buffer, the user can get the received data from the ring buffer directly.
+ *
+ * @note When using the RX ring buffer, one byte is reserved for internal use. In other
+ * words, if @p ringBufferSize is 32, then only 31 bytes are used for saving data.
+ *
+ * @param base USART peripheral base address.
+ * @param handle USART handle pointer.
+ * @param ringBuffer Start address of the ring buffer for background receiving. Pass NULL to disable the ring buffer.
+ * @param ringBufferSize size of the ring buffer.
+ */
+void USART_TransferStartRingBuffer(USART_Type *base,
+                                   usart_handle_t *handle,
+                                   uint8_t *ringBuffer,
+                                   size_t ringBufferSize);
+
+/*!
+ * @brief Aborts the background transfer and uninstalls the ring buffer.
+ *
+ * This function aborts the background transfer and uninstalls the ring buffer.
+ *
+ * @param base USART peripheral base address.
+ * @param handle USART handle pointer.
+ */
+void USART_TransferStopRingBuffer(USART_Type *base, usart_handle_t *handle);
+
+/*!
+ * @brief Get the length of received data in RX ring buffer.
+ *
+ * @param handle USART handle pointer.
+ * @return Length of received data in RX ring buffer.
+ */
+size_t USART_TransferGetRxRingBufferLength(usart_handle_t *handle);
+
+/*!
+ * @brief Aborts the interrupt-driven data transmit.
+ *
+ * This function aborts the interrupt driven data sending. The user can get the remainBtyes to find out
+ * how many bytes are still not sent out.
+ *
+ * @param base USART peripheral base address.
+ * @param handle USART handle pointer.
+ */
+void USART_TransferAbortSend(USART_Type *base, usart_handle_t *handle);
+
+/*!
+ * @brief Get the number of bytes that have been written to USART TX register.
+ *
+ * This function gets the number of bytes that have been written to USART TX
+ * register by interrupt method.
+ *
+ * @param base USART peripheral base address.
+ * @param handle USART handle pointer.
+ * @param count Send bytes count.
+ * @retval kStatus_NoTransferInProgress No send in progress.
+ * @retval kStatus_InvalidArgument Parameter is invalid.
+ * @retval kStatus_Success Get successfully through the parameter \p count;
+ */
+status_t USART_TransferGetSendCount(USART_Type *base, usart_handle_t *handle, uint32_t *count);
+
+/*!
+ * @brief Receives a buffer of data using an interrupt method.
+ *
+ * This function receives data using an interrupt method. This is a non-blocking function, which
+ *  returns without waiting for all data to be received.
+ * If the RX ring buffer is used and not empty, the data in the ring buffer is copied and
+ * the parameter @p receivedBytes shows how many bytes are copied from the ring buffer.
+ * After copying, if the data in the ring buffer is not enough to read, the receive
+ * request is saved by the USART driver. When the new data arrives, the receive request
+ * is serviced first. When all data is received, the USART driver notifies the upper layer
+ * through a callback function and passes the status parameter @ref kStatus_USART_RxIdle.
+ * For example, the upper layer needs 10 bytes but there are only 5 bytes in the ring buffer.
+ * The 5 bytes are copied to the xfer->data and this function returns with the
+ * parameter @p receivedBytes set to 5. For the left 5 bytes, newly arrived data is
+ * saved from the xfer->data[5]. When 5 bytes are received, the USART driver notifies the upper layer.
+ * If the RX ring buffer is not enabled, this function enables the RX and RX interrupt
+ * to receive data to the xfer->data. When all data is received, the upper layer is notified.
+ *
+ * @param base USART peripheral base address.
+ * @param handle USART handle pointer.
+ * @param xfer USART transfer structure, see #usart_transfer_t.
+ * @param receivedBytes Bytes received from the ring buffer directly.
+ * @retval kStatus_Success Successfully queue the transfer into transmit queue.
+ * @retval kStatus_USART_RxBusy Previous receive request is not finished.
+ * @retval kStatus_InvalidArgument Invalid argument.
+ */
+status_t USART_TransferReceiveNonBlocking(USART_Type *base,
+                                          usart_handle_t *handle,
+                                          usart_transfer_t *xfer,
+                                          size_t *receivedBytes);
+
+/*!
+ * @brief Aborts the interrupt-driven data receiving.
+ *
+ * This function aborts the interrupt-driven data receiving. The user can get the remainBytes to find out
+ * how many bytes not received yet.
+ *
+ * @param base USART peripheral base address.
+ * @param handle USART handle pointer.
+ */
+void USART_TransferAbortReceive(USART_Type *base, usart_handle_t *handle);
+
+/*!
+ * @brief Get the number of bytes that have been received.
+ *
+ * This function gets the number of bytes that have been received.
+ *
+ * @param base USART peripheral base address.
+ * @param handle USART handle pointer.
+ * @param count Receive bytes count.
+ * @retval kStatus_NoTransferInProgress No receive in progress.
+ * @retval kStatus_InvalidArgument Parameter is invalid.
+ * @retval kStatus_Success Get successfully through the parameter \p count;
+ */
+status_t USART_TransferGetReceiveCount(USART_Type *base, usart_handle_t *handle, uint32_t *count);
+
+/*!
+ * @brief USART IRQ handle function.
+ *
+ * This function handles the USART transmit and receive IRQ request.
+ *
+ * @param base USART peripheral base address.
+ * @param handle USART handle pointer.
+ */
+void USART_TransferHandleIRQ(USART_Type *base, usart_handle_t *handle);
+
+/* @} */
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*! @}*/
+
+#endif /* _FSL_USART_H_ */

FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/utilities/freertos_tasks_c_additions.h

@@ -0,0 +1,122 @@
+/*
+ * Copyright 2017-2019 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/* freertos_tasks_c_additions.h Rev. 1.3 */
+#ifndef FREERTOS_TASKS_C_ADDITIONS_H
+#define FREERTOS_TASKS_C_ADDITIONS_H
+
+#include <stdint.h>
+
+#if (configUSE_TRACE_FACILITY == 0)
+#error "configUSE_TRACE_FACILITY must be enabled"
+#endif
+
+#define FREERTOS_DEBUG_CONFIG_MAJOR_VERSION 1
+#define FREERTOS_DEBUG_CONFIG_MINOR_VERSION 3
+
+/* NOTE!!
+ * Default to a FreeRTOS version which didn't include these macros. FreeRTOS
+ * v7.5.3 is used here.
+ */
+#ifndef tskKERNEL_VERSION_BUILD
+#define tskKERNEL_VERSION_BUILD 3
+#endif
+#ifndef tskKERNEL_VERSION_MINOR
+#define tskKERNEL_VERSION_MINOR 5
+#endif
+#ifndef tskKERNEL_VERSION_MAJOR
+#define tskKERNEL_VERSION_MAJOR 7
+#endif
+
+/* NOTE!!
+ * The configFRTOS_MEMORY_SCHEME macro describes the heap scheme using a value
+ * 1 - 5 which corresponds to the following schemes:
+ *
+ * heap_1 - the very simplest, does not permit memory to be freed
+ * heap_2 - permits memory to be freed, but not does coalescence adjacent free
+ *          blocks.
+ * heap_3 - simply wraps the standard malloc() and free() for thread safety
+ * heap_4 - coalesces adjacent free blocks to avoid fragmentation. Includes
+ *          absolute address placement option
+ * heap_5 - as per heap_4, with the ability to span the heap across
+ *          multiple nonOadjacent memory areas
+ */
+#ifndef configFRTOS_MEMORY_SCHEME
+#define configFRTOS_MEMORY_SCHEME 3 /* thread safe malloc */
+#endif
+
+#if ((configFRTOS_MEMORY_SCHEME > 5) || (configFRTOS_MEMORY_SCHEME < 1))
+#error "Invalid configFRTOS_MEMORY_SCHEME setting!"
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern const uint8_t FreeRTOSDebugConfig[];
+
+/* NOTES!!
+ * IAR documentation is confusing. It suggests the data must be statically
+ * linked, and the #pragma placed immediately before the symbol definition.
+ * The IAR supplied examples violate both "rules", so this is a best guess.
+ */
+
+#if (tskKERNEL_VERSION_MAJOR >= 10) && (tskKERNEL_VERSION_MINOR >= 2)
+#if defined(__GNUC__)
+char *const portArch_Name __attribute__((section(".rodata"))) = portARCH_NAME;
+#elif defined(__CC_ARM) || defined(__ARMCC_VERSION)
+char *const portArch_Name __attribute__((used)) = portARCH_NAME;
+#elif defined(__IAR_SYSTEMS_ICC__)
+char *const portArch_Name = portARCH_NAME;
+#pragma required=portArch_Name
+#endif
+#else
+char *const portArch_Name = NULL;
+#endif	// tskKERNEL_VERSION_MAJOR
+
+#if defined(__GNUC__)
+const uint8_t FreeRTOSDebugConfig[] __attribute__((section(".rodata"))) =
+#elif defined(__CC_ARM) || defined(__ARMCC_VERSION)
+const uint8_t FreeRTOSDebugConfig[] __attribute__((used)) =
+#elif defined(__IAR_SYSTEMS_ICC__)
+#pragma required=FreeRTOSDebugConfig
+const uint8_t FreeRTOSDebugConfig[] =
+#endif
+{
+    FREERTOS_DEBUG_CONFIG_MAJOR_VERSION,
+    FREERTOS_DEBUG_CONFIG_MINOR_VERSION,
+    tskKERNEL_VERSION_MAJOR,
+    tskKERNEL_VERSION_MINOR,
+    tskKERNEL_VERSION_BUILD,
+    configFRTOS_MEMORY_SCHEME,
+    offsetof(struct tskTaskControlBlock, pxTopOfStack),
+#if (tskKERNEL_VERSION_MAJOR > 8)
+    offsetof(struct tskTaskControlBlock, xStateListItem),
+#else
+    offsetof(struct tskTaskControlBlock, xGenericListItem),
+#endif
+    offsetof(struct tskTaskControlBlock, xEventListItem),
+    offsetof(struct tskTaskControlBlock, pxStack),
+    offsetof(struct tskTaskControlBlock, pcTaskName),
+    offsetof(struct tskTaskControlBlock, uxTCBNumber),
+    offsetof(struct tskTaskControlBlock, uxTaskNumber),
+    configMAX_TASK_NAME_LEN,
+    configMAX_PRIORITIES,
+    configENABLE_MPU,
+    configENABLE_FPU,
+    configENABLE_TRUSTZONE,
+	configRUN_FREERTOS_SECURE_ONLY,
+	0, 			// 32-bit align
+	0, 0, 0, 0	// padding
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // FREERTOS_TASKS_C_ADDITIONS_H

FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/utilities/fsl_assert.c

@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "fsl_common.h"
+#include "fsl_debug_console.h"
+
+#ifndef NDEBUG
+#if (defined(__CC_ARM)) || (defined(__ARMCC_VERSION)) || (defined(__ICCARM__))
+void __aeabi_assert(const char *failedExpr, const char *file, int line)
+{
+    PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" \n", failedExpr, file, line);
+    for (;;)
+    {
+        __BKPT(0);
+    }
+}
+#elif (defined(__GNUC__))
+#if defined(__REDLIB__)
+void __assertion_failed(char *failedExpr)
+{
+    PRINTF("ASSERT ERROR \" %s \n", failedExpr);
+    for (;;)
+    {
+        __BKPT(0);
+    }
+}
+#else
+void __assert_func(const char *file, int line, const char *func, const char *failedExpr)
+{
+    PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" function name \"%s\" \n", failedExpr, file, line, func);
+    for (;;)
+    {
+        __BKPT(0);
+    }
+}
+#endif /* defined(__REDLIB__) */
+#endif /* (defined(__CC_ARM) || (defined(__ICCARM__)) || (defined(__ARMCC_VERSION)) */
+#endif /* NDEBUG */

FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/utilities/fsl_debug_console.h

@@ -0,0 +1,244 @@
+/*
+ * Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2018 NXP
+ * All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Debug console shall provide input and output functions to scan and print formatted data.
+ * o Support a format specifier for PRINTF follows this prototype "%[flags][width][.precision][length]specifier"
+ *   - [flags] :'-', '+', '#', ' ', '0'
+ *   - [width]:  number (0,1...)
+ *   - [.precision]: number (0,1...)
+ *   - [length]: do not support
+ *   - [specifier]: 'd', 'i', 'f', 'F', 'x', 'X', 'o', 'p', 'u', 'c', 's', 'n'
+ * o Support a format specifier for SCANF follows this prototype " %[*][width][length]specifier"
+ *   - [*]: is supported.
+ *   - [width]: number (0,1...)
+ *   - [length]: 'h', 'hh', 'l','ll','L'. ignore ('j','z','t')
+ *   - [specifier]: 'd', 'i', 'u', 'f', 'F', 'e', 'E', 'g', 'G', 'a', 'A', 'o', 'c', 's'
+ */
+
+#ifndef _FSL_DEBUGCONSOLE_H_
+#define _FSL_DEBUGCONSOLE_H_
+
+#include "fsl_common.h"
+#include "serial_manager.h"
+
+/*!
+ * @addtogroup debugconsole
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+extern serial_handle_t g_serialHandle; /*!< serial manager handle */
+
+/*! @brief Definition select redirect toolchain printf, scanf to uart or not. */
+#define DEBUGCONSOLE_REDIRECT_TO_TOOLCHAIN 0U /*!< Select toolchain printf and scanf. */
+#define DEBUGCONSOLE_REDIRECT_TO_SDK 1U       /*!< Select SDK version printf, scanf. */
+#define DEBUGCONSOLE_DISABLE 2U               /*!< Disable debugconsole function. */
+
+/*! @brief Definition to select sdk or toolchain printf, scanf. The macro only support
+ * to be redefined in project setting.
+ */
+#ifndef SDK_DEBUGCONSOLE
+#define SDK_DEBUGCONSOLE 1U
+#endif
+
+#if defined(SDK_DEBUGCONSOLE) && !(SDK_DEBUGCONSOLE)
+#include <stdio.h>
+#endif
+
+/*! @brief Definition to select redirect toolchain printf, scanf to uart or not.
+ *
+ *  if SDK_DEBUGCONSOLE defined to 0,it represents select toolchain printf, scanf.
+ *  if SDK_DEBUGCONSOLE defined to 1,it represents select SDK version printf, scanf.
+ *  if SDK_DEBUGCONSOLE defined to 2,it represents disable debugconsole function.
+ */
+#if SDK_DEBUGCONSOLE == DEBUGCONSOLE_DISABLE /* Disable debug console */
+#define PRINTF
+#define SCANF
+#define PUTCHAR
+#define GETCHAR
+#elif SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK /* Select printf, scanf, putchar, getchar of SDK version. */
+#define PRINTF DbgConsole_Printf
+#define SCANF DbgConsole_Scanf
+#define PUTCHAR DbgConsole_Putchar
+#define GETCHAR DbgConsole_Getchar
+#elif SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_TOOLCHAIN /* Select printf, scanf, putchar, getchar of toolchain. \ \
+                                                              */
+#define PRINTF printf
+#define SCANF scanf
+#define PUTCHAR putchar
+#define GETCHAR getchar
+#endif /* SDK_DEBUGCONSOLE */
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*! @name Initialization*/
+/* @{ */
+
+#if ((SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK) || defined(SDK_DEBUGCONSOLE_UART))
+/*!
+ * @brief Initializes the peripheral used for debug messages.
+ *
+ * Call this function to enable debug log messages to be output via the specified peripheral
+ * initialized by the serial manager module.
+ * After this function has returned, stdout and stdin are connected to the selected peripheral.
+ *
+ * @param instance      The instance of the module.
+ * @param baudRate      The desired baud rate in bits per second.
+ * @param device        Low level device type for the debug console, can be one of the following.
+ *                      @arg kSerialPort_Uart,
+ *                      @arg kSerialPort_UsbCdc
+ *                      @arg kSerialPort_UsbCdcVirtual.
+ * @param clkSrcFreq    Frequency of peripheral source clock.
+ *
+ * @return              Indicates whether initialization was successful or not.
+ * @retval kStatus_Success          Execution successfully
+ */
+status_t DbgConsole_Init(uint8_t instance, uint32_t baudRate, serial_port_type_t device, uint32_t clkSrcFreq);
+
+/*!
+ * @brief De-initializes the peripheral used for debug messages.
+ *
+ * Call this function to disable debug log messages to be output via the specified peripheral
+ * initialized by the serial manager module.
+ *
+ * @return Indicates whether de-initialization was successful or not.
+ */
+status_t DbgConsole_Deinit(void);
+#else
+/*!
+ * Use an error to replace the DbgConsole_Init when SDK_DEBUGCONSOLE is not DEBUGCONSOLE_REDIRECT_TO_SDK and
+ * SDK_DEBUGCONSOLE_UART is not defined.
+ */
+static inline status_t DbgConsole_Init(uint8_t instance,
+                                       uint32_t baudRate,
+                                       serial_port_type_t device,
+                                       uint32_t clkSrcFreq)
+{
+    (void)instance;
+    (void)baudRate;
+    (void)device;
+    (void)clkSrcFreq;
+    return (status_t)kStatus_Fail;
+}
+/*!
+ * Use an error to replace the DbgConsole_Deinit when SDK_DEBUGCONSOLE is not DEBUGCONSOLE_REDIRECT_TO_SDK and
+ * SDK_DEBUGCONSOLE_UART is not defined.
+ */
+static inline status_t DbgConsole_Deinit(void)
+{
+    return (status_t)kStatus_Fail;
+}
+#endif /* ((SDK_DEBUGCONSOLE == DEBUGCONSOLE_REDIRECT_TO_SDK) || defined(SDK_DEBUGCONSOLE_UART)) */
+
+#if SDK_DEBUGCONSOLE
+/*!
+ * @brief Writes formatted output to the standard output stream.
+ *
+ * Call this function to write a formatted output to the standard output stream.
+ *
+ * @param   formatString Format control string.
+ * @return  Returns the number of characters printed or a negative value if an error occurs.
+ */
+int DbgConsole_Printf(const char *formatString, ...);
+
+/*!
+ * @brief Writes a character to stdout.
+ *
+ * Call this function to write a character to stdout.
+ *
+ * @param   ch Character to be written.
+ * @return  Returns the character written.
+ */
+int DbgConsole_Putchar(int ch);
+
+/*!
+ * @brief Reads formatted data from the standard input stream.
+ *
+ * Call this function to read formatted data from the standard input stream.
+ *
+ * @note Due the limitation in the BM OSA environment (CPU is blocked in the function,
+ * other tasks will not be scheduled), the function cannot be used when the
+ * DEBUG_CONSOLE_TRANSFER_NON_BLOCKING is set in the BM OSA environment.
+ * And an error is returned when the function called in this case. The suggestion
+ * is that polling the non-blocking function DbgConsole_TryGetchar to get the input char.
+ *
+ * @param   formatString Format control string.
+ * @return  Returns the number of fields successfully converted and assigned.
+ */
+int DbgConsole_Scanf(char *formatString, ...);
+
+/*!
+ * @brief Reads a character from standard input.
+ *
+ * Call this function to read a character from standard input.
+ *
+ * @note Due the limitation in the BM OSA environment (CPU is blocked in the function,
+ * other tasks will not be scheduled), the function cannot be used when the
+ * DEBUG_CONSOLE_TRANSFER_NON_BLOCKING is set in the BM OSA environment.
+ * And an error is returned when the function called in this case. The suggestion
+ * is that polling the non-blocking function DbgConsole_TryGetchar to get the input char.
+ *
+ * @return Returns the character read.
+ */
+int DbgConsole_Getchar(void);
+
+/*!
+ * @brief Writes formatted output to the standard output stream with the blocking mode.
+ *
+ * Call this function to write a formatted output to the standard output stream with the blocking mode.
+ * The function will send data with blocking mode no matter the DEBUG_CONSOLE_TRANSFER_NON_BLOCKING set
+ * or not.
+ * The function could be used in system ISR mode with DEBUG_CONSOLE_TRANSFER_NON_BLOCKING set.
+ *
+ * @param   formatString Format control string.
+ * @return  Returns the number of characters printed or a negative value if an error occurs.
+ */
+int DbgConsole_BlockingPrintf(const char *formatString, ...);
+
+/*!
+ * @brief Debug console flush.
+ *
+ * Call this function to wait the tx buffer empty.
+ * If interrupt transfer is using, make sure the global IRQ is enable before call this function
+ * This function should be called when
+ * 1, before enter power down mode
+ * 2, log is required to print to terminal immediately
+ * @return Indicates whether wait idle was successful or not.
+ */
+status_t DbgConsole_Flush(void);
+
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+/*!
+ * @brief Debug console try to get char
+ * This function provides a API which will not block current task, if character is
+ * available return it, otherwise return fail.
+ * @param ch the address of char to receive
+ * @return Indicates get char was successful or not.
+ */
+status_t DbgConsole_TryGetchar(char *ch);
+#endif
+
+#endif /* SDK_DEBUGCONSOLE */
+
+/*! @} */
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+/*! @} */
+
+#endif /* _FSL_DEBUGCONSOLE_H_ */

FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/utilities/fsl_debug_console_conf.h

@@ -0,0 +1,158 @@
+/*
+ * Copyright 2017 - 2019 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _FSL_DEBUG_CONSOLE_CONF_H_
+#define _FSL_DEBUG_CONSOLE_CONF_H_
+
+/****************Debug console configuration********************/
+
+/*! @brief If Non-blocking mode is needed, please define it at project setting,
+ * otherwise blocking mode is the default transfer mode.
+ * Warning: If you want to use non-blocking transfer,please make sure the corresponding
+ * IO interrupt is enable, otherwise there is no output.
+ * And non-blocking is combine with buffer, no matter bare-metal or rtos.
+ * Below shows how to configure in your project if you want to use non-blocking mode.
+ * For IAR, right click project and select "Options", define it in "C/C++ Compiler->Preprocessor->Defined symbols".
+ * For KEIL, click "Options for Target…", define it in "C/C++->Preprocessor Symbols->Define".
+ * For ARMGCC, open CmakeLists.txt and add the following lines,
+ * "SET(CMAKE_C_FLAGS_DEBUG "${CMAKE_C_FLAGS_DEBUG} -DDEBUG_CONSOLE_TRANSFER_NON_BLOCKING")" for debug target.
+ * "SET(CMAKE_C_FLAGS_RELEASE "${CMAKE_C_FLAGS_RELEASE} -DDEBUG_CONSOLE_TRANSFER_NON_BLOCKING")" for release target.
+ * For MCUxpresso, right click project and select "Properties", define it in "C/C++ Build->Settings->MCU C
+ * Complier->Preprocessor".
+ *
+ */
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+/*! @brief define the transmit buffer length which is used to store the multi task log, buffer is enabled automatically
+ * when
+ * non-blocking transfer is using,
+ * This value will affect the RAM's ultilization, should be set per paltform's capability and software requirement.
+ * If it is configured too small, log maybe missed , because the log will not be
+ * buffered if the buffer is full, and the print will return immediately with -1.
+ * And this value should be multiple of 4 to meet memory alignment.
+ *
+ */
+#ifndef DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN
+#define DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN (512U)
+#endif /* DEBUG_CONSOLE_TRANSMIT_BUFFER_LEN */
+
+/*! @brief define the receive buffer length which is used to store the user input, buffer is enabled automatically when
+ * non-blocking transfer is using,
+ * This value will affect the RAM's ultilization, should be set per paltform's capability and software requirement.
+ * If it is configured too small, log maybe missed, because buffer will be overwrited if buffer is too small.
+ * And this value should be multiple of 4 to meet memory alignment.
+ *
+ */
+#ifndef DEBUG_CONSOLE_RECEIVE_BUFFER_LEN
+#define DEBUG_CONSOLE_RECEIVE_BUFFER_LEN (1024U)
+#endif /* DEBUG_CONSOLE_RECEIVE_BUFFER_LEN */
+
+/*!@ brief Whether enable the reliable TX function
+ * If the macro is zero, the reliable TX function of the debug console is disabled.
+ * When the macro is zero, the string of PRINTF will be thrown away after the transmit buffer is full.
+ */
+#ifndef DEBUG_CONSOLE_TX_RELIABLE_ENABLE
+#define DEBUG_CONSOLE_TX_RELIABLE_ENABLE (1U)
+#endif /* DEBUG_CONSOLE_RX_ENABLE */
+
+#else
+#define DEBUG_CONSOLE_TRANSFER_BLOCKING
+#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */
+
+/*!@ brief Whether enable the RX function
+ * If the macro is zero, the receive function of the debug console is disabled.
+ */
+#ifndef DEBUG_CONSOLE_RX_ENABLE
+#define DEBUG_CONSOLE_RX_ENABLE (1U)
+#endif /* DEBUG_CONSOLE_RX_ENABLE */
+
+/*!@ brief define the MAX log length debug console support , that is when you call printf("log", x);, the log
+ * length can not bigger than this value.
+ * This macro decide the local log buffer length, the buffer locate at stack, the stack maybe overflow if
+ * the buffer is too big and current task stack size not big enough.
+ */
+#ifndef DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN
+#define DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN (128U)
+#endif /* DEBUG_CONSOLE_PRINTF_MAX_LOG_LEN */
+
+/*!@ brief define the buffer support buffer scanf log length, that is when you call scanf("log", &x);, the log
+ * length can not bigger than this value.
+ * As same as the DEBUG_CONSOLE_BUFFER_PRINTF_MAX_LOG_LEN.
+ */
+#ifndef DEBUG_CONSOLE_SCANF_MAX_LOG_LEN
+#define DEBUG_CONSOLE_SCANF_MAX_LOG_LEN (20U)
+#endif /* DEBUG_CONSOLE_SCANF_MAX_LOG_LEN */
+
+/*! @brief Debug console synchronization
+ * User should not change these macro for synchronization mode, but add the
+ * corresponding synchronization mechanism per different software environment.
+ * Such as, if another RTOS is used,
+ * add:
+ *  #define DEBUG_CONSOLE_SYNCHRONIZATION_XXXX 3
+ * in this configuration file and implement the synchronization in fsl.log.c.
+ */
+/*! @brief synchronization for baremetal software */
+#define DEBUG_CONSOLE_SYNCHRONIZATION_BM 0
+/*! @brief synchronization for freertos software */
+#define DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS 1
+
+/*! @brief RTOS synchronization mechanism disable
+ * If not defined, default is enable, to avoid multitask log print mess.
+ * If other RTOS is used, you can implement the RTOS's specific synchronization mechanism in fsl.log.c
+ * If synchronization is disabled, log maybe messed on terminal.
+ */
+#ifndef DEBUG_CONSOLE_DISABLE_RTOS_SYNCHRONIZATION
+#ifdef DEBUG_CONSOLE_TRANSFER_NON_BLOCKING
+#ifdef FSL_RTOS_FREE_RTOS
+#define DEBUG_CONSOLE_SYNCHRONIZATION_MODE DEBUG_CONSOLE_SYNCHRONIZATION_FREERTOS
+#else
+#define DEBUG_CONSOLE_SYNCHRONIZATION_MODE DEBUG_CONSOLE_SYNCHRONIZATION_BM
+#endif /* FSL_RTOS_FREE_RTOS */
+#else
+#define DEBUG_CONSOLE_SYNCHRONIZATION_MODE DEBUG_CONSOLE_SYNCHRONIZATION_BM
+#endif /* DEBUG_CONSOLE_TRANSFER_NON_BLOCKING */
+#endif /* DEBUG_CONSOLE_DISABLE_RTOS_SYNCHRONIZATION */
+
+/*! @brief echo function support
+ * If you want to use the echo function,please define DEBUG_CONSOLE_ENABLE_ECHO
+ * at your project setting.
+ */
+#ifndef DEBUG_CONSOLE_ENABLE_ECHO
+#define DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION 0
+#else
+#define DEBUG_CONSOLE_ENABLE_ECHO_FUNCTION 1
+#endif /* DEBUG_CONSOLE_ENABLE_ECHO */
+
+/*********************************************************************/
+
+/***************Debug console other configuration*********************/
+/*! @brief Definition to printf the float number. */
+#ifndef PRINTF_FLOAT_ENABLE
+#define PRINTF_FLOAT_ENABLE 0U
+#endif /* PRINTF_FLOAT_ENABLE */
+
+/*! @brief Definition to scanf the float number. */
+#ifndef SCANF_FLOAT_ENABLE
+#define SCANF_FLOAT_ENABLE 0U
+#endif /* SCANF_FLOAT_ENABLE */
+
+/*! @brief Definition to support advanced format specifier for printf. */
+#ifndef PRINTF_ADVANCED_ENABLE
+#define PRINTF_ADVANCED_ENABLE 0U
+#endif /* PRINTF_ADVANCED_ENABLE */
+
+/*! @brief Definition to support advanced format specifier for scanf. */
+#ifndef SCANF_ADVANCED_ENABLE
+#define SCANF_ADVANCED_ENABLE 0U
+#endif /* SCANF_ADVANCED_ENABLE */
+
+/*! @brief Definition to select virtual com(USB CDC) as the debug console. */
+#ifndef BOARD_USE_VIRTUALCOM
+#define BOARD_USE_VIRTUALCOM 0U
+#endif
+/*******************************************************************/
+
+#endif /* _FSL_DEBUG_CONSOLE_CONF_H_ */

FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/NXP_Code/utilities/fsl_str.h

@@ -0,0 +1,66 @@
+/*
+ * Copyright 2017 NXP
+ * All rights reserved.
+ *
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef _FSL_STR_H
+#define _FSL_STR_H
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup debugconsole
+ * @{
+ */
+
+/*******************************************************************************
+ * Prototypes
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*!
+ * @brief A function pointer which is used when format printf log.
+ */
+typedef void (*printfCb)(char *buf, int32_t *indicator, char val, int len);
+
+/*!
+ * @brief This function outputs its parameters according to a formatted string.
+ *
+ * @note I/O is performed by calling given function pointer using following
+ * (*func_ptr)(c);
+ *
+ * @param[in] fmt   Format string for printf.
+ * @param[in] ap  Arguments to printf.
+ * @param[in] buf  pointer to the buffer
+ * @param cb print callbck function pointer
+ *
+ * @return Number of characters to be print
+ */
+int StrFormatPrintf(const char *fmt, va_list ap, char *buf, printfCb cb);
+
+/*!
+ * @brief Converts an input line of ASCII characters based upon a provided
+ * string format.
+ *
+ * @param[in] line_ptr The input line of ASCII data.
+ * @param[in] format   Format first points to the format string.
+ * @param[in] args_ptr The list of parameters.
+ *
+ * @return Number of input items converted and assigned.
+ * @retval IO_EOF When line_ptr is empty string "".
+ */
+int StrFormatScanf(const char *line_ptr, char *format, va_list args_ptr);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+/*! @} */
+
+#endif /* _FSL_STR_H */

FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/Projects/MCUXpresso/.cproject

@@ -0,0 +1,360 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
+	<storageModule moduleId="org.eclipse.cdt.core.settings">
+		<cconfiguration id="com.crt.advproject.config.exe.debug.1736457840">
+			<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.crt.advproject.config.exe.debug.1736457840" moduleId="org.eclipse.cdt.core.settings" name="Debug">
+				<externalSettings/>
+				<extensions>
+					<extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="org.eclipse.cdt.core.GNU_ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+					<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
+					<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
+				</extensions>
+			</storageModule>
+			<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+				<configuration artifactExtension="axf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe" cleanCommand="rm -rf" description="Debug build" errorParsers="org.eclipse.cdt.core.CWDLocator;org.eclipse.cdt.core.GmakeErrorParser;org.eclipse.cdt.core.GCCErrorParser;org.eclipse.cdt.core.GLDErrorParser;org.eclipse.cdt.core.GASErrorParser" id="com.crt.advproject.config.exe.debug.1736457840" name="Debug" parent="com.crt.advproject.config.exe.debug" postannouncebuildStep="Performing post-build steps" postbuildStep="arm-none-eabi-size &quot;${BuildArtifactFileName}&quot;; # arm-none-eabi-objcopy -v -O binary &quot;${BuildArtifactFileName}&quot; &quot;${BuildArtifactFileBaseName}.bin&quot; ; # checksum -p ${TargetChip} -d &quot;${BuildArtifactFileBaseName}.bin&quot;;  ">
+					<folderInfo id="com.crt.advproject.config.exe.debug.1736457840." name="/" resourcePath="">
+						<toolChain id="com.crt.advproject.toolchain.exe.debug.240336044" name="NXP MCU Tools" superClass="com.crt.advproject.toolchain.exe.debug">
+							<targetPlatform binaryParser="org.eclipse.cdt.core.ELF;org.eclipse.cdt.core.GNU_ELF" id="com.crt.advproject.platform.exe.debug.1779853764" name="ARM-based MCU (Debug)" superClass="com.crt.advproject.platform.exe.debug"/>
+							<builder buildPath="${workspace_loc:/FreeRTOSDemo}/Debug" id="com.crt.advproject.builder.exe.debug.1263695098" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" superClass="com.crt.advproject.builder.exe.debug"/>
+							<tool id="com.crt.advproject.cpp.exe.debug.1728072488" name="MCU C++ Compiler" superClass="com.crt.advproject.cpp.exe.debug">
+								<option id="com.crt.advproject.cpp.arch.1175296083" name="Architecture" superClass="com.crt.advproject.cpp.arch" useByScannerDiscovery="true" value="com.crt.advproject.cpp.target.cm4" valueType="enumerated"/>
+								<option id="com.crt.advproject.cpp.misc.dialect.1590244997" name="Language standard" superClass="com.crt.advproject.cpp.misc.dialect" useByScannerDiscovery="true"/>
+								<option id="gnu.cpp.compiler.option.dialect.flags.1629555862" name="Other dialect flags" superClass="gnu.cpp.compiler.option.dialect.flags" useByScannerDiscovery="true"/>
+								<option id="gnu.cpp.compiler.option.preprocessor.nostdinc.602726906" name="Do not search system directories (-nostdinc)" superClass="gnu.cpp.compiler.option.preprocessor.nostdinc" useByScannerDiscovery="false"/>
+								<option id="gnu.cpp.compiler.option.preprocessor.preprocess.1961578482" name="Preprocess only (-E)" superClass="gnu.cpp.compiler.option.preprocessor.preprocess" useByScannerDiscovery="false"/>
+								<option id="gnu.cpp.compiler.option.preprocessor.def.1002107014" name="Defined symbols (-D)" superClass="gnu.cpp.compiler.option.preprocessor.def" useByScannerDiscovery="false"/>
+								<option id="gnu.cpp.compiler.option.preprocessor.undef.638012443" name="Undefined symbols (-U)" superClass="gnu.cpp.compiler.option.preprocessor.undef" useByScannerDiscovery="false"/>
+								<option id="gnu.cpp.compiler.option.include.paths.983001089" name="Include paths (-I)" superClass="gnu.cpp.compiler.option.include.paths" useByScannerDiscovery="false"/>
+								<option id="gnu.cpp.compiler.option.include.files.804685852" name="Include files (-include)" superClass="gnu.cpp.compiler.option.include.files" useByScannerDiscovery="false"/>
+								<option id="com.crt.advproject.cpp.exe.debug.option.optimization.level.1649848490" name="Optimization Level" superClass="com.crt.advproject.cpp.exe.debug.option.optimization.level" useByScannerDiscovery="true"/>
+								<option id="gnu.cpp.compiler.option.optimization.flags.677012392" name="Other optimization flags" superClass="gnu.cpp.compiler.option.optimization.flags" useByScannerDiscovery="false" value="-fno-common" valueType="string"/>
+								<option id="com.crt.advproject.cpp.exe.debug.option.debugging.level.1417587731" name="Debug Level" superClass="com.crt.advproject.cpp.exe.debug.option.debugging.level" useByScannerDiscovery="false"/>
+								<option id="gnu.cpp.compiler.option.debugging.other.559941603" name="Other debugging flags" superClass="gnu.cpp.compiler.option.debugging.other" useByScannerDiscovery="false"/>
+								<option id="gnu.cpp.compiler.option.debugging.prof.564795725" name="Generate prof information (-p)" superClass="gnu.cpp.compiler.option.debugging.prof" useByScannerDiscovery="false"/>
+								<option id="gnu.cpp.compiler.option.debugging.gprof.815932622" name="Generate gprof information (-pg)" superClass="gnu.cpp.compiler.option.debugging.gprof" useByScannerDiscovery="false"/>
+								<option id="gnu.cpp.compiler.option.debugging.codecov.790181683" name="Generate gcov information (-ftest-coverage -fprofile-arcs)" superClass="gnu.cpp.compiler.option.debugging.codecov" useByScannerDiscovery="false"/>
+								<option id="gnu.cpp.compiler.option.warnings.syntax.88112652" name="Check syntax only (-fsyntax-only)" superClass="gnu.cpp.compiler.option.warnings.syntax" useByScannerDiscovery="false"/>
+								<option id="gnu.cpp.compiler.option.warnings.pedantic.881300834" name="Pedantic (-pedantic)" superClass="gnu.cpp.compiler.option.warnings.pedantic" useByScannerDiscovery="false"/>
+								<option id="gnu.cpp.compiler.option.warnings.pedantic.error.1725242808" name="Pedantic warnings as errors (-pedantic-errors)" superClass="gnu.cpp.compiler.option.warnings.pedantic.error" useByScannerDiscovery="false"/>
+								<option id="gnu.cpp.compiler.option.warnings.nowarn.1002132921" name="Inhibit all warnings (-w)" superClass="gnu.cpp.compiler.option.warnings.nowarn" useByScannerDiscovery="false"/>
+								<option id="gnu.cpp.compiler.option.warnings.allwarn.1620754777" name="All warnings (-Wall)" superClass="gnu.cpp.compiler.option.warnings.allwarn" useByScannerDiscovery="false"/>
+								<option id="gnu.cpp.compiler.option.warnings.extrawarn.306762746" name="Extra warnings (-Wextra)" superClass="gnu.cpp.compiler.option.warnings.extrawarn" useByScannerDiscovery="false"/>
+								<option id="gnu.cpp.compiler.option.warnings.toerrors.566950003" name="Warnings as errors (-Werror)" superClass="gnu.cpp.compiler.option.warnings.toerrors" useByScannerDiscovery="false"/>
+								<option id="gnu.cpp.compiler.option.warnings.wconversion.704369576" name="Implicit conversion warnings (-Wconversion)" superClass="gnu.cpp.compiler.option.warnings.wconversion" useByScannerDiscovery="false"/>
+								<option id="gnu.cpp.compiler.option.other.other.2132215552" name="Other flags" superClass="gnu.cpp.compiler.option.other.other" useByScannerDiscovery="false"/>
+								<option id="gnu.cpp.compiler.option.other.verbose.1872876346" name="Verbose (-v)" superClass="gnu.cpp.compiler.option.other.verbose" useByScannerDiscovery="false"/>
+								<option id="gnu.cpp.compiler.option.other.pic.1826951272" name="Position Independent Code (-fPIC)" superClass="gnu.cpp.compiler.option.other.pic" useByScannerDiscovery="false"/>
+								<option id="com.crt.advproject.cpp.lto.1861915514" name="Enable Link-time optimization (-flto)" superClass="com.crt.advproject.cpp.lto" useByScannerDiscovery="false"/>
+								<option id="com.crt.advproject.cpp.lto.fat.486980577" name="Fat lto objects (-ffat-lto-objects)" superClass="com.crt.advproject.cpp.lto.fat" useByScannerDiscovery="false"/>
+								<option id="com.crt.advproject.cpp.merge.constants.249495250" name="Merge Identical Constants (-fmerge-constants)" superClass="com.crt.advproject.cpp.merge.constants" useByScannerDiscovery="false"/>
+								<option id="com.crt.advproject.cpp.prefixmap.110171675" name="Remove path from __FILE__ (-fmacro-prefix-map)" superClass="com.crt.advproject.cpp.prefixmap" useByScannerDiscovery="false"/>
+								<option id="com.crt.advproject.cpp.fpu.1380190083" name="Floating point" superClass="com.crt.advproject.cpp.fpu" useByScannerDiscovery="true" value="com.crt.advproject.cpp.fpu.fpv4.hard" valueType="enumerated"/>
+								<option id="com.crt.advproject.cpp.thumb.87730734" name="Thumb mode" superClass="com.crt.advproject.cpp.thumb" useByScannerDiscovery="false"/>
+								<option id="com.crt.advproject.cpp.thumbinterwork.149757268" name="Enable Thumb interworking" superClass="com.crt.advproject.cpp.thumbinterwork" useByScannerDiscovery="false"/>
+								<option id="com.crt.advproject.cpp.securestate.1982530234" name="TrustZone Project Type" superClass="com.crt.advproject.cpp.securestate" useByScannerDiscovery="false"/>
+								<option id="com.crt.advproject.cpp.hdrlib.926137618" name="Library headers" superClass="com.crt.advproject.cpp.hdrlib" useByScannerDiscovery="false"/>
+								<option id="com.crt.advproject.cpp.stackusage.140442899" name="Generate Stack Usage Info (-fstack-usage)" superClass="com.crt.advproject.cpp.stackusage" useByScannerDiscovery="false"/>
+								<option id="com.crt.advproject.cpp.specs.14407963" name="Specs" superClass="com.crt.advproject.cpp.specs" useByScannerDiscovery="false"/>
+								<option id="com.crt.advproject.cpp.config.1666925" name="Obsolete (Config)" superClass="com.crt.advproject.cpp.config" useByScannerDiscovery="false"/>
+								<option id="com.crt.advproject.cpp.store.10625467" name="Obsolete (Store)" superClass="com.crt.advproject.cpp.store" useByScannerDiscovery="false"/>
+							</tool>
+							<tool id="com.crt.advproject.gcc.exe.debug.1970139153" name="MCU C Compiler" superClass="com.crt.advproject.gcc.exe.debug">
+								<option id="com.crt.advproject.gcc.thumb.1105729438" name="Thumb mode" superClass="com.crt.advproject.gcc.thumb" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								<option id="com.crt.advproject.gcc.arch.1614152875" name="Architecture" superClass="com.crt.advproject.gcc.arch" useByScannerDiscovery="true" value="com.crt.advproject.gcc.target.cm4" valueType="enumerated"/>
+								<option id="com.crt.advproject.c.misc.dialect.61301729" name="Language standard" superClass="com.crt.advproject.c.misc.dialect" useByScannerDiscovery="true" value="com.crt.advproject.misc.dialect.gnu99" valueType="enumerated"/>
+								<option id="gnu.c.compiler.option.dialect.flags.356693735" name="Other dialect flags" superClass="gnu.c.compiler.option.dialect.flags" useByScannerDiscovery="true"/>
+								<option id="gnu.c.compiler.option.preprocessor.nostdinc.221833775" name="Do not search system directories (-nostdinc)" superClass="gnu.c.compiler.option.preprocessor.nostdinc" useByScannerDiscovery="false"/>
+								<option id="gnu.c.compiler.option.preprocessor.preprocess.1943460156" name="Preprocess only (-E)" superClass="gnu.c.compiler.option.preprocessor.preprocess" useByScannerDiscovery="false"/>
+								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="gnu.c.compiler.option.preprocessor.def.symbols.581612319" name="Defined symbols (-D)" superClass="gnu.c.compiler.option.preprocessor.def.symbols" useByScannerDiscovery="false" valueType="definedSymbols">
+									<listOptionValue builtIn="false" value="CPU_LPC54018JET180=1"/>
+									<listOptionValue builtIn="false" value="CPU_LPC54018JET180_cm4"/>
+									<listOptionValue builtIn="false" value="XIP_IMAGE"/>
+									<listOptionValue builtIn="false" value="W25Q128JVFM"/>
+									<listOptionValue builtIn="false" value="CPU_LPC54018"/>
+									<listOptionValue builtIn="false" value="__USE_CMSIS"/>
+									<listOptionValue builtIn="false" value="MXL12835F"/>
+									<listOptionValue builtIn="false" value="SERIAL_PORT_TYPE_UART=1"/>
+									<listOptionValue builtIn="false" value="FSL_RTOS_FREE_RTOS"/>
+									<listOptionValue builtIn="false" value="SDK_DEBUGCONSOLE=0"/>
+									<listOptionValue builtIn="false" value="CR_INTEGER_PRINTF"/>
+									<listOptionValue builtIn="false" value="PRINTF_FLOAT_ENABLE=0"/>
+									<listOptionValue builtIn="false" value="__MCUXPRESSO"/>
+									<listOptionValue builtIn="false" value="DEBUG"/>
+									<listOptionValue builtIn="false" value="__REDLIB__"/>
+								</option>
+								<option id="gnu.c.compiler.option.preprocessor.undef.symbol.1347678265" name="Undefined symbols (-U)" superClass="gnu.c.compiler.option.preprocessor.undef.symbol" useByScannerDiscovery="false"/>
+								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="gnu.c.compiler.option.include.paths.1527135388" name="Include paths (-I)" superClass="gnu.c.compiler.option.include.paths" useByScannerDiscovery="false" valueType="includePath">
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/}&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/NXP_Code/board}&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/NXP_Code/drivers}&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/NXP_Code/device}&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/NXP_Code/CMSIS}&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/NXP_Code/utilities}&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/NXP_Code/component/serial_manager}&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/NXP_Code/component/lists}&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/NXP_Code/component/uart}&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/Config}&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/Demo}&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/FreeRTOS/include}&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/FreeRTOS/portable/GCC/ARM_CM4_MPU}&quot;"/>
+								</option>
+								<option id="gnu.c.compiler.option.include.files.1633401450" name="Include files (-include)" superClass="gnu.c.compiler.option.include.files" useByScannerDiscovery="false"/>
+								<option id="com.crt.advproject.gcc.exe.debug.option.optimization.level.1718806940" name="Optimization Level" superClass="com.crt.advproject.gcc.exe.debug.option.optimization.level" useByScannerDiscovery="true"/>
+								<option id="gnu.c.compiler.option.optimization.flags.1201874316" name="Other optimization flags" superClass="gnu.c.compiler.option.optimization.flags" useByScannerDiscovery="false" value="-fno-common" valueType="string"/>
+								<option id="com.crt.advproject.gcc.exe.debug.option.debugging.level.1042826050" name="Debug Level" superClass="com.crt.advproject.gcc.exe.debug.option.debugging.level" useByScannerDiscovery="false"/>
+								<option id="gnu.c.compiler.option.debugging.other.1014019160" name="Other debugging flags" superClass="gnu.c.compiler.option.debugging.other" useByScannerDiscovery="false"/>
+								<option id="gnu.c.compiler.option.debugging.prof.451745226" name="Generate prof information (-p)" superClass="gnu.c.compiler.option.debugging.prof" useByScannerDiscovery="false"/>
+								<option id="gnu.c.compiler.option.debugging.gprof.1439287771" name="Generate gprof information (-pg)" superClass="gnu.c.compiler.option.debugging.gprof" useByScannerDiscovery="false"/>
+								<option id="gnu.c.compiler.option.debugging.codecov.721867846" name="Generate gcov information (-ftest-coverage -fprofile-arcs)" superClass="gnu.c.compiler.option.debugging.codecov" useByScannerDiscovery="false"/>
+								<option id="gnu.c.compiler.option.warnings.syntax.187338404" name="Check syntax only (-fsyntax-only)" superClass="gnu.c.compiler.option.warnings.syntax" useByScannerDiscovery="false"/>
+								<option id="gnu.c.compiler.option.warnings.pedantic.647919284" name="Pedantic (-pedantic)" superClass="gnu.c.compiler.option.warnings.pedantic" useByScannerDiscovery="false"/>
+								<option id="gnu.c.compiler.option.warnings.pedantic.error.1676517576" name="Pedantic warnings as errors (-pedantic-errors)" superClass="gnu.c.compiler.option.warnings.pedantic.error" useByScannerDiscovery="false"/>
+								<option id="gnu.c.compiler.option.warnings.nowarn.304135482" name="Inhibit all warnings (-w)" superClass="gnu.c.compiler.option.warnings.nowarn" useByScannerDiscovery="false"/>
+								<option id="gnu.c.compiler.option.warnings.allwarn.1611226404" name="All warnings (-Wall)" superClass="gnu.c.compiler.option.warnings.allwarn" useByScannerDiscovery="false"/>
+								<option id="gnu.c.compiler.option.warnings.extrawarn.1201734336" name="Extra warnings (-Wextra)" superClass="gnu.c.compiler.option.warnings.extrawarn" useByScannerDiscovery="false"/>
+								<option id="gnu.c.compiler.option.warnings.toerrors.1850215729" name="Warnings as errors (-Werror)" superClass="gnu.c.compiler.option.warnings.toerrors" useByScannerDiscovery="false"/>
+								<option id="gnu.c.compiler.option.warnings.wconversion.2031332653" name="Implicit conversion warnings (-Wconversion)" superClass="gnu.c.compiler.option.warnings.wconversion" useByScannerDiscovery="false"/>
+								<option id="gnu.c.compiler.option.misc.other.552564654" name="Other flags" superClass="gnu.c.compiler.option.misc.other" useByScannerDiscovery="false" value="-c  -ffunction-sections  -fdata-sections  -ffreestanding  -fno-builtin" valueType="string"/>
+								<option id="gnu.c.compiler.option.misc.verbose.1861014715" name="Verbose (-v)" superClass="gnu.c.compiler.option.misc.verbose" useByScannerDiscovery="false"/>
+								<option id="gnu.c.compiler.option.misc.ansi.1425557981" name="Support ANSI programs (-ansi)" superClass="gnu.c.compiler.option.misc.ansi" useByScannerDiscovery="false"/>
+								<option id="gnu.c.compiler.option.misc.pic.1997513529" name="Position Independent Code (-fPIC)" superClass="gnu.c.compiler.option.misc.pic" useByScannerDiscovery="false"/>
+								<option id="com.crt.advproject.gcc.lto.495354563" name="Enable Link-time optimization (-flto)" superClass="com.crt.advproject.gcc.lto" useByScannerDiscovery="false"/>
+								<option id="com.crt.advproject.gcc.lto.fat.1429637975" name="Fat lto objects (-ffat-lto-objects)" superClass="com.crt.advproject.gcc.lto.fat" useByScannerDiscovery="false"/>
+								<option id="com.crt.advproject.gcc.merge.constants.2144524488" name="Merge Identical Constants (-fmerge-constants)" superClass="com.crt.advproject.gcc.merge.constants" useByScannerDiscovery="false"/>
+								<option id="com.crt.advproject.gcc.prefixmap.72414569" name="Remove path from __FILE__ (-fmacro-prefix-map)" superClass="com.crt.advproject.gcc.prefixmap" useByScannerDiscovery="false"/>
+								<option id="com.crt.advproject.gcc.fpu.574740811" name="Floating point" superClass="com.crt.advproject.gcc.fpu" useByScannerDiscovery="true" value="com.crt.advproject.gcc.fpu.fpv4.hard" valueType="enumerated"/>
+								<option id="com.crt.advproject.gcc.thumbinterwork.69036773" name="Enable Thumb interworking" superClass="com.crt.advproject.gcc.thumbinterwork" useByScannerDiscovery="false"/>
+								<option id="com.crt.advproject.gcc.securestate.718028118" name="TrustZone Project Type" superClass="com.crt.advproject.gcc.securestate" useByScannerDiscovery="false"/>
+								<option id="com.crt.advproject.gcc.hdrlib.1084824936" name="Library headers" superClass="com.crt.advproject.gcc.hdrlib" useByScannerDiscovery="false"/>
+								<option id="com.crt.advproject.gcc.stackusage.498146456" name="Generate Stack Usage Info (-fstack-usage)" superClass="com.crt.advproject.gcc.stackusage" useByScannerDiscovery="false"/>
+								<option id="com.crt.advproject.gcc.specs.1658292762" name="Specs" superClass="com.crt.advproject.gcc.specs" useByScannerDiscovery="false"/>
+								<option id="com.crt.advproject.gcc.config.1464370851" name="Obsolete (Config)" superClass="com.crt.advproject.gcc.config" useByScannerDiscovery="false"/>
+								<option id="com.crt.advproject.gcc.store.1462187297" name="Obsolete (Store)" superClass="com.crt.advproject.gcc.store" useByScannerDiscovery="false"/>
+								<inputType id="com.crt.advproject.compiler.input.376371565" superClass="com.crt.advproject.compiler.input"/>
+							</tool>
+							<tool id="com.crt.advproject.gas.exe.debug.232366964" name="MCU Assembler" superClass="com.crt.advproject.gas.exe.debug">
+								<option id="com.crt.advproject.gas.thumb.508465339" name="Thumb mode" superClass="com.crt.advproject.gas.thumb" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								<option id="com.crt.advproject.gas.arch.1442555343" name="Architecture" superClass="com.crt.advproject.gas.arch" useByScannerDiscovery="false" value="com.crt.advproject.gas.target.cm4" valueType="enumerated"/>
+								<option id="gnu.both.asm.option.flags.crt.414346265" name="Assembler flags" superClass="gnu.both.asm.option.flags.crt" useByScannerDiscovery="false" value="-c -x assembler-with-cpp -D__REDLIB__" valueType="string"/>
+								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="gnu.both.asm.option.include.paths.1198095644" name="Include paths (-I)" superClass="gnu.both.asm.option.include.paths" useByScannerDiscovery="false" valueType="includePath">
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/}&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/NXP_Code/board}&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/NXP_Code/drivers}&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/NXP_Code/device}&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/NXP_Code/CMSIS}&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/NXP_Code/utilities}&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/NXP_Code/component/serial_manager}&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/NXP_Code/component/lists}&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/NXP_Code/component/uart}&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/Config}&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/Demo}&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/FreeRTOS/include}&quot;"/>
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/FreeRTOS/portable/GCC/ARM_CM4_MPU}&quot;"/>
+								</option>
+								<option id="gnu.both.asm.option.warnings.nowarn.1118988451" name="Suppress warnings (-W)" superClass="gnu.both.asm.option.warnings.nowarn" useByScannerDiscovery="false"/>
+								<option id="gnu.both.asm.option.version.243519415" name="Announce version (-v)" superClass="gnu.both.asm.option.version" useByScannerDiscovery="false"/>
+								<option id="com.crt.advproject.gas.exe.debug.option.debugging.level.1183104583" name="Debug level" superClass="com.crt.advproject.gas.exe.debug.option.debugging.level" useByScannerDiscovery="false"/>
+								<option id="com.crt.advproject.gas.fpu.201100762" name="Floating point" superClass="com.crt.advproject.gas.fpu" useByScannerDiscovery="false" value="com.crt.advproject.gas.fpu.fpv4.hard" valueType="enumerated"/>
+								<option id="com.crt.advproject.gas.thumbinterwork.2139771195" name="Enable Thumb interworking" superClass="com.crt.advproject.gas.thumbinterwork" useByScannerDiscovery="false"/>
+								<option id="com.crt.advproject.gas.hdrlib.1781682919" name="Library headers" superClass="com.crt.advproject.gas.hdrlib" useByScannerDiscovery="false"/>
+								<option id="com.crt.advproject.gas.specs.20766936" name="Specs" superClass="com.crt.advproject.gas.specs" useByScannerDiscovery="false"/>
+								<option id="com.crt.advproject.gas.config.1936625602" name="Obsolete (Config)" superClass="com.crt.advproject.gas.config" useByScannerDiscovery="false"/>
+								<option id="com.crt.advproject.gas.store.2044928625" name="Obsolete (Store)" superClass="com.crt.advproject.gas.store" useByScannerDiscovery="false"/>
+								<inputType id="cdt.managedbuild.tool.gnu.assembler.input.518347860" superClass="cdt.managedbuild.tool.gnu.assembler.input"/>
+								<inputType id="com.crt.advproject.assembler.input.1598241085" name="Additional Assembly Source Files" superClass="com.crt.advproject.assembler.input"/>
+							</tool>
+							<tool id="com.crt.advproject.link.cpp.exe.debug.954394348" name="MCU C++ Linker" superClass="com.crt.advproject.link.cpp.exe.debug">
+								<option id="com.crt.advproject.link.cpp.arch.79930041" name="Architecture" superClass="com.crt.advproject.link.cpp.arch" value="com.crt.advproject.link.cpp.target.cm4" valueType="enumerated"/>
+								<option id="gnu.cpp.link.option.nostart.1526270418" name="Do not use standard start files (-nostartfiles)" superClass="gnu.cpp.link.option.nostart"/>
+								<option id="gnu.cpp.link.option.nodeflibs.1123106397" name="Do not use default libraries (-nodefaultlibs)" superClass="gnu.cpp.link.option.nodeflibs"/>
+								<option id="gnu.cpp.link.option.nostdlibs.1271825831" name="No startup or default libs (-nostdlib)" superClass="gnu.cpp.link.option.nostdlibs" value="true" valueType="boolean"/>
+								<option id="gnu.cpp.link.option.strip.1226567945" name="Omit all symbol information (-s)" superClass="gnu.cpp.link.option.strip"/>
+								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="gnu.cpp.link.option.libs.546881884" name="Libraries (-l)" superClass="gnu.cpp.link.option.libs" valueType="libs">
+									<listOptionValue builtIn="false" value="power_hardabi"/>
+								</option>
+								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="gnu.cpp.link.option.paths.1281361528" name="Library search path (-L)" superClass="gnu.cpp.link.option.paths" valueType="libPaths">
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/NXP_Code/libs}&quot;"/>
+								</option>
+								<option id="gnu.cpp.link.option.flags.1910216190" name="Linker flags" superClass="gnu.cpp.link.option.flags"/>
+								<option id="gnu.cpp.link.option.other.468789820" name="Other options (-Xlinker [option])" superClass="gnu.cpp.link.option.other"/>
+								<option id="gnu.cpp.link.option.userobjs.1106092448" name="Other objects" superClass="gnu.cpp.link.option.userobjs"/>
+								<option id="gnu.cpp.link.option.shared.2033156219" name="Shared (-shared)" superClass="gnu.cpp.link.option.shared"/>
+								<option id="gnu.cpp.link.option.soname.1852338686" name="Shared object name (-Wl,-soname=)" superClass="gnu.cpp.link.option.soname"/>
+								<option id="gnu.cpp.link.option.implname.1917463940" name="Import Library name (-Wl,--out-implib=)" superClass="gnu.cpp.link.option.implname"/>
+								<option id="gnu.cpp.link.option.defname.2110006287" name="DEF file name (-Wl,--output-def=)" superClass="gnu.cpp.link.option.defname"/>
+								<option id="gnu.cpp.link.option.debugging.prof.780973193" name="Generate prof information (-p)" superClass="gnu.cpp.link.option.debugging.prof"/>
+								<option id="gnu.cpp.link.option.debugging.gprof.461845632" name="Generate gprof information (-pg)" superClass="gnu.cpp.link.option.debugging.gprof"/>
+								<option id="gnu.cpp.link.option.debugging.codecov.847067807" name="Generate gcov information (-ftest-coverage -fprofile-arcs)" superClass="gnu.cpp.link.option.debugging.codecov"/>
+								<option id="com.crt.advproject.link.cpp.lto.1929871411" name="Enable Link-time optimization (-flto)" superClass="com.crt.advproject.link.cpp.lto"/>
+								<option id="com.crt.advproject.link.cpp.lto.optmization.level.1183253597" name="Link-time optimization level" superClass="com.crt.advproject.link.cpp.lto.optmization.level"/>
+								<option id="com.crt.advproject.link.cpp.fpu.1798703829" name="Floating point" superClass="com.crt.advproject.link.cpp.fpu" value="com.crt.advproject.link.cpp.fpu.fpv4.hard" valueType="enumerated"/>
+								<option id="com.crt.advproject.link.cpp.thumb.58205290" name="Thumb mode" superClass="com.crt.advproject.link.cpp.thumb"/>
+								<option id="com.crt.advproject.link.cpp.manage.17690161" name="Manage linker script" superClass="com.crt.advproject.link.cpp.manage"/>
+								<option id="com.crt.advproject.link.cpp.script.1619962145" name="Linker script" superClass="com.crt.advproject.link.cpp.script"/>
+								<option id="com.crt.advproject.link.cpp.scriptdir.83294990" name="Script path" superClass="com.crt.advproject.link.cpp.scriptdir"/>
+								<option id="com.crt.advproject.link.cpp.crpenable.1720063411" name="Enable automatic placement of Code Read Protection field in image" superClass="com.crt.advproject.link.cpp.crpenable"/>
+								<option id="com.crt.advproject.link.cpp.flashconfigenable.1416205990" name="Enable automatic placement of Flash Configuration field in image" superClass="com.crt.advproject.link.cpp.flashconfigenable" value="true" valueType="boolean"/>
+								<option id="com.crt.advproject.link.cpp.ecrp.1286282871" name="Enhanced CRP" superClass="com.crt.advproject.link.cpp.ecrp"/>
+								<option id="com.crt.advproject.link.cpp.hdrlib.1686324205" name="Library" superClass="com.crt.advproject.link.cpp.hdrlib"/>
+								<option id="com.crt.advproject.link.cpp.nanofloat.136841965" name="Enable printf float " superClass="com.crt.advproject.link.cpp.nanofloat"/>
+								<option id="com.crt.advproject.link.cpp.nanofloat.scanf.1521712693" name="Enable scanf float " superClass="com.crt.advproject.link.cpp.nanofloat.scanf"/>
+								<option id="com.crt.advproject.link.cpp.toram.1625707651" name="Link application to RAM" superClass="com.crt.advproject.link.cpp.toram"/>
+								<option id="com.crt.advproject.link.memory.load.image.cpp.1481323376" name="Plain load image" superClass="com.crt.advproject.link.memory.load.image.cpp"/>
+								<option id="com.crt.advproject.link.memory.heapAndStack.style.cpp.178619048" name="Heap and Stack placement" superClass="com.crt.advproject.link.memory.heapAndStack.style.cpp"/>
+								<option id="com.crt.advproject.link.cpp.stackOffset.971599184" name="Stack offset" superClass="com.crt.advproject.link.cpp.stackOffset"/>
+								<option id="com.crt.advproject.link.memory.heapAndStack.cpp.833529442" name="Heap and Stack options" superClass="com.crt.advproject.link.memory.heapAndStack.cpp"/>
+								<option id="com.crt.advproject.link.memory.data.cpp.1778405209" name="Global data placement" superClass="com.crt.advproject.link.memory.data.cpp"/>
+								<option id="com.crt.advproject.link.memory.sections.cpp.1993238170" name="Extra linker script input sections" superClass="com.crt.advproject.link.memory.sections.cpp"/>
+								<option id="com.crt.advproject.link.cpp.multicore.slave.2027409717" name="Multicore configuration" superClass="com.crt.advproject.link.cpp.multicore.slave"/>
+								<option id="com.crt.advproject.link.cpp.multicore.master.1488779522" name="Multicore master" superClass="com.crt.advproject.link.cpp.multicore.master"/>
+								<option id="com.crt.advproject.link.cpp.multicore.empty.861920854" name="No Multicore options for this project" superClass="com.crt.advproject.link.cpp.multicore.empty"/>
+								<option id="com.crt.advproject.link.cpp.multicore.master.userobjs.1495488545" name="Slave Objects (not visible)" superClass="com.crt.advproject.link.cpp.multicore.master.userobjs"/>
+								<option id="com.crt.advproject.link.cpp.config.926506335" name="Obsolete (Config)" superClass="com.crt.advproject.link.cpp.config"/>
+								<option id="com.crt.advproject.link.cpp.store.940562340" name="Obsolete (Store)" superClass="com.crt.advproject.link.cpp.store"/>
+								<option id="com.crt.advproject.link.cpp.securestate.769885353" name="TrustZone Project Type" superClass="com.crt.advproject.link.cpp.securestate"/>
+								<option id="com.crt.advproject.link.cpp.sgstubs.placement.875652002" name="Secure Gateway Placement" superClass="com.crt.advproject.link.cpp.sgstubs.placement"/>
+								<option id="com.crt.advproject.link.cpp.sgstubenable.992803253" name="Enable generation of Secure Gateway Import Library" superClass="com.crt.advproject.link.cpp.sgstubenable"/>
+								<option id="com.crt.advproject.link.cpp.nonsecureobject.882116138" name="Secure Gateway Import Library" superClass="com.crt.advproject.link.cpp.nonsecureobject"/>
+								<option id="com.crt.advproject.link.cpp.inimplib.1943791199" name="Input Secure Gateway Import Library" superClass="com.crt.advproject.link.cpp.inimplib"/>
+							</tool>
+							<tool id="com.crt.advproject.link.exe.debug.1377892473" name="MCU Linker" superClass="com.crt.advproject.link.exe.debug">
+								<option id="com.crt.advproject.link.thumb.1824663771" name="Thumb mode" superClass="com.crt.advproject.link.thumb" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								<option id="com.crt.advproject.link.memory.load.image.558349136" name="Plain load image" superClass="com.crt.advproject.link.memory.load.image" useByScannerDiscovery="false" value="true;SRAMX" valueType="string"/>
+								<option defaultValue="com.crt.advproject.heapAndStack.mcuXpressoStyle" id="com.crt.advproject.link.memory.heapAndStack.style.1318181182" name="Heap and Stack placement" superClass="com.crt.advproject.link.memory.heapAndStack.style" useByScannerDiscovery="false" valueType="enumerated"/>
+								<option id="com.crt.advproject.link.memory.heapAndStack.1059234943" name="Heap and Stack options" superClass="com.crt.advproject.link.memory.heapAndStack" useByScannerDiscovery="false" value="&amp;Heap:Default;Post Data;Default&amp;Stack:Default;End;Default" valueType="string"/>
+								<option id="com.crt.advproject.link.memory.data.851042339" name="Global data placement" superClass="com.crt.advproject.link.memory.data" useByScannerDiscovery="false" value="SRAM_0_1_2_3" valueType="string"/>
+								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="true" id="com.crt.advproject.link.memory.sections.30529004" name="Extra linker script input sections" superClass="com.crt.advproject.link.memory.sections" useByScannerDiscovery="false" valueType="stringList"/>
+								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="true" id="com.crt.advproject.link.gcc.multicore.master.userobjs.1457180455" name="Slave Objects (not visible)" superClass="com.crt.advproject.link.gcc.multicore.master.userobjs" useByScannerDiscovery="false" valueType="userObjs"/>
+								<option id="com.crt.advproject.link.arch.302870297" name="Architecture" superClass="com.crt.advproject.link.arch" useByScannerDiscovery="false" value="com.crt.advproject.link.target.cm4" valueType="enumerated"/>
+								<option id="gnu.c.link.option.nostart.130997344" name="Do not use standard start files (-nostartfiles)" superClass="gnu.c.link.option.nostart" useByScannerDiscovery="false"/>
+								<option id="gnu.c.link.option.nodeflibs.513286166" name="Do not use default libraries (-nodefaultlibs)" superClass="gnu.c.link.option.nodeflibs" useByScannerDiscovery="false"/>
+								<option id="gnu.c.link.option.nostdlibs.184113888" name="No startup or default libs (-nostdlib)" superClass="gnu.c.link.option.nostdlibs" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								<option id="gnu.c.link.option.strip.1699207811" name="Omit all symbol information (-s)" superClass="gnu.c.link.option.strip" useByScannerDiscovery="false"/>
+								<option id="gnu.c.link.option.noshared.1811362499" name="No shared libraries (-static)" superClass="gnu.c.link.option.noshared" useByScannerDiscovery="false"/>
+								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="gnu.c.link.option.libs.1319534926" name="Libraries (-l)" superClass="gnu.c.link.option.libs" useByScannerDiscovery="false" valueType="libs">
+									<listOptionValue builtIn="false" value="power_hardabi"/>
+								</option>
+								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="gnu.c.link.option.paths.718525159" name="Library search path (-L)" superClass="gnu.c.link.option.paths" useByScannerDiscovery="false" valueType="libPaths">
+									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/NXP_Code/libs}&quot;"/>
+								</option>
+								<option id="gnu.c.link.option.ldflags.760660943" name="Linker flags" superClass="gnu.c.link.option.ldflags" useByScannerDiscovery="false"/>
+								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="gnu.c.link.option.other.719404017" name="Other options (-Xlinker [option])" superClass="gnu.c.link.option.other" useByScannerDiscovery="false" valueType="stringList">
+									<listOptionValue builtIn="false" value="-Map=&quot;${BuildArtifactFileBaseName}.map&quot;"/>
+									<listOptionValue builtIn="false" value="--gc-sections"/>
+									<listOptionValue builtIn="false" value="-print-memory-usage"/>
+									<listOptionValue builtIn="false" value="--sort-section=alignment"/>
+									<listOptionValue builtIn="false" value="--cref"/>
+								</option>
+								<option id="gnu.c.link.option.userobjs.1411804971" name="Other objects" superClass="gnu.c.link.option.userobjs" useByScannerDiscovery="false"/>
+								<option id="gnu.c.link.option.shared.1311734214" name="Shared (-shared)" superClass="gnu.c.link.option.shared" useByScannerDiscovery="false"/>
+								<option id="gnu.c.link.option.soname.1154964079" name="Shared object name (-Wl,-soname=)" superClass="gnu.c.link.option.soname" useByScannerDiscovery="false"/>
+								<option id="gnu.c.link.option.implname.1486483013" name="Import Library name (-Wl,--out-implib=)" superClass="gnu.c.link.option.implname" useByScannerDiscovery="false"/>
+								<option id="gnu.c.link.option.defname.804399135" name="DEF file name (-Wl,--output-def=)" superClass="gnu.c.link.option.defname" useByScannerDiscovery="false"/>
+								<option id="gnu.c.link.option.debugging.prof.699682390" name="Generate prof information (-p)" superClass="gnu.c.link.option.debugging.prof" useByScannerDiscovery="false"/>
+								<option id="gnu.c.link.option.debugging.gprof.1465979208" name="Generate gprof information (-pg)" superClass="gnu.c.link.option.debugging.gprof" useByScannerDiscovery="false"/>
+								<option id="gnu.c.link.option.debugging.codecov.1165703681" name="Generate gcov information (-ftest-coverage -fprofile-arcs)" superClass="gnu.c.link.option.debugging.codecov" useByScannerDiscovery="false"/>
+								<option id="com.crt.advproject.link.gcc.lto.128207414" name="Enable Link-time optimization (-flto)" superClass="com.crt.advproject.link.gcc.lto" useByScannerDiscovery="false"/>
+								<option id="com.crt.advproject.link.gcc.lto.optmization.level.2050759852" name="Link-time optimization level" superClass="com.crt.advproject.link.gcc.lto.optmization.level" useByScannerDiscovery="false"/>
+								<option id="com.crt.advproject.link.fpu.1624232115" name="Floating point" superClass="com.crt.advproject.link.fpu" useByScannerDiscovery="false" value="com.crt.advproject.link.fpu.fpv4.hard" valueType="enumerated"/>
+								<option id="com.crt.advproject.link.manage.1883987729" name="Manage linker script" superClass="com.crt.advproject.link.manage" useByScannerDiscovery="false" value="false" valueType="boolean"/>
+								<option id="com.crt.advproject.link.script.1712620045" name="Linker script" superClass="com.crt.advproject.link.script" useByScannerDiscovery="false" value="FreeRTOSDemo.ld" valueType="string"/>
+								<option id="com.crt.advproject.link.scriptdir.1776047271" name="Script path" superClass="com.crt.advproject.link.scriptdir" useByScannerDiscovery="false" value="../" valueType="string"/>
+								<option id="com.crt.advproject.link.crpenable.454979384" name="Enable automatic placement of Code Read Protection field in image" superClass="com.crt.advproject.link.crpenable" useByScannerDiscovery="false"/>
+								<option id="com.crt.advproject.link.flashconfigenable.1315063676" name="Enable automatic placement of Flash Configuration field in image" superClass="com.crt.advproject.link.flashconfigenable" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								<option id="com.crt.advproject.link.ecrp.1292274236" name="Enhanced CRP" superClass="com.crt.advproject.link.ecrp" useByScannerDiscovery="false"/>
+								<option id="com.crt.advproject.link.gcc.hdrlib.959913482" name="Library" superClass="com.crt.advproject.link.gcc.hdrlib" useByScannerDiscovery="false" value="com.crt.advproject.gcc.link.hdrlib.codered.semihost_nf" valueType="enumerated"/>
+								<option id="com.crt.advproject.link.gcc.nanofloat.107690637" name="Enable printf float " superClass="com.crt.advproject.link.gcc.nanofloat" useByScannerDiscovery="false"/>
+								<option id="com.crt.advproject.link.gcc.nanofloat.scanf.1889181136" name="Enable scanf float " superClass="com.crt.advproject.link.gcc.nanofloat.scanf" useByScannerDiscovery="false"/>
+								<option id="com.crt.advproject.link.toram.454075824" name="Link application to RAM" superClass="com.crt.advproject.link.toram" useByScannerDiscovery="false"/>
+								<option id="com.crt.advproject.link.stackOffset.380466158" name="Stack offset" superClass="com.crt.advproject.link.stackOffset" useByScannerDiscovery="false"/>
+								<option id="com.crt.advproject.link.gcc.multicore.slave.529501453" name="Multicore configuration" superClass="com.crt.advproject.link.gcc.multicore.slave" useByScannerDiscovery="false"/>
+								<option id="com.crt.advproject.link.gcc.multicore.master.292232186" name="Multicore master" superClass="com.crt.advproject.link.gcc.multicore.master" useByScannerDiscovery="false"/>
+								<option id="com.crt.advproject.link.gcc.multicore.empty.965063611" name="No Multicore options for this project" superClass="com.crt.advproject.link.gcc.multicore.empty" useByScannerDiscovery="false"/>
+								<option id="com.crt.advproject.link.config.1081721194" name="Obsolete (Config)" superClass="com.crt.advproject.link.config" useByScannerDiscovery="false"/>
+								<option id="com.crt.advproject.link.store.1571893346" name="Obsolete (Store)" superClass="com.crt.advproject.link.store" useByScannerDiscovery="false"/>
+								<option id="com.crt.advproject.link.securestate.1516768621" name="TrustZone Project Type" superClass="com.crt.advproject.link.securestate" useByScannerDiscovery="false"/>
+								<option id="com.crt.advproject.link.sgstubs.placement.185951968" name="Secure Gateway Placement" superClass="com.crt.advproject.link.sgstubs.placement" useByScannerDiscovery="false"/>
+								<option id="com.crt.advproject.link.sgstubenable.1797053478" name="Enable generation of Secure Gateway Import Library" superClass="com.crt.advproject.link.sgstubenable" useByScannerDiscovery="false"/>
+								<option id="com.crt.advproject.link.nonsecureobject.1171352109" name="Secure Gateway Import Library" superClass="com.crt.advproject.link.nonsecureobject" useByScannerDiscovery="false"/>
+								<option id="com.crt.advproject.link.inimplib.810999894" name="Input Secure Gateway Import Library" superClass="com.crt.advproject.link.inimplib" useByScannerDiscovery="false"/>
+								<inputType id="cdt.managedbuild.tool.gnu.c.linker.input.1748396116" superClass="cdt.managedbuild.tool.gnu.c.linker.input">
+									<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
+									<additionalInput kind="additionalinput" paths="$(LIBS)"/>
+								</inputType>
+							</tool>
+							<tool id="com.crt.advproject.tool.debug.debug.1356436549" name="MCU Debugger" superClass="com.crt.advproject.tool.debug.debug">
+								<option id="com.crt.advproject.linkserver.debug.prevent.debug.1251553097" name="Prevent Debugging" superClass="com.crt.advproject.linkserver.debug.prevent.debug" useByScannerDiscovery="false"/>
+								<option id="com.crt.advproject.miscellaneous.end_of_heap.586705874" name="Last used address of the heap" superClass="com.crt.advproject.miscellaneous.end_of_heap" useByScannerDiscovery="false"/>
+								<option id="com.crt.advproject.miscellaneous.pvHeapStart.24161347" name="First address of the heap" superClass="com.crt.advproject.miscellaneous.pvHeapStart" useByScannerDiscovery="false"/>
+								<option id="com.crt.advproject.miscellaneous.pvHeapLimit.1198762046" name="Maximum extent of heap" superClass="com.crt.advproject.miscellaneous.pvHeapLimit" useByScannerDiscovery="false"/>
+								<option id="com.crt.advproject.debugger.security.nonsecureimageenable.526210663" name="Enable pre-programming of Non-Secure Image" superClass="com.crt.advproject.debugger.security.nonsecureimageenable" useByScannerDiscovery="false"/>
+								<option id="com.crt.advproject.debugger.security.nonsecureimage.1974267144" name="Non-Secure Project" superClass="com.crt.advproject.debugger.security.nonsecureimage" useByScannerDiscovery="false"/>
+							</tool>
+						</toolChain>
+					</folderInfo>
+				</configuration>
+			</storageModule>
+			<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+		</cconfiguration>
+	</storageModule>
+	<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+		<project id="FreeRTOSDemo.null.1072149409" name="FreeRTOSDemo" projectType="com.crt.advproject.projecttype.exe"/>
+	</storageModule>
+	<storageModule moduleId="scannerConfiguration">
+		<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		<scannerConfigBuildInfo instanceId="com.crt.advproject.config.exe.debug.1736457840;com.crt.advproject.config.exe.debug.1736457840.;com.crt.advproject.gas.exe.debug.232366964;com.crt.advproject.assembler.input.1598241085">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		</scannerConfigBuildInfo>
+		<scannerConfigBuildInfo instanceId="com.crt.advproject.config.exe.debug.1736457840;com.crt.advproject.config.exe.debug.1736457840.;com.crt.advproject.gcc.exe.debug.1970139153;com.crt.advproject.compiler.input.376371565">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		</scannerConfigBuildInfo>
+		<scannerConfigBuildInfo instanceId="com.crt.advproject.config.exe.release.1833812586;com.crt.advproject.config.exe.release.1833812586.;com.crt.advproject.gas.exe.release.1656888725;com.crt.advproject.assembler.input.1464252272">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		</scannerConfigBuildInfo>
+		<scannerConfigBuildInfo instanceId="com.crt.advproject.config.exe.release.1833812586;com.crt.advproject.config.exe.release.1833812586.;com.crt.advproject.gcc.exe.release.1615587634;com.crt.advproject.compiler.input.254355885">
+			<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
+		</scannerConfigBuildInfo>
+	</storageModule>
+	<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
+	<storageModule moduleId="com.nxp.mcuxpresso.core.datamodels">
+		<sdkName>SDK_2.x_LPC54018-IoT-Module</sdkName>
+		<sdkExample>lpc54018iotmodule_freertos_hello</sdkExample>
+		<sdkVersion>2.7.0</sdkVersion>
+		<sdkComponents>platform.drivers.clock.LPC54018;platform.drivers.power.LPC54018;platform.drivers.common.LPC54018;device.LPC54018_CMSIS.LPC54018;platform.Include_core_cm4.LPC54018;platform.Include_common.LPC54018;platform.Include_dsp.LPC54018;platform.drivers.reset.LPC54018;middleware.amazon_freertos-kernel.heap_4.LPC54018;middleware.amazon_freertos-kernel.LPC54018;middleware.amazon_freertos-kernel.extension.LPC54018;utility.debug_console.LPC54018;component.serial_manager.LPC54018;component.lists.LPC54018;component.usart_adapter.LPC54018;platform.drivers.flexcomm_usart.LPC54018;platform.drivers.flexcomm.LPC54018;component.serial_manager_uart.LPC54018;device.LPC54018_startup.LPC54018;platform.drivers.lpc_iocon.LPC54018;platform.drivers.lpc_gpio.LPC54018;platform.drivers.emc.LPC54018;platform.utilities.assert.LPC54018;platform.utilities.misc_utilities.LPC54018;lpc54018iotmodule_freertos_hello;</sdkComponents>
+		<boardId>lpc54018iotmodule</boardId>
+		<package>LPC54018JET180</package>
+		<core>cm4</core>
+		<coreId>core0_LPC54018</coreId>
+	</storageModule>
+	<storageModule moduleId="com.crt.config">
+		<projectStorage>&lt;?xml version="1.0" encoding="UTF-8"?&gt;&#13;
+&lt;TargetConfig&gt;&#13;
+&lt;Properties property_3="NXP" property_4="LPC54018" property_count="5" version="100300"/&gt;&#13;
+&lt;infoList vendor="NXP"&gt;&#13;
+&lt;info chip="LPC54018" name="LPC54018"&gt;&#13;
+&lt;chip&gt;&#13;
+&lt;name&gt;LPC54018&lt;/name&gt;&#13;
+&lt;family&gt;LPC540xx&lt;/family&gt;&#13;
+&lt;vendor&gt;NXP&lt;/vendor&gt;&#13;
+&lt;memory can_program="true" id="Flash" is_ro="true" size="0" type="Flash"/&gt;&#13;
+&lt;memory id="RAM" size="352" type="RAM"/&gt;&#13;
+&lt;memoryInstance derived_from="Flash" driver="LPC540xx_SPIFI_SFDP.cfx" edited="true" id="BOARD_FLASH" location="0x10000000" size="0x1000000"/&gt;&#13;
+&lt;memoryInstance derived_from="RAM" edited="true" id="SRAMX" location="0x0" size="0x30000"/&gt;&#13;
+&lt;memoryInstance derived_from="RAM" edited="true" id="SRAM_0_1_2_3" location="0x20000000" size="0x28000"/&gt;&#13;
+&lt;memoryInstance derived_from="RAM" edited="true" id="USB_RAM" location="0x40100000" size="0x2000"/&gt;&#13;
+&lt;/chip&gt;&#13;
+&lt;processor&gt;&#13;
+&lt;name gcc_name="cortex-m4"&gt;Cortex-M4&lt;/name&gt;&#13;
+&lt;family&gt;Cortex-M&lt;/family&gt;&#13;
+&lt;/processor&gt;&#13;
+&lt;/info&gt;&#13;
+&lt;/infoList&gt;&#13;
+&lt;/TargetConfig&gt;</projectStorage>
+	</storageModule>
+	<storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
+	<storageModule moduleId="refreshScope"/>
+</cproject>

FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/Projects/MCUXpresso/.project

@@ -0,0 +1,102 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>FreeRTOSDemo</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.xtext.ui.shared.xtextBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<triggers>clean,full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<triggers>full,incremental,</triggers>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>com.nxp.mcuxpresso.core.datamodels.sdkNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+		<nature>org.eclipse.xtext.ui.shared.xtextNature</nature>
+	</natures>
+	<linkedResources>
+		<link>
+			<name>Config</name>
+			<type>2</type>
+			<locationURI>PARENT-2-PROJECT_LOC/Config</locationURI>
+		</link>
+		<link>
+			<name>Demo</name>
+			<type>2</type>
+			<locationURI>PARENT-2-PROJECT_LOC/Demo</locationURI>
+		</link>
+		<link>
+			<name>FreeRTOS</name>
+			<type>2</type>
+			<locationURI>PARENT-4-PROJECT_LOC/Source</locationURI>
+		</link>
+		<link>
+			<name>NXP_Code</name>
+			<type>2</type>
+			<locationURI>PARENT-2-PROJECT_LOC/NXP_Code</locationURI>
+		</link>
+	</linkedResources>
+	<filteredResources>
+		<filter>
+			<id>1578832143838</id>
+			<name>FreeRTOS/portable</name>
+			<type>9</type>
+			<matcher>
+				<id>org.eclipse.ui.ide.multiFilter</id>
+				<arguments>1.0-name-matches-false-false-GCC</arguments>
+			</matcher>
+		</filter>
+		<filter>
+			<id>1578832143844</id>
+			<name>FreeRTOS/portable</name>
+			<type>9</type>
+			<matcher>
+				<id>org.eclipse.ui.ide.multiFilter</id>
+				<arguments>1.0-name-matches-false-false-MemMang</arguments>
+			</matcher>
+		</filter>
+		<filter>
+			<id>1578832143849</id>
+			<name>FreeRTOS/portable</name>
+			<type>9</type>
+			<matcher>
+				<id>org.eclipse.ui.ide.multiFilter</id>
+				<arguments>1.0-name-matches-false-false-Common</arguments>
+			</matcher>
+		</filter>
+		<filter>
+			<id>1578832168749</id>
+			<name>FreeRTOS/portable/GCC</name>
+			<type>9</type>
+			<matcher>
+				<id>org.eclipse.ui.ide.multiFilter</id>
+				<arguments>1.0-name-matches-false-false-ARM_CM4_MPU</arguments>
+			</matcher>
+		</filter>
+		<filter>
+			<id>1578832213951</id>
+			<name>FreeRTOS/portable/MemMang</name>
+			<type>5</type>
+			<matcher>
+				<id>org.eclipse.ui.ide.multiFilter</id>
+				<arguments>1.0-name-matches-false-false-heap_4.c</arguments>
+			</matcher>
+		</filter>
+	</filteredResources>
+</projectDescription>

FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/Projects/MCUXpresso/FreeRTOSDemo.ld

@@ -0,0 +1,362 @@
+GROUP (
+  "libcr_semihost_nf.a"
+  "libcr_c.a"
+  "libcr_eabihelpers.a"
+  "libgcc.a"
+)
+
+/*
+ *   LPC54018 does not execute from Flash but from RAM (SRAMX). As a result, the
+ *   MPU needs to be programmed to set the portion of SRAMX containing kernel
+ *   code as privileged Read Only and the portion of SRAMX containing remaining
+ *   of the code as Read Only. To facilitate this, SRAMX is divided into two
+ *   parts:
+ *       1. SRAMX_CODE - 128KB. Contains code.
+ *       2. SRAMX_DATA - 64 KB. Contains data (only stack and heap as of now).
+ *
+ *   SRAM_0_1_2_3 is of size 160 KB which is not a power of 2. ARM v7 MPU requires
+ *   the size of an MPU region to be a power of two. Since FreeRTOS Cortex M4 MPU
+ *   port programs MPU to grant access to all SRAM (for tasks created using
+ *   xTaskCreate), we need to ensure that the size of SRAM region is a power of
+ *   two. This is why SRAM_0_1_2_3 is divided into two parts:
+ *       1. SRAM_0_1_2_3 - 128 KB. Contains data. Since the size is now a power
+ *          of two, an MPU region can be used to grant access to it.
+ *       2. SRAM_0_1_2_3_UNUSED - 32 KB. Unused.
+ */
+MEMORY
+{
+    /* Define each memory region. */
+    BOARD_FLASH (rx)            : ORIGIN = 0x10000000, LENGTH = 0x1000000 /* 16M bytes (alias Flash). */
+    SRAMX_CODE (rwx)            : ORIGIN = 0x0,        LENGTH = 0x20000   /* 128K bytes. */
+    SRAMX_DATA (rwx)            : ORIGIN = 0x20000,    LENGTH = 0x10000   /* 64K bytes (alias RAM). */
+    SRAM_0_1_2_3 (rwx)          : ORIGIN = 0x20000000, LENGTH = 0x20000   /* 128K bytes (alias RAM2). */
+    SRAM_0_1_2_3_UNUSED (rwx)   : ORIGIN = 0x20020000, LENGTH = 0x8000    /* 32K bytes. */
+    USB_RAM (rwx)               : ORIGIN = 0x40100000, LENGTH = 0x2000    /* 8K bytes (alias RAM3). */
+}
+
+/* Initial 32K SRAMX_CODE is used to store kernel functions and
+ * initial 512 bytes of SRAM_0_1_2_3 is used to store kernel data. */
+__privileged_functions_region_size__  = 32K;
+__privileged_data_region_size__       = 512;
+
+/* Symbols needed by the MPU setup code. */
+__FLASH_segment_start__ = ORIGIN( SRAMX_CODE );
+__FLASH_segment_end__   = __FLASH_segment_start__ + LENGTH( SRAMX_CODE );
+__SRAM_segment_start__  = ORIGIN( SRAM_0_1_2_3 );
+__SRAM_segment_end__    = __SRAM_segment_start__ + LENGTH( SRAM_0_1_2_3 );
+
+/* Entry point. */
+ENTRY(ResetISR)
+
+/* Sections. */
+SECTIONS
+{
+    /* The startup code and FreeRTOS kernel code are placed at the beginning
+     * of SRAMX_CODE. */
+    .privileged_functions : ALIGN(4)
+    {
+        FILL(0xff)
+        __vectors_start__ = ABSOLUTE(.);
+        __FLASH_segment_start__ = __vectors_start__;
+        __privileged_functions_start__ = __vectors_start__;
+        KEEP(*(.isr_vector))
+
+        /* Global Section Table. */
+        . = ALIGN(4);
+        __section_table_start = .;
+
+        __data_section_table = .;
+        LONG((LOADADDR(.data_RAM) - LOADADDR(.privileged_functions)) + ORIGIN(SRAMX_CODE));
+        LONG(     ADDR(.data_RAM));
+        LONG(   SIZEOF(.data_RAM));
+
+        LONG((LOADADDR(.data) - LOADADDR(.privileged_functions)) + ORIGIN(SRAMX_CODE));
+        LONG(     ADDR(.data));
+        LONG(   SIZEOF(.data));
+
+        LONG((LOADADDR(.data_RAM3) - LOADADDR(.privileged_functions)) + ORIGIN(SRAMX_CODE));
+        LONG(     ADDR(.data_RAM3));
+        LONG(   SIZEOF(.data_RAM3));
+        __data_section_table_end = .;
+
+        __bss_section_table = .;
+        LONG(    ADDR(.bss_RAM));
+        LONG(  SIZEOF(.bss_RAM));
+
+        LONG(    ADDR(.bss));
+        LONG(  SIZEOF(.bss));
+
+        LONG(    ADDR(.bss_RAM3));
+        LONG(  SIZEOF(.bss_RAM3));
+        __bss_section_table_end = .;
+
+        __section_table_end = .;
+        /* End of Global Section Table. */
+
+        /* Functions placed after vector table. */
+        *(.after_vectors*)
+
+        /* Kernel code. */
+        *(privileged_functions)
+
+        FILL(0xDEAD);
+        /* Ensure that non-privileged code is placed after the region reserved for
+         * privileged kernel code. */
+        /* Note that dot (.) actually refers to the byte offset from the start of
+         * the current section (.privileged_functions in this case). As a result,
+         * setting dot (.) to a value sets the size of the section. */
+        . = __privileged_functions_region_size__;
+        __privileged_functions_end__ = .;
+    } > SRAMX_CODE AT> BOARD_FLASH
+
+    /* Text Section. */
+    .text : ALIGN(4)
+    {
+        /* Place the FreeRTOS System Calls first in the unprivileged region. */
+        __syscalls_flash_start__ = .;
+        *(freertos_system_calls)
+        __syscalls_flash_end__ = .;
+
+        /* Unprivileged code and RO data. */
+       *(.text*)
+        KEEP(*freertos*/tasks.o(.rodata*)) /* FreeRTOS Debug Config. */
+       *(.rodata .rodata.* .constdata .constdata.*)
+       . = ALIGN(4);
+    } > SRAMX_CODE AT> BOARD_FLASH
+
+    /* For exception handling/unwind - some Newlib functions (in common
+     * with C++ and STDC++) use this. */
+    .ARM.extab : ALIGN(4)
+    {
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+    } > SRAMX_CODE AT> BOARD_FLASH
+
+    __exidx_start = .;
+
+    .ARM.exidx : ALIGN(4)
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > SRAMX_CODE AT> BOARD_FLASH
+
+    __exidx_end = .;
+
+    /* End of text section. */
+    _etext = .;
+
+    /* USB_RAM. */
+    .m_usb_data (NOLOAD) :
+    {
+        *(m_usb_global)
+    } > USB_RAM AT> USB_RAM
+
+    /* Data section for SRAMX_DATA. */
+    .data_RAM : ALIGN(4)
+    {
+        FILL(0xff)
+        PROVIDE(__start_data_RAM = .);
+        PROVIDE(__start_data_SRAMX_DATA = .);
+        *(.ramfunc.$RAM)
+        *(.ramfunc.$SRAMX)
+        *(.data.$RAM)
+        *(.data.$SRAMX)
+        *(.data.$RAM.*)
+        *(.data.$SRAMX.*)
+        . = ALIGN(4);
+        PROVIDE(__end_data_RAM = .);
+        PROVIDE(__end_data_SRAMX_DATA = .);
+    } > SRAMX_DATA AT>BOARD_FLASH
+
+    /* Data section for USB_RAM. */
+    .data_RAM3 : ALIGN(4)
+    {
+        FILL(0xff)
+        PROVIDE(__start_data_RAM3 = .);
+        PROVIDE(__start_data_USB_RAM = .);
+        *(.ramfunc.$RAM3)
+        *(.ramfunc.$USB_RAM)
+        *(.data.$RAM3)
+        *(.data.$USB_RAM)
+        *(.data.$RAM3.*)
+        *(.data.$USB_RAM.*)
+        . = ALIGN(4);
+        PROVIDE(__end_data_RAM3 = .);
+        PROVIDE(__end_data_USB_RAM = .);
+     } > USB_RAM AT>BOARD_FLASH
+
+    /* Main Data Section - Reserved. */
+    .uninit_RESERVED (NOLOAD) : ALIGN(4)
+    {
+        _start_uninit_RESERVED = .;
+        __privileged_data_start__ = _start_uninit_RESERVED;
+
+        KEEP(*(.bss.$RESERVED*))
+       . = ALIGN(4);
+
+        _end_uninit_RESERVED = .;
+    } > SRAM_0_1_2_3 AT> SRAM_0_1_2_3
+
+    /* Main DATA section (SRAM_0_1_2_3). */
+    .data : ALIGN(4)
+    {
+        _data = .;
+        PROVIDE(__start_data_RAM2 = .);
+        PROVIDE(__start_data_SRAM_0_1_2_3 = .);
+
+        /* FreeRTOS kernel data. */
+        *(privileged_data)
+        FILL(0xDEAD);
+        /* Ensure that non-privileged data is placed after the region reserved for
+         * privileged kernel data. */
+        /* Note that dot (.) actually refers to the byte offset from the start of
+         * the current section (.data in this case). As a result, setting
+         * dot (.) to a value extends the size of the section. */
+        . = __privileged_data_region_size__;
+        __privileged_data_end__ = .;
+
+        FILL(0xff)
+        *(vtable)
+        *(.ramfunc*)
+        KEEP(*(CodeQuickAccess))
+        KEEP(*(DataQuickAccess))
+        *(RamFunction)
+        *(.data*)
+        . = ALIGN(4);
+        _edata = .;
+        PROVIDE(__end_data_RAM2 = .);
+        PROVIDE(__end_data_SRAM_0_1_2_3 = .);
+    } > SRAM_0_1_2_3 AT>BOARD_FLASH
+
+    /* BSS section for SRAMX_DATA. */
+    .bss_RAM : ALIGN(4)
+    {
+        PROVIDE(__start_bss_RAM = .);
+        PROVIDE(__start_bss_SRAMX_DATA = .);
+        *(.bss.$RAM)
+        *(.bss.$SRAMX)
+        *(.bss.$RAM.*)
+        *(.bss.$SRAMX.*)
+        . = ALIGN (. != 0 ? 4 : 1); /* Avoid empty segment. */
+        PROVIDE(__end_bss_RAM = .);
+        PROVIDE(__end_bss_SRAMX_DATA = .);
+    } > SRAMX_DATA AT> SRAMX_DATA
+
+    /* BSS section for USB_RAM. */
+    .bss_RAM3 : ALIGN(4)
+    {
+        PROVIDE(__start_bss_RAM3 = .);
+        PROVIDE(__start_bss_USB_RAM = .);
+        *(.bss.$RAM3)
+        *(.bss.$USB_RAM)
+        *(.bss.$RAM3.*)
+        *(.bss.$USB_RAM.*)
+        . = ALIGN (. != 0 ? 4 : 1); /* Avoid empty segment. */
+        PROVIDE(__end_bss_RAM3 = .);
+        PROVIDE(__end_bss_USB_RAM = .);
+    } > USB_RAM AT> USB_RAM
+
+    /* Main BSS Section. */
+    .bss : ALIGN(4)
+    {
+        _bss = .;
+        PROVIDE(__start_bss_RAM2 = .);
+        PROVIDE(__start_bss_SRAM_0_1_2_3 = .);
+        *(.bss*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = .;
+        PROVIDE(__end_bss_RAM2 = .);
+        PROVIDE(__end_bss_SRAM_0_1_2_3 = .);
+        PROVIDE(end = .);
+    } > SRAM_0_1_2_3 AT> SRAM_0_1_2_3
+
+    /* NOINIT section for SRAMX_DATA. */
+    .noinit_RAM (NOLOAD) : ALIGN(4)
+    {
+        PROVIDE(__start_noinit_RAM = .);
+        PROVIDE(__start_noinit_SRAMX_DATA = .);
+        *(.noinit.$RAM)
+        *(.noinit.$SRAMX)
+        *(.noinit.$RAM.*)
+        *(.noinit.$SRAMX.*)
+        . = ALIGN(4);
+        PROVIDE(__end_noinit_RAM = .);
+        PROVIDE(__end_noinit_SRAMX_DATA = .);
+    } > SRAMX_DATA AT> SRAMX_DATA
+
+    /* NOINIT section for USB_RAM. */
+    .noinit_RAM3 (NOLOAD) : ALIGN(4)
+    {
+        PROVIDE(__start_noinit_RAM3 = .);
+        PROVIDE(__start_noinit_USB_RAM = .);
+        *(.noinit.$RAM3)
+        *(.noinit.$USB_RAM)
+        *(.noinit.$RAM3.*)
+        *(.noinit.$USB_RAM.*)
+        . = ALIGN(4);
+        PROVIDE(__end_noinit_RAM3 = .);
+        PROVIDE(__end_noinit_USB_RAM = .);
+    } > USB_RAM AT> USB_RAM
+
+    /* Default NOINIT Section. */
+    .noinit (NOLOAD): ALIGN(4)
+    {
+        _noinit = .;
+        PROVIDE(__start_noinit_RAM2 = .);
+        PROVIDE(__start_noinit_SRAM_0_1_2_3 = .);
+        *(.noinit*)
+         . = ALIGN(4);
+        _end_noinit = .;
+       PROVIDE(__end_noinit_RAM2 = .);
+       PROVIDE(__end_noinit_SRAM_0_1_2_3 = .);
+    } > SRAM_0_1_2_3 AT> SRAM_0_1_2_3
+
+    /* Reserve and place Heap within memory map. */
+    _HeapSize = 0x1000;
+    .heap : ALIGN(4)
+    {
+        _pvHeapStart = .;
+        . += _HeapSize;
+        . = ALIGN(4);
+        _pvHeapLimit = .;
+    } > SRAMX_DATA
+
+     /* Reserve space in memory for Stack. */
+     _StackSize = 0x1000;
+    .heap2stackfill  :
+    {
+        . += _StackSize;
+    } > SRAMX_DATA
+
+    /* Locate actual Stack in memory map. */
+    .stack ORIGIN(SRAMX_DATA) + LENGTH(SRAMX_DATA) - _StackSize - 0:  ALIGN(4)
+    {
+        _vStackBase = .;
+        . = ALIGN(4);
+        _vStackTop = . + _StackSize;
+    } > SRAMX_DATA
+
+    /* ## Create checksum value (used in startup). ## */
+    PROVIDE(__valid_user_code_checksum = 0 -
+                                         (_vStackTop
+                                         + (ResetISR + 1)
+                                         + (NMI_Handler + 1)
+                                         + (HardFault_Handler + 1)
+                                         + (( DEFINED(MemManage_Handler) ? MemManage_Handler : 0 ) + 1)   /* MemManage_Handler may not be defined. */
+                                         + (( DEFINED(BusFault_Handler) ? BusFault_Handler : 0 ) + 1)     /* BusFault_Handler may not be defined. */
+                                         + (( DEFINED(UsageFault_Handler) ? UsageFault_Handler : 0 ) + 1) /* UsageFault_Handler may not be defined. */
+                                         ) );
+
+    /* Provide basic symbols giving location and size of main text
+     * block, including initial values of RW data sections. Note that
+     * these will need extending to give a complete picture with
+     * complex images (e.g multiple Flash banks). */
+    _image_start = LOADADDR(.privileged_functions);
+    _image_end = LOADADDR(.data) + SIZEOF(.data);
+    _image_size = _image_end - _image_start;
+
+    /* Provide symbols for LPC540xx parts for startup code to use
+     * to set image to be plain load image or XIP.
+     * Config : Plain load image = true. */
+    __imghdr_loadaddress = ADDR(.privileged_functions);
+    __imghdr_imagetype = 1;
+}

FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/Projects/MCUXpresso/Startup/memfault_handler.c

@@ -0,0 +1,48 @@
+/*
+ * FreeRTOS Kernel V10.2.1
+ * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * http://www.FreeRTOS.org
+ * http://aws.amazon.com/freertos
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/**
+ * @brief Mem fault handler.
+ */
+void MemManage_Handler( void ) __attribute__ (( naked ));
+/*-----------------------------------------------------------*/
+
+void MemManage_Handler( void )
+{
+	__asm volatile
+	(
+		" tst lr, #4										\n"
+		" ite eq											\n"
+		" mrseq r0, msp										\n"
+		" mrsne r0, psp										\n"
+		" ldr r1, handler_address_const						\n"
+		" bx r1												\n"
+		"													\n"
+		" handler_address_const: .word vHandleMemoryFault	\n"
+	);
+}
+/*-----------------------------------------------------------*/

FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/Projects/MCUXpresso/Startup/semihost_hardfault.c

@@ -0,0 +1,109 @@
+// ****************************************************************************
+// semihost_hardfault.c
+//                - Provides hard fault handler to allow semihosting code not
+//                  to hang application when debugger not connected.
+//
+// ****************************************************************************
+// Copyright 2017-2020 NXP
+// All rights reserved.
+//
+// Software that is described herein is for illustrative purposes only
+// which provides customers with programming information regarding the
+// NXP Cortex-M based MCUs. This software is supplied "AS IS" without any
+// warranties of any kind, and NXP Semiconductors and its licensor disclaim any
+// and all warranties, express or implied, including all implied warranties of
+// merchantability, fitness for a particular purpose and non-infringement of
+// intellectual property rights.  NXP Semiconductors assumes no responsibility
+// or liability for the use of the software, conveys no license or rights under
+// any patent, copyright, mask work right, or any other intellectual property
+// rights in or to any products. NXP Semiconductors reserves the right to make
+// changes in the software without notification. NXP Semiconductors also makes
+// no representation or warranty that such application will be suitable for the
+// specified use without further testing or modification.
+//
+// Permission to use, copy, modify, and distribute this software and its
+// documentation is hereby granted, under NXP Semiconductors' and its
+// licensor's relevant copyrights in the software, without fee, provided that it
+// is used in conjunction with NXP Semiconductors microcontrollers.  This
+// copyright, permission, and disclaimer notice must appear in all copies of
+// this code.
+// ****************************************************************************
+//
+//                       ===== DESCRIPTION =====
+//
+// One of the issues with applications that make use of semihosting operations
+// (such as printf calls) is that the code will not execute correctly when the
+// debugger is not connected. Generally this will show up with the application
+// appearing to just hang. This may include the application running from reset
+// or powering up the board (with the application already in FLASH), and also
+// as the application failing to continue to execute after a debug session is
+// terminated.
+//
+// The problem here is that the "bottom layer" of the semihosted variants of
+// the C library, semihosting is implemented by a "BKPT 0xAB" instruction.
+// When the debug tools are not connected, this instruction triggers a hard
+// fault - and the default hard fault handler within an application will
+// typically just contains an infinite loop - causing the application to
+// appear to have hang when no debugger is connected.
+//
+// The below code provides an example hard fault handler which instead looks
+// to see what the instruction that caused the hard fault was - and if it
+// was a "BKPT 0xAB", then it instead returns back to the user application.
+//
+// In most cases this will allow applications containing semihosting
+// operations to execute (to some degree) when the debugger is not connected.
+//
+// == NOTE ==
+//
+// Correct execution of the application containing semihosted operations
+// which are vectored onto this hard fault handler cannot be guaranteed. This
+// is because the handler may not return data or return codes that the higher
+// level C library code or application code expects. This hard fault handler
+// is meant as a development aid, and it is not recommended to leave
+// semihosted code in a production build of your application!
+//
+// ****************************************************************************
+
+// Allow handler to be removed by setting a define (via command line)
+#if !defined (__SEMIHOST_HARDFAULT_DISABLE)
+
+__attribute__((naked))
+void HardFault_Handler(void){
+    __asm(  ".syntax unified\n"
+        // Check which stack is in use
+            "MOVS   R0, #4  \n"
+            "MOV    R1, LR  \n"
+            "TST    R0, R1  \n"
+            "BEQ    _MSP    \n"
+            "MRS    R0, PSP \n"
+            "B  _process      \n"
+            "_MSP:  \n"
+            "MRS    R0, MSP \n"
+        // Load the instruction that triggered hard fault
+        "_process:     \n"
+            "LDR    R1,[R0,#24] \n"
+            "LDRH    R2,[r1] \n"
+        // Semihosting instruction is "BKPT 0xAB" (0xBEAB)
+            "LDR    R3,=0xBEAB \n"
+            "CMP     R2,R3 \n"
+            "BEQ    _semihost_return \n"
+        // Wasn't semihosting instruction so enter infinite loop
+            "B . \n"
+        // Was semihosting instruction, so adjust location to
+        // return to by 1 instruction (2 bytes), then exit function
+        "_semihost_return: \n"
+            "ADDS    R1,#2 \n"
+            "STR    R1,[R0,#24] \n"
+    	// Set a return value from semihosting operation.
+    	// 32 is slightly arbitrary, but appears to allow most
+    	// C Library IO functions sitting on top of semihosting to
+    	// continue to operate to some degree
+    		    "MOVS   R1,#32 \n"
+    		    "STR R1,[ R0,#0 ] \n" // R0 is at location 0 on stack
+    	// Return from hard fault handler to application
+            "BX LR \n"
+        ".syntax divided\n") ;
+}
+
+#endif
+

FreeRTOS/Demo/CORTEX_MPU_LPC54018_MCUXpresso/Projects/MCUXpresso/Startup/startup_lpc54018.c

@@ -0,0 +1,820 @@
+//*****************************************************************************
+// LPC54018 startup code for use with MCUXpresso IDE
+//
+// Version : 101019
+//*****************************************************************************
+//
+// Copyright 2016-2019 NXP
+// All rights reserved.
+//
+// SPDX-License-Identifier: BSD-3-Clause
+//*****************************************************************************
+
+#if defined (DEBUG)
+#pragma GCC push_options
+#pragma GCC optimize ("Og")
+#endif // (DEBUG)
+
+#if defined (__cplusplus)
+#ifdef __REDLIB__
+#error Redlib does not support C++
+#else
+//*****************************************************************************
+//
+// The entry point for the C++ library startup
+//
+//*****************************************************************************
+extern "C" {
+    extern void __libc_init_array(void);
+}
+#endif
+#endif
+
+#define WEAK __attribute__ ((weak))
+#define WEAK_AV __attribute__ ((weak, section(".after_vectors")))
+#define ALIAS(f) __attribute__ ((weak, alias (#f)))
+
+//*****************************************************************************
+#if defined (__cplusplus)
+extern "C" {
+#endif
+
+//*****************************************************************************
+// Variable to store CRP value in. Will be placed automatically
+// by the linker when "Enable Code Read Protect" selected.
+// See crp.h header for more information
+//*****************************************************************************
+#include <NXP/crp.h>
+__CRP const unsigned int CRP_WORD = CRP_NO_CRP ;
+
+//*****************************************************************************
+// Declaration of external SystemInit function
+//*****************************************************************************
+#if defined (__USE_CMSIS)
+extern void SystemInit(void);
+#endif // (__USE_CMSIS)
+
+//*****************************************************************************
+// Forward declaration of the core exception handlers.
+// When the application defines a handler (with the same name), this will
+// automatically take precedence over these weak definitions.
+// If your application is a C++ one, then any interrupt handlers defined
+// in C++ files within in your main application will need to have C linkage
+// rather than C++ linkage. To do this, make sure that you are using extern "C"
+// { .... } around the interrupt handler within your main application code.
+//*****************************************************************************
+     void ResetISR(void);
+WEAK void NMI_Handler(void);
+WEAK void HardFault_Handler(void);
+WEAK void MemManage_Handler(void);
+WEAK void BusFault_Handler(void);
+WEAK void UsageFault_Handler(void);
+WEAK void SVC_Handler(void);
+WEAK void DebugMon_Handler(void);
+WEAK void PendSV_Handler(void);
+WEAK void SysTick_Handler(void);
+WEAK void IntDefaultHandler(void);
+
+//*****************************************************************************
+// Forward declaration of the application IRQ handlers. When the application
+// defines a handler (with the same name), this will automatically take
+// precedence over weak definitions below
+//*****************************************************************************
+WEAK void WDT_BOD_IRQHandler(void);
+WEAK void DMA0_IRQHandler(void);
+WEAK void GINT0_IRQHandler(void);
+WEAK void GINT1_IRQHandler(void);
+WEAK void PIN_INT0_IRQHandler(void);
+WEAK void PIN_INT1_IRQHandler(void);
+WEAK void PIN_INT2_IRQHandler(void);
+WEAK void PIN_INT3_IRQHandler(void);
+WEAK void UTICK0_IRQHandler(void);
+WEAK void MRT0_IRQHandler(void);
+WEAK void CTIMER0_IRQHandler(void);
+WEAK void CTIMER1_IRQHandler(void);
+WEAK void SCT0_IRQHandler(void);
+WEAK void CTIMER3_IRQHandler(void);
+WEAK void FLEXCOMM0_IRQHandler(void);
+WEAK void FLEXCOMM1_IRQHandler(void);
+WEAK void FLEXCOMM2_IRQHandler(void);
+WEAK void FLEXCOMM3_IRQHandler(void);
+WEAK void FLEXCOMM4_IRQHandler(void);
+WEAK void FLEXCOMM5_IRQHandler(void);
+WEAK void FLEXCOMM6_IRQHandler(void);
+WEAK void FLEXCOMM7_IRQHandler(void);
+WEAK void ADC0_SEQA_IRQHandler(void);
+WEAK void ADC0_SEQB_IRQHandler(void);
+WEAK void ADC0_THCMP_IRQHandler(void);
+WEAK void DMIC0_IRQHandler(void);
+WEAK void HWVAD0_IRQHandler(void);
+WEAK void USB0_NEEDCLK_IRQHandler(void);
+WEAK void USB0_IRQHandler(void);
+WEAK void RTC_IRQHandler(void);
+WEAK void FLEXCOMM10_IRQHandler(void);
+WEAK void Reserved47_IRQHandler(void);
+WEAK void PIN_INT4_IRQHandler(void);
+WEAK void PIN_INT5_IRQHandler(void);
+WEAK void PIN_INT6_IRQHandler(void);
+WEAK void PIN_INT7_IRQHandler(void);
+WEAK void CTIMER2_IRQHandler(void);
+WEAK void CTIMER4_IRQHandler(void);
+WEAK void RIT_IRQHandler(void);
+WEAK void SPIFI0_IRQHandler(void);
+WEAK void FLEXCOMM8_IRQHandler(void);
+WEAK void FLEXCOMM9_IRQHandler(void);
+WEAK void SDIO_IRQHandler(void);
+WEAK void CAN0_IRQ0_IRQHandler(void);
+WEAK void CAN0_IRQ1_IRQHandler(void);
+WEAK void CAN1_IRQ0_IRQHandler(void);
+WEAK void CAN1_IRQ1_IRQHandler(void);
+WEAK void USB1_IRQHandler(void);
+WEAK void USB1_NEEDCLK_IRQHandler(void);
+WEAK void ETHERNET_IRQHandler(void);
+WEAK void ETHERNET_PMT_IRQHandler(void);
+WEAK void ETHERNET_MACLP_IRQHandler(void);
+WEAK void Reserved68_IRQHandler(void);
+WEAK void LCD_IRQHandler(void);
+WEAK void SHA_IRQHandler(void);
+WEAK void SMARTCARD0_IRQHandler(void);
+WEAK void SMARTCARD1_IRQHandler(void);
+
+//*****************************************************************************
+// Forward declaration of the driver IRQ handlers. These are aliased
+// to the IntDefaultHandler, which is a 'forever' loop. When the driver
+// defines a handler (with the same name), this will automatically take
+// precedence over these weak definitions
+//*****************************************************************************
+void WDT_BOD_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void DMA0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void GINT0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void GINT1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void PIN_INT0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void PIN_INT1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void PIN_INT2_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void PIN_INT3_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void UTICK0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void MRT0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void CTIMER0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void CTIMER1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void SCT0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void CTIMER3_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void FLEXCOMM0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void FLEXCOMM1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void FLEXCOMM2_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void FLEXCOMM3_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void FLEXCOMM4_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void FLEXCOMM5_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void FLEXCOMM6_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void FLEXCOMM7_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void ADC0_SEQA_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void ADC0_SEQB_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void ADC0_THCMP_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void DMIC0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void HWVAD0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void USB0_NEEDCLK_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void USB0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void RTC_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void FLEXCOMM10_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void Reserved47_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void PIN_INT4_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void PIN_INT5_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void PIN_INT6_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void PIN_INT7_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void CTIMER2_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void CTIMER4_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void RIT_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void SPIFI0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void FLEXCOMM8_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void FLEXCOMM9_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void SDIO_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void CAN0_IRQ0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void CAN0_IRQ1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void CAN1_IRQ0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void CAN1_IRQ1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void USB1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void USB1_NEEDCLK_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void ETHERNET_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void ETHERNET_PMT_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void ETHERNET_MACLP_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void Reserved68_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void LCD_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void SHA_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void SMARTCARD0_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+void SMARTCARD1_DriverIRQHandler(void) ALIAS(IntDefaultHandler);
+
+//*****************************************************************************
+// The entry point for the application.
+// __main() is the entry point for Redlib based applications
+// main() is the entry point for Newlib based applications
+//*****************************************************************************
+#if defined (__REDLIB__)
+extern void __main(void);
+#endif
+extern int main(void);
+
+//*****************************************************************************
+// External declaration for the pointer to the stack top from the Linker Script
+//*****************************************************************************
+extern void _vStackTop(void);
+extern void _image_size(void);
+//*****************************************************************************
+// External declaration for LPC MCU vector table checksum from  Linker Script
+//*****************************************************************************
+WEAK extern void __valid_user_code_checksum();
+
+//*****************************************************************************
+// External declaration for image type and load address from  Linker Script
+//*****************************************************************************
+WEAK extern void __imghdr_loadaddress();
+WEAK extern void __imghdr_imagetype();
+
+//*****************************************************************************
+#if defined (__cplusplus)
+} // extern "C"
+#endif
+#ifndef IMG_BAUDRATE
+#define IMG_BAUDRATE 0
+#endif
+//*****************************************************************************
+// The vector table.
+// This relies on the linker script to place at correct location in memory.
+//*****************************************************************************
+extern void (* const g_pfnVectors[])(void);
+extern void * __Vectors __attribute__ ((alias ("g_pfnVectors")));
+
+__attribute__ ((used, section(".isr_vector")))
+void (* const g_pfnVectors[])(void) = {
+    // Core Level - CM4
+    &_vStackTop,                       // The initial stack pointer
+    ResetISR,                          // The reset handler
+    NMI_Handler,                       // The NMI handler
+    HardFault_Handler,                 // The hard fault handler
+    MemManage_Handler,                 // The MPU fault handler
+    BusFault_Handler,                  // The bus fault handler
+    UsageFault_Handler,                // The usage fault handler
+    __valid_user_code_checksum,        // LPC MCU checksum
+    0,                                 // ECRP
+    (void (*)(void))0xEDDC94BD,        // Reserved
+    (void (*)(void))0x160,             // Reserved
+    SVC_Handler,                       // SVCall handler
+    DebugMon_Handler,                  // Debug monitor handler
+    0,                                 // Reserved
+    PendSV_Handler,                    // The PendSV handler
+    SysTick_Handler,                   // The SysTick handler
+
+    // Chip Level - LPC54018
+    WDT_BOD_IRQHandler,         // 16: Windowed watchdog timer, Brownout detect
+    DMA0_IRQHandler,            // 17: DMA controller
+    GINT0_IRQHandler,           // 18: GPIO group 0
+    GINT1_IRQHandler,           // 19: GPIO group 1
+    PIN_INT0_IRQHandler,        // 20: Pin interrupt 0 or pattern match engine slice 0
+    PIN_INT1_IRQHandler,        // 21: Pin interrupt 1or pattern match engine slice 1
+    PIN_INT2_IRQHandler,        // 22: Pin interrupt 2 or pattern match engine slice 2
+    PIN_INT3_IRQHandler,        // 23: Pin interrupt 3 or pattern match engine slice 3
+    UTICK0_IRQHandler,          // 24: Micro-tick Timer
+    MRT0_IRQHandler,            // 25: Multi-rate timer
+    CTIMER0_IRQHandler,         // 26: Standard counter/timer CTIMER0
+    CTIMER1_IRQHandler,         // 27: Standard counter/timer CTIMER1
+    SCT0_IRQHandler,            // 28: SCTimer/PWM
+    CTIMER3_IRQHandler,         // 29: Standard counter/timer CTIMER3
+    FLEXCOMM0_IRQHandler,       // 30: Flexcomm Interface 0 (USART, SPI, I2C, FLEXCOMM)
+    FLEXCOMM1_IRQHandler,       // 31: Flexcomm Interface 1 (USART, SPI, I2C, FLEXCOMM)
+    FLEXCOMM2_IRQHandler,       // 32: Flexcomm Interface 2 (USART, SPI, I2C, FLEXCOMM)
+    FLEXCOMM3_IRQHandler,       // 33: Flexcomm Interface 3 (USART, SPI, I2C, FLEXCOMM)
+    FLEXCOMM4_IRQHandler,       // 34: Flexcomm Interface 4 (USART, SPI, I2C, FLEXCOMM)
+    FLEXCOMM5_IRQHandler,       // 35: Flexcomm Interface 5 (USART, SPI, I2C,, FLEXCOMM)
+    FLEXCOMM6_IRQHandler,       // 36: Flexcomm Interface 6 (USART, SPI, I2C, I2S,, FLEXCOMM)
+    FLEXCOMM7_IRQHandler,       // 37: Flexcomm Interface 7 (USART, SPI, I2C, I2S,, FLEXCOMM)
+    ADC0_SEQA_IRQHandler,       // 38: ADC0 sequence A completion.
+    ADC0_SEQB_IRQHandler,       // 39: ADC0 sequence B completion.
+    ADC0_THCMP_IRQHandler,      // 40: ADC0 threshold compare and error.
+    DMIC0_IRQHandler,           // 41: Digital microphone and DMIC subsystem
+    HWVAD0_IRQHandler,          // 42: Hardware Voice Activity Detector
+    USB0_NEEDCLK_IRQHandler,    // 43: USB Activity Wake-up Interrupt
+    USB0_IRQHandler,            // 44: USB device
+    RTC_IRQHandler,             // 45: RTC alarm and wake-up interrupts
+    FLEXCOMM10_IRQHandler,      // 46: Flexcomm Interface 10 (SPI, FLEXCOMM)
+    Reserved47_IRQHandler,      // 47: Reserved interrupt
+    PIN_INT4_IRQHandler,        // 48: Pin interrupt 4 or pattern match engine slice 4 int
+    PIN_INT5_IRQHandler,        // 49: Pin interrupt 5 or pattern match engine slice 5 int
+    PIN_INT6_IRQHandler,        // 50: Pin interrupt 6 or pattern match engine slice 6 int
+    PIN_INT7_IRQHandler,        // 51: Pin interrupt 7 or pattern match engine slice 7 int
+    CTIMER2_IRQHandler,         // 52: Standard counter/timer CTIMER2
+    CTIMER4_IRQHandler,         // 53: Standard counter/timer CTIMER4
+    RIT_IRQHandler,             // 54: Repetitive Interrupt Timer
+    SPIFI0_IRQHandler,          // 55: SPI flash interface
+    FLEXCOMM8_IRQHandler,       // 56: Flexcomm Interface 8 (USART, SPI, I2C, FLEXCOMM)
+    FLEXCOMM9_IRQHandler,       // 57: Flexcomm Interface 9 (USART, SPI, I2C, FLEXCOMM)
+    SDIO_IRQHandler,            // 58: SD/MMC
+    CAN0_IRQ0_IRQHandler,       // 59: CAN0 interrupt0
+    CAN0_IRQ1_IRQHandler,       // 60: CAN0 interrupt1
+    CAN1_IRQ0_IRQHandler,       // 61: CAN1 interrupt0
+    CAN1_IRQ1_IRQHandler,       // 62: CAN1 interrupt1
+    USB1_IRQHandler,            // 63: USB1 interrupt
+    USB1_NEEDCLK_IRQHandler,    // 64: USB1 activity
+    ETHERNET_IRQHandler,        // 65: Ethernet
+    ETHERNET_PMT_IRQHandler,    // 66: Ethernet power management interrupt
+    ETHERNET_MACLP_IRQHandler,  // 67: Ethernet MAC interrupt
+    Reserved68_IRQHandler,      // 68: Reserved interrupt
+    LCD_IRQHandler,             // 69: LCD interrupt
+    SHA_IRQHandler,             // 70: SHA interrupt
+    SMARTCARD0_IRQHandler,      // 71: Smart card 0 interrupt
+    SMARTCARD1_IRQHandler,      // 72: Smart card 1 interrupt
+
+    0,                          // Reserved
+    0,                          // Reserved
+    0,                          // Reserved
+    0,                          // Reserved
+    0,                          // Reserved
+    0,                          // Reserved
+    0,                          // Reserved
+    0,                          // Reserved
+    0,                          // Reserved
+    0,                          // Reserved
+    0,                          // Reserved
+    0,                          // Reserved
+    0,                          // Reserved
+    0,                          // Reserved
+    0,                          // Reserved
+    (void (*)(void))0xFEEDA5A5, // Header Marker
+
+#if defined (ADD_CRC)
+    (__imghdr_imagetype - 1),   // (0x04) Image Type
+     __imghdr_loadaddress,      // (0x08) Load_address
+#else
+    __imghdr_imagetype,         // (0x04) Image Type
+    __imghdr_loadaddress,       // (0x08) Load_address
+#endif
+    (void (*)(void))(((unsigned)_image_size) - 4),            // (0x0C) load_length, exclude 4 bytes CRC field.
+    0,                          // (0x10) CRC value (only applicable to NON Non-secure images).
+    0,                          // (0x14) Version (only applicable to DUAL_ENH image type.
+    0,                          // (0x18) EMC static memory configuration settings, required for EMC boot
+    (void (*)(void))IMG_BAUDRATE,       // (0x1C) image baudrate
+    0,                          // (0x20) reserved
+    (void (*)(void))0xEDDC94BD,         // (0x24) Image_marker
+    0,                          // (0x28) SBZ
+    0,                          // (0x2C) reserved
+    #ifdef W25Q128JVFM
+    /* SPIFI Descriptor - W25Q128JVFM */
+    (void (*)(void))0x00000000,         // 0xFFFFFFFF to default 1-bit SPI mode  ；DevStrAdr
+    (void (*)(void))0x001870EF,         // mfgId + extCount
+    (void (*)(void))0x00000000,         // extid 0-3
+    (void (*)(void))0x00000000,         // extid 4-7
+    (void (*)(void))0x0001001D,         // caps
+    (void (*)(void))0x00000100,         // Blks + RESV1
+    (void (*)(void))0x00010000,         // blkSize
+    (void (*)(void))0x00000000,         // subBlks + subBlkSize
+    (void (*)(void))0x00000100,         // pageSize + RESV2
+    (void (*)(void))0x00003F00,         // maxReadSize
+    (void (*)(void))0x68506850,         // maxClkRate,maxReadRate,maxHSReadRate,maxProgramRate
+    (void (*)(void))0x04030050,         // maxHSProgramRate,initDeInitFxId,clearStatusFxId,getStatusFxId,
+    (void (*)(void))0x14110D09,         // setStatusFxId,setOptionsFxId,getReadCmdFxId,getWriteCmdFxId
+    #endif
+
+     #ifdef MXL12835F
+     /* SPI Descriptor - MXL12835F */
+    (void (*)(void))0x00000000,         // 0xFFFFFFFF to default 1-bit SPI mode  ;DevStrAdr
+    (void (*)(void))0x001820C2,         // mfgId + extCount
+    (void (*)(void))0x00000000,         // extid 0-3
+    (void (*)(void))0x00000000,         // extid 4-7
+    (void (*)(void))0x0001001D,         // caps
+    (void (*)(void))0x00000100,         // Blks + RESV1
+    (void (*)(void))0x00010000,         // blkSize
+    (void (*)(void))0x00000000,         // subBlks + subBlkSize
+    (void (*)(void))0x00000100,         // pageSize + RESV2
+    (void (*)(void))0x00003F00,         // maxReadSize
+    (void (*)(void))0x68506850,         // maxClkRate,maxReadRate,maxHSReadRate,maxProgramRate
+    (void (*)(void))0x06030050,         // maxHSProgramRate,initDeInitFxId,clearStatusFxId,getStatusFxId
+    (void (*)(void))0x14110F0B,         // setStatusFxId,setOptionsFxId,getReadCmdFxId,getWriteCmdFxId
+    #endif
+
+}; /* End of g_pfnVectors */
+
+//*****************************************************************************
+// Functions to carry out the initialization of RW and BSS data sections. These
+// are written as separate functions rather than being inlined within the
+// ResetISR() function in order to cope with MCUs with multiple banks of
+// memory.
+//*****************************************************************************
+__attribute__ ((section(".after_vectors.init_data")))
+void data_init(unsigned int romstart, unsigned int start, unsigned int len) {
+    unsigned int *pulDest = (unsigned int*) start;
+    unsigned int *pulSrc = (unsigned int*) romstart;
+    unsigned int loop;
+    for (loop = 0; loop < len; loop = loop + 4)
+        *pulDest++ = *pulSrc++;
+}
+
+__attribute__ ((section(".after_vectors.init_bss")))
+void bss_init(unsigned int start, unsigned int len) {
+    unsigned int *pulDest = (unsigned int*) start;
+    unsigned int loop;
+    for (loop = 0; loop < len; loop = loop + 4)
+        *pulDest++ = 0;
+}
+
+//*****************************************************************************
+// The following symbols are constructs generated by the linker, indicating
+// the location of various points in the "Global Section Table". This table is
+// created by the linker via the Code Red managed linker script mechanism. It
+// contains the load address, execution address and length of each RW data
+// section and the execution and length of each BSS (zero initialized) section.
+//*****************************************************************************
+extern unsigned int __data_section_table;
+extern unsigned int __data_section_table_end;
+extern unsigned int __bss_section_table;
+extern unsigned int __bss_section_table_end;
+
+//*****************************************************************************
+// Reset entry point for your code.
+// Sets up a simple runtime environment and initializes the C/C++
+// library.
+//*****************************************************************************
+__attribute__ ((section(".after_vectors.reset")))
+void ResetISR(void) {
+
+    // Disable interrupts
+    __asm volatile ("cpsid i");
+
+
+    // Enable SRAM clock used by Stack
+    __asm volatile ("LDR R0, =0x40000220\n\t"
+                    "MOV R1, #56\n\t"
+                    "STR R1, [R0]");
+
+#if defined (__USE_CMSIS)
+// If __USE_CMSIS defined, then call CMSIS SystemInit code
+    SystemInit();
+
+#endif // (__USE_CMSIS)
+
+    //
+    // Copy the data sections from flash to SRAM.
+    //
+    unsigned int LoadAddr, ExeAddr, SectionLen;
+    unsigned int *SectionTableAddr;
+
+    // Load base address of Global Section Table
+    SectionTableAddr = &__data_section_table;
+
+    // Copy the data sections from flash to SRAM.
+    while (SectionTableAddr < &__data_section_table_end) {
+        LoadAddr = *SectionTableAddr++;
+        ExeAddr = *SectionTableAddr++;
+        SectionLen = *SectionTableAddr++;
+        data_init(LoadAddr, ExeAddr, SectionLen);
+    }
+
+    // At this point, SectionTableAddr = &__bss_section_table;
+    // Zero fill the bss segment
+    while (SectionTableAddr < &__bss_section_table_end) {
+        ExeAddr = *SectionTableAddr++;
+        SectionLen = *SectionTableAddr++;
+        bss_init(ExeAddr, SectionLen);
+    }
+
+#if !defined (__USE_CMSIS)
+// Assume that if __USE_CMSIS defined, then CMSIS SystemInit code
+// will enable the FPU
+#if defined (__VFP_FP__) && !defined (__SOFTFP__)
+    //
+    // Code to enable the Cortex-M4 FPU only included
+    // if appropriate build options have been selected.
+    // Code taken from Section 7.1, Cortex-M4 TRM (DDI0439C)
+    //
+    // Read CPACR (located at address 0xE000ED88)
+    // Set bits 20-23 to enable CP10 and CP11 coprocessors
+    // Write back the modified value to the CPACR
+    asm volatile ("LDR.W R0, =0xE000ED88\n\t"
+                  "LDR R1, [R0]\n\t"
+                  "ORR R1, R1, #(0xF << 20)\n\t"
+                  "STR R1, [R0]");
+#endif // (__VFP_FP__) && !(__SOFTFP__)
+#endif // (__USE_CMSIS)
+
+
+#if !defined (__USE_CMSIS)
+// Assume that if __USE_CMSIS defined, then CMSIS SystemInit code
+// will setup the VTOR register
+
+    // Check to see if we are running the code from a non-zero
+    // address (eg RAM, external flash), in which case we need
+    // to modify the VTOR register to tell the CPU that the
+    // vector table is located at a non-0x0 address.
+    unsigned int * pSCB_VTOR = (unsigned int *) 0xE000ED08;
+    if ((unsigned int *)g_pfnVectors!=(unsigned int *) 0x00000000) {
+        *pSCB_VTOR = (unsigned int)g_pfnVectors;
+    }
+#endif // (__USE_CMSIS)
+#if defined (__cplusplus)
+    //
+    // Call C++ library initialisation
+    //
+    __libc_init_array();
+#endif
+
+    // Reenable interrupts
+    __asm volatile ("cpsie i");
+
+#if defined (__REDLIB__)
+    // Call the Redlib library, which in turn calls main()
+    __main();
+#else
+    main();
+#endif
+
+    //
+    // main() shouldn't return, but if it does, we'll just enter an infinite loop
+    //
+    while (1) {
+        ;
+    }
+}
+
+//*****************************************************************************
+// Default core exception handlers. Override the ones here by defining your own
+// handler routines in your application code.
+//*****************************************************************************
+WEAK_AV void NMI_Handler(void)
+{ while(1) {}
+}
+
+WEAK_AV void HardFault_Handler(void)
+{ while(1) {}
+}
+
+WEAK_AV void MemManage_Handler(void)
+{ while(1) {}
+}
+
+WEAK_AV void BusFault_Handler(void)
+{ while(1) {}
+}
+
+WEAK_AV void UsageFault_Handler(void)
+{ while(1) {}
+}
+
+WEAK_AV void SVC_Handler(void)
+{ while(1) {}
+}
+
+WEAK_AV void DebugMon_Handler(void)
+{ while(1) {}
+}
+
+WEAK_AV void PendSV_Handler(void)
+{ while(1) {}
+}
+
+WEAK_AV void SysTick_Handler(void)
+{ while(1) {}
+}
+
+//*****************************************************************************
+// Processor ends up here if an unexpected interrupt occurs or a specific
+// handler is not present in the application code.
+//*****************************************************************************
+WEAK_AV void IntDefaultHandler(void)
+{ while(1) {}
+}
+
+//*****************************************************************************
+// Default application exception handlers. Override the ones here by defining
+// your own handler routines in your application code. These routines call
+// driver exception handlers or IntDefaultHandler() if no driver exception
+// handler is included.
+//*****************************************************************************
+WEAK void WDT_BOD_IRQHandler(void)
+{   WDT_BOD_DriverIRQHandler();
+}
+
+WEAK void DMA0_IRQHandler(void)
+{   DMA0_DriverIRQHandler();
+}
+
+WEAK void GINT0_IRQHandler(void)
+{   GINT0_DriverIRQHandler();
+}
+
+WEAK void GINT1_IRQHandler(void)
+{   GINT1_DriverIRQHandler();
+}
+
+WEAK void PIN_INT0_IRQHandler(void)
+{   PIN_INT0_DriverIRQHandler();
+}
+
+WEAK void PIN_INT1_IRQHandler(void)
+{   PIN_INT1_DriverIRQHandler();
+}
+
+WEAK void PIN_INT2_IRQHandler(void)
+{   PIN_INT2_DriverIRQHandler();
+}
+
+WEAK void PIN_INT3_IRQHandler(void)
+{   PIN_INT3_DriverIRQHandler();
+}
+
+WEAK void UTICK0_IRQHandler(void)
+{   UTICK0_DriverIRQHandler();
+}
+
+WEAK void MRT0_IRQHandler(void)
+{   MRT0_DriverIRQHandler();
+}
+
+WEAK void CTIMER0_IRQHandler(void)
+{   CTIMER0_DriverIRQHandler();
+}
+
+WEAK void CTIMER1_IRQHandler(void)
+{   CTIMER1_DriverIRQHandler();
+}
+
+WEAK void SCT0_IRQHandler(void)
+{   SCT0_DriverIRQHandler();
+}
+
+WEAK void CTIMER3_IRQHandler(void)
+{   CTIMER3_DriverIRQHandler();
+}
+
+WEAK void FLEXCOMM0_IRQHandler(void)
+{   FLEXCOMM0_DriverIRQHandler();
+}
+
+WEAK void FLEXCOMM1_IRQHandler(void)
+{   FLEXCOMM1_DriverIRQHandler();
+}
+
+WEAK void FLEXCOMM2_IRQHandler(void)
+{   FLEXCOMM2_DriverIRQHandler();
+}
+
+WEAK void FLEXCOMM3_IRQHandler(void)
+{   FLEXCOMM3_DriverIRQHandler();
+}
+
+WEAK void FLEXCOMM4_IRQHandler(void)
+{   FLEXCOMM4_DriverIRQHandler();
+}
+
+WEAK void FLEXCOMM5_IRQHandler(void)
+{   FLEXCOMM5_DriverIRQHandler();
+}
+
+WEAK void FLEXCOMM6_IRQHandler(void)
+{   FLEXCOMM6_DriverIRQHandler();
+}
+
+WEAK void FLEXCOMM7_IRQHandler(void)
+{   FLEXCOMM7_DriverIRQHandler();
+}
+
+WEAK void ADC0_SEQA_IRQHandler(void)
+{   ADC0_SEQA_DriverIRQHandler();
+}
+
+WEAK void ADC0_SEQB_IRQHandler(void)
+{   ADC0_SEQB_DriverIRQHandler();
+}
+
+WEAK void ADC0_THCMP_IRQHandler(void)
+{   ADC0_THCMP_DriverIRQHandler();
+}
+
+WEAK void DMIC0_IRQHandler(void)
+{   DMIC0_DriverIRQHandler();
+}
+
+WEAK void HWVAD0_IRQHandler(void)
+{   HWVAD0_DriverIRQHandler();
+}
+
+WEAK void USB0_NEEDCLK_IRQHandler(void)
+{   USB0_NEEDCLK_DriverIRQHandler();
+}
+
+WEAK void USB0_IRQHandler(void)
+{   USB0_DriverIRQHandler();
+}
+
+WEAK void RTC_IRQHandler(void)
+{   RTC_DriverIRQHandler();
+}
+
+WEAK void FLEXCOMM10_IRQHandler(void)
+{   FLEXCOMM10_DriverIRQHandler();
+}
+
+WEAK void Reserved47_IRQHandler(void)
+{   Reserved47_DriverIRQHandler();
+}
+
+WEAK void PIN_INT4_IRQHandler(void)
+{   PIN_INT4_DriverIRQHandler();
+}
+
+WEAK void PIN_INT5_IRQHandler(void)
+{   PIN_INT5_DriverIRQHandler();
+}
+
+WEAK void PIN_INT6_IRQHandler(void)
+{   PIN_INT6_DriverIRQHandler();
+}
+
+WEAK void PIN_INT7_IRQHandler(void)
+{   PIN_INT7_DriverIRQHandler();
+}
+
+WEAK void CTIMER2_IRQHandler(void)
+{   CTIMER2_DriverIRQHandler();
+}
+
+WEAK void CTIMER4_IRQHandler(void)
+{   CTIMER4_DriverIRQHandler();
+}
+
+WEAK void RIT_IRQHandler(void)
+{   RIT_DriverIRQHandler();
+}
+
+WEAK void SPIFI0_IRQHandler(void)
+{   SPIFI0_DriverIRQHandler();
+}
+
+WEAK void FLEXCOMM8_IRQHandler(void)
+{   FLEXCOMM8_DriverIRQHandler();
+}
+
+WEAK void FLEXCOMM9_IRQHandler(void)
+{   FLEXCOMM9_DriverIRQHandler();
+}
+
+WEAK void SDIO_IRQHandler(void)
+{   SDIO_DriverIRQHandler();
+}
+
+WEAK void CAN0_IRQ0_IRQHandler(void)
+{   CAN0_IRQ0_DriverIRQHandler();
+}
+
+WEAK void CAN0_IRQ1_IRQHandler(void)
+{   CAN0_IRQ1_DriverIRQHandler();
+}
+
+WEAK void CAN1_IRQ0_IRQHandler(void)
+{   CAN1_IRQ0_DriverIRQHandler();
+}
+
+WEAK void CAN1_IRQ1_IRQHandler(void)
+{   CAN1_IRQ1_DriverIRQHandler();
+}
+
+WEAK void USB1_IRQHandler(void)
+{   USB1_DriverIRQHandler();
+}
+
+WEAK void USB1_NEEDCLK_IRQHandler(void)
+{   USB1_NEEDCLK_DriverIRQHandler();
+}
+
+WEAK void ETHERNET_IRQHandler(void)
+{   ETHERNET_DriverIRQHandler();
+}
+
+WEAK void ETHERNET_PMT_IRQHandler(void)
+{   ETHERNET_PMT_DriverIRQHandler();
+}
+
+WEAK void ETHERNET_MACLP_IRQHandler(void)
+{   ETHERNET_MACLP_DriverIRQHandler();
+}
+
+WEAK void Reserved68_IRQHandler(void)
+{   Reserved68_DriverIRQHandler();
+}
+
+WEAK void LCD_IRQHandler(void)
+{   LCD_DriverIRQHandler();
+}
+
+WEAK void SHA_IRQHandler(void)
+{   SHA_DriverIRQHandler();
+}
+
+WEAK void SMARTCARD0_IRQHandler(void)
+{   SMARTCARD0_DriverIRQHandler();
+}
+
+WEAK void SMARTCARD1_IRQHandler(void)
+{   SMARTCARD1_DriverIRQHandler();
+}
+
+//*****************************************************************************
+
+#if defined (DEBUG)
+#pragma GCC pop_options
+#endif // (DEBUG)