len0rd/FreeRTOS-Kernel
1
0
Fork 0
mirror of https://github.com/FreeRTOS/FreeRTOS-Kernel.git synced 2025-04-19 21:11:57 -04:00
Code Issues Packages Projects Releases Wiki Activity

Comment ready for release.

Browse source
This commit is contained in:
Richard Barry 2008-03-06 20:55:49 +00:00
parent f39424feee
commit bf5cd55c55
3 changed files with 131 additions and 227 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

149
Source/portable/GCC/PPC405_Xilinx/port.c
View file

@ -1,5 +1,5 @@
/* /*
FreeRTOS.org V4.7.1 - Copyright (C) 2003-2008 Richard Barry. FreeRTOS.org V4.7.2 - Copyright (C) 2003-2008 Richard Barry.
This file is part of the FreeRTOS.org distribution. This file is part of the FreeRTOS.org distribution.
@ -54,28 +54,47 @@
#include "xintc.h" #include "xintc.h"
#include "xintc_i.h" #include "xintc_i.h"
/* Standard includes. */ /*-----------------------------------------------------------*/
#include <string.h>
/* Definitions to set the initial MSR of each task. */
#define portCRITICAL_INTERRUPT_ENABLE ( 1UL << 17UL )
#define portEXTERNAL_INTERRUPT_ENABLE ( 1UL << 15UL )
#define portMACHINE_CHECK_ENABLE ( 1UL << 12UL )
#define portINITIAL_MSR ( portCRITICAL_INTERRUPT_ENABLE | portEXTERNAL_INTERRUPT_ENABLE | portMACHINE_CHECK_ENABLE )
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
#define portCRITICAL_INTERRUPT_ENABLE ( 0UL << 17UL )
#define portEXTERNAL_INTERRUPT_ENABLE ( 1UL << 15UL )
#define portMACHINE_CHECK_ENABLE ( 0UL << 12UL )
#define portINITIAL_MSR ( portCRITICAL_INTERRUPT_ENABLE | portEXTERNAL_INTERRUPT_ENABLE | portMACHINE_CHECK_ENABLE )
/* /*
* Setup the system timer to generate the tick interrupt.
*/ */
static void prvSetupTimerInterrupt( void ); static void prvSetupTimerInterrupt( void );
/*
* The handler for the tick interrupt - defined in portasm.s.
*/
extern void vPortTickISR( void ); extern void vPortTickISR( void );
/*
* The handler for the yield function - defined in portasm.s.
*/
extern void vPortYield( void ); extern void vPortYield( void );
/*
* Function to start the scheduler running by starting the highest
* priority task that has thus far been created.
*/
extern void vPortStartFirstTask( void ); extern void vPortStartFirstTask( void );
/*-----------------------------------------------------------*/
/* Structure used to hold the state of the interrupt controller. */
static XIntc xInterruptController; static XIntc xInterruptController;
/*-----------------------------------------------------------*/
/* /*
* Initialise the stack of a task to look exactly as if a call to * Initialise the stack of a task to look exactly as if the task had been
* portSAVE_CONTEXT had been made. * interrupted.
* *
* See the header file portable.h. * See the header file portable.h.
*/ */
@ -165,7 +184,6 @@ portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE
*pxTopOfStack = ( portSTACK_TYPE ) vPortStartFirstTask;/* Next LR. */ *pxTopOfStack = ( portSTACK_TYPE ) vPortStartFirstTask;/* Next LR. */
pxTopOfStack--; pxTopOfStack--;
*pxTopOfStack = 0x00000000UL;;/* Backchain. */ *pxTopOfStack = 0x00000000UL;;/* Backchain. */
// pxTopOfStack--;
return pxTopOfStack; return pxTopOfStack;
} }
@ -173,14 +191,8 @@ portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE
portBASE_TYPE xPortStartScheduler( void ) portBASE_TYPE xPortStartScheduler( void )
{ {
extern void *pxCurrentTCB;
prvSetupTimerInterrupt(); prvSetupTimerInterrupt();
XExc_RegisterHandler( XEXC_ID_SYSTEM_CALL, ( XExceptionHandler ) vPortYield, ( void * ) 0 ); XExc_RegisterHandler( XEXC_ID_SYSTEM_CALL, ( XExceptionHandler ) vPortYield, ( void * ) 0 );
// XExc_mEnableExceptions( XEXC_NON_CRITICAL );
vPortStartFirstTask(); vPortStartFirstTask();
/* Should not get here as the tasks are now running! */ /* Should not get here as the tasks are now running! */
@ -197,7 +209,6 @@ void vPortEndScheduler( void )
/* /*
* Hardware initialisation to generate the RTOS tick. * Hardware initialisation to generate the RTOS tick.
*/ */
static void prvTickISR( void );
static void prvSetupTimerInterrupt( void ) static void prvSetupTimerInterrupt( void )
{ {
const unsigned portLONG ulInterval = ( ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL ); const unsigned portLONG ulInterval = ( ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL );
@ -216,69 +227,43 @@ const unsigned portLONG ulInterval = ( ( configCPU_CLOCK_HZ / configTICK_RATE_HZ
} }
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
static void prvTickISR( void )
{
static unsigned portLONG ulTicks = 0;
ulTicks++;
if( ulTicks >= 1000 )
{
vParTestToggleLED( 0 );
ulTicks = 0;
}
XTime_PITClearInterrupt();
}
/*-----------------------------------------------------------*/
void vPortISRHandler( void *vNullDoNotUse ) void vPortISRHandler( void *vNullDoNotUse )
{ {
Xuint32 IntrStatus; unsigned portLONG ulInterruptStatus, ulInterruptMask = 1UL;
Xuint32 IntrMask = 1; portBASE_TYPE xInterruptNumber;
int IntrNumber; XIntc_Config *pxInterruptController;
//extern XIntc xInterruptController; XIntc_VectorTableEntry *pxTable;
XIntc_Config *CfgPtr;// = xInterruptController.CfgPtr;
/* Get the configuration data using the device ID */
//CfgPtr = &XIntc_ConfigTable[(Xuint32)DeviceId];
CfgPtr = &XIntc_ConfigTable[(Xuint32)XPAR_OPB_INTC_0_DEVICE_ID];
/* Get the interrupts that are waiting to be serviced */
IntrStatus = XIntc_mGetIntrStatus(CfgPtr->BaseAddress);
/* Service each interrupt that is active and enabled by checking each
* bit in the register from LSB to MSB which corresponds to an interrupt
* intput signal
*/
for (IntrNumber = 0; IntrNumber < XPAR_INTC_MAX_NUM_INTR_INPUTS;
IntrNumber++)
{
if (IntrStatus & 1)
{
XIntc_VectorTableEntry *TablePtr;
/* The interrupt is active and enabled, call the interrupt
* handler that was setup with the specified parameter
*/
TablePtr = &(CfgPtr->HandlerTable[IntrNumber]);
TablePtr->Handler(TablePtr->CallBackRef);
/* Clear the interrupt. */ /* Get the configuration by using the device ID - in this case it is
XIntc_mAckIntr(CfgPtr->BaseAddress, IntrMask); assumed that only one interrupt controller is being used. */
pxInterruptController = &XIntc_ConfigTable[ XPAR_OPB_INTC_0_DEVICE_ID ];
/* Which interrupts are pending? */
ulInterruptStatus = XIntc_mGetIntrStatus( pxInterruptController->BaseAddress );
for( xInterruptNumber = 0; xInterruptNumber < XPAR_INTC_MAX_NUM_INTR_INPUTS; xInterruptNumber++ )
{
if( ulInterruptStatus & 0x01UL )
{
/* Call the registered handler. */
pxTable = &( pxInterruptController->HandlerTable[ xInterruptNumber ] );
pxTable->Handler( pxTable->CallBackRef );
/* Clear the pending interrupt. */
XIntc_mAckIntr( pxInterruptController->BaseAddress, ulInterruptMask );
break; break;
} }
/* Move to the next interrupt to check */ /* Check the next interrupt. */
IntrMask <<= 1; ulInterruptMask <<= 0x01UL;
IntrStatus >>= 1; ulInterruptStatus >>= 0x01UL;
/* If there are no other bits set indicating that all interrupts /* Have we serviced all interrupts? */
* have been serviced, then exit the loop if( ulInterruptStatus == 0UL )
*/ {
if (IntrStatus == 0) break;
{ }
break; }
}
}
} }
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
@ -286,9 +271,16 @@ void vPortSetupInterruptController( void )
{ {
extern void vPortISRWrapper( void ); extern void vPortISRWrapper( void );
/* Perform all library calls necessary to initialise the exception table
and interrupt controller. This assumes only one interrupt controller is in
use. */
XExc_mDisableExceptions( XEXC_NON_CRITICAL ); XExc_mDisableExceptions( XEXC_NON_CRITICAL );
XExc_Init(); XExc_Init();
XExc_RegisterHandler( XEXC_ID_NON_CRITICAL_INT, (XExceptionHandler)vPortISRWrapper, NULL );
/* The library functions save the context - we then jump to a wrapper to
save the stack into the TCB. The wrapper then calls the handler defined
above. */
XExc_RegisterHandler( XEXC_ID_NON_CRITICAL_INT, ( XExceptionHandler ) vPortISRWrapper, NULL );
XIntc_Initialize( &xInterruptController, XPAR_OPB_INTC_0_DEVICE_ID ); XIntc_Initialize( &xInterruptController, XPAR_OPB_INTC_0_DEVICE_ID );
XIntc_Start( &xInterruptController, XIN_REAL_MODE ); XIntc_Start( &xInterruptController, XIN_REAL_MODE );
} }
@ -298,6 +290,9 @@ portBASE_TYPE xPortInstallInterruptHandler( unsigned portCHAR ucInterruptID, XIn
{ {
portBASE_TYPE xReturn = pdFAIL; portBASE_TYPE xReturn = pdFAIL;
/* This function is defined here so the scope of xInterruptController can
remain within this file. */
if( XST_SUCCESS == XIntc_Connect( &xInterruptController, ucInterruptID, pxHandler, pvCallBackRef ) ) if( XST_SUCCESS == XIntc_Connect( &xInterruptController, ucInterruptID, pxHandler, pvCallBackRef ) )
{ {
XIntc_Enable( &xInterruptController, ucInterruptID ); XIntc_Enable( &xInterruptController, ucInterruptID );

204
Source/portable/GCC/PPC405_Xilinx/portasm.s
View file

@ -10,18 +10,6 @@
.global vPortTickISR .global vPortTickISR
.global vPortISRWrapper .global vPortISRWrapper
.set portCONTEXT_SIZE, 156
.set portR0_OFFSET, 152
.set portGPR_OFFSET, 32
.set portCR_OFFSET, 28
.set portXER_OFFSET, 24
.set portLR_OFFSET, 16
.set portCTR_OFFSET, 16
.set portUSPRG0_OFFSET, 12
.set portSRR0_OFFSET, 8
.set portSRR1_OFFSET, 4
.set BChainField, 0 .set BChainField, 0
.set NextLRField, BChainField + 4 .set NextLRField, BChainField + 4
.set MSRField, NextLRField + 4 .set MSRField, NextLRField + 4
@ -37,131 +25,7 @@
.set IFrameSize, r3r31Field + ( ( 31 - 3 ) + 1 ) * 4 .set IFrameSize, r3r31Field + ( ( 31 - 3 ) + 1 ) * 4
.macro portRESTORE_CONTEXT .macro portSAVE_STACK_POINTER_AND_LR
# Get the address of the TCB.
xor R0, R0, R0
addis SP, R0, pxCurrentTCB@ha
lwz SP, pxCurrentTCB@l( SP )
# Get the task stack pointer from the TCB.
lwz SP, 0( SP )
# Pop the special purpose registers
lwz R0, portSRR1_OFFSET( SP )
mtspr SRR1, R0
lwz R0, portSRR0_OFFSET( SP )
mtspr SRR0, R0
lwz R0, portUSPRG0_OFFSET( SP )
mtspr 256, R0 #USPRG0
lwz R0, portCTR_OFFSET( SP )
mtspr CTR, R0
lwz R0, portLR_OFFSET( SP )
mtspr LR, R0
lwz R0, portXER_OFFSET( SP )
mtspr XER, R0
lwz R0, portCR_OFFSET( SP )
mtcr R0
# Pop GPRs
lmw R2, portGPR_OFFSET( SP )
# Finally pop R0 and correct the stack pointer
lwz R0, portR0_OFFSET( SP )
addi R1, R1, portCONTEXT_SIZE
# Start the task running
rfi
.endm
.macro portSAVE_CONTEXT
# Make room on the stack.
subi R1, R1, portCONTEXT_SIZE
# Push R0, then the GPRs
stw R0, portR0_OFFSET( SP )
stm R2, portGPR_OFFSET( SP )
# Push the SFRs
mfcr R0
stw R0, portCR_OFFSET( SP )
mfspr R0, XER
stw R0, portXER_OFFSET( SP )
mfspr R0, LR
stw R0, portLR_OFFSET( SP )
mfspr R0, CTR
stw R0, portCTR_OFFSET( SP )
mfspr R0, 256 #USPRG0
stw R0, portUSPRG0_OFFSET( SP )
mfspr R0, SRR0
stw R0, portSRR0_OFFSET( SP )
mfspr R0, SRR1
stw R0, portSRR1_OFFSET( SP )
# Get the address of the TCB.
xor R0, R0, R0
addis R2, R0, pxCurrentTCB@ha
lwz R2, pxCurrentTCB@l( R2 )
# Store the stack pointer into the TCB
stw SP, 0( R2 )
.endm
.macro int_epilogue
# Get the address of the TCB.
xor R0, R0, R0
addis SP, R0, pxCurrentTCB@ha
lwz SP, pxCurrentTCB@l( SP )
# Get the task stack pointer from the TCB.
lwz SP, 0( SP )
# Restore MSR register to SRR1.
lwz R0,MSRField(R1)
mtsrr1 R0
# Restore current PC location to SRR0.
lwz R0,PCField(R1)
mtsrr0 R0
# Save USPRG0 register
lwz R0,USPRG0Field(R1)
mtspr 0x100,R0
# Restore Condition register
lwz R0,CRField(R1)
mtcr R0
# Restore Fixed Point Exception register
lwz R0,XERField(R1)
mtxer R0
# Restore Counter register
lwz R0,CTRField(R1)
mtctr R0
# Restore Link register
lwz R0,LRField(R1)
mtlr R0
# Restore remaining GPR registers.
lmw R3,r3r31Field(R1)
# Restore r0 and r2.
lwz R0,r0Field(R1)
lwz R2,r2Field(R1)
# Remove frame from stack
addi R1,R1,IFrameSize
.endm
.macro portENTER_SWITCHING_ISR
# Get the address of the TCB. # Get the address of the TCB.
xor R0, R0, R0 xor R0, R0, R0
@ -180,7 +44,7 @@
.endm .endm
.macro portEXIT_SWITCHING_ISR .macro portRESTORE_STACK_POINTER_AND_LR
# Restore the link register # Restore the link register
lwz R11, 0( R1 ) lwz R11, 0( R1 )
@ -202,25 +66,67 @@
vPortStartFirstTask: vPortStartFirstTask:
int_epilogue # Get the address of the TCB.
rfi xor R0, R0, R0
addis SP, R0, pxCurrentTCB@ha
lwz SP, pxCurrentTCB@l( SP )
#vPortStartFirstTask: # Get the task stack pointer from the TCB.
# portRESTORE_CONTEXT lwz SP, 0( SP )
# rfi
# Restore MSR register to SRR1.
lwz R0, MSRField(R1)
mtsrr1 R0
# Restore current PC location to SRR0.
lwz R0, PCField(R1)
mtsrr0 R0
# Save USPRG0 register
lwz R0, USPRG0Field(R1)
mtspr 0x100,R0
# Restore Condition register
lwz R0, CRField(R1)
mtcr R0
# Restore Fixed Point Exception register
lwz R0, XERField(R1)
mtxer R0
# Restore Counter register
lwz R0, CTRField(R1)
mtctr R0
# Restore Link register
lwz R0, LRField(R1)
mtlr R0
# Restore remaining GPR registers.
lmw R3,r3r31Field(R1)
# Restore r0 and r2.
lwz R0, r0Field(R1)
lwz R2, r2Field(R1)
# Remove frame from stack
addi R1,R1,IFrameSize
# Return into the first task
rfi
vPortYield: vPortYield:
portENTER_SWITCHING_ISR portSAVE_STACK_POINTER_AND_LR
bl vTaskSwitchContext bl vTaskSwitchContext
portEXIT_SWITCHING_ISR portRESTORE_STACK_POINTER_AND_LR
blr blr
vPortTickISR: vPortTickISR:
portENTER_SWITCHING_ISR portSAVE_STACK_POINTER_AND_LR
bl vTaskIncrementTick bl vTaskIncrementTick
#if configUSE_PREEMPTION == 1 #if configUSE_PREEMPTION == 1
bl vTaskSwitchContext bl vTaskSwitchContext
@ -230,12 +136,12 @@ vPortTickISR:
lis R0, 2048 lis R0, 2048
mttsr R0 mttsr R0
portEXIT_SWITCHING_ISR portRESTORE_STACK_POINTER_AND_LR
blr blr
vPortISRWrapper: vPortISRWrapper:
portENTER_SWITCHING_ISR portSAVE_STACK_POINTER_AND_LR
bl vPortISRHandler bl vPortISRHandler
portEXIT_SWITCHING_ISR portRESTORE_STACK_POINTER_AND_LR
blr blr

5
Source/portable/GCC/PPC405_Xilinx/portmacro.h
View file

@ -77,6 +77,8 @@ extern "C" {
#endif #endif
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
/* This port uses the critical nesting count from the TCB rather than
maintaining a separate value and then saving this value in the task stack. */
#define portCRITICAL_NESTING_IN_TCB 1 #define portCRITICAL_NESTING_IN_TCB 1
/* Interrupt control macros. */ /* Interrupt control macros. */
@ -97,6 +99,7 @@ void vTaskExitCritical( void );
void vPortYield( void ); void vPortYield( void );
#define portYIELD() asm volatile ( "SC \n\t NOP" ) #define portYIELD() asm volatile ( "SC \n\t NOP" )
#define portYIELD_FROM_ISR() vTaskSwitchContext() #define portYIELD_FROM_ISR() vTaskSwitchContext()
/*-----------------------------------------------------------*/ /*-----------------------------------------------------------*/
/* Hardware specifics. */ /* Hardware specifics. */
@ -110,7 +113,7 @@ void vPortYield( void );
#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) #define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) #define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
/* Port specific initialisation function. */ /* Port specific interrupt handling functions. */
void vPortSetupInterruptController( void ); void vPortSetupInterruptController( void );
portBASE_TYPE xPortInstallInterruptHandler( unsigned portCHAR ucInterruptID, XInterruptHandler pxHandler, void *pvCallBackRef ); portBASE_TYPE xPortInstallInterruptHandler( unsigned portCHAR ucInterruptID, XInterruptHandler pxHandler, void *pvCallBackRef );