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Added demo for the MB9A314 - the IAR project is working, the Keil one is not set up for the correct chip yet.

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Richard Barry 2011-08-30 20:32:41 +00:00
parent 9c92745440
commit bcbd6c8a7d
24 changed files with 27442 additions and 0 deletions
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167
Demo/CORTEX_MB9A310_IAR_Keil/FreeRTOSConfig.h Normal file
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/*
FreeRTOS V7.0.1 - Copyright (C) 2011 Real Time Engineers Ltd.
FreeRTOS supports many tools and architectures. V7.0.0 is sponsored by:
Atollic AB - Atollic provides professional embedded systems development
tools for C/C++ development, code analysis and test automation.
See http://www.atollic.com
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>NOTE<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel. FreeRTOS is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details. You should have received a copy of the GNU General Public
License and the FreeRTOS license exception along with FreeRTOS; if not it
can be viewed here: http://www.freertos.org/a00114.html and also obtained
by writing to Richard Barry, contact details for whom are available on the
FreeRTOS WEB site.
1 tab == 4 spaces!
http://www.FreeRTOS.org - Documentation, latest information, license and
contact details.
http://www.SafeRTOS.com - A version that is certified for use in safety
critical systems.
http://www.OpenRTOS.com - Commercial support, development, porting,
licensing and training services.
*/
#ifndef FREERTOS_CONFIG_H
#define FREERTOS_CONFIG_H
/*-----------------------------------------------------------
* Application specific definitions.
*
* These definitions should be adjusted for your particular hardware and
* application requirements.
*
* THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
* FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
*
* See http://www.freertos.org/a00110.html.
*----------------------------------------------------------*/
/* Use a guard to ensure the following few definitions are'nt included in
assembly files that include this header file. */
#ifndef __IASMARM__
#include <stdint.h>
extern uint32_t SystemCoreClock;
#endif
#define configUSE_PREEMPTION 1
#define configUSE_IDLE_HOOK 1
#define configUSE_TICK_HOOK 1
#define configCPU_CLOCK_HZ ( SystemCoreClock )
#define configTICK_RATE_HZ ( ( portTickType ) 1000 )
#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 )
#define configMINIMAL_STACK_SIZE ( ( unsigned short ) 90 )
#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 30 * 1024 ) )
#define configMAX_TASK_NAME_LEN ( 10 )
#define configUSE_TRACE_FACILITY 1
#define configUSE_16_BIT_TICKS 0
#define configIDLE_SHOULD_YIELD 1
#define configUSE_MUTEXES 1
#define configQUEUE_REGISTRY_SIZE 0
#define configGENERATE_RUN_TIME_STATS 0
#define configCHECK_FOR_STACK_OVERFLOW 2
#define configUSE_RECURSIVE_MUTEXES 1
#define configUSE_MALLOC_FAILED_HOOK 1
#define configUSE_APPLICATION_TASK_TAG 0
#define configUSE_COUNTING_SEMAPHORES 1
/* Co-routine definitions. */
#define configUSE_CO_ROUTINES 0
#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
/* Software timer definitions. */
#define configUSE_TIMERS 1
#define configTIMER_TASK_PRIORITY ( 2 )
#define configTIMER_QUEUE_LENGTH 10
#define configTIMER_TASK_STACK_DEPTH ( configMINIMAL_STACK_SIZE * 2 )
/* Set the following definitions to 1 to include the API function, or zero
to exclude the API function. */
#define INCLUDE_vTaskPrioritySet 1
#define INCLUDE_uxTaskPriorityGet 1
#define INCLUDE_vTaskDelete 1
#define INCLUDE_vTaskCleanUpResources 1
#define INCLUDE_vTaskSuspend 1
#define INCLUDE_vTaskDelayUntil 1
#define INCLUDE_vTaskDelay 1
/* Use the system definition, if there is one */
#ifdef __NVIC_PRIO_BITS
#define configPRIO_BITS __NVIC_PRIO_BITS
#else
#define configPRIO_BITS 4 /* 15 priority levels */
#endif
#define configLIBRARY_LOWEST_INTERRUPT_PRIORITY 0xf
#define configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY 5
/* The lowest priority. */
#define configKERNEL_INTERRUPT_PRIORITY ( configLIBRARY_LOWEST_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
/* Priority 5, or 160 as only the top three bits are implemented. */
#define configMAX_SYSCALL_INTERRUPT_PRIORITY ( configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS) )
#define configASSERT( x ) if( ( x ) == 0 ) { taskDISABLE_INTERRUPTS(); for( ;; ); }
#define vPortSVCHandler SVC_Handler
#define xPortPendSVHandler PendSV_Handler
#define vPortSVCHandler SVC_Handler
#define xPortSysTickHandler SysTick_Handler
/* MAC address configuration. */
#define configMAC_ADDR0 0x00
#define configMAC_ADDR1 0x12
#define configMAC_ADDR2 0x13
#define configMAC_ADDR3 0x10
#define configMAC_ADDR4 0x15
#define configMAC_ADDR5 0x11
/* IP address configuration. */
#define configIP_ADDR0 192
#define configIP_ADDR1 168
#define configIP_ADDR2 0
#define configIP_ADDR3 200
/* Netmask configuration. */
#define configNET_MASK0 255
#define configNET_MASK1 255
#define configNET_MASK2 255
#define configNET_MASK3 0
#endif /* FREERTOS_CONFIG_H */

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Demo/CORTEX_MB9A310_IAR_Keil/Fujitu_source/core_cm3.c Normal file
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/**************************************************************************//**
* @file core_cm3.c
* @brief CMSIS Cortex-M3 Core Peripheral Access Layer Source File
* @version V1.40
* @date 18. February 2010
*
* @note
* Copyright (C) 2009-2010 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#include <stdint.h>
/* define compiler specific symbols */
#if defined ( __CC_ARM )
#define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
#elif defined ( __ICCARM__ )
#define __ASM __asm /*!< asm keyword for IAR Compiler */
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
#elif defined ( __GNUC__ )
#define __ASM __asm /*!< asm keyword for GNU Compiler */
#define __INLINE inline /*!< inline keyword for GNU Compiler */
#elif defined ( __TASKING__ )
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
#endif
/* ########################## Core Instruction Access ######################### */
#if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/
/**
* @brief Reverse byte order (16 bit)
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in unsigned short value
*/
#if (__ARMCC_VERSION < 400677)
__ASM uint32_t __REV16(uint16_t value)
{
rev16 r0, r0
bx lr
}
#endif /* __ARMCC_VERSION */
/**
* @brief Reverse byte order in signed short value with sign extension to integer
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in signed short value with sign extension to integer
*/
#if (__ARMCC_VERSION < 400677)
__ASM int32_t __REVSH(int16_t value)
{
revsh r0, r0
bx lr
}
#endif /* __ARMCC_VERSION */
/**
* @brief Remove the exclusive lock created by ldrex
*
* Removes the exclusive lock which is created by ldrex.
*/
#if (__ARMCC_VERSION < 400000)
__ASM void __CLREX(void)
{
clrex
}
#endif /* __ARMCC_VERSION */
#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
/* obsolete */
#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
/* obsolete */
#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
/* obsolete */
#endif
/* ########################### Core Function Access ########################### */
#if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/
/**
* @brief Return the Control Register value
*
* @return Control value
*
* Return the content of the control register
*/
#if (__ARMCC_VERSION < 400000)
__ASM uint32_t __get_CONTROL(void)
{
mrs r0, control
bx lr
}
#endif /* __ARMCC_VERSION */
/**
* @brief Set the Control Register value
*
* @param control Control value
*
* Set the control register
*/
#if (__ARMCC_VERSION < 400000)
__ASM void __set_CONTROL(uint32_t control)
{
msr control, r0
bx lr
}
#endif /* __ARMCC_VERSION */
/**
* @brief Get IPSR Register value
*
* @return uint32_t IPSR value
*
* return the content of the IPSR register
*/
#if (__ARMCC_VERSION < 400000)
__ASM uint32_t __get_IPSR(void)
{
mrs r0, ipsr
bx lr
}
#endif /* __ARMCC_VERSION */
/**
* @brief Get APSR Register value
*
* @return uint32_t APSR value
*
* return the content of the APSR register
*/
#if (__ARMCC_VERSION < 400000)
__ASM uint32_t __get_APSR(void)
{
mrs r0, apsr
bx lr
}
#endif /* __ARMCC_VERSION */
/**
* @brief Get xPSR Register value
*
* @return uint32_t xPSR value
*
* return the content of the xPSR register
*/
#if (__ARMCC_VERSION < 400000)
__ASM uint32_t __get_xPSR(void)
{
mrs r0, xpsr
bx lr
}
#endif /* __ARMCC_VERSION */
/**
* @brief Return the Process Stack Pointer
*
* @return ProcessStackPointer
*
* Return the actual process stack pointer
*/
#if (__ARMCC_VERSION < 400000)
__ASM uint32_t __get_PSP(void)
{
mrs r0, psp
bx lr
}
#endif /* __ARMCC_VERSION */
/**
* @brief Set the Process Stack Pointer
*
* @param topOfProcStack Process Stack Pointer
*
* Assign the value ProcessStackPointer to the MSP
* (process stack pointer) Cortex processor register
*/
#if (__ARMCC_VERSION < 400000)
__ASM void __set_PSP(uint32_t topOfProcStack)
{
msr psp, r0
bx lr
}
#endif /* __ARMCC_VERSION */
/**
* @brief Return the Main Stack Pointer
*
* @return Main Stack Pointer
*
* Return the current value of the MSP (main stack pointer)
* Cortex processor register
*/
#if (__ARMCC_VERSION < 400000)
__ASM uint32_t __get_MSP(void)
{
mrs r0, msp
bx lr
}
#endif /* __ARMCC_VERSION */
/**
* @brief Set the Main Stack Pointer
*
* @param topOfMainStack Main Stack Pointer
*
* Assign the value mainStackPointer to the MSP
* (main stack pointer) Cortex processor register
*/
#if (__ARMCC_VERSION < 400000)
__ASM void __set_MSP(uint32_t mainStackPointer)
{
msr msp, r0
bx lr
}
#endif /* __ARMCC_VERSION */
/**
* @brief Return the Base Priority value
*
* @return BasePriority
*
* Return the content of the base priority register
*/
#if (__ARMCC_VERSION < 400000)
__ASM uint32_t __get_BASEPRI(void)
{
mrs r0, basepri
bx lr
}
#endif /* __ARMCC_VERSION */
/**
* @brief Set the Base Priority value
*
* @param basePri BasePriority
*
* Set the base priority register
*/
#if (__ARMCC_VERSION < 400000)
__ASM void __set_BASEPRI(uint32_t basePri)
{
msr basepri, r0
bx lr
}
#endif /* __ARMCC_VERSION */
/**
* @brief Return the Priority Mask value
*
* @return PriMask
*
* Return state of the priority mask bit from the priority mask register
*/
#if (__ARMCC_VERSION < 400000)
__ASM uint32_t __get_PRIMASK(void)
{
mrs r0, primask
bx lr
}
#endif /* __ARMCC_VERSION */
/**
* @brief Set the Priority Mask value
*
* @param priMask PriMask
*
* Set the priority mask bit in the priority mask register
*/
#if (__ARMCC_VERSION < 400000)
__ASM void __set_PRIMASK(uint32_t priMask)
{
msr primask, r0
bx lr
}
#endif /* __ARMCC_VERSION */
/**
* @brief Return the Fault Mask value
*
* @return FaultMask
*
* Return the content of the fault mask register
*/
#if (__ARMCC_VERSION < 400000)
__ASM uint32_t __get_FAULTMASK(void)
{
mrs r0, faultmask
bx lr
}
#endif /* __ARMCC_VERSION */
/**
* @brief Set the Fault Mask value
*
* @param faultMask faultMask value
*
* Set the fault mask register
*/
#if (__ARMCC_VERSION < 400000)
__ASM void __set_FAULTMASK(uint32_t faultMask)
{
msr faultmask, r0
bx lr
}
#endif /* __ARMCC_VERSION */
/**
* @brief Return the FPSCR value
*
* @return FloatingPointStatusControlRegister
*
* Return the content of the FPSCR register
*/
/**
* @brief Set the FPSCR value
*
* @param fpscr FloatingPointStatusControlRegister
*
* Set the FPSCR register
*/
#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
/* obsolete */
#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
/* obsolete */
#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
/* obsolete */
#endif

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Demo/CORTEX_MB9A310_IAR_Keil/Fujitu_source/mb9af314l.h Normal file
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/************************************************************************/
/* (C) Fujitsu Semiconductor Europe GmbH (FSEU) */
/* */
/* The following software deliverable is intended for and must only be */
/* used for reference and in an evaluation laboratory environment. */
/* It is provided on an as-is basis without charge and is subject to */
/* alterations. */
/* It is the user's obligation to fully test the software in its */
/* environment and to ensure proper functionality, qualification and */
/* compliance with component specifications. */
/* */
/* In the event the software deliverable includes the use of open */
/* source components, the provisions of the governing open source */
/* license agreement shall apply with respect to such software */
/* deliverable. */
/* FSEU does not warrant that the deliverables do not infringe any */
/* third party intellectual property right (IPR). In the event that */
/* the deliverables infringe a third party IPR it is the sole */
/* responsibility of the customer to obtain necessary licenses to */
/* continue the usage of the deliverable. */
/* */
/* To the maximum extent permitted by applicable law FSEU disclaims all */
/* warranties, whether express or implied, in particular, but not */
/* limited to, warranties of merchantability and fitness for a */
/* particular purpose for which the deliverable is not designated. */
/* */
/* To the maximum extent permitted by applicable law, FSEU's liability */
/* is restricted to intentional misconduct and gross negligence. */
/* FSEU is not liable for consequential damages. */
/* */
/* (V1.5) */
/************************************************************************/
/**
******************************************************************************
** \file mcu.h
**
** Header File for device dependent includes
**
** History:
** 2011-05-19 V1.00 MWi first version
**
******************************************************************************/
/**
******************************************************************************
** \brief MCU header file include
**
******************************************************************************/
#ifndef _MB9AF314L_H_
#include "mb9af314l.h"
#endif
/**
******************************************************************************
** \brief MCU system start-up header file include
**
******************************************************************************/
#ifndef _SYSTEM_MB9AF31X_H_
#include "system_mb9af31x.h"
#endif

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Demo/CORTEX_MB9A310_IAR_Keil/Fujitu_source/startup_iar/startup_mb9af31x.s Normal file
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;/************************************************************************/
;/* (C) Fujitsu Semiconductor Europe GmbH (FSEU) */
;/* */
;/* The following software deliverable is intended for and must only be */
;/* used for reference and in an evaluation laboratory environment. */
;/* It is provided on an as-is basis without charge and is subject to */
;/* alterations. */
;/* It is the user's obligation to fully test the software in its */
;/* environment and to ensure proper functionality, qualification and */
;/* compliance with component specifications. */
;/* */
;/* In the event the software deliverable includes the use of open */
;/* source components, the provisions of the governing open source */
;/* license agreement shall apply with respect to such software */
;/* deliverable. */
;/* FSEU does not warrant that the deliverables do not infringe any */
;/* third party intellectual property right (IPR). In the event that */
;/* the deliverables infringe a third party IPR it is the sole */
;/* responsibility of the customer to obtain necessary licenses to */
;/* continue the usage of the deliverable. */
;/* */
;/* To the maximum extent permitted by applicable law FSEU disclaims all */
;/* warranties, whether express or implied, in particular, but not */
;/* limited to, warranties of merchantability and fitness for a */
;/* particular purpose for which the deliverable is not designated. */
;/* */
;/* To the maximum extent permitted by applicable law, FSEU's liability */
;/* is restricted to intentional misconduct and gross negligence. */
;/* FSEU is not liable for consequential damages. */
;/* */
;/* (V1.5) */
;/************************************************************************/
;/* Startup for IAR */
;/* Version V1.03 */
;/* Date 2011-05-17 */
;/* Target-mcu MB9A310 */
;/************************************************************************/
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table DCD sfe(CSTACK) ; Top of Stack
DCD Reset_Handler ; Reset
DCD NMI_Handler ; NMI
DCD HardFault_Handler ; Hard Fault
DCD MemManage_Handler ; MPU Fault
DCD BusFault_Handler ; Bus Fault
DCD UsageFault_Handler ; Usage Fault
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall
DCD DebugMon_Handler ; Debug Monitor
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV
DCD SysTick_Handler ; SysTick
DCD CSV_Handler ; 0: Clock Super Visor
DCD SWDT_Handler ; 1: Software Watchdog Timer
DCD LVD_Handler ; 2: Low Voltage Detector
DCD MFT_WG_IRQHandler ; 3: Wave Form Generator / DTIF
DCD INT0_7_Handler ; 4: External Interrupt Request ch.0 to ch.7
DCD INT8_15_Handler ; 5: External Interrupt Request ch.8 to ch.15
DCD DT_Handler ; 6: Dual Timer / Quad Decoder
DCD MFS0RX_IRQHandler ; 7: MultiFunction Serial ch.0
DCD MFS0TX_IRQHandler ; 8: MultiFunction Serial ch.0
DCD MFS1RX_IRQHandler ; 9: MultiFunction Serial ch.1
DCD MFS1TX_IRQHandler ; 10: MultiFunction Serial ch.1
DCD MFS2RX_IRQHandler ; 11: MultiFunction Serial ch.2
DCD MFS2TX_IRQHandler ; 12: MultiFunction Serial ch.2
DCD MFS3RX_IRQHandler ; 13: MultiFunction Serial ch.3
DCD MFS3TX_IRQHandler ; 14: MultiFunction Serial ch.3
DCD MFS4RX_IRQHandler ; 15: MultiFunction Serial ch.4
DCD MFS4TX_IRQHandler ; 16: MultiFunction Serial ch.4
DCD MFS5RX_IRQHandler ; 17: MultiFunction Serial ch.5
DCD MFS5TX_IRQHandler ; 18: MultiFunction Serial ch.5
DCD MFS6RX_IRQHandler ; 19: MultiFunction Serial ch.6
DCD MFS6TX_IRQHandler ; 20: MultiFunction Serial ch.6
DCD MFS7RX_IRQHandler ; 21: MultiFunction Serial ch.7
DCD MFS7TX_IRQHandler ; 22: MultiFunction Serial ch.7
DCD PPG_Handler ; 23: PPG
DCD TIM_IRQHandler ; 24: OSC / PLL / Watch Counter
DCD ADC0_IRQHandler ; 25: ADC0
DCD ADC1_IRQHandler ; 26: ADC1
DCD ADC2_IRQHandler ; 27: ADC2
DCD MFT_FRT_IRQHandler ; 28: Free-run Timer
DCD MFT_IPC_IRQHandler ; 29: Input Capture
DCD MFT_OPC_IRQHandler ; 30: Output Compare
DCD BT_IRQHandler ; 31: Base Timer ch.0 to ch.7
DCD DummyHandler ; 32: Reserved
DCD DummyHandler ; 33: Reserved
DCD USBF_Handler ; 34: USB Function
DCD USB_Handler ; 35: USB Function / USB HOST
DCD DummyHandler ; 36: Reserved
DCD DummyHandler ; 37: Reserved
DCD DMAC0_Handler ; 38: DMAC ch.0
DCD DMAC1_Handler ; 39: DMAC ch.1
DCD DMAC2_Handler ; 40: DMAC ch.2
DCD DMAC3_Handler ; 41: DMAC ch.3
DCD DMAC4_Handler ; 42: DMAC ch.4
DCD DMAC5_Handler ; 43: DMAC ch.5
DCD DMAC6_Handler ; 44: DMAC ch.6
DCD DMAC7_Handler ; 45: DMAC ch.7
DCD DummyHandler ; 46: Reserved
DCD DummyHandler ; 47: Reserved
THUMB
; Dummy Exception Handlers (infinite loops which can be modified)
PUBWEAK Reset_Handler
SECTION .text:CODE:REORDER(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:REORDER(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:REORDER(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:REORDER(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:REORDER(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:REORDER(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:REORDER(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK CSV_Handler
SECTION .text:CODE:REORDER(1)
CSV_Handler
B CSV_Handler
PUBWEAK SWDT_Handler
SECTION .text:CODE:REORDER(1)
SWDT_Handler
B SWDT_Handler
PUBWEAK LVD_Handler
SECTION .text:CODE:REORDER(1)
LVD_Handler
B LVD_Handler
PUBWEAK MFT_WG_IRQHandler
SECTION .text:CODE:REORDER(1)
MFT_WG_IRQHandler
B MFT_WG_IRQHandler
PUBWEAK INT0_7_Handler
SECTION .text:CODE:REORDER(1)
INT0_7_Handler
B INT0_7_Handler
PUBWEAK INT8_15_Handler
SECTION .text:CODE:REORDER(1)
INT8_15_Handler
B INT8_15_Handler
PUBWEAK DT_Handler
SECTION .text:CODE:REORDER(1)
DT_Handler
B DT_Handler
PUBWEAK MFS0RX_IRQHandler
SECTION .text:CODE:REORDER(1)
MFS0RX_IRQHandler
B MFS0RX_IRQHandler
PUBWEAK MFS0TX_IRQHandler
SECTION .text:CODE:REORDER(1)
MFS0TX_IRQHandler
B MFS0TX_IRQHandler
PUBWEAK MFS1RX_IRQHandler
SECTION .text:CODE:REORDER(1)
MFS1RX_IRQHandler
B MFS1RX_IRQHandler
PUBWEAK MFS1TX_IRQHandler
SECTION .text:CODE:REORDER(1)
MFS1TX_IRQHandler
B MFS1TX_IRQHandler
PUBWEAK MFS2RX_IRQHandler
SECTION .text:CODE:REORDER(1)
MFS2RX_IRQHandler
B MFS2RX_IRQHandler
PUBWEAK MFS2TX_IRQHandler
SECTION .text:CODE:REORDER(1)
MFS2TX_IRQHandler
B MFS2TX_IRQHandler
PUBWEAK MFS3RX_IRQHandler
SECTION .text:CODE:REORDER(1)
MFS3RX_IRQHandler
B MFS3RX_IRQHandler
PUBWEAK MFS3TX_IRQHandler
SECTION .text:CODE:REORDER(1)
MFS3TX_IRQHandler
B MFS3TX_IRQHandler
PUBWEAK MFS4RX_IRQHandler
SECTION .text:CODE:REORDER(1)
MFS4RX_IRQHandler
B MFS4RX_IRQHandler
PUBWEAK MFS4TX_IRQHandler
SECTION .text:CODE:REORDER(1)
MFS4TX_IRQHandler
B MFS4TX_IRQHandler
PUBWEAK MFS5RX_IRQHandler
SECTION .text:CODE:REORDER(1)
MFS5RX_IRQHandler
B MFS5RX_IRQHandler
PUBWEAK MFS5TX_IRQHandler
SECTION .text:CODE:REORDER(1)
MFS5TX_IRQHandler
B MFS5TX_IRQHandler
PUBWEAK MFS6RX_IRQHandler
SECTION .text:CODE:REORDER(1)
MFS6RX_IRQHandler
B MFS6RX_IRQHandler
PUBWEAK MFS6TX_IRQHandler
SECTION .text:CODE:REORDER(1)
MFS6TX_IRQHandler
B MFS6TX_IRQHandler
PUBWEAK MFS7RX_IRQHandler
SECTION .text:CODE:REORDER(1)
MFS7RX_IRQHandler
B MFS7RX_IRQHandler
PUBWEAK MFS7TX_IRQHandler
SECTION .text:CODE:REORDER(1)
MFS7TX_IRQHandler
B MFS7TX_IRQHandler
PUBWEAK PPG_Handler
SECTION .text:CODE:REORDER(1)
PPG_Handler
B PPG_Handler
PUBWEAK TIM_IRQHandler
SECTION .text:CODE:REORDER(1)
TIM_IRQHandler
B TIM_IRQHandler
PUBWEAK ADC0_IRQHandler
SECTION .text:CODE:REORDER(1)
ADC0_IRQHandler
B ADC0_IRQHandler
PUBWEAK ADC1_IRQHandler
SECTION .text:CODE:REORDER(1)
ADC1_IRQHandler
B ADC1_IRQHandler
PUBWEAK ADC2_IRQHandler
SECTION .text:CODE:REORDER(1)
ADC2_IRQHandler
B ADC2_IRQHandler
PUBWEAK MFT_FRT_IRQHandler
SECTION .text:CODE:REORDER(1)
MFT_FRT_IRQHandler
B MFT_FRT_IRQHandler
PUBWEAK MFT_IPC_IRQHandler
SECTION .text:CODE:REORDER(1)
MFT_IPC_IRQHandler
B MFT_IPC_IRQHandler
PUBWEAK MFT_OPC_IRQHandler
SECTION .text:CODE:REORDER(1)
MFT_OPC_IRQHandler
B MFT_OPC_IRQHandler
PUBWEAK BT_IRQHandler
SECTION .text:CODE:REORDER(1)
BT_IRQHandler
B BT_IRQHandler
PUBWEAK USBF_Handler
SECTION .text:CODE:REORDER(1)
USBF_Handler
B USBF_Handler
PUBWEAK USB_Handler
SECTION .text:CODE:REORDER(1)
USB_Handler
B USB_Handler
PUBWEAK DMAC0_Handler
SECTION .text:CODE:REORDER(1)
DMAC0_Handler
B DMAC0_Handler
PUBWEAK DMAC1_Handler
SECTION .text:CODE:REORDER(1)
DMAC1_Handler
B DMAC1_Handler
PUBWEAK DMAC2_Handler
SECTION .text:CODE:REORDER(1)
DMAC2_Handler
B DMAC2_Handler
PUBWEAK DMAC3_Handler
SECTION .text:CODE:REORDER(1)
DMAC3_Handler
B DMAC3_Handler
PUBWEAK DMAC4_Handler
SECTION .text:CODE:REORDER(1)
DMAC4_Handler
B DMAC4_Handler
PUBWEAK DMAC5_Handler
SECTION .text:CODE:REORDER(1)
DMAC5_Handler
B DMAC5_Handler
PUBWEAK DMAC6_Handler
SECTION .text:CODE:REORDER(1)
DMAC6_Handler
B DMAC6_Handler
PUBWEAK DMAC7_Handler
SECTION .text:CODE:REORDER(1)
DMAC7_Handler
B DMAC7_Handler
PUBWEAK DummyHandler
SECTION .text:CODE:REORDER(1)
DummyHandler
B DummyHandler
END

327
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;/************************************************************************/
;/* (C) Fujitsu Semiconductor Europe GmbH */
;/* */
;/* The following software deliverable is intended for and must only be */
;/* used for reference and in an evaluation laboratory environment. */
;/* It is provided on an as-is basis without charge and is subject to */
;/* alterations. */
;/* It is the user’s obligation to fully test the software in its */
;/* environment and to ensure proper functionality, qualification and */
;/* compliance with component specifications. */
;/* */
;/* In the event the software deliverable includes the use of open */
;/* source components, the provisions of the governing open source */
;/* license agreement shall apply with respect to such software */
;/* deliverable. */
;/* FSEU does not warrant that the deliverables do not infringe any */
;/* third party intellectual property right (IPR). In the event that */
;/* the deliverables infringe a third party IPR it is the sole */
;/* responsibility of the customer to obtain necessary licenses to */
;/* continue the usage of the deliverable. */
;/* */
;/* To the maximum extent permitted by applicable law FSEU disclaims all */
;/* warranties, whether express or implied, in particular, but not */
;/* limited to, warranties of merchantability and fitness for a */
;/* particular purpose for which the deliverable is not designated. */
;/* */
;/* To the maximum extent permitted by applicable law, FSEU's liability */
;/* is restricted to intention and gross negligence. */
;/* FSEU is not liable for consequential damages. */
;/* */
;/* (V1.4) */
;/************************************************************************/
;/* Startup for ARM */
;/* Version V1.02 */
;/* Date 2011-01-12 */
;/* Target-mcu MB9B5xx */
;/************************************************************************/
; Stack Configuration
; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
Stack_Size EQU 0x00000200
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; Heap Configuration
; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
Heap_Size EQU 0x00000000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
DCD CSV_Handler ; 0: Clock Super Visor
DCD SWDT_Handler ; 1: Software Watchdog Timer
DCD LVD_Handler ; 2: Low Voltage Detector
DCD MFT_WG_IRQHandler ; 3: Wave Form Generator / DTIF
DCD INT0_7_Handler ; 4: External Interrupt Request ch.0 to ch.7
DCD INT8_15_Handler ; 5: External Interrupt Request ch.8 to ch.15
DCD DT_Handler ; 6: Dual Timer / Quad Decoder
DCD MFS0RX_IRQHandler ; 7: MultiFunction Serial ch.0
DCD MFS0TX_IRQHandler ; 8: MultiFunction Serial ch.0
DCD MFS1RX_IRQHandler ; 9: MultiFunction Serial ch.1
DCD MFS1TX_IRQHandler ; 10: MultiFunction Serial ch.1
DCD MFS2RX_IRQHandler ; 11: MultiFunction Serial ch.2
DCD MFS2TX_IRQHandler ; 12: MultiFunction Serial ch.2
DCD MFS3RX_IRQHandler ; 13: MultiFunction Serial ch.3
DCD MFS3TX_IRQHandler ; 14: MultiFunction Serial ch.3
DCD MFS4RX_IRQHandler ; 15: MultiFunction Serial ch.4
DCD MFS4TX_IRQHandler ; 16: MultiFunction Serial ch.4
DCD MFS5RX_IRQHandler ; 17: MultiFunction Serial ch.5
DCD MFS5TX_IRQHandler ; 18: MultiFunction Serial ch.5
DCD MFS6RX_IRQHandler ; 19: MultiFunction Serial ch.6
DCD MFS6TX_IRQHandler ; 20: MultiFunction Serial ch.6
DCD MFS7RX_IRQHandler ; 21: MultiFunction Serial ch.7
DCD MFS7TX_IRQHandler ; 22: MultiFunction Serial ch.7
DCD PPG_Handler ; 23: PPG
DCD TIM_IRQHandler ; 24: OSC / PLL / Watch Counter
DCD ADC0_IRQHandler ; 25: ADC0
DCD ADC1_IRQHandler ; 26: ADC1
DCD ADC2_IRQHandler ; 27: ADC2
DCD MFT_FRT_IRQHandler ; 28: Free-run Timer
DCD MFT_IPC_IRQHandler ; 29: Input Capture
DCD MFT_OPC_IRQHandler ; 30: Output Compare
DCD BT_IRQHandler ; 31: Base Timer ch.0 to ch.7
DCD CAN0_IRQHandler ; 32: CAN ch.0
DCD CAN1_IRQHandler ; 33: CAN ch.1
DCD USBF_Handler ; 34: USB Function
DCD USB_Handler ; 35: USB Function / USB HOST
DCD DummyHandler ; 36: Reserved
DCD DummyHandler ; 37: Reserved
DCD DMAC0_Handler ; 38: DMAC ch.0
DCD DMAC1_Handler ; 39: DMAC ch.1
DCD DMAC2_Handler ; 40: DMAC ch.2
DCD DMAC3_Handler ; 41: DMAC ch.3
DCD DMAC4_Handler ; 42: DMAC ch.4
DCD DMAC5_Handler ; 43: DMAC ch.5
DCD DMAC6_Handler ; 44: DMAC ch.6
DCD DMAC7_Handler ; 45: DMAC ch.7
DCD DummyHandler ; 46: Reserved
DCD DummyHandler ; 47: Reserved
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT CSV_Handler [WEAK]
EXPORT SWDT_Handler [WEAK]
EXPORT LVD_Handler [WEAK]
EXPORT MFT_WG_IRQHandler [WEAK]
EXPORT INT0_7_Handler [WEAK]
EXPORT INT8_15_Handler [WEAK]
EXPORT DT_Handler [WEAK]
EXPORT MFS0RX_IRQHandler [WEAK]
EXPORT MFS0TX_IRQHandler [WEAK]
EXPORT MFS1RX_IRQHandler [WEAK]
EXPORT MFS1TX_IRQHandler [WEAK]
EXPORT MFS2RX_IRQHandler [WEAK]
EXPORT MFS2TX_IRQHandler [WEAK]
EXPORT MFS3RX_IRQHandler [WEAK]
EXPORT MFS3TX_IRQHandler [WEAK]
EXPORT MFS4RX_IRQHandler [WEAK]
EXPORT MFS4TX_IRQHandler [WEAK]
EXPORT MFS5RX_IRQHandler [WEAK]
EXPORT MFS5TX_IRQHandler [WEAK]
EXPORT MFS6RX_IRQHandler [WEAK]
EXPORT MFS6TX_IRQHandler [WEAK]
EXPORT MFS7RX_IRQHandler [WEAK]
EXPORT MFS7TX_IRQHandler [WEAK]
EXPORT PPG_Handler [WEAK]
EXPORT TIM_IRQHandler [WEAK]
EXPORT ADC0_IRQHandler [WEAK]
EXPORT ADC1_IRQHandler [WEAK]
EXPORT ADC2_IRQHandler [WEAK]
EXPORT MFT_FRT_IRQHandler [WEAK]
EXPORT MFT_IPC_IRQHandler [WEAK]
EXPORT MFT_OPC_IRQHandler [WEAK]
EXPORT BT_IRQHandler [WEAK]
EXPORT CAN0_IRQHandler [WEAK]
EXPORT CAN1_IRQHandler [WEAK]
EXPORT USBF_Handler [WEAK]
EXPORT USB_Handler [WEAK]
EXPORT DMAC0_Handler [WEAK]
EXPORT DMAC1_Handler [WEAK]
EXPORT DMAC2_Handler [WEAK]
EXPORT DMAC3_Handler [WEAK]
EXPORT DMAC4_Handler [WEAK]
EXPORT DMAC5_Handler [WEAK]
EXPORT DMAC6_Handler [WEAK]
EXPORT DMAC7_Handler [WEAK]
EXPORT DummyHandler [WEAK]
CSV_Handler
SWDT_Handler
LVD_Handler
MFT_WG_IRQHandler
INT0_7_Handler
INT8_15_Handler
DT_Handler
MFS0RX_IRQHandler
MFS0TX_IRQHandler
MFS1RX_IRQHandler
MFS1TX_IRQHandler
MFS2RX_IRQHandler
MFS2TX_IRQHandler
MFS3RX_IRQHandler
MFS3TX_IRQHandler
MFS4RX_IRQHandler
MFS4TX_IRQHandler
MFS5RX_IRQHandler
MFS5TX_IRQHandler
MFS6RX_IRQHandler
MFS6TX_IRQHandler
MFS7RX_IRQHandler
MFS7TX_IRQHandler
PPG_Handler
TIM_IRQHandler
ADC0_IRQHandler
ADC1_IRQHandler
ADC2_IRQHandler
MFT_FRT_IRQHandler
MFT_IPC_IRQHandler
MFT_OPC_IRQHandler
BT_IRQHandler
CAN0_IRQHandler
CAN1_IRQHandler
USBF_Handler
USB_Handler
DMAC0_Handler
DMAC1_Handler
DMAC2_Handler
DMAC3_Handler
DMAC4_Handler
DMAC5_Handler
DMAC6_Handler
DMAC7_Handler
DummyHandler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END

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/************************************************************************/
/* (C) Fujitsu Semiconductor Europe GmbH (FSEU) */
/* */
/* The following software deliverable is intended for and must only be */
/* used for reference and in an evaluation laboratory environment. */
/* It is provided on an as-is basis without charge and is subject to */
/* alterations. */
/* It is the user's obligation to fully test the software in its */
/* environment and to ensure proper functionality, qualification and */
/* compliance with component specifications. */
/* */
/* In the event the software deliverable includes the use of open */
/* source components, the provisions of the governing open source */
/* license agreement shall apply with respect to such software */
/* deliverable. */
/* FSEU does not warrant that the deliverables do not infringe any */
/* third party intellectual property right (IPR). In the event that */
/* the deliverables infringe a third party IPR it is the sole */
/* responsibility of the customer to obtain necessary licenses to */
/* continue the usage of the deliverable. */
/* */
/* To the maximum extent permitted by applicable law FSEU disclaims all */
/* warranties, whether express or implied, in particular, but not */
/* limited to, warranties of merchantability and fitness for a */
/* particular purpose for which the deliverable is not designated. */
/* */
/* To the maximum extent permitted by applicable law, FSEU's liability */
/* is restricted to intentional misconduct and gross negligence. */
/* FSEU is not liable for consequential damages. */
/* */
/* (V1.5) */
/************************************************************************/
#include "mcu.h"
/** \file system_mb9af31x.c
**
** FM3 system initialization functions
** All adjustments can be done in belonging header file.
**
** History:
** 2011-05-16 V1.0 MWi original version
******************************************************************************/
/**
******************************************************************************
** System Clock Frequency (Core Clock) Variable according CMSIS
******************************************************************************/
uint32_t SystemCoreClock = __HCLK;
/**
******************************************************************************
** \brief Update the System Core Clock with current core Clock retrieved from
** cpu registers.
** \param none
** \return none
******************************************************************************/
void SystemCoreClockUpdate (void) {
uint32_t masterClk;
uint32_t u32RegisterRead; // Workaround variable for MISRA C rule conformance
switch ((FM3_CRG->SCM_CTL >> 5) & 0x07) {
case 0: /* internal High-speed Cr osc. */
masterClk = __CLKHC;
break;
case 1: /* external main osc. */
masterClk = __CLKMO;
break;
case 2: /* PLL clock */
// Workaround for preventing MISRA C:1998 Rule 46 (MISRA C:2004 Rule 12.2)
// violation:
// "Unordered accesses to a volatile location"
u32RegisterRead = (__CLKMO * (((FM3_CRG->PLL_CTL2) & 0x1F) + 1));
masterClk = (u32RegisterRead / (((FM3_CRG->PLL_CTL1 >> 4) & 0x0F) + 1));
break;
case 4: /* internal Low-speed CR osc. */
masterClk = __CLKLC;
break;
case 5: /* external Sub osc. */
masterClk = __CLKSO;
break;
default:
masterClk = 0Ul;
break;
}
switch (FM3_CRG->BSC_PSR & 0x07) {
case 0:
SystemCoreClock = masterClk;
break;
case 1:
SystemCoreClock = masterClk / 2;
break;
case 2:
SystemCoreClock = masterClk / 3;
break;
case 3:
SystemCoreClock = masterClk / 4;
break;
case 4:
SystemCoreClock = masterClk / 6;
break;
case 5:
SystemCoreClock = masterClk /8;
break;
case 6:
SystemCoreClock = masterClk /16;
break;
default:
SystemCoreClock = 0Ul;
break;
}
}
/**
******************************************************************************
** \brief Setup the microcontroller system. Initialize the System and update
** the SystemCoreClock variable.
**
** \param none
** \return none
******************************************************************************/
void SystemInit (void) {
static uint32_t u32IoRegisterRead; // Workaround variable for MISRA C rule conformance
#if (HWWD_DISABLE) /* HW Watchdog Disable */
FM3_HWWDT->WDG_LCK = 0x1ACCE551; /* HW Watchdog Unlock */
FM3_HWWDT->WDG_LCK = 0xE5331AAE;
FM3_HWWDT->WDG_CTL = 0; /* HW Watchdog stop */
#endif
#if (CLOCK_SETUP) /* Clock Setup */
FM3_CRG->BSC_PSR = BSC_PSR_Val; /* set System Clock presacaler */
FM3_CRG->APBC0_PSR = APBC0_PSR_Val; /* set APB0 presacaler */
FM3_CRG->APBC1_PSR = APBC1_PSR_Val; /* set APB1 presacaler */
FM3_CRG->APBC2_PSR = APBC2_PSR_Val; /* set APB2 presacaler */
FM3_CRG->SWC_PSR = SWC_PSR_Val | (1UL << 7); /* set SW Watchdog presacaler */
FM3_CRG->TTC_PSR = TTC_PSR_Val; /* set Trace Clock presacaler */
FM3_CRG->CSW_TMR = CSW_TMR_Val; /* set oscillation stabilization wait time */
if (SCM_CTL_Val & (1UL << 1)) { /* Main clock oscillator enabled ? */
FM3_CRG->SCM_CTL |= (1UL << 1); /* enable main oscillator */
while (!(FM3_CRG->SCM_STR & (1UL << 1))); /* wait for Main clock oscillation stable */
}
if (SCM_CTL_Val & (1UL << 3)) { /* Sub clock oscillator enabled ? */
FM3_CRG->SCM_CTL |= (1UL << 3); /* enable sub oscillator */
while (!(FM3_CRG->SCM_STR & (1UL << 3))); /* wait for Sub clock oscillation stable */
}
FM3_CRG->PSW_TMR = PSW_TMR_Val; /* set PLL stabilization wait time */
FM3_CRG->PLL_CTL1 = PLL_CTL1_Val; /* set PLLM and PLLK */
FM3_CRG->PLL_CTL2 = PLL_CTL2_Val; /* set PLLN */
if (SCM_CTL_Val & (1UL << 4)) { /* PLL enabled ? */
FM3_CRG->SCM_CTL |= (1UL << 4); /* enable PLL */
while (!(FM3_CRG->SCM_STR & (1UL << 4))); /* wait for PLL stable */
}
FM3_CRG->SCM_CTL |= (SCM_CTL_Val & 0xE0); /* Set Master Clock switch */
// Workaround for preventing MISRA C:1998 Rule 46 (MISRA C:2004 Rule 12.2)
// violations:
// "Unordered reads and writes to or from same location" and
// "Unordered accesses to a volatile location"
do
{
u32IoRegisterRead = (FM3_CRG->SCM_CTL & 0xE0);
}while ((FM3_CRG->SCM_STR & 0xE0) != u32IoRegisterRead);
#endif // (CLOCK_SETUP)
#if (CR_TRIM_SETUP)
/* CR Trimming Data */
if( 0x000003FF != (FM3_FLASH_IF->CRTRMM & 0x000003FF) )
{
/* UnLock (MCR_FTRM) */
FM3_CRTRIM->MCR_RLR = 0x1ACCE554;
/* Set MCR_FTRM */
FM3_CRTRIM->MCR_FTRM = FM3_FLASH_IF->CRTRMM;
/* Lock (MCR_FTRM) */
FM3_CRTRIM->MCR_RLR = 0x00000000;
}
#endif // (CR_TRIM_SETUP)
}

674
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/************************************************************************/
/* (C) Fujitsu Semiconductor Europe GmbH (FSEU) */
/* */
/* The following software deliverable is intended for and must only be */
/* used for reference and in an evaluation laboratory environment. */
/* It is provided on an as-is basis without charge and is subject to */
/* alterations. */
/* It is the user's obligation to fully test the software in its */
/* environment and to ensure proper functionality, qualification and */
/* compliance with component specifications. */
/* */
/* In the event the software deliverable includes the use of open */
/* source components, the provisions of the governing open source */
/* license agreement shall apply with respect to such software */
/* deliverable. */
/* FSEU does not warrant that the deliverables do not infringe any */
/* third party intellectual property right (IPR). In the event that */
/* the deliverables infringe a third party IPR it is the sole */
/* responsibility of the customer to obtain necessary licenses to */
/* continue the usage of the deliverable. */
/* */
/* To the maximum extent permitted by applicable law FSEU disclaims all */
/* warranties, whether express or implied, in particular, but not */
/* limited to, warranties of merchantability and fitness for a */
/* particular purpose for which the deliverable is not designated. */
/* */
/* To the maximum extent permitted by applicable law, FSEU's liability */
/* is restricted to intentional misconduct and gross negligence. */
/* FSEU is not liable for consequential damages. */
/* */
/* (V1.5) */
/************************************************************************/
/** \file system_mb9af31x.h
**
** Headerfile for FM3 system parameters
**
** User clock definitions can be done for the following clock settings:
** - CLOCK_SETUP : Execute the clock settings form the settings below in
** SystemInit()
** - __CLKMO : External clock frequency for main oscillion
** - __CLKSO : External clock frequency for sub oscillion
** - SCM_CTL : System Clock Mode Control Register
** - BSC_PSR : Base Clock Prescaler Register
** - APBC0_PSR : APB0 Prescaler Register
** - APBC1_PSR : APB1 Prescaler Register
** - APBC2_PSR : APB2 Prescaler Register
** - SWC_PSR : Software Watchdog Clock Prescaler Register
** - TTC_PSR : Trace Clock Prescaler Register
** - CSW_TMR : Clock Stabilization Wait Time Register
** - PSW_TMR : PLL Clock Stabilization Wait Time Setup Register
** - PLL_CTL1 : PLL Control Register 1
** - PLL_CTL2 : PLL Control Register 2
**
** The register settings are check for correct values of reserved bits.
** Otherwise a preprocessor error is output and stops the build process.
** Furthermore the 'master clock' is retrieved from the register settings
** and the system clock (HCLK) is calculated from the Base Clock Prescaler
** Register (BSC_PSR). This value is used for the global CMSIS variable
** #SystemCoreClock. Also the absolute external, PLL and HCL freqeuncy is
** is checked. Note that not all possible wrong setting are checked! The
** user has to take care to fulfill the settings stated in the according
** device's data sheet!
**
** User definition for Hardware Watchdog:
** - HWWD_DISABLE : Disables Hardware Watchdog in SystemInit()
**
** User definition for CR Trimming:
** - CR_TRIM_SETUP : Enables CR trimming in SystemInit()
**
** History:
** 2011-05-16 V1.0 MWi original version
*****************************************************************************/
#ifndef _SYSTEM_MB9AF31X_H_
#define _SYSTEM_MB9AF31X_H_
/******************************************************************************/
/* Include files */
/******************************************************************************/
#include <stdint.h>
/******************************************************************************/
/* Global pre-processor symbols/macros ('define') */
/******************************************************************************/
/******************************************************************************/
/* */
/* START OF USER SETTINGS HERE */
/* =========================== */
/* */
/* All lines with '<<<' can be set by user. */
/* */
/******************************************************************************/
/**
******************************************************************************
** \brief Clock Setup Enable
** <i>(USER SETTING)</i>
**
** - 0 = No clock setup done by system_mb9xfxxx.c
** - 1 = Clock setup done by system_mb9xfxxx.c
******************************************************************************/
#define CLOCK_SETUP 1 // <<< Define clock setup here
/**
******************************************************************************
** \brief External Main Clock Frequency (in Hz, [value]UL)
** <i>(USER SETTING)</i>
******************************************************************************/
#define __CLKMO ( 4000000UL) // <<< External 4MHz Crystal
/**
******************************************************************************
** \brief External Sub Clock Frequency (in Hz, [value]UL)
** <i>(USER SETTING)</i>
******************************************************************************/
#define __CLKSO ( 32768UL) // <<< External 32KHz Crystal
/**
******************************************************************************
** \brief System Clock Mode Control Register value definition
** <i>(USER SETTING)</i>
**
** SCM_CTL
**
** Bit#7-5 : RCS[2:0]
** - 0 = Internal high-speed CR oscillation (default)
** - 1 = Main oscillation clock
** - 2 = PLL oscillation clock
** - 3 = (not allowed)
** - 4 = Internal low-speed CR oscillation
** - 5 = Sub clock oscillation
** - 6 = (not allowed)
** - 7 = (not allowed)
**
** Bit#4 : PLLE
** - 0 = Disable PLL (default)
** - 1 = Enable PLL
**
** Bit#3 : SOSCE
** - 0 = Disable sub oscillation (default)
** - 1 = Enable sub oscillation
**
** Bit#2 : (reserved)
**
** Bit#1 : MOSCE
** - 0 = Disable main oscillation (default)
** - 1 = Enable main oscillation
**
** Bit#0 : (reserved)
******************************************************************************/
#define SCM_CTL_Val 0x00000052 // <<< Define SCM_CTL here
/**
******************************************************************************
** \brief Base Clock Prescaler Register value definition
** <i>(USER SETTING)</i>
**
** BSC_PSR
**
** Bit#7-3 : (reserved)
**
** Bit#2-0 : BSR[2:0]
** - 0 = HCLK = Master Clock
** - 1 = HCLK = Master Clock / 2
** - 2 = HCLK = Master Clock / 3
** - 3 = HCLK = Master Clock / 4
** - 4 = HCLK = Master Clock / 6
** - 5 = HCLK = Master Clock / 8
** - 6 = HCLK = Master Clock / 16
** - 7 = (reserved)
******************************************************************************/
#define BSC_PSR_Val 0x00000000 // <<< Define BSC_PSR here
/**
******************************************************************************
** \brief APB0 Prescaler Register value definition
** <i>(USER SETTING)</i>
**
** APBC0_PSR
**
** Bit#7-2 : (reserved)
**
** Bit#1-0 : BSR[2:0]
** - 0 = PCLK0 = HCLK
** - 1 = PCLK0 = HCLK / 2
** - 2 = PCLK0 = HCLK / 4
** - 3 = PCLK0 = HCLK / 8
******************************************************************************/
#define APBC0_PSR_Val 0x00000001 // <<< Define APBC0_PSR here
/**
******************************************************************************
** \brief APB1 Prescaler Register value definition
** <i>(USER SETTING)</i>
**
** APBC1_PSR
**
** Bit#7 : APBC1EN
** - 0 = Disable PCLK1 output
** - 1 = Enables PCLK1 (default)
**
** Bit#6-5 : (reserved)
**
** Bit#4 : APBC1RST
** - 0 = APB1 bus reset, inactive (default)
** - 1 = APB1 bus reset, active
**
** Bit#3-2 : (reserved)
**
** Bit#1-0 : APBC1[2:0]
** - 0 = PCLK1 = HCLK
** - 1 = PCLK1 = HCLK / 2
** - 2 = PCLK1 = HCLK / 4
** - 3 = PCLK1 = HCLK / 8
******************************************************************************/
#define APBC1_PSR_Val 0x00000081 // <<< Define APBC1_PSR here
/**
******************************************************************************
** \brief APB2 Prescaler Register value definition
** <i>(USER SETTING)</i>
**
** APBC2_PSR
**
** Bit#7 : APBC2EN
** - 0 = Disable PCLK2 output
** - 1 = Enables PCLK2 (default)
**
** Bit#6-5 : (reserved)
**
** Bit#4 : APBC2RST
** - 0 = APB2 bus reset, inactive (default)
** - 1 = APB2 bus reset, active
**
** Bit#3-2 : (reserved)
**
** Bit#1-0 : APBC2[1:0]
** - 0 = PCLK2 = HCLK
** - 1 = PCLK2 = HCLK / 2
** - 2 = PCLK2 = HCLK / 4
** - 3 = PCLK2 = HCLK / 8
******************************************************************************/
#define APBC2_PSR_Val 0x00000081 // <<< Define APBC2_PSR here
/**
******************************************************************************
** \brief Software Watchdog Clock Prescaler Register value definition
** <i>(USER SETTING)</i>
**
** SWC_PSR
**
** Bit#7 : TESTB
** - 0 = (not allowed)
** - 1 = (always write "1" to this bit)
**
** Bit#6-2 : (reserved)
**
** Bit#1-0 : SWDS[2:0]
** - 0 = SWDGOGCLK = PCLK0
** - 1 = SWDGOGCLK = PCLK0 / 2
** - 2 = SWDGOGCLK = PCLK0 / 4
** - 3 = SWDGOGCLK = PCLK0 / 8
******************************************************************************/
#define SWC_PSR_Val 0x00000003 // <<< Define SWC_PSR here
/**
******************************************************************************
** \brief Trace Clock Prescaler Register value definition
** <i>(USER SETTING)</i>
**
** TTC_PSR
**
** Bit#7-1 : (reserved)
**
** Bit#0 : TTC
** - 0 = TPIUCLK = HCLK
** - 1 = TPIUCLK = HCLK / 2
******************************************************************************/
#define TTC_PSR_Val 0x00000000 // <<< Define TTC_PSR here
/**
******************************************************************************
** \brief Clock Stabilization Wait Time Register value definition
** <i>(USER SETTING)</i>
**
** CSW_TMR
**
** Bit#7 : (reserved)
**
** Bit#6-4 : SOWT[2:0]
** - 0 = ~10.3 ms (default)
** - 1 = ~20.5 ms
** - 2 = ~41 ms
** - 3 = ~82 ms
** - 4 = ~164 ms
** - 5 = ~327 ms
** - 6 = ~655 ms
** - 7 = ~1.31 s
**
** Bit#3-0 : MOWT[3:0]
** - 0 = ~500 ns (default)
** - 1 = ~8 us
** - 2 = ~16 us
** - 3 = ~32 us
** - 4 = ~64 us
** - 5 = ~128 us
** - 6 = ~256 us
** - 7 = ~512 us
** - 8 = ~1.0 ms
** - 9 = ~2.0 ms
** - 10 = ~4.0 ms
** - 11 = ~8.0 ms
** - 12 = ~33.0 ms
** - 13 = ~131 ms
** - 14 = ~524 ms
** - 15 = ~2.0 s
******************************************************************************/
#define CSW_TMR_Val 0x0000005C // <<< Define CSW_TMR here
/**
******************************************************************************
** \brief PLL Clock Stabilization Wait Time Setup Register value definition
** <i>(USER SETTING)</i>
**
** PSW_TMR
**
** Bit#7-5 : (reserved)
**
** Bit#4 : PINC
** - 0 = Selects CLKMO (main oscillation) (default)
** - 1 = (setting diabled)
**
** Bit#3 : (reserved)
**
** Bit#2-0 : POWT[2:0]
** - 0 = ~128 us (default)
** - 1 = ~256 us
** - 2 = ~512 us
** - 3 = ~1.02 ms
** - 4 = ~2.05 ms
** - 5 = ~4.10 ms
** - 6 = ~8.20 ms
** - 7 = ~16.40 ms
******************************************************************************/
#define PSW_TMR_Val 0x00000000 // <<< Define PSW_TMR here
/**
******************************************************************************
** \brief PLL Control Register 1 value definition
** <i>(USER SETTING)</i>
**
** PLL_CTL1
**
** Bit#7-4 : PLLK[3:0]
** - 0 = Division(PLLK) = 1/1 (default)
** - 1 = Division(PLLK) = 1/2
** - 2 = Division(PLLK) = 1/3
** - . . .
** - 15 = Division(PLLK) = 1/16
**
** Bit#3-0 : PLLM[3:0]
** - 0 = Division(PLLM) = 1/1 (default)
** - 1 = Division(PLLM) = 1/2
** - 2 = Division(PLLM) = 1/3
** - . . .
** - 15 = Division(PLLM) = 1/16
******************************************************************************/
#define PLL_CTL1_Val 0x00000004 // <<< Define PLL_CTL1 here
/**
******************************************************************************
** \brief PLL Control Register 2 value definition
** <i>(USER SETTING)</i>
**
** PLL_CTL2
**
** Bit#7-6 : (reserved)
**
** Bit#5-0 : PLLM[5:0]
** - 0 = Division(PLLN) = 1/1 (default)
** - 1 = Division(PLLN) = 1/2
** - 2 = Division(PLLN) = 1/3
** - . . .
** - 63 = Division(PLLN) = 1/64
******************************************************************************/
#define PLL_CTL2_Val 0x00000009 // <<< Define PLL_CTL2 here
/**
******************************************************************************
** \brief Hardware Watchdog disable definition
** <i>(USER SETTING)</i>
**
** - 0 = Hardware Watchdog enable
** - 1 = Hardware Watchdog disable
******************************************************************************/
#define HWWD_DISABLE 1 // <<< Define HW Watach dog enable here
/**
******************************************************************************
** \brief Trimming CR
** <i>(USER SETTING)</i>
**
** - 0 = CR is not trimmed at startup
** - 1 = CR is trimmed at startup
******************************************************************************/
#define CR_TRIM_SETUP 1 // <<< Define CR trimming at startup enable here
/******************************************************************************/
/* */
/* END OF USER SETTINGS HERE */
/* ========================= */
/* */
/******************************************************************************/
/******************************************************************************/
/* Device dependent System Clock absolute maximum ranges */
/******************************************************************************/
/**
******************************************************************************
** \brief Internal High-Speed CR Oscillator Frequency (in Hz, [value]UL)
** <i>(USER SETTING)</i>
******************************************************************************/
#define __CLKHC ( 4000000UL) /* Internal 4MHz CR Oscillator */
/**
******************************************************************************
** \brief Internal Low-Speed CR Oscillator Frequency (in Hz, [value]UL)
** <i>(USER SETTING)</i>
******************************************************************************/
#define __CLKLC ( 100000UL) /* Internal 100KHz CR Oscillator */
/**
******************************************************************************
** \brief Any case minimum Main Clock frequency (in Hz, [value]UL)
** <i>(DEVICE DEPENDENT SETTING)</i>
******************************************************************************/
#define __CLKMOMIN ( 4000000UL)
/**
******************************************************************************
** \brief Maximum Main Clock frequency using external clock
** <i>(DEVICE DEPENDENT SETTING)</i>
******************************************************************************/
#define __CLKMOMAX ( 48000000UL)
/**
******************************************************************************
** \brief Any case minimum Sub Clock frequency
** <i>(DEVICE DEPENDENT SETTING)</i>
******************************************************************************/
#define __CLKSOMIN ( 32000UL)
/**
******************************************************************************
** \brief Maximum Sub Clock frequency using external clock
** <i>(DEVICE DEPENDENT SETTING)</i>
******************************************************************************/
#define __CLKSOMAX ( 100000UL)
/**
******************************************************************************
** \brief Absolute minimum PLL input frequency
** <i>(DEVICE DEPENDENT SETTING)</i>
******************************************************************************/
#define __PLLCLKINMIN ( 4000000UL)
/**
******************************************************************************
** \brief Absolute maximum PLL input frequency
** <i>(DEVICE DEPENDENT SETTING)</i>
******************************************************************************/
#define __PLLCLKINMAX ( 16000000UL)
/**
******************************************************************************
** \brief Absolute minimum PLL oscillation frequency
** <i>(DEVICE DEPENDENT SETTING)</i>
******************************************************************************/
#define __PLLCLKMIN (200000000UL)
/**
******************************************************************************
** \brief Absolute maximum PLL oscillation frequency
** <i>(DEVICE DEPENDENT SETTING)</i>
******************************************************************************/
#define __PLLCLKMAX (300000000UL)
/**
******************************************************************************
** \brief Absolute maximum System Clock frequency (HCLK)
** <i>(DEVICE DEPENDENT SETTING)</i>
******************************************************************************/
#define __HCLKMAX ( 40000000UL)
/**
******************************************************************************
** \brief Preprocessor macro for checking range (clock settings)
******************************************************************************/
#define CHECK_RANGE(val, min, max) ((val < min) || (val > max))
/**
******************************************************************************
** \brief Preprocessor macro for checking bits with mask (clock settings)
******************************************************************************/
#define CHECK_RSVD(val, mask) (val & mask)
/******************************************************************************/
/* Check register settings */
/******************************************************************************/
#if (CHECK_RSVD((SCM_CTL_Val), ~0x000000FA))
#error "SCM_CTL: Invalid values of reserved bits!"
#endif
#if ((SCM_CTL_Val & 0xE0) == 0x40) && ((SCM_CTL_Val & 0x10) != 0x10)
#error "SCM_CTL: CLKPLL is selected but PLL is not enabled!"
#endif
#if (CHECK_RSVD((CSW_TMR_Val), ~0x0000007F))
#error "CSW_TMR: Invalid values of reserved bits!"
#endif
#if ((SCM_CTL_Val & 0x10)) /* if PLL is used */
#if (CHECK_RSVD((PSW_TMR_val), ~0x00000007))
#error "PSW_TMR: Invalid values of reserved bits!"
#endif
#if (CHECK_RSVD((PLL_CTL1_Val), ~0x000000FF))
#error "PLL_CTL1: Invalid values of reserved bits!"
#endif
#if (CHECK_RSVD((PLL_CTL2_Val), ~0x0000003F))
#error "PLL_CTL2: Invalid values of reserved bits!"
#endif
#endif
#if (CHECK_RSVD((BSC_PSR_Val), ~0x00000007))
#error "BSC_PSR: Invalid values of reserved bits!"
#endif
#if (CHECK_RSVD((APBC0_PSR_Val), ~0x00000003))
#error "APBC0_PSR: Invalid values of reserved bits!"
#endif
#if (CHECK_RSVD((APBC1_PSR_Val), ~0x00000083))
#error "APBC1_PSR: Invalid values of reserved bits!"
#endif
#if (CHECK_RSVD((APBC2_PSR_Val), ~0x00000083))
#error "APBC2_PSR: Invalid values of reserved bits!"
#endif
#if (CHECK_RSVD((SWC_PSR_Val), ~0x00000003))
#error "SWC_PSR: Invalid values of reserved bits!"
#endif
#if (CHECK_RSVD((TTC_PSR_Val), ~0x00000001))
#error "TTC_PSR: Invalid values of reserved bits!"
#endif
/******************************************************************************/
/* Define clocks with checking settings */
/******************************************************************************/
/**
******************************************************************************
** \brief Calculate PLL K factor from settings
******************************************************************************/
#define __PLLK (((PLL_CTL1_Val >> 4) & 0x0F) + 1)
/**
******************************************************************************
** \brief Calculate PLL N factor from settings
******************************************************************************/
#define __PLLN (((PLL_CTL2_Val ) & 0x1F) + 1)
/**
******************************************************************************
** \brief Calculate PLL M factor from settings
******************************************************************************/
#define __PLLM (((PLL_CTL1_Val ) & 0x0F) + 1)
/**
******************************************************************************
** \brief Calculate PLL output frequency from settings
******************************************************************************/
#define __PLLCLK ((__CLKMO * __PLLN) / __PLLK)
/******************************************************************************/
/* Determine core clock frequency according to settings */
/******************************************************************************/
/**
******************************************************************************
** \brief Define Master Clock from settings
******************************************************************************/
#if (((SCM_CTL_Val >> 5) & 0x07) == 0)
#define __MASTERCLK (__CLKHC)
#elif (((SCM_CTL_Val >> 5) & 0x07) == 1)
#define __MASTERCLK (__CLKMO)
#elif (((SCM_CTL_Val >> 5) & 0x07) == 2)
#define __MASTERCLK (__PLLCLK)
#elif (((SCM_CTL_Val >> 5) & 0x07) == 4)
#define __MASTERCLK (__CLKLC)
#elif (((SCM_CTL_Val >> 5) & 0x07) == 5)
#define __MASTERCLK (__CLKSO)
#else
#define __MASTERCLK (0UL)
#endif
/**
******************************************************************************
** \brief Define System Clock Frequency (Core Clock) from settings
******************************************************************************/
#if ((BSC_PSR_Val & 0x07) == 0)
#define __HCLK (__MASTERCLK / 1)
#elif ((BSC_PSR_Val & 0x07) == 1)
#define __HCLK (__MASTERCLK / 2)
#elif ((BSC_PSR_Val & 0x07) == 2)
#define __HCLK (__MASTERCLK / 3)
#elif ((BSC_PSR_Val & 0x07) == 3)
#define __HCLK (__MASTERCLK / 4)
#elif ((BSC_PSR_Val & 0x07) == 4)
#define __HCLK (__MASTERCLK / 6)
#elif ((BSC_PSR_Val & 0x07) == 5)
#define __HCLK (__MASTERCLK / 8)
#elif ((BSC_PSR_Val & 0x07) == 6)
#define __HCLK (__MASTERCLK /16)
#else
#define __HCLK (0UL)
#endif
/******************************************************************************/
/* HCLK range check */
/******************************************************************************/
#if (CHECK_RANGE(__CLKMO, __CLKMOMIN, __CLKMOMAX) != 0)
#error "Main Oscillator Clock (CLKMO) out of range!"
#endif
#if (CHECK_RANGE(__CLKSO, __CLKSOMIN, __CLKSOMAX) != 0)
#error "Sub Oscillator Clock (CLKMO) out of range!"
#endif
#if (CHECK_RANGE((__CLKMO / __PLLK), __PLLCLKINMIN, __PLLCLKINMAX) != 0)
#error "PLL input frequency out of range!"
#endif
#if (CHECK_RANGE(((__CLKMO * __PLLN * __PLLM) / __PLLK), __PLLCLKMIN, __PLLCLKMAX) != 0)
#error "PLL oscillation frequency out of range!"
#endif
#if (CHECK_RANGE(__HCLK, 0, __HCLKMAX) != 0)
#error "System Clock (HCLK) out of range!"
#endif
/******************************************************************************/
/* Global function prototypes ('extern', definition in C source) */
/******************************************************************************/
extern uint32_t SystemCoreClock; // System Clock Frequency (Core Clock)
extern void SystemInit (void); // Initialize the system
extern void SystemCoreClockUpdate (void); // Update SystemCoreClock variable
#ifdef __cplusplus
}
#endif
#endif /* __SYSTEM_MB9AF31X_H */

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/*
FreeRTOS V7.0.1 - Copyright (C) 2011 Real Time Engineers Ltd.
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>NOTE<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel. FreeRTOS is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details. You should have received a copy of the GNU General Public
License and the FreeRTOS license exception along with FreeRTOS; if not it
can be viewed here: http://www.freertos.org/a00114.html and also obtained
by writing to Richard Barry, contact details for whom are available on the
FreeRTOS WEB site.
1 tab == 4 spaces!
http://www.FreeRTOS.org - Documentation, latest information, license and
contact details.
http://www.SafeRTOS.com - A version that is certified for use in safety
critical systems.
http://www.OpenRTOS.com - Commercial support, development, porting,
licensing and training services.
*/
/*-----------------------------------------------------------
* Simple parallel port IO routines.
*-----------------------------------------------------------*/
/* Kernel includes. */
#include "FreeRTOS.h"
#include "task.h"
/* Fujitsu drivers/libraries. */
#include "mcu.h"
/* Only the LEDs on one of the two seven segment displays are used. */
#define partstMAX_LEDS 8
/*-----------------------------------------------------------*/
void vParTestInitialise( void )
{
/* Analog inputs are not used on the LED outputs. */
FM3_GPIO->ADE = 0x0000;
/* Set to output. */
FM3_GPIO->DDR1 |= 0xFFFF;
FM3_GPIO->DDR3 |= 0xFFFF;
/* Set as GPIO. */
FM3_GPIO->PFR1 &= 0x0000;
FM3_GPIO->PFR3 &= 0x0000;
/* Start with all LEDs off. */
FM3_GPIO->PDOR1 = 0xFFFF;
FM3_GPIO->PDOR1 = 0xFFFF;
}
/*-----------------------------------------------------------*/
void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue )
{
if( uxLED < partstMAX_LEDS )
{
/* A critical section is used as the LEDs are also accessed from an
interrupt. */
taskENTER_CRITICAL();
{
if( xValue == pdTRUE )
{
FM3_GPIO->PDOR1 &= ~( 1UL << uxLED );
}
else
{
FM3_GPIO->PDOR1 |= ( 1UL << uxLED );
}
}
taskEXIT_CRITICAL();
}
}
/*-----------------------------------------------------------*/
void vParTestSetLEDFromISR( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue )
{
unsigned portBASE_TYPE uxInterruptFlags;
uxInterruptFlags = portSET_INTERRUPT_MASK_FROM_ISR();
{
if( uxLED < partstMAX_LEDS )
{
if( xValue == pdTRUE )
{
FM3_GPIO->PDOR1 &= ~( 1UL << uxLED );
}
else
{
FM3_GPIO->PDOR1 |= ( 1UL << uxLED );
}
}
}
portCLEAR_INTERRUPT_MASK_FROM_ISR( uxInterruptFlags );
}
/*-----------------------------------------------------------*/
void vParTestToggleLED( unsigned portBASE_TYPE uxLED )
{
if( uxLED < partstMAX_LEDS )
{
/* A critical section is used as the LEDs are also accessed from an
interrupt. */
taskENTER_CRITICAL();
{
if( ( FM3_GPIO->PDOR1 & ( 1UL << uxLED ) ) != 0UL )
{
FM3_GPIO->PDOR1 &= ~( 1UL << uxLED );
}
else
{
FM3_GPIO->PDOR1 |= ( 1UL << uxLED );
}
}
taskEXIT_CRITICAL();
}
}
/*-----------------------------------------------------------*/

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<?xml version="1.0" encoding="iso-8859-1"?>
<workspace>
<project>
<path>$WS_DIR$\RTOSDemo_IAR.ewp</path>
</project>
<batchBuild/>
</workspace>

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execUserReset()
{
__message("Executing __hwReset");
__hwReset(0);
__message("__hwReset done");
__hwResetWithStrategy(0, 2);
__writeMemory32(0x1FFFC000, 0xE000ED08, "Memory"); //Vector table remap at 0x1FFFC000
}
execUserPreload()
{
__writeMemory32(0x1FFFC000, 0xE000ED08, "Memory"); //Vector table remap at 0x1FFFC000
}

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<?xml version="1.0" encoding="iso-8859-1"?>
<flash_board>
<pass>
<loader>$PROJ_DIR$\config\flashloader\FlashMB9A310.flash</loader>
</pass>
</flash_board>

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<?xml version="1.0" encoding="iso-8859-1"?>
<flash_device>
<exe>$PROJ_DIR$\config\flashloader\FlashMB9A310.out</exe>
<page>4</page>
<block>2 0x4000</block>
<block>1 0x18000</block>
<block>3 0x20000</block>
<flash_base>0x00000000</flash_base>
<macro>$PROJ_DIR$\config\flashloader\FlashMB9A310.mac</macro>
<aggregate>1</aggregate>
<args_doc>The "--protect" argument is used to program
protection code 0x0001 in the security code area of the
flash.
Note: Writing the protection code disables JTAG access
and debug is not possible. To release security, perform
the chip erase operation using a serial writer because
the security cannot be released through JTAG pins.</args_doc>
</flash_device>

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setup()
{
/*Disable HWD*/
__writeMemory32(0x1ACCE551, 0x40011C00, "Memory"); //Unlock WDG_LCK = 0x1ACCE551
__writeMemory32(0xE5331AAE, 0x40011C00, "Memory"); //Unlock WDG_LCK = 0xE5331AAE
__writeMemory32(0x00000000, 0x40011008, "Memory"); //WDG_CTL = 0
/*Clock from High Speed internal Oscilator*/
__writeMemory32(__readMemory32(0x40010000, "Memory") & ~0xE0, 0x40010000, "Memory");
/*Wait*/
__delay(5);
__emulatorSpeed(0);
/*Base Clock Prescaler Register*/
__writeMemory32(0, 0x40010010, "Memory");
/*Vectors at RAM*/
__writeMemory32(0x1FFFE000, 0xE000ED08, "Memory"); //Vector table remap at 0x1FFFE000
}
execUserPreload()
{
__message "----- Prepare hardware for Flashloader -----\n";
setup();
}
execUserFlashInit() // Called by debugger before loading flash loader in RAM.
{
__message "----- Prepare hardware for Flashloader -----\n";
setup();
}

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Demo/CORTEX_MB9A310_IAR_Keil/config/flashloader/FlashMB9A310.out Normal file
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/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x0;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = 0x0;
define symbol __ICFEDIT_region_ROM_end__ = 0x0003FFFF;
define symbol __ICFEDIT_region_RAM_start__ = 0x1FFFC000;
define symbol __ICFEDIT_region_RAM_end__ = 0x20003FFF;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x400;
define symbol __ICFEDIT_size_heap__ = 0x800;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
initialize by copy { readwrite };
do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block HEAP };

674
Demo/CORTEX_MB9A310_IAR_Keil/main-full.c Normal file
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@ -0,0 +1,674 @@
/*
FreeRTOS V7.0.1 - Copyright (C) 2011 Real Time Engineers Ltd.
FreeRTOS supports many tools and architectures. V7.0.0 is sponsored by:
Atollic AB - Atollic provides professional embedded systems development
tools for C/C++ development, code analysis and test automation.
See http://www.atollic.com
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>NOTE<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel. FreeRTOS is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details. You should have received a copy of the GNU General Public
License and the FreeRTOS license exception along with FreeRTOS; if not it
can be viewed here: http://www.freertos.org/a00114.html and also obtained
by writing to Richard Barry, contact details for whom are available on the
FreeRTOS WEB site.
1 tab == 4 spaces!
http://www.FreeRTOS.org - Documentation, latest information, license and
contact details.
http://www.SafeRTOS.com - A version that is certified for use in safety
critical systems.
http://www.OpenRTOS.com - Commercial support, development, porting,
licensing and training services.
*/
/*
* main-blinky.c is included when the "Blinky" build configuration is used.
* main-full.c is included when the "Full" build configuration is used.
*
* main-full.c (this file) defines a comprehensive demo that creates many
* tasks, queues, semaphores and timers. It also demonstrates how Cortex-M3
* interrupts can interact with FreeRTOS tasks/timers.
*
* This project runs on the SK-FM3-100PMC evaluation board, which is populated
* with an MB9BF5006N Cortex-M3 based microcontroller.
*
* The main() Function:
* main() creates three demo specific software timers, one demo specific queue,
* and two demo specific tasks. It then creates a whole host of 'standard
* demo' tasks/queues/semaphores, before starting the scheduler. The demo
* specific tasks and timers are described in the comments here. The standard
* demo tasks are described on the FreeRTOS.org web site.
*
* The standard demo tasks provide no specific functionality. They are
* included to both test the FreeRTOS port, and provide examples of how the
* various FreeRTOS API functions can be used.
*
* This demo creates 43 tasks in total. If you want a simpler demo, use the
* Blinky build configuration.
*
* The Demo Specific Queue Send Task:
* The queue send task is implemented by the prvQueueSendTask() function in
* this file. prvQueueSendTask() sits in a loop that causes it to repeatedly
* block for 200 milliseconds, before sending the value 100 to the queue that
* was created within main(). Once the value is sent, the task loops back
* around to block for another 200 milliseconds.
*
* The Demo Specific Queue Receive Task:
* The queue receive task is implemented by the prvQueueReceiveTask() function
* in this file. prvQueueReceiveTask() sits in a loop that causes it to
* repeatedly attempt to read data from the queue that was created within
* main(). When data is received, the task checks the value of the data, and
* if the value equals the expected 100, toggles an LED in the 7 segment display
* (see the documentation page for this demo on the FreeRTOS.org site to see
* which LED is used). The 'block time' parameter passed to the queue receive
* function specifies that the task should be held in the Blocked state
* indefinitely to wait for data to be available on the queue. The queue
* receive task will only leave the Blocked state when the queue send task
* writes to the queue. As the queue send task writes to the queue every 200
* milliseconds, the queue receive task leaves the Blocked state every 200
* milliseconds, and therefore toggles the LED every 200 milliseconds.
*
* The Demo Specific LED Software Timer and the Button Interrupt:
* The user button SW2 is configured to generate an interrupt each time it is
* pressed. The interrupt service routine switches an LED on, and resets the
* LED software timer. The LED timer has a 5000 millisecond (5 second) period,
* and uses a callback function that is defined to just turn the LED off again.
* Therefore, pressing the user button will turn the LED on, and the LED will
* remain on until a full five seconds pass without the button being pressed.
* See the documentation page for this demo on the FreeRTOS.org web site to see
* which LED is used.
*
* The Demo Specific "Check" Callback Function:
* This is called each time the 'check' timer expires. The check timer
* callback function inspects all the standard demo tasks to see if they are
* all executing as expected. The check timer is initially configured to
* expire every three seconds, but will shorted this to every 500ms if an error
* is ever discovered. The check timer callback toggles the LED defined by
* the mainCHECK_LED definition each time it executes. Therefore, if LED
* mainCHECK_LED is toggling every three seconds, then no error have been found.
* If LED mainCHECK_LED is toggling every 500ms, then at least one errors has
* been found. The variable pcStatusMessage is set to a string that indicates
* which task reported an error. See the documentation page for this demo on
* the FreeRTOS.org web site to see which LED in the 7 segment display is used.
*
* The Demo Specific "Digit Counter" Callback Function:
* This is called each time the 'digit counter' timer expires. It causes the
* digits 0 to 9 to be displayed in turn as the first character of the two
* character display. The LEDs in the other digit of the two character
* display are used as general purpose LEDs, as described in this comment block.
*
* The Demo Specific Idle Hook Function:
* The idle hook function demonstrates how to query the amount of FreeRTOS heap
* space that is remaining (see vApplicationIdleHook() defined in this file).
*
* The Demo Specific Tick Hook Function:
* The tick hook function is used to test the interrupt safe software timer
* functionality.
*/
/* Kernel includes. */
#include "FreeRTOS.h"
#include "task.h"
#include "queue.h"
#include "timers.h"
/* Fujitsu drivers/libraries. */
#include "mcu.h"
/* Common demo includes. */
#include "partest.h"
#include "flash.h"
#include "BlockQ.h"
#include "death.h"
#include "blocktim.h"
#include "semtest.h"
#include "GenQTest.h"
#include "QPeek.h"
#include "recmutex.h"
#include "TimerDemo.h"
#include "comtest2.h"
#include "PollQ.h"
#include "countsem.h"
#include "dynamic.h"
/* The rate at which data is sent to the queue, specified in milliseconds, and
converted to ticks using the portTICK_RATE_MS constant. */
#define mainQUEUE_SEND_FREQUENCY_MS ( 200 / portTICK_RATE_MS )
/* The number of items the queue can hold. This is 1 as the receive task
will remove items as they are added, meaning the send task should always find
the queue empty. */
#define mainQUEUE_LENGTH ( 1 )
/* The LED toggled by the check timer callback function. This is an LED in the
second digit of the two digit 7 segment display. See the documentation page
for this demo on the FreeRTOS.org web site to see which LED this relates to. */
#define mainCHECK_LED ( 1UL << 3UL )
/* The LED toggle by the queue receive task. This is an LED in the second digit
of the two digit 7 segment display. See the documentation page for this demo on
the FreeRTOS.org web site to see which LED this relates to. */
#define mainTASK_CONTROLLED_LED 0x07UL
/* The LED turned on by the button interrupt, and turned off by the LED timer.
This is an LED in the second digit of the two digit 7 segment display. See the
documentation page for this demo on the FreeRTOS.org web site to see which LED
this relates to. */
#define mainTIMER_CONTROLLED_LED 0x05UL
/* The LED used by the comtest tasks. See the comtest.c file for more
information. The LEDs used by the comtest task are in the second digit of the
two digit 7 segment display. See the documentation page for this demo on the
FreeRTOS.org web site to see which LEDs this relates to. */
#define mainCOM_TEST_LED 0x03UL
/* Constant used by the standard timer test functions. */
#define mainTIMER_TEST_PERIOD ( 50 )
/* Priorities used by the various different standard demo tasks. */
#define mainCHECK_TASK_PRIORITY ( configMAX_PRIORITIES - 1 )
#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 1 )
#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 )
#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 )
#define mainCREATOR_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 )
#define mainFLASH_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )
#define mainINTEGER_TASK_PRIORITY ( tskIDLE_PRIORITY )
#define mainGEN_QUEUE_TASK_PRIORITY ( tskIDLE_PRIORITY )
#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 )
/* Priorities defined in this main-full.c file. */
#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )
#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )
/* The period at which the check timer will expire, in ms, provided no errors
have been reported by any of the standard demo tasks. ms are converted to the
equivalent in ticks using the portTICK_RATE_MS constant. */
#define mainCHECK_TIMER_PERIOD_MS ( 3000UL / portTICK_RATE_MS )
/* The period at which the check timer will expire, in ms, if an error has been
reported in one of the standard demo tasks. ms are converted to the equivalent
in ticks using the portTICK_RATE_MS constant. */
#define mainERROR_CHECK_TIMER_PERIOD_MS ( 500UL / portTICK_RATE_MS )
/* The period at which the digit counter timer will expire, in ms, and converted
to ticks using the portTICK_RATE_MS constant. */
#define mainDIGIT_COUNTER_TIMER_PERIOD_MS ( 250UL / portTICK_RATE_MS )
/* The LED will remain on until the button has not been pushed for a full
5000ms. */
#define mainLED_TIMER_PERIOD_MS ( 5000UL / portTICK_RATE_MS )
/* A zero block time. */
#define mainDONT_BLOCK ( 0UL )
/* Baud rate used by the comtest tasks. */
#define mainCOM_TEST_BAUD_RATE ( 115200UL )
/*-----------------------------------------------------------*/
/*
* Setup the NVIC, LED outputs, and button inputs.
*/
static void prvSetupHardware( void );
/*
* The application specific (not common demo) tasks as described in the comments
* at the top of this file.
*/
static void prvQueueReceiveTask( void *pvParameters );
static void prvQueueSendTask( void *pvParameters );
/*
* The LED timer callback function. This does nothing but switch an LED off.
*/
static void prvLEDTimerCallback( xTimerHandle xTimer );
/*
* The check timer callback function, as described at the top of this file.
*/
static void prvCheckTimerCallback( xTimerHandle xTimer );
/*
* The digit counter callback function, as described at the top of this file.
*/
static void prvDigitCounterTimerCallback( xTimerHandle xTimer );
/*
* This is not a 'standard' partest function, so the prototype is not in
* partest.h, and is instead included here.
*/
void vParTestSetLEDFromISR( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue );
/*-----------------------------------------------------------*/
/* The queue used by both application specific demo tasks defined in this file. */
static xQueueHandle xQueue = NULL;
/* The LED software timer. This uses prvLEDTimerCallback() as it's callback
function. */
static xTimerHandle xLEDTimer = NULL;
/* The digit counter software timer. This displays a counting digit on one half
of the seven segment displays. */
static xTimerHandle xDigitCounterTimer = NULL;
/* The check timer. This uses prvCheckTimerCallback() as its callback
function. */
static xTimerHandle xCheckTimer = NULL;
/* If an error is detected in a standard demo task, then pcStatusMessage will
be set to point to a string that identifies the offending task. This is just
to make debugging easier. */
static const char *pcStatusMessage = NULL;
/*-----------------------------------------------------------*/
int main(void)
{
/* Configure the NVIC, LED outputs and button inputs. */
prvSetupHardware();
/* Create the queue. */
xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( unsigned long ) );
if( xQueue != NULL )
{
/* Start the two application specific demo tasks, as described in the
comments at the top of this file. */
xTaskCreate( prvQueueReceiveTask, ( signed char * ) "Rx", configMINIMAL_STACK_SIZE, NULL, mainQUEUE_RECEIVE_TASK_PRIORITY, NULL );
xTaskCreate( prvQueueSendTask, ( signed char * ) "TX", configMINIMAL_STACK_SIZE, NULL, mainQUEUE_SEND_TASK_PRIORITY, NULL );
/* Create the software timer that is responsible for turning off the LED
if the button is not pushed within 5000ms, as described at the top of
this file. */
xLEDTimer = xTimerCreate( ( const signed char * ) "LEDTimer", /* A text name, purely to help debugging. */
( mainLED_TIMER_PERIOD_MS ), /* The timer period, in this case 5000ms (5s). */
pdFALSE, /* This is a one shot timer, so xAutoReload is set to pdFALSE. */
( void * ) 0, /* The ID is not used, so can be set to anything. */
prvLEDTimerCallback /* The callback function that switches the LED off. */
);
/* Create the software timer that performs the 'check' functionality,
as described at the top of this file. */
xCheckTimer = xTimerCreate( ( const signed char * ) "CheckTimer",/* A text name, purely to help debugging. */
( mainCHECK_TIMER_PERIOD_MS ), /* The timer period, in this case 3000ms (3s). */
pdTRUE, /* This is an auto-reload timer, so xAutoReload is set to pdTRUE. */
( void * ) 0, /* The ID is not used, so can be set to anything. */
prvCheckTimerCallback /* The callback function that inspects the status of all the other tasks. */
);
/* Create the software timer that performs the 'digit counting'
functionality, as described at the top of this file. */
xDigitCounterTimer = xTimerCreate( ( const signed char * ) "DigitCounter", /* A text name, purely to help debugging. */
( mainDIGIT_COUNTER_TIMER_PERIOD_MS ), /* The timer period, in this case 3000ms (3s). */
pdTRUE, /* This is an auto-reload timer, so xAutoReload is set to pdTRUE. */
( void * ) 0, /* The ID is not used, so can be set to anything. */
prvDigitCounterTimerCallback /* The callback function that inspects the status of all the other tasks. */
);
/* Create a lot of 'standard demo' tasks. Over 40 tasks are created in
this demo. For a much simpler demo, select the 'blinky' build
configuration. */
vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );
vCreateBlockTimeTasks();
vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );
vStartGenericQueueTasks( mainGEN_QUEUE_TASK_PRIORITY );
vStartLEDFlashTasks( mainFLASH_TASK_PRIORITY );
vStartQueuePeekTasks();
vStartRecursiveMutexTasks();
vStartTimerDemoTask( mainTIMER_TEST_PERIOD );
vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED );
vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );
vStartCountingSemaphoreTasks();
vStartDynamicPriorityTasks();
/* The suicide tasks must be created last, as they need to know how many
tasks were running prior to their creation in order to ascertain whether
or not the correct/expected number of tasks are running at any given
time. */
vCreateSuicidalTasks( mainCREATOR_TASK_PRIORITY );
/* Start the tasks and timer running. */
vTaskStartScheduler();
}
/* If all is well, the scheduler will now be running, and the following line
will never be reached. If the following line does execute, then there was
insufficient FreeRTOS heap memory available for the idle and/or timer tasks
to be created. See the memory management section on the FreeRTOS web site
for more details. */
for( ;; );
}
/*-----------------------------------------------------------*/
static void prvCheckTimerCallback( xTimerHandle xTimer )
{
/* Check the standard demo tasks are running without error. Latch the
latest reported error in the pcStatusMessage character pointer. */
if( xAreGenericQueueTasksStillRunning() != pdTRUE )
{
pcStatusMessage = "Error: GenQueue";
}
if( xAreQueuePeekTasksStillRunning() != pdTRUE )
{
pcStatusMessage = "Error: QueuePeek\r\n";
}
if( xAreBlockingQueuesStillRunning() != pdTRUE )
{
pcStatusMessage = "Error: BlockQueue\r\n";
}
if( xAreBlockTimeTestTasksStillRunning() != pdTRUE )
{
pcStatusMessage = "Error: BlockTime\r\n";
}
if( xAreSemaphoreTasksStillRunning() != pdTRUE )
{
pcStatusMessage = "Error: SemTest\r\n";
}
if( xIsCreateTaskStillRunning() != pdTRUE )
{
pcStatusMessage = "Error: Death\r\n";
}
if( xAreRecursiveMutexTasksStillRunning() != pdTRUE )
{
pcStatusMessage = "Error: RecMutex\r\n";
}
if( xAreComTestTasksStillRunning() != pdPASS )
{
pcStatusMessage = "Error: ComTest\r\n";
}
if( xAreTimerDemoTasksStillRunning( ( mainCHECK_TIMER_PERIOD_MS ) ) != pdTRUE )
{
pcStatusMessage = "Error: TimerDemo";
}
if( xArePollingQueuesStillRunning() != pdTRUE )
{
pcStatusMessage = "Error: PollQueue";
}
if( xAreCountingSemaphoreTasksStillRunning() != pdTRUE )
{
pcStatusMessage = "Error: CountSem";
}
if( xAreDynamicPriorityTasksStillRunning() != pdTRUE )
{
pcStatusMessage = "Error: DynamicPriority";
}
/* Toggle the check LED to give an indication of the system status. If
the LED toggles every mainCHECK_TIMER_PERIOD_MS milliseconds then
everything is ok. A faster toggle indicates an error. vParTestToggleLED()
is not used to toggle this particular LED as it is on a different IP port
to to the LEDs controlled by ParTest.c. A critical section is not required
as the only other place this port is accessed is from another timer - and
only one timer can be running at any one time. */
if( ( FM3_GPIO->PDOR3 & mainCHECK_LED ) != 0 )
{
FM3_GPIO->PDOR3 &= ~mainCHECK_LED;
}
else
{
FM3_GPIO->PDOR3 |= mainCHECK_LED;
}
/* Have any errors been latch in pcStatusMessage? If so, shorten the
period of the check timer to mainERROR_CHECK_TIMER_PERIOD_MS milliseconds.
This will result in an increase in the rate at which mainCHECK_LED
toggles. */
if( pcStatusMessage != NULL )
{
/* This call to xTimerChangePeriod() uses a zero block time. Functions
called from inside of a timer callback function must *never* attempt
to block. */
xTimerChangePeriod( xCheckTimer, ( mainERROR_CHECK_TIMER_PERIOD_MS ), mainDONT_BLOCK );
}
}
/*-----------------------------------------------------------*/
static void prvLEDTimerCallback( xTimerHandle xTimer )
{
/* The timer has expired - so no button pushes have occurred in the last
five seconds - turn the LED off. */
vParTestSetLED( mainTIMER_CONTROLLED_LED, pdFALSE );
}
/*-----------------------------------------------------------*/
static void prvDigitCounterTimerCallback( xTimerHandle xTimer )
{
/* Define the bit patterns that display numbers on the seven segment display. */
static const unsigned short usNumbersPatterns[] = { 0x8004, 0xF204, 0x4804, 0x6004, 0x3204, 0x2404, 0x0404, 0xF104, 0x0004, 0x2004 };
static long lCounter = 0L;
const long lNumberOfDigits = 10L;
unsigned short usCheckLEDState;
/* Unfortunately the LED uses the same port as the digit counter, so remember
the state of the check LED. A critical section is not required to access
the port as only one timer can be executing at any one time. */
usCheckLEDState = ( FM3_GPIO->PDOR3 & mainCHECK_LED );
/* Display the next number, counting up. */
FM3_GPIO->PDOR3 = usNumbersPatterns[ lCounter ] | usCheckLEDState;
/* Move onto the next digit. */
lCounter++;
/* Ensure the counter does not go off the end of the array. */
if( lCounter >= lNumberOfDigits )
{
lCounter = 0L;
}
}
/*-----------------------------------------------------------*/
/* The ISR executed when the user button is pushed. */
void INT0_7_Handler( void )
{
portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE;
/* The button was pushed, so ensure the LED is on before resetting the
LED timer. The LED timer will turn the LED off if the button is not
pushed within 5000ms. */
vParTestSetLEDFromISR( mainTIMER_CONTROLLED_LED, pdTRUE );
/* This interrupt safe FreeRTOS function can be called from this interrupt
because the interrupt priority is below the
configMAX_SYSCALL_INTERRUPT_PRIORITY setting in FreeRTOSConfig.h. */
xTimerResetFromISR( xLEDTimer, &xHigherPriorityTaskWoken );
/* Clear the interrupt before leaving. This just clears all the interrupts
for simplicity, as only one is actually used in this simple demo anyway. */
FM3_EXTI->EICL = 0x0000;
/* If calling xTimerResetFromISR() caused a task (in this case the timer
service/daemon task) to unblock, and the unblocked task has a priority
higher than or equal to the task that was interrupted, then
xHigherPriorityTaskWoken will now be set to pdTRUE, and calling
portEND_SWITCHING_ISR() will ensure the unblocked task runs next. */
portEND_SWITCHING_ISR( xHigherPriorityTaskWoken );
}
/*-----------------------------------------------------------*/
static void prvQueueSendTask( void *pvParameters )
{
portTickType xNextWakeTime;
const unsigned long ulValueToSend = 100UL;
/* The timer command queue will have been filled when the timer test tasks
were created in main() (this is part of the test they perform). Therefore,
while the check and digit counter timers can be created in main(), they
cannot be started from main(). Once the scheduler has started, the timer
service task will drain the command queue, and now the check and digit
counter timers can be started successfully. */
xTimerStart( xCheckTimer, portMAX_DELAY );
xTimerStart( xDigitCounterTimer, portMAX_DELAY );
/* Initialise xNextWakeTime - this only needs to be done once. */
xNextWakeTime = xTaskGetTickCount();
for( ;; )
{
/* Place this task in the blocked state until it is time to run again.
The block time is specified in ticks, the constant used converts ticks
to ms. While in the Blocked state this task will not consume any CPU
time. */
vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS );
/* Send to the queue - causing the queue receive task to unblock and
toggle an LED. 0 is used as the block time so the sending operation
will not block - it shouldn't need to block as the queue should always
be empty at this point in the code. */
xQueueSend( xQueue, &ulValueToSend, mainDONT_BLOCK );
}
}
/*-----------------------------------------------------------*/
static void prvQueueReceiveTask( void *pvParameters )
{
unsigned long ulReceivedValue;
for( ;; )
{
/* Wait until something arrives in the queue - this task will block
indefinitely provided INCLUDE_vTaskSuspend is set to 1 in
FreeRTOSConfig.h. */
xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY );
/* To get here something must have been received from the queue, but
is it the expected value? If it is, toggle the LED. */
if( ulReceivedValue == 100UL )
{
vParTestToggleLED( mainTASK_CONTROLLED_LED );
}
}
}
/*-----------------------------------------------------------*/
static void prvSetupHardware( void )
{
const unsigned short usButtonInputBit = 0x01U;
SystemInit();
SystemCoreClockUpdate();
/* Initialise the IO used for the LEDs on the 7 segment displays. */
vParTestInitialise();
/* Set the switches to input (P18->P1F). */
FM3_GPIO->DDR5 = 0x0000;
FM3_GPIO->PFR5 = 0x0000;
/* Assign the button input as GPIO. */
FM3_GPIO->PFR1 |= usButtonInputBit;
/* Button interrupt on falling edge. */
FM3_EXTI->ELVR = 0x0003;
/* Clear all external interrupts. */
FM3_EXTI->EICL = 0x0000;
/* Enable the button interrupt. */
FM3_EXTI->ENIR |= usButtonInputBit;
/* Setup the GPIO and the NVIC for the switch used in this simple demo. */
NVIC_SetPriority( EXINT0_7_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
NVIC_EnableIRQ( EXINT0_7_IRQn );
}
/*-----------------------------------------------------------*/
void vApplicationMallocFailedHook( void )
{
/* Called if a call to pvPortMalloc() fails because there is insufficient
free memory available in the FreeRTOS heap. pvPortMalloc() is called
internally by FreeRTOS API functions that create tasks, queues, software
timers, and semaphores. The size of the FreeRTOS heap is set by the
configTOTAL_HEAP_SIZE configuration constant in FreeRTOSConfig.h. */
for( ;; );
}
/*-----------------------------------------------------------*/
void vApplicationStackOverflowHook( xTaskHandle *pxTask, signed char *pcTaskName )
{
( void ) pcTaskName;
( void ) pxTask;
/* Run time stack overflow checking is performed if
configconfigCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook
function is called if a stack overflow is detected. */
taskDISABLE_INTERRUPTS();
for( ;; );
}
/*-----------------------------------------------------------*/
void vApplicationIdleHook( void )
{
volatile size_t xFreeStackSpace;
/* This function is called on each cycle of the idle task. In this case it
does nothing useful, other than report the amount of FreeRTOS heap that
remains unallocated. */
xFreeStackSpace = xPortGetFreeHeapSize();
if( xFreeStackSpace > 100 )
{
/* By now, the kernel has allocated everything it is going to, so
if there is a lot of heap remaining unallocated then
the value of configTOTAL_HEAP_SIZE in FreeRTOSConfig.h can be
reduced accordingly. */
}
}
/*-----------------------------------------------------------*/
void vApplicationTickHook( void )
{
/* Call the periodic timer test, which tests the timer API functions that
can be called from an ISR. */
vTimerPeriodicISRTests();
}
/*-----------------------------------------------------------*/

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@ -0,0 +1,399 @@
/*
FreeRTOS V7.0.1 - Copyright (C) 2011 Real Time Engineers Ltd.
FreeRTOS supports many tools and architectures. V7.0.0 is sponsored by:
Atollic AB - Atollic provides professional embedded systems development
tools for C/C++ development, code analysis and test automation.
See http://www.atollic.com
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>NOTE<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel. FreeRTOS is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details. You should have received a copy of the GNU General Public
License and the FreeRTOS license exception along with FreeRTOS; if not it
can be viewed here: http://www.freertos.org/a00114.html and also obtained
by writing to Richard Barry, contact details for whom are available on the
FreeRTOS WEB site.
1 tab == 4 spaces!
http://www.FreeRTOS.org - Documentation, latest information, license and
contact details.
http://www.SafeRTOS.com - A version that is certified for use in safety
critical systems.
http://www.OpenRTOS.com - Commercial support, development, porting,
licensing and training services.
*/
/*
* main-blinky.c is included when the "Blinky" build configuration is used.
* main-full.c is included when the "Full" build configuration is used.
*
* main-blinky.c (this file) defines a very simple demo that creates two tasks,
* one queue, and one timer. It also demonstrates how Cortex-M3 interrupts can
* interact with FreeRTOS tasks/timers.
*
* This simple demo project runs on the SK-FM3-64PMC1 evaluation board, which
* is populated with an MB9A300 microcontroller.
*
* The idle hook function:
* The idle hook function demonstrates how to query the amount of FreeRTOS heap
* space that is remaining (see vApplicationIdleHook() defined in this file).
*
* The main() Function:
* main() creates one software timer, one queue, and two tasks. It then starts
* the scheduler.
*
* The Queue Send Task:
* The queue send task is implemented by the prvQueueSendTask() function in
* this file. prvQueueSendTask() sits in a loop that causes it to repeatedly
* block for 200 milliseconds, before sending the value 100 to the queue that
* was created within main(). Once the value is sent, the task loops back
* around to block for another 200 milliseconds.
*
* The Queue Receive Task:
* The queue receive task is implemented by the prvQueueReceiveTask() function
* in this file. prvQueueReceiveTask() sits in a loop that causes it to
* repeatedly attempt to read data from the queue that was created within
* main(). When data is received, the task checks the value of the data, and
* if the value equals the expected 100, toggles an LED on the 7 segment
* display. The 'block time' parameter passed to the queue receive function
* specifies that the task should be held in the Blocked state indefinitely to
* wait for data to be available on the queue. The queue receive task will only
* leave the Blocked state when the queue send task writes to the queue. As the
* queue send task writes to the queue every 200 milliseconds, the queue receive
* task leaves the Blocked state every 200 milliseconds, and therefore toggles
* the LED every 200 milliseconds.
*
* The LED Software Timer and the Button Interrupt:
* The user button SW2 is configured to generate an interrupt each time it is
* pressed. The interrupt service routine switches an LED in the 7 segment
* display on, and resets the LED software timer. The LED timer has a 5000
* millisecond (5 second) period, and uses a callback function that is defined
* to just turn the LED off again. Therefore, pressing the user button will
* turn the LED on, and the LED will remain on until a full five seconds pass
* without the button being pressed.
*/
/* Kernel includes. */
#include "FreeRTOS.h"
#include "task.h"
#include "queue.h"
#include "timers.h"
/* Fujitsu drivers/libraries. */
#include "mcu.h"
/* Priorities at which the tasks are created. */
#define mainQUEUE_RECEIVE_TASK_PRIORITY ( tskIDLE_PRIORITY + 2 )
#define mainQUEUE_SEND_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )
/* The rate at which data is sent to the queue, specified in milliseconds, and
converted to ticks using the portTICK_RATE_MS constant. */
#define mainQUEUE_SEND_FREQUENCY_MS ( 200 / portTICK_RATE_MS )
/* The number of items the queue can hold. This is 1 as the receive task
will remove items as they are added, meaning the send task should always find
the queue empty. */
#define mainQUEUE_LENGTH ( 1 )
/* The LED toggle by the queue receive task. */
#define mainTASK_CONTROLLED_LED ( 1UL << 3UL )
/* The LED turned on by the button interrupt, and turned off by the LED timer. */
#define mainTIMER_CONTROLLED_LED ( 1UL << 2UL )
/*-----------------------------------------------------------*/
/*
* Setup the NVIC, LED outputs, and button inputs.
*/
static void prvSetupHardware( void );
/*
* The tasks as described in the comments at the top of this file.
*/
static void prvQueueReceiveTask( void *pvParameters );
static void prvQueueSendTask( void *pvParameters );
/*
* The LED timer callback function. This does nothing but switch off the
* LED defined by the mainTIMER_CONTROLLED_LED constant.
*/
static void vLEDTimerCallback( xTimerHandle xTimer );
/*-----------------------------------------------------------*/
/* The queue used by both tasks. */
static xQueueHandle xQueue = NULL;
/* The LED software timer. This uses vLEDTimerCallback() as its callback
function. */
static xTimerHandle xLEDTimer = NULL;
/*-----------------------------------------------------------*/
int main(void)
{
/* Configure the NVIC, LED outputs and button inputs. */
prvSetupHardware();
/* Create the queue. */
xQueue = xQueueCreate( mainQUEUE_LENGTH, sizeof( unsigned long ) );
if( xQueue != NULL )
{
/* Start the two tasks as described in the comments at the top of this
file. */
xTaskCreate( prvQueueReceiveTask, ( signed char * ) "Rx", configMINIMAL_STACK_SIZE, NULL, mainQUEUE_RECEIVE_TASK_PRIORITY, NULL );
xTaskCreate( prvQueueSendTask, ( signed char * ) "TX", configMINIMAL_STACK_SIZE, NULL, mainQUEUE_SEND_TASK_PRIORITY, NULL );
/* Create the software timer that is responsible for turning off the LED
if the button is not pushed within 5000ms, as described at the top of
this file. */
xLEDTimer = xTimerCreate( ( const signed char * ) "LEDTimer", /* A text name, purely to help debugging. */
( 5000 / portTICK_RATE_MS ), /* The timer period, in this case 5000ms (5s). */
pdFALSE, /* This is a one shot timer, so xAutoReload is set to pdFALSE. */
( void * ) 0, /* The ID is not used, so can be set to anything. */
vLEDTimerCallback /* The callback function that switches the LED off. */
);
/* Start the tasks and timer running. */
vTaskStartScheduler();
}
/* If all is well, the scheduler will now be running, and the following line
will never be reached. If the following line does execute, then there was
insufficient FreeRTOS heap memory available for the idle and/or timer tasks
to be created. See the memory management section on the FreeRTOS web site
for more details. */
for( ;; );
}
/*-----------------------------------------------------------*/
static void vLEDTimerCallback( xTimerHandle xTimer )
{
/* The timer has expired - so no button pushes have occurred in the last
five seconds - turn the LED off. NOTE - accessing the LED port should use
a critical section because it is accessed from multiple tasks, and the
button interrupt - in this trivial case, for simplicity, the critical
section is omitted. */
FM3_GPIO->PDOR3 |= mainTIMER_CONTROLLED_LED;
}
/*-----------------------------------------------------------*/
/* The ISR executed when the user button is pushed. */
void INT0_7_Handler( void )
{
portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE;
/* The button was pushed, so ensure the LED is on before resetting the
LED timer. The LED timer will turn the LED off if the button is not
pushed within 5000ms. */
FM3_GPIO->PDOR3 &= ~mainTIMER_CONTROLLED_LED;
/* This interrupt safe FreeRTOS function can be called from this interrupt
because the interrupt priority is below the
configMAX_SYSCALL_INTERRUPT_PRIORITY setting in FreeRTOSConfig.h. */
xTimerResetFromISR( xLEDTimer, &xHigherPriorityTaskWoken );
/* Clear the interrupt before leaving. This just clears all the interrupts
for simplicity, as only one is actually used in this simple demo anyway. */
FM3_EXTI->EICL = 0x0000;
/* If calling xTimerResetFromISR() caused a task (in this case the timer
service/daemon task) to unblock, and the unblocked task has a priority
higher than or equal to the task that was interrupted, then
xHigherPriorityTaskWoken will now be set to pdTRUE, and calling
portEND_SWITCHING_ISR() will ensure the unblocked task runs next. */
portEND_SWITCHING_ISR( xHigherPriorityTaskWoken );
}
/*-----------------------------------------------------------*/
static void prvQueueSendTask( void *pvParameters )
{
portTickType xNextWakeTime;
const unsigned long ulValueToSend = 100UL;
/* Initialise xNextWakeTime - this only needs to be done once. */
xNextWakeTime = xTaskGetTickCount();
for( ;; )
{
/* Place this task in the blocked state until it is time to run again.
The block time is specified in ticks, the constant used converts ticks
to ms. While in the Blocked state this task will not consume any CPU
time. */
vTaskDelayUntil( &xNextWakeTime, mainQUEUE_SEND_FREQUENCY_MS );
/* Send to the queue - causing the queue receive task to unblock and
toggle an LED. 0 is used as the block time so the sending operation
will not block - it shouldn't need to block as the queue should always
be empty at this point in the code. */
xQueueSend( xQueue, &ulValueToSend, 0 );
}
}
/*-----------------------------------------------------------*/
static void prvQueueReceiveTask( void *pvParameters )
{
unsigned long ulReceivedValue;
for( ;; )
{
/* Wait until something arrives in the queue - this task will block
indefinitely provided INCLUDE_vTaskSuspend is set to 1 in
FreeRTOSConfig.h. */
xQueueReceive( xQueue, &ulReceivedValue, portMAX_DELAY );
/* To get here something must have been received from the queue, but
is it the expected value? If it is, toggle the LED. */
if( ulReceivedValue == 100UL )
{
/* NOTE - accessing the LED port should use a critical section
because it is accessed from multiple tasks, and the button interrupt
- in this trivial case, for simplicity, the critical section is
omitted. */
if( ( FM3_GPIO->PDOR3 & mainTASK_CONTROLLED_LED ) != 0 )
{
FM3_GPIO->PDOR3 &= ~mainTASK_CONTROLLED_LED;
}
else
{
FM3_GPIO->PDOR3 |= mainTASK_CONTROLLED_LED;
}
}
}
}
/*-----------------------------------------------------------*/
static void prvSetupHardware( void )
{
const unsigned short usButtonInputBit = 0x01U;
SystemInit();
SystemCoreClockUpdate();
/* Analog inputs are not used on the LED outputs. */
FM3_GPIO->ADE = 0x0000;
/* Set to output. */
FM3_GPIO->DDR1 |= 0xFFFF;
FM3_GPIO->DDR3 |= 0xFFFF;
/* Set as GPIO. */
FM3_GPIO->PFR1 &= 0x0000;
FM3_GPIO->PFR3 &= 0x0000;
/* Start with all LEDs off. */
FM3_GPIO->PDOR3 = 0xFFFF;
FM3_GPIO->PDOR1 = 0xFFFF;
/* Set the switches to input (P18->P1F). */
FM3_GPIO->DDR5 = 0x0000;
FM3_GPIO->PFR5 = 0x0000;
/* Assign the button input as GPIO. */
FM3_GPIO->PFR1 |= usButtonInputBit;
/* Button interrupt on falling edge. */
FM3_EXTI->ELVR = 0x0003;
/* Clear all external interrupts. */
FM3_EXTI->EICL = 0x0000;
/* Enable the button interrupt. */
FM3_EXTI->ENIR |= usButtonInputBit;
/* Setup the GPIO and the NVIC for the switch used in this simple demo. */
NVIC_SetPriority( EXINT0_7_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
NVIC_EnableIRQ( EXINT0_7_IRQn );
}
/*-----------------------------------------------------------*/
void vApplicationMallocFailedHook( void )
{
/* Called if a call to pvPortMalloc() fails because there is insufficient
free memory available in the FreeRTOS heap. pvPortMalloc() is called
internally by FreeRTOS API functions that create tasks, queues, software
timers, and semaphores. The size of the FreeRTOS heap is set by the
configTOTAL_HEAP_SIZE configuration constant in FreeRTOSConfig.h. */
for( ;; );
}
/*-----------------------------------------------------------*/
void vApplicationStackOverflowHook( xTaskHandle *pxTask, signed char *pcTaskName )
{
( void ) pcTaskName;
( void ) pxTask;
/* Run time stack overflow checking is performed if
configconfigCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook
function is called if a stack overflow is detected. */
for( ;; );
}
/*-----------------------------------------------------------*/
void vApplicationTickHook( void )
{
/* A tick hook is used by the "Full" build configuration. The Full and
blinky build configurations share a FreeRTOSConfig.h header file, so this
simple build configuration also has to define a tick hook - even though it
does not actually use it for anything. */
}
/*-----------------------------------------------------------*/
void vApplicationIdleHook( void )
{
volatile size_t xFreeHeapSpace;
/* This function is called on each cycle of the idle task. In this case it
does nothing useful, other than report the amount of FreeRTOS heap that
remains unallocated. */
xFreeHeapSpace = xPortGetFreeHeapSize();
if( xFreeHeapSpace > 100 )
{
/* By now, the kernel has allocated everything it is going to, so
if there is a lot of heap remaining unallocated then
the value of configTOTAL_HEAP_SIZE in FreeRTOSConfig.h can be
reduced accordingly. */
}
}
/*-----------------------------------------------------------*/

298
Demo/CORTEX_MB9A310_IAR_Keil/serial.c Normal file
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@ -0,0 +1,298 @@
/*
FreeRTOS V7.0.1 - Copyright (C) 2011 Real Time Engineers Ltd.
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>NOTE<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel. FreeRTOS is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details. You should have received a copy of the GNU General Public
License and the FreeRTOS license exception along with FreeRTOS; if not it
can be viewed here: http://www.freertos.org/a00114.html and also obtained
by writing to Richard Barry, contact details for whom are available on the
FreeRTOS WEB site.
1 tab == 4 spaces!
http://www.FreeRTOS.org - Documentation, latest information, license and
contact details.
http://www.SafeRTOS.com - A version that is certified for use in safety
critical systems.
http://www.OpenRTOS.com - Commercial support, development, porting,
licensing and training services.
*/
/*
BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR UART0.
***Note*** This example uses queues to send each character into an interrupt
service routine and out of an interrupt service routine individually. This
is done to demonstrate queues being used in an interrupt, and to deliberately
load the system to test the FreeRTOS port. It is *NOT* meant to be an
example of an efficient implementation. An efficient implementation should
use FIFOs or DMA if available, and only use FreeRTOS API functions when
enough has been received to warrant a task being unblocked to process the
data.
*/
/* Scheduler includes. */
#include "FreeRTOS.h"
#include "queue.h"
#include "semphr.h"
#include "comtest2.h"
/* Library includes. */
#include "mcu.h"
/* Demo application includes. */
#include "serial.h"
/*-----------------------------------------------------------*/
/* Register bit definitions. */
#define serRX_INT_ENABLE 0x10
#define serTX_INT_ENABLE 0x08
#define serRX_ENABLE 0x02
#define serTX_ENABLE 0x01
#define serORE_ERROR_BIT 0x08
#define serFRE_ERROR_BIT 0x10
#define serPE_ERROR_BIT 0x20
#define serRX_INT 0x04
#define serTX_INT 0x02
/* Misc defines. */
#define serINVALID_QUEUE ( ( xQueueHandle ) 0 )
#define serNO_BLOCK ( ( portTickType ) 0 )
/*-----------------------------------------------------------*/
/* The queue used to hold received characters. */
static xQueueHandle xRxedChars;
static xQueueHandle xCharsForTx;
/*-----------------------------------------------------------*/
/*
* See the serial2.h header file.
*/
xComPortHandle xSerialPortInitMinimal( unsigned long ulWantedBaud, unsigned portBASE_TYPE uxQueueLength )
{
/* Create the queues used to hold Rx/Tx characters. */
xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed char ) );
xCharsForTx = xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE ) sizeof( signed char ) );
/* If the queues were created correctly then setup the serial port
hardware. */
if( ( xRxedChars != serINVALID_QUEUE ) && ( xCharsForTx != serINVALID_QUEUE ) )
{
/* Ensure interrupts don't fire during the init process. Interrupts
will be enabled automatically when the first task start running. */
portDISABLE_INTERRUPTS();
/* Configure P21 and P22 for use by the UART. */
FM3_GPIO->PFR2 |= ( 1 << 0x01 ) | ( 1 << 0x02 );
/* SIN0_0 and SOT0_0. */
FM3_GPIO->EPFR07 |= ( 1 << 6 );
/* Reset. */
FM3_MFS0_UART->SCR = 0x80;
/* Enable output in mode 0. */
FM3_MFS0_UART->SMR = 0x01;
/* Clear all errors that may already be present. */
FM3_MFS0_UART->SSR = 0x00;
FM3_MFS0_UART->ESCR = 0x00;
FM3_MFS0_UART->BGR = ( configCPU_CLOCK_HZ / 2UL ) / ( ulWantedBaud - 1UL );
/* Enable Rx, Tx, and the Rx interrupt. */
FM3_MFS0_UART->SCR |= ( serRX_ENABLE | serTX_ENABLE | serRX_INT_ENABLE );
/* Configure the NVIC for UART interrupts. */
NVIC_ClearPendingIRQ( MFS0RX_IRQn );
NVIC_EnableIRQ( MFS0RX_IRQn );
/* The priority *MUST* be at or below
configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY as FreeRTOS API functions
are called in the interrupt handler. */
NVIC_SetPriority( MFS0RX_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
/* Do the same for the Tx interrupts. */
NVIC_ClearPendingIRQ( MFS0TX_IRQn );
NVIC_EnableIRQ( MFS0TX_IRQn );
/* The priority *MUST* be at or below
configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY as FreeRTOS API functions
are called in the interrupt handler. */
NVIC_SetPriority( MFS0TX_IRQn, configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY );
}
/* This demo file only supports a single port but we have to return
something to comply with the standard demo header file. */
return ( xComPortHandle ) 0;
}
/*-----------------------------------------------------------*/
signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed char *pcRxedChar, portTickType xBlockTime )
{
/* The port handle is not required as this driver only supports one port. */
( void ) pxPort;
/* Get the next character from the buffer. Return false if no characters
are available, or arrive before xBlockTime expires. */
if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) )
{
return pdTRUE;
}
else
{
return pdFALSE;
}
}
/*-----------------------------------------------------------*/
void vSerialPutString( xComPortHandle pxPort, const signed char * const pcString, unsigned short usStringLength )
{
signed char *pxNext;
/* A couple of parameters that this port does not use. */
( void ) usStringLength;
( void ) pxPort;
/* NOTE: This implementation does not handle the queue being full as no
block time is used! */
/* The port handle is not required as this driver only supports one UART. */
( void ) pxPort;
/* Send each character in the string, one at a time. */
pxNext = ( signed char * ) pcString;
while( *pxNext )
{
xSerialPutChar( pxPort, *pxNext, serNO_BLOCK );
pxNext++;
}
}
/*-----------------------------------------------------------*/
signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed char cOutChar, portTickType xBlockTime )
{
signed portBASE_TYPE xReturn;
if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) == pdPASS )
{
xReturn = pdPASS;
/* Enable the UART Tx interrupt. */
FM3_MFS0_UART->SCR |= serTX_INT_ENABLE;
}
else
{
xReturn = pdFAIL;
}
return xReturn;
}
/*-----------------------------------------------------------*/
void vSerialClose( xComPortHandle xPort )
{
/* Not supported as not required by the demo application. */
}
/*-----------------------------------------------------------*/
void MFS0RX_IRQHandler( void )
{
portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE;
char cChar;
if( ( FM3_MFS0_UART->SSR & ( serORE_ERROR_BIT | serFRE_ERROR_BIT | serPE_ERROR_BIT ) ) != 0 )
{
/* A PE, ORE or FRE error occurred. Clear it. */
FM3_MFS0_UART->SSR |= ( 1 << 7 );
cChar = FM3_MFS0_UART->RDR;
}
else if( FM3_MFS0_UART->SSR & serRX_INT )
{
/* A character has been received on the USART, send it to the Rx
handler task. */
cChar = FM3_MFS0_UART->RDR;
xQueueSendFromISR( xRxedChars, &cChar, &xHigherPriorityTaskWoken );
}
/* If sending or receiving from a queue has caused a task to unblock, and
the unblocked task has a priority equal to or higher than the currently
running task (the task this ISR interrupted), then xHigherPriorityTaskWoken
will have automatically been set to pdTRUE within the queue send or receive
function. portEND_SWITCHING_ISR() will then ensure that this ISR returns
directly to the higher priority unblocked task. */
portEND_SWITCHING_ISR( xHigherPriorityTaskWoken );
}
/*-----------------------------------------------------------*/
void MFS0TX_IRQHandler( void )
{
portBASE_TYPE xHigherPriorityTaskWoken = pdFALSE;
char cChar;
if( FM3_MFS0_UART->SSR & serTX_INT )
{
/* The interrupt was caused by the TX register becoming empty. Are
there any more characters to transmit? */
if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xHigherPriorityTaskWoken ) == pdTRUE )
{
/* A character was retrieved from the queue so can be sent to the
USART now. */
FM3_MFS0_UART->TDR = cChar;
}
else
{
/* Disable the Tx interrupt. */
FM3_MFS0_UART->SCR &= ~serTX_INT_ENABLE;
}
}
/* If sending or receiving from a queue has caused a task to unblock, and
the unblocked task has a priority equal to or higher than the currently
running task (the task this ISR interrupted), then xHigherPriorityTaskWoken
will have automatically been set to pdTRUE within the queue send or receive
function. portEND_SWITCHING_ISR() will then ensure that this ISR returns
directly to the higher priority unblocked task. */
portEND_SWITCHING_ISR( xHigherPriorityTaskWoken );
}