+* +* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- -------- -------------------------------------------------------- +* 1.00a sv 06/29/05 Created for Test App Integration +* 1.00c sn 05/09/06 Added Interrupt Setup Function +*+******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xparameters.h" +#include "xstatus.h" +#include "xintc.h" +#ifdef __MICROBLAZE__ +#include "mb_interface.h" +#endif +#ifdef __PPC__ +#include "xexception_l.h" +#endif + + +/************************** Constant Definitions *****************************/ + +/* + * The following constants map to the XPAR parameters created in the + * xparameters.h file. They are defined here such that a user can easily + * change all the needed parameters in one place. This definition is not + * included if the example is generated from the TestAppGen test tool. + */ +#ifndef TESTAPP_GEN +#define INTC_DEVICE_ID XPAR_OPB_INTC_0_DEVICE_ID +#endif + +/**************************** Type Definitions *******************************/ + + +/***************** Macros (Inline Functions) Definitions *********************/ + + +/************************** Function Prototypes ******************************/ + +XStatus IntcSelfTestExample(Xuint16 DeviceId); +XStatus IntcInterruptSetup(XIntc *IntcInstancePtr, Xuint16 DeviceId); + +/************************** Variable Definitions *****************************/ + +static XIntc InterruptController; /* Instance of the Interrupt Controller */ + + +/*****************************************************************************/ +/** +* +* This is the main function for the Interrupt Controller example. This +* function is not included if the example is generated from the TestAppGen test +* tool. +* +* @param None. +* +* @return XST_SUCCESS to indicate success, otherwise XST_FAILURE. +* +* @note None. +* +******************************************************************************/ +#ifndef TESTAPP_GEN +int main(void) +{ + XStatus Status; + + /* + * Run the Intc example , specify the Device ID generated in xparameters.h + */ + Status = IntcSelfTestExample(INTC_DEVICE_ID); + if (Status != XST_SUCCESS) + { + return XST_FAILURE; + } + + return XST_SUCCESS; + +} +#endif + +/*****************************************************************************/ +/** +* +* This function runs a self-test on the driver/device. This is a destructive +* test. This function is an example of how to use the interrupt controller +* driver component (XIntc) and the hardware device. This function is designed +* to work without any hardware devices to cause interrupts. It may not return +* if the interrupt controller is not properly connected to the processor in +* either software or hardware. +* +* This function relies on the fact that the interrupt controller hardware +* has come out of the reset state such that it will allow interrupts to be +* simulated by the software. +* +* @param DeviceId is device ID of the Interrupt Controller Device , typically +* XPAR_
+* MODIFICATION HISTORY: +* +* Ver Who Date Changes +* ----- ---- -------- ----------------------------------------------- +* 1.00b sv 06/08/06 Created for supporting Test App Interrupt examples +*+******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xparameters.h" +#include "xuartlite.h" +#include "xintc.h" + +#ifdef __MICROBLAZE__ +#include "mb_interface.h" +#else +#include "xexception_l.h" +#endif + + +/************************** Constant Definitions *****************************/ + +/* + * The following constants map to the XPAR parameters created in the + * xparameters.h file. They are defined here such that a user can easily + * change all the needed parameters in one place. + */ +#ifndef TESTAPP_GEN +#define UARTLITE_DEVICE_ID XPAR_RS232_UART_DEVICE_ID +#define INTC_DEVICE_ID XPAR_OPB_INTC_0_DEVICE_ID +#define UARTLITE_IRPT_INTR XPAR_OPB_INTC_0_RS232_UART_INTERRUPT_INTR +#endif + +/* + * The following constant controls the length of the buffers to be sent + * and received with the UartLite device. + */ +#define TEST_BUFFER_SIZE 100 + + +/**************************** Type Definitions *******************************/ + + +/***************** Macros (Inline Functions) Definitions *********************/ + + +/************************** Function Prototypes ******************************/ + +XStatus UartLiteIntrExample(XIntc *IntcInstancePtr, + XUartLite *UartLiteInstancePtr, + Xuint16 UartLiteDeviceId, + Xuint16 UartLiteIntrId); + + +static void UartLiteSendHandler(void *CallBackRef, unsigned int EventData); + +static void UartLiteRecvHandler(void *CallBackRef, unsigned int EventData); + + +static XStatus UartLiteSetupIntrSystem(XIntc *IntcInstancePtr, + XUartLite *UartLiteInstancePtr, + Xuint16 UartLiteIntrId); + +static void UartLiteDisableIntrSystem(XIntc *IntrInstancePtr, + Xuint16 UartLiteIntrId); + + +/************************** Variable Definitions *****************************/ + +/* + * The instances to support the device drivers are global such that the + * are initialized to zero each time the program runs. + */ +#ifndef TESTAPP_GEN +static XIntc IntcInstance; /* The instance of the Interrupt Controller */ +static XUartLite UartLiteInst; /* The instance of the UartLite Device */ +#endif + + + +/* + * The following variables are shared between non-interrupt processing and + * interrupt processing such that they must be global. + */ + +/* + * The following buffers are used in this example to send and receive data + * with the UartLite. + */ +Xuint8 SendBuffer[TEST_BUFFER_SIZE]; +Xuint8 ReceiveBuffer[TEST_BUFFER_SIZE]; + +/* + * The following counter is used to determine when the entire buffer has + * been sent. + */ +static volatile int TotalSentCount; + + +/******************************************************************************/ +/** +* +* Main function to call the UartLite interrupt example. +* +* @param None. +* +* @return XST_SUCCESS if successful, else XST_FAILURE. +* +* @note None +* +*******************************************************************************/ +#ifndef TESTAPP_GEN +int main(void) +{ + XStatus Status; + + /* + * Run the UartLite Interrupt example , specify the Device ID that is + * generated in xparameters.h. + */ + Status = UartLiteIntrExample(&IntcInstance, + &UartLiteInst, + UARTLITE_DEVICE_ID, + UARTLITE_IRPT_INTR); + if (Status != XST_SUCCESS) + { + return XST_FAILURE; + } + + return XST_SUCCESS; +} +#endif + +/****************************************************************************/ +/** +* +* This function does a minimal test on the UartLite device and driver as a +* design example. The purpose of this function is to illustrate how to use +* the XUartLite component. +* +* This function sends data and expects to receive the same data through the +* UartLite. The user must provide a physical loopback such that data which +* is transmitted will be received. +* +* This function uses the interrupt driver mode of the UartLite. The calls to +* the UartLite driver in the interrupt handlers, should only use the +* non-blocking calls. +* +* @param IntcInstancePtr is a pointer to the instance of the INTC component. +* @param UartLiteInstPtr is a pointer to the instance of UartLite component. +* @param UartLiteDeviceId is the Device ID of the UartLite Device and is the +* XPAR_
+* Ver Who Date Changes +* ----- ---- -------- ----------------------------------------------- +* 1.00a ecm 01/25/04 First Release. +* 1.00a sv 06/13/05 Minor changes to comply to Doxygen and Coding guidelines +*+******************************************************************************/ + +/***************************** Include Files *********************************/ + +#include "xparameters.h" +#include "xuartlite.h" + +/************************** Constant Definitions *****************************/ + +/* + * The following constants map to the XPAR parameters created in the + * xparameters.h file. They are defined here such that a user can easily + * change all the needed parameters in one place. + */ +#define UARTLITE_DEVICE_ID XPAR_RS232_UART_DEVICE_ID + + +/**************************** Type Definitions *******************************/ + + +/***************** Macros (Inline Functions) Definitions *********************/ + + +/************************** Function Prototypes ******************************/ + +XStatus UartLiteSelfTestExample(Xuint16 DeviceId); + +/************************** Variable Definitions *****************************/ + +XUartLite UartLite; /* Instance of the UartLite device */ + +/*****************************************************************************/ +/** +* +* Main function to call the example. This function is not included if the +* example is generated from the TestAppGen test tool. +* +* @param None. +* +* @return XST_SUCCESS if succesful, otherwise XST_FAILURE. +* +* @note None. +* +******************************************************************************/ +#ifndef TESTAPP_GEN +int main(void) +{ + XStatus Status; + + /* + * Run the UartLite self test example, specify the the Device ID that is + * generated in xparameters.h + */ + Status = UartLiteSelfTestExample(UARTLITE_DEVICE_ID); + if (Status != XST_SUCCESS) + { + return XST_FAILURE; + } + + return XST_SUCCESS; + +} +#endif + +/*****************************************************************************/ +/** +* +* This function does a minimal test on the UartLite device and driver as a +* design example. The purpose of this function is to illustrate +* how to use the XUartLite component. +* +* +* @param DeviceId is the XPAR_
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+ + The attributes are obtained from the SIGIS and IOB_STATE parameters set on the PORT in the MHS file + + CLK + indicates Clock ports, (SIGIS = CLK) + + INTR + indicates Interrupt ports,(SIGIS = INTR) + + RESET + indicates Reset ports, (SIGIS = RST) + + BUF or REG + Indicates ports that instantiate or infer IOB primitives, (IOB_STATE = BUF or REG) + |
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| # | +NAME | +DIR | +SIGNAL | +
| TABLE OF CONTENTS | +
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+ + Overview + + + Block Diagram + + + External Ports + + +
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+Attributes Key The attributes are obtained from the SIGIS and IOB_STATE parameters set on the PORT in the MHS file CLK indicates Clock ports, (SIGIS = CLK) INTR indicates Interrupt ports,(SIGIS = INTR) RESET indicates Reset ports, (SIGIS = RST) BUF or REG Indicates ports that instantiate or infer IOB primitives, (IOB_STATE = BUF or REG) + |
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+ + diff --git a/Demo/PPC405_Xilinx_Virtex4_GCC/blkdiagram/system.svg b/Demo/PPC405_Xilinx_Virtex4_GCC/blkdiagram/system.svg new file mode 100644 index 000000000..4af3f7fa1 --- /dev/null +++ b/Demo/PPC405_Xilinx_Virtex4_GCC/blkdiagram/system.svg @@ -0,0 +1,1427 @@ + + + + diff --git a/Demo/PPC405_Xilinx_Virtex4_GCC/data/system.ucf b/Demo/PPC405_Xilinx_Virtex4_GCC/data/system.ucf new file mode 100644 index 000000000..ed2e6bbe7 --- /dev/null +++ b/Demo/PPC405_Xilinx_Virtex4_GCC/data/system.ucf @@ -0,0 +1,339 @@ +############################################################################ +## This system.ucf file is generated by Base System Builder based on the +## settings in the selected Xilinx Board Definition file. Please add other +## user constraints to this file based on customer design specifications. +############################################################################ + +Net sys_clk_pin LOC=AE14; +Net sys_clk_pin IOSTANDARD = LVCMOS33; +Net sys_rst_pin LOC=D6; +Net sys_rst_pin PULLUP; +## System level constraints +Net sys_clk_pin TNM_NET = sys_clk_pin; +TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 10000 ps; +Net sys_rst_pin TIG; +NET "ppc_reset_bus_Chip_Reset_Req" TPTHRU = "RST_GRP"; +NET "ppc_reset_bus_Core_Reset_Req" TPTHRU = "RST_GRP"; +NET "ppc_reset_bus_System_Reset_Req" TPTHRU = "RST_GRP"; +TIMESPEC "TS_RST1" = FROM CPUS THRU RST_GRP TO FFS TIG; +Net fpga_0_SRAM_CLOCK LOC=AF7; +Net fpga_0_SRAM_CLOCK SLEW = FAST; +Net fpga_0_SRAM_CLOCK IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_CLOCK DRIVE = 16; + +## IO Devices constraints + +#### Module RS232_Uart constraints + +Net fpga_0_RS232_Uart_RX_pin LOC=W2; +Net fpga_0_RS232_Uart_RX_pin IOSTANDARD = LVCMOS33; +Net fpga_0_RS232_Uart_TX_pin LOC=W1; +Net fpga_0_RS232_Uart_TX_pin IOSTANDARD = LVCMOS33; + +#### Module LEDs_4Bit constraints + +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> LOC=G5; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> IOSTANDARD = LVCMOS25; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> PULLUP; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> SLEW = SLOW; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> DRIVE = 2; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<0> TIG; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> LOC=G6; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> IOSTANDARD = LVCMOS25; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> PULLUP; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> SLEW = SLOW; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> DRIVE = 2; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<1> TIG; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> LOC=A11; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> IOSTANDARD = LVCMOS25; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> PULLUP; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> SLEW = SLOW; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> DRIVE = 2; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<2> TIG; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> LOC=A12; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> IOSTANDARD = LVCMOS25; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> PULLUP; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> SLEW = SLOW; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> DRIVE = 2; +Net fpga_0_LEDs_4Bit_GPIO_IO_pin<3> TIG; + +#### Module LEDs_Positions constraints + +Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> LOC=C6; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> IOSTANDARD = LVCMOS25; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> PULLUP; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> SLEW = SLOW; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> DRIVE = 2; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<0> TIG; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> LOC=F9; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> IOSTANDARD = LVCMOS25; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> PULLUP; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> SLEW = SLOW; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> DRIVE = 2; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<1> TIG; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> LOC=A5; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> IOSTANDARD = LVCMOS25; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> PULLUP; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> SLEW = SLOW; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> DRIVE = 2; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<2> TIG; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> LOC=E10; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> IOSTANDARD = LVCMOS25; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> PULLUP; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> SLEW = SLOW; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> DRIVE = 2; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<3> TIG; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> LOC=E2; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> IOSTANDARD = LVCMOS25; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> PULLUP; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> SLEW = SLOW; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> DRIVE = 2; +Net fpga_0_LEDs_Positions_GPIO_IO_pin<4> TIG; + +#### Module SRAM constraints + +Net fpga_0_SRAM_Mem_A_pin<29> LOC=Y1; +Net fpga_0_SRAM_Mem_A_pin<29> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<29> SLEW = FAST; +Net fpga_0_SRAM_Mem_A_pin<29> DRIVE = 8; +Net fpga_0_SRAM_Mem_A_pin<28> LOC=Y2; +Net fpga_0_SRAM_Mem_A_pin<28> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<28> SLEW = FAST; +Net fpga_0_SRAM_Mem_A_pin<28> DRIVE = 8; +Net fpga_0_SRAM_Mem_A_pin<27> LOC=AA1; +Net fpga_0_SRAM_Mem_A_pin<27> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<27> SLEW = FAST; +Net fpga_0_SRAM_Mem_A_pin<27> DRIVE = 8; +Net fpga_0_SRAM_Mem_A_pin<26> LOC=AB1; +Net fpga_0_SRAM_Mem_A_pin<26> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<26> SLEW = FAST; +Net fpga_0_SRAM_Mem_A_pin<26> DRIVE = 8; +Net fpga_0_SRAM_Mem_A_pin<25> LOC=AB2; +Net fpga_0_SRAM_Mem_A_pin<25> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<25> SLEW = FAST; +Net fpga_0_SRAM_Mem_A_pin<25> DRIVE = 8; +Net fpga_0_SRAM_Mem_A_pin<24> LOC=AC1; +Net fpga_0_SRAM_Mem_A_pin<24> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<24> SLEW = FAST; +Net fpga_0_SRAM_Mem_A_pin<24> DRIVE = 8; +Net fpga_0_SRAM_Mem_A_pin<23> LOC=AC2; +Net fpga_0_SRAM_Mem_A_pin<23> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<23> SLEW = FAST; +Net fpga_0_SRAM_Mem_A_pin<23> DRIVE = 8; +Net fpga_0_SRAM_Mem_A_pin<22> LOC=AD1; +Net fpga_0_SRAM_Mem_A_pin<22> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<22> SLEW = FAST; +Net fpga_0_SRAM_Mem_A_pin<22> DRIVE = 8; +Net fpga_0_SRAM_Mem_A_pin<21> LOC=AD2; +Net fpga_0_SRAM_Mem_A_pin<21> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<21> SLEW = FAST; +Net fpga_0_SRAM_Mem_A_pin<21> DRIVE = 8; +Net fpga_0_SRAM_Mem_A_pin<20> LOC=AE3; +Net fpga_0_SRAM_Mem_A_pin<20> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<20> SLEW = FAST; +Net fpga_0_SRAM_Mem_A_pin<20> DRIVE = 8; +Net fpga_0_SRAM_Mem_A_pin<19> LOC=AF3; +Net fpga_0_SRAM_Mem_A_pin<19> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<19> SLEW = FAST; +Net fpga_0_SRAM_Mem_A_pin<19> DRIVE = 8; +Net fpga_0_SRAM_Mem_A_pin<18> LOC=W3; +Net fpga_0_SRAM_Mem_A_pin<18> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<18> SLEW = FAST; +Net fpga_0_SRAM_Mem_A_pin<18> DRIVE = 8; +Net fpga_0_SRAM_Mem_A_pin<17> LOC=W6; +Net fpga_0_SRAM_Mem_A_pin<17> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<17> SLEW = FAST; +Net fpga_0_SRAM_Mem_A_pin<17> DRIVE = 8; +Net fpga_0_SRAM_Mem_A_pin<16> LOC=W5; +Net fpga_0_SRAM_Mem_A_pin<16> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<16> SLEW = FAST; +Net fpga_0_SRAM_Mem_A_pin<16> DRIVE = 8; +Net fpga_0_SRAM_Mem_A_pin<15> LOC=AA3; +Net fpga_0_SRAM_Mem_A_pin<15> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<15> SLEW = FAST; +Net fpga_0_SRAM_Mem_A_pin<15> DRIVE = 8; +Net fpga_0_SRAM_Mem_A_pin<14> LOC=AA4; +Net fpga_0_SRAM_Mem_A_pin<14> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<14> SLEW = FAST; +Net fpga_0_SRAM_Mem_A_pin<14> DRIVE = 8; +Net fpga_0_SRAM_Mem_A_pin<13> LOC=AB3; +Net fpga_0_SRAM_Mem_A_pin<13> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<13> SLEW = FAST; +Net fpga_0_SRAM_Mem_A_pin<13> DRIVE = 8; +Net fpga_0_SRAM_Mem_A_pin<12> LOC=AB4; +Net fpga_0_SRAM_Mem_A_pin<12> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<12> SLEW = FAST; +Net fpga_0_SRAM_Mem_A_pin<12> DRIVE = 8; +Net fpga_0_SRAM_Mem_A_pin<11> LOC=AC4; +Net fpga_0_SRAM_Mem_A_pin<11> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<11> SLEW = FAST; +Net fpga_0_SRAM_Mem_A_pin<11> DRIVE = 8; +Net fpga_0_SRAM_Mem_A_pin<10> LOC=AB5; +Net fpga_0_SRAM_Mem_A_pin<10> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<10> SLEW = FAST; +Net fpga_0_SRAM_Mem_A_pin<10> DRIVE = 8; +Net fpga_0_SRAM_Mem_A_pin<9> LOC=AC5; +Net fpga_0_SRAM_Mem_A_pin<9> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_A_pin<9> SLEW = FAST; +Net fpga_0_SRAM_Mem_A_pin<9> DRIVE = 8; +Net fpga_0_SRAM_Mem_BEN_pin<3> LOC=Y6; +Net fpga_0_SRAM_Mem_BEN_pin<3> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_BEN_pin<3> SLEW = FAST; +Net fpga_0_SRAM_Mem_BEN_pin<3> DRIVE = 8; +Net fpga_0_SRAM_Mem_BEN_pin<2> LOC=Y5; +Net fpga_0_SRAM_Mem_BEN_pin<2> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_BEN_pin<2> SLEW = FAST; +Net fpga_0_SRAM_Mem_BEN_pin<2> DRIVE = 8; +Net fpga_0_SRAM_Mem_BEN_pin<1> LOC=Y4; +Net fpga_0_SRAM_Mem_BEN_pin<1> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_BEN_pin<1> SLEW = FAST; +Net fpga_0_SRAM_Mem_BEN_pin<1> DRIVE = 8; +Net fpga_0_SRAM_Mem_BEN_pin<0> LOC=Y3; +Net fpga_0_SRAM_Mem_BEN_pin<0> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_BEN_pin<0> SLEW = FAST; +Net fpga_0_SRAM_Mem_BEN_pin<0> DRIVE = 8; +Net fpga_0_SRAM_Mem_WEN_pin LOC=AB6; +Net fpga_0_SRAM_Mem_WEN_pin IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_WEN_pin SLEW = FAST; +Net fpga_0_SRAM_Mem_WEN_pin DRIVE = 8; +Net fpga_0_SRAM_Mem_DQ_pin<31> LOC=AD13; +Net fpga_0_SRAM_Mem_DQ_pin<31> SLEW = FAST; +Net fpga_0_SRAM_Mem_DQ_pin<31> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<31> DRIVE = 12; +Net fpga_0_SRAM_Mem_DQ_pin<30> LOC=AC13; +Net fpga_0_SRAM_Mem_DQ_pin<30> SLEW = FAST; +Net fpga_0_SRAM_Mem_DQ_pin<30> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<30> DRIVE = 12; +Net fpga_0_SRAM_Mem_DQ_pin<29> LOC=AC15; +Net fpga_0_SRAM_Mem_DQ_pin<29> SLEW = FAST; +Net fpga_0_SRAM_Mem_DQ_pin<29> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<29> DRIVE = 12; +Net fpga_0_SRAM_Mem_DQ_pin<28> LOC=AC16; +Net fpga_0_SRAM_Mem_DQ_pin<28> SLEW = FAST; +Net fpga_0_SRAM_Mem_DQ_pin<28> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<28> DRIVE = 12; +Net fpga_0_SRAM_Mem_DQ_pin<27> LOC=AA11; +Net fpga_0_SRAM_Mem_DQ_pin<27> SLEW = FAST; +Net fpga_0_SRAM_Mem_DQ_pin<27> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<27> DRIVE = 12; +Net fpga_0_SRAM_Mem_DQ_pin<26> LOC=AA12; +Net fpga_0_SRAM_Mem_DQ_pin<26> SLEW = FAST; +Net fpga_0_SRAM_Mem_DQ_pin<26> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<26> DRIVE = 12; +Net fpga_0_SRAM_Mem_DQ_pin<25> LOC=AD14; +Net fpga_0_SRAM_Mem_DQ_pin<25> SLEW = FAST; +Net fpga_0_SRAM_Mem_DQ_pin<25> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<25> DRIVE = 12; +Net fpga_0_SRAM_Mem_DQ_pin<24> LOC=AC14; +Net fpga_0_SRAM_Mem_DQ_pin<24> SLEW = FAST; +Net fpga_0_SRAM_Mem_DQ_pin<24> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<24> DRIVE = 12; +Net fpga_0_SRAM_Mem_DQ_pin<23> LOC=AA13; +Net fpga_0_SRAM_Mem_DQ_pin<23> SLEW = FAST; +Net fpga_0_SRAM_Mem_DQ_pin<23> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<23> DRIVE = 12; +Net fpga_0_SRAM_Mem_DQ_pin<22> LOC=AB13; +Net fpga_0_SRAM_Mem_DQ_pin<22> SLEW = FAST; +Net fpga_0_SRAM_Mem_DQ_pin<22> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<22> DRIVE = 12; +Net fpga_0_SRAM_Mem_DQ_pin<21> LOC=AA15; +Net fpga_0_SRAM_Mem_DQ_pin<21> SLEW = FAST; +Net fpga_0_SRAM_Mem_DQ_pin<21> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<21> DRIVE = 12; +Net fpga_0_SRAM_Mem_DQ_pin<20> LOC=AA16; +Net fpga_0_SRAM_Mem_DQ_pin<20> SLEW = FAST; +Net fpga_0_SRAM_Mem_DQ_pin<20> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<20> DRIVE = 12; +Net fpga_0_SRAM_Mem_DQ_pin<19> LOC=AC11; +Net fpga_0_SRAM_Mem_DQ_pin<19> SLEW = FAST; +Net fpga_0_SRAM_Mem_DQ_pin<19> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<19> DRIVE = 12; +Net fpga_0_SRAM_Mem_DQ_pin<18> LOC=AC12; +Net fpga_0_SRAM_Mem_DQ_pin<18> SLEW = FAST; +Net fpga_0_SRAM_Mem_DQ_pin<18> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<18> DRIVE = 12; +Net fpga_0_SRAM_Mem_DQ_pin<17> LOC=AB14; +Net fpga_0_SRAM_Mem_DQ_pin<17> SLEW = FAST; +Net fpga_0_SRAM_Mem_DQ_pin<17> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<17> DRIVE = 12; +Net fpga_0_SRAM_Mem_DQ_pin<16> LOC=AA14; +Net fpga_0_SRAM_Mem_DQ_pin<16> SLEW = FAST; +Net fpga_0_SRAM_Mem_DQ_pin<16> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<16> DRIVE = 12; +Net fpga_0_SRAM_Mem_DQ_pin<15> LOC=D12; +Net fpga_0_SRAM_Mem_DQ_pin<15> SLEW = FAST; +Net fpga_0_SRAM_Mem_DQ_pin<15> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<15> DRIVE = 12; +Net fpga_0_SRAM_Mem_DQ_pin<14> LOC=E13; +Net fpga_0_SRAM_Mem_DQ_pin<14> SLEW = FAST; +Net fpga_0_SRAM_Mem_DQ_pin<14> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<14> DRIVE = 12; +Net fpga_0_SRAM_Mem_DQ_pin<13> LOC=C16; +Net fpga_0_SRAM_Mem_DQ_pin<13> SLEW = FAST; +Net fpga_0_SRAM_Mem_DQ_pin<13> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<13> DRIVE = 12; +Net fpga_0_SRAM_Mem_DQ_pin<12> LOC=D16; +Net fpga_0_SRAM_Mem_DQ_pin<12> SLEW = FAST; +Net fpga_0_SRAM_Mem_DQ_pin<12> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<12> DRIVE = 12; +Net fpga_0_SRAM_Mem_DQ_pin<11> LOC=D11; +Net fpga_0_SRAM_Mem_DQ_pin<11> SLEW = FAST; +Net fpga_0_SRAM_Mem_DQ_pin<11> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<11> DRIVE = 12; +Net fpga_0_SRAM_Mem_DQ_pin<10> LOC=C11; +Net fpga_0_SRAM_Mem_DQ_pin<10> SLEW = FAST; +Net fpga_0_SRAM_Mem_DQ_pin<10> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<10> DRIVE = 12; +Net fpga_0_SRAM_Mem_DQ_pin<9> LOC=E14; +Net fpga_0_SRAM_Mem_DQ_pin<9> SLEW = FAST; +Net fpga_0_SRAM_Mem_DQ_pin<9> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<9> DRIVE = 12; +Net fpga_0_SRAM_Mem_DQ_pin<8> LOC=D15; +Net fpga_0_SRAM_Mem_DQ_pin<8> SLEW = FAST; +Net fpga_0_SRAM_Mem_DQ_pin<8> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<8> DRIVE = 12; +Net fpga_0_SRAM_Mem_DQ_pin<7> LOC=D13; +Net fpga_0_SRAM_Mem_DQ_pin<7> SLEW = FAST; +Net fpga_0_SRAM_Mem_DQ_pin<7> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<7> DRIVE = 12; +Net fpga_0_SRAM_Mem_DQ_pin<6> LOC=D14; +Net fpga_0_SRAM_Mem_DQ_pin<6> SLEW = FAST; +Net fpga_0_SRAM_Mem_DQ_pin<6> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<6> DRIVE = 12; +Net fpga_0_SRAM_Mem_DQ_pin<5> LOC=F15; +Net fpga_0_SRAM_Mem_DQ_pin<5> SLEW = FAST; +Net fpga_0_SRAM_Mem_DQ_pin<5> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<5> DRIVE = 12; +Net fpga_0_SRAM_Mem_DQ_pin<4> LOC=F16; +Net fpga_0_SRAM_Mem_DQ_pin<4> SLEW = FAST; +Net fpga_0_SRAM_Mem_DQ_pin<4> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<4> DRIVE = 12; +Net fpga_0_SRAM_Mem_DQ_pin<3> LOC=F11; +Net fpga_0_SRAM_Mem_DQ_pin<3> SLEW = FAST; +Net fpga_0_SRAM_Mem_DQ_pin<3> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<3> DRIVE = 12; +Net fpga_0_SRAM_Mem_DQ_pin<2> LOC=F12; +Net fpga_0_SRAM_Mem_DQ_pin<2> SLEW = FAST; +Net fpga_0_SRAM_Mem_DQ_pin<2> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<2> DRIVE = 12; +Net fpga_0_SRAM_Mem_DQ_pin<1> LOC=F13; +Net fpga_0_SRAM_Mem_DQ_pin<1> SLEW = FAST; +Net fpga_0_SRAM_Mem_DQ_pin<1> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<1> DRIVE = 12; +Net fpga_0_SRAM_Mem_DQ_pin<0> LOC=F14; +Net fpga_0_SRAM_Mem_DQ_pin<0> SLEW = FAST; +Net fpga_0_SRAM_Mem_DQ_pin<0> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_DQ_pin<0> DRIVE = 12; +Net fpga_0_SRAM_Mem_OEN_pin<0> LOC=AC6; +Net fpga_0_SRAM_Mem_OEN_pin<0> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_OEN_pin<0> SLEW = FAST; +Net fpga_0_SRAM_Mem_OEN_pin<0> DRIVE = 8; +Net fpga_0_SRAM_Mem_CEN_pin<0> LOC=V7; +Net fpga_0_SRAM_Mem_CEN_pin<0> IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_CEN_pin<0> SLEW = FAST; +Net fpga_0_SRAM_Mem_CEN_pin<0> DRIVE = 8; +Net fpga_0_SRAM_Mem_ADV_LDN_pin LOC=W4; +Net fpga_0_SRAM_Mem_ADV_LDN_pin IOSTANDARD = LVCMOS33; +Net fpga_0_SRAM_Mem_ADV_LDN_pin SLEW = FAST; +Net fpga_0_SRAM_Mem_ADV_LDN_pin DRIVE = 8; + diff --git a/Demo/PPC405_Xilinx_Virtex4_GCC/etc/bitgen.ut b/Demo/PPC405_Xilinx_Virtex4_GCC/etc/bitgen.ut new file mode 100644 index 000000000..976536332 --- /dev/null +++ b/Demo/PPC405_Xilinx_Virtex4_GCC/etc/bitgen.ut @@ -0,0 +1,20 @@ +-g CclkPin:PULLUP +-g TdoPin:PULLNONE +-g M1Pin:PULLDOWN +-g DonePin:PULLUP +-g DriveDone:No +-g StartUpClk:JTAGCLK +-g DONE_cycle:4 +-g GTS_cycle:5 +-g M0Pin:PULLUP +-g M2Pin:PULLUP +-g ProgPin:PULLUP +-g TckPin:PULLUP +-g TdiPin:PULLUP +-g TmsPin:PULLUP +-g DonePipe:No +-g GWE_cycle:6 +-g LCK_cycle:NoWait +-g Security:NONE +#-m +-g Persist:No diff --git a/Demo/PPC405_Xilinx_Virtex4_GCC/etc/download.cmd b/Demo/PPC405_Xilinx_Virtex4_GCC/etc/download.cmd new file mode 100644 index 000000000..15728dcff --- /dev/null +++ b/Demo/PPC405_Xilinx_Virtex4_GCC/etc/download.cmd @@ -0,0 +1,6 @@ +setMode -bscan +setCable -p auto +identify +assignfile -p 3 -file implementation/download.bit +program -p 3 +quit diff --git a/Demo/PPC405_Xilinx_Virtex4_GCC/etc/fast_runtime.opt b/Demo/PPC405_Xilinx_Virtex4_GCC/etc/fast_runtime.opt new file mode 100644 index 000000000..6cc2599ab --- /dev/null +++ b/Demo/PPC405_Xilinx_Virtex4_GCC/etc/fast_runtime.opt @@ -0,0 +1,82 @@ +FLOWTYPE = FPGA; +############################################################### +## Filename: fast_runtime.opt +## +## Option File For Xilinx FPGA Implementation Flow for Fast +## Runtime. +## +## Version: 4.1.1 +############################################################### +# +# Options for Translator +# +# Type "ngdbuild -h" for a detailed list of ngdbuild command line options +# +Program ngdbuild +-p