mirror of
https://github.com/FreeRTOS/FreeRTOS-Kernel.git
synced 2025-04-19 21:11:57 -04:00
Update to allow nesting.
This commit is contained in:
Richard Barry
parent
b7f66b9db6
commit
bafcf8901e
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@ -49,12 +49,9 @@
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#include "FreeRTOSConfig.h"
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#define portCONTEXT_SIZE 136
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#define portEXL_AND_IE_BITS 0x03
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#define portCONTEXT_SIZE 132
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#define portEPC_STACK_LOCATION 124
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#define portSTATUS_STACK_LOCATION 128
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#define portCAUSE_STACK_LOCATION 132
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/******************************************************************/
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.macro portSAVE_CONTEXT
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@ -64,26 +61,16 @@
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original values in case of interrupt nesting. */
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mfc0 k0, _CP0_CAUSE
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addiu sp, sp, -portCONTEXT_SIZE
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sw k0, portCAUSE_STACK_LOCATION(sp)
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mfc0 k1, _CP0_STATUS
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/* Also save s6 and s5 so we can use them during this interrupt. Any
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nesting interrupts should maintain the values of these registers
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accross the ISR. */
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across the ISR. */
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sw s6, 44(sp)
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sw s5, 40(sp)
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sw k1, portSTATUS_STACK_LOCATION(sp)
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/* Enable interrupts above the current priority. SysCall interrupts
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enable priorities above configKERNEL_INTERRUPT_PRIORITY, so first
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check if the interrupt was a system call (32). */
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add s6, zero, k0
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and s6, s6, 32
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beq s6, zero, .+20 /* Not a system call, mask up to the current interrupt priority. */
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nop
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addiu k0, zero, configKERNEL_INTERRUPT_PRIORITY /* Was a system call, mask only to kernel priority. */
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beq zero, zero, .+12
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nop
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/* Enable interrupts above the current priority. */
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srl k0, k0, 0xa
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ins k1, k0, 10, 6
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ins k1, zero, 1, 4
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@ -97,7 +84,7 @@
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/* If the nesting count is 0 then swap to the the system stack, otherwise
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the system stack is already being used. */
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bne s6, zero, .+16
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bne s6, zero, .+20
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nop
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/* Swap to the system stack. */
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@ -108,14 +95,15 @@
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addiu s6, s6, 1
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sw s6, 0(k0)
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/* s6 holds the EPC value, we may want this during the context switch. */
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/* s6 holds the EPC value, this is saved after interrupts are re-enabled. */
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mfc0 s6, _CP0_EPC
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/* Re-enable interrupts. */
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mtc0 k1, _CP0_STATUS
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/* Save the context into the space just created. s6 is saved again
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here as it now contains the EPC value. */
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here as it now contains the EPC value. No other s registers need be
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saved. */
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sw ra, 120(s5)
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sw s8, 116(s5)
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sw t9, 112(s5)
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@ -134,38 +122,30 @@
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sw a0, 60(s5)
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sw v1, 56(s5)
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sw v0, 52(s5)
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sw s7, 48(s5)
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sw s6, portEPC_STACK_LOCATION(s5)
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/* s5 and s6 has already been saved. */
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sw s4, 36(s5)
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sw s3, 32(s5)
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sw s2, 28(s5)
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sw s1, 24(s5)
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sw s0, 20(s5)
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sw $1, 16(s5)
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/* s7 is used as a scratch register. */
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mfhi s7
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sw s7, 12(s5)
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mflo s7
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sw s7, 8(s5)
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/* s6 is used as a scratch register. */
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mfhi s6
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sw s6, 12(s5)
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mflo s6
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sw s6, 8(s5)
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/* Each task maintains its own nesting count. */
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la s7, uxCriticalNesting
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lw s7, (s7)
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sw s7, 4(s5)
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la s6, uxCriticalNesting
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lw s6, (s6)
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sw s6, 4(s5)
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/* Update the TCB stack pointer value if the nesting count is 1. */
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la s7, uxInterruptNesting
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lw s7, (s7)
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addiu s7, s7, -1
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bne s7, zero, .+24 /* Dont save the stack pointer to the task or swap stacks. */
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/* Update the task stack pointer value if nesting is zero. */
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la s6, uxInterruptNesting
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lw s6, (s6)
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addiu s6, s6, -1
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bne s6, zero, .+20
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nop
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/* Save the stack pointer to the task. */
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la s7, pxCurrentTCB
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lw s7, (s7)
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sw s5, (s7)
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/* Save the stack pointer. */
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la s6, uxSavedTaskStackPointer
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sw s5, (s6)
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.endm
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@ -174,35 +154,23 @@
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/* Restore the stack pointer from the TCB. This is only done if the
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nesting count is 1. */
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la s7, uxInterruptNesting
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lw s7, (s7)
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addiu s7, s7, -1
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bne s7, zero, .+24 /* Dont load the stack pointer. */
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la s6, uxInterruptNesting
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lw s6, (s6)
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addiu s6, s6, -1
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bne s6, zero, .+20
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nop
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la s0, pxCurrentTCB
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lw s0, (s0)
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lw s5, (s0)
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la s6, uxSavedTaskStackPointer
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lw s5, (s6)
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/* Restore the context, the first item of which is the critical nesting
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depth. */
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la s0, uxCriticalNesting
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lw s1, 4(s5)
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sw s1, (s0)
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/* Restore the rest of the context. */
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lw s0, 8(s5)
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mtlo s0
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lw s0, 12(s5)
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mthi s0
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/* Restore the context. */
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lw s6, 8(s5)
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mtlo s6
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lw s6, 12(s5)
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mthi s6
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lw $1, 16(s5)
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lw s0, 20(s5)
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lw s1, 24(s5)
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lw s2, 28(s5)
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lw s3, 32(s5)
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lw s4, 36(s5)
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/* s5 is loaded later. */
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/* s6 is loaded as it was used as a scratch register and therefore saved
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as part of the interrupt context. */
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lw s6, 44(s5)
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lw s7, 48(s5)
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lw v0, 52(s5)
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lw v1, 56(s5)
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lw a0, 60(s5)
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@ -231,8 +199,15 @@
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addiu k1, k1, -1
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sw k1, 0(k0)
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lw k1, portSTATUS_STACK_LOCATION(s5)
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lw k0, portEPC_STACK_LOCATION(s5)
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/* Restore the critical nesting count. */
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la k0, uxCriticalNesting
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lw k1, 4(s5)
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sw k1, (k0)
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/* If the critical nesting is not zero then set status as if within
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a critical section. */
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lw k0, portSTATUS_STACK_LOCATION(s5)
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lw k1, portEPC_STACK_LOCATION(s5)
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/* Leave the stack how we found it. First load sp from s5, then restore
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s5 from the stack. */
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@ -240,9 +215,9 @@
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lw s5, 40(sp)
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addiu sp, sp, portCONTEXT_SIZE
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mtc0 k1, _CP0_STATUS
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mtc0 k0, _CP0_STATUS
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ehb
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mtc0 k0, _CP0_EPC
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mtc0 k1, _CP0_EPC
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eret
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nop
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@ -51,9 +51,6 @@
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* Implementation of functions defined in portable.h for the PIC32MX port.
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*----------------------------------------------------------*/
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/* Library includes. */
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#include <string.h>
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/* Scheduler include files. */
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#include "FreeRTOS.h"
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#include "task.h"
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@ -64,12 +61,13 @@
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/* Bits within various registers. */
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#define portIE_BIT ( 0x00000001 )
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#define portEXL_BIT ( 0x00000002 )
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#define portSW0_ENABLE ( 0x00000100 )
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#define portIPL_SHIFT ( 10 )
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#define portALL_IPL_BITS ( 0x1f << portIPL_SHIFT )
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#define portALL_IPL_BITS ( 0x3f << portIPL_SHIFT )
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/* The EXL bit is set to ensure interrupts do not occur while the context of
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the first task is being restored. */
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#define portINITIAL_SR ( portIE_BIT | portEXL_BIT )
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#define portINITIAL_SR ( portIE_BIT | portEXL_BIT | portSW0_ENABLE )
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/* Records the nesting depth of calls to portENTER_CRITICAL(). */
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unsigned portBASE_TYPE uxCriticalNesting = 0x55555555;
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@ -78,6 +76,13 @@ unsigned portBASE_TYPE uxCriticalNesting = 0x55555555;
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decremented to 0 when the first task starts. */
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volatile unsigned portBASE_TYPE uxInterruptNesting = 0x01;
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/* Used to store the original interrupt mask when the mask level is temporarily
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raised during an ISR. */
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volatile unsigned portBASE_TYPE uxSavedStatusRegister = 0;
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/* Stores the task stack pointer when a switch is made to use the system stack. */
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unsigned portBASE_TYPE uxSavedTaskStackPointer = 0;
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/* The stack used by interrupt service routines that cause a context switch. */
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portSTACK_TYPE xISRStack[ configISR_STACK_SIZE ] = { 0 };
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@ -89,10 +94,9 @@ const portBASE_TYPE * const xISRStackTop = &( xISRStack[ configISR_STACK_SIZE -
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extern void __attribute__( (interrupt(ipl1), vector(_TIMER_1_VECTOR))) vT1InterruptHandler( void );
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/*
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* General exception handler that will be called for all general exceptions
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* other than SYS. This should be overridden by a user provided handler.
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* The software interrupt handler that performs the yield.
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*/
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void vApplicationGeneralExceptionHandler( unsigned portLONG ulCause, unsigned portLONG ulStatus ) __attribute__((weak));
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void __attribute__( (interrupt(ipl1), vector(_CORE_SOFTWARE_0_VECTOR))) vPortYieldISR( void );
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/*-----------------------------------------------------------*/
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@ -156,7 +160,7 @@ unsigned portLONG ulStatus;
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/* Mask interrupts at and below the kernel interrupt priority. */
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ulStatus = _CP0_GET_STATUS();
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ulStatus |= ( configKERNEL_INTERRUPT_PRIORITY << portIPL_SHIFT );
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ulStatus |= ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT );
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_CP0_SET_STATUS( ulStatus );
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/* Once interrupts are disabled we can access the nesting count directly. */
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@ -186,14 +190,18 @@ unsigned portLONG ulStatus;
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portBASE_TYPE xPortStartScheduler( void )
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{
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extern void vPortStartFirstTask( void );
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extern void *pxCurrentTCB;
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memset( xISRStack, 0x5a, configISR_STACK_SIZE * sizeof( portSTACK_TYPE ) );
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/* Setup the software interrupt. */
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mConfigIntCoreSW0( CSW_INT_ON | CSW_INT_PRIOR_1 | CSW_INT_SUB_PRIOR_0 );
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/* Setup the timer to generate the tick. Interrupts will have been
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disabled by the time we get here. */
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prvSetupTimerInterrupt();
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/* Kick off the highest priority task that has been created so far. */
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/* Kick off the highest priority task that has been created so far.
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Its stack location is loaded into uxSavedTaskStackPointer. */
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uxSavedTaskStackPointer = *( unsigned portBASE_TYPE * ) pxCurrentTCB;
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vPortStartFirstTask();
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/* Should never get here as the tasks will now be executing. */
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@ -201,12 +209,49 @@ extern void vPortStartFirstTask( void );
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}
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/*-----------------------------------------------------------*/
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void vApplicationGeneralExceptionHandler( unsigned portLONG ulCause, unsigned portLONG ulStatus )
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void vPortYield( void )
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{
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/* This function is declared weak and should be overridden by the users
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application. */
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while( 1 );
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unsigned portLONG ulStatus;
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SetCoreSW0();
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/* Unmask all interrupts. */
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ulStatus = _CP0_GET_STATUS();
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ulStatus &= ~portALL_IPL_BITS;
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_CP0_SET_STATUS( ulStatus );
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}
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/*-----------------------------------------------------------*/
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void vPortIncrementTick( void )
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{
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vPortSetInterruptMaskFromISR();
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vTaskIncrementTick();
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vPortClearInterruptMaskFromISR();
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/* If we are using the preemptive scheduler then we might want to select
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a different task to execute. */
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#if configUSE_PREEMPTION == 1
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SetCoreSW0();
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#endif /* configUSE_PREEMPTION */
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/* Clear timer 0 interrupt. */
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mT1ClearIntFlag();
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}
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/*-----------------------------------------------------------*/
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void vPortSetInterruptMaskFromISR( void )
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{
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asm volatile ( "di" );
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uxSavedStatusRegister = _CP0_GET_STATUS() | 0x01;
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_CP0_SET_STATUS( ( uxSavedStatusRegister | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) ) );
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}
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/*-----------------------------------------------------------*/
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void vPortClearInterruptMaskFromISR( void )
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{
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_CP0_SET_STATUS( uxSavedStatusRegister );
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}
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/*-----------------------------------------------------------*/
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@ -59,12 +59,11 @@
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.extern pxCurrentTCB
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.extern uxCriticalNesting
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.extern vTaskSwitchContext
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.extern vTaskIncrementTick
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.extern vApplicationGeneralExceptionHandler
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.extern vPortIncrementTick
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.extern xISRStackTop
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.global vPortStartFirstTask
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.global _general_exception_context
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.global vPortYieldISR
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.global vT1InterruptHandler
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@ -79,21 +78,9 @@ vT1InterruptHandler:
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portSAVE_CONTEXT
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jal vTaskIncrementTick
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jal vPortIncrementTick
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nop
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/* If we are using the preemptive scheduler then we might want to select
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a different task to execute. */
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#if configUSE_PREEMPTION == 1
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jal vTaskSwitchContext
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nop
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#endif /* configUSE_PREEMPTION */
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/* Clear timer 0 interrupt. */
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la s1, IFS0CLR
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addiu s0,zero,_IFS0_T1IF_MASK
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sw s0, 0(s1)
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portRESTORE_CONTEXT
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.end vT1InterruptHandler
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@ -113,58 +100,214 @@ vPortStartFirstTask:
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.end xPortStartScheduler
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/*******************************************************************/
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.section .FreeRTOS, "ax", @progbits
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.set noreorder
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.set noat
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.ent _general_exception_context
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.ent vPortYieldISR
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_general_exception_context:
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vPortYieldISR:
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/* Save the context of the current task. */
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portSAVE_CONTEXT
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/* Make room for the context. First save the current status so we can
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manipulate it, and the cause and EPC registers so we capture their
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original values in case of interrupt nesting. */
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mfc0 k0, _CP0_CAUSE
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addiu sp, sp, -portCONTEXT_SIZE
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mfc0 k1, _CP0_STATUS
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/* Was this handler caused by a syscall? The original Cause
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value was saved to the stack as it could change as interrupts
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nest. Use of k registers must be protected from use by nesting
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interrupts. */
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lw s7, portCAUSE_STACK_LOCATION(s5)
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andi s7, s7, portEXC_CODE_MASK
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addi s7, s7, -( _EXCCODE_SYS << 2 )
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/* Also save s6 and s5 so we can use them during this interrupt. Any
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nesting interrupts should maintain the values of these registers
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accross the ISR. */
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sw s6, 44(sp)
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sw s5, 40(sp)
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sw k1, portSTATUS_STACK_LOCATION(sp)
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/* Yes - call the SYSCALL handler to select a new task to execute. */
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beq s7, zero, SyscallHandler
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nop
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/* Enable interrupts above the current priority. */
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srl k0, k0, 0xa
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ins k1, k0, 10, 6
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ins k1, zero, 1, 4
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/* No - call the application handler to handle all other types of
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exception. Pass the status and cause to the application provided
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handler. Interrupts are disabled during the execution of the user
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defined handler. */
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di
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lw a1, portSTATUS_STACK_LOCATION(s5)
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lw a0, portCAUSE_STACK_LOCATION(s5)
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jal vApplicationGeneralExceptionHandler
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nop
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ei
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beq zero, zero, FinishExceptionHandler
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nop
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/* s5 is used as the frame pointer. */
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add s5, zero, sp
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SyscallHandler:
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/* Swap to the system stack. This is not conditional on the nesting
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count as this interrupt is always the lowest priority and therefore
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the nesting is always 0. */
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la sp, xISRStackTop
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lw sp, (sp)
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/* Adjust the return that was placed onto the stack to be the
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address of the instruction following the syscall. s6 already
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contains the EPC value. */
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addi s6, 4
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/* Increment and save the nesting count in case this gets preempted. */
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la k0, uxInterruptNesting
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lw s6, (k0)
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addiu s6, s6, 1
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sw s6, 0(k0)
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|
||||
/* s6 holds the EPC value, this is saved with the rest of the context
|
||||
after interrupts are enabled. */
|
||||
mfc0 s6, _CP0_EPC
|
||||
|
||||
/* Re-enable interrupts. */
|
||||
mtc0 k1, _CP0_STATUS
|
||||
|
||||
/* Save the context into the space just created. s6 is saved again
|
||||
here as it now contains the EPC value. */
|
||||
sw ra, 120(s5)
|
||||
sw s8, 116(s5)
|
||||
sw t9, 112(s5)
|
||||
sw t8, 108(s5)
|
||||
sw t7, 104(s5)
|
||||
sw t6, 100(s5)
|
||||
sw t5, 96(s5)
|
||||
sw t4, 92(s5)
|
||||
sw t3, 88(s5)
|
||||
sw t2, 84(s5)
|
||||
sw t1, 80(s5)
|
||||
sw t0, 76(s5)
|
||||
sw a3, 72(s5)
|
||||
sw a2, 68(s5)
|
||||
sw a1, 64(s5)
|
||||
sw a0, 60(s5)
|
||||
sw v1, 56(s5)
|
||||
sw v0, 52(s5)
|
||||
sw s7, 48(s5)
|
||||
sw s6, portEPC_STACK_LOCATION(s5)
|
||||
/* s5 and s6 has already been saved. */
|
||||
sw s4, 36(s5)
|
||||
sw s3, 32(s5)
|
||||
sw s2, 28(s5)
|
||||
sw s1, 24(s5)
|
||||
sw s0, 20(s5)
|
||||
sw $1, 16(s5)
|
||||
|
||||
/* s7 is used as a scratch register as this should always be saved across
|
||||
nesting interrupts. */
|
||||
mfhi s7
|
||||
sw s7, 12(s5)
|
||||
mflo s7
|
||||
sw s7, 8(s5)
|
||||
|
||||
/* Each task maintains its own nesting count. */
|
||||
la s7, uxCriticalNesting
|
||||
lw s7, (s7)
|
||||
sw s7, 4(s5)
|
||||
|
||||
/* Save the stack pointer to the task. */
|
||||
la s7, pxCurrentTCB
|
||||
lw s7, (s7)
|
||||
sw s5, (s7)
|
||||
|
||||
/* Set the interrupt mask to the max priority that can use the API. */
|
||||
di
|
||||
mfc0 s7, _CP0_STATUS
|
||||
ori s7, s7, 1
|
||||
ori s6, s7, configMAX_SYSCALL_INTERRUPT_PRIORITY << 10
|
||||
|
||||
/* This mtc0 re-enables interrupts, but only above
|
||||
configMAX_SYSCALL_INTERRUPT_PRIORITY. */
|
||||
mtc0 s6, _CP0_STATUS
|
||||
|
||||
/* Clear the software interrupt in the core. */
|
||||
mfc0 s6, _CP0_CAUSE
|
||||
addiu s4,zero,-257
|
||||
and s6, s6, s4
|
||||
mtc0 s6, _CP0_CAUSE
|
||||
|
||||
/* Clear the interrupt in the interrupt controller. */
|
||||
la s6, IFS0CLR
|
||||
addiu s4, zero, 2
|
||||
sw s4, (s6)
|
||||
|
||||
jal vTaskSwitchContext
|
||||
nop
|
||||
|
||||
FinishExceptionHandler:
|
||||
portRESTORE_CONTEXT
|
||||
/* Clear the interrupt mask again. The saved status value is still in s7. */
|
||||
mtc0 s7, _CP0_STATUS
|
||||
|
||||
.end _general_exception_context
|
||||
/* Restore the stack pointer from the TCB. */
|
||||
la s0, pxCurrentTCB
|
||||
lw s0, (s0)
|
||||
lw s5, (s0)
|
||||
|
||||
/* Restore the rest of the context. */
|
||||
lw s0, 8(s5)
|
||||
mtlo s0
|
||||
lw s0, 12(s5)
|
||||
mthi s0
|
||||
lw $1, 16(s5)
|
||||
lw s0, 20(s5)
|
||||
lw s1, 24(s5)
|
||||
lw s2, 28(s5)
|
||||
lw s3, 32(s5)
|
||||
lw s4, 36(s5)
|
||||
/* s5 is loaded later. */
|
||||
lw s6, 44(s5)
|
||||
lw s7, 48(s5)
|
||||
lw v0, 52(s5)
|
||||
lw v1, 56(s5)
|
||||
lw a0, 60(s5)
|
||||
lw a1, 64(s5)
|
||||
lw a2, 68(s5)
|
||||
lw a3, 72(s5)
|
||||
lw t0, 76(s5)
|
||||
lw t1, 80(s5)
|
||||
lw t2, 84(s5)
|
||||
lw t3, 88(s5)
|
||||
lw t4, 92(s5)
|
||||
lw t5, 96(s5)
|
||||
lw t6, 100(s5)
|
||||
lw t7, 104(s5)
|
||||
lw t8, 108(s5)
|
||||
lw t9, 112(s5)
|
||||
lw s8, 116(s5)
|
||||
lw ra, 120(s5)
|
||||
|
||||
/* Protect access to the k registers, and others. */
|
||||
di
|
||||
|
||||
/* Decrement the nesting count. */
|
||||
la k0, uxInterruptNesting
|
||||
lw k1, (k0)
|
||||
addiu k1, k1, -1
|
||||
sw k1, 0(k0)
|
||||
|
||||
/* Switch back to use the real stack pointer. */
|
||||
add sp, zero, s5
|
||||
|
||||
/* Restore the critical nesting depth. */
|
||||
la s5, uxCriticalNesting
|
||||
lw k0, 4(sp)
|
||||
sw k0, (s5)
|
||||
|
||||
/* If the critical nesting is not zero and a yield is not pended
|
||||
then set status as if within a critical section. */
|
||||
lw s5, portSTATUS_STACK_LOCATION(sp)
|
||||
beq k0, zero, .+28
|
||||
nop
|
||||
mfc0 k1, _CP0_CAUSE
|
||||
andi k1, k1, 256
|
||||
bne k1, zero, .+12
|
||||
nop
|
||||
or s5, s5, (configMAX_SYSCALL_INTERRUPT_PRIORITY<<10)
|
||||
|
||||
lw k0, portEPC_STACK_LOCATION(sp)
|
||||
|
||||
mtc0 s5, _CP0_STATUS
|
||||
ehb
|
||||
|
||||
/* Restore the real s5 value. */
|
||||
lw s5, 40(sp)
|
||||
|
||||
/* Remove stack frame. */
|
||||
addiu sp, sp, portCONTEXT_SIZE
|
||||
|
||||
mtc0 k0, _CP0_EPC
|
||||
eret
|
||||
nop
|
||||
|
||||
.end vPortYieldISR
|
||||
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -99,11 +99,17 @@ extern void vPortEnterCritical( void );
|
|||
extern void vPortExitCritical( void );
|
||||
#define portENTER_CRITICAL() vPortEnterCritical()
|
||||
#define portEXIT_CRITICAL() vPortExitCritical()
|
||||
|
||||
extern void vPortSetInterruptMaskFromISR();
|
||||
extern void vPortClearInterruptMaskFromISR();
|
||||
#define portSET_INTERRUPT_MASK_FROM_ISR() vPortSetInterruptMaskFromISR()
|
||||
#define portCLEAR_INTERRUPT_MASK_FROM_ISR() vPortClearInterruptMaskFromISR()
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Task utilities. */
|
||||
#define portYIELD() asm volatile ( "ehb \r\n" \
|
||||
"SYSCALL \r\n" )
|
||||
extern void vPortYield( void );
|
||||
#define portYIELD() vPortYield()
|
||||
|
||||
#define portNOP() asm volatile ( "nop" )
|
||||
|
||||
|
|
@ -114,7 +120,7 @@ extern void vPortExitCritical( void );
|
|||
#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
#define portEND_SWITCHING_ISR( vSwitchRequired ) if( vSwitchRequired ) vTaskSwitchContext()
|
||||
#define portEND_SWITCHING_ISR( vSwitchRequired ) if( vSwitchRequired ) SetCoreSW0()
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in a new issue