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Continue work on Risc V port.

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This commit is contained in:
Richard Barry 2018-11-06 02:04:28 +00:00
parent 74d0d16aab
commit baee711cb6
3 changed files with 45 additions and 12 deletions
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7
FreeRTOS/Source/portable/GCC/RISC-V-RV32/portASM.S
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@ -38,7 +38,7 @@
#define CONTEXT_SIZE ( 28 * WORD_SIZE )
.global xPortStartScheduler
.global xPortStartFirstTask
.global vPortTrapHandler
.extern pxCurrentTCB
.extern handle_trap
@ -46,7 +46,8 @@
/*-----------------------------------------------------------*/
.align 8
xPortStartScheduler:
xPortStartFirstTask:
lw sp, pxCurrentTCB /* Load pxCurrentTCB. */
lw sp, 0( sp ) /* Read sp from first TCB member. */
@ -81,7 +82,7 @@ xPortStartScheduler:
addi sp, sp, CONTEXT_SIZE
csrs mstatus, 8 /* Enable machine interrupts. */
csrs mie, 8 /* Enable soft interrupt. */
ret
ret
/*-----------------------------------------------------------*/