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Add additional memory barriers into ARM GCC asm code to ensure no re-ordering across asm code as optimisers get more aggressive.

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This commit is contained in:
Richard Barry 2017-03-07 04:06:10 +00:00
parent c3acc441ac
commit b9fe24962e
16 changed files with 100 additions and 98 deletions
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24
FreeRTOS/Source/portable/GCC/ARM_CM0/port.c
View file

@ -79,15 +79,15 @@
#define portNVIC_SYSTICK_CTRL ( ( volatile uint32_t * ) 0xe000e010 )
#define portNVIC_SYSTICK_LOAD ( ( volatile uint32_t * ) 0xe000e014 )
#define portNVIC_SYSTICK_CURRENT_VALUE ( ( volatile uint32_t * ) 0xe000e018 )
#define portNVIC_INT_CTRL ( ( volatile uint32_t *) 0xe000ed04 )
#define portNVIC_SYSPRI2 ( ( volatile uint32_t *) 0xe000ed20 )
#define portNVIC_SYSTICK_CLK 0x00000004
#define portNVIC_SYSTICK_INT 0x00000002
#define portNVIC_SYSTICK_ENABLE 0x00000001
#define portNVIC_PENDSVSET 0x10000000
#define portMIN_INTERRUPT_PRIORITY ( 255UL )
#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL )
#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL )
#define portNVIC_INT_CTRL ( ( volatile uint32_t *) 0xe000ed04 )
#define portNVIC_SYSPRI2 ( ( volatile uint32_t *) 0xe000ed20 )
#define portNVIC_SYSTICK_CLK 0x00000004
#define portNVIC_SYSTICK_INT 0x00000002
#define portNVIC_SYSTICK_ENABLE 0x00000001
#define portNVIC_PENDSVSET 0x10000000
#define portMIN_INTERRUPT_PRIORITY ( 255UL )
#define portNVIC_PENDSV_PRI ( portMIN_INTERRUPT_PRIORITY << 16UL )
#define portNVIC_SYSTICK_PRI ( portMIN_INTERRUPT_PRIORITY << 24UL )
/* Constants required to set up the initial stack. */
#define portINITIAL_XPSR ( 0x01000000 )
@ -243,7 +243,7 @@ void vPortYield( void )
/* Barriers are normally not required but do ensure the code is completely
within the specified behaviour for the architecture. */
__asm volatile( "dsb" );
__asm volatile( "dsb" ::: "memory" );
__asm volatile( "isb" );
}
/*-----------------------------------------------------------*/
@ -252,7 +252,7 @@ void vPortEnterCritical( void )
{
portDISABLE_INTERRUPTS();
uxCriticalNesting++;
__asm volatile( "dsb" );
__asm volatile( "dsb" ::: "memory" );
__asm volatile( "isb" );
}
/*-----------------------------------------------------------*/
@ -274,6 +274,7 @@ uint32_t ulSetInterruptMaskFromISR( void )
" mrs r0, PRIMASK \n"
" cpsid i \n"
" bx lr "
::: "memory"
);
/* To avoid compiler warnings. This line will never be reached. */
@ -286,6 +287,7 @@ void vClearInterruptMaskFromISR( uint32_t ulMask )
__asm volatile(
" msr PRIMASK, r0 \n"
" bx lr "
::: "memory"
);
/* Just to avoid compiler warning. */

4
FreeRTOS/Source/portable/GCC/ARM_CM0/portmacro.h
View file

@ -136,8 +136,8 @@ extern void vClearInterruptMaskFromISR( uint32_t ulMask ) __attribute__((naked)
#define portSET_INTERRUPT_MASK_FROM_ISR() ulSetInterruptMaskFromISR()
#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vClearInterruptMaskFromISR( x )
#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " )
#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " )
#define portDISABLE_INTERRUPTS() __asm volatile ( " cpsid i " ::: "memory" )
#define portENABLE_INTERRUPTS() __asm volatile ( " cpsie i " ::: "memory" )
#define portENTER_CRITICAL() vPortEnterCritical()
#define portEXIT_CRITICAL() vPortExitCritical()