diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo.stp b/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo.stp
new file mode 100644
index 000000000..6c51853d4
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo.stp
@@ -0,0 +1,47881 @@
+NOTE "CREATOR" "FlashPro Version: v11.0";
+NOTE "CAPTURE" "11.0.0.23";
+NOTE "DEVICE" "M2S050T_ES";
+NOTE "PACKAGE" "M2S050T_ES-fg896";
+NOTE "DATE" "2013/05/05";
+NOTE "TIME" "13:53:08";
+NOTE "STAPL_VERSION" "JESD71";
+NOTE "VENDOR" "Microsemi Corporation";
+NOTE "IDCODE" "0F8021CF";
+NOTE "IDMASK" "0FFFFFFF";
+NOTE "DESIGN" "RTOSDemo";
+NOTE "DESIGN_DIRECTORY" "";
+NOTE "CHECKSUM" "4918";
+NOTE "SECURITY" "Disable";
+NOTE "ALG_VERSION" "1";
+NOTE "MAP_VERSION" "0";
+NOTE "TOOL_VERSION" "1";
+NOTE "MAX_FREQ" "10000000";
+NOTE "SILSIG" "00000000";
+NOTE "SPEED_GRAD" "STD";
+NOTE "TEMP_GRAD" "COM";
+NOTE "PLAYER_VERSION_VARIABLE" "PLAYERVERSIONVARIABLE";
+NOTE "PLAYER_VERSION_SW_VARIABLE" "PLAYERVERSIONSWVARIABLE";
+
+ACTION PROGRAM = 
+       VERIFY_IDCODE,
+       PROC_ENABLE,
+       DO_PROGRAM,
+       DO_VERIFY OPTIONAL,
+       DO_EXIT;
+ACTION VERIFY = 
+       VERIFY_IDCODE,
+       PROC_ENABLE,
+       DO_VERIFY,
+       DO_EXIT;
+ACTION ENC_DATA_AUTHENTICATION = 
+       VERIFY_IDCODE,
+       DO_AUTHENTICATION,
+       DO_EXIT;
+ACTION READ_IDCODE = 
+       VERIFY_IDCODE,
+       PRINT_IDCODE,
+       DO_EXIT;
+ACTION DEVICE_INFO = 
+       VERIFY_IDCODE,
+       DO_DEVICE_INFO,
+       DO_EXIT;
+
+
+
+DATA PARAMETERS;
+    INTEGER FREQ =4;
+ENDDATA;
+
+DATA GV;
+    BOOLEAN ID[32];
+    BOOLEAN PASS = 1;
+    BOOLEAN BUFF32[32];
+    INTEGER STATUS =0;
+    INTEGER DATAINDEX =0;
+    INTEGER ICURNUMOFCOMPONENTS =0;
+    INTEGER ICURCOMPONENTNO =0;
+    INTEGER IPOLL =0;
+    INTEGER BPGMMODE =0;
+    INTEGER I =0;
+    INTEGER INUMOFBLOCKS =0;
+    BOOLEAN SHARED_BUFFER[4736];
+    BOOLEAN ACT_UROW_ALGO_VERSION[6] = $01;
+    BOOLEAN ACT_UROW_PGM_TYPE[4];
+    BOOLEAN ACT_UROW_SW_VERSION[7];
+    BOOLEAN ACT_UROW_PROGRAM_SW[4];
+    INTEGER HEX[16] = 70,69,68,67,66,65,57,56,55,54,53,52,51,50,49,48;
+    BOOLEAN PGMMODE[8];
+    BOOLEAN DATA_STATUS_RESULT[32];
+    BOOLEAN READ_PROG_INFO_RESULT[128];
+    BOOLEAN KEYHI_REG[128];
+    BOOLEAN KEYLO_REG[128];
+    BOOLEAN IDCODEVALUE[32] = $0f8021cf;
+    BOOLEAN IDMASK[32] = $0fffffff;
+    INTEGER IDREV;
+    INTEGER IDFAB;
+    BOOLEAN BSRPATTERN[1146] = $249249249249249249249249249249249249249249249249
+        249249249249249249249249249249249249249249249249249249249249249249249249
+        249249249249249249249249249249249249249249249249249249249249249249249249
+        249249249249249249249249249249249249249249249249249249249249249249249249
+        24924924924924924924924;
+    BOOLEAN SAMPLEMASK[1146] = $000000000000000000000000000000000000000000000000
+        000000000000000000000000000000000000000000000000000000000000000000000000
+        000000000000000000000000000000000000000000000000000000000000000000000000
+        000000000000000000000000000000000000000000000000000000000000000000000000
+        00000000000000000000000;
+    BOOLEAN BSR[1146];
+    BOOLEAN SAMPLE_DEVICE[1146];
+    BOOLEAN SEC_UL[96];
+    BOOLEAN SEC_UKL[12];
+    BOOLEAN SEC_VL[12];
+    BOOLEAN SEC_OPOK[4];
+    BOOLEAN SEC_CCNFG[8];
+    BOOLEAN SEC_USERCODE[32];
+    BOOLEAN SEC_UCNFG[46];
+    BOOLEAN SEC_CL[12];
+    BOOLEAN SEC_DL[12];
+    BOOLEAN SECURITY_QUERIED = 0;
+    INTEGER DATASTARTINDEX =0;
+    INTEGER DATAENVMSTARTINDEX =0;
+    INTEGER DATAENVMSIZE =0;
+    INTEGER DATASIZE =4;
+    INTEGER NUMOFCOMPONENTS =4;
+    BOOLEAN NUMOFBLOCKS[88] = $0000640005b0937e400020;
+    BOOLEAN TOOL_INFO[32] = $00000000;
+    INTEGER LABEL_SEPARATOR;
+ENDDATA;
+
+DATA CONSTBLOCK;
+    INTEGER SELF=1;
+    INTEGER SCULPTW=3;
+    INTEGER BPWIN=4;
+    INTEGER ACTEL_IHP=5;
+    INTEGER FP3=2;
+    INTEGER FP4=7;
+    INTEGER FP_FTDI=8;
+    INTEGER SIL_EXPL=9;
+    INTEGER ATE=14;
+    INTEGER FP34=1;
+    INTEGER FP40=2;
+    INTEGER FP41=3;
+    INTEGER FP42=4;
+    INTEGER FP50=5;
+    INTEGER FP51=6;
+    INTEGER FP60=7;
+    INTEGER FP61=8;
+    INTEGER FP62=9;
+    INTEGER FP84=11;
+    INTEGER FP85=12;
+    INTEGER FP86=13;
+    INTEGER FP90=14;
+    INTEGER FP91=15;
+    INTEGER FP_10_LCP=16;
+    INTEGER FP_11_BETA_SPA=17;
+    INTEGER FP_11_BETA_SP1=18;
+    INTEGER FP_11=19;
+    INTEGER FP=1;
+    INTEGER DIRECTC=2;
+    INTEGER NON_ACTEL=6;
+    INTEGER SPI_MASTER=1;
+    INTEGER SPI_SLAVE=2;
+    INTEGER JTAG=3;
+    INTEGER I2C_MASTER=4;
+    INTEGER I2C_SLAVE=5;
+    INTEGER PDB=1;
+    INTEGER STAPL=2;
+    INTEGER SVF=3;
+    INTEGER PCF=4;
+    INTEGER IEEE1532=5;
+ENDDATA;
+
+DATA BITSTREAM;
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+        b0E8A4PMAI7@RtY34OzYy20bSxYyf9fVyo4gmJweJFxCjPeHnhupME1jAHNFTKfROQ5pOaMu
+        e6CTWYfplKEQDGOXggHfmCehkGDyl0fSM3EVhMyhcKUSQGKhZzxIWZW_SYl26@5eQjm_LrMi
+        MrSh@zq39AOfvdj0xq7rOlu91HIeXRVPsCOyeTS01ayDDyWIdHXPB9PymIlUqc6wJ8fih78B
+        2zmtNUm6SHnG1M9bmF5q4@DmHHUyydEgPzWnXNTjD112vpsLqgH0WGDTnHFldh9Jhe4fJU53
+        rCG9IfMVWWo1O7Kw4YJLnCOexwawCtWwstwiyTtXe6YE5sMWxZ9qDo3qWmEH9A2GMSdczC6M
+        mfC4K0qt1x2lfurdqkwSEsMnQ@Kh0InWsyerJXfiRn6SC2M1pNozXPqVPOSGVyhGm9mnuUao
+        Qz3PRLtq72zPGpygxYyoY@DjXoxEdc@ZulirCrupJyl4WG06fnyKGm4VoCruIeUc9Ykw3Jcc
+        @idE66SLjPkFeA1abwv5MHZybm0hUYAzcH3mQnLfKC7nBTArRaQ4DUGGh3jsMe2UnjN@xcbD
+        0qENcu4D087TWeEBj8QQrogh10ZG98qNPArzDjUZJNzigsuNLAb2TTkroKQXxLDiT3p0LMyJ
+        RO8J24FZy169Iq7x_ZO0zfwPv3z62NK@Elg9MZsy38BTN563Q0wM5MM9ccAbM6LmWSCbxl4Q
+        tMWf3v27DfZOoz6Wl3my7zyKEtPvrol3UxX0xDh2mCPdQeX7ia9cfOE2dJUbWnL8S6sPQOf4
+        EGG@xJVb1reC69FvgMADhVEuwHuEbC2P9c3WLwkvtV5I3E7EJV_1fnF1sKz2RtGWAGn8o3rf
+        O9t4HC5DONKmb9GTFRJr7AoAhiZq7vnex9tVx0CoN2COC2LHAQcuHP8gfRmWg2K2JekspTN_
+        UnZ000060e3juROomopj5d@XPIaWjr_4_hgDi65yaTB912D6GiuN7kxx8dwdTn04pIPCVKOp
+        vuERpLpnLbzxC4J5k08sMsm2@tXDj3qgBRgUQr5kWm9MJryepc2G0048T0G60u@10QmXhE6D
+        P5Q8sMaksObijKzhY8SH7EBi_601Phalu9UEbFq0C0m3e@pyuwRNxUintGtmWHP@SifU@WnZ
+        l4xXoohzz7QCq2MvD4YnBcCJf0mqsjgwJMY9RR75wy2yfT5ep3E1o1J9571rwyFFUzuGQlVB
+        U2cjq8Cj3q7oWaxH4FfMEfYNzcFBKy4OD2f4F4t_OgIu1CAvipOUFJm7om0_BGLDNw08VgMC
+        8aY0mxoSHJ82ba213ylA5OY8r01V@Dy@00@F0m@30CdBY@0l93bmgufmW58mvg3NLc_lvVoE
+        CthJMU4nrrspuMF1t@ss4u1A9K0SKIXVViU9jP_Gp4otA4y8JHBBHW0S4QeoFo1@k7mSQVll
+        Qj8iKw1aAd@2Rv@1003;
+ENDDATA;
+
+
+PROCEDURE READ_FSN USES GV;
+    BOOLEAN READ_FSN_RESULT[129];
+    PASS = 0;
+    READ_FSN_RESULT[128..0] = $000000000000000000000000000000000;
+    IRSTOP IRPAUSE;
+    DRSTOP DRPAUSE;
+    IRSCAN 8, $f0;
+    DRSCAN 129, READ_FSN_RESULT[];
+    WAIT IDLE, 3 CYCLES;
+    WAIT 10 USEC, DRPAUSE;
+    FOR IPOLL = 100000 TO 0 STEP -1;
+        DRSCAN 129, $000000000000000000000000000000000, CAPTURE READ_FSN_RESULT[];
+        IF ( ! (READ_FSN_RESULT[128]==0) ) THEN GOTO READ_FSN_POLL;
+        IPOLL = 0;
+        PASS = 1;
+        READ_FSN_POLL:
+        IF ( ! (PASS==0) ) THEN GOTO READ_FSN_DONE;
+        IRSCAN 8, $f0;
+        WAIT IRPAUSE, 10 USEC;
+        READ_FSN_DONE:
+        LABEL_SEPARATOR = 0;
+    NEXT IPOLL;
+    IF ( ! (PASS==0) ) THEN GOTO READ_FSN_COMPLETE;
+    PRINT "Failed to read FSN.";
+    STATUS = -24;
+    READ_FSN_COMPLETE:
+    PRINT "===================================================================================";
+    EXPORT "DSN", READ_FSN_RESULT[127..0];
+    PRINT "===================================================================================";
+ENDPROC;
+
+PROCEDURE DO_EXIT USES GV;
+    PRINT "Please power cycle your board.";
+    EXIT STATUS;
+ENDPROC;
+
+PROCEDURE LOAD_KEYLO USES GV,DO_EXIT;
+    BOOLEAN KEYLO_RESULT[128];
+    PASS = 0;
+    IRSTOP IRPAUSE;
+    DRSTOP DRPAUSE;
+    IRSCAN 8, $eb;
+    DRSCAN 128, KEYLO_REG[];
+    WAIT IDLE, 3 CYCLES;
+    WAIT 10 USEC, DRPAUSE;
+    FOR IPOLL = 100000 TO 0 STEP -1;
+        DRSCAN 128, $00000000000000000000000000000000, CAPTURE KEYLO_RESULT[127..0];
+        IF ( ! (KEYLO_RESULT[127]==0) ) THEN GOTO KEYLO_POLL;
+        IPOLL = 0;
+        PASS = 1;
+        KEYLO_POLL:
+        IF ( ! (PASS==0) ) THEN GOTO KEYLO_DONE;
+        IRSCAN 8, $eb;
+        WAIT IRPAUSE, 10 USEC;
+        KEYLO_DONE:
+        LABEL_SEPARATOR = 0;
+    NEXT IPOLL;
+    IF ( ! (PASS==0) ) THEN GOTO KEYLO_PASS;
+    PRINT "Failed to load keylo.";
+    EXPORT "keylo_result", KEYLO_RESULT[127..0];
+    STATUS = -35;
+    CALL DO_EXIT;
+    KEYLO_PASS:
+    LABEL_SEPARATOR = 0;
+ENDPROC;
+
+PROCEDURE LOAD_KEYHI USES GV,DO_EXIT;
+    BOOLEAN KEYHI_RESULT[128];
+    PASS = 0;
+    IRSTOP IRPAUSE;
+    DRSTOP DRPAUSE;
+    IRSCAN 8, $ec;
+    DRSCAN 128, KEYHI_REG[];
+    WAIT IDLE, 3 CYCLES;
+    WAIT 10 USEC, DRPAUSE;
+    FOR IPOLL = 100000 TO 0 STEP -1;
+        DRSCAN 128, $00000000000000000000000000000000, CAPTURE KEYHI_RESULT[127..0];
+        IF ( ! (KEYHI_RESULT[127]==0) ) THEN GOTO KEYHI_POLL;
+        IPOLL = 0;
+        PASS = 1;
+        KEYHI_POLL:
+        IF ( ! (PASS==0) ) THEN GOTO KEYHI_DONE;
+        IRSCAN 8, $ec;
+        WAIT IRPAUSE, 10 USEC;
+        KEYHI_DONE:
+        LABEL_SEPARATOR = 0;
+    NEXT IPOLL;
+    IF ( ! (PASS==0) ) THEN GOTO KEYHI_PASS;
+    PRINT "Failed to load keyhi.";
+    EXPORT "keyhi_result", KEYHI_RESULT[127..0];
+    STATUS = -35;
+    CALL DO_EXIT;
+    KEYHI_PASS:
+    LABEL_SEPARATOR = 0;
+ENDPROC;
+
+PROCEDURE DUMP_SECURITY_INFO USES GV;
+    PRINT "--- Security locks and configuration settings ---";
+    EXPORT "QUERY_SECURITY", SHARED_BUFFER[335..0];
+    IF ( ! (SECURITY_QUERIED==1) ) THEN GOTO Label_0;
+    IF ( ! (SEC_UL[0]==1) ) THEN GOTO JTAGTESTDIS_SELECT;
+    PRINT "JTAG test instructions are disabled.";
+    JTAGTESTDIS_SELECT:
+    IF ( ! (SEC_UL[1]==1) ) THEN GOTO USL_SELECT;
+    PRINT "User lock segment is protected.";
+    USL_SELECT:
+    IF ( ! (SEC_UL[2]==1) ) THEN GOTO UEWL_SELECT;
+    PRINT "FPGA array erase/write protected.";
+    UEWL_SELECT:
+    IF ( ! (SEC_UL[3]==1) ) THEN GOTO UVL_SELECT;
+    PRINT "Fabric verify is protected.";
+    UVL_SELECT:
+    IF ( ! (SEC_UL[4]==1) ) THEN GOTO UPTL_SELECT;
+    PRINT "User key 1/2 encrypted programming is enforced for the FPGA Array.";
+    UPTL_SELECT:
+    IF ( ! (SEC_UL[8]==1) ) THEN GOTO UL_JTAG_PROG_SELECT;
+    PRINT "JTAG programming interface is protected.";
+    UL_JTAG_PROG_SELECT:
+    IF ( ! (SEC_UL[9]==1) ) THEN GOTO UL_SPI_PROG_SELECT;
+    PRINT "SPI slave programming interface is protected.";
+    UL_SPI_PROG_SELECT:
+    IF ( ! (SEC_UL[11]==1) ) THEN GOTO USPL_SELECT;
+    PRINT "User security is permanently locked.";
+    USPL_SELECT:
+    IF ( ! (SEC_UL[12]==1) ) THEN GOTO UL_E0_R_SELECT;
+    PRINT "Debug read access to eNVM module 0 is protected.";
+    UL_E0_R_SELECT:
+    IF ( ! (SEC_UL[13]==1) ) THEN GOTO UL_E1_R_SELECT;
+    PRINT "Debug read access to eNVM module 1 is protected.";
+    UL_E1_R_SELECT:
+    IF ( ! (SEC_UL[17]==1) ) THEN GOTO UL_E0_PT_SELECT;
+    PRINT "User key 1/2 encrypted programming is enforced for eNVM module 0.";
+    UL_E0_PT_SELECT:
+    IF ( ! (SEC_UL[18]==1) ) THEN GOTO UL_PROG_SVC_ENABLE_SELECT;
+    PRINT "IAP/ISP services are protected.";
+    UL_PROG_SVC_ENABLE_SELECT:
+    IF ( ! (SEC_UL[26]==1) ) THEN GOTO UL_EXTDIGEST_ENABLE_SELECT;
+    PRINT "Digest requests from SPI/JTAG is protected.";
+    UL_EXTDIGEST_ENABLE_SELECT:
+    IF ( ! (SEC_UL[27]==1) ) THEN GOTO UL_REFLASH_ENABLE_SELECT;
+    PRINT "Auto Programming is protected.";
+    UL_REFLASH_ENABLE_SELECT:
+    IF ( ! (SEC_UL[28]==1) ) THEN GOTO UL_BACKLEVEL_DISABLE_SELECT;
+    PRINT "BACKLEVEL checking is enabled.";
+    UL_BACKLEVEL_DISABLE_SELECT:
+    IF ( ! (SEC_UL[31]==1) ) THEN GOTO UL_BUS_IDS_ESRAM0_R_SELECT;
+    PRINT "Arm CortexM3 access to eSRAM module 0 read is protected.";
+    UL_BUS_IDS_ESRAM0_R_SELECT:
+    IF ( ! (SEC_UL[32]==1) ) THEN GOTO UL_BUS_IDS_ESRAM0_W_SELECT;
+    PRINT "Arm CortexM3 access to eSRAM module 0 write is protected.";
+    UL_BUS_IDS_ESRAM0_W_SELECT:
+    IF ( ! (SEC_UL[33]==1) ) THEN GOTO UL_BUS_IDS_ESRAM1_R_SELECT;
+    PRINT "Arm CortexM3 access to eSRAM module 1 read is protected.";
+    UL_BUS_IDS_ESRAM1_R_SELECT:
+    IF ( ! (SEC_UL[34]==1) ) THEN GOTO UL_BUS_IDS_ESRAM1_W_SELECT;
+    PRINT "Arm CortexM3 access to eSRAM module 1 write is protected.";
+    UL_BUS_IDS_ESRAM1_W_SELECT:
+    IF ( ! (SEC_UL[35]==1) ) THEN GOTO UL_BUS_IDS_ENVM0_R_SELECT;
+    PRINT "Arm CortexM3 access to eNVM module 0 read is protected.";
+    UL_BUS_IDS_ENVM0_R_SELECT:
+    IF ( ! (SEC_UL[36]==1) ) THEN GOTO UL_BUS_IDS_ENVM0_W_SELECT;
+    PRINT "Arm CortexM3 access to eNVM module 0 write is protected.";
+    UL_BUS_IDS_ENVM0_W_SELECT:
+    IF ( ! (SEC_UL[37]==1) ) THEN GOTO UL_BUS_IDS_ENVM1_R_SELECT;
+    PRINT "Arm CortexM3 access to eNVM module 1 read is protected.";
+    UL_BUS_IDS_ENVM1_R_SELECT:
+    IF ( ! (SEC_UL[38]==1) ) THEN GOTO UL_BUS_IDS_ENVM1_W_SELECT;
+    PRINT "Arm CortexM3 access to eNVM module 1 write is protected.";
+    UL_BUS_IDS_ENVM1_W_SELECT:
+    IF ( ! (SEC_UL[39]==1) ) THEN GOTO UL_BUS_IDS_DDR_R_SELECT;
+    PRINT "Arm CortexM3 access to DDR bridge read is protected.";
+    UL_BUS_IDS_DDR_R_SELECT:
+    IF ( ! (SEC_UL[40]==1) ) THEN GOTO UL_BUS_IDS_DDR_W_SELECT;
+    PRINT "Arm CortexM3 access to DDR bridge write is protected.";
+    UL_BUS_IDS_DDR_W_SELECT:
+    IF ( ! (SEC_UL[41]==1) ) THEN GOTO UL_BUS_FIC_ESRAM0_R_SELECT;
+    PRINT "Fabric access to eSRAM module 0 read is protected.";
+    UL_BUS_FIC_ESRAM0_R_SELECT:
+    IF ( ! (SEC_UL[42]==1) ) THEN GOTO UL_BUS_FIC_ESRAM0_W_SELECT;
+    PRINT "Fabric access to eSRAM module 0 write is protected.";
+    UL_BUS_FIC_ESRAM0_W_SELECT:
+    IF ( ! (SEC_UL[43]==1) ) THEN GOTO UL_BUS_FIC_ESRAM1_R_SELECT;
+    PRINT "Fabric access to eSRAM module 1 read is protected.";
+    UL_BUS_FIC_ESRAM1_R_SELECT:
+    IF ( ! (SEC_UL[44]==1) ) THEN GOTO UL_BUS_FIC_ESRAM1_W_SELECT;
+    PRINT "Fabric access to eSRAM module 1 write is protected.";
+    UL_BUS_FIC_ESRAM1_W_SELECT:
+    IF ( ! (SEC_UL[45]==1) ) THEN GOTO UL_BUS_FIC_ENVM0_R_SELECT;
+    PRINT "Fabric access to eNVM module 0 read is protected.";
+    UL_BUS_FIC_ENVM0_R_SELECT:
+    IF ( ! (SEC_UL[46]==1) ) THEN GOTO UL_BUS_FIC_ENVM0_W_SELECT;
+    PRINT "Fabric access to eNVM module 0 write is protected.";
+    UL_BUS_FIC_ENVM0_W_SELECT:
+    IF ( ! (SEC_UL[47]==1) ) THEN GOTO UL_BUS_FIC_ENVM1_R_SELECT;
+    PRINT "Fabric access to eNVM module 1 read is protected.";
+    UL_BUS_FIC_ENVM1_R_SELECT:
+    IF ( ! (SEC_UL[48]==1) ) THEN GOTO UL_BUS_FIC_ENVM1_W_SELECT;
+    PRINT "Fabric access to eNVM module 1 write is protected.";
+    UL_BUS_FIC_ENVM1_W_SELECT:
+    IF ( ! (SEC_UL[49]==1) ) THEN GOTO UL_BUS_FIC_DDR_R_SELECT;
+    PRINT "Fabric access to DDR bridge read is protected.";
+    UL_BUS_FIC_DDR_R_SELECT:
+    IF ( ! (SEC_UL[50]==1) ) THEN GOTO UL_BUS_FIC_DDR_W_SELECT;
+    PRINT "Fabric access to DDR bridge write is protected.";
+    UL_BUS_FIC_DDR_W_SELECT:
+    IF ( ! (SEC_UL[51]==1) ) THEN GOTO UL_BUS_EXT_ESRAM0_R_SELECT;
+    PRINT "External master access to eSRAM module 0 read is protected.";
+    UL_BUS_EXT_ESRAM0_R_SELECT:
+    IF ( ! (SEC_UL[52]==1) ) THEN GOTO UL_BUS_EXT_ESRAM0_W_SELECT;
+    PRINT "External master access to eSRAM module 0 write is protected.";
+    UL_BUS_EXT_ESRAM0_W_SELECT:
+    IF ( ! (SEC_UL[53]==1) ) THEN GOTO UL_BUS_EXT_ESRAM1_R_SELECT;
+    PRINT "External master access to eSRAM module 1 read is protected.";
+    UL_BUS_EXT_ESRAM1_R_SELECT:
+    IF ( ! (SEC_UL[54]==1) ) THEN GOTO UL_BUS_EXT_ESRAM1_W_SELECT;
+    PRINT "External master access to eSRAM module 1 write is protected.";
+    UL_BUS_EXT_ESRAM1_W_SELECT:
+    IF ( ! (SEC_UL[55]==1) ) THEN GOTO UL_BUS_EXT_ENVM0_R_SELECT;
+    PRINT "External master access to eNVM module 0 read is protected.";
+    UL_BUS_EXT_ENVM0_R_SELECT:
+    IF ( ! (SEC_UL[56]==1) ) THEN GOTO UL_BUS_EXT_ENVM0_W_SELECT;
+    PRINT "External master access to eNVM module 0 write is protected.";
+    UL_BUS_EXT_ENVM0_W_SELECT:
+    IF ( ! (SEC_UL[57]==1) ) THEN GOTO UL_BUS_EXT_ENVM1_R_SELECT;
+    PRINT "External master access to eNVM module 1 read is protected.";
+    UL_BUS_EXT_ENVM1_R_SELECT:
+    IF ( ! (SEC_UL[58]==1) ) THEN GOTO UL_BUS_EXT_ENVM1_W_SELECT;
+    PRINT "External master access to eNVM module 1 write is protected.";
+    UL_BUS_EXT_ENVM1_W_SELECT:
+    IF ( ! (SEC_UL[59]==1) ) THEN GOTO UL_BUS_EXT_DDR_R_SELECT;
+    PRINT "External master access to DDR bridge read is protected.";
+    UL_BUS_EXT_DDR_R_SELECT:
+    IF ( ! (SEC_UL[60]==1) ) THEN GOTO UL_BUS_EXT_DDR_W_SELECT;
+    PRINT "External master access to DDR bridge write is protected.";
+    UL_BUS_EXT_DDR_W_SELECT:
+    IF ( ! (SEC_UL[65]==1) ) THEN GOTO UL_BUS_SII_ENVM0_R_SELECT;
+    PRINT "eNVM Module 0 is read/verify protected.";
+    UL_BUS_SII_ENVM0_R_SELECT:
+    IF ( ! (SEC_UL[66]==1) ) THEN GOTO UL_BUS_SII_ENVM0_W_SELECT;
+    PRINT "eNVM module 0 is erase/write protected.";
+    UL_BUS_SII_ENVM0_W_SELECT:
+    IF ( ! (SEC_UL[71]==1) ) THEN GOTO UL_M3_ALLOWED_L0_SELECT;
+    PRINT "Arm CortexM3 access to eNVM module 0 lower sector is protected.";
+    UL_M3_ALLOWED_L0_SELECT:
+    IF ( ! (SEC_UL[72]==1) ) THEN GOTO UL_FAB_ALLOWED_L0_SELECT;
+    PRINT "Fabric access to eNVM module 0 lower sector is protected.";
+    UL_FAB_ALLOWED_L0_SELECT:
+    IF ( ! (SEC_UL[73]==1) ) THEN GOTO UL_OTHERS_ALLOWED_L0_SELECT;
+    PRINT "Other masters access to eNVM module 0 lower sector is protected.";
+    UL_OTHERS_ALLOWED_L0_SELECT:
+    IF ( ! (SEC_UL[74]==1) ) THEN GOTO UL_WRITE_ALLOWED_L0_SELECT;
+    PRINT "Master write access to eNVM module 0 lower sector is protected.";
+    UL_WRITE_ALLOWED_L0_SELECT:
+    IF ( ! (SEC_UL[75]==1) ) THEN GOTO UL_M3_ALLOWED_U0_SELECT;
+    PRINT "Arm CortexM3 access to eNVM module 0 upper sector is protected.";
+    UL_M3_ALLOWED_U0_SELECT:
+    IF ( ! (SEC_UL[76]==1) ) THEN GOTO UL_FAB_ALLOWED_U0_SELECT;
+    PRINT "Fabric access to eNVM module 0 upper sector is protected.";
+    UL_FAB_ALLOWED_U0_SELECT:
+    IF ( ! (SEC_UL[77]==1) ) THEN GOTO UL_OTHERS_ALLOWED_U0_SELECT;
+    PRINT "Other masters access to eNVM module 0 upper sector is protected.";
+    UL_OTHERS_ALLOWED_U0_SELECT:
+    IF ( ! (SEC_UL[78]==1) ) THEN GOTO UL_WRITE_ALLOWED_U0_SELECT;
+    PRINT "Master write access to eNVM module 0 upper sector is protected.";
+    UL_WRITE_ALLOWED_U0_SELECT:
+    IF ( ! (SEC_UL[30]==1) ) THEN GOTO UL_AUTO_DIGEST_POR_SELECT;
+    PRINT "Automatic digest check at power up is enabled.";
+    IF ( ! ( (SEC_UCNFG[4]==1)&&(SEC_UL[10]==0)) ) THEN GOTO AUTODIGEST_FABRIC_SELECT;
+    PRINT "FPGA array power on digest is enabled.";
+    AUTODIGEST_FABRIC_SELECT:
+    IF ( ! (SEC_UCNFG[5]==1) ) THEN GOTO AUTODIGEST_ENVM0_SELECT;
+    PRINT "eNVM module 0 power on digest is enabled.";
+    AUTODIGEST_ENVM0_SELECT:
+    LABEL_SEPARATOR = 0;
+    UL_AUTO_DIGEST_POR_SELECT:
+    IF ( ! (SEC_UKL[0]==1) ) THEN GOTO UKSL_SELECT;
+    PRINT "User Key Set 1 is erase/write protected.";
+    UKSL_SELECT:
+    IF ( ! (SEC_UKL[1]==1) ) THEN GOTO UKSVL_SELECT;
+    PRINT "User Key Set 1 is verify protected.";
+    UKSVL_SELECT:
+    IF ( ! (SEC_VL[0]==1) ) THEN GOTO VSL_SELECT;
+    PRINT "User Key Set 2 is erase/write protected.";
+    VSL_SELECT:
+    IF ( ! (SEC_VL[1]==1) ) THEN GOTO VSPL_SELECT;
+    PRINT "User Key Set 2 is permanently locked.";
+    VSPL_SELECT:
+    IF ( ! (INT(SEC_CCNFG[1..0])==0) ) THEN GOTO NOT_50US;
+    PRINT "Power on reset delay: 50us";
+    NOT_50US:
+    IF ( ! (INT(SEC_CCNFG[1..0])==1) ) THEN GOTO NOT_1MS;
+    PRINT "Power on reset delay: 1ms";
+    NOT_1MS:
+    IF ( ! (INT(SEC_CCNFG[1..0])==2) ) THEN GOTO NOT_10MS;
+    PRINT "Power on reset delay: 10ms";
+    NOT_10MS:
+    IF ( ! (INT(SEC_CCNFG[1..0])==3) ) THEN GOTO NOT_100MS;
+    PRINT "Power on reset delay: 100ms";
+    NOT_100MS:
+    IF ( ! (SEC_CCNFG[2]==1) ) THEN GOTO BG_AVM_DISABLE_SELECT;
+    PRINT "Avionics Mode is disabled.";
+    BG_AVM_DISABLE_SELECT:
+    IF ( ! (SEC_CCNFG[3]==0) ) THEN GOTO MODE1V_SELECT;
+    PRINT "Operational Voltage: 1.2V";
+    PRINT "Internal Oscillator: 50MHZ";
+    MODE1V_SELECT:
+    IF ( ! (SEC_CCNFG[3]==1) ) THEN GOTO MODE12V_SELECT;
+    PRINT "Operational Voltage: 1.0V";
+    PRINT "Internal Oscillator: 25MHZ";
+    MODE12V_SELECT:
+    IF ( ! (SEC_CL[0]==1) ) THEN GOTO OTPL_SELECT;
+    PRINT "FPGA Array is one time programmable.";
+    OTPL_SELECT:
+    LABEL_SEPARATOR = 0;
+    Label_0:
+    IF ( ! (SECURITY_QUERIED==0) ) THEN GOTO DUMP_SEC_CANNOTREAD;
+    PRINT "Security locks and configuration settings cannot be read from the device.";
+    PRINT "This could be because of debug locks, please use programming file with DPK.";
+    DUMP_SEC_CANNOTREAD:
+    PRINT "-------------------------------------------------
+    ";
+ENDPROC;
+
+PROCEDURE SET_PGM_MODE USES GV,DO_EXIT;
+    BOOLEAN MODE_RESULT[8];
+    PASS = 0;
+    IRSTOP IRPAUSE;
+    DRSTOP DRPAUSE;
+    IRSCAN 8, $af;
+    DRSCAN 8, $00;
+    WAIT IDLE, 3 CYCLES;
+    WAIT 10 USEC, DRPAUSE;
+    FOR IPOLL = 100000 TO 0 STEP -1;
+        DRSCAN 8, $00, CAPTURE MODE_RESULT[7..0];
+        IF ( ! (MODE_RESULT[7]==0) ) THEN GOTO MODE_POLL;
+        IPOLL = 0;
+        PASS = 1;
+        MODE_POLL:
+        IF ( ! (PASS==0) ) THEN GOTO MODE_DONE;
+        IRSCAN 8, $af;
+        WAIT IRPAUSE, 10 USEC;
+        MODE_DONE:
+        LABEL_SEPARATOR = 0;
+    NEXT IPOLL;
+    IF ( ! (PASS==0) ) THEN GOTO MODE_PASSED;
+    PRINT "Failed to set programming voltage";
+    STATUS = 5;
+    CALL DO_EXIT;
+    MODE_PASSED:
+    LABEL_SEPARATOR = 0;
+ENDPROC;
+
+PROCEDURE POLL_DEVICE_READY USES GV,DO_EXIT;
+    PASS = 0;
+    INTEGER ILOOP_0;
+    FOR ILOOP_0 = 1000000 - 1 TO 0 STEP -1;
+        IRSTOP IRPAUSE;
+        DRSTOP DRPAUSE;
+        IRSCAN 8, $8f;
+        WAIT IDLE, 1 CYCLES;
+        WAIT IDLE, 10 USEC;
+        DRSCAN 8, $00,COMPARE $00,$80,PASS;
+        IF PASS THEN ILOOP_0 = 0;
+    NEXT ILOOP_0;
+    IF ( ! (PASS==0) ) THEN GOTO DEVICE_READY;
+    PRINT "Device is busy.";
+    STATUS = 5;
+    CALL DO_EXIT;
+    DEVICE_READY:
+    LABEL_SEPARATOR = 0;
+ENDPROC;
+
+PROCEDURE READ_SHARED_BUFFER USES GV,DO_EXIT;
+    INTEGER IBLOCK =0;
+    BOOLEAN BLOCKBUFFER[129];
+    FOR IBLOCK = 0 TO (INUMOFBLOCKS-1) STEP 1;
+        PASS = 0;
+        BOOLEAN SHARED_BUFFER_RESULT[129];
+        BLOCKBUFFER[6..1] = BOOL(IBLOCK);
+        IRSTOP IRPAUSE;
+        DRSTOP DRPAUSE;
+        IRSCAN 8, $f2;
+        DRSCAN 129, BLOCKBUFFER[];
+        WAIT IDLE, 3 CYCLES;
+        WAIT 10 USEC, DRPAUSE;
+        FOR IPOLL = 100000 TO 0 STEP -1;
+            DRSCAN 129, $000000000000000000000000000000000, CAPTURE SHARED_BUFFER_RESULT[];
+            IF ( ! (SHARED_BUFFER_RESULT[128]==0) ) THEN GOTO READ_BUFFER_POLL;
+            IPOLL = 0;
+            PASS = 1;
+            READ_BUFFER_POLL:
+            IF ( ! (PASS==0) ) THEN GOTO READ_BUFFER_DONE;
+            IRSCAN 8, $f2;
+            WAIT IRPAUSE, 10 USEC;
+            READ_BUFFER_DONE:
+            LABEL_SEPARATOR = 0;
+        NEXT IPOLL;
+        IF ( ! (PASS==0) ) THEN GOTO READ_BUFFER_PASS;
+        PRINT "Failed to read design information.";
+        STATUS = 5;
+        CALL DO_EXIT;
+        READ_BUFFER_PASS:
+        SHARED_BUFFER[((128*IBLOCK)+127)..(128*IBLOCK)] = SHARED_BUFFER_RESULT[127..0];
+    NEXT IBLOCK;
+ENDPROC;
+
+PROCEDURE DO_QUERY_SECURITY USES GV,DO_EXIT,READ_SHARED_BUFFER;
+    BOOLEAN QUERY_SECURITY_RESULT[16];
+    PASS = 0;
+    SECURITY_QUERIED = 0;
+    IRSTOP IRPAUSE;
+    DRSTOP DRPAUSE;
+    IRSCAN 8, $b8;
+    DRSCAN 16, $0000;
+    WAIT IDLE, 3 CYCLES;
+    WAIT 10 USEC, DRPAUSE;
+    FOR IPOLL = 100000 TO 0 STEP -1;
+        DRSCAN 16, $0000, CAPTURE QUERY_SECURITY_RESULT[];
+        IF ( ! (QUERY_SECURITY_RESULT[15]==0) ) THEN GOTO QUERY_SECURITY_POLL;
+        IPOLL = 0;
+        PASS = 1;
+        QUERY_SECURITY_POLL:
+        IF ( ! (PASS==0) ) THEN GOTO QUERY_SECURITY_DONE;
+        IRSCAN 8, $b8;
+        WAIT IRPAUSE, 10 USEC;
+        QUERY_SECURITY_DONE:
+        LABEL_SEPARATOR = 0;
+    NEXT IPOLL;
+    IF ( ! (PASS==0) ) THEN GOTO QUERY_SECURITY_PASS;
+    PRINT "Failed to query security information.";
+    STATUS = 14;
+    CALL DO_EXIT;
+    QUERY_SECURITY_PASS:
+    INUMOFBLOCKS = 3;
+    CALL READ_SHARED_BUFFER;
+    FOR I = 0 TO 319 STEP 1;
+        IF ( ! (SHARED_BUFFER[I]==1) ) THEN GOTO DO_QUERY_SECURITY_SUCCESS;
+        SECURITY_QUERIED = 1;
+        I = 320;
+        DO_QUERY_SECURITY_SUCCESS:
+        LABEL_SEPARATOR = 0;
+    NEXT I;
+ENDPROC;
+
+PROCEDURE DO_READ_SECURITY USES GV,DO_QUERY_SECURITY;
+    INTEGER BYTEIDX =0;
+    CALL DO_QUERY_SECURITY;
+    IF ( ! (SECURITY_QUERIED==0) ) THEN GOTO Label_1;
+    PRINT "WARNING! Security cannot be read. This can be because of programmed debug lock. Please generate programming file with debug passkey provided.";
+    Label_1:
+    BYTEIDX = 0;
+    SEC_UKL[5..0] = SHARED_BUFFER[((BYTEIDX*8)+7)..((BYTEIDX*8)+2)];
+    BYTEIDX = 1;
+    SEC_UKL[11..6] = SHARED_BUFFER[((BYTEIDX*8)+7)..((BYTEIDX*8)+2)];
+    BYTEIDX = 2;
+    SEC_VL[5..0] = SHARED_BUFFER[((BYTEIDX*8)+7)..((BYTEIDX*8)+2)];
+    BYTEIDX = 3;
+    SEC_VL[11..6] = SHARED_BUFFER[((BYTEIDX*8)+7)..((BYTEIDX*8)+2)];
+    BYTEIDX = 4;
+    SEC_UL[5..0] = SHARED_BUFFER[((BYTEIDX*8)+7)..((BYTEIDX*8)+2)];
+    BYTEIDX = 5;
+    SEC_UL[11..6] = SHARED_BUFFER[((BYTEIDX*8)+7)..((BYTEIDX*8)+2)];
+    BYTEIDX = 6;
+    SEC_UL[17..12] = SHARED_BUFFER[((BYTEIDX*8)+7)..((BYTEIDX*8)+2)];
+    BYTEIDX = 7;
+    SEC_UL[23..18] = SHARED_BUFFER[((BYTEIDX*8)+7)..((BYTEIDX*8)+2)];
+    BYTEIDX = 8;
+    SEC_CL[2..0] = SHARED_BUFFER[((BYTEIDX*8)+7)..((BYTEIDX*8)+5)];
+    SEC_OPOK[2..0] = SHARED_BUFFER[((BYTEIDX*8)+4)..((BYTEIDX*8)+2)];
+    BYTEIDX = 9;
+    SEC_CL[5..3] = SHARED_BUFFER[((BYTEIDX*8)+7)..((BYTEIDX*8)+5)];
+    SEC_CCNFG[1..0] = SHARED_BUFFER[((BYTEIDX*8)+4)..((BYTEIDX*8)+3)];
+    SEC_OPOK[3] = SHARED_BUFFER[((BYTEIDX*8)+2)];
+    BYTEIDX = 10;
+    SEC_CL[8..6] = SHARED_BUFFER[((BYTEIDX*8)+7)..((BYTEIDX*8)+5)];
+    SEC_CCNFG[4..2] = SHARED_BUFFER[((BYTEIDX*8)+4)..((BYTEIDX*8)+2)];
+    BYTEIDX = 11;
+    SEC_CL[11..9] = SHARED_BUFFER[((BYTEIDX*8)+7)..((BYTEIDX*8)+5)];
+    SEC_CCNFG[7..5] = SHARED_BUFFER[((BYTEIDX*8)+4)..((BYTEIDX*8)+2)];
+    BYTEIDX = 12;
+    SEC_UL[26..24] = SHARED_BUFFER[((BYTEIDX*8)+7)..((BYTEIDX*8)+5)];
+    SEC_USERCODE[2..0] = SHARED_BUFFER[((BYTEIDX*8)+4)..((BYTEIDX*8)+2)];
+    BYTEIDX = 13;
+    SEC_UL[29..27] = SHARED_BUFFER[((BYTEIDX*8)+7)..((BYTEIDX*8)+5)];
+    SEC_USERCODE[5..3] = SHARED_BUFFER[((BYTEIDX*8)+4)..((BYTEIDX*8)+2)];
+    BYTEIDX = 14;
+    SEC_UL[32..30] = SHARED_BUFFER[((BYTEIDX*8)+7)..((BYTEIDX*8)+5)];
+    SEC_USERCODE[8..6] = SHARED_BUFFER[((BYTEIDX*8)+4)..((BYTEIDX*8)+2)];
+    BYTEIDX = 15;
+    SEC_UL[35..33] = SHARED_BUFFER[((BYTEIDX*8)+7)..((BYTEIDX*8)+5)];
+    SEC_USERCODE[11..9] = SHARED_BUFFER[((BYTEIDX*8)+4)..((BYTEIDX*8)+2)];
+    BYTEIDX = 16;
+    SEC_UL[38..36] = SHARED_BUFFER[((BYTEIDX*8)+7)..((BYTEIDX*8)+5)];
+    SEC_USERCODE[14..12] = SHARED_BUFFER[((BYTEIDX*8)+4)..((BYTEIDX*8)+2)];
+    BYTEIDX = 17;
+    SEC_UL[41..39] = SHARED_BUFFER[((BYTEIDX*8)+7)..((BYTEIDX*8)+5)];
+    SEC_USERCODE[17..15] = SHARED_BUFFER[((BYTEIDX*8)+4)..((BYTEIDX*8)+2)];
+    BYTEIDX = 18;
+    SEC_UL[44..42] = SHARED_BUFFER[((BYTEIDX*8)+7)..((BYTEIDX*8)+5)];
+    SEC_USERCODE[20..18] = SHARED_BUFFER[((BYTEIDX*8)+4)..((BYTEIDX*8)+2)];
+    BYTEIDX = 19;
+    SEC_UL[47..45] = SHARED_BUFFER[((BYTEIDX*8)+7)..((BYTEIDX*8)+5)];
+    SEC_USERCODE[23..21] = SHARED_BUFFER[((BYTEIDX*8)+4)..((BYTEIDX*8)+2)];
+    BYTEIDX = 20;
+    SEC_UL[50..48] = SHARED_BUFFER[((BYTEIDX*8)+7)..((BYTEIDX*8)+5)];
+    SEC_USERCODE[26..24] = SHARED_BUFFER[((BYTEIDX*8)+4)..((BYTEIDX*8)+2)];
+    BYTEIDX = 21;
+    SEC_UL[53..51] = SHARED_BUFFER[((BYTEIDX*8)+7)..((BYTEIDX*8)+5)];
+    SEC_USERCODE[29..27] = SHARED_BUFFER[((BYTEIDX*8)+4)..((BYTEIDX*8)+2)];
+    BYTEIDX = 22;
+    SEC_UL[56..54] = SHARED_BUFFER[((BYTEIDX*8)+7)..((BYTEIDX*8)+5)];
+    SEC_UCNFG[0] = SHARED_BUFFER[((BYTEIDX*8)+4)];
+    SEC_USERCODE[31..30] = SHARED_BUFFER[((BYTEIDX*8)+3)..((BYTEIDX*8)+2)];
+    BYTEIDX = 23;
+    SEC_UL[59..57] = SHARED_BUFFER[((BYTEIDX*8)+7)..((BYTEIDX*8)+5)];
+    SEC_UCNFG[3..1] = SHARED_BUFFER[((BYTEIDX*8)+4)..((BYTEIDX*8)+2)];
+    BYTEIDX = 24;
+    SEC_UL[62..60] = SHARED_BUFFER[((BYTEIDX*8)+7)..((BYTEIDX*8)+5)];
+    SEC_UCNFG[6..4] = SHARED_BUFFER[((BYTEIDX*8)+4)..((BYTEIDX*8)+2)];
+    BYTEIDX = 25;
+    SEC_UL[65..63] = SHARED_BUFFER[((BYTEIDX*8)+7)..((BYTEIDX*8)+5)];
+    SEC_UCNFG[9..7] = SHARED_BUFFER[((BYTEIDX*8)+4)..((BYTEIDX*8)+2)];
+    BYTEIDX = 26;
+    SEC_UL[68..66] = SHARED_BUFFER[((BYTEIDX*8)+7)..((BYTEIDX*8)+5)];
+    SEC_UCNFG[12..10] = SHARED_BUFFER[((BYTEIDX*8)+4)..((BYTEIDX*8)+2)];
+    BYTEIDX = 27;
+    SEC_UL[71..69] = SHARED_BUFFER[((BYTEIDX*8)+7)..((BYTEIDX*8)+5)];
+    SEC_UCNFG[15..13] = SHARED_BUFFER[((BYTEIDX*8)+4)..((BYTEIDX*8)+2)];
+    BYTEIDX = 28;
+    SEC_UL[74..72] = SHARED_BUFFER[((BYTEIDX*8)+7)..((BYTEIDX*8)+5)];
+    BYTEIDX = 29;
+    SEC_UL[77..75] = SHARED_BUFFER[((BYTEIDX*8)+7)..((BYTEIDX*8)+5)];
+    BYTEIDX = 30;
+    SEC_UL[80..78] = SHARED_BUFFER[((BYTEIDX*8)+7)..((BYTEIDX*8)+5)];
+    SEC_UCNFG[18..16] = SHARED_BUFFER[((BYTEIDX*8)+4)..((BYTEIDX*8)+2)];
+    BYTEIDX = 31;
+    SEC_UL[83..81] = SHARED_BUFFER[((BYTEIDX*8)+7)..((BYTEIDX*8)+5)];
+    SEC_UCNFG[21..19] = SHARED_BUFFER[((BYTEIDX*8)+4)..((BYTEIDX*8)+2)];
+    BYTEIDX = 32;
+    SEC_UL[86..84] = SHARED_BUFFER[((BYTEIDX*8)+7)..((BYTEIDX*8)+5)];
+    SEC_UCNFG[24..22] = SHARED_BUFFER[((BYTEIDX*8)+4)..((BYTEIDX*8)+2)];
+    BYTEIDX = 33;
+    SEC_UL[89..87] = SHARED_BUFFER[((BYTEIDX*8)+7)..((BYTEIDX*8)+5)];
+    SEC_UCNFG[27..25] = SHARED_BUFFER[((BYTEIDX*8)+4)..((BYTEIDX*8)+2)];
+    BYTEIDX = 34;
+    SEC_UL[92..90] = SHARED_BUFFER[((BYTEIDX*8)+7)..((BYTEIDX*8)+5)];
+    SEC_UCNFG[30..28] = SHARED_BUFFER[((BYTEIDX*8)+4)..((BYTEIDX*8)+2)];
+    BYTEIDX = 35;
+    SEC_UL[95..93] = SHARED_BUFFER[((BYTEIDX*8)+7)..((BYTEIDX*8)+5)];
+    SEC_UCNFG[33..31] = SHARED_BUFFER[((BYTEIDX*8)+4)..((BYTEIDX*8)+2)];
+    BYTEIDX = 36;
+    SEC_DL[2..0] = SHARED_BUFFER[((BYTEIDX*8)+7)..((BYTEIDX*8)+5)];
+    SEC_UCNFG[36..34] = SHARED_BUFFER[((BYTEIDX*8)+4)..((BYTEIDX*8)+2)];
+    BYTEIDX = 37;
+    SEC_DL[5..3] = SHARED_BUFFER[((BYTEIDX*8)+7)..((BYTEIDX*8)+5)];
+    SEC_UCNFG[39..37] = SHARED_BUFFER[((BYTEIDX*8)+4)..((BYTEIDX*8)+2)];
+    BYTEIDX = 38;
+    SEC_DL[8..6] = SHARED_BUFFER[((BYTEIDX*8)+7)..((BYTEIDX*8)+5)];
+    SEC_UCNFG[42..40] = SHARED_BUFFER[((BYTEIDX*8)+4)..((BYTEIDX*8)+2)];
+    BYTEIDX = 39;
+    SEC_DL[11..9] = SHARED_BUFFER[((BYTEIDX*8)+7)..((BYTEIDX*8)+5)];
+    SEC_UCNFG[45..43] = SHARED_BUFFER[((BYTEIDX*8)+4)..((BYTEIDX*8)+2)];
+ENDPROC;
+
+PROCEDURE PROC_ENABLE USES GV,DO_EXIT,SET_PGM_MODE,POLL_DEVICE_READY,DO_READ_SECURITY;
+    CALL POLL_DEVICE_READY;
+    CALL SET_PGM_MODE;
+    CALL DO_READ_SECURITY;
+    BOOLEAN ISC_ENABLE_RESULT[32];
+    BPGMMODE = 1;
+    PASS = 0;
+    BSR[1145..0] = BSRPATTERN[1145..0];
+    BOOLEAN SHIFT_DATA[1146];
+    IRSCAN 8, $01;
+    DRSCAN 1146, BSR[];
+    WAIT IDLE, 1 CYCLES;
+    DRSCAN 1146, SHIFT_DATA[], CAPTURE SAMPLE_DEVICE[];
+    FOR I = 0 TO 1145;
+        IF ( ! (SAMPLEMASK[I]==1) ) THEN GOTO Label_2;
+        BSR[I] = SAMPLE_DEVICE[I];
+        Label_2:
+        LABEL_SEPARATOR = 0;
+    NEXT I;
+    IRSTOP IRPAUSE;
+    DRSTOP DRPAUSE;
+    IRSCAN 8, $01;
+    DRSCAN 1146, BSR[];
+    WAIT IDLE, 1 CYCLES;
+    BOOLEAN TOOLINFO[32] = $00000000;
+    TOOLINFO[5..0] = ACT_UROW_ALGO_VERSION[5..0];
+    TOOLINFO[9..6] = ACT_UROW_PROGRAM_SW[3..0];
+    TOOLINFO[22..17] = ACT_UROW_SW_VERSION[5..0];
+    TOOLINFO[25..23] = BOOL(1);
+    TOOLINFO[28..26] = BOOL(3);
+    TOOLINFO[31..29] = BOOL(2);
+    IRSTOP IRPAUSE;
+    DRSTOP DRPAUSE;
+    IRSCAN 8, $80;
+    DRSCAN 32, TOOLINFO[];
+    WAIT IDLE, 3 CYCLES;
+    WAIT 10 USEC, DRPAUSE;
+    FOR IPOLL = 1000000 TO 0 STEP -1;
+        DRSCAN 32, $00000000, CAPTURE ISC_ENABLE_RESULT[31..0];
+        IF ( ! (ISC_ENABLE_RESULT[31]==0) ) THEN GOTO ISC_ENABLE_POLL;
+        IPOLL = 0;
+        PASS = 1;
+        ISC_ENABLE_POLL:
+        IF ( ! (PASS==0) ) THEN GOTO ISC_ENABLE_DONE;
+        IRSCAN 8, $80;
+        WAIT IRPAUSE, 10 USEC;
+        ISC_ENABLE_DONE:
+        LABEL_SEPARATOR = 0;
+    NEXT IPOLL;
+    EXPORT "ISC_ENABLE_RESULT", ISC_ENABLE_RESULT[];
+    EXPORT "CRCERR: ", ISC_ENABLE_RESULT[0];
+    EXPORT "EDCERR: ", ISC_ENABLE_RESULT[1];
+    IF ( ! (INT(ISC_ENABLE_RESULT[4..2])==0) ) THEN GOTO NOT_COLD;
+    PRINT "TEMPRANGE: COLD";
+    NOT_COLD:
+    IF ( ! (INT(ISC_ENABLE_RESULT[4..2])==1) ) THEN GOTO NOT_ROOM;
+    PRINT "TEMPGRADE: ROOM";
+    NOT_ROOM:
+    IF ( ! (INT(ISC_ENABLE_RESULT[4..2])==2) ) THEN GOTO NOT_HOT;
+    PRINT "TEMPGRADE: HOT";
+    NOT_HOT:
+    EXPORT "VPPRANGE: ", ISC_ENABLE_RESULT[7..5];
+    IF ( ! (INT(ISC_ENABLE_RESULT[7..5])==0) ) THEN GOTO NOT_LOW;
+    PRINT "VPPRANGE: LOW";
+    NOT_LOW:
+    IF ( ! (INT(ISC_ENABLE_RESULT[7..5])==1) ) THEN GOTO NOT_NOMINAL;
+    PRINT "VPPRANGE: NOMINAL";
+    NOT_NOMINAL:
+    IF ( ! (INT(ISC_ENABLE_RESULT[7..5])==2) ) THEN GOTO NOT_HIGH;
+    PRINT "VPPRANGE: HIGH";
+    NOT_HIGH:
+    EXPORT "TEMP: ", ISC_ENABLE_RESULT[15..8];
+    EXPORT "VPP: ", ISC_ENABLE_RESULT[23..16];
+    IF ( ! ( (PASS==0)||( (PASS==1)&&(ISC_ENABLE_RESULT[0]==1))) ) THEN GOTO ISC_ENABLE_PASS;
+    PRINT "Failed to enter programming mode.";
+    STATUS = 5;
+    CALL DO_EXIT;
+    ISC_ENABLE_PASS:
+    LABEL_SEPARATOR = 0;
+ENDPROC;
+
+PROCEDURE PRINT_IDCODE USES GV;
+    EXPORT "IDCODE", ID[];
+ENDPROC;
+
+PROCEDURE VERIFY_IDCODE USES GV,PARAMETERS,DO_EXIT;
+    FREQUENCY (FREQ*1000000);
+    WAIT RESET, 5 CYCLES;
+    IRSTOP IRPAUSE;
+    DRSTOP DRPAUSE;
+    IRSCAN 8, $0f;
+    DRSCAN 32, $00000000;
+    WAIT IDLE, 1 CYCLES;
+    DRSCAN 32, $00000000, CAPTURE ID[],COMPARE IDCODEVALUE[],IDMASK[],PASS;
+    IF ( ! (PASS==0) ) THEN GOTO IDOK;
+    STATUS = 6;
+    PRINT "Failed to verify IDCODE";
+    CALL DO_EXIT;
+    IDOK:
+    IF ( ! (PASS==1) ) THEN GOTO IDNOTOK;
+    IDNOTOK:
+    IDREV = INT(ID[31..28]);
+ENDPROC;
+
+PROCEDURE GET_DATA_STATUS USES GV;
+    INTEGER IPOLLDATA =0;
+    PASS = 0;
+    IRSTOP IRPAUSE;
+    DRSTOP DRPAUSE;
+    IRSCAN 8, $c9;
+    DRSCAN 32, $00000000;
+    WAIT IDLE, 3 CYCLES;
+    WAIT 10 USEC, DRPAUSE;
+    FOR IPOLLDATA = 100000 TO 0 STEP -1;
+        DRSCAN 32, $00000000, CAPTURE DATA_STATUS_RESULT[31..0];
+        IF ( ! (DATA_STATUS_RESULT[31]==0) ) THEN GOTO DATA_STATUS_POLL;
+        IPOLLDATA = 0;
+        PASS = 1;
+        DATA_STATUS_POLL:
+        IF ( ! (PASS==0) ) THEN GOTO DATA_STATUS_READ;
+        IRSCAN 8, $c9;
+        WAIT IRPAUSE, 10 USEC;
+        DATA_STATUS_READ:
+        LABEL_SEPARATOR = 0;
+    NEXT IPOLLDATA;
+ENDPROC;
+
+PROCEDURE PROCESS_DATA USES BITSTREAM,GV,DO_EXIT,GET_DATA_STATUS;
+    BOOLEAN DATA_SHIFT_RESULT[128];
+    INTEGER BLOCKNO =0;
+    INTEGER CURRNUMOFBLOCKS =0;
+    INTEGER COMPONENTNO =0;
+    FOR COMPONENTNO = ICURCOMPONENTNO TO ICURNUMOFCOMPONENTS STEP 1;
+        CURRNUMOFBLOCKS = INT(NUMOFBLOCKS[((COMPONENTNO*22)-1)..((COMPONENTNO-1)*22)]);
+        FOR BLOCKNO = 1 TO CURRNUMOFBLOCKS STEP 1;
+            PASS = 0;
+            IRSTOP IRPAUSE;
+            DRSTOP DRPAUSE;
+            IRSCAN 8, $ee;
+            DRSCAN 128, DATASTREAM[(DATAINDEX+127)..DATAINDEX];
+            WAIT IDLE, 3 CYCLES;
+            WAIT 16 USEC, DRPAUSE;
+            FOR IPOLL = 10000000 TO 0 STEP -1;
+                DRSCAN 128, $00000000000000000000000000000000, CAPTURE DATA_SHIFT_RESULT[127..0];
+                IF ( ! (DATA_SHIFT_RESULT[127]==0) ) THEN GOTO DATA_POLL;
+                IPOLL = 0;
+                PASS = 1;
+                DATA_POLL:
+                IF ( ! (PASS==0) ) THEN GOTO DATA_DONE;
+                IRSCAN 8, $ee;
+                WAIT IRPAUSE, 10 USEC;
+                DATA_DONE:
+                LABEL_SEPARATOR = 0;
+            NEXT IPOLL;
+            IF ( ! ( (PASS==0)||( (PASS==1)&&( (DATA_SHIFT_RESULT[3]==1)||(DATA_SHIFT_RESULT[4]==1)))) ) THEN GOTO DATA_PASS;
+            CALL GET_DATA_STATUS;
+            IF ( ! ( (PASS==0)||( (PASS==1)&&(DATA_STATUS_RESULT[2]==1))) ) THEN GOTO NO_ERROR_PER_BLOCK;
+            IF ( ! (INT(DATA_STATUS_RESULT[15..8])!=0) ) THEN GOTO NOT_AUTHERR;
+            PRINT "Authentication Error.";
+            IF ( ! ( ( ( ( ( ( (INT(DATA_STATUS_RESULT[15..8])==1)||(INT(DATA_STATUS_RESULT[15..8])==2))||(INT(DATA_STATUS_RESULT[15..8])==3))||(INT(DATA_STATUS_RESULT[15..8])==4))||(INT(DATA_STATUS_RESULT[15..8])==7))||(INT(DATA_STATUS_RESULT[15..8])==8))||(INT(DATA_STATUS_RESULT[15..8])==9)) ) THEN GOTO NOT_INVALID_BITSTREAM;
+            PRINT "Invalid/Corrupted programming file.";
+            NOT_INVALID_BITSTREAM:
+            IF ( ! (INT(DATA_STATUS_RESULT[15..8])==5) ) THEN GOTO BACKLEVEL_SATISFIED;
+            PRINT "Back level not satisfied.";
+            BACKLEVEL_SATISFIED:
+            IF ( ! (INT(DATA_STATUS_RESULT[15..8])==10) ) THEN GOTO CORRECT_IDCODE;
+            PRINT "Incorrect DEVICEID.";
+            CORRECT_IDCODE:
+            IF ( ! (INT(DATA_STATUS_RESULT[15..8])==11) ) THEN GOTO BITSTREAM_FINE;
+            PRINT "Programming file is out dated, please regenerate.";
+            BITSTREAM_FINE:
+            IF ( ! (INT(DATA_STATUS_RESULT[15..8])==12) ) THEN GOTO BITSTREAM_VER;
+            PRINT "Programming file does not support verification.";
+            BITSTREAM_VER:
+            LABEL_SEPARATOR = 0;
+            NOT_AUTHERR:
+            IF ( ! (INT(DATA_STATUS_RESULT[7..3])!=0) ) THEN GOTO NOT_ERRORCODE;
+            IF ( ! (INT(DATA_STATUS_RESULT[7..3])==5) ) THEN GOTO NOT_NVMVERIFY;
+            PRINT "Failed to verify eNVM.";
+            NOT_NVMVERIFY:
+            IF ( ! (INT(DATA_STATUS_RESULT[7..3])==4) ) THEN GOTO NOT_NVMPRG;
+            PRINT "Failed to program eNVM.";
+            NOT_NVMPRG:
+            IF ( ! (INT(DATA_STATUS_RESULT[7..3])==3) ) THEN GOTO PROTOCOL_ENABLED;
+            PRINT "Programming protocol is disabled.";
+            PROTOCOL_ENABLED:
+            IF ( ! (INT(DATA_STATUS_RESULT[7..3])==2) ) THEN GOTO DEVICE_NO_SEC;
+            PRINT "Device security prevented operation.";
+            DEVICE_NO_SEC:
+            IF ( ! (INT(DATA_STATUS_RESULT[7..3])==1) ) THEN GOTO FABRIC_VER_FINE;
+            PRINT "Failed to verify FPGA Array.";
+            FABRIC_VER_FINE:
+            LABEL_SEPARATOR = 0;
+            NOT_ERRORCODE:
+            PRINT "componentNo: ",COMPONENTNO;
+            PRINT "blockNo: ",BLOCKNO;
+            EXPORT "DATA_STATUS_RESULT: ", DATA_STATUS_RESULT[31..0];
+            EXPORT "ERRORCODE: ", DATA_STATUS_RESULT[7..3];
+            EXPORT "AUTHERRCODE: ", DATA_STATUS_RESULT[15..8];
+            STATUS = 10;
+            CALL DO_EXIT;
+            NO_ERROR_PER_BLOCK:
+            LABEL_SEPARATOR = 0;
+            DATA_PASS:
+            DATAINDEX = (DATAINDEX+128);
+        NEXT BLOCKNO;
+    NEXT COMPONENTNO;
+ENDPROC;
+
+PROCEDURE SET_MODE USES GV,DO_EXIT;
+    BOOLEAN DATA_INIT_RESULT[8];
+    PASS = 0;
+    IRSTOP IRPAUSE;
+    DRSTOP DRPAUSE;
+    IRSCAN 8, $ae;
+    DRSCAN 8, PGMMODE[];
+    WAIT IDLE, 3 CYCLES;
+    WAIT 10 USEC, DRPAUSE;
+    FOR IPOLL = 100000 TO 0 STEP -1;
+        DRSCAN 8, $00, CAPTURE DATA_INIT_RESULT[7..0];
+        IF ( ! (DATA_INIT_RESULT[7]==0) ) THEN GOTO DATA_INIT_POLL;
+        IPOLL = 0;
+        PASS = 1;
+        DATA_INIT_POLL:
+        IF ( ! (PASS==0) ) THEN GOTO DATA_INIT_DONE;
+        IRSCAN 8, $ae;
+        WAIT IRPAUSE, 10 USEC;
+        DATA_INIT_DONE:
+        LABEL_SEPARATOR = 0;
+    NEXT IPOLL;
+    IF ( ! (PASS==0) ) THEN GOTO DATA_INIT_PASSED;
+    PRINT "Failed to set programming mode";
+    STATUS = 5;
+    CALL DO_EXIT;
+    DATA_INIT_PASSED:
+    LABEL_SEPARATOR = 0;
+ENDPROC;
+
+PROCEDURE DO_VERIFY USES GV,PROCESS_DATA,SET_MODE;
+    PRINT "Verifying FPGA Array...";
+    PGMMODE[7..0] = $02;
+    CALL SET_MODE;
+    ICURCOMPONENTNO = 1;
+    ICURNUMOFCOMPONENTS = DATASIZE;
+    DATAINDEX = DATASTARTINDEX;
+    CALL PROCESS_DATA;
+ENDPROC;
+
+PROCEDURE DO_PROGRAM USES GV,PROCESS_DATA,SET_MODE;
+    PRINT "Programming FPGA Array...";
+    PGMMODE[7..0] = $01;
+    CALL SET_MODE;
+    ICURCOMPONENTNO = 1;
+    ICURNUMOFCOMPONENTS = DATASIZE;
+    DATAINDEX = DATASTARTINDEX;
+    CALL PROCESS_DATA;
+ENDPROC;
+
+PROCEDURE DO_AUTHENTICATION USES GV,PROCESS_DATA,SET_MODE;
+    PRINT "Encrypted data authentication...";
+    PGMMODE[7..0] = $00;
+    CALL SET_MODE;
+    ICURCOMPONENTNO = 1;
+    ICURNUMOFCOMPONENTS = DATASIZE;
+    DATAINDEX = DATASTARTINDEX;
+    CALL PROCESS_DATA;
+ENDPROC;
+
+PROCEDURE DUMP_PROG_INFO USES GV,CONSTBLOCK;
+    INTEGER TMPINT =0;
+    BUFF32[31..0] = READ_PROG_INFO_RESULT[95..64];
+    EXPORT "PROG_INFO", READ_PROG_INFO_RESULT[127..0];
+    TMPINT = INT(READ_PROG_INFO_RESULT[48..48]);
+    IF ( ! (TMPINT==0) ) THEN GOTO NOT_12;
+    PRINT "VCC was programmed at 1.2V";
+    NOT_12:
+    IF ( ! (TMPINT==1) ) THEN GOTO NOT_10;
+    PRINT "VCC was programmed at 1.0V";
+    NOT_10:
+    TMPINT = INT(BUFF32[5..0]);
+    IF ( ! ( (TMPINT==0)||(TMPINT==63)) ) THEN GOTO NOT_UNDEF;
+    PRINT "Algorithm Version:";
+    NOT_UNDEF:
+    IF ( ! ( (TMPINT!=0)&&(TMPINT!=63)) ) THEN GOTO UNDEF;
+    PRINT "Algorithm Version: ",INT(BUFF32[5..0]);
+    UNDEF:
+    TMPINT = INT(BUFF32[9..6]);
+    IF ( ! (TMPINT==SELF) ) THEN GOTO NOT_SELF;
+    PRINT "Programmer: SPI Master Auto Programming";
+    NOT_SELF:
+    IF ( ! (TMPINT==SCULPTW) ) THEN GOTO NOT_SCULPTW;
+    PRINT "Programmer: Silicon Sculptor II/III";
+    NOT_SCULPTW:
+    IF ( ! (TMPINT==BPWIN) ) THEN GOTO NOT_BPW;
+    PRINT "Programmer: BP Programmer";
+    NOT_BPW:
+    IF ( ! (TMPINT==ACTEL_IHP) ) THEN GOTO NOT_ACTEL_IHP;
+    PRINT "Programmer: Actel IHP";
+    NOT_ACTEL_IHP:
+    IF ( ! (TMPINT==FP3) ) THEN GOTO NOT_FP3;
+    PRINT "Programmer: FlashPro3";
+    NOT_FP3:
+    IF ( ! (TMPINT==FP4) ) THEN GOTO NOT_FP4;
+    PRINT "Programmer: FlashPro4";
+    NOT_FP4:
+    IF ( ! (TMPINT==FP_FTDI) ) THEN GOTO NOT_FTDI;
+    PRINT "Programmer: FP-FTDI";
+    NOT_FTDI:
+    IF ( ! (TMPINT==SIL_EXPL) ) THEN GOTO NOT_SIL_EXPL;
+    PRINT "Programmer: Silicon Explorer";
+    NOT_SIL_EXPL:
+    IF ( ! (TMPINT==ATE) ) THEN GOTO NOT_ATE;
+    PRINT "Programmer: Non Actel Programmer";
+    NOT_ATE:
+    IF ( ! ( (TMPINT==0)||(TMPINT==15)) ) THEN GOTO UNDEF_P_T;
+    PRINT "Programmer:";
+    UNDEF_P_T:
+    TMPINT = INT(BUFF32[22..17]);
+    IF ( ! (TMPINT==FP34) ) THEN GOTO NOT_FP34;
+    PRINT "Software Version: FlashPro v3.4";
+    NOT_FP34:
+    IF ( ! (TMPINT==FP40) ) THEN GOTO NOT_FP40;
+    PRINT "Software Version: FlashPro v4.0";
+    NOT_FP40:
+    IF ( ! (TMPINT==FP41) ) THEN GOTO NOT_FP41;
+    PRINT "Software Version: FlashPro v4.1";
+    NOT_FP41:
+    IF ( ! (TMPINT==FP42) ) THEN GOTO NOT_FP42;
+    PRINT "Software Version: FlashPro v4.2";
+    NOT_FP42:
+    IF ( ! (TMPINT==FP50) ) THEN GOTO NOT_FP50;
+    PRINT "Software Version: FlashPro v5.0";
+    NOT_FP50:
+    IF ( ! (TMPINT==FP51) ) THEN GOTO NOT_FP51;
+    PRINT "Software Version: FlashPro v5.1";
+    NOT_FP51:
+    IF ( ! (TMPINT==FP60) ) THEN GOTO NOT_FP60;
+    PRINT "Software Version: FlashPro v6.0";
+    NOT_FP60:
+    IF ( ! (TMPINT==FP61) ) THEN GOTO NOT_FP61;
+    PRINT "Software Version: FlashPro v6.1";
+    NOT_FP61:
+    IF ( ! (TMPINT==FP62) ) THEN GOTO NOT_FP62;
+    PRINT "Software Version: FlashPro v6.2";
+    NOT_FP62:
+    IF ( ! (TMPINT==FP84) ) THEN GOTO NOT_FP84;
+    PRINT "Software Version: FlashPro v8.4";
+    NOT_FP84:
+    IF ( ! (TMPINT==FP85) ) THEN GOTO NOT_FP85;
+    PRINT "Software Version: FlashPro v8.5";
+    NOT_FP85:
+    IF ( ! (TMPINT==FP86) ) THEN GOTO NOT_FP86;
+    PRINT "Software Version: FlashPro v8.6";
+    NOT_FP86:
+    IF ( ! (TMPINT==FP90) ) THEN GOTO NOT_FP90;
+    PRINT "Software Version: FlashPro v9.0";
+    NOT_FP90:
+    IF ( ! (TMPINT==FP91) ) THEN GOTO NOT_FP91;
+    PRINT "Software Version: FlashPro v9.1";
+    NOT_FP91:
+    IF ( ! (TMPINT==FP_10_LCP) ) THEN GOTO NOT_10_LCP;
+    PRINT "Software Version: FlashPro 10.0 LCP";
+    NOT_10_LCP:
+    IF ( ! (TMPINT==FP_11_BETA_SPA) ) THEN GOTO NOT_11_BETA_SPA;
+    PRINT "Software Version: FlashPro 11.0 Beta SPA";
+    NOT_11_BETA_SPA:
+    IF ( ! (TMPINT==FP_11_BETA_SP1) ) THEN GOTO NOT_11_BETA_SP1;
+    PRINT "Software Version: FlashPro 11.0 Beta SP1";
+    NOT_11_BETA_SP1:
+    IF ( ! (TMPINT==FP_11) ) THEN GOTO NOT_11;
+    PRINT "Software Version: FlashPro 11.0";
+    NOT_11:
+    IF ( ! ( (TMPINT==0)||(TMPINT==63)) ) THEN GOTO NOT_UNDEF_SOFT_VER;
+    PRINT "Software Version:";
+    NOT_UNDEF_SOFT_VER:
+    TMPINT = INT(BUFF32[25..23]);
+    IF ( ! (TMPINT==FP) ) THEN GOTO NOT_FP;
+    PRINT "Programming Software: FlashPro";
+    NOT_FP:
+    IF ( ! (TMPINT==DIRECTC) ) THEN GOTO NOT_DC;
+    PRINT "Programming Software: Direct C";
+    NOT_DC:
+    IF ( ! (TMPINT==NON_ACTEL) ) THEN GOTO NOT_NON_ACTEL;
+    PRINT "Programming Software: Non Actel SW";
+    NOT_NON_ACTEL:
+    IF ( ! ( (TMPINT==0)||(TMPINT==7)) ) THEN GOTO UNDEF_P_S;
+    PRINT "Programming Software:";
+    UNDEF_P_S:
+    TMPINT = INT(BUFF32[28..26]);
+    IF ( ! (TMPINT==SPI_MASTER) ) THEN GOTO NOT_SPI_MASTER;
+    PRINT "Programming Interface Protocol: SPI Master";
+    NOT_SPI_MASTER:
+    IF ( ! (TMPINT==SPI_SLAVE) ) THEN GOTO NOT_SPI_SLAVE;
+    PRINT "Programming Interface Protocol: SPI Slave";
+    NOT_SPI_SLAVE:
+    IF ( ! (TMPINT==JTAG) ) THEN GOTO NOT_JTAG;
+    PRINT "Programming Interface Protocol: JTAG";
+    NOT_JTAG:
+    IF ( ! (TMPINT==I2C_MASTER) ) THEN GOTO NOT_I2C_MASTER;
+    PRINT "Programming Interface Protocol: I2C Master";
+    NOT_I2C_MASTER:
+    IF ( ! (TMPINT==I2C_SLAVE) ) THEN GOTO NOT_I2C_SLAVE;
+    PRINT "Programming Interface Protocol: I2C Slave";
+    NOT_I2C_SLAVE:
+    IF ( ! ( (TMPINT==0)||(TMPINT==7)) ) THEN GOTO UNDEF_P_I_P;
+    PRINT "Programming Interface Protocol:";
+    UNDEF_P_I_P:
+    TMPINT = INT(BUFF32[31..29]);
+    IF ( ! (TMPINT==PDB) ) THEN GOTO NOT_PDB;
+    PRINT "Programming File Type: PDB";
+    NOT_PDB:
+    IF ( ! (TMPINT==STAPL) ) THEN GOTO NOT_STAPL;
+    PRINT "Programming File Type: STAPL";
+    NOT_STAPL:
+    IF ( ! (TMPINT==SVF) ) THEN GOTO NOT_SVF;
+    PRINT "Programming File Type: SVF";
+    NOT_SVF:
+    IF ( ! (TMPINT==PCF) ) THEN GOTO NOT_PCF;
+    PRINT "Programming File Type: PCF";
+    NOT_PCF:
+    IF ( ! (TMPINT==IEEE1532) ) THEN GOTO NOT_IEEE1532;
+    PRINT "Programming File Type: IEEE 1532";
+    NOT_IEEE1532:
+    IF ( ! ( (TMPINT==0)||(TMPINT==7)) ) THEN GOTO UNDEF_P_F_T;
+    PRINT "Programming File Type:";
+    UNDEF_P_F_T:
+    LABEL_SEPARATOR = 0;
+ENDPROC;
+
+PROCEDURE FIX_INT_ARRAYS USES GV;
+    INTEGER TEMP =0;
+    IF ( ! (HEX[0]!=48) ) THEN GOTO Label_3;
+    FOR I = 0 TO 7;
+        TEMP = HEX[I];
+        HEX[I] = HEX[(15-I)];
+        HEX[(15-I)] = TEMP;
+    NEXT I;
+    Label_3:
+    LABEL_SEPARATOR = 0;
+ENDPROC;
+
+PROCEDURE DO_READ_DESIGN_INFO USES GV,DO_EXIT,READ_SHARED_BUFFER;
+    BOOLEAN READ_DESIGN_INFO_RESULT[8];
+    PASS = 0;
+    IRSTOP IRPAUSE;
+    DRSTOP DRPAUSE;
+    IRSCAN 8, $a6;
+    DRSCAN 8, $00;
+    WAIT IDLE, 3 CYCLES;
+    WAIT 10 USEC, DRPAUSE;
+    FOR IPOLL = 100000 TO 0 STEP -1;
+        DRSCAN 8, $00, CAPTURE READ_DESIGN_INFO_RESULT[];
+        IF ( ! (READ_DESIGN_INFO_RESULT[7]==0) ) THEN GOTO READ_DESIGN_INFO_POLL;
+        IPOLL = 0;
+        PASS = 1;
+        READ_DESIGN_INFO_POLL:
+        IF ( ! (PASS==0) ) THEN GOTO READ_DESIGN_INFO_DONE;
+        IRSCAN 8, $a6;
+        WAIT IRPAUSE, 10 USEC;
+        READ_DESIGN_INFO_DONE:
+        LABEL_SEPARATOR = 0;
+    NEXT IPOLL;
+    IF ( ! (PASS==0) ) THEN GOTO READ_DESIGN_INFO_PASS;
+    PRINT "Failed to read design information.";
+    STATUS = 5;
+    CALL DO_EXIT;
+    READ_DESIGN_INFO_PASS:
+    INUMOFBLOCKS = 3;
+    CALL READ_SHARED_BUFFER;
+    PRINT "Design Name: ",CHR$(INT(SHARED_BUFFER[23..16])),CHR$(INT(SHARED_BUFFER[31..24]))
+        ,CHR$(INT(SHARED_BUFFER[39..32])),CHR$(INT(SHARED_BUFFER[47..40])),CHR$(INT(SHARED_BUFFER[55..48]))
+        ,CHR$(INT(SHARED_BUFFER[63..56])),CHR$(INT(SHARED_BUFFER[71..64])),CHR$(INT(SHARED_BUFFER[79..72]))
+        ,CHR$(INT(SHARED_BUFFER[87..80])),CHR$(INT(SHARED_BUFFER[95..88])),CHR$(INT(SHARED_BUFFER[103..96]))
+        ,CHR$(INT(SHARED_BUFFER[111..104])),CHR$(INT(SHARED_BUFFER[119..112])),CHR$(INT(SHARED_BUFFER[127..120]))
+        ,CHR$(INT(SHARED_BUFFER[135..128])),CHR$(INT(SHARED_BUFFER[143..136])),CHR$(INT(SHARED_BUFFER[151..144]))
+        ,CHR$(INT(SHARED_BUFFER[159..152])),CHR$(INT(SHARED_BUFFER[167..160])),CHR$(INT(SHARED_BUFFER[175..168]))
+        ,CHR$(INT(SHARED_BUFFER[183..176])),CHR$(INT(SHARED_BUFFER[191..184])),CHR$(INT(SHARED_BUFFER[199..192]))
+        ,CHR$(INT(SHARED_BUFFER[207..200])),CHR$(INT(SHARED_BUFFER[215..208])),CHR$(INT(SHARED_BUFFER[223..216]))
+        ,CHR$(INT(SHARED_BUFFER[231..224])),CHR$(INT(SHARED_BUFFER[239..232])),CHR$(INT(SHARED_BUFFER[247..240]))
+        ,CHR$(INT(SHARED_BUFFER[255..248]));
+    EXPORT "CHECKSUM: ", SHARED_BUFFER[15..0];
+    EXPORT "READ_DESIGN_INFO: ", SHARED_BUFFER[271..0];
+    EXPORT "DESIGNVER: ", SHARED_BUFFER[271..256];
+    EXPORT "BACKLEVEL: ", SHARED_BUFFER[287..272];
+ENDPROC;
+
+PROCEDURE DO_READ_PROG_INFO USES GV,DO_EXIT;
+    PASS = 0;
+    IRSTOP IRPAUSE;
+    DRSTOP DRPAUSE;
+    IRSCAN 8, $e7;
+    DRSCAN 128, $00000000000000000000000000000000;
+    WAIT IDLE, 3 CYCLES;
+    WAIT 10 USEC, DRPAUSE;
+    FOR IPOLL = 100000 TO 0 STEP -1;
+        DRSCAN 128, $00000000000000000000000000000000, CAPTURE READ_PROG_INFO_RESULT[];
+        IF ( ! (READ_PROG_INFO_RESULT[127]==0) ) THEN GOTO READ_PROG_INFO_POLL;
+        IPOLL = 0;
+        PASS = 1;
+        READ_PROG_INFO_POLL:
+        IF ( ! (PASS==0) ) THEN GOTO READ_PROG_INFO_DONE;
+        IRSCAN 8, $e7;
+        WAIT IRPAUSE, 10 USEC;
+        READ_PROG_INFO_DONE:
+        LABEL_SEPARATOR = 0;
+    NEXT IPOLL;
+    IF ( ! (PASS==0) ) THEN GOTO READ_PROG_INFO_PASS;
+    PRINT "Failed to read programming information.";
+    STATUS = 5;
+    CALL DO_EXIT;
+    READ_PROG_INFO_PASS:
+    LABEL_SEPARATOR = 0;
+ENDPROC;
+
+PROCEDURE DO_DEVICE_INFO USES GV,READ_FSN,DO_EXIT,DUMP_SECURITY_INFO,DO_READ_SECURITY
+    ,PRINT_IDCODE,DUMP_PROG_INFO,DO_READ_DESIGN_INFO,DO_READ_PROG_INFO;
+    CALL PRINT_IDCODE;
+    IRSCAN 8, $8f, CAPTURE BUFF32[7..0];
+    IF ( ! (BUFF32[2]==1) ) THEN GOTO CORE_NOT_ENABLED;
+    PRINT "FPGA Array is programmed and enabled.";
+    CORE_NOT_ENABLED:
+    IF ( ! (BUFF32[2]==0) ) THEN GOTO CORE_ENABLED;
+    PRINT "FPGA Array is not enabled.";
+    CORE_ENABLED:
+    CALL DO_READ_DESIGN_INFO;
+    CALL DO_READ_PROG_INFO;
+    CALL DUMP_PROG_INFO;
+    CALL READ_FSN;
+    IF ( ! (READ_FSN_RESULT[128]==1) ) THEN GOTO FSN_NOT_BUSY;
+    CALL DO_EXIT;
+    FSN_NOT_BUSY:
+    CALL DO_READ_SECURITY;
+    CALL DUMP_SECURITY_INFO;
+ENDPROC;
+
+
+CRC D6F9;
diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo/.cproject b/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo/.cproject
new file mode 100644
index 000000000..f15a8a386
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo/.cproject
@@ -0,0 +1,451 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<?fileVersion 4.0.0?>
+
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+<externalSettings/>
+<extensions>
+<extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
+<extension id="org.eclipse.cdt.core.MakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
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+</extensions>
+</storageModule>
+<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+<configuration artifactName="RTOSDemo" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug,org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe" cleanCommand="rm -rf" description="" id="cdt.managedbuild.config.gnu.cross.cortexm3.exe.debug.437611960" name="Debug" parent="cdt.managedbuild.config.gnu.cross.cortexm3.exe.debug">
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+<listOptionValue builtIn="false" value="${workspace_loc:/RTOSDemo_Hardware_Platform/drivers/mss_gpio}"/>
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diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo/.project b/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo/.project
new file mode 100644
index 000000000..db74fca93
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo/.project
@@ -0,0 +1,81 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>RTOSDemo</name>
+	<comment></comment>
+	<projects>
+        <project> RTOSDemo_Hardware_Platform </project>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<arguments>
+				<dictionary>
+					<key>?name?</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.append_environment</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.autoBuildTarget</key>
+					<value>all</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildArguments</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildCommand</key>
+					<value>make</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildLocation</key>
+					<value>${workspace_loc:/RTOSDemo/Debug}</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.cleanBuildTarget</key>
+					<value>clean</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.contents</key>
+					<value>org.eclipse.cdt.make.core.activeConfigSettings</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableAutoBuild</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableCleanBuild</key>
+					<value>true</value>
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+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableFullBuild</key>
+					<value>true</value>
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+					<key>org.eclipse.cdt.make.core.fullBuildTarget</key>
+					<value>all</value>
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+					<key>org.eclipse.cdt.make.core.stopOnError</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>
+					<value>true</value>
+				</dictionary>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
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diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo/main.c b/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo/main.c
new file mode 100644
index 000000000..6eca2d8d4
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo/main.c
@@ -0,0 +1,71 @@
+/*******************************************************************************
+ * (c) Copyright 2009-2013 Microsemi SoC Products Group.  All rights reserved.
+ *
+ * Simple SmartFusion2 microcontroller subsystem (MSS) GPIO example program.
+ *
+ * Please refer to the file README.txt for further details about this example.
+ *
+ * SVN $Revision: 5491 $
+ * SVN $Date: 2013-03-29 16:00:31 +0000 (Fri, 29 Mar 2013) $
+ */
+#include "drivers/mss_gpio/mss_gpio.h"
+#include "CMSIS/system_m2sxxx.h"
+
+/*==============================================================================
+  Private functions.
+ */
+static void delay(void);
+
+/*==============================================================================
+ * main() function.
+ */
+int main()
+{
+    /*
+     * Initialize MSS GPIOs.
+     */
+    MSS_GPIO_init();
+    
+    /*
+     * Configure MSS GPIOs.
+     */
+    MSS_GPIO_config( MSS_GPIO_0 , MSS_GPIO_OUTPUT_MODE );
+    MSS_GPIO_config( MSS_GPIO_1 , MSS_GPIO_OUTPUT_MODE );
+    MSS_GPIO_config( MSS_GPIO_2 , MSS_GPIO_OUTPUT_MODE );
+    MSS_GPIO_config( MSS_GPIO_3 , MSS_GPIO_OUTPUT_MODE );
+    
+    /*
+     * Infinite loop.
+     */
+    for(;;)
+    {
+        uint32_t gpio_pattern;
+        /*
+         * Decrement delay counter.
+         */
+        delay();
+        
+        /*
+         * Toggle GPIO output pattern by doing an exclusive OR of all
+         * pattern bits with ones.
+         */
+        gpio_pattern = MSS_GPIO_get_outputs();
+        gpio_pattern ^= 0xFFFFFFFF;
+        MSS_GPIO_set_outputs( gpio_pattern );
+    }
+    
+    return 0;
+}
+
+/*==============================================================================
+  Delay between displays of the watchdog counter value.
+ */
+static void delay(void)
+{
+    volatile uint32_t delay_count = SystemCoreClock / 512;
+    
+    while(delay_count > 0u)
+    {
+        --delay_count;
+    }
+}
diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/.cproject b/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/.cproject
new file mode 100644
index 000000000..f70f5c9e6
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/.cproject
@@ -0,0 +1,320 @@
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+</profile>
+</scannerConfigBuildInfo>
+</storageModule>
+<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
+<storageModule moduleId="org.eclipse.cdt.internal.ui.text.commentOwnerProjectMappings"/>
+<storageModule moduleId="org.eclipse.cdt.core.language.mapping"/>
+</cconfiguration>
+</storageModule>
+<storageModule moduleId="cdtBuildSystem" version="4.0.0">
+<project id="RTOSDemo_Hardware_Platform.cdt.managedbuild.target.gnu.cross.cortexm3.lib.597503304" name="Static Library" projectType="cdt.managedbuild.target.gnu.cross.cortexm3.lib"/>
+</storageModule>
+</cproject>
diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/.project b/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/.project
new file mode 100644
index 000000000..876bbbc2a
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/.project
@@ -0,0 +1,80 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<projectDescription>
+	<name>RTOSDemo_Hardware_Platform</name>
+	<comment></comment>
+	<projects>
+	</projects>
+	<buildSpec>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
+			<arguments>
+				<dictionary>
+					<key>?name?</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.append_environment</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.autoBuildTarget</key>
+					<value>all</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildArguments</key>
+					<value></value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildCommand</key>
+					<value>make</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.buildLocation</key>
+					<value>${workspace_loc:/RTOSDemo_Hardware_Platform/Debug}</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.cleanBuildTarget</key>
+					<value>clean</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.contents</key>
+					<value>org.eclipse.cdt.make.core.activeConfigSettings</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableAutoBuild</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableCleanBuild</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.enableFullBuild</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.fullBuildTarget</key>
+					<value>all</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.stopOnError</key>
+					<value>true</value>
+				</dictionary>
+				<dictionary>
+					<key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>
+					<value>true</value>
+				</dictionary>
+			</arguments>
+		</buildCommand>
+		<buildCommand>
+			<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
+			<arguments>
+			</arguments>
+		</buildCommand>
+	</buildSpec>
+	<natures>
+		<nature>org.eclipse.cdt.core.cnature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
+		<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
+	</natures>
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diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/CMSIS/hw_reg_io.h b/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/CMSIS/hw_reg_io.h
new file mode 100644
index 000000000..e6ff7c1d3
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/CMSIS/hw_reg_io.h
@@ -0,0 +1,113 @@
+/*******************************************************************************
+ * (c) Copyright 2011-2013 Microsemi SoC Products Group. All rights reserved.
+ *
+ *  SmartFusion2 Cortex Microcontroller Software Interface - Peripheral
+ *  Access Layer.
+ *
+ *  This file provides interfaces to perform register and register bit level 
+ *  read / write operations. These interfaces support bit-banding in case of 
+ *  Cortex-M3 CPU.
+ *
+ * SVN $Revision: 5263 $
+ * SVN $Date: 2013-03-21 14:44:58 +0000 (Thu, 21 Mar 2013) $
+ */
+
+#ifndef HW_REG_IO_H_
+#define HW_REG_IO_H_
+
+#include <stdint.h>                       /* Include standard types */
+
+#if defined ( __CC_ARM   )
+  #define __INLINE         __inline       /*!< inline keyword for ARM Compiler       */
+
+#elif defined ( __ICCARM__ )
+  #define __INLINE        inline          /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
+
+#elif defined   (  __GNUC__  )
+  #define __INLINE        inline          /*!< inline keyword for GNU Compiler       */
+#endif
+
+/*****************************************************************************************
+ * Definitions for register access
+ */
+
+#define HW_REG(addr)            (*((volatile uint32_t *) (addr)))
+
+static __INLINE void write_reg32(volatile uint32_t * reg, uint32_t val)
+{
+    HW_REG(reg) = val;
+}
+static __INLINE void write_reg16(volatile uint16_t * reg, uint16_t val)
+{
+    HW_REG(reg) = val;
+}
+static __INLINE void write_reg8(volatile uint8_t * reg, uint8_t val)
+{
+    HW_REG(reg) = val;
+}
+
+static __INLINE uint32_t read_reg32(volatile uint32_t * reg)
+{
+    return ( HW_REG(reg) );
+}
+static __INLINE uint16_t read_reg16(volatile uint16_t * reg)
+{
+    return ( HW_REG(reg) );
+}
+static __INLINE uint8_t read_reg8(volatile uint8_t * reg)
+{
+    return ( HW_REG(reg) );
+}
+/*****************************************************************************************
+ * Definitions for register bits access using bit-band aliases for Cortex-M3 
+ */
+#define BITBAND(addr,bitnum)    (((uint32_t)addr & 0xF0000000)+0x02000000+(((uint32_t)addr & 0xFFFFF)<<5)+(bitnum<<2))
+#define HW_REG_BIT(reg,bitnum)  (*(volatile unsigned int *)((BITBAND(reg,bitnum))))
+
+/*****************************************************************************************
+ * Functions to set a bit field in Cortex-M3 
+ */
+static __INLINE void set_bit_reg32(volatile uint32_t * reg, uint8_t bit)
+{
+    HW_REG_BIT(reg,bit) = 0x1;
+}
+static __INLINE void set_bit_reg16(volatile uint16_t * reg, uint8_t bit)
+{
+    HW_REG_BIT(reg,bit) = 0x1;
+}
+static __INLINE void set_bit_reg8(volatile uint8_t * reg, uint8_t bit)
+{
+    HW_REG_BIT(reg,bit) = 0x1;
+}
+/*****************************************************************************************
+ * Functions to clear a bit field in Cortex-M3
+ */
+static __INLINE void clear_bit_reg32(volatile uint32_t * reg, uint8_t bit)
+{
+    HW_REG_BIT(reg,bit) = 0x0;
+}
+static __INLINE void clear_bit_reg16(volatile uint16_t * reg, uint8_t bit)
+{
+    HW_REG_BIT(reg,bit) = 0x0;
+}
+static __INLINE void clear_bit_reg8(volatile uint8_t * reg, uint8_t bit)
+{
+    HW_REG_BIT(reg,bit) = 0x0;
+}
+/*****************************************************************************************
+ * Functions to read a bit field in Cortex-M3
+ */
+static __INLINE uint8_t read_bit_reg32(volatile uint32_t * reg, uint8_t bit)
+{
+    return (HW_REG_BIT(reg,bit));
+}
+static __INLINE uint8_t read_bit_reg16(volatile uint16_t * reg, uint8_t bit)
+{
+    return (HW_REG_BIT(reg,bit));
+}
+static __INLINE uint8_t read_bit_reg8(volatile uint8_t * reg, uint8_t bit)
+{
+    return (HW_REG_BIT(reg,bit));
+}
+
+#endif /* HW_REG_IO_H_ */
diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/CMSIS/m2sxxx.h b/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/CMSIS/m2sxxx.h
new file mode 100644
index 000000000..c2cd72b22
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/CMSIS/m2sxxx.h
@@ -0,0 +1,2749 @@
+/*******************************************************************************
+ * (c) Copyright 2010-2013 Microsemi SoC Products Group. All rights reserved.
+ *
+ *  Microsemi SmartFusion2 Cortex Microcontroller Software Interface - Peripheral
+ *  Access Layer.
+ *
+ *  This file describes the interrupt assignment and peripheral registers for
+ *  the SmartFusion2 familly of devices.
+ *
+ * SVN $Revision: 5267 $
+ * SVN $Date: 2013-03-21 20:45:39 +0000 (Thu, 21 Mar 2013) $
+ */
+#ifndef __SMARTFUSION2_CMSIS_PAL_H__
+#define __SMARTFUSION2_CMSIS_PAL_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * ==========================================================================
+ * ---------- Interrupt Number Definition -----------------------------------
+ * ==========================================================================
+ */
+
+typedef enum IRQn
+{
+/******  Cortex-M3 Processor Exceptions Numbers *********************************************************/
+  NonMaskableInt_IRQn             = -14,      /*!< 2 Non Maskable Interrupt - Watchdog timeout interrupt*/
+  HardFault_IRQn                  = -13,      /*!< 2 Hard Fault Interrupt                               */
+  MemoryManagement_IRQn           = -12,      /*!< 4 Cortex-M3 Memory Management Interrupt              */
+  BusFault_IRQn                   = -11,      /*!< 5 Cortex-M3 Bus Fault Interrupt                      */
+  UsageFault_IRQn                 = -10,      /*!< 6 Cortex-M3 Usage Fault Interrupt                    */
+  SVCall_IRQn                     = -5,       /*!< 11 Cortex-M3 SV Call Interrupt                       */
+  DebugMonitor_IRQn               = -4,       /*!< 12 Cortex-M3 Debug Monitor Interrupt                 */
+  PendSV_IRQn                     = -2,       /*!< 14 Cortex-M3 Pend SV Interrupt                       */
+  SysTick_IRQn                    = -1,       /*!< 15 Cortex-M3 System Tick Interrupt                   */
+
+/******  SmartFusion2 specific Interrupt Numbers *********************************************************/
+  WdogWakeup_IRQn                 = 0,        /*!< WatchDog wakeup interrupt                            */
+  RTC_Wakeup_IRQn                 = 1,        /*!< RTC wakeup interrupt                                 */
+  SPI0_IRQn                       = 2,        /*!< SPI0 interrupt                                       */
+  SPI1_IRQn                       = 3,        /*!< SPI1 interrupt                                       */
+  I2C0_IRQn                       = 4,        /*!< I2C0 interrupt                                       */
+  I2C0_SMBAlert_IRQn              = 5,        /*!< I2C0 SMBus Alert interrupt                           */
+  I2C0_SMBus_IRQn                 = 6,        /*!< I2C0 SMBus Suspend interrupt                         */
+  I2C1_IRQn                       = 7,        /*!< I2C1 interrupt                                       */
+  I2C1_SMBAlert_IRQn              = 8,        /*!< I2C1 SMBus Alert interrupt                           */
+  I2C1_SMBus_IRQn                 = 9,        /*!< I2C1 SMBus Suspend interrupt                         */
+  UART0_IRQn                      = 10,       /*!< UART0 interrupt                                      */
+  UART1_IRQn                      = 11,       /*!< UART1 interrupt                                      */
+  EthernetMAC_IRQn                = 12,       /*!< Ethernet MAC interrupt                               */
+  DMA_IRQn                        = 13,       /*!< Peripheral DMA interrupt                             */
+  Timer1_IRQn                     = 14,       /*!< Timer1 interrupt                                     */
+  Timer2_IRQn                     = 15,       /*!< Timer2 interrupt                                     */
+  CAN_IRQn                        = 16,       /*!< CAN controller interrupt                             */
+  ENVM0_IRQn                      = 17,       /*!< eNVM0 operation completion interrupt                 */
+  ENVM1_IRQn                      = 18,       /*!< eNVM1 operation completion interrupt                 */
+  ComBlk_IRQn                     = 19,       /*!< COM block interrupt                                  */
+  USB_IRQn                        = 20,       /*!< USB interrupt                                        */
+  USB_DMA_IRQn                    = 21,       /*!< USB DMA interrupt                                    */
+  PLL_Lock_IRQn                   = 22,       /*!< PLL lock interrupt                                   */
+  PLL_LockLost_IRQn               = 23,       /*!< PLL loss of lock interrupt                           */
+  CommSwitchError_IR              = 24,       /*!< Communications Switch error interrupt                */
+  CacheError_IRQn                 = 25,       /*!< Cache error interrupt                                */
+  DDR_IRQn                        = 26,       /*!< DDR controller interrupt                             */
+  HPDMA_Complete_IRQn             = 27,       /*!< High speed DMA transfer complete interrupt           */
+  HPDMA_Error_IRQn                = 28,       /*!< High speed DMA transfer error interrupt              */
+  ECC_Error_IRQn                  = 29,       /*!< ECC error detected                                   */
+  MDDR_IOCalib_IRQn               = 30,       /*!< MDDR Calibration finished interrupt                  */
+  FAB_PLL_Lock_IRQn               = 31,       /*!< MSSDDR Fabric PLL lock interrupt                   */
+  FAB_PLL_LockLost_IRQn           = 32,       /*!< MSSDDR Fabric PLL lock lost interrupt              */
+  FIC64_IRQn                      = 33,       /*!< FIC64 interrupt                                      */
+  FabricIrq0_IRQn                 = 34,       /*!< FPGA fabric interrupt 0                              */
+  FabricIrq1_IRQn                 = 35,       /*!< FPGA fabric interrupt 1                              */
+  FabricIrq2_IRQn                 = 36,       /*!< FPGA fabric interrupt 2                              */
+  FabricIrq3_IRQn                 = 37,       /*!< FPGA fabric interrupt 3                              */
+  FabricIrq4_IRQn                 = 38,       /*!< FPGA fabric interrupt 4                              */
+  FabricIrq5_IRQn                 = 39,       /*!< FPGA fabric interrupt 5                              */
+  FabricIrq6_IRQn                 = 40,       /*!< FPGA fabric interrupt 6                              */
+  FabricIrq7_IRQn                 = 41,       /*!< FPGA fabric interrupt 7                              */
+  FabricIrq8_IRQn                 = 42,       /*!< FPGA fabric interrupt 8                              */
+  FabricIrq9_IRQn                 = 43,       /*!< FPGA fabric interrupt 9                              */
+  FabricIrq10_IRQn                = 44,       /*!< FPGA fabric interrupt 10                             */
+  FabricIrq11_IRQn                = 45,       /*!< FPGA fabric interrupt 11                             */
+  FabricIrq12_IRQn                = 46,       /*!< FPGA fabric interrupt 12                             */
+  FabricIrq13_IRQn                = 47,       /*!< FPGA fabric interrupt 13                             */
+  FabricIrq14_IRQn                = 48,       /*!< FPGA fabric interrupt 14                             */
+  FabricIrq15_IRQn                = 49,       /*!< FPGA fabric interrupt 15                             */  
+  GPIO0_IRQn                      = 50,       /*!< GPIO 0 interrupt                                     */
+  GPIO1_IRQn                      = 51,       /*!< GPIO 1 interrupt                                     */
+  GPIO2_IRQn                      = 52,       /*!< GPIO 2 interrupt                                     */
+  GPIO3_IRQn                      = 53,       /*!< GPIO 3 interrupt                                     */
+  GPIO4_IRQn                      = 54,       /*!< GPIO 4 interrupt                                     */
+  GPIO5_IRQn                      = 55,       /*!< GPIO 5 interrupt                                     */
+  GPIO6_IRQn                      = 56,       /*!< GPIO 6 interrupt                                     */
+  GPIO7_IRQn                      = 57,       /*!< GPIO 7 interrupt                                     */
+  GPIO8_IRQn                      = 58,       /*!< GPIO 8 interrupt                                     */
+  GPIO9_IRQn                      = 59,       /*!< GPIO 9 interrupt                                     */
+  GPIO10_IRQn                     = 60,       /*!< GPIO 10 interrupt                                    */
+  GPIO11_IRQn                     = 61,       /*!< GPIO 11 interrupt                                    */
+  GPIO12_IRQn                     = 62,       /*!< GPIO 12 interrupt                                    */
+  GPIO13_IRQn                     = 63,       /*!< GPIO 13 interrupt                                    */
+  GPIO14_IRQn                     = 64,       /*!< GPIO 14 interrupt                                    */
+  GPIO15_IRQn                     = 65,       /*!< GPIO 15 interrupt                                    */
+  GPIO16_IRQn                     = 66,       /*!< GPIO 16 interrupt                                    */
+  GPIO17_IRQn                     = 67,       /*!< GPIO 17 interrupt                                    */
+  GPIO18_IRQn                     = 68,       /*!< GPIO 18 interrupt                                    */
+  GPIO19_IRQn                     = 69,       /*!< GPIO 19 interrupt                                    */
+  GPIO20_IRQn                     = 70,       /*!< GPIO 20 interrupt                                    */
+  GPIO21_IRQn                     = 71,       /*!< GPIO 21 interrupt                                    */
+  GPIO22_IRQn                     = 72,       /*!< GPIO 22 interrupt                                    */
+  GPIO23_IRQn                     = 73,       /*!< GPIO 23 interrupt                                    */
+  GPIO24_IRQn                     = 74,       /*!< GPIO 24 interrupt                                    */
+  GPIO25_IRQn                     = 75,       /*!< GPIO 25 interrupt                                    */ 
+  GPIO26_IRQn                     = 76,       /*!< GPIO 26 interrupt                                    */
+  GPIO27_IRQn                     = 77,       /*!< GPIO 27 interrupt                                    */
+  GPIO28_IRQn                     = 78,       /*!< GPIO 28 interrupt                                    */
+  GPIO29_IRQn                     = 79,       /*!< GPIO 29 interrupt                                    */
+  GPIO30_IRQn                     = 80,       /*!< GPIO 30 interrupt                                    */
+  GPIO31_IRQn                     = 81        /*!< GPIO 31 interrupt                                    */
+} IRQn_Type;
+
+/*
+ * ==========================================================================
+ * ----------- Processor and Core Peripheral Section ------------------------
+ * ==========================================================================
+ */
+#define __CM3_REV                 0x0201    /*!< Core revision r2p1                              */
+#define __MPU_PRESENT             1         /*!< MPU present or not                              */
+#define __NVIC_PRIO_BITS          4         /*!< Number of Bits used for Priority Levels         */
+#define __Vendor_SysTickConfig    0         /*!< Set to 1 if different SysTick Config is used    */
+
+#include <core_cm3.h>   /* Cortex-M3 processor and core peripherals           */
+
+/******************************************************************************/
+/*                Device Specific Peripheral registers structures             */
+/******************************************************************************/
+#if defined   ( __CC_ARM   )
+  /* Enable anonymous unions when building using Keil-MDK */
+  #pragma anon_unions
+#endif
+
+/*----------------------------------------------------------------------------*/
+/*----------------------------------- UART -----------------------------------*/
+/*----------------------------------------------------------------------------*/
+typedef struct
+{
+    union
+    {
+        __I  uint8_t    RBR;
+        __O  uint8_t    THR;
+        __IO uint8_t    DLR;
+             uint32_t   RESERVED0;
+    };
+
+    union
+    {
+        __IO uint8_t  DMR;
+        __IO uint8_t  IER;
+             uint32_t RESERVED1;
+    };
+
+    union
+    {
+        __IO uint8_t  IIR;
+        __IO uint8_t  FCR;
+             uint32_t RESERVED2;
+    };
+
+    __IO uint8_t  LCR;
+         uint8_t  RESERVED3[3];
+
+    __IO uint8_t  MCR;
+         uint8_t  RESERVED4[3];
+
+    __I  uint8_t  LSR;
+         uint8_t  RESERVED5[3];
+
+    __I  uint8_t  MSR;
+         uint8_t  RESERVED6[3];
+
+    __IO uint8_t  SR;
+         uint8_t  RESERVED7[7];
+
+    __IO uint8_t  IEM;
+         uint8_t  RESERVED8[3];
+
+    __IO uint8_t  IIM;
+         uint8_t  RESERVED9[7];
+
+    __IO uint8_t  MM0;
+         uint8_t  RESERVED10[3];
+
+    __IO uint8_t  MM1;
+         uint8_t  RESERVED11[3];
+
+    __IO uint8_t  MM2;
+         uint8_t  RESERVED12[3];
+
+    __IO uint8_t  DFR;
+         uint8_t  RESERVED13[7];
+
+     __IO uint8_t GFR;
+         uint8_t  RESERVED14[3];
+
+     __IO uint8_t TTG;
+         uint8_t  RESERVED15[3];
+
+     __IO uint8_t RTO;
+         uint8_t  RESERVED16[3];
+
+     __IO uint8_t ADR;
+         uint8_t  RESERVED17[3];
+
+} UART_TypeDef;
+
+/*----------------------------------------------------------------------------*/
+/*----------------------------------- I2C ------------------------------------*/
+/*----------------------------------------------------------------------------*/
+typedef struct
+{
+    __IO uint8_t  CTRL;
+         uint8_t  RESERVED0;
+         uint16_t RESERVED1;
+         uint8_t  STATUS;
+         uint8_t  RESERVED2;
+         uint16_t RESERVED3;
+    __IO uint8_t  DATA;
+         uint8_t  RESERVED4;
+         uint16_t RESERVED5;
+    __IO uint8_t  ADDR;
+         uint8_t  RESERVED6;
+         uint16_t RESERVED7;
+    __IO uint8_t  SMBUS;
+         uint8_t  RESERVED8;
+         uint16_t RESERVED9;
+    __IO uint8_t  FREQ;
+         uint8_t  RESERVED10;
+         uint16_t RESERVED11;
+    __IO uint8_t  GLITCHREG;
+         uint8_t  RESERVED12;
+         uint16_t RESERVED13;
+    __IO uint8_t  SLAVE1_ADDR;
+         uint8_t  RESERVED14;
+         uint16_t RESERVED15;
+} I2C_TypeDef;
+
+/*------------------------------------------------------------------------------
+ * I2C bit band
+ */
+typedef struct
+{
+    __IO uint32_t CTRL_CR0;
+    __IO uint32_t CTRL_CR1;
+    __IO uint32_t CTRL_AA;
+    __IO uint32_t CTRL_SI;
+    __IO uint32_t CTRL_STO;
+    __IO uint32_t CTRL_STA;
+    __IO uint32_t CTRL_ENS1;
+    __IO uint32_t CTRL_CR2;
+         uint32_t RESERVED0[56];
+    __IO uint32_t DATA_DIR;
+         uint32_t RESERVED1[31];
+    __IO uint32_t ADDR_GC;
+} I2C_BitBand_TypeDef;
+
+/*----------------------------------------------------------------------------*/
+/*----------------------------------- SPI ------------------------------------*/
+/*----------------------------------------------------------------------------*/
+typedef struct
+{
+    __IO uint32_t CONTROL;
+    __IO uint32_t TXRXDF_SIZE;
+    __I  uint32_t STATUS;
+    __O  uint32_t INT_CLEAR;
+    __I  uint32_t RX_DATA;
+    __O  uint32_t TX_DATA;
+    __IO uint32_t CLK_GEN;
+    __IO uint32_t SLAVE_SELECT;
+    __I  uint32_t MIS;
+    __I  uint32_t RIS;
+    __IO uint32_t CONTROL2;
+    __IO uint32_t COMMAND;
+    __IO uint32_t PKTSIZE;
+    __IO uint32_t CMDSIZE;
+    __IO uint32_t HWSTATUS;
+    __IO uint32_t STAT8;
+    __IO uint32_t CTRL0;
+    __IO uint32_t CTRL1;
+    __IO uint32_t CTRL2;
+    __IO uint32_t CTRL3;
+} SPI_TypeDef;
+
+/*----------------------------------------------------------------------------*/
+/*----------------------------------- GPIO -----------------------------------*/
+/*----------------------------------------------------------------------------*/
+typedef struct
+{
+    __IO uint32_t GPIO_0_CFG;
+    __IO uint32_t GPIO_1_CFG;
+    __IO uint32_t GPIO_2_CFG;
+    __IO uint32_t GPIO_3_CFG;
+    __IO uint32_t GPIO_4_CFG;
+    __IO uint32_t GPIO_5_CFG;
+    __IO uint32_t GPIO_6_CFG;
+    __IO uint32_t GPIO_7_CFG;
+    __IO uint32_t GPIO_8_CFG;
+    __IO uint32_t GPIO_9_CFG;
+    __IO uint32_t GPIO_10_CFG;
+    __IO uint32_t GPIO_11_CFG;
+    __IO uint32_t GPIO_12_CFG;
+    __IO uint32_t GPIO_13_CFG;
+    __IO uint32_t GPIO_14_CFG;
+    __IO uint32_t GPIO_15_CFG;
+    __IO uint32_t GPIO_16_CFG;
+    __IO uint32_t GPIO_17_CFG;
+    __IO uint32_t GPIO_18_CFG;
+    __IO uint32_t GPIO_19_CFG;
+    __IO uint32_t GPIO_20_CFG;
+    __IO uint32_t GPIO_21_CFG;
+    __IO uint32_t GPIO_22_CFG;
+    __IO uint32_t GPIO_23_CFG;
+    __IO uint32_t GPIO_24_CFG;
+    __IO uint32_t GPIO_25_CFG;
+    __IO uint32_t GPIO_26_CFG;
+    __IO uint32_t GPIO_27_CFG;
+    __IO uint32_t GPIO_28_CFG;
+    __IO uint32_t GPIO_29_CFG;
+    __IO uint32_t GPIO_30_CFG;
+    __IO uint32_t GPIO_31_CFG;
+    __IO uint32_t GPIO_IRQ;
+    __I  uint32_t GPIO_IN;
+    __IO uint32_t GPIO_OUT;
+} GPIO_TypeDef;
+
+/*------------------------------------------------------------------------------
+ * GPIO bit band
+ */
+typedef struct
+{
+    __IO uint32_t GPIO_0_CFG[32];
+    __IO uint32_t GPIO_1_CFG[32];
+    __IO uint32_t GPIO_2_CFG[32];
+    __IO uint32_t GPIO_3_CFG[32];
+    __IO uint32_t GPIO_4_CFG[32];
+    __IO uint32_t GPIO_5_CFG[32];
+    __IO uint32_t GPIO_6_CFG[32];
+    __IO uint32_t GPIO_7_CFG[32];
+    __IO uint32_t GPIO_8_CFG[32];
+    __IO uint32_t GPIO_9_CFG[32];
+    __IO uint32_t GPIO_10_CFG[32];
+    __IO uint32_t GPIO_11_CFG[32];
+    __IO uint32_t GPIO_12_CFG[32];
+    __IO uint32_t GPIO_13_CFG[32];
+    __IO uint32_t GPIO_14_CFG[32];
+    __IO uint32_t GPIO_15_CFG[32];
+    __IO uint32_t GPIO_16_CFG[32];
+    __IO uint32_t GPIO_17_CFG[32];
+    __IO uint32_t GPIO_18_CFG[32];
+    __IO uint32_t GPIO_19_CFG[32];
+    __IO uint32_t GPIO_20_CFG[32];
+    __IO uint32_t GPIO_21_CFG[32];
+    __IO uint32_t GPIO_22_CFG[32];
+    __IO uint32_t GPIO_23_CFG[32];
+    __IO uint32_t GPIO_24_CFG[32];
+    __IO uint32_t GPIO_25_CFG[32];
+    __IO uint32_t GPIO_26_CFG[32];
+    __IO uint32_t GPIO_27_CFG[32];
+    __IO uint32_t GPIO_28_CFG[32];
+    __IO uint32_t GPIO_29_CFG[32];
+    __IO uint32_t GPIO_30_CFG[32];
+    __IO uint32_t GPIO_31_CFG[32];
+    __IO uint32_t GPIO_IRQ[32];
+    __I  uint32_t GPIO_IN[32];
+    __IO uint32_t GPIO_OUT[32];
+} GPIO_BitBand_TypeDef;
+
+
+/*----------------------------------------------------------------------------*/
+/*--------------------------------- HPDMA ------------------------------------*/
+/*----------------------------------------------------------------------------*/
+
+typedef struct
+{
+    __IO uint32_t HPDMASAR_REG              ;
+    __IO uint32_t HPDMADAR_REG              ;
+    __IO uint32_t HPDMACR_REG               ;
+    __I  uint32_t HPDMASR_REG               ;
+    __I  uint32_t HPDMAPTR_REG              ;
+}HPDMA_Descriptor_TypeDef;
+
+typedef struct
+{
+    __I  uint32_t HPDMAEDR_REG              ;
+    HPDMA_Descriptor_TypeDef  Descriptor[4] ;
+    __O  uint32_t HPDMAICR_REG              ;
+    __I  uint32_t HPDMADR_REG               ;
+} HPDMA_TypeDef;
+
+typedef struct
+{
+         uint32_t RESERVED0[64];
+    __IO uint32_t HPDMACR_XFR_SIZE[16]     ;
+    __IO uint32_t HPDMACR_DCP_VALID        ;
+    __IO uint32_t HPDMACR_DCP_XFR_DIR      ;
+    __IO uint32_t HPDMACR_DCP_CLR          ;
+    __IO uint32_t HPDMACR_DCP_PAUSE        ;
+    __IO uint32_t HPDMACR_XFR_CMP_INT      ;
+    __IO uint32_t HPDMACR_XFR_ERR_INT      ;
+    __IO uint32_t HPDMACR_NON_WORD_INT     ;
+         uint32_t RESERVED1[9];
+
+    __I  uint32_t HPDMASR_DCP_ACTIVE       ;
+    __I  uint32_t HPDMASR_DCP_CMPLET       ;
+    __I  uint32_t HPDMASR_DCP_SERR         ;
+    __I  uint32_t HPDMASR_DCP_DERR         ;
+         uint32_t RESERVED2[60]            ;
+}HPDMA_Descriptor_BitBand_TypeDef;
+
+/*------------------------------------------------------------------------------
+ * HPDMA bit band
+ */
+typedef struct
+{
+    __I  uint32_t HPDMAEDR_DCP_EMPTY[4]           ;
+    __I  uint32_t HPDMAEDR_DCP_CMPLET[4]          ;
+    __I  uint32_t HPDMAEDR_DCP_ERR[4]             ;
+    __I  uint32_t HPDMAEDR_DCP_NON_WORD_ERR[4]    ;
+         uint32_t RESERVED0[16]                   ;
+
+    HPDMA_Descriptor_BitBand_TypeDef Descriptor[4];
+
+    __O  uint32_t HPDMAICR_CLR_XFR_INT[4]         ;
+    __O  uint32_t HPDMAICR_NON_WORD_INT[4]        ;
+         uint32_t RESERVED1[16]                   ;
+
+    __I  uint32_t HPDMADR_BFR_EMPTY               ;
+    __I  uint32_t HPDMADR_BFR_FULL                ;
+    __I  uint32_t HPDMADR_BFR_RD_PNTR[3]          ;
+    __I  uint32_t HPDMADR_BFR_WR_PNTR [3]         ;
+    __I  uint32_t HPDMADR_AHM1_CST_DBG[4]         ;
+    __I  uint32_t HPDMADR_AHM2_CST_DBG[4]         ;
+    __I  uint32_t HPDMADR_WBC_CST_DBG[3]          ;
+    __I  uint32_t HPDMADR_RBC_CST_DBG[3]          ;
+    __I  uint32_t HPDMADR_RRBN_CST_DBG[4]         ;
+    __I  uint32_t HPDMADR_DMA_CST_DBG[4]          ;
+
+         uint32_t RESERVED2[4]                    ;
+}HPDMA_BitBand_TypeDef;
+
+/*----------------------------------------------------------------------------*/
+/*----------------------------------- RTC ------------------------------------*/
+/*----------------------------------------------------------------------------*/
+typedef struct
+{
+    __IO uint32_t CONTROL_REG             ;
+    __IO uint32_t MODE_REG                ;
+    __IO uint32_t PRESCALER_REG           ;
+    __IO uint32_t ALARM_LOWER_REG         ;
+    __IO uint32_t ALARM_UPPER_REG         ;
+    __IO uint32_t COMPARE_LOWER_REG       ;
+    __IO uint32_t COMPARE_UPPER_REG       ;
+         uint32_t RESERVED0               ;
+    __IO uint32_t DATE_TIME_LOWER_REG     ;
+    __IO uint32_t DATE_TIME_UPPER_REG     ;
+
+         uint32_t RESERVED1[2]            ;
+    __IO uint32_t SECONDS_REG             ;
+    __IO uint32_t MINUTES_REG             ;
+    __IO uint32_t HOURS_REG               ;
+    __IO uint32_t DAY_REG                 ;
+    __IO uint32_t MONTH_REG               ;
+    __IO uint32_t YEAR_REG                ;
+    __IO uint32_t WEEKDAY_REG             ;
+    __IO uint32_t WEEK_REG                ;
+
+    __IO uint32_t SECONDS_CNT_REG         ;
+    __IO uint32_t MINUTES_CNT_REG         ;
+    __IO uint32_t HOURS_CNT_REG           ;
+    __IO uint32_t DAY_CNT_REG             ;
+    __IO uint32_t MONTH_CNT_REG           ;
+    __IO uint32_t YEAR_CNT_REG            ;
+    __IO uint32_t WEEKDAY_CNT_REG         ;
+    __IO uint32_t WEEK_CNT_REG            ;
+} RTC_TypeDef;
+
+/*----------------------------------------------------------------------------*/
+/*---------------------------------- Timer -----------------------------------*/
+/*----------------------------------------------------------------------------*/
+typedef struct
+{
+    __I  uint32_t TIM1_VAL;
+    __IO uint32_t TIM1_LOADVAL;
+    __IO uint32_t TIM1_BGLOADVAL;
+    __IO uint32_t TIM1_CTRL;
+    __IO uint32_t TIM1_RIS;
+    __I  uint32_t TIM1_MIS;
+
+    __I  uint32_t TIM2_VAL;
+    __IO uint32_t TIM2_LOADVAL;
+    __IO uint32_t TIM2_BGLOADVAL;
+    __IO uint32_t TIM2_CTRL;
+    __IO uint32_t TIM2_RIS;
+    __I  uint32_t TIM2_MIS;
+
+    __I  uint32_t TIM64_VAL_U;
+    __I  uint32_t TIM64_VAL_L;
+    __IO uint32_t TIM64_LOADVAL_U;
+    __IO uint32_t TIM64_LOADVAL_L;
+    __IO uint32_t TIM64_BGLOADVAL_U;
+    __IO uint32_t TIM64_BGLOADVAL_L;
+    __IO uint32_t TIM64_CTRL;
+    __IO uint32_t TIM64_RIS;
+    __I  uint32_t TIM64_MIS;
+    __IO uint32_t TIM64_MODE;
+} TIMER_TypeDef;
+
+/*------------------------------------------------------------------------------
+ * Timer bit band
+ */
+typedef struct
+{
+    __I  uint32_t TIM1_VALUE_BIT[32];
+    __IO uint32_t TIM1_LOADVAL[32];
+    __IO uint32_t TIM1_BGLOADVAL[32];
+
+    __IO uint32_t TIM1ENABLE;
+    __IO uint32_t TIM1MODE;
+    __IO uint32_t TIM1INTEN;
+    __IO uint32_t TIM1_CTRL_RESERVED[29];
+    __IO uint32_t TIM1_RIS[32];
+    __I  uint32_t TIM1_MIS[32];
+
+    __I  uint32_t TIM2_VALUE[32];
+    __IO uint32_t TIM2_LOADVAL[32];
+    __IO uint32_t TIM2_BGLOADVAL[32];
+
+    __IO uint32_t TIM2ENABLE;
+    __IO uint32_t TIM2MODE;
+    __IO uint32_t TIM2INTEN;
+    __IO uint32_t TIM2_CTRL[29];
+    __IO uint32_t TIM2_RIS[32];
+    __I  uint32_t TIM2_MIS[32];
+
+    __I  uint32_t TIM64VALUEU[32];
+    __I  uint32_t TIM64VALUEL[32];
+    __IO uint32_t TIM64LOADVALUEU[32];
+    __IO uint32_t TIM64LOADVALUEL[32];
+    __IO uint32_t TIM64BGLOADVALUEU[32];
+    __IO uint32_t TIM64BGLOADVALUEL[32];
+    __IO uint32_t TIM64ENABLE;
+    __IO uint32_t TIM64MODE;
+    __IO uint32_t TIM64INTEN;
+    __IO uint32_t TIM64_CTRL[29];
+    __IO uint32_t TIM64_RIS[32];
+    __I  uint32_t TIM64_MIS[32];
+    __IO uint32_t TIM64_MODE[32];
+} TIMER_BitBand_TypeDef;
+
+/*----------------------------------------------------------------------------*/
+/*--------------------------------- Watchdog ---------------------------------*/
+/*----------------------------------------------------------------------------*/
+typedef struct
+{
+    __I  uint32_t WDOGVALUE;
+    __I  uint32_t WDOGLOAD;
+    __I  uint32_t WDOGMVRP;
+    __O  uint32_t WDOGREFRESH;
+    __I  uint32_t WDOGENABLE;
+    __IO uint32_t WDOGCONTROL;
+    __I  uint32_t WDOGSTATUS;
+    __IO uint32_t WDOGRIS;
+    __I  uint32_t WDOGMIS;
+} WATCHDOG_TypeDef;
+
+/*----------------------------------------------------------------------------*/
+/*----------------------------- Real Time Clock ------------------------------*/
+/*----------------------------------------------------------------------------*/
+
+/*----------------------------------------------------------------------------*/
+/*----------------------------- Peripherals DMA ------------------------------*/
+/*----------------------------------------------------------------------------*/
+typedef struct
+{
+    __IO uint32_t CRTL;
+    __IO uint32_t STATUS;
+    __IO uint32_t BUFFER_A_SRC_ADDR;
+    __IO uint32_t BUFFER_A_DEST_ADDR;
+    __IO uint32_t BUFFER_A_TRANSFER_COUNT;
+    __IO uint32_t BUFFER_B_SRC_ADDR;
+    __IO uint32_t BUFFER_B_DEST_ADDR;
+    __IO uint32_t BUFFER_B_TRANSFER_COUNT;
+} PDMA_Channel_TypeDef;
+
+typedef struct
+{
+    __IO uint32_t RATIO_HIGH_LOW;
+    __IO uint32_t BUFFER_STATUS;
+         uint32_t RESERVED[6];
+    PDMA_Channel_TypeDef CHANNEL[8];
+} PDMA_TypeDef;
+
+/*----------------------------------------------------------------------------*/
+/*------------------------------ Ethernet MAC --------------------------------*/
+/*----------------------------------------------------------------------------*/
+typedef struct
+{
+	/* 
+     * MAC registers (MCXMAC)
+     */
+    __IO uint32_t CFG1;
+    __IO uint32_t CFG2;
+    __IO uint32_t IFG;
+    __IO uint32_t HALF_DUPLEX;
+    __IO uint32_t MAX_FRAME_LENGTH;
+         uint32_t RESERVED0[2];
+    __IO uint32_t TEST;
+    __IO uint32_t MII_CONFIG;
+    __IO uint32_t MII_COMMAND;
+    __IO uint32_t MII_ADDRESS;
+    __O  uint32_t MII_CTRL;
+    __I  uint32_t MII_STATUS;
+    __I  uint32_t MII_INDICATORS;
+    __IO uint32_t INTERFACE_CTRL;
+    __I  uint32_t INTERFACE_STATUS;
+    __IO uint32_t STATION_ADDRESS1;
+    __IO uint32_t STATION_ADDRESS2;
+    /* 
+     * FIFO Configuration / Access registers (MCXFIF)
+     */
+    __IO uint32_t FIFO_CFG0;
+    __IO uint32_t FIFO_CFG1;
+    __IO uint32_t FIFO_CFG2;
+    __IO uint32_t FIFO_CFG3;
+    __IO uint32_t FIFO_CFG4;
+    __IO uint32_t FIFO_CFG5;
+    __IO uint32_t FIFO_RAM_ACCESS0;
+    __IO uint32_t FIFO_RAM_ACCESS1;
+    __IO uint32_t FIFO_RAM_ACCESS2;
+    __I  uint32_t FIFO_RAM_ACCESS3;
+    __IO uint32_t FIFO_RAM_ACCESS4;
+    __IO uint32_t FIFO_RAM_ACCESS5;
+    __IO uint32_t FIFO_RAM_ACCESS6;
+    __I  uint32_t FIFO_RAM_ACCESS7;
+    /*
+     * Statistics registers (MSTAT)
+     */
+    __IO uint32_t TR64;
+    __IO uint32_t TR127;
+    __IO uint32_t TR255;
+    __IO uint32_t TR511;
+    __IO uint32_t TR1K;
+    __IO uint32_t TRMAX;
+    __IO uint32_t TRMGV;
+    __IO uint32_t RBYT;
+    __IO uint32_t PPKT;
+    __IO uint32_t RFCS;
+    __IO uint32_t RMCA;
+    __IO uint32_t RBCA;
+    __IO uint32_t RXCF;
+    __IO uint32_t RXPF;
+    __IO uint32_t RXUO;
+    __IO uint32_t RALN;
+    __IO uint32_t RFLR;
+    __IO uint32_t RCDE;
+    __IO uint32_t RCSE;
+    __IO uint32_t RUND;
+    __IO uint32_t ROVR;
+    __IO uint32_t RFRG;
+    __IO uint32_t RJBR;
+    __IO uint32_t RDRP;
+    __IO uint32_t TBYT;
+    __IO uint32_t TPKT;
+    __IO uint32_t TMCA;
+    __IO uint32_t TBCA;
+    __IO uint32_t TXPF;
+    __IO uint32_t TDFR;
+    __IO uint32_t TEDF;
+    __IO uint32_t TSCL;
+    __IO uint32_t TMCL;
+    __IO uint32_t TLCL;
+    __IO uint32_t TXCL;
+    __IO uint32_t TNCL;
+    __IO uint32_t TPFH;
+    __IO uint32_t TDRP;
+    __IO uint32_t TJBR;
+    __IO uint32_t TFCS;
+    __IO uint32_t TXCF;
+    __IO uint32_t TOVR;
+    __IO uint32_t TUND;
+    __IO uint32_t TFRG;
+    __I  uint32_t CAR1;
+    __I  uint32_t CAR2;
+    __IO uint32_t CAM1;
+    __IO uint32_t CAM2;
+     uint32_t RESERVED1[16];
+    /*
+     * DMA registers (MAHBE)
+     */
+    __IO uint32_t DMA_TX_CTRL;
+    __IO uint32_t DMA_TX_DESC;
+    __IO uint32_t DMA_TX_STATUS;
+    __IO uint32_t DMA_RX_CTRL;
+    __IO uint32_t DMA_RX_DESC;
+    __IO uint32_t DMA_RX_STATUS;
+    __IO uint32_t DMA_IRQ_MASK;
+    __I  uint32_t DMA_IRQ;
+} MAC_TypeDef;
+
+/*----------------------------------------------------------------------------*/
+/*------------------------------ USB --------------------------------*/
+/*----------------------------------------------------------------------------*/
+typedef struct
+{
+    __IO uint16_t   TX_MAX_P;
+    __IO uint16_t   TX_CSR;  
+    __IO uint16_t   RX_MAX_P;
+    __IO uint16_t   RX_CSR;  
+    __IO uint16_t   RX_COUNT;
+    __IO uint8_t    TX_TYPE; 
+    __IO uint8_t    TX_INTERVAL;
+    __IO uint8_t    RX_TYPE;    
+    __IO uint8_t    RX_INTERVAL;
+    __IO uint8_t    RESERVED;
+    __IO uint8_t    FIFO_SIZE;  
+} USB_endpoint_regs_t;
+
+typedef struct
+{
+    __IO uint8_t    TX_FUNC_ADDR;
+    __IO uint8_t    UNUSED0;
+    __IO uint8_t    TX_HUB_ADDR;
+    __IO uint8_t    TX_HUB_PORT;
+    __IO uint8_t    RX_FUNC_ADDR;
+    __IO uint8_t    UNUSED1;
+    __IO uint8_t    RX_HUB_ADDR;
+    __IO uint8_t    RX_HUB_PORT;
+} USB_tar_t;
+
+typedef union
+{
+    struct
+    {
+        __IO uint32_t   VALUE;
+    } WORD;
+
+    struct
+    {
+        __IO uint8_t    VALUE;
+        __IO uint8_t    RESERVED1;
+        __IO uint8_t    RESERVED2;
+        __IO uint8_t    RESERVED3;
+    } BYTE;
+
+    struct
+    {
+        __IO uint16_t   VALUE;
+        __IO uint16_t   RESERVED;
+    } HALFWORD;
+} USB_fifo_t;
+
+typedef union
+{
+    struct                          
+    {
+        __IO uint16_t   TX_MAX_P;   
+        __IO uint16_t   CSR0;       
+        __IO uint16_t   RX_MAX_P;   
+        __IO uint16_t   RX_CSR;     
+        __IO uint16_t   COUNT0;     
+        __IO uint8_t    RESERVED0;
+        __IO uint8_t    RESERVED1;
+        __IO uint8_t    RESERVED2;
+        __IO uint8_t    RESERVED3;
+        __IO uint8_t    RESERVED4;
+        __IO uint8_t    CONFIG_DATA;  
+    } DEVICE_EP0;
+
+    struct                            
+    {
+        __IO uint16_t   TX_MAX_P;
+        __IO uint16_t   TX_CSR;
+        __IO uint16_t   RX_MAX_P;
+        __IO uint16_t   RX_CSR;
+        __IO uint16_t   RX_COUNT;
+        __IO uint8_t    RESERVED0;
+        __IO uint8_t    RESERVED1;
+        __IO uint8_t    RESERVED2;
+        __IO uint8_t    RESERVED3;
+        __IO uint8_t    RESERVED4;
+        __IO uint8_t    FIFO_SIZE;
+    } DEVICE_EPN;
+
+    struct                          
+    {
+        __IO uint16_t   TX_MAX_P;
+        __IO uint16_t   CSR0;
+        __IO uint16_t   RX_MAX_P;
+        __IO uint16_t   RX_CSR;
+        __IO uint16_t   COUNT0;
+        __IO uint8_t    TYPE0;
+        __IO uint8_t    NAK_LIMIT0;
+        __IO uint8_t    RX_TYPE;
+        __IO uint8_t    RX_INTERVAL;
+        __IO uint8_t    RESERVED0;
+        __IO uint8_t    CONFIG_DATA;
+    } HOST_EP0;
+
+    struct                          
+    {
+        __IO uint16_t   TX_MAX_P;
+        __IO uint16_t   TX_CSR;
+        __IO uint16_t   RX_MAX_P;
+        __IO uint16_t   RX_CSR;
+        __IO uint16_t   RX_COUNT;
+        __IO uint8_t    TX_TYPE;
+        __IO uint8_t    TX_INTERVAL;
+        __IO uint8_t    RX_TYPE;
+        __IO uint8_t    RX_INTERVAL;
+        __IO uint8_t    RESERVED0;
+        __IO uint8_t    FIFO_SIZE;
+    } HOST_EPN;
+
+} USB_indexed_csr_t;
+
+typedef struct {
+    __IO uint32_t   IRQ;    
+    __IO uint32_t   CNTL;
+    __IO uint32_t   ADDR;
+    __IO uint32_t   COUNT;
+} USB_DMA_channel;
+
+typedef struct
+{
+    /* 
+    * Common USB Registers 
+    */
+    __IO uint8_t    FADDR;            
+    __IO uint8_t    POWER;            
+    __IO uint16_t   TX_IRQ;           
+    __IO uint16_t   RX_IRQ;           
+    __IO uint16_t   TX_IRQ_ENABLE;    
+    __IO uint16_t   RX_IRQ_ENABLE;    
+    __IO uint8_t    USB_IRQ;          
+    __IO uint8_t    USB_ENABLE;       
+    __IO uint16_t   FRAME;            
+    __IO uint8_t    INDEX;            
+    __IO uint8_t    TEST_MODE;        
+
+    /*
+    * Indexed CSR
+    */
+    USB_indexed_csr_t   INDEXED_CSR;
+
+    /*
+    * Endpoint FIFOs 
+    */
+    USB_fifo_t      FIFO[16];         
+
+    /*
+    * OTG, dynamic FIFO and version 
+    */
+    __IO uint8_t    DEV_CTRL;         
+    __IO uint8_t    MISC;             
+    __IO uint8_t    TX_FIFO_SIZE;     
+    __IO uint8_t    RX_FIFO_SIZE;     
+    __IO uint16_t   TX_FIFO_ADDR;     
+    __IO uint16_t   RX_FIFO_ADDR;     
+    __IO uint32_t   VBUS_CSR;         
+    __IO uint16_t   HW_VERSION;       
+    __IO uint16_t   RESERVED;         
+
+    /* 
+    * ULPI and configuration registers 
+    */
+    __IO uint8_t    ULPI_VBUS_CTRL;   
+    __IO uint8_t    ULPI_CARKIT_CTRL; 
+    __IO uint8_t    ULPI_IRQ_MASK;    
+    __IO uint8_t    ULPI_IRQ_SRC;     
+    __IO uint8_t    ULPI_DATA_REG;    
+    __IO uint8_t    ULPI_ADDR_REG;    
+    __IO uint8_t    ULPI_CTRL_REG;    
+    __IO uint8_t    ULPI_RAW_DATA;    
+    __IO uint8_t    EP_INFO;          
+    __IO uint8_t    RAM_INFO;         
+    __IO uint8_t    LINK_INFO;        
+    __IO uint8_t    VP_LEN;           
+    __IO uint8_t    HS_EOF1;          
+    __IO uint8_t    FS_EOF1;          
+    __IO uint8_t    LS_EOF1;          
+    __IO uint8_t    SOFT_RST;         
+
+    /* 
+    * Target Address registers 
+    */
+    USB_tar_t       TAR[16];          
+
+    /* 
+    * Endpoints CSR 
+    */
+    USB_endpoint_regs_t ENDPOINT[16]; 
+
+    /* 
+    * DMA 
+    */
+    USB_DMA_channel DMA_CHANNEL[8];
+	
+    __IO uint32_t   RESERVED_EXT[32];
+    __IO uint32_t   RQ_PKT_CNT[16];   
+    __IO uint16_t   RX_DPBUF_DIS;
+    __IO uint16_t   TX_DPBUF_DIS;
+    __IO uint16_t   C_T_UCH;
+    __IO uint16_t   C_T_HHSRTN;
+    __IO uint16_t   C_T_HSBT;
+
+} MSS_USB_TypeDef;
+
+/*----------------------------------------------------------------------------*/
+/*---------------------- eNVM Special Function Registers ---------------------*/
+/*----------------------------------------------------------------------------*/
+typedef struct
+{
+    __I  uint8_t  AB[128];
+    __IO uint8_t  WD[128];
+    __I  uint8_t  RESERVED0[32];
+    __I  uint32_t STATUS;
+    __IO uint32_t RESERVED1;
+    __IO uint32_t NV_PAGE_STATUS;
+    __I  uint32_t NV_FREQRNG;
+    __I  uint32_t NV_DPD;
+    __IO uint32_t NV_CE;
+         uint32_t RESERVED2;
+    __IO uint32_t RESERVED3;
+    __IO uint32_t PAGE_LOCK;
+    __IO uint32_t DWSIZE;
+    __IO uint32_t CMD;
+    __IO uint32_t RESERVED4;
+    __I  uint32_t RESERVED5;
+    __IO uint32_t INTEN;
+    __IO uint32_t CLRHINT;
+         uint32_t RESERVED6[40];
+    __IO uint32_t REQ_ACCESS;
+} NVM_TypeDef;
+
+typedef struct
+{
+    __I  uint32_t AB[32];
+    __IO uint32_t WD[32];
+    __I  uint32_t RESERVED0[8];
+    __I  uint32_t STATUS;
+    __IO uint32_t RESERVED1;
+    __IO uint32_t NV_PAGE_STATUS;
+    __I  uint32_t NV_FREQRNG;
+    __I  uint32_t NV_DPD;
+    __IO uint32_t NV_CE;
+         uint32_t RESERVED2;
+    __IO uint32_t RESERVED3;
+    __IO uint32_t PAGE_LOCK;
+    __IO uint32_t DWSIZE;
+    __IO uint32_t CMD;
+    __IO uint32_t RESERVED4;
+    __I  uint32_t RESERVED5;
+    __IO uint32_t INTEN;
+    __IO uint32_t CLRHINT;
+         uint32_t RESERVED6[40];
+    __IO uint32_t REQ_ACCESS;
+} NVM32_TypeDef;
+
+/*----------------------------------------------------------------------------*/
+/*---------------------------------- COMBLK ----------------------------------*/
+/*----------------------------------------------------------------------------*/
+typedef struct
+{
+    __IO uint32_t CONTROL;
+    __IO uint32_t STATUS;
+    __IO uint32_t INT_ENABLE;
+    __IO uint32_t RESERVED;
+    __IO uint32_t DATA8;
+    __IO uint32_t DATA32;
+    __IO uint32_t FRAME_START8;
+    __IO uint32_t FRAME_START32;
+} COMBLK_TypeDef;
+
+/*----------------------------------------------------------------------------*/
+/*--------------------- FPGA Fabric Interrupt Controller ---------------------*/
+/*----------------------------------------------------------------------------*/
+/*
+ * Please refer to the SmartFusion2 Interrupt Controller User's Guide for a
+ * description of the following registers.
+ * The registers defined below can be accessed using INTERRUPT_CTRL as follows:
+ *      uint32_t reason0;
+ *      INTERRUPT_CTRL->INTERRUPT_MODE = 0;
+ *      reason0 = INTERRUPT_CTRL->INTERRUPT_REASON0;
+ */
+typedef struct
+{
+    __IO uint32_t INTERRUPT_ENABLE0;
+    __IO uint32_t INTERRUPT_ENABLE1;
+    __IO uint32_t INTERRUPT_REASON0;
+    __IO uint32_t INTERRUPT_REASON1;
+    __IO uint32_t INTERRUPT_MODE;
+} INTERRUPT_CTRL_TypeDef;
+
+/*
+ * Please refer to the SmartFusion2 Interrupt Controller User's Guide for a
+ * description of the following register bits.
+ * The register bits defined below can be accessed using INTERRUPT_CTRL_BITBAND
+ * as follows:
+ *  setting/clearing a bit:
+ *      INTERRUPT_CTRL_BITBAND->MAC_INT_ENBL = 1;
+ *      INTERRUPT_CTRL_BITBAND->PDMAINTERRUPT_ENBL = 0;
+ *  reading a bit value:
+ *      uint32_t timer1_interrupt;
+ *      timer1_interrupt = INTERRUPT_CTRL_BITBAND->TIMER1_INTR_STATUS;
+ */
+typedef struct
+{
+    /*
+     * INTERRUPT_ENABLE0 register bitband definitions.
+     */
+    __IO uint32_t SPIINT0_ENBL;
+    __IO uint32_t SPIINT1_ENBL;
+    __IO uint32_t I2C_INT0_ENBL;
+    __IO uint32_t I2C_INT1_ENBL;
+    __IO uint32_t MMUART0_INTR_ENBL;
+    __IO uint32_t MMUART1_INTR_ENBL;
+    __IO uint32_t MAC_INT_ENBL;
+    __IO uint32_t USB_MC_INT_ENBL;
+    __IO uint32_t PDMAINTERRUPT_ENBL;
+    __IO uint32_t HPD_XFR_CMP_INT_ENBL;
+    __IO uint32_t TIMER1_INTR_ENBL;
+    __IO uint32_t TIMER2_INTR_ENBL;
+    __IO uint32_t CAN_INTR_ENBL;
+    __IO uint32_t RTC_WAKEUP_INTR_ENBL;
+    __IO uint32_t WDOGWAKEUPINT_ENBL;
+    __IO uint32_t MSSDDR_PLL_LOCKLOST_INT_ENBL;
+    __IO uint32_t ENVM_INT0_ENBL;
+    __IO uint32_t ENVM_INT1_ENBL;
+    __IO uint32_t I2C_SMBALERT0_ENBL;
+    __IO uint32_t I2C_SMBSUS0_ENBL;
+    __IO uint32_t I2C_SMBALERT1_ENBL;
+    __IO uint32_t I2C_SMBSUS1_ENBL;
+    __IO uint32_t HPD_XFR_ERR_INT_ENBL;
+    __IO uint32_t MSSDDR_PLL_LOCK_INT_ENBL;
+    __IO uint32_t SW_ERRORINTERRUPT_ENBL;
+    __IO uint32_t DDRB_INTR_ENBL;
+    __IO uint32_t ECCINTR_ENBL;
+    __IO uint32_t CACHE_ERRINTR_ENBL;
+    __IO uint32_t SOFTINTERRUPT_ENBL;
+    __IO uint32_t COMBLK_INTR_ENBL;
+    __IO uint32_t USB_DMA_INT_ENBL;
+    __IO uint32_t RESERVED0;
+    
+    /*
+     * INTERRUPT_ENABLE1 register bitband definitions.
+     */
+    __IO uint32_t RESERVED1[3];
+    __IO uint32_t MDDR_IO_CALIB_INT_ENBL;
+    __IO uint32_t RESERVED2;
+    __IO uint32_t FAB_PLL_LOCK_INT_ENBL;
+    __IO uint32_t FAB_PLL_LOCKLOST_INT_ENBL;
+    __IO uint32_t FIC64_INT_ENBL;
+    __IO uint32_t RESERVED3[24];
+    
+    /*
+     * INTERRUPT_REASON0 register bitband definitions.
+     */
+    __IO uint32_t SPIINT0_STATUS;
+    __IO uint32_t SPIINT1_STATUS;
+    __IO uint32_t I2C_INT0_STATUS;
+    __IO uint32_t I2C_INT1_STATUS;
+    __IO uint32_t MMUART0_INTR_STATUS;
+    __IO uint32_t MMUART1_INTR_STATUS;
+    __IO uint32_t MAC_INT_STATUS;
+    __IO uint32_t USB_MC_INT_STATUS;
+    __IO uint32_t PDMAINTERRUPT_STATUS;
+    __IO uint32_t HPD_XFR_CMP_INT_STATUS;
+    __IO uint32_t TIMER1_INTR_STATUS;
+    __IO uint32_t TIMER2_INTR_STATUS;
+    __IO uint32_t CAN_INTR_STATUS;
+    __IO uint32_t RTC_WAKEUP_INTR_STATUS;
+    __IO uint32_t WDOGWAKEUPINT_STATUS;
+    __IO uint32_t MSSDDR_PLL_LOCKLOST_INT_STATUS;
+    __IO uint32_t ENVM_INT0_STATUS;
+    __IO uint32_t ENVM_INT1_STATUS;
+    __IO uint32_t I2C_SMBALERT0_STATUS;
+    __IO uint32_t I2C_SMBSUS0_STATUS;
+    __IO uint32_t I2C_SMBALERT1_STATUS;
+    __IO uint32_t I2C_SMBSUS1_STATUS;
+    __IO uint32_t HPD_XFR_ERR_INT_STATUS;
+    __IO uint32_t MSSDDR_PLL_LOCK_INT_STATUS;
+    __IO uint32_t SW_ERRORINTERRUPT_STATUS;
+    __IO uint32_t DDRB_INTR_STATUS;
+    __IO uint32_t ECCINTR_STATUS;
+    __IO uint32_t CACHE_ERRINTR_STATUS;
+    __IO uint32_t SOFTINTERRUPT_STATUS;
+    __IO uint32_t COMBLK_INTR_STATUS;
+    __IO uint32_t USB_DMA_INT_STATUS;
+    __IO uint32_t RESERVED4;
+    
+    /*
+     * INTERRUPT_REASON1 register bitband definitions.
+     */
+    __IO uint32_t RESERVED5[3];
+    __IO uint32_t MDDR_IO_CALIB_INT_STATUS;
+    __IO uint32_t RESERVED6;
+    __IO uint32_t FAB_PLL_LOCK_INT_STATUS;
+    __IO uint32_t FAB_PLL_LOCKLOST_INT_STATUS;
+    __IO uint32_t FIC64_INT_STATUS;
+    __IO uint32_t RESERVED7[24];
+    
+    /*
+     * INTERRUPT_MODE register bitband definitions.
+     */
+    __IO uint32_t SELECT_MODE;
+    __IO uint32_t RESERVED8[31];
+    
+} INTERRUPT_CTRL_BitBand_TypeDef;
+
+/*----------------------------------------------------------------------------*/
+/*------------------------ DDR Controller APB Registers ----------------------*/
+/*----------------------------------------------------------------------------*/
+typedef struct
+{
+    /*--------------------------------------------------------------------------
+     * DDR Controller registers.
+     * All registers are 16-bit wide unless mentioned beside the definition.
+     */
+    struct
+    {
+        __IO uint32_t DYN_SOFT_RESET_CR;
+        __IO uint32_t RESERVED0;
+        __IO uint32_t DYN_REFRESH_1_CR;
+        __IO uint32_t DYN_REFRESH_2_CR;
+        __IO uint32_t DYN_POWERDOWN_CR;
+        __IO uint32_t DYN_DEBUG_CR;
+        __IO uint32_t MODE_CR;
+        __IO uint32_t ADDR_MAP_BANK_CR;
+        __IO uint32_t ECC_DATA_MASK_CR;
+        __IO uint32_t ADDR_MAP_COL_1_CR;
+        __IO uint32_t ADDR_MAP_COL_2_CR;
+        __IO uint32_t ADDR_MAP_ROW_1_CR;
+        __IO uint32_t ADDR_MAP_ROW_2_CR;
+        __IO uint32_t INIT_1_CR;
+        __IO uint32_t CKE_RSTN_CYCLES_CR[2];     /* 0:27 bits are valid */
+        __IO uint32_t INIT_MR_CR;
+        __IO uint32_t INIT_EMR_CR;
+        __IO uint32_t INIT_EMR2_CR;
+        __IO uint32_t INIT_EMR3_CR;
+        __IO uint32_t DRAM_BANK_TIMING_PARAM_CR;
+        __IO uint32_t DRAM_RD_WR_LATENCY_CR;
+        __IO uint32_t DRAM_RD_WR_PRE_CR;
+        __IO uint32_t DRAM_MR_TIMING_PARAM_CR;
+        __IO uint32_t DRAM_RAS_TIMING_CR;
+        __IO uint32_t DRAM_RD_WR_TRNARND_TIME_CR;
+        __IO uint32_t DRAM_T_PD_CR;
+        __IO uint32_t DRAM_BANK_ACT_TIMING_CR;
+        __IO uint32_t ODT_PARAM_1_CR;
+        __IO uint32_t ODT_PARAM_2_CR;
+        __IO uint32_t ADDR_MAP_COL_3_CR;
+        __IO uint32_t MODE_REG_RD_WR_CR;
+        __IO uint32_t MODE_REG_DATA_CR;
+        __IO uint32_t PWR_SAVE_1_CR;
+        __IO uint32_t PWR_SAVE_2_CR;
+        __IO uint32_t ZQ_LONG_TIME_CR;
+        __IO uint32_t ZQ_SHORT_TIME_CR;
+        __IO uint32_t ZQ_SHORT_INT_REFRESH_MARGIN_CR[2];
+        __IO uint32_t PERF_PARAM_1_CR;
+        __IO uint32_t HPR_QUEUE_PARAM_CR[2];
+        __IO uint32_t LPR_QUEUE_PARAM_CR[2];
+        __IO uint32_t WR_QUEUE_PARAM_CR;
+        __IO uint32_t PERF_PARAM_2_CR;
+        __IO uint32_t PERF_PARAM_3_CR;
+        __IO uint32_t DFI_RDDATA_EN_CR;
+        __IO uint32_t DFI_MIN_CTRLUPD_TIMING_CR;
+        __IO uint32_t DFI_MAX_CTRLUPD_TIMING_CR;
+        __IO uint32_t DFI_WR_LVL_CONTROL_CR[2];
+        __IO uint32_t DFI_RD_LVL_CONTROL_CR[2];
+        __IO uint32_t DFI_CTRLUPD_TIME_INTERVAL_CR;
+        __IO uint32_t DYN_SOFT_RESET_CR2;
+        __IO uint32_t AXI_FABRIC_PRI_ID_CR;
+        __I  uint32_t DDRC_SR;
+        __I  uint32_t SINGLE_ERR_CNT_SR;
+        __I  uint32_t DOUBLE_ERR_CNT_SR;
+        __I  uint32_t LUE_SYNDROME_SR[5];       /* LUE : Last Uncorrected Error */
+        __I  uint32_t LUE_ADDRESS_SR[2];        
+        __I  uint32_t LCE_SYNDROME_SR[5];       /* LCE : Last Corrected Error */
+        __I  uint32_t LCE_ADDRESS_SR[2];
+        __I  uint32_t LCB_NUMBER_SR;            /* LCB : Last Corrected Bit */
+        __I  uint32_t LCB_MASK_SR[4];          
+        __I  uint32_t ECC_INT_SR;
+        __O  uint32_t ECC_INT_CLR_REG;
+        __I  uint32_t ECC_OUTPUT_DATA_SR;
+        __IO uint32_t RESERVED1[46];
+    } ddrc;
+    
+    /*--------------------------------------------------------------------------
+     * DDR PHY configuration registers
+     */
+    struct 
+    {
+        __IO uint32_t DYN_BIST_TEST_CR;
+        __IO uint32_t DYN_BIST_TEST_ERRCLR_CR[3];
+        __IO uint32_t BIST_TEST_SHIFT_PATTERN_CR[3];
+        __IO uint32_t LOOPBACK_TEST_CR;
+        __IO uint32_t BOARD_LOOPBACK_CR;
+        __IO uint32_t CTRL_SLAVE_RATIO_CR;
+        __IO uint32_t CTRL_SLAVE_FORCE_CR;
+        __IO uint32_t CTRL_SLAVE_DELAY_CR;
+        __IO uint32_t DATA_SLICE_IN_USE_CR;
+        __IO uint32_t LVL_NUM_OF_DQ0_CR;
+        __IO uint32_t DQ_OFFSET_CR[3];
+        __IO uint32_t DIS_CALIB_RST_CR;
+        __IO uint32_t DLL_LOCK_DIFF_CR;
+        __IO uint32_t FIFO_WE_IN_DELAY_CR[3];
+        __IO uint32_t FIFO_WE_IN_FORCE_CR;
+        __IO uint32_t FIFO_WE_SLAVE_RATIO_CR[4];
+        __IO uint32_t GATELVL_INIT_MODE_CR;
+        __IO uint32_t GATELVL_INIT_RATIO_CR[4];
+        __IO uint32_t LOCAL_ODT_CR;
+        __IO uint32_t INVERT_CLKOUT_CR;
+        __IO uint32_t RD_DQS_SLAVE_DELAY_CR[3];
+        __IO uint32_t RD_DQS_SLAVE_FORCE_CR;
+        __IO uint32_t RD_DQS_SLAVE_RATIO_CR[4];
+        __IO uint32_t WR_DQS_SLAVE_DELAY_CR[3];
+        __IO uint32_t WR_DQS_SLAVE_FORCE_CR;
+        __IO uint32_t WR_DQS_SLAVE_RATIO_CR[4];
+        __IO uint32_t WR_DATA_SLAVE_DELAY_CR[3];
+        __IO uint32_t WR_DATA_SLAVE_FORCE_CR;
+        __IO uint32_t WR_DATA_SLAVE_RATIO_CR[4];
+        __IO uint32_t WRLVL_INIT_MODE_CR;
+        __IO uint32_t WRLVL_INIT_RATIO_CR[4];
+        __IO uint32_t WR_RD_RL_CR;
+        __IO uint32_t RDC_FIFO_RST_ERRCNTCLR_CR;
+        __IO uint32_t RDC_WE_TO_RE_DELAY_CR;
+        __IO uint32_t USE_FIXED_RE_CR;
+        __IO uint32_t USE_RANK0_DELAYS_CR;
+        __IO uint32_t USE_LVL_TRNG_LEVEL_CR;
+        __IO uint32_t CONFIG_CR;
+        __IO uint32_t RD_WR_GATE_LVL_CR;
+        __IO uint32_t DYN_RESET_CR;
+
+        /*----------------------------------------------------------------------
+         * DDR PHY status registers
+         */    
+        __I  uint32_t LEVELLING_FAILURE_SR;
+        __I  uint32_t BIST_ERROR_SR[3];
+        __I  uint32_t WRLVL_DQS_RATIO_SR[4];
+        __I  uint32_t WRLVL_DQ_RATIO_SR[4];
+        __I  uint32_t RDLVL_DQS_RATIO_SR[4];
+        __I  uint32_t FIFO_SR[4];
+        __I  uint32_t MASTER_DLL_SR;
+        __I  uint32_t DLL_SLAVE_VALUE_SR[2];
+        __I  uint32_t STATUS_OF_IN_DELAY_VAL_SR[2];
+        __I  uint32_t STATUS_OF_OUT_DELAY_VAL_SR[2];
+        __I  uint32_t DLL_LOCK_AND_SLAVE_VAL_SR;
+        __I  uint32_t CTRL_OUTPUT_FILTER_SR;
+        __I  uint32_t CTRL_OF_OUTPUT_DELAY_SR;
+        __I  uint32_t RD_DQS_SLAVE_DLL_VAL_SR[3];
+        __I  uint32_t WR_DATA_SLAVE_DLL_VAL_SR[3];
+        __I  uint32_t FIFO_WE_SLAVE_DLL_VAL_SR[3];
+        __I  uint32_t WR_DQS_SLAVE_DLL_VAL_SR[3];
+        __I  uint32_t CTRL_SLAVE_DLL_VAL_SR; 
+        __IO uint32_t RESERVED2[13];
+    } phy;
+    
+    /*--------------------------------------------------------------------------
+     * FIC-64 registers
+     * These registers are 16-bit wide and 32-bit aligned.
+     */
+    struct 
+    {
+        __IO uint32_t NB_ADDR_CR;
+        __IO uint32_t NBRWB_SIZE_CR;
+        __IO uint32_t WB_TIMEOUT_CR;
+        __IO uint32_t HPD_SW_RW_EN_CR;
+        __IO uint32_t HPD_SW_RW_INVAL_CR;
+        __IO uint32_t SW_WR_ERCLR_CR;
+        __IO uint32_t ERR_INT_ENABLE_CR;
+        __IO uint32_t NUM_AHB_MASTERS_CR;
+        __I  uint32_t HPB_ERR_ADDR_SR[2];
+        __I  uint32_t SW_ERR_ADDR_SR[2];
+        __I  uint32_t HPD_SW_WRB_EMPTY_SR;
+        __I  uint32_t SW_HPB_LOCKOUT_SR;
+        __I  uint32_t SW_HPD_WERR_SR;
+             uint32_t RESERVED0;
+        __IO uint32_t LOCK_TIMEOUTVAL_CR[2];
+        __IO uint32_t LOCK_TIMEOUT_EN_CR;
+             uint32_t RESERVED1[5];
+        __IO uint32_t RDWR_ERR_SR;
+    } fic;
+} DDRCore_TypeDef;
+
+/*----------------------------------------------------------------------------*/
+/*--------------------- MDDR APB Configuration Registers ---------------------*/
+/*----------------------------------------------------------------------------*/
+typedef struct
+{
+    /*--------------------------------------------------------------------------
+     * MDDR core configuration registers.
+     * These registers are to be accessed as:
+     * MDDR->core.fic.<regname> = <value>;
+     * MDDR->core.phy.<regname> = <value>;
+     * MDDR->core.ddrc.<regname> = <value>;
+     */
+    DDRCore_TypeDef core;
+    
+} MDDR_TypeDef;
+
+
+/*----------------------------------------------------------------------------*/
+/*--------------------- FDDR APB Configuration Registers ---------------------*/
+/*----------------------------------------------------------------------------*/
+typedef struct 
+{
+    /*--------------------------------------------------------------------------
+     * FDDR core configuration registers. These are same as corresponding 
+     * MDDR registers. 
+     * These registers are to be accessed as:
+     * FDDR->core.fic.<regname> = <value>;
+     * FDDR->core.phy.<regname> = <value>;
+     * FDDR->core.ddrc.<regname> = <value>;
+     */
+    DDRCore_TypeDef core;
+    __IO uint32_t RESERVED[39];
+    
+    /*--------------------------------------------------------------------------
+     * FDDR system registers
+     * These registers are to be accessed as:
+     * FDDR->sysreg.PLL_CONFIG_LOW_2 = 0x04u;
+     */
+    struct 
+    {
+        __IO uint32_t PLL_CONFIG_LOW_1;
+        __IO uint32_t PLL_CONFIG_LOW_2;
+        __IO uint32_t PLL_CONFIG_HIGH;
+        __IO uint32_t FACC_CLK_EN;
+        __IO uint32_t FACC_MUX_CONFIG;
+        __IO uint32_t FACC_DIVISOR_RATIO;
+        __IO uint32_t PLL_DELAY_LINE_SEL;
+        __IO uint32_t SOFT_RESET; 
+        __IO uint32_t IO_CALIB;
+        __IO uint32_t INTERRUPT_ENABLE;
+        __IO uint32_t AXI_AHB_MODE_SEL;
+        __IO uint32_t PHY_SELF_REF_EN;
+        __IO uint32_t FAB_PLL_CLK_SR;
+        __IO uint32_t FPLL_CLK_SR;
+        __IO uint32_t CLK_CALIB_STATUS;
+        __IO uint32_t INTERRUPT_SR;
+        __IO uint32_t CLK_CALIB_CONFIG;
+        __IO uint32_t IO_CALIB_SR;
+        __IO uint32_t FATC_RESET;
+    } sysreg;
+} FDDR_TypeDef;
+
+/*----------------------------------------------------------------------------*/
+/*------------------------------ SERDES Interface ----------------------------*/
+/*----------------------------------------------------------------------------*/
+
+/*------------------------------------------------------------------------------
+  AXI window
+ */
+typedef struct
+{
+    __IO    uint32_t    base;
+    __IO    uint32_t    size;
+    __IO    uint32_t    window_lsb;
+    __IO    uint32_t    window_msb;
+} axi_window_TypeDef;
+
+/*------------------------------------------------------------------------------
+  PCI Express Bridge Core registers.
+  
+  This data structure is used to access to the registers of the PCI Express
+  Bridge Core.
+ */
+typedef struct
+{
+    /*======================= Information registers ======================*/
+    /**
+      Information register: vendor_id & device_id
+      bits [15:0]   vendor_id
+      bits [31:16]  device_id
+     */
+    /* 0x000 */
+    __IO    uint32_t    VID_DEVID;
+
+    /**
+      PCI Express Control & Status Register: cfg_prmscr
+     */
+    /* 0x004 */
+    __IO    uint32_t    CFG_PRMSCR;
+    
+    /**
+      Information register: class_code
+     */
+    /* 0x008 */
+    __IO    uint32_t    CLASS_CODE;
+    
+    __IO    uint32_t    RESERVED0;
+    
+    /**
+      Bridge Configuration Register: bar0
+     */
+    /* 0x010 */
+    __IO    uint32_t    BAR0;
+    
+    /**
+      Bridge Configuration Register: bar1
+     */
+    /* 0x014 */
+    __IO    uint32_t    BAR1;
+    
+    /**
+      Bridge Configuration Register: bar2
+     */
+    /* 0x018 */
+    __IO    uint32_t    BAR2;
+    
+    /**
+      Bridge Configuration Register: bar3
+     */
+    /* 0x01C */
+    __IO    uint32_t    BAR3;
+    
+    /**
+      Bridge Configuration Register: bar4
+     */
+    /* 0x020 */
+    __IO    uint32_t    BAR4;
+    
+    /**
+      Bridge Configuration Register: bar5
+     */
+    /* 0x024 */
+    __IO    uint32_t    BAR5;
+    
+    __IO    uint32_t    RESERVED1;
+    
+    /**
+      Information register: subsystem_id
+     */
+    /* 0x02C */
+    __IO    uint32_t    SUBSYSTEM_ID;
+    
+    /**
+      PCI Express Control & Status Register: pcie_devscr
+     */
+    /* 0x030 */
+    __IO    uint32_t    PCIE_DEVSCR;
+    
+    /**
+      PCI Express Control & Status Register: pcie_linkscr
+     */
+    /* 0x034 */
+    __IO    uint32_t    PCIE_LINKSCR;
+    
+    /**
+      Bridge Configuration Register: tc_vc_mapping
+     */
+    /* 0x038 */
+    __IO    uint32_t    TC_VC_MAPPING;
+    
+    /**
+      Information register: captured_bus_device_nb
+     */
+    /* 0x03C */
+    __IO    uint32_t    CAPTURED_BUS_DEVICE_NB;
+    
+    /**
+      Endpoint Interrupt register: msi_ctrl_status
+     */
+    /* 0x040 */
+    __IO    uint32_t    MSI_CTRL_STATUS;
+    
+    /**
+      Power Management register: ltssm
+     */
+    /* 0x044 */
+    __IO    uint32_t    LTSSM;
+    
+    /**
+      Power Management register: power_mgt_capability
+     */
+    /* 0x048 */
+    __IO    uint32_t    POWER_MGT_CAPABILITY;
+    
+    /**
+      PCI Express Control & Status Register: cfg_pmscr
+     */
+    /* 0x04C */
+    __IO    uint32_t    CFG_PMSCR;
+    
+    /**
+      Bridge Configuration Register: aer_ecrc_capability
+     */
+    /* 0x050 */
+    __IO    uint32_t    AER_ECRC_CAPABILITY;
+    
+    /**
+      Bridge Configuration Register: vc1_capability
+     */
+    /* 0x054 */
+    __IO    uint32_t    VC1_CAPABILITY;
+    
+    /**
+      Bridge Configuration Register: max_payload_size
+     */
+    /* 0x058 */
+    __IO    uint32_t    MAX_PAYLOAD_SIZE;
+    
+    /**
+      Bridge Configuration Register: clkreq
+     */
+    /* 0x05C */
+    __IO    uint32_t    CLKREQ;
+    
+    /**
+      Power Management register: aspm_l0s_capability
+     */
+    /* 0x060 */
+    __IO    uint32_t    ASPM_L0S_CAPABILITY;
+    
+    /**
+      Power Management register: aspm_l1_capability
+     */
+    /* 0x064 */
+    __IO    uint32_t    ASPM_L1_CAPABILITY;
+    
+    /**
+      Power Management register: timeout_completion
+     */
+    /* 0x068 */
+    __IO    uint32_t    TIMEOUT_COMPLETION;
+
+    __IO    uint32_t    RESERVED2;
+    
+    /**
+      Power Management register: pm_data_scale
+     */
+    /* 0x070 */
+    __IO    uint32_t    PM_DATA_SCALE[4];
+    
+    /**
+      Endpoint Interrupt register: msi
+     */
+    /* 0x080 */
+    __IO    uint32_t    MSI[8];
+    
+    /**
+      Bridge Configuration Register: error_counter
+     */
+    /* 0x0A0 */
+    __IO    uint32_t    ERROR_COUNTER[4];
+    
+    /**
+      Bridge Configuration Register: credit_allocation
+     */
+    /* 0x0B0 */
+    __IO    uint32_t    CREDIT_ALLOCATION[4];
+    
+    /**
+      Address Mapping register: axi_slave_window
+     */
+    /* 0x0C0 */
+    axi_window_TypeDef      AXI_SLAVE_WINDOW[4];
+    
+    /**
+      Address Mapping register: axi_master_window
+     */
+    /* 0x100 */
+    axi_window_TypeDef      AXI_MASTER_WINDOW[4];
+    
+    /**
+      Rootport Interrupt register: imask
+     */
+    /* 0x140 */
+    __IO    uint32_t    IMASK;
+    
+    /**
+      Rootport Interrupt register: istatus
+     */
+    /* 0x144 */
+    __IO    uint32_t    ISTATUS;
+    
+    /**
+      Rootport Interrupt register: icmd
+     */
+    /* 0x148 */
+    __IO    uint32_t    ICMD;
+    
+    /**
+      Rootport Interrupt register: irstatus
+     */
+    /* 0x14C */
+    __IO    uint32_t    IRSTATUS;
+    
+    /**
+      Rootport Interrupt register: imsiaddr
+     */
+    /* 0x150 */
+    __IO    uint32_t    IMSIADDR;
+    
+    /**
+      PCI Express Control & Status Register: slotcap
+     */
+    /* 0x154 */
+    __IO    uint32_t    SLOTCAP;
+    
+    /**
+      PCI Express Control & Status Register: slotcsr
+     */
+    /* 0x158 */
+    __IO    uint32_t    SLOTCSR;
+    
+    /**
+      PCI Express Control & Status Register: rootcsr
+     */
+    /* 0x15C */
+    __IO    uint32_t    ROOTCSR;
+    
+    /**
+      Configuration Register: cfg_control
+     */
+    /* 0x160 */
+    __IO    uint32_t    CFG_CONTROL;
+    
+    /**
+      Configuration Register: cfg_write_data
+     */
+    /* 0x164 */
+    __IO    uint32_t    CFG_WRITE_DATA;
+    
+    /**
+      Configuration Register: cfg_read_data
+     */
+    /* 0x168 */
+    __IO    uint32_t    CFG_READ_DATA;
+    
+    /**
+      Information register: info
+     */
+    /* 0x16C */
+    __IO    uint32_t    INFO;
+    
+    /**
+      Input/Output Control Register: io_control
+     */
+    /* 0x170 */
+    __IO    uint32_t    IO_CONTROL;
+    
+    /**
+      Input/Output Control Register: io_addr
+     */
+    /* 0x174 */
+    __IO    uint32_t    IO_ADDR;
+    
+    /**
+      Input/Output Control Register: io_write_data
+     */
+    /* 0x178 */
+    __IO    uint32_t    IO_WRITE_DATA;
+    
+    /**
+      Input/Output Control Register: io_read_data
+     */
+    /* 0x17C */
+    __IO    uint32_t    IO_READ_DATA;
+    
+    /**
+      Configuration Register: cfg_fbe
+     */
+    /* 0x180 */
+    __IO    uint32_t    CFG_FBE;
+    
+    /**
+      Address Mapping register: prefetch_io_window
+     */
+    /* 0x184 */
+    __IO    uint32_t    PREFETCH_IO_WINDOW;
+    
+    __IO    uint32_t    RESERVED4[31];
+    
+    /**
+      Bridge Configuration Register: pcie_config
+     */
+    /* 0x204 */
+    __IO    uint32_t    PCIE_CONFIG;
+    
+    __IO    uint32_t    RESERVED5[10];
+    
+    /**
+      PCI Express Control & Status Register: pcie_dev2scr
+     */
+    /* 0x230 */
+    __IO    uint32_t    PCIE_DEV2SCR;
+    
+    /**
+      PCI Express Control & Status Register: pcie_link2scr
+     */
+    /* 0x234 */
+    __IO    uint32_t    PCIE_LINK2SCR;
+    
+    __IO    uint32_t    RESERVED6[10];
+    
+    /**
+      Power Management register: aspm_l0s_gen2 capability
+     */
+    /* 0x260 */
+    __IO    uint32_t    ASPM_L0S_GEN2;
+    
+    __IO    uint32_t    RESERVED7[39];
+    
+    /**
+      Bridge Configuration Register: k_cnt_config
+     */
+    /* 0x300 */
+    __IO    uint32_t    K_CNT_CONFIG[6];
+    
+    __IO    uint32_t    RESERVED8[826];
+    
+} PCIE_TypeDef;
+ 
+/*------------------------------------------------------------------------------
+  SERDESIF System Registers.
+ */
+typedef struct
+{
+    __IO    uint32_t    SER_PLL_CONFIG_LOW;
+    __IO    uint32_t    SER_PLL_CONFIG_HIGH;
+    __IO    uint32_t    SERDESIF_SOFT_RESET;
+    __IO    uint32_t    SER_INTERRUPT_ENABLE;
+    __IO    uint32_t    CONFIG_AXI_AHB_BRIDGE;
+    __IO    uint32_t    CONFIG_ECC_INTR_ENABLE;
+    __IO    uint32_t    CONFIG_TEST_IN;
+    __IO    uint32_t    TEST_OUT_READ_ADDR;
+    __IO    uint32_t    CONFIG_PCIE_PM;
+    __IO    uint32_t    CONFIG_PHY_MODE_0;
+    __IO    uint32_t    CONFIG_PHY_MODE_1;
+    __IO    uint32_t    CONFIG_PHY_MODE_2;
+    __IO    uint32_t    CONFIG_PCIE_0;
+    __IO    uint32_t    CONFIG_PCIE_1;
+    __IO    uint32_t    CONFIG_PCIE_2;
+    __IO    uint32_t    CONFIG_PCIE_3;
+    __IO    uint32_t    CONFIG_BAR_SIZE_0_1;
+    __IO    uint32_t    CONFIG_BAR_SIZE_2_3;
+    __IO    uint32_t    CONFIG_BAR_SIZE_3_4;
+    __IO    uint32_t    SER_CLK_STATUS;
+    __IO    uint32_t    SER_CLK_CALIB_STATUS;
+    __IO    uint32_t    TEST_OUT_READ_DATA;
+    __IO    uint32_t    SER_INTERRUPT;
+    __IO    uint32_t    SERDESIF_INTR_STATUS;
+    __IO    uint32_t    SER_CLK_CALIB_CONFIG;
+    __IO    uint32_t    REFCLK_SEL;
+    __IO    uint32_t    PCLK_SEL;
+    __IO    uint32_t    EPCS_RSTN_SEL;
+    __IO    uint32_t    CHIP_ENABLES;
+    __IO    uint32_t    SERDES_TEST_OUT;
+    __IO    uint32_t    SERDES_FATC_RESET;
+    __IO    uint32_t    RC_OSC_SPLL_REFCLK_SEL;
+    __IO    uint32_t    SPREAD_SPECTRUM_CLK;
+    __IO    uint32_t    CONF_AXI_MSTR_WNDW_0;
+    __IO    uint32_t    CONF_AXI_MSTR_WNDW_1;
+    __IO    uint32_t    CONF_AXI_MSTR_WNDW_2;
+    __IO    uint32_t    CONF_AXI_MSTR_WNDW_3;
+    __IO    uint32_t    CONF_AXI_SLV_WNDW_0;
+    __IO    uint32_t    CONF_AXI_SLV_WNDW_1;
+    __IO    uint32_t    CONF_AXI_SLV_WNDW_2;
+    __IO    uint32_t    CONF_AXI_SLV_WNDW_3;
+    __IO    uint32_t    DESKEW_CONFIG;
+    __IO    uint32_t    DEBUG_MODE_KEY;
+    __IO    uint32_t    RESERVED0;
+    __IO    uint32_t    EXTRA_BITS;
+} SERDES_INTF_SYSREG_TypeDef;
+
+/*------------------------------------------------------------------------------
+  SERDES PHY registers
+ */
+typedef struct
+{
+    /**
+      Control register 0
+     */
+    __IO    uint32_t    CR0;
+    
+    /**
+      Clock count for error counter decrement
+     */
+    __IO    uint32_t    ERRCNT_DEC;
+    
+    /**
+      Error counter threshold - Rx idle detect max latency
+     */
+    __IO    uint32_t    RXIDLE_MAX_ERRCNT_THR;
+    
+    /**
+      Tx Impedance ratio
+     */
+    __IO    uint32_t    IMPED_RATIO;
+    
+    /**
+      PLL F settings and PCLK ratio
+     */
+    __IO    uint32_t    PLL_F_PCLK_RATIO;
+    
+    /**
+      PLL M & N settings
+     */
+    __IO    uint32_t    PLL_M_N;
+    
+    /**
+      250ns timer base count
+     */
+    __IO    uint32_t    CNT250NS_MAX;
+    
+    /**
+      Rx Equalization amplitude ratio
+     */
+    __IO    uint32_t    RE_AMP_RATIO;
+    
+    /**
+      Rx Equalization Cut frequency
+     */
+    __IO    uint32_t    RE_CUT_RATIO;
+    
+    /**
+      Tx Amplitude ratio
+     */
+    __IO    uint32_t    TX_AMP_RATIO;
+    
+    /**
+      Tx Post-Cursor ratio
+     */
+    __IO    uint32_t    TX_PST_RATIO;
+    
+    /**
+      Tx Pre-Cursor ratio
+     */
+    __IO    uint32_t    TX_PRE_RATIO;
+    
+    /**
+      End of calibration counter
+     */
+    __IO    uint32_t    ENDCALIB_MAX;
+    
+    /**
+      Calibration stability counter
+     */
+    __IO    uint32_t    CALIB_STABILITY_COUNT;
+    
+    /**
+      Power down feature
+     */
+    __IO    uint32_t    POWER_DOWN;
+    
+    /**
+      Rx offset counter
+     */
+    __IO    uint32_t    RX_OFFSET_COUNT;
+    
+    /**
+      PLL F settings and PCLK ratio (in PCIe 5 Gbps speed)
+     */
+    __IO    uint32_t    PLL_F_PCLK_RATIO_5GBPS;
+    
+    /**
+      PLL M & N sttings (in PCIe 5 Gbps spped)
+     */
+    __IO    uint32_t    PLL_M_N_5GBPS;
+    
+    /**
+      250ns timer base count (in PCIe 5 Gbps speed)
+     */
+    __IO    uint32_t    CNT250NS_MAX_5GBPS;
+    
+    /**
+      reserved
+     */
+    __IO    uint32_t    RESERVED;
+    
+    /**
+      Tx Post-Cursor ratio with TxDeemp=0, Full swing
+     */
+    __IO    uint32_t    TX_PST_RATIO_DEEMP0_FULL;
+    
+    /**
+      Tx Pre-Cursor ratio TxDeemp=0, full swing
+     */
+    __IO    uint32_t    TX_PRE_RATIO_DEEMP0_FULL;
+    
+    /**
+      Tx Post-Cursor ratio with TxDeemp=1, Full swing
+     */
+    __IO    uint32_t    TX_PST_RATIO_DEEMP1_FULL;
+    
+    /**
+      Tx Pre-Cursor ratio TxDeemp=1, full swing
+     */
+    __IO    uint32_t    TX_PRE_RATIO_DEEMP1_FULL;
+    
+    /**
+      Tx Amplitude ratio TxMargin=0, full swing
+     */
+    __IO    uint32_t    TX_AMP_RATIO_MARGIN0_FULL;
+    
+    /**
+      Tx Amplitude ratio TxMargin=1, full swing
+     */
+    __IO    uint32_t    TX_AMP_RATIO_MARGIN1_FULL;
+    
+    /**
+      Tx Amplitude ratio TxMargin=2, full swing
+     */
+    __IO    uint32_t    TX_AMP_RATIO_MARGIN2_FULL;
+    
+    /**
+      Tx Amplitude ratio TxMargin=3, full swing
+     */
+    __IO    uint32_t    TX_AMP_RATIO_MARGIN3_FULL;
+    
+    /**
+      Tx Amplitude ratio TxMargin=4, full swing
+     */
+    __IO    uint32_t    TX_AMP_RATIO_MARGIN4_FULL;
+    
+    /**
+      Tx Amplitude ratio TxMargin=5, full swing
+     */
+    __IO    uint32_t    TX_AMP_RATIO_MARGIN5_FULL;
+    
+    /**
+      Tx Amplitude ratio TxMargin=6, full swing
+     */
+    __IO    uint32_t    TX_AMP_RATIO_MARGIN6_FULL;
+    
+    /**
+      Tx Amplitude ratio TxMargin=7, full swing
+     */
+    __IO    uint32_t    TX_AMP_RATIO_MARGIN7_FULL;
+    
+    /**
+      Rx Equalization amplitude ratio TxDeemp=0
+     */
+    __IO    uint32_t    RE_AMP_RATIO_DEEMP0;
+    
+    /**
+      Rx Equalization Cut frequency TxDeemp=0
+     */
+    __IO    uint32_t    RE_CUT_RATIO_DEEMP0;
+    
+    /**
+      Rx Equalization amplitude ratio TxDeemp=1
+     */
+    __IO    uint32_t    RE_AMP_RATIO_DEEMP1;
+    
+    /**
+      Rx Equalization Cut frequency TxDeemp=1
+     */
+    __IO    uint32_t    RE_CUT_RATIO_DEEMP1;
+    
+    /**
+      Tx Post-Cursor ratio with TxDeemp=0, Half swing
+     */
+    __IO    uint32_t    TX_PST_RATIO_DEEMP0_HALF;
+    
+    /**
+      Tx Pre-Cursor ratio TxDeemp=0, Half swing
+     */
+    __IO    uint32_t    TX_PRE_RATIO_DEEMP0_HALF;
+    
+    /**
+      Tx Post-Cursor ratio with TxDeemp=1, Half swing
+     */
+    __IO    uint32_t    TX_PST_RATIO_DEEMP1_HALF;
+    
+    /**
+      Tx Pre-Cursor ratio TxDeemp=1, Half swing
+     */
+    __IO    uint32_t    TX_PRE_RATIO_DEEMP1_HALF;
+    
+    /**
+      Tx Amplitude ratio TxMargin=0, Half swing
+     */
+    __IO    uint32_t    TX_AMP_RATIO_MARGIN0_HALF;
+    
+    /**
+      Tx Amplitude ratio TxMargin=1, Half swing
+     */
+    __IO    uint32_t    TX_AMP_RATIO_MARGIN1_HALF;
+    
+    /**
+      Tx Amplitude ratio TxMargin=2, Half swing
+     */
+    __IO    uint32_t    TX_AMP_RATIO_MARGIN2_HALF;
+    
+    /**
+      Tx Amplitude ratio TxMargin=3, Half swing
+     */
+    __IO    uint32_t    TX_AMP_RATIO_MARGIN3_HALF;
+    
+    /**
+      Tx Amplitude ratio TxMargin=4, Half swing
+     */
+    __IO    uint32_t    TX_AMP_RATIO_MARGIN4_HALF;
+    
+    /**
+      Tx Amplitude ratio TxMargin=5, Half swing
+     */
+    __IO    uint32_t    TX_AMP_RATIO_MARGIN5_HALF;
+    
+    /**
+      Tx Amplitude ratio TxMargin=6, Half swing
+     */
+    __IO    uint32_t    TX_AMP_RATIO_MARGIN6_HALF;
+    
+    /**
+      Tx Amplitude ratio TxMargin=7, Half swing
+     */
+    __IO    uint32_t    TX_AMP_RATIO_MARGIN7_HALF;
+    
+    /**
+      PMA status
+     */
+    __IO    uint32_t    PMA_STATUS;
+    
+    /**
+      Tx sweep center (RO)
+     */
+    __IO    uint32_t    TX_SWEEP_CENTER;
+    
+    /**
+      Rx seep center (RO)
+     */
+    __IO    uint32_t    RX_SWEEP_CENTER;
+    
+    /**
+      Rx Equalization sweep center (RO)
+     */
+    __IO    uint32_t    RE_SWEEP_CENTER;
+    
+    /**
+      Receiver Shift Loader parameter 0 (RO)
+     */
+    __IO    uint32_t    ATXDRR_7_0;
+    
+    /**
+      Receiver Shift Loader parameter 1 (RO)
+     */
+    __IO    uint32_t    ATXDRR_14_8;
+    
+    /**
+      Transmitter P Shift Loader parameter0-0
+     */
+    __IO    uint32_t    ATXDRP_DYN_7_0;
+    
+    /**
+      Transmitter P Shift Loader parameter0-1
+     */
+    __IO    uint32_t    ATXDRP_DYN_15_8;
+    
+    /**
+      Transmitter P Shift Loader parameter0-2
+     */
+    __IO    uint32_t    ATXDRP_DYN_20_16;
+    
+    /**
+      Transmitter A Shift Loader parameter0-0
+     */
+    __IO    uint32_t    ATXDRA_DYN_7_0;
+    
+    /**
+      Transmitter A Shift Loader parameter0-1
+     */
+    __IO    uint32_t    ATXDRA_DYN_15_8;
+    
+    /**
+      Transmitter A Shift Loader parameter0-2
+     */
+    __IO    uint32_t    ATXDRA_DYN_20_16;
+    
+    /**
+      Transmitter T Shift Loader parameter0-0
+     */
+    __IO    uint32_t    ATXDRT_DYN_7_0;
+    
+    /**
+      Transmitter T Shift Loader parameter0-1
+     */
+    __IO    uint32_t    ATXDRT_DYN_15_8;
+    
+    /**
+      Transmitter T Shift Loader parameter0-2
+     */
+    __IO    uint32_t    ATXDRT_DYN_20_16;
+    
+    /**
+      Transmitter P Shift Loader parameter 1-0 (RO)
+     */
+    __IO    uint32_t    ATXDRP_EI1_7_0;
+    
+    /**
+      Transmitter P Shift Loader parameter 1-1 (RO)
+     */
+    __IO    uint32_t    ATXDRP_EI1_15_8;
+    
+    /**
+      Transmitter P Shift Loader parameter 1-2 (RO)
+     */
+    __IO    uint32_t    ATXDRP_EI1_20_16;
+    
+    /**
+      Transmitter A Shift Loader parameter 1-0 (RO)
+     */
+    __IO    uint32_t    ATXDRA_EI1_7_0;
+    
+    /**
+      Transmitter A Shift Loader parameter 1-1 (RO)
+     */
+    __IO    uint32_t    ATXDRA_EI1_15_8;
+    
+    /**
+      Transmitter A Shift Loader parameter 1-2 (RO)
+     */
+    __IO    uint32_t    ATXDRA_EI1_20_16;
+    
+    /**
+      Transmitter T Shift Loader parameter 1-0 (RO)
+     */
+    __IO    uint32_t    ATXDRT_EI1_7_0;
+    
+    /**
+      Transmitter T Shift Loader parameter 1-1 (RO)
+     */
+    __IO    uint32_t    ATXDRT_EI1_15_8;
+    
+    /**
+      Transmitter T Shift Loader parameter 1-2 (RO)
+     */
+    __IO    uint32_t    ATXDRT_EI1_20_16;
+    
+    /**
+      Transmitter P shift Loader parameter 2-0 (RO)
+     */
+    __IO    uint32_t    ATXDRP_EI2_7_0;
+    
+    /**
+      Transmitter P shift Loader parameter 2-1 (RO)
+     */
+    __IO    uint32_t    ATXDRP_EI2_15_8;
+    
+    /**
+      Transmitter P shift Loader parameter 2-2 (RO)
+     */
+    __IO    uint32_t    ATXDRP_EI2_20_16;
+    
+    /**
+      Transmitter A Shift parametr 2-0 (RO)
+     */
+    __IO    uint32_t    ATXDRA_EI2_7_0;
+    
+    /**
+      Transmitter A Shift parametr 2-1 (RO)
+     */
+    __IO    uint32_t    ATXDRA_EI2_15_8;
+    
+    /**
+      Transmitter A Shift parametr 2-2 (RO)
+     */
+    __IO    uint32_t    ATXDRA_EI2_20_16;
+    
+    /**
+      Transmitter T Shift parametr 2-0 (RO)
+     */
+    __IO    uint32_t    ATXDRT_EI2_7_0;
+    
+    /**
+      Transmitter T Shift parametr 2-1 (RO)
+     */
+    __IO    uint32_t    ATXDRT_EI2_15_8;
+    
+    /**
+      Transmitter T Shift parametr 2-2 (RO)
+     */
+    __IO    uint32_t    ATXDRT_EI2_20_16;
+    
+    /**
+      Override calibration register (RW)
+     */
+    __IO    uint32_t    OVERRIDE_CALIB;
+    
+    /**
+      Force Receiver Shift Loader parameter 0 (RW)
+     */
+    __IO    uint32_t    FORCE_ATXDRR_7_0;
+    
+    /**
+      Force Receiver Shift Loader parameter 1 (RW)
+     */
+    __IO    uint32_t    FORCE_ATXDRR_15_8;
+    
+    /**
+      Force Receiver Shift Loader parameter 2 (RW)
+     */
+    __IO    uint32_t    FORCE_ATXDRR_20_16;
+    
+    /**
+      Force Transmitter P Shift Loader parameter 0 (RW)
+     */
+    __IO    uint32_t    FORCE_ATXDRP_7_0;
+    
+    /**
+      Force Transmitter P Shift Loader parameter 1 (RW)
+     */
+    __IO    uint32_t    FORCE_ATXDRP_15_8;
+    
+    /**
+      Force Transmitter P Shift Loader parameter 2 (RW)
+     */
+    __IO    uint32_t    FORCE_ATXDRP_20_16;
+    
+    /**
+      Force Transmitter A Shift Loader parameter 0 (RW)
+     */
+    __IO    uint32_t    FORCE_ATXDRA_7_0;
+    
+    /**
+      Force Transmitter A Shift Loader parameter 1 (RW)
+     */
+    __IO    uint32_t    FORCE_ATXDRA_15_8;
+    
+    /**
+      Force Transmitter A Shift Loader parameter 2 (RW)
+     */
+    __IO    uint32_t    FORCE_ATXDRA_20_16;
+    
+    /**
+      Force Transmitter T Shift parameter 0-0 (RO)
+     */
+    __IO    uint32_t    FORCE_ATXDRT_7_0;
+    
+    /**
+      Force Transmitter T Shift parameter 0-1 (RO)
+     */
+    __IO    uint32_t    FORCE_ATXDRT_15_8;
+    
+    /**
+      Force Transmitter T Shift parameter 0-2 (RO)
+     */
+    __IO    uint32_t    FORCE_ATXDRT_20_16;
+    
+    /**
+      RxD offset calibration result (RO)
+     */
+    __IO    uint32_t    RXD_OFFSET_CALIB_RESULT;
+    
+    /**
+      RxT offset calibration result (RO)
+     */
+    __IO    uint32_t    RXT_OFFSET_CALIB_RESULT;
+    
+    /**
+      Schmitt trigger calibration result (RO)
+     */
+    __IO    uint32_t    SCHMITT_TRIG_CALIB_RESULT;
+    
+    /**
+      Force RxD offset calibration settings (RW)
+     */
+    __IO    uint32_t    FORCE_RXD_OFFSET_CALIB;
+    
+    /**
+      Force RxT offset calibration settings (RW)
+     */
+    __IO    uint32_t    FORCE_RXT_OFFSET_CALIB;
+    
+    /**
+      Force Schmitt trigger calibration settings (RW)
+     */
+    __IO    uint32_t    FORCE_SCHMITT_TRIG_CALIB;
+    
+    /**
+      PRBS control register (RW)
+     */
+    __IO    uint32_t    PRBS_CTRL;
+    
+    /**
+      PRBS error counter register (RO)
+     */
+    __IO    uint32_t    PRBS_ERRCNT;
+    
+    /**
+      PHY reset override register (RW)
+     */
+    __IO    uint32_t    PHY_RESET_OVERRIDE;
+    
+    /**
+      PHY power override register (RW)
+     */
+    __IO    uint32_t    PHY_POWER_OVERRIDE;
+    
+    /**
+      Custom Pattern Byte 0 (RW)
+     */
+    __IO    uint32_t    CUSTOM_PATTERN_7_0;
+    
+    /**
+      Custom Pattern Byte 1 (RW)
+     */
+    __IO    uint32_t    CUSTOM_PATTERN_15_8;
+    
+    /**
+      Custom Pattern Byte 2 (RW)
+     */
+    __IO    uint32_t    CUSTOM_PATTERN_23_16;
+    
+    /**
+      Custom Pattern Byte 3 (RW)
+     */
+    __IO    uint32_t    CUSTOM_PATTERN_31_24;
+    
+    /**
+      Custom Pattern Byte 4 (RW)
+     */
+    __IO    uint32_t    CUSTOM_PATTERN_39_32;
+    
+    /**
+      Custom Pattern Byte 5 (RW)
+     */
+    __IO    uint32_t    CUSTOM_PATTERN_47_40;
+    
+    /**
+      Custom Pattern Byte 6 (RW)
+     */
+    __IO    uint32_t    CUSTOM_PATTERN55_48;
+    
+    /**
+      Custom Pattern Byte 7 (RW)
+     */
+    __IO    uint32_t    CUSTOM_PATTERN_63_56;
+    
+    /**
+      Custom Pattern Byte 8 (RW)
+     */
+    __IO    uint32_t    CUSTOM_PATTERN_71_64;
+    
+    /**
+      Custom Pattern Byte 9 (RW)
+     */
+    __IO    uint32_t    CUSTOM_PATTERN_79_72;
+    
+    /**
+      Custom Pattern Control (RW)
+     */
+    __IO    uint32_t    CUSTOM_PATTERN_CTRL;
+    
+    /**
+      Custom Pattern Status register (RO)
+     */
+    __IO    uint32_t    CUSTOM_PATTERN_STATUS;
+    
+    /**
+      PCS Loopback Control (RW)
+     */
+    __IO    uint32_t    PCS_LOOPBBACK_CTRL;
+    
+    /**
+      Gen1 Transmit PLL Current Charge Pump (RW)
+     */
+    __IO    uint32_t    GEN1_TX_PLL_CCP;
+    
+    /**
+      Gen1 Receive PLL Current Charge Pump (RW)
+     */
+    __IO    uint32_t    GEN1_RX_PLL_CCP;
+    
+    /**
+      Gen2 Transmit PLL Current Charge Pump (RW)
+     */
+    __IO    uint32_t    GEN2_TX_PLL_CCP;
+    
+    /**
+      Gen2 Receive PLL Current Charge Pump (RW)
+     */
+    __IO    uint32_t    GEN2_RX_PLL_CCP;
+    
+    /**
+      CDR PLL manual control
+     */
+    __IO    uint32_t    CDR_PLL_MANUAL_CR;
+    
+    /**
+      Reserved0
+     */
+    __IO    uint32_t    RESERVED0[6];
+    
+    /**
+      Update settings command register
+     */
+    __IO    uint32_t    UPDATE_SETTINGS;
+    
+    /**
+      Reserved1
+     */
+    __IO    uint32_t    RESERVED1[31];
+    
+    /**
+      PRBS first error cycle counter bits [7:0]
+     */
+    __IO    uint32_t    PRBS_ERR_CYC_FIRST_7_0;
+    
+    /**
+      PRBS first error cycle counter bits [15:8]
+     */
+    __IO    uint32_t    PRBS_ERR_CYC_FIRST_15_8;
+    
+    /**
+      PRBS first error cycle counter bits [23:16]
+     */
+    __IO    uint32_t    PRBS_ERR_CYC_FIRST_23_16;
+    
+    /**
+      PRBS first error cycle counter bits [31:24]
+     */
+    __IO    uint32_t    PRBS_ERR_CYC_FIRST_31_24;
+    
+    /**
+      PRBS first error cycle counter bits [39:32]
+     */
+    __IO    uint32_t    PRBS_ERR_CYC_FIRST_39_32;
+    
+    /**
+      PRBS first error cycle counter bits [47:40]
+     */
+    __IO    uint32_t    PRBS_ERR_CYC_FIRST_47_40;
+    
+    /**
+      PRBS first error cycle counter bits [49:48]
+     */
+    __IO    uint32_t    PRBS_ERR_CYC_FIRST_49_48;
+    
+    /**
+      Reserved2
+     */
+    __IO    uint32_t    RESERVED2;
+    
+    /**
+      PRBS last error cycle counter bits [7:0]
+     */
+    __IO    uint32_t    PRBS_ERR_CYC_LAST_7_0;
+    
+    /**
+      PRBS last error cycle counter bits [15:8]
+     */
+    __IO    uint32_t    PRBS_ERR_CYC_LAST_15_8;
+    
+    /**
+      PRBS last error cycle counter bits [23:16]
+     */
+    __IO    uint32_t    PRBS_ERR_CYC_LAST_23_16;
+    
+    /**
+      PRBS last error cycle counter bits [31:24]
+     */
+    __IO    uint32_t    PRBS_ERR_CYC_LAST_31_24;
+    
+    /**
+      PRBS last error cycle counter bits [39:32]
+     */
+    __IO    uint32_t    PRBS_ERR_CYC_LAST_39_32;
+    
+    /**
+      PRBS last error cycle counter bits [47:40]
+     */
+    __IO    uint32_t    PRBS_ERR_CYC_LAST_47_40;
+    
+    /**
+      PRBS last error cycle counter bits [49:48]
+     */
+    __IO    uint32_t    PRBS_ERR_CYC_LAST_49_48;
+    
+    /**
+      Reserved3
+     */
+    __IO    uint32_t    RESERVED3[81];
+    
+} SERDES_TypeDef;
+ 
+/*-------------------------------------------------------------------------*//**
+  The serdesif_regs_t data structure provides access to the complete set of the
+  SERDES Interface hardware block configuration registers. These registers are
+  accessed through the APB interface of the SERDES Interface hardware block.
+ */
+typedef struct
+{
+    /**
+      PCIe core registers.
+     */
+    PCIE_TypeDef                core;
+    
+    /**
+      SERDES macro registers.
+     */
+    SERDES_TypeDef              lane[4];
+    
+    /**
+      SERDESIF system registers.
+     */
+    SERDES_INTF_SYSREG_TypeDef     sys_regs;
+    
+} SERDESIF_TypeDef;
+
+
+/*----------------------------------------------------------------------------*/
+/*------------------------------ System Registers ----------------------------*/
+/*----------------------------------------------------------------------------*/
+typedef struct
+{
+    __IO     uint32_t    ESRAM_CR;                                 /*0X0   */
+    __IO     uint32_t    ESRAM_MAX_LAT_CR;                         /*0X4   */
+    __IO     uint32_t    DDR_CR;                                   /*0X8   */
+    __IO     uint32_t    ENVM_CR;                                  /*0XC   */
+    __IO     uint32_t    ENVM_REMAP_BASE_CR;                       /*0X10  */
+    __IO     uint32_t    ENVM_REMAP_FAB_CR;                        /*0X14  */
+    __IO     uint32_t    CC_CR;                                    /*0X18  */
+    __IO     uint32_t    CC_REGION_CR;                             /*0X1C  */
+    __IO     uint32_t    CC_LOCK_BASE_ADDR_CR;                     /*0X20  */
+    __IO     uint32_t    CC_FLUSH_INDX_CR;                         /*0X24  */
+    __IO     uint32_t    DDRB_BUF_TIMER_CR;                        /*0X28  */
+    __IO     uint32_t    DDRB_NB_ADDR_CR;                          /*0X2C  */
+    __IO     uint32_t    DDRB_NB_SIZE_CR;                          /*0X30  */
+    __IO     uint32_t    DDRB_CR;                                  /*0X34  */
+    __IO     uint32_t    EDAC_CR;                                  /*0X38  */
+    __IO     uint32_t    MASTER_WEIGHT0_CR;                        /*0X3C  */
+    __IO     uint32_t    MASTER_WEIGHT1_CR;                        /*0X40  */
+    __IO     uint32_t    SOFT_IRQ_CR;                              /*0X44  */
+    __IO     uint32_t    SOFT_RST_CR;                              /*0X48  */
+    __IO     uint32_t    M3_CR;                                    /*0X4C  */
+    __IO     uint32_t    FAB_IF_CR;                                /*0X50  */
+    __IO     uint32_t    LOOPBACK_CR;                              /*0X54  */
+    __IO     uint32_t    GPIO_SYSRESET_SEL_CR;                     /*0X58  */
+    __IO     uint32_t    GPIN_SRC_SEL_CR;                          /*0X5C  */
+    __IO     uint32_t    MDDR_CR;                                  /*0X60  */
+    __IO     uint32_t    USB_IO_INPUT_SEL_CR;                      /*0X64  */
+    __IO     uint32_t    PERIPH_CLK_MUX_SEL_CR;                    /*0X68  */
+    __IO     uint32_t    WDOG_CR;                                  /*0X6C  */
+    __IO     uint32_t    MDDR_IO_CALIB_CR;                         /*0X70  */
+    __IO     uint32_t    SPARE_OUT_CR;                             /*0X74  */
+    __IO     uint32_t    EDAC_IRQ_ENABLE_CR;                       /*0X78  */
+    __IO     uint32_t    USB_CR;                                   /*0X7C  */
+    __IO     uint32_t    ESRAM_PIPELINE_CR;                        /*0X80  */
+    __IO     uint32_t    MSS_IRQ_ENABLE_CR;                        /*0X84  */
+    __IO     uint32_t    RTC_WAKEUP_CR;                            /*0X88  */
+    __IO     uint32_t    MAC_CR;                                   /*0X8C  */
+    __IO     uint32_t    MSSDDR_PLL_STATUS_LOW_CR;                 /*0X90  */
+    __IO     uint32_t    MSSDDR_PLL_STATUS_HIGH_CR;                /*0X94  */
+    __IO     uint32_t    MSSDDR_FACC1_CR;                          /*0X98  */
+    __IO     uint32_t    MSSDDR_FACC2_CR;                          /*0X9C  */
+    __IO     uint32_t    PLL_LOCK_EN_CR;                           /*0XA0  */
+    __IO     uint32_t    MSSDDR_CLK_CALIB_CR;                      /*0XA4  */
+    __IO     uint32_t    PLL_DELAY_LINE_SEL_CR;                    /*0XA8  */
+    __IO     uint32_t    MAC_STAT_CLRONRD_CR;                      /*0XAC  */
+    __IO     uint32_t    RESET_SOURCE_CR;                          /*0XB0  */
+    __I      uint32_t    CC_DC_ERR_ADDR_SR;                        /*0XB4  */
+    __I      uint32_t    CC_IC_ERR_ADDR_SR;                        /*0XB8  */
+    __I      uint32_t    CC_SB_ERR_ADDR_SR;                        /*0XBC  */
+    __I      uint32_t    CC_DECC_ERR_ADDR_SR;                      /*0XC0  */
+    __I      uint32_t    CC_IC_MISS_CNT_SR;                        /*0XC4  */
+    __I      uint32_t    CC_IC_HIT_CNT_SR;                         /*0XC8  */
+    __I      uint32_t    CC_DC_MISS_CNT_SR;                        /*0XCC  */
+    __I      uint32_t    CC_DC_HIT_CNT_SR;                         /*0XD0  */
+    __I      uint32_t    CC_IC_TRANS_CNT_SR;                       /*0XD4  */
+    __I      uint32_t    CC_DC_TRANS_CNT_SR;                       /*0XD8  */
+    __I      uint32_t    DDRB_DS_ERR_ADR_SR;                       /*0XDC  */
+    __I      uint32_t    DDRB_HPD_ERR_ADR_SR;                      /*0XE0  */
+    __I      uint32_t    DDRB_SW_ERR_ADR_SR;                       /*0XE4  */
+    __I      uint32_t    DDRB_BUF_EMPTY_SR;                        /*0XE8  */
+    __I      uint32_t    DDRB_DSBL_DN_SR;                          /*0XEC  */
+    __I      uint32_t    ESRAM0_EDAC_CNT;                          /*0XF0  */
+    __I      uint32_t    ESRAM1_EDAC_CNT;                          /*0XF4  */
+    __I      uint32_t    CC_EDAC_CNT;                              /*0XF8  */
+    __I      uint32_t    MAC_EDAC_TX_CNT;                          /*0XFC  */
+    __I      uint32_t    MAC_EDAC_RX_CNT;                          /*0X100 */
+    __I      uint32_t    USB_EDAC_CNT;                             /*0X104 */
+    __I      uint32_t    CAN_EDAC_CNT;                             /*0X108 */
+    __I      uint32_t    ESRAM0_EDAC_ADR;                          /*0X10C */
+    __I      uint32_t    ESRAM1_EDAC_ADR;                          /*0X110 */
+    __I      uint32_t    MAC_EDAC_RX_ADR;                          /*0X114 */
+    __I      uint32_t    MAC_EDAC_TX_ADR;                          /*0X118 */
+    __I      uint32_t    CAN_EDAC_ADR;                             /*0X11C */
+    __I      uint32_t    USB_EDAC_ADR;                             /*0X120 */
+    __I      uint32_t    MM0_1_2_SECURITY;                         /*0X124 */
+    __I      uint32_t    MM4_5_FIC64_SECURITY;                     /*0X128 */
+    __I      uint32_t    MM3_6_7_8_SECURITY;                       /*0X12C */
+    __I      uint32_t    MM9_SECURITY;                             /*0X130 */
+    __I      uint32_t    M3_SR;                                    /*0X134 */
+    __I      uint32_t    ETM_COUNT_LOW;                            /*0X138 */
+    __I      uint32_t    ETM_COUNT_HIGH;                           /*0X13C */
+    __I      uint32_t    DEVICE_SR;                                /*0X140 */
+    __I      uint32_t    ENVM_PROTECT_USER;                        /*0X144 */
+    __I      uint32_t    ENVM_STATUS;                              /*0X148 */
+    __I      uint32_t    DEVICE_VERSION;                           /*0X14C */
+    __I      uint32_t    MSSDDR_PLL_STATUS;                        /*0X150 */
+    __I      uint32_t    USB_SR;                                   /*0X154 */
+    __I      uint32_t    ENVM_SR;                                  /*0X158 */
+    __I      uint32_t    SPARE_IN;                                 /*0X15C */
+    __I      uint32_t    DDRB_STATUS;                              /*0X160 */
+    __I      uint32_t    MDDR_IO_CALIB_STATUS;                     /*0X164 */
+    __I      uint32_t    MSSDDR_CLK_CALIB_STATUS;                  /*0X168 */
+    __I      uint32_t    WDOGLOAD;                                 /*0X16C */
+    __I      uint32_t    WDOGMVRP;                                 /*0X170 */
+    __I      uint32_t    USERCONFIG0;                              /*0X174 */
+    __I      uint32_t    USERCONFIG1;                              /*0X178 */
+    __I      uint32_t    USERCONFIG2;                              /*0X17C */
+    __I      uint32_t    USERCONFIG3;                              /*0X180 */
+    __I      uint32_t    FAB_PROT_SIZE;                            /*0X184 */
+    __I      uint32_t    FAB_PROT_BASE;                            /*0X188 */
+    __I      uint32_t    MSS_GPIO_DEF;                             /*0X18C */
+    __IO     uint32_t    EDAC_SR;                                  /*0X190 */
+    __IO     uint32_t    MSS_INTERNAL_SR;                          /*0X194 */
+    __IO     uint32_t    MSS_EXTERNAL_SR;                          /*0X198 */
+    __IO     uint32_t    WDOGTIMEOUTEVENT;                         /*0X19C */
+    __IO     uint32_t    CLR_MSS_COUNTERS;                         /*0X1A0 */
+    __IO     uint32_t    CLR_EDAC_COUNTERS;                        /*0X1A4 */
+    __IO     uint32_t    FLUSH_CR;                                 /*0X1A8 */
+    __IO     uint32_t    MAC_STAT_CLR_CR;                          /*0X1AC */
+    __IO     uint32_t    IOMUXCELL_CONFIG[57];                     /*0X1B0 */
+    __I      uint32_t    NVM_PROTECT_FACTORY;                      /*0X294 */
+    __I      uint32_t    DEVICE_STATUS_FIXED;                      /*0X298 */
+    __I      uint32_t    MBIST_ES0;                                /*0X29C */
+    __I      uint32_t    MBIST_ES1;                                /*0X2A0 */
+    __IO     uint32_t    MSDDR_PLL_STAUS_1;                        /*0X2A4 */
+    __I      uint32_t    REDUNDANCY_ESRAM0;                        /*0X2A8 */
+    __I      uint32_t    REDUNDANCY_ESRAM1;                        /*0X2AC */
+    __I      uint32_t    SERDESIF;                                 /*0X2B0 */
+
+} SYSREG_TypeDef;
+
+#define SYSREG_ENVM0_SOFTRESET_MASK         ( (uint32_t)0x01u << 0u )
+#define SYSREG_ENVM1_SOFTRESET_MASK         ( (uint32_t)0x01u << 1u )
+#define SYSREG_ESRAM0_SOFTRESET_MASK        ( (uint32_t)0x01u << 2u )
+#define SYSREG_ESRAM1_SOFTRESET_MASK        ( (uint32_t)0x01u << 3u )
+#define SYSREG_MAC_SOFTRESET_MASK           ( (uint32_t)0x01u << 4u )
+#define SYSREG_PDMA_SOFTRESET_MASK          ( (uint32_t)0x01u << 5u )
+#define SYSREG_TIMER_SOFTRESET_MASK         ( (uint32_t)0x01u << 6u )
+#define SYSREG_MMUART0_SOFTRESET_MASK       ( (uint32_t)0x01u << 7u )
+#define SYSREG_MMUART1_SOFTRESET_MASK       ( (uint32_t)0x01u << 8u )
+#define SYSREG_SPI0_SOFTRESET_MASK          ( (uint32_t)0x01u << 9u )
+#define SYSREG_SPI1_SOFTRESET_MASK          ( (uint32_t)0x01u << 10u )
+#define SYSREG_I2C0_SOFTRESET_MASK          ( (uint32_t)0x01u << 11u )
+#define SYSREG_I2C1_SOFTRESET_MASK          ( (uint32_t)0x01u << 12u )
+#define SYSREG_CAN_SOFTRESET_MASK           ( (uint32_t)0x01u << 13u )
+#define SYSREG_USB_SOFTRESET_MASK           ( (uint32_t)0x01u << 14u )
+#define SYSREG_COMBLK_SOFTRESET_MASK        ( (uint32_t)0x01u << 15u )
+#define SYSREG_FPGA_SOFTRESET_MASK          ( (uint32_t)0x01u << 16u )
+#define SYSREG_HPDMA_SOFTRESET_MASK         ( (uint32_t)0x01u << 17u )
+#define SYSREG_FIC32_0_SOFTRESET_MASK       ( (uint32_t)0x01u << 18u )
+#define SYSREG_FIC32_1_SOFTRESET_MASK       ( (uint32_t)0x01u << 19u )
+#define SYSREG_GPIO_SOFTRESET_MASK          ( (uint32_t)0x01u << 20u )
+#define SYSREG_GPIO_7_0_SOFTRESET_MASK      ( (uint32_t)0x01u << 21u )
+#define SYSREG_GPIO_15_8_SOFTRESET_MASK     ( (uint32_t)0x01u << 22u )
+#define SYSREG_GPIO_23_16_SOFTRESET_MASK    ( (uint32_t)0x01u << 23u )
+#define SYSREG_GPIO_31_24_SOFTRESET_MASK    ( (uint32_t)0x01u << 24u )
+#define SYSREG_MDDR_SOFTRESET_MASK          ( (uint32_t)0x01u << 25u )
+#define SYSREG_FIC64_SOFTRESET_MASK         ( (uint32_t)0x01u << 26u )
+
+/*----------------------------------------------------------------------------*/
+/*-------------------------- CoreSF2Config Registers -------------------------*/
+/*----------------------------------------------------------------------------*/
+typedef struct {
+    __IO     uint32_t   CONFIG_DONE;
+    __I      uint32_t   INIT_DONE;
+    __IO     uint32_t   CLR_INIT_DONE;
+} CoreSF2Config_TypeDef;
+
+/******************************************************************************/
+/*                         Peripheral memory map                              */
+/******************************************************************************/
+#define UART0_BASE              0x40000000u
+#define SPI0_BASE               0x40001000u
+#define I2C0_BASE               0x40002000u
+#define PDMA_BASE               0x40003000u
+#define TIMER_BASE              0x40004000u
+#define WATCHDOG_BASE           0x40005000u
+#define H2F_IRQ_CTRL_BASE       0x40006000u
+#define UART1_BASE              0x40010000u
+#define SPI1_BASE               0x40011000u
+#define I2C1_BASE               0x40012000u
+#define GPIO_BASE               0x40013000u
+#define HPDMA_BASE              0x40014000u
+#define CAN_BASE                0x40015000u
+#define COMBLK_BASE             0x40016000u
+#define RTC_BASE                0x40017000u
+#define DDR0_CFG_BASE           0x40020800u
+#define DDR1_CFG_BASE           0x40021000u
+#define CORE_SF2_CFG_BASE       0x40022000u
+#define SERDES0_CFG_BASE        0x40028000u
+#define SERDES1_CFG_BASE        0x4002C000u
+#define SYSREG_BASE             0x40038000u
+#define ETHERNET_BASE           0x40041000u
+#define USB_BASE                0x40043000u
+#define ENVM1_BASE              0x60080000u
+#define ENVM2_BASE              0x600C0000u
+
+/******************************************************************************/
+/* bitband address calculation macro                             */
+/******************************************************************************/
+#define BITBAND_ADDRESS(X)  ((X & 0xF0000000U) + 0x02000000U + ((X & 0xFFFFFU) << 5))
+
+/******************************************************************************/
+/*                         Peripheral declaration                             */
+/******************************************************************************/
+#define UART0                   ((UART_TypeDef *) UART0_BASE)
+#define SPI0                    ((SPI_TypeDef *) SPI0_BASE)
+#define I2C0                    ((I2C_TypeDef *) I2C0_BASE)
+#define I2C0_BITBAND            ((I2C_BitBand_TypeDef *) BITBAND_ADDRESS(I2C0_BASE))
+#define MAC                     ((MAC_TypeDef *) ETHERNET_BASE)
+#define PDMA                    ((PDMA_TypeDef *) PDMA_BASE)
+#define TIMER                   ((TIMER_TypeDef *) TIMER_BASE)
+#define TIMER_BITBAND           ((TIMER_BitBand_TypeDef *) BITBAND_ADDRESS(TIMER_BASE))
+#define WATCHDOG                ((WATCHDOG_TypeDef *) WATCHDOG_BASE)
+#define INTERRUPT_CTRL          ((INTERRUPT_CTRL_TypeDef *) H2F_IRQ_CTRL_BASE)
+#define INTERRUPT_CTRL_BITBAND  ((INTERRUPT_CTRL_BitBand_TypeDef *) BITBAND_ADDRESS(H2F_IRQ_CTRL_BASE))
+#define UART1                   ((UART_TypeDef *) UART1_BASE)
+#define SPI1                    ((SPI_TypeDef *) SPI1_BASE)
+#define I2C1                    ((I2C_TypeDef *) I2C1_BASE)
+#define I2C1_BITBAND            ((I2C_BitBand_TypeDef *) BITBAND_ADDRESS(I2C1_BASE))
+#define GPIO                    ((GPIO_TypeDef *) GPIO_BASE)
+#define GPIO_BITBAND            ((GPIO_BitBand_TypeDef *) BITBAND_ADDRESS(GPIO_BASE))
+#define HPDMA                   ((HPDMA_TypeDef *) HPDMA_BASE)
+#define HPDMA_BITBAND           ((HPDMA_BitBand_TypeDef *) BITBAND_ADDRESS(HPDMA_BASE))
+#define COMBLK                  ((COMBLK_TypeDef *) COMBLK_BASE)
+#define RTC                     ((RTC_TypeDef *) RTC_BASE)
+#define ENVM_1                  ((NVM_TypeDef *) ENVM1_BASE)
+#define ENVM_2                  ((NVM_TypeDef *) ENVM2_BASE)
+#define SYSREG                  ((SYSREG_TypeDef *) SYSREG_BASE)
+#define MDDR                    ((MDDR_TypeDef *) DDR0_CFG_BASE)
+#define FDDR                    ((FDDR_TypeDef *) DDR1_CFG_BASE) 
+#define USB                     ((MSS_USB_TypeDef *) USB_BASE)
+#define SERDES0                 ((SERDESIF_TypeDef *) SERDES0_CFG_BASE)
+#define SERDES1                 ((SERDESIF_TypeDef *) SERDES1_CFG_BASE)
+#define CORE_SF2_CFG            ((CoreSF2Config_TypeDef *) CORE_SF2_CFG_BASE)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* __SMARTFUSION2_CMSIS_PAL_H__ */
+
diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/CMSIS/mss_assert.h b/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/CMSIS/mss_assert.h
new file mode 100644
index 000000000..656915ffb
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/CMSIS/mss_assert.h
@@ -0,0 +1,61 @@
+/*******************************************************************************
+ * (c) Copyright 2009-2013 Microsemi SoC Products Group. All rights reserved.
+ * 
+ * Assertion implementation.
+ *
+ * This file provides the implementation of the ASSERT macro. This file can be
+ * modified to cater for project specific requirements regarding the way
+ * assertions are handled.
+ *
+ * SVN $Revision: 5279 $
+ * SVN $Date: 2013-03-22 20:48:38 +0000 (Fri, 22 Mar 2013) $
+ */
+#ifndef __MSS_ASSERT_H_
+#define __MSS_ASSERT_H_
+
+#include <assert.h>
+
+#if defined ( __GNUC__   )
+
+#if defined(NDEBUG)
+
+#define ASSERT(CHECK)
+
+#else   /* NDEBUG */
+/*
+ * SoftConsole assertion handling
+ */
+#define ASSERT(CHECK)  \
+    do { \
+        if (!(CHECK)) \
+        { \
+            __asm volatile ("BKPT\n\t"); \
+        } \
+    } while (0);
+    
+#endif  /* NDEBUG */
+
+#elif defined ( __ICCARM__ )
+/*
+ * IAR Embedded Workbench assertion handling.
+ * Call C library assert function which should result in error message
+ * displayed in debugger.
+ */
+#define ASSERT(X)   assert(X)
+
+#else
+/*
+ * Keil assertion handling.
+ * Call C library assert function which should result in error message
+ * displayed in debugger.
+ */
+
+#ifndef __MICROLIB
+  #define ASSERT(X)   assert(X)
+#else
+  #define ASSERT(X)
+#endif
+
+#endif
+
+#endif  /* __MSS_ASSERT_H_ */
diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/CMSIS/startup_gcc/debug-in-external-ram.ld b/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/CMSIS/startup_gcc/debug-in-external-ram.ld
new file mode 100644
index 000000000..95aca2335
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/CMSIS/startup_gcc/debug-in-external-ram.ld
@@ -0,0 +1,186 @@
+/*******************************************************************************
+ * (c) Copyright 2012-2013 Microsemi SoC Products Group.  All rights reserved.
+ * 
+ * SmartFusion2 Cortex-M3 linker script for creating a SoftConsole downloadable
+ * debug image executing in SmartFusion2 development board external RAM.
+ *
+ * SVN $Revision: 5269 $
+ * SVN $Date: 2013-03-21 20:53:38 +0000 (Thu, 21 Mar 2013) $
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-bigarm",
+	      "elf32-littlearm")
+GROUP(-lc -lgcc -lm)
+OUTPUT_ARCH(arm)
+ENTRY(Reset_Handler)
+SEARCH_DIR(.)
+__DYNAMIC  =  0;
+
+/*******************************************************************************
+ * Start of board customization.
+ *******************************************************************************/
+MEMORY
+{
+  /* SmartFusion2 internal eSRAM */
+  esram (rwx) : ORIGIN = 0x20000000, LENGTH = 64k
+  
+  /* SmartFusion2 development board external RAM */
+  external_ram (rwx) : ORIGIN = 0x70000000, LENGTH = 2M
+}
+
+RAM_START_ADDRESS = 0x70000000;	/* Must be the same value MEMORY region ram ORIGIN above. */
+RAM_SIZE = 64k;					/* Must be the same value MEMORY region ram LENGTH above. */
+MAIN_STACK_SIZE = 8k;			/* Cortex main stack size. */
+PROCESS_STACK_SIZE	= 4k;		/* Cortex process stack size (only available with OS extensions).*/
+
+/*******************************************************************************
+ * End of board customization.
+ *******************************************************************************/
+ 
+PROVIDE (__main_stack_start = RAM_START_ADDRESS + RAM_SIZE);
+PROVIDE (__process_stack_start = __main_stack_start - MAIN_STACK_SIZE);
+PROVIDE (_estack = __main_stack_start);
+PROVIDE (__mirrored_nvm = 0);   /* Indicate to startup code that NVM is not mirrored to VMA address .text copy is required. */
+
+SECTIONS
+{
+  .init :
+  {
+    __vector_table_vma_base_address = .;
+    *(.isr_vector)
+    . = ALIGN(0x4);
+  } >esram
+  
+  .text :
+  {
+    CREATE_OBJECT_SYMBOLS
+    __text_load = LOADADDR(.text);
+    __text_start = .;
+    *(.text .text.* .gnu.linkonce.t.*)
+    *(.plt)
+    *(.gnu.warning)
+    *(.glue_7t) *(.glue_7) *(.vfp11_veneer)
+
+    . = ALIGN(0x4);
+    /* These are for running static constructors and destructors under ELF.  */
+    KEEP (*crtbegin.o(.ctors))
+    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*crtend.o(.ctors))
+    KEEP (*crtbegin.o(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*crtend.o(.dtors))
+
+    *(.rodata .rodata.* .gnu.linkonce.r.*)
+
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    *(.gcc_except_table) 
+    *(.eh_frame_hdr)
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(.fini_array))
+    KEEP (*(SORT(.fini_array.*)))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >external_ram
+  /* .ARM.exidx is sorted, so has to go in its own output section.  */
+   __exidx_start = .;
+  .ARM.exidx :
+  {
+    *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+  } >external_ram
+  __exidx_end = .;
+  _etext = .;
+  PROVIDE(__text_end = .);
+
+  .data :
+  {
+    __data_load = LOADADDR (.data);
+    _sidata = LOADADDR (.data);
+    __data_start = .;
+    _sdata = .;
+    KEEP(*(.jcr))
+    *(.got.plt) *(.got)
+    *(.shdata)
+    *(.data .data.* .gnu.linkonce.d.*)
+    . = ALIGN (4);
+    _edata = .;
+  } >external_ram 
+
+  .bss :
+  {
+    __bss_start__ = . ;
+    _sbss = .;
+    *(.shbss)
+    *(.bss .bss.* .gnu.linkonce.b.*)
+    *(COMMON)
+    . = ALIGN (8);
+    __bss_end__ = .;
+    _end = .;
+    __end = _end;
+    _ebss = .;
+    PROVIDE(end = .);
+  } >external_ram 
+
+  /* 
+   * The .stack section is only specified here in order for the linker to generate
+   * an error if the esram is full.
+   */
+  .stack :
+  {
+  	. = ALIGN(4);
+    . += PROCESS_STACK_SIZE;
+    . = ALIGN(4);
+    . += MAIN_STACK_SIZE;
+    . = ALIGN(4);
+  } >external_ram
+  
+  .stab 0 (NOLOAD) :
+  {
+    *(.stab)
+  }
+
+  .stabstr 0 (NOLOAD) :
+  {
+    *(.stabstr)
+  }
+  /* DWARF debug sections.
+     Symbols in the DWARF debugging sections are relative to the beginning
+     of the section so we begin them at 0.  */
+  /* DWARF 1 */
+  .debug          0 : { *(.debug) }
+  .line           0 : { *(.line) }
+  /* GNU DWARF 1 extensions */
+  .debug_srcinfo  0 : { *(.debug_srcinfo) }
+  .debug_sfnames  0 : { *(.debug_sfnames) }
+  /* DWARF 1.1 and DWARF 2 */
+  .debug_aranges  0 : { *(.debug_aranges) }
+  .debug_pubnames 0 : { *(.debug_pubnames) }
+  /* DWARF 2 */
+  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+  .debug_abbrev   0 : { *(.debug_abbrev) }
+  .debug_line     0 : { *(.debug_line) }
+  .debug_frame    0 : { *(.debug_frame) }
+  .debug_str      0 : { *(.debug_str) }
+  .debug_loc      0 : { *(.debug_loc) }
+  .debug_macinfo  0 : { *(.debug_macinfo) }
+  /* SGI/MIPS DWARF 2 extensions */
+  .debug_weaknames 0 : { *(.debug_weaknames) }
+  .debug_funcnames 0 : { *(.debug_funcnames) }
+  .debug_typenames 0 : { *(.debug_typenames) }
+  .debug_varnames  0 : { *(.debug_varnames) }
+  .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }
+  .ARM.attributes 0 : { KEEP (*(.ARM.attributes)) }
+  /DISCARD/ : { *(.note.GNU-stack) *(.isr_vector) }
+}
diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/CMSIS/startup_gcc/debug-in-microsemi-smartfusion2-envm.ld b/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/CMSIS/startup_gcc/debug-in-microsemi-smartfusion2-envm.ld
new file mode 100644
index 000000000..59daa1873
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/CMSIS/startup_gcc/debug-in-microsemi-smartfusion2-envm.ld
@@ -0,0 +1,184 @@
+/*******************************************************************************
+ * (c) Copyright 2012-2013 Microsemi SoC Products Group.  All rights reserved.
+ * 
+ * SmartFusion2 Cortex-M3 linker script for creating a SoftConsole downloadable
+ * debug image executing in SmartFusion2 internal eNVM.
+ *
+ * SVN $Revision: 5269 $
+ * SVN $Date: 2013-03-21 20:53:38 +0000 (Thu, 21 Mar 2013) $
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-bigarm",
+	      "elf32-littlearm")
+GROUP(-lc -lgcc -lm)
+OUTPUT_ARCH(arm)
+ENTRY(Reset_Handler)
+SEARCH_DIR(.)
+__DYNAMIC  =  0;
+
+/*******************************************************************************
+ * Start of board customization.
+ *******************************************************************************/
+MEMORY
+{
+  /*
+   * WARNING: The words "SOFTCONSOLE", "FLASH", and "USE", the colon ":", and
+   *          the name of the type of flash memory are all in a specific order.
+   *          Please do not modify that comment line, in order to ensure
+   *          debugging of your application will use the flash memory correctly.
+   */
+
+  /* SOFTCONSOLE FLASH USE: microsemi-smartfusion2-envm */
+  rom (rx)  : ORIGIN = 0x60000000, LENGTH = 256k
+  
+  /* SmartFusion2 internal eNVM mirrored to 0x00000000 */
+  romMirror (rx) : ORIGIN = 0x00000000, LENGTH = 256k
+
+  /* SmartFusion2 internal eSRAM */
+  ram (rwx) : ORIGIN = 0x20000000, LENGTH = 64k
+}
+
+RAM_START_ADDRESS = 0x20000000; 	/* Must be the same value MEMORY region ram ORIGIN above. */
+RAM_SIZE = 64k; 					/* Must be the same value MEMORY region ram LENGTH above. */
+MAIN_STACK_SIZE = 8k; 				/* Cortex main stack size. */
+PROCESS_STACK_SIZE	= 4k; 			/* Cortex process stack size (only available with OS extensions).*/
+
+/*******************************************************************************
+ * End of board customization.
+ *******************************************************************************/
+ 
+PROVIDE (__main_stack_start = RAM_START_ADDRESS + RAM_SIZE);
+PROVIDE (__process_stack_start = __main_stack_start - MAIN_STACK_SIZE);
+PROVIDE (_estack = __main_stack_start);
+PROVIDE (__mirrored_nvm = 1);   /* Indicate to startup code that NVM is mirrored to VMA address and no text copy is required. */
+
+SECTIONS
+{
+  .init :
+  {
+    __vector_table_vma_base_address = .;
+    *(.isr_vector)
+    . = ALIGN(0x4);
+  } >romMirror AT>rom
+  
+  .text :
+  {
+    CREATE_OBJECT_SYMBOLS
+    __text_load = LOADADDR(.text);
+    __text_start = .;
+    
+    *(.text .text.* .gnu.linkonce.t.*)
+    *(.plt)
+    *(.gnu.warning)
+    *(.glue_7t) *(.glue_7) *(.vfp11_veneer)
+
+    . = ALIGN(0x4);
+    /* These are for running static constructors and destructors under ELF.  */
+    KEEP (*crtbegin.o(.ctors))
+    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*crtend.o(.ctors))
+    KEEP (*crtbegin.o(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*crtend.o(.dtors))
+
+    *(.rodata .rodata.* .gnu.linkonce.r.*)
+
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    *(.gcc_except_table) 
+    *(.eh_frame_hdr)
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(.fini_array))
+    KEEP (*(SORT(.fini_array.*)))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >romMirror AT>rom
+
+  /* .ARM.exidx is sorted, so has to go in its own output section.  */
+   __exidx_start = .;
+  .ARM.exidx :
+  {
+    *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+  } >ram AT>rom
+  __exidx_end = .;
+  _etext = .;
+
+  .data :
+  {
+    __data_load = LOADADDR(.data);
+    _sidata = LOADADDR (.data);
+    __data_start = .;
+    _sdata = .;
+    KEEP(*(.jcr))
+    *(.got.plt) *(.got)
+    *(.shdata)
+    *(.data .data.* .gnu.linkonce.d.*)
+    . = ALIGN (4);
+  	_edata = .;
+  } >ram AT>rom
+
+  .bss :
+  {
+    __bss_start__ = . ;
+    _sbss = .;
+    *(.shbss)
+    *(.bss .bss.* .gnu.linkonce.b.*)
+    *(COMMON)
+    . = ALIGN (8);
+    __bss_end__ = .;
+    _end = .;
+    __end = _end;
+    _ebss = .;
+    PROVIDE(end = .);
+  } >ram AT>rom
+
+  .stab 0 (NOLOAD) :
+  {
+    *(.stab)
+  }
+
+  .stabstr 0 (NOLOAD) :
+  {
+    *(.stabstr)
+  }
+  /* DWARF debug sections.
+     Symbols in the DWARF debugging sections are relative to the beginning
+     of the section so we begin them at 0.  */
+  /* DWARF 1 */
+  .debug          0 : { *(.debug) }
+  .line           0 : { *(.line) }
+  /* GNU DWARF 1 extensions */
+  .debug_srcinfo  0 : { *(.debug_srcinfo) }
+  .debug_sfnames  0 : { *(.debug_sfnames) }
+  /* DWARF 1.1 and DWARF 2 */
+  .debug_aranges  0 : { *(.debug_aranges) }
+  .debug_pubnames 0 : { *(.debug_pubnames) }
+  /* DWARF 2 */
+  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+  .debug_abbrev   0 : { *(.debug_abbrev) }
+  .debug_line     0 : { *(.debug_line) }
+  .debug_frame    0 : { *(.debug_frame) }
+  .debug_str      0 : { *(.debug_str) }
+  .debug_loc      0 : { *(.debug_loc) }
+  .debug_macinfo  0 : { *(.debug_macinfo) }
+  /* SGI/MIPS DWARF 2 extensions */
+  .debug_weaknames 0 : { *(.debug_weaknames) }
+  .debug_funcnames 0 : { *(.debug_funcnames) }
+  .debug_typenames 0 : { *(.debug_typenames) }
+  .debug_varnames  0 : { *(.debug_varnames) }
+  .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }
+  .ARM.attributes 0 : { KEEP (*(.ARM.attributes)) }
+  /DISCARD/ : { *(.note.GNU-stack)  }
+}
diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/CMSIS/startup_gcc/debug-in-microsemi-smartfusion2-esram.ld b/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/CMSIS/startup_gcc/debug-in-microsemi-smartfusion2-esram.ld
new file mode 100644
index 000000000..15e56c06c
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/CMSIS/startup_gcc/debug-in-microsemi-smartfusion2-esram.ld
@@ -0,0 +1,178 @@
+/*******************************************************************************
+ * (c) Copyright 2012-2013 Microsemi SoC Products Group.  All rights reserved.
+ * 
+ * SmartFusion2 Cortex-M3 linker script for creating a SoftConsole downloadable
+ * debug image executing in SmartFusion2 internal eSRAM.
+ *
+ * SVN $Revision: 5269 $
+ * SVN $Date: 2013-03-21 20:53:38 +0000 (Thu, 21 Mar 2013) $
+ */
+
+ OUTPUT_FORMAT("elf32-littlearm", "elf32-bigarm",
+	      "elf32-littlearm")
+GROUP(-lc -lgcc -lm)
+OUTPUT_ARCH(arm)
+ENTRY(Reset_Handler)
+SEARCH_DIR(.)
+__DYNAMIC  =  0;
+
+/*******************************************************************************
+ * Start of board customization.
+ *******************************************************************************/
+MEMORY
+{
+  /* SmartFusion2 internal eSRAM */
+  ram (rwx) : ORIGIN = 0x20000000, LENGTH = 64k
+}
+
+RAM_START_ADDRESS = 0x20000000;	/* Must be the same value MEMORY region ram ORIGIN above. */
+RAM_SIZE = 64k;					/* Must be the same value MEMORY region ram LENGTH above. */
+MAIN_STACK_SIZE = 8k;			/* Cortex main stack size. */
+PROCESS_STACK_SIZE	= 4k;		/* Cortex process stack size (only available with OS extensions).*/
+
+/*******************************************************************************
+ * End of board customization.
+ *******************************************************************************/
+ 
+PROVIDE (__main_stack_start = RAM_START_ADDRESS + RAM_SIZE);
+PROVIDE (__process_stack_start = __main_stack_start - MAIN_STACK_SIZE);
+PROVIDE (_estack = __main_stack_start);
+PROVIDE (__mirrored_nvm = 0);   /* Indicate to startup code that NVM is not mirrored to VMA address .text copy is required. */
+
+SECTIONS
+{
+  .text :
+  {
+    CREATE_OBJECT_SYMBOLS
+    __text_load = LOADADDR(.text);
+    __text_start = .;
+    __vector_table_vma_base_address = .;    
+    *(.isr_vector)
+    *(.text .text.* .gnu.linkonce.t.*)
+    *(.plt)
+    *(.gnu.warning)
+    *(.glue_7t) *(.glue_7) *(.vfp11_veneer)
+
+    . = ALIGN(0x4);
+    /* These are for running static constructors and destructors under ELF.  */
+    KEEP (*crtbegin.o(.ctors))
+    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*crtend.o(.ctors))
+    KEEP (*crtbegin.o(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*crtend.o(.dtors))
+
+    *(.rodata .rodata.* .gnu.linkonce.r.*)
+
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    *(.gcc_except_table) 
+    *(.eh_frame_hdr)
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(.fini_array))
+    KEEP (*(SORT(.fini_array.*)))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >ram
+  /* .ARM.exidx is sorted, so has to go in its own output section.  */
+   __exidx_start = .;
+  .ARM.exidx :
+  {
+    *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+  } >ram
+  __exidx_end = .;
+  _etext = .;
+  PROVIDE(__text_end = .);
+
+  .data :
+  {
+    __data_load = LOADADDR (.data);
+    _sidata = LOADADDR (.data);
+    __data_start = .;
+    _sdata = .;
+    KEEP(*(.jcr))
+    *(.got.plt) *(.got)
+    *(.shdata)
+    *(.data .data.* .gnu.linkonce.d.*)
+    . = ALIGN (4);
+    _edata = .;
+  } >ram 
+
+  .bss :
+  {
+    __bss_start__ = . ;
+    _sbss = .;
+    *(.shbss)
+    *(.bss .bss.* .gnu.linkonce.b.*)
+    *(COMMON)
+    . = ALIGN (8);
+    __bss_end__ = .;
+    _end = .;
+    __end = _end;
+    _ebss = .;
+    PROVIDE(end = .);
+  } >ram 
+
+  /* 
+   * The .stack section is only specified here in order for the linker to generate
+   * an error if the ram is full.
+   */
+  .stack :
+  {
+  	. = ALIGN(4);
+    . += PROCESS_STACK_SIZE;
+    . = ALIGN(4);
+    . += MAIN_STACK_SIZE;
+    . = ALIGN(4);
+  } >ram
+  
+  .stab 0 (NOLOAD) :
+  {
+    *(.stab)
+  }
+
+  .stabstr 0 (NOLOAD) :
+  {
+    *(.stabstr)
+  }
+  /* DWARF debug sections.
+     Symbols in the DWARF debugging sections are relative to the beginning
+     of the section so we begin them at 0.  */
+  /* DWARF 1 */
+  .debug          0 : { *(.debug) }
+  .line           0 : { *(.line) }
+  /* GNU DWARF 1 extensions */
+  .debug_srcinfo  0 : { *(.debug_srcinfo) }
+  .debug_sfnames  0 : { *(.debug_sfnames) }
+  /* DWARF 1.1 and DWARF 2 */
+  .debug_aranges  0 : { *(.debug_aranges) }
+  .debug_pubnames 0 : { *(.debug_pubnames) }
+  /* DWARF 2 */
+  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+  .debug_abbrev   0 : { *(.debug_abbrev) }
+  .debug_line     0 : { *(.debug_line) }
+  .debug_frame    0 : { *(.debug_frame) }
+  .debug_str      0 : { *(.debug_str) }
+  .debug_loc      0 : { *(.debug_loc) }
+  .debug_macinfo  0 : { *(.debug_macinfo) }
+  /* SGI/MIPS DWARF 2 extensions */
+  .debug_weaknames 0 : { *(.debug_weaknames) }
+  .debug_funcnames 0 : { *(.debug_funcnames) }
+  .debug_typenames 0 : { *(.debug_typenames) }
+  .debug_varnames  0 : { *(.debug_varnames) }
+  .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }
+  .ARM.attributes 0 : { KEEP (*(.ARM.attributes)) }
+  /DISCARD/ : { *(.note.GNU-stack) *(.isr_vector) }
+}
diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/CMSIS/startup_gcc/newlib_stubs.c b/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/CMSIS/startup_gcc/newlib_stubs.c
new file mode 100644
index 000000000..c6d794da1
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/CMSIS/startup_gcc/newlib_stubs.c
@@ -0,0 +1,273 @@
+/*******************************************************************************
+ * (c) Copyright 2009-2013 Microsemi SoC Products Group.  All rights reserved.
+ * 
+ * Stubs for Newlib system calls.
+ *  
+ * SVN $Revision: 5269 $
+ * SVN $Date: 2013-03-21 20:53:38 +0000 (Thu, 21 Mar 2013) $
+ */
+#include <stdlib.h>
+#include <sys/unistd.h>
+#include <sys/stat.h>
+#include <sys/times.h>
+#include <errno.h>
+
+/*==============================================================================
+ * Redirection of standard output to a SmartFusion2 MSS UART.
+ *------------------------------------------------------------------------------
+ * A default implementation for the redirection of the output of printf() to a
+ * UART is provided at the bottom of this file. This redirection is enabled by
+ * adding the symbol/define MICROSEMI_STDIO_THRU_MMUART0 or
+ * MICROSEMI_STDIO_THRU_MMUART0 to your project settings and specifying the baud
+ * rate using the MICROSEMI_STDIO_BAUD_RATE define.
+ */
+#ifdef MICROSEMI_STDIO_THRU_MMUART0
+#ifndef MICROSEMI_STDIO_THRU_UART
+#define MICROSEMI_STDIO_THRU_UART
+#endif
+#endif  /* MICROSEMI_STDIO_THRU_MMUART0 */
+
+#ifdef MICROSEMI_STDIO_THRU_MMUART1
+#ifndef MICROSEMI_STDIO_THRU_UART
+#define MICROSEMI_STDIO_THRU_UART
+#endif
+#endif  /* MICROSEMI_STDIO_THRU_MMUART1 */
+
+/*
+ * Select which MMUART will be used for stdio and what baud rate will be used.
+ * Default to 57600 baud if no baud rate is specified using the
+ * MICROSEMI_STDIO_BAUD_RATE #define.
+ */ 
+#ifdef MICROSEMI_STDIO_THRU_UART
+#include "../../drivers/mss_uart/mss_uart.h"
+
+#ifndef MICROSEMI_STDIO_BAUD_RATE
+#define MICROSEMI_STDIO_BAUD_RATE  MSS_UART_57600_BAUD
+#endif
+
+#ifdef MICROSEMI_STDIO_THRU_MMUART0
+static mss_uart_instance_t * const gp_my_uart = &g_mss_uart0;
+#else
+static mss_uart_instance_t * const gp_my_uart = &g_mss_uart1;
+#endif
+
+/*------------------------------------------------------------------------------
+ * Global flag used to indicate if the UART driver needs to be initialized.
+ */
+static int g_stdio_uart_init_done = 0;
+
+#endif /* MICROSEMI_STDIO_THRU_UART */
+
+/*==============================================================================
+ * Environment variables.
+ * A pointer to a list of environment variables and their values. For a minimal
+ * environment, this empty list is adequate:
+ */
+char *__env[1] = { 0 };
+char **environ = __env;
+
+/*==============================================================================
+ * Close a file.
+ */
+int _close(int file)
+{
+    return -1;
+}
+
+/*==============================================================================
+ * Transfer control to a new process.
+ */
+int _execve(char *name, char **argv, char **env)
+{
+    errno = ENOMEM;
+    return -1;
+}
+
+/*==============================================================================
+ * Exit a program without cleaning up files.
+ */
+void _exit( int code )
+{
+    /* Should we force a system reset? */
+    while( 1 )
+    {
+        ;
+    }
+}
+
+/*==============================================================================
+ * Create a new process.
+ */
+int _fork(void)
+{
+    errno = EAGAIN;
+    return -1;
+}
+
+/*==============================================================================
+ * Status of an open file.
+ */
+int _fstat(int file, struct stat *st)
+{
+    st->st_mode = S_IFCHR;
+    return 0;
+}
+
+/*==============================================================================
+ * Process-ID
+ */
+int _getpid(void)
+{
+    return 1;
+}
+
+/*==============================================================================
+ * Query whether output stream is a terminal.
+ */
+int _isatty(int file)
+{
+    return 1;
+}
+
+/*==============================================================================
+ * Send a signal.
+ */
+int _kill(int pid, int sig)
+{
+    errno = EINVAL;
+    return -1;
+}
+
+/*==============================================================================
+ * Establish a new name for an existing file.
+ */
+int _link(char *old, char *new)
+{
+    errno = EMLINK;
+    return -1;
+}
+
+/*==============================================================================
+ * Set position in a file.
+ */
+int _lseek(int file, int ptr, int dir)
+{
+    return 0;
+}
+
+/*==============================================================================
+ * Open a file.
+ */
+int _open(const char *name, int flags, int mode)
+{
+    return -1;
+}
+
+/*==============================================================================
+ * Read from a file.
+ */
+int _read(int file, char *ptr, int len)
+{
+    return 0;
+}
+
+/*==============================================================================
+ * Write to a file. libc subroutines will use this system routine for output to
+ * all files, including stdout�so if you need to generate any output, for
+ * example to a serial port for debugging, you should make your minimal write
+ * capable of doing this.
+ */
+int _write_r( void * reent, int file, char * ptr, int len )
+{
+#ifdef MICROSEMI_STDIO_THRU_UART
+    /*--------------------------------------------------------------------------
+     * Initialize the UART driver if it is the first time this function is
+     * called.
+     */
+    if(!g_stdio_uart_init_done)
+    {
+        MSS_UART_init(gp_my_uart,
+                      MICROSEMI_STDIO_BAUD_RATE,
+                      MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY);
+                      
+        g_stdio_uart_init_done = 1;
+    }
+    
+    /*--------------------------------------------------------------------------
+     * Output text to the UART.
+     */
+    MSS_UART_polled_tx(gp_my_uart, (uint8_t *)ptr, len);
+    
+    return len;
+#else   /* MICROSEMI_STDIO_THRU_UART */
+    return 0;
+#endif  /* MICROSEMI_STDIO_THRU_UART */
+}
+
+/*==============================================================================
+ * Increase program data space. As malloc and related functions depend on this,
+ * it is useful to have a working implementation. The following suffices for a
+ * standalone system; it exploits the symbol _end automatically defined by the
+ * GNU linker. 
+ */
+caddr_t _sbrk(int incr)
+{
+    extern char _end;        /* Defined by the linker */
+    static char *heap_end;
+    char *prev_heap_end;
+    char * stack_ptr;
+    
+    if (heap_end == 0)
+    {
+      heap_end = &_end;
+    }
+    
+    prev_heap_end = heap_end;
+    asm volatile ("MRS %0, msp" : "=r" (stack_ptr) );
+    if (heap_end + incr > stack_ptr)
+    {
+      _write_r ((void *)0, 1, "Heap and stack collision\n", 25);
+      _exit (1);
+    }
+  
+    heap_end += incr;
+    return (caddr_t) prev_heap_end;
+}
+
+/*==============================================================================
+ * Status of a file (by name).
+ */
+int _stat(char *file, struct stat *st)
+{
+    st->st_mode = S_IFCHR;
+    return 0;
+}
+
+/*==============================================================================
+ * Timing information for current process.
+ */
+int _times(struct tms *buf)
+{
+    return -1;
+}
+
+/*==============================================================================
+ * Remove a file's directory entry.
+ */
+int _unlink(char *name)
+{
+    errno = ENOENT;
+    return -1;
+}
+
+/*==============================================================================
+ * Wait for a child process.
+ */
+int _wait(int *status)
+{
+    errno = ECHILD;
+    return -1;
+}
+
+
+
diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/CMSIS/startup_gcc/production-execute-in-place.ld b/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/CMSIS/startup_gcc/production-execute-in-place.ld
new file mode 100644
index 000000000..9dca87a18
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/CMSIS/startup_gcc/production-execute-in-place.ld
@@ -0,0 +1,172 @@
+/*******************************************************************************
+ * (c) Copyright 2009-2013 Microsemi SoC Products Group.  All rights reserved.
+ * 
+ * SmartFusion2 Cortex-M3 linker script creating an executable image for use in
+ * the Libero flow for executing code in place in internal eNVM.
+ *
+ * SVN $Revision: 5269 $
+ * SVN $Date: 2013-03-21 20:53:38 +0000 (Thu, 21 Mar 2013) $
+ */
+OUTPUT_FORMAT("elf32-littlearm", "elf32-bigarm",
+	      "elf32-littlearm")
+GROUP(-lc -lgcc -lm)
+OUTPUT_ARCH(arm)
+ENTRY(Reset_Handler)
+SEARCH_DIR(.)
+__DYNAMIC  =  0;
+
+/*******************************************************************************
+ * Start of board customization.
+ *******************************************************************************/
+MEMORY
+{
+  /* SmartFusion2 internal eNVM */
+  rom (rx) : ORIGIN = 0, LENGTH = 256k
+  
+  /* SmartFusion2 internal eSRAM */
+  ram (rwx) : ORIGIN = 0x20000000, LENGTH = 64k
+}
+
+RAM_START_ADDRESS = 0x20000000;	/* Must be the same value as MEMORY region ram ORIGIN above. */
+RAM_SIZE = 64k;					/* Must be the same value as MEMORY region ram LENGTH above. */
+MAIN_STACK_SIZE = 8k;			/* Cortex main stack size. */
+PROCESS_STACK_SIZE	= 4k;		/* Cortex process stack size (only available with OS extensions).*/
+
+/*******************************************************************************
+ * End of board customization.
+ *******************************************************************************/
+ 
+PROVIDE (__main_stack_start = RAM_START_ADDRESS + RAM_SIZE);
+PROVIDE (__process_stack_start = __main_stack_start - MAIN_STACK_SIZE);
+PROVIDE (_estack = __main_stack_start);
+PROVIDE (__mirrored_nvm = 0);   /* Indicate to startup code that NVM is not mirrored to VMA address .text copy is required. */
+
+SECTIONS
+{
+  .reset :
+  {
+    __vector_table_vma_base_address = .;
+    *(.isr_vector)
+    . = ALIGN(0x4);
+  } >rom
+  
+  .text :
+  {
+    CREATE_OBJECT_SYMBOLS
+    __text_load = LOADADDR(.text);
+    __text_start = .;
+    
+    *(.text .text.* .gnu.linkonce.t.*)
+    *(.plt)
+    *(.gnu.warning)
+    *(.glue_7t) *(.glue_7) *(.vfp11_veneer)
+
+    . = ALIGN(0x4);
+    /* These are for running static constructors and destructors under ELF.  */
+    KEEP (*crtbegin.o(.ctors))
+    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*crtend.o(.ctors))
+    KEEP (*crtbegin.o(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*crtend.o(.dtors))
+
+    *(.rodata .rodata.* .gnu.linkonce.r.*)
+
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    *(.gcc_except_table) 
+    *(.eh_frame_hdr)
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(.fini_array))
+    KEEP (*(SORT(.fini_array.*)))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >rom
+  /* .ARM.exidx is sorted, so has to go in its own output section.  */
+   __exidx_start = .;
+  .ARM.exidx :
+  {
+    *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+  } >rom
+  __exidx_end = .;
+  _etext = .;
+
+  .data :
+  {
+    __data_load = LOADADDR(.data);
+    _sidata = LOADADDR (.data);
+    __data_start = .;
+    _sdata = .;
+    KEEP(*(.jcr))
+    *(.got.plt) *(.got)
+    *(.shdata)
+    *(.data .data.* .gnu.linkonce.d.*)
+    . = ALIGN (4);
+  	_edata = .;
+  } >ram AT>rom
+
+  .bss :
+  {
+    __bss_start__ = . ;
+    _sbss = .;
+    *(.shbss)
+    *(.bss .bss.* .gnu.linkonce.b.*)
+    *(COMMON)
+    . = ALIGN (8);
+    __bss_end__ = .;
+    _end = .;
+    __end = _end;
+    _ebss = .;
+    PROVIDE(end = .);
+  } >ram AT>rom
+
+  .stab 0 (NOLOAD) :
+  {
+    *(.stab)
+  }
+
+  .stabstr 0 (NOLOAD) :
+  {
+    *(.stabstr)
+  }
+  /* DWARF debug sections.
+     Symbols in the DWARF debugging sections are relative to the beginning
+     of the section so we begin them at 0.  */
+  /* DWARF 1 */
+  .debug          0 : { *(.debug) }
+  .line           0 : { *(.line) }
+  /* GNU DWARF 1 extensions */
+  .debug_srcinfo  0 : { *(.debug_srcinfo) }
+  .debug_sfnames  0 : { *(.debug_sfnames) }
+  /* DWARF 1.1 and DWARF 2 */
+  .debug_aranges  0 : { *(.debug_aranges) }
+  .debug_pubnames 0 : { *(.debug_pubnames) }
+  /* DWARF 2 */
+  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+  .debug_abbrev   0 : { *(.debug_abbrev) }
+  .debug_line     0 : { *(.debug_line) }
+  .debug_frame    0 : { *(.debug_frame) }
+  .debug_str      0 : { *(.debug_str) }
+  .debug_loc      0 : { *(.debug_loc) }
+  .debug_macinfo  0 : { *(.debug_macinfo) }
+  /* SGI/MIPS DWARF 2 extensions */
+  .debug_weaknames 0 : { *(.debug_weaknames) }
+  .debug_funcnames 0 : { *(.debug_funcnames) }
+  .debug_typenames 0 : { *(.debug_typenames) }
+  .debug_varnames  0 : { *(.debug_varnames) }
+  .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }
+  .ARM.attributes 0 : { KEEP (*(.ARM.attributes)) }
+  /DISCARD/ : { *(.note.GNU-stack)  }
+}
diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/CMSIS/startup_gcc/production-relocate-executable.ld b/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/CMSIS/startup_gcc/production-relocate-executable.ld
new file mode 100644
index 000000000..89c42e376
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/CMSIS/startup_gcc/production-relocate-executable.ld
@@ -0,0 +1,178 @@
+/*******************************************************************************
+ * (c) Copyright 2009-2013 Microsemi SoC Products Group.  All rights reserved.
+ * 
+ * SmartFusion2 Cortex-M3 linker script creating an executable image for use in
+ * the Libero flow for relocating executable from internal eNVM to external RAM
+ * before starting execution.
+ *
+ * SVN $Revision: 5269 $
+ * SVN $Date: 2013-03-21 20:53:38 +0000 (Thu, 21 Mar 2013) $
+ */
+OUTPUT_FORMAT("elf32-littlearm", "elf32-bigarm",
+	      "elf32-littlearm")
+GROUP(-lc -lgcc -lm)
+OUTPUT_ARCH(arm)
+ENTRY(Reset_Handler)
+SEARCH_DIR(.)
+__DYNAMIC  =  0;
+
+/*******************************************************************************
+ * Start of board customization.
+ *******************************************************************************/
+MEMORY
+{
+  /* SmartFusion2 internal eNVM */
+  rom (rx) : ORIGIN = 0, LENGTH = 256k
+  
+  /* SmartFusion2 internal eSRAM */
+  esram (rwx) : ORIGIN = 0x20000000, LENGTH = 64k
+  
+  /* SmartFusion2 development board external RAM */
+  external_ram (rwx) : ORIGIN = 0x70000000, LENGTH = 2M
+}
+
+RAM_START_ADDRESS = 0x20000000;	/* Must be the same value as MEMORY region esram ORIGIN above. */
+RAM_SIZE = 64k;					/* Must be the same value as MEMORY region esram LENGTH above. */
+MAIN_STACK_SIZE = 8k;			/* Cortex main stack size. */
+PROCESS_STACK_SIZE	= 4k;		/* Cortex process stack size (only available with OS extensions).*/
+
+/*******************************************************************************
+ * End of board customization.
+ *******************************************************************************/
+ 
+PROVIDE (__main_stack_start = RAM_START_ADDRESS + RAM_SIZE);
+PROVIDE (__process_stack_start = __main_stack_start - MAIN_STACK_SIZE);
+PROVIDE (_estack = __main_stack_start);
+PROVIDE (__mirrored_nvm = 0);   /* Indicate to startup code that NVM is not mirrored to VMA address .text copy is required. */
+
+SECTIONS
+{
+  .reset :
+  {
+    __vector_table_vma_base_address = .;
+    *(.isr_vector)
+    /* SystemInit() is called before relocation to RAM so keep in ROM */
+	*system_m2sxxx.o(.text*)    
+    . = ALIGN(0x4);
+  } >rom
+  
+  .text :
+  {
+    CREATE_OBJECT_SYMBOLS
+    __text_load = LOADADDR(.text);
+    __text_start = .;
+    
+    *(.text .text.* .gnu.linkonce.t.*)
+    *(.plt)
+    *(.gnu.warning)
+    *(.glue_7t) *(.glue_7) *(.vfp11_veneer)
+
+    . = ALIGN(0x4);
+    /* These are for running static constructors and destructors under ELF.  */
+    KEEP (*crtbegin.o(.ctors))
+    KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*crtend.o(.ctors))
+    KEEP (*crtbegin.o(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*crtend.o(.dtors))
+
+    *(.rodata .rodata.* .gnu.linkonce.r.*)
+
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    *(.gcc_except_table) 
+    *(.eh_frame_hdr)
+    *(.eh_frame)
+
+    KEEP (*(.init))
+    KEEP (*(.fini))
+
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT(.init_array.*)))
+    KEEP (*(.init_array))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(.fini_array))
+    KEEP (*(SORT(.fini_array.*)))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >external_ram AT>rom
+  /* .ARM.exidx is sorted, so has to go in its own output section.  */
+   __exidx_start = .;
+  .ARM.exidx :
+  {
+    *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+  } >external_ram AT>rom
+  __exidx_end = .;
+  _etext = .;
+
+  .data :
+  {
+    __data_load = LOADADDR(.data);
+    _sidata = LOADADDR (.data);
+    __data_start = .;
+    _sdata = .;
+    KEEP(*(.jcr))
+    *(.got.plt) *(.got)
+    *(.shdata)
+    *(.data .data.* .gnu.linkonce.d.*)
+    . = ALIGN (4);
+  	_edata = .;
+  } >esram AT>rom
+
+  .bss :
+  {
+    __bss_start__ = . ;
+    _sbss = .;
+    *(.shbss)
+    *(.bss .bss.* .gnu.linkonce.b.*)
+    *(COMMON)
+    . = ALIGN (8);
+    __bss_end__ = .;
+    _end = .;
+    __end = _end;
+    _ebss = .;
+    PROVIDE(end = .);
+  } >esram AT>rom
+
+  .stab 0 (NOLOAD) :
+  {
+    *(.stab)
+  }
+
+  .stabstr 0 (NOLOAD) :
+  {
+    *(.stabstr)
+  }
+  /* DWARF debug sections.
+     Symbols in the DWARF debugging sections are relative to the beginning
+     of the section so we begin them at 0.  */
+  /* DWARF 1 */
+  .debug          0 : { *(.debug) }
+  .line           0 : { *(.line) }
+  /* GNU DWARF 1 extensions */
+  .debug_srcinfo  0 : { *(.debug_srcinfo) }
+  .debug_sfnames  0 : { *(.debug_sfnames) }
+  /* DWARF 1.1 and DWARF 2 */
+  .debug_aranges  0 : { *(.debug_aranges) }
+  .debug_pubnames 0 : { *(.debug_pubnames) }
+  /* DWARF 2 */
+  .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+  .debug_abbrev   0 : { *(.debug_abbrev) }
+  .debug_line     0 : { *(.debug_line) }
+  .debug_frame    0 : { *(.debug_frame) }
+  .debug_str      0 : { *(.debug_str) }
+  .debug_loc      0 : { *(.debug_loc) }
+  .debug_macinfo  0 : { *(.debug_macinfo) }
+  /* SGI/MIPS DWARF 2 extensions */
+  .debug_weaknames 0 : { *(.debug_weaknames) }
+  .debug_funcnames 0 : { *(.debug_funcnames) }
+  .debug_typenames 0 : { *(.debug_typenames) }
+  .debug_varnames  0 : { *(.debug_varnames) }
+  .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }
+  .ARM.attributes 0 : { KEEP (*(.ARM.attributes)) }
+  /DISCARD/ : { *(.note.GNU-stack)  }
+}
diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/CMSIS/startup_gcc/startup_m2sxxx.s b/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/CMSIS/startup_gcc/startup_m2sxxx.s
new file mode 100644
index 000000000..ff927d543
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/CMSIS/startup_gcc/startup_m2sxxx.s
@@ -0,0 +1,951 @@
+/*******************************************************************************
+ * (c) Copyright 2012-2013 Microsemi SoC Products Group.  All rights reserved.
+ * 
+ *  SmartFusion2 vector table and startup code for CodeSourcery G++.
+ *
+ * SVN $Revision: 5269 $
+ * SVN $Date: 2013-03-21 20:53:38 +0000 (Thu, 21 Mar 2013) $
+ */
+
+	.syntax unified
+    .cpu cortex-m3
+    .thumb
+    
+
+/*==============================================================================
+ * Vector table
+ */
+    .global     g_pfnVectors
+    .section    .isr_vector,"a",%progbits
+    .type       g_pfnVectors, %object
+    .size       g_pfnVectors, .-g_pfnVectors
+    
+g_pfnVectors:
+    .word  _estack
+    .word  Reset_Handler
+    .word  NMI_Handler
+    .word  HardFault_Handler
+    .word  MemManage_Handler
+    .word  BusFault_Handler
+    .word  UsageFault_Handler
+    .word  0
+    .word  0
+    .word  0
+    .word  0
+    .word  SVC_Handler
+    .word  DebugMon_Handler
+    .word  0
+    .word  PendSV_Handler
+    .word  SysTick_Handler
+    .word  WdogWakeup_IRQHandler
+    .word  RTC_Wakeup_IRQHandler
+    .word  SPI0_IRQHandler
+    .word  SPI1_IRQHandler
+    .word  I2C0_IRQHandler
+    .word  I2C0_SMBAlert_IRQHandler
+    .word  I2C0_SMBus_IRQHandler
+    .word  I2C1_IRQHandler
+    .word  I2C1_SMBAlert_IRQHandler
+    .word  I2C1_SMBus_IRQHandler
+    .word  UART0_IRQHandler
+    .word  UART1_IRQHandler
+    .word  EthernetMAC_IRQHandler
+    .word  DMA_IRQHandler
+    .word  Timer1_IRQHandler
+    .word  Timer2_IRQHandler
+    .word  CAN_IRQHandler
+    .word  ENVM0_IRQHandler
+    .word  ENVM1_IRQHandler
+    .word  ComBlk_IRQHandler
+    .word  USB_IRQHandler
+    .word  USB_DMA_IRQHandler
+    .word  PLL_Lock_IRQHandler
+    .word  PLL_LockLost_IRQHandler
+    .word  CommSwitchError_IRQHandler
+    .word  CacheError_IRQHandler
+    .word  DDR_IRQHandler
+    .word  HPDMA_Complete_IRQHandler
+    .word  HPDMA_Error_IRQHandler
+    .word  ECC_Error_IRQHandler
+    .word  MDDR_IOCalib_IRQHandler
+    .word  FAB_PLL_Lock_IRQHandler
+    .word  FAB_PLL_LockLost_IRQHandler
+    .word  FIC64_IRQHandler
+    .word  FabricIrq0_IRQHandler
+    .word  FabricIrq1_IRQHandler
+    .word  FabricIrq2_IRQHandler
+    .word  FabricIrq3_IRQHandler
+    .word  FabricIrq4_IRQHandler
+    .word  FabricIrq5_IRQHandler
+    .word  FabricIrq6_IRQHandler
+    .word  FabricIrq7_IRQHandler
+    .word  FabricIrq8_IRQHandler
+    .word  FabricIrq9_IRQHandler
+    .word  FabricIrq10_IRQHandler
+    .word  FabricIrq11_IRQHandler
+    .word  FabricIrq12_IRQHandler
+    .word  FabricIrq13_IRQHandler
+    .word  FabricIrq14_IRQHandler
+    .word  FabricIrq15_IRQHandler    
+    .word  GPIO0_IRQHandler
+    .word  GPIO1_IRQHandler
+    .word  GPIO2_IRQHandler
+    .word  GPIO3_IRQHandler
+    .word  GPIO4_IRQHandler
+    .word  GPIO5_IRQHandler
+    .word  GPIO6_IRQHandler
+    .word  GPIO7_IRQHandler
+    .word  GPIO8_IRQHandler
+    .word  GPIO9_IRQHandler
+    .word  GPIO10_IRQHandler
+    .word  GPIO11_IRQHandler
+    .word  GPIO12_IRQHandler
+    .word  GPIO13_IRQHandler
+    .word  GPIO14_IRQHandler
+    .word  GPIO15_IRQHandler
+    .word  GPIO16_IRQHandler
+    .word  GPIO17_IRQHandler
+    .word  GPIO18_IRQHandler
+    .word  GPIO19_IRQHandler
+    .word  GPIO20_IRQHandler
+    .word  GPIO21_IRQHandler
+    .word  GPIO22_IRQHandler
+    .word  GPIO23_IRQHandler
+    .word  GPIO24_IRQHandler
+    .word  GPIO25_IRQHandler
+    .word  GPIO26_IRQHandler
+    .word  GPIO27_IRQHandler
+    .word  GPIO28_IRQHandler
+    .word  GPIO29_IRQHandler
+    .word  GPIO30_IRQHandler
+    .word  GPIO31_IRQHandler
+
+	
+/*==============================================================================
+ * Reset_Handler
+ */
+    .global Reset_Handler
+    .type   Reset_Handler, %function
+Reset_Handler:
+_start:
+/*------------------------------------------------------------------------------	
+ * Call CMSIS system init function.
+ */
+    ldr     r0, =SystemInit
+    blx     r0
+    
+/*------------------------------------------------------------------------------	 
+ * Check if the executable is built for NVM LMA mirrored to VMA address.
+ * This is done for debugging executables running out of eNVM with SoftConsole.
+ * The .text section should not be copied in this case since both the LMA and
+ * VMA point at the eNVM despite the LMA and VMa having different values.
+ */
+    ldr r0, =__mirrored_nvm
+    cmp r0, #0
+    bne copy_data
+    
+/*------------------------------------------------------------------------------	 
+ * Copy code section.
+ */
+	ldr r0, =__text_load
+	ldr r1, =__text_start
+	ldr r2, =_etext
+	cmp r0, r1
+	beq copy_data
+copy_code_loop:
+	cmp r1, r2
+    itt ne
+	ldrne r3, [r0], #4
+	strne r3, [r1], #4
+	bne copy_code_loop
+
+/*------------------------------------------------------------------------------	
+ * Copy data section.
+ */
+copy_data:
+	ldr r0, =__data_load
+	ldr r1, =__data_start
+	ldr r2, =_edata
+	cmp r0, r1
+	beq clear_bss
+copy_data_loop:
+	cmp r1, r2
+    itt ne
+	ldrne r3, [r0], #4
+	strne r3, [r1], #4
+	bne copy_data_loop
+	
+/*------------------------------------------------------------------------------	
+ * Clear .bss
+ */
+clear_bss:
+	ldr r0, =0
+	ldr r1, =__bss_start__
+	ldr r2, =__bss_end__
+clear_bss_loop:
+	cmp r1, r2
+    it ne
+	strne r0, [r1], #4
+	bne clear_bss_loop
+
+/*------------------------------------------------------------------------------	
+ * Call global constructors
+ */
+    /*
+     * Align to word and use 32-bits LDR instruction to ensure the ADD instruction
+     * taking PC as argument is aligned on a word boundary.
+     */
+    .align 4
+call_glob_ctor:
+	ldr.w r0, =__libc_init_array
+    add lr, pc, #3
+ 	bx r0
+
+/*------------------------------------------------------------------------------	
+ * branch to main.
+ */
+branch_to_main: 	 
+	mov	r0, #0		/*  no arguments  */
+	mov	r1, #0		/*  no argv either */
+    ldr pc, =main
+
+ExitLoop:
+    B ExitLoop
+
+/*==============================================================================
+ * NMI_Handler
+ */
+    .weak   NMI_Handler
+    .type   NMI_Handler, %function
+NMI_Handler:
+    B .
+
+/*==============================================================================
+ * HardFault_Handler
+ */
+    .weak   HardFault_Handler
+    .type   HardFault_Handler, %function
+HardFault_Handler:
+    B .
+
+/*==============================================================================
+ * MemManage_Handler
+ */
+    .weak   MemManage_Handler
+    .type   MemManage_Handler, %function
+MemManage_Handler:
+    B .
+
+/*==============================================================================
+ * BusFault_Handler
+ */
+    .weak   BusFault_Handler
+    .type   BusFault_Handler, %function
+BusFault_Handler:
+    B .
+
+/*==============================================================================
+ * UsageFault_Handler
+ */
+    .weak   UsageFault_Handler
+    .type   UsageFault_Handler, %function
+UsageFault_Handler:
+    B .
+
+/*==============================================================================
+ * SVC_Handler
+ */
+    .weak   SVC_Handler
+    .type   SVC_Handler, %function
+SVC_Handler:
+    B .
+
+/*==============================================================================
+ * DebugMon_Handler
+ */
+    .weak   DebugMon_Handler
+    .type   DebugMon_Handler, %function
+DebugMon_Handler:
+    B .
+
+/*==============================================================================
+ * PendSV_Handler
+ */
+    .weak   PendSV_Handler
+    .type   PendSV_Handler, %function
+PendSV_Handler:
+    B .
+
+/*==============================================================================
+ * SysTick_Handler
+ */
+    .weak   SysTick_Handler
+    .type   SysTick_Handler, %function
+SysTick_Handler:
+    B .
+
+/*==============================================================================
+ * WdogWakeup_IRQHandler
+ */
+    .weak   WdogWakeup_IRQHandler
+    .type   WdogWakeup_IRQHandler, %function
+WdogWakeup_IRQHandler:
+    B .
+
+/*==============================================================================
+ * RTC_Wakeup_IRQHandler
+ */
+    .weak   RTC_Wakeup_IRQHandler
+    .type   RTC_Wakeup_IRQHandler, %function
+RTC_Wakeup_IRQHandler:
+    B .
+
+/*==============================================================================
+ * SPI0_IRQHandler
+ */
+    .weak   SPI0_IRQHandler
+    .type   SPI0_IRQHandler, %function
+SPI0_IRQHandler:
+    B .
+
+/*==============================================================================
+ * SPI1_IRQHandler
+ */
+    .weak   SPI1_IRQHandler
+    .type   SPI1_IRQHandler, %function
+SPI1_IRQHandler:
+    B .
+
+/*==============================================================================
+ * I2C0_IRQHandler
+ */
+    .weak   I2C0_IRQHandler
+    .type   I2C0_IRQHandler, %function
+I2C0_IRQHandler:
+    B .
+
+/*==============================================================================
+ * I2C0_SMBAlert_IRQHandler
+ */
+    .weak   I2C0_SMBAlert_IRQHandler
+    .type   I2C0_SMBAlert_IRQHandler, %function
+I2C0_SMBAlert_IRQHandler:
+    B .
+
+/*==============================================================================
+ * I2C0_SMBus_IRQHandler
+ */
+    .weak   I2C0_SMBus_IRQHandler
+    .type   I2C0_SMBus_IRQHandler, %function
+I2C0_SMBus_IRQHandler:
+    B .
+
+/*==============================================================================
+ * I2C1_IRQHandler
+ */
+    .weak   I2C1_IRQHandler
+    .type   I2C1_IRQHandler, %function
+I2C1_IRQHandler:
+    B .
+
+/*==============================================================================
+ * I2C1_SMBAlert_IRQHandler
+ */
+    .weak   I2C1_SMBAlert_IRQHandler
+    .type   I2C1_SMBAlert_IRQHandler, %function
+I2C1_SMBAlert_IRQHandler:
+    B .
+
+/*==============================================================================
+ * I2C1_SMBus_IRQHandler
+ */
+    .weak   I2C1_SMBus_IRQHandler
+    .type   I2C1_SMBus_IRQHandler, %function
+I2C1_SMBus_IRQHandler:
+    B .
+
+/*==============================================================================
+ * UART0_IRQHandler
+ */
+    .weak   UART0_IRQHandler
+    .type   UART0_IRQHandler, %function
+UART0_IRQHandler:
+    B .
+
+/*==============================================================================
+ * UART1_IRQHandler
+ */
+    .weak   UART1_IRQHandler
+    .type   UART1_IRQHandler, %function
+UART1_IRQHandler:
+    B .
+    
+/*==============================================================================
+ * EthernetMAC_IRQHandler
+ */
+    .weak   EthernetMAC_IRQHandler
+    .type   EthernetMAC_IRQHandler, %function
+EthernetMAC_IRQHandler:
+    B .
+
+/*==============================================================================
+ * DMA_IRQHandler
+ */
+    .weak   DMA_IRQHandler
+    .type   DMA_IRQHandler, %function
+DMA_IRQHandler:
+    B .
+
+/*==============================================================================
+ * Timer1_IRQHandler
+ */
+    .weak   Timer1_IRQHandler
+    .type   Timer1_IRQHandler, %function
+Timer1_IRQHandler:
+    B .
+
+/*==============================================================================
+ * Timer2_IRQHandler
+ */
+    .weak   Timer2_IRQHandler
+    .type   Timer2_IRQHandler, %function
+Timer2_IRQHandler:
+    B .
+    
+/*==============================================================================
+ * CAN_IRQHandler
+ */
+    .weak   CAN_IRQHandler
+    .type   CAN_IRQHandler, %function
+CAN_IRQHandler:
+    B .
+    
+/*==============================================================================
+ * ENVM0_IRQHandler
+ */
+    .weak   ENVM0_IRQHandler
+    .type   ENVM0_IRQHandler, %function
+ENVM0_IRQHandler:
+    B .
+
+/*==============================================================================
+ * ENVM1_IRQHandler
+ */
+    .weak   ENVM1_IRQHandler
+    .type   ENVM1_IRQHandler, %function
+ENVM1_IRQHandler:
+    B .
+
+/*==============================================================================
+ * ComBlk_IRQHandler
+ */
+    .weak   ComBlk_IRQHandler
+    .type   ComBlk_IRQHandler, %function
+ComBlk_IRQHandler:
+    B .
+    
+/*==============================================================================
+ * USB_IRQHandler
+ */
+    .weak   USB_IRQHandler
+    .type   USB_IRQHandler, %function
+USB_IRQHandler:
+    B .
+    
+/*==============================================================================
+ * USB_DMA_IRQHandler
+ */
+    .weak   USB_DMA_IRQHandler
+    .type   USB_DMA_IRQHandler, %function
+USB_DMA_IRQHandler:
+    B .
+
+/*==============================================================================
+ * PLL_Lock_IRQHandler
+ */
+    .weak   PLL_Lock_IRQHandler
+    .type   PLL_Lock_IRQHandler, %function
+PLL_Lock_IRQHandler:
+    B .
+
+/*==============================================================================
+ * PLL_LockLost_IRQHandler
+ */
+    .weak   PLL_LockLost_IRQHandler
+    .type   PLL_LockLost_IRQHandler, %function
+PLL_LockLost_IRQHandler:
+    B .
+
+/*==============================================================================
+ * CommSwitchError_IRQHandler
+ */
+    .weak   CommSwitchError_IRQHandler
+    .type   CommSwitchError_IRQHandler, %function
+CommSwitchError_IRQHandler:
+    B .
+
+/*==============================================================================
+ * CacheError_IRQHandler
+ */
+    .weak   CacheError_IRQHandler
+    .type   CacheError_IRQHandler, %function
+CacheError_IRQHandler:
+    B .
+
+/*==============================================================================
+ * DDR_IRQHandler
+ */
+    .weak   DDR_IRQHandler
+    .type   DDR_IRQHandler, %function
+DDR_IRQHandler:
+    B .
+
+/*==============================================================================
+ * HPDMA_Complete_IRQHandler
+ */
+    .weak   HPDMA_Complete_IRQHandler
+    .type   HPDMA_Complete_IRQHandler, %function
+HPDMA_Complete_IRQHandler:
+    B .
+
+/*==============================================================================
+ * HPDMA_Error_IRQHandler
+ */
+    .weak   HPDMA_Error_IRQHandler
+    .type   HPDMA_Error_IRQHandler, %function
+HPDMA_Error_IRQHandler:
+    B .
+    
+/*==============================================================================
+ * ECC_Error_IRQHandler
+ */
+    .weak   ECC_Error_IRQHandler
+    .type   ECC_Error_IRQHandler, %function
+ECC_Error_IRQHandler:
+    B .
+
+/*==============================================================================
+ * MDDR_IOCalib_IRQHandler
+ */
+    .weak   MDDR_IOCalib_IRQHandler
+    .type   MDDR_IOCalib_IRQHandler, %function
+MDDR_IOCalib_IRQHandler:
+    B .
+
+/*==============================================================================
+ * FAB_PLL_Lock_IRQHandler
+ */
+    .weak   FAB_PLL_Lock_IRQHandler
+    .type   FAB_PLL_Lock_IRQHandler, %function    
+FAB_PLL_Lock_IRQHandler:
+    B .
+
+/*==============================================================================
+ * FAB_PLL_LockLost_IRQHandler
+ */
+    .weak   FAB_PLL_LockLost_IRQHandler
+    .type   FAB_PLL_LockLost_IRQHandler, %function        
+FAB_PLL_LockLost_IRQHandler:
+    B .
+    
+/*==============================================================================
+ * FIC64_IRQHandler
+ */
+    .weak   FIC64_IRQHandler
+    .type   FIC64_IRQHandler, %function            
+FIC64_IRQHandler:
+    B .
+    
+/*==============================================================================
+ * FabricIrq0_IRQHandler
+ */
+    .weak   FabricIrq0_IRQHandler
+    .type   FabricIrq0_IRQHandler, %function
+FabricIrq0_IRQHandler:
+    B .
+
+/*==============================================================================
+ * FabricIrq1_IRQHandler
+ */
+    .weak   FabricIrq1_IRQHandler
+    .type   FabricIrq1_IRQHandler, %function
+FabricIrq1_IRQHandler:
+    B .
+
+/*==============================================================================
+ * FabricIrq2_IRQHandler
+ */
+    .weak   FabricIrq2_IRQHandler
+    .type   FabricIrq2_IRQHandler, %function
+FabricIrq2_IRQHandler:
+    B .
+
+/*==============================================================================
+ * FabricIrq3_IRQHandler
+ */
+    .weak   FabricIrq3_IRQHandler
+    .type   FabricIrq3_IRQHandler, %function
+FabricIrq3_IRQHandler:
+    B .
+
+/*==============================================================================
+ * FabricIrq4_IRQHandler
+ */
+    .weak   FabricIrq4_IRQHandler
+    .type   FabricIrq4_IRQHandler, %function
+FabricIrq4_IRQHandler:
+    B .
+
+/*==============================================================================
+ * FabricIrq5_IRQHandler
+ */
+    .weak   FabricIrq5_IRQHandler
+    .type   FabricIrq5_IRQHandler, %function
+FabricIrq5_IRQHandler:
+    B .
+
+/*==============================================================================
+ * FabricIrq6_IRQHandler
+ */
+    .weak   FabricIrq6_IRQHandler
+    .type   FabricIrq6_IRQHandler, %function
+FabricIrq6_IRQHandler:
+    B .
+
+/*==============================================================================
+ * FabricIrq7_IRQHandler
+ */
+    .weak   FabricIrq7_IRQHandler
+    .type   FabricIrq7_IRQHandler, %function
+FabricIrq7_IRQHandler:
+    B .
+    
+/*==============================================================================
+ * FabricIrq8_IRQHandler
+ */
+    .weak   FabricIrq8_IRQHandler
+    .type   FabricIrq8_IRQHandler, %function
+FabricIrq8_IRQHandler:
+    B .
+
+/*==============================================================================
+ * FabricIrq9_IRQHandler
+ */
+    .weak   FabricIrq9_IRQHandler
+    .type   FabricIrq9_IRQHandler, %function
+FabricIrq9_IRQHandler:
+    B .
+
+/*==============================================================================
+ * FabricIrq10_IRQHandler
+ */
+    .weak   FabricIrq10_IRQHandler
+    .type   FabricIrq10_IRQHandler, %function
+FabricIrq10_IRQHandler:
+    B .
+
+/*==============================================================================
+ * FabricIrq11_IRQHandler
+ */
+    .weak   FabricIrq11_IRQHandler
+    .type   FabricIrq11_IRQHandler, %function
+FabricIrq11_IRQHandler:
+    B .
+
+/*==============================================================================
+ * FabricIrq12_IRQHandler
+ */
+    .weak   FabricIrq12_IRQHandler
+    .type   FabricIrq12_IRQHandler, %function
+FabricIrq12_IRQHandler:
+    B .
+
+/*==============================================================================
+ * FabricIrq13_IRQHandler
+ */
+    .weak   FabricIrq13_IRQHandler
+    .type   FabricIrq13_IRQHandler, %function
+FabricIrq13_IRQHandler:
+    B .
+
+/*==============================================================================
+ * FabricIrq14_IRQHandler
+ */
+    .weak   FabricIrq14_IRQHandler
+    .type   FabricIrq14_IRQHandler, %function
+FabricIrq14_IRQHandler:
+    B .
+
+/*==============================================================================
+ * FabricIrq15_IRQHandler
+ */
+    .weak   FabricIrq15_IRQHandler
+    .type   FabricIrq15_IRQHandler, %function
+FabricIrq15_IRQHandler:
+    B .    
+
+/*==============================================================================
+ * GPIO0_IRQHandler
+ */
+    .weak   GPIO0_IRQHandler
+    .type   GPIO0_IRQHandler, %function
+GPIO0_IRQHandler:
+    B .
+
+/*==============================================================================
+ * GPIO1_IRQHandler
+ */
+    .weak   GPIO1_IRQHandler
+    .type   GPIO1_IRQHandler, %function
+GPIO1_IRQHandler:
+    B .
+
+/*==============================================================================
+ * GPIO2_IRQHandler
+ */
+    .weak   GPIO2_IRQHandler
+    .type   GPIO2_IRQHandler, %function
+GPIO2_IRQHandler:
+    B .
+
+/*==============================================================================
+ * GPIO3_IRQHandler
+ */
+    .weak   GPIO3_IRQHandler
+    .type   GPIO3_IRQHandler, %function
+GPIO3_IRQHandler:
+    B .
+
+/*==============================================================================
+ * GPIO4_IRQHandler
+ */
+    .weak   GPIO4_IRQHandler
+    .type   GPIO4_IRQHandler, %function
+GPIO4_IRQHandler:
+    B .
+
+/*==============================================================================
+ * GPIO5_IRQHandler
+ */
+    .weak   GPIO5_IRQHandler
+    .type   GPIO5_IRQHandler, %function
+GPIO5_IRQHandler:
+    B .
+
+/*==============================================================================
+ * GPIO6_IRQHandler
+ */
+    .weak   GPIO6_IRQHandler
+    .type   GPIO6_IRQHandler, %function
+GPIO6_IRQHandler:
+    B .
+
+/*==============================================================================
+ * GPIO7_IRQHandler
+ */
+    .weak   GPIO7_IRQHandler
+    .type   GPIO7_IRQHandler, %function
+GPIO7_IRQHandler:
+    B .
+
+/*==============================================================================
+ * GPIO8_IRQHandler
+ */
+    .weak   GPIO8_IRQHandler
+    .type   GPIO8_IRQHandler, %function
+GPIO8_IRQHandler:
+    B .
+
+/*==============================================================================
+ * GPIO9_IRQHandler
+ */
+    .weak   GPIO9_IRQHandler
+    .type   GPIO9_IRQHandler, %function
+GPIO9_IRQHandler:
+    B .
+
+/*==============================================================================
+ * GPIO10_IRQHandler
+ */
+    .weak   GPIO10_IRQHandler
+    .type   GPIO10_IRQHandler, %function
+GPIO10_IRQHandler:
+    B .
+
+/*==============================================================================
+ * GPIO11_IRQHandler
+ */
+    .weak   GPIO11_IRQHandler
+    .type   GPIO11_IRQHandler, %function
+GPIO11_IRQHandler:
+    B .
+
+/*==============================================================================
+ * GPIO12_IRQHandler
+ */
+    .weak   GPIO12_IRQHandler
+    .type   GPIO12_IRQHandler, %function
+GPIO12_IRQHandler:
+    B .
+
+/*==============================================================================
+ * GPIO13_IRQHandler
+ */
+    .weak   GPIO13_IRQHandler
+    .type   GPIO13_IRQHandler, %function
+GPIO13_IRQHandler:
+    B .
+
+/*==============================================================================
+ * GPIO14_IRQHandler
+ */
+    .weak   GPIO14_IRQHandler
+    .type   GPIO14_IRQHandler, %function
+GPIO14_IRQHandler:
+    B .
+
+/*==============================================================================
+ * GPIO15_IRQHandler
+ */
+    .weak   GPIO15_IRQHandler
+    .type   GPIO15_IRQHandler, %function
+GPIO15_IRQHandler:
+    B .
+
+/*==============================================================================
+ * GPIO16_IRQHandler
+ */
+    .weak   GPIO16_IRQHandler
+    .type   GPIO16_IRQHandler, %function
+GPIO16_IRQHandler:
+    B .
+
+/*==============================================================================
+ * GPIO17_IRQHandler
+ */
+    .weak   GPIO17_IRQHandler
+    .type   GPIO17_IRQHandler, %function
+GPIO17_IRQHandler:
+    B .
+
+/*==============================================================================
+ * GPIO18_IRQHandler
+ */
+    .weak   GPIO18_IRQHandler
+    .type   GPIO18_IRQHandler, %function
+GPIO18_IRQHandler:
+    B .
+
+/*==============================================================================
+ * GPIO19_IRQHandler
+ */
+    .weak   GPIO19_IRQHandler
+    .type   GPIO19_IRQHandler, %function
+GPIO19_IRQHandler:
+    B .
+
+/*==============================================================================
+ * GPIO20_IRQHandler
+ */
+    .weak   GPIO20_IRQHandler
+    .type   GPIO20_IRQHandler, %function
+GPIO20_IRQHandler:
+    B .
+
+/*==============================================================================
+ * GPIO21_IRQHandler
+ */
+    .weak   GPIO21_IRQHandler
+    .type   GPIO21_IRQHandler, %function
+GPIO21_IRQHandler:
+    B .
+
+/*==============================================================================
+ * GPIO22_IRQHandler
+ */
+    .weak   GPIO22_IRQHandler
+    .type   GPIO22_IRQHandler, %function
+GPIO22_IRQHandler:
+    B .
+
+/*==============================================================================
+ * GPIO23_IRQHandler
+ */
+    .weak   GPIO23_IRQHandler
+    .type   GPIO23_IRQHandler, %function
+GPIO23_IRQHandler:
+    B .
+
+/*==============================================================================
+ * GPIO24_IRQHandler
+ */
+    .weak   GPIO24_IRQHandler
+    .type   GPIO24_IRQHandler, %function
+GPIO24_IRQHandler:
+    B .
+
+/*==============================================================================
+ * GPIO25_IRQHandler
+ */
+    .weak   GPIO25_IRQHandler
+    .type   GPIO25_IRQHandler, %function
+GPIO25_IRQHandler:
+    B .
+
+/*==============================================================================
+ * GPIO26_IRQHandler
+ */
+    .weak   GPIO26_IRQHandler
+    .type   GPIO26_IRQHandler, %function
+GPIO26_IRQHandler:
+    B .
+
+/*==============================================================================
+ * GPIO27_IRQHandler
+ */
+    .weak   GPIO27_IRQHandler
+    .type   GPIO27_IRQHandler, %function
+GPIO27_IRQHandler:
+    B .
+
+/*==============================================================================
+ * GPIO28_IRQHandler
+ */
+    .weak   GPIO28_IRQHandler
+    .type   GPIO28_IRQHandler, %function
+GPIO28_IRQHandler:
+    B .
+
+/*==============================================================================
+ * GPIO29_IRQHandler
+ */
+    .weak   GPIO29_IRQHandler
+    .type   GPIO29_IRQHandler, %function
+GPIO29_IRQHandler:
+    B .
+
+/*==============================================================================
+ * GPIO30_IRQHandler
+ */
+    .weak   GPIO30_IRQHandler
+    .type   GPIO30_IRQHandler, %function
+GPIO30_IRQHandler:
+    B .
+
+/*==============================================================================
+ * GPIO31_IRQHandler
+ */
+    .weak   GPIO31_IRQHandler
+    .type   GPIO31_IRQHandler, %function
+GPIO31_IRQHandler:
+    B .
+
+/*==============================================================================
+ * mscc_post_hw_cfg_init
+ */
+    .weak   mscc_post_hw_cfg_init
+    .type   mscc_post_hw_cfg_init, %function
+mscc_post_hw_cfg_init:
+    BX LR
+
+.end
diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/CMSIS/sys_init_cfg_types.h b/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/CMSIS/sys_init_cfg_types.h
new file mode 100644
index 000000000..c8368af2e
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/CMSIS/sys_init_cfg_types.h
@@ -0,0 +1,212 @@
+/*******************************************************************************
+ * (c) Copyright 2012 Microsemi SoC Products Group.  All rights reserved.
+ * 
+ *  
+ *
+ * SVN $Revision: 4410 $
+ * SVN $Date: 2012-07-16 14:36:17 +0100 (Mon, 16 Jul 2012) $
+ */
+ 
+#ifndef SYSTEM_INIT_CFG_TYPES_H_
+#define SYSTEM_INIT_CFG_TYPES_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif 
+
+/*============================================================================*/
+/*                              DDR Configuration                             */
+/*============================================================================*/
+typedef struct
+{
+    /*--------------------------------------------------------------------------
+     * DDR Controller registers.
+     */
+    struct
+    {
+        uint16_t DYN_SOFT_RESET_CR;
+        uint16_t RESERVED0;
+        uint16_t DYN_REFRESH_1_CR;
+        uint16_t DYN_REFRESH_2_CR;
+        uint16_t DYN_POWERDOWN_CR;
+        uint16_t DYN_DEBUG_CR;
+        uint16_t MODE_CR;
+        uint16_t ADDR_MAP_BANK_CR;
+        uint16_t ECC_DATA_MASK_CR;
+        uint16_t ADDR_MAP_COL_1_CR;
+        uint16_t ADDR_MAP_COL_2_CR;
+        uint16_t ADDR_MAP_ROW_1_CR;
+        uint16_t ADDR_MAP_ROW_2_CR;
+        uint16_t INIT_1_CR;
+        uint16_t CKE_RSTN_CYCLES_1_CR;
+        uint16_t CKE_RSTN_CYCLES_2_CR;
+        uint16_t INIT_MR_CR;
+        uint16_t INIT_EMR_CR;
+        uint16_t INIT_EMR2_CR;
+        uint16_t INIT_EMR3_CR;
+        uint16_t DRAM_BANK_TIMING_PARAM_CR;
+        uint16_t DRAM_RD_WR_LATENCY_CR;
+        uint16_t DRAM_RD_WR_PRE_CR;
+        uint16_t DRAM_MR_TIMING_PARAM_CR;
+        uint16_t DRAM_RAS_TIMING_CR;
+        uint16_t DRAM_RD_WR_TRNARND_TIME_CR;
+        uint16_t DRAM_T_PD_CR;
+        uint16_t DRAM_BANK_ACT_TIMING_CR;
+        uint16_t ODT_PARAM_1_CR;
+        uint16_t ODT_PARAM_2_CR;
+        uint16_t ADDR_MAP_COL_3_CR;
+        uint16_t MODE_REG_RD_WR_CR;
+        uint16_t MODE_REG_DATA_CR;
+        uint16_t PWR_SAVE_1_CR;
+        uint16_t PWR_SAVE_2_CR;
+        uint16_t ZQ_LONG_TIME_CR;
+        uint16_t ZQ_SHORT_TIME_CR;
+        uint16_t ZQ_SHORT_INT_REFRESH_MARGIN_1_CR;
+        uint16_t ZQ_SHORT_INT_REFRESH_MARGIN_2_CR;
+        uint16_t PERF_PARAM_1_CR;
+        uint16_t HPR_QUEUE_PARAM_1_CR;
+        uint16_t HPR_QUEUE_PARAM_2_CR;
+        uint16_t LPR_QUEUE_PARAM_1_CR;
+        uint16_t LPR_QUEUE_PARAM_2_CR;
+        uint16_t WR_QUEUE_PARAM_CR;
+        uint16_t PERF_PARAM_2_CR;
+        uint16_t PERF_PARAM_3_CR;
+        uint16_t DFI_RDDATA_EN_CR;
+        uint16_t DFI_MIN_CTRLUPD_TIMING_CR;
+        uint16_t DFI_MAX_CTRLUPD_TIMING_CR;
+        uint16_t DFI_WR_LVL_CONTROL_1_CR;
+        uint16_t DFI_WR_LVL_CONTROL_2_CR;
+        uint16_t DFI_RD_LVL_CONTROL_1_CR;
+        uint16_t DFI_RD_LVL_CONTROL_2_CR;
+        uint16_t DFI_CTRLUPD_TIME_INTERVAL_CR;
+        uint16_t DYN_SOFT_RESET_CR2;
+        uint16_t AXI_FABRIC_PRI_ID_CR;
+    } ddrc;
+    
+    /*--------------------------------------------------------------------------
+     * DDR PHY configuration registers
+     */
+    struct 
+    {
+        uint16_t LOOPBACK_TEST_CR;
+        uint16_t BOARD_LOOPBACK_CR;
+        uint16_t CTRL_SLAVE_RATIO_CR;
+        uint16_t CTRL_SLAVE_FORCE_CR;
+        uint16_t CTRL_SLAVE_DELAY_CR;
+        uint16_t DATA_SLICE_IN_USE_CR;
+        uint16_t LVL_NUM_OF_DQ0_CR;
+        uint16_t DQ_OFFSET_1_CR;
+        uint16_t DQ_OFFSET_2_CR;
+        uint16_t DQ_OFFSET_3_CR;
+        uint16_t DIS_CALIB_RST_CR;
+        uint16_t DLL_LOCK_DIFF_CR;
+        uint16_t FIFO_WE_IN_DELAY_1_CR;
+        uint16_t FIFO_WE_IN_DELAY_2_CR;
+        uint16_t FIFO_WE_IN_DELAY_3_CR;
+        uint16_t FIFO_WE_IN_FORCE_CR;
+        uint16_t FIFO_WE_SLAVE_RATIO_1_CR;
+        uint16_t FIFO_WE_SLAVE_RATIO_2_CR;
+        uint16_t FIFO_WE_SLAVE_RATIO_3_CR;
+        uint16_t FIFO_WE_SLAVE_RATIO_4_CR;
+        uint16_t GATELVL_INIT_MODE_CR;
+        uint16_t GATELVL_INIT_RATIO_1_CR;
+        uint16_t GATELVL_INIT_RATIO_2_CR;
+        uint16_t GATELVL_INIT_RATIO_3_CR;
+        uint16_t GATELVL_INIT_RATIO_4_CR;
+        uint16_t LOCAL_ODT_CR;
+        uint16_t INVERT_CLKOUT_CR;
+        uint16_t RD_DQS_SLAVE_DELAY_1_CR;
+        uint16_t RD_DQS_SLAVE_DELAY_2_CR;
+        uint16_t RD_DQS_SLAVE_DELAY_3_CR;
+        uint16_t RD_DQS_SLAVE_FORCE_CR;
+        uint16_t RD_DQS_SLAVE_RATIO_1_CR;
+        uint16_t RD_DQS_SLAVE_RATIO_2_CR;
+        uint16_t RD_DQS_SLAVE_RATIO_3_CR;
+        uint16_t RD_DQS_SLAVE_RATIO_4_CR;
+        uint16_t WR_DQS_SLAVE_DELAY_1_CR;
+        uint16_t WR_DQS_SLAVE_DELAY_2_CR;
+        uint16_t WR_DQS_SLAVE_DELAY_3_CR;
+        uint16_t WR_DQS_SLAVE_FORCE_CR;
+        uint16_t WR_DQS_SLAVE_RATIO_1_CR;
+        uint16_t WR_DQS_SLAVE_RATIO_2_CR;
+        uint16_t WR_DQS_SLAVE_RATIO_3_CR;
+        uint16_t WR_DQS_SLAVE_RATIO_4_CR;
+        uint16_t WR_DATA_SLAVE_DELAY_1_CR;
+        uint16_t WR_DATA_SLAVE_DELAY_2_CR;
+        uint16_t WR_DATA_SLAVE_DELAY_3_CR;
+        uint16_t WR_DATA_SLAVE_FORCE_CR;
+        uint16_t WR_DATA_SLAVE_RATIO_1_CR;
+        uint16_t WR_DATA_SLAVE_RATIO_2_CR;
+        uint16_t WR_DATA_SLAVE_RATIO_3_CR;
+        uint16_t WR_DATA_SLAVE_RATIO_4_CR;
+        uint16_t WRLVL_INIT_MODE_CR;
+        uint16_t WRLVL_INIT_RATIO_1_CR;
+        uint16_t WRLVL_INIT_RATIO_2_CR;
+        uint16_t WRLVL_INIT_RATIO_3_CR;
+        uint16_t WRLVL_INIT_RATIO_4_CR;
+        uint16_t WR_RD_RL_CR;
+        uint16_t RDC_FIFO_RST_ERRCNTCLR_CR;
+        uint16_t RDC_WE_TO_RE_DELAY_CR;
+        uint16_t USE_FIXED_RE_CR;
+        uint16_t USE_RANK0_DELAYS_CR;
+        uint16_t USE_LVL_TRNG_LEVEL_CR;
+        uint16_t CONFIG_CR;
+        uint16_t RD_WR_GATE_LVL_CR;
+        uint16_t DYN_RESET_CR;
+    } phy;
+    
+    /*--------------------------------------------------------------------------
+     * FIC-64 registers
+     * These registers are 16-bit wide and 32-bit aligned.
+     */
+    struct 
+    {
+        uint16_t NB_ADDR_CR;
+        uint16_t NBRWB_SIZE_CR;
+        uint16_t WB_TIMEOUT_CR;
+        uint16_t HPD_SW_RW_EN_CR;
+        uint16_t HPD_SW_RW_INVAL_CR;
+        uint16_t SW_WR_ERCLR_CR;
+        uint16_t ERR_INT_ENABLE_CR;
+        uint16_t NUM_AHB_MASTERS_CR;
+        uint16_t LOCK_TIMEOUTVAL_1_CR;
+        uint16_t LOCK_TIMEOUTVAL_2_CR;
+        uint16_t LOCK_TIMEOUT_EN_CR;
+    } fic;
+} ddr_subsys_cfg_t;
+
+/*============================================================================*/
+/*                             FDDR Configuration                             */
+/*============================================================================*/
+
+typedef struct 
+{
+    uint16_t PLL_CONFIG_LOW_1;
+    uint16_t PLL_CONFIG_LOW_2;
+    uint16_t PLL_CONFIG_HIGH;
+    uint16_t FACC_CLK_EN;
+    uint16_t FACC_MUX_CONFIG;
+    uint16_t FACC_DIVISOR_RATIO;
+    uint16_t PLL_DELAY_LINE_SEL;
+    uint16_t SOFT_RESET; 
+    uint16_t IO_CALIB;
+    uint16_t INTERRUPT_ENABLE;
+    uint16_t AXI_AHB_MODE_SEL;
+    uint16_t PHY_SELF_REF_EN;
+} fddr_sysreg_t;
+
+/*============================================================================*/
+/*                 PCI Express Bridge IP Core configuration.                  */
+/*============================================================================*/
+
+typedef struct
+{
+    uint32_t * p_reg;
+    uint32_t value;
+} cfg_addr_value_pair_t;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SYSTEM_INIT_CFG_TYPES_H_ */
diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/CMSIS/system_m2sxxx.c b/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/CMSIS/system_m2sxxx.c
new file mode 100644
index 000000000..04134b86e
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/CMSIS/system_m2sxxx.c
@@ -0,0 +1,560 @@
+/*******************************************************************************
+ * (c) Copyright 2012-2013 Microsemi SoC Products Group. All rights reserved.
+ * 
+ *  SmartFusion2 CMSIS system initialization.
+ *
+ * SVN $Revision: 5280 $
+ * SVN $Date: 2013-03-22 20:51:50 +0000 (Fri, 22 Mar 2013) $
+ */
+#include "m2sxxx.h"
+#include "../drivers_config/sys_config/sys_config.h"
+#include "sys_init_cfg_types.h"
+
+/*------------------------------------------------------------------------------
+  Silicon revisions.
+ */
+#define UNKNOWN_SILICON_REV     0
+#define M2S050_REV_A_SILICON    1
+#define M2S050_REV_B_SILICON    2
+
+/*------------------------------------------------------------------------------
+ * 
+ */
+void mscc_post_hw_cfg_init(void);
+
+/*------------------------------------------------------------------------------
+ * System registers of interest.
+ */
+/*
+ * MSSDDR_FACC1_CR register masks:
+ */
+#define DDR_CLK_EN_SHIFT    8u
+#define FACC_GLMUX_SEL_MASK         0x00001000u
+#define CONTROLLER_PLL_INIT_MASK    0x04000000u
+#define RCOSC_DIV2_MASK             0x00000004u
+
+/*
+ * MSSDDR_PLL_STATUS register masks:
+ */
+#define FAB_PLL_LOCK_MASK   0x00000001u
+#define MPLL_LOCK_MASK      0x00000002u
+
+/*
+ * MSSDDR_PLL_STATUS_HIGH_CR register masks:
+ */
+#define FACC_PLL_BYPASS_MASK    0x00000001u
+
+/*------------------------------------------------------------------------------
+ * Standard CMSIS global variables.
+ */
+uint32_t SystemCoreClock = MSS_SYS_M3_CLK_FREQ;         /*!< System Clock Frequency (Core Clock) */
+
+/*------------------------------------------------------------------------------
+ * SmartFusion2 specific clocks.
+ */
+uint32_t g_FrequencyPCLK0 = MSS_SYS_APB_0_CLK_FREQ;     /*!< Clock frequency of APB bus 0. */  
+uint32_t g_FrequencyPCLK1 = MSS_SYS_APB_1_CLK_FREQ;     /*!< Clock frequency of APB bus 1. */
+uint32_t g_FrequencyPCLK2 = MSS_SYS_APB_2_CLK_FREQ;     /*!< Clock frequency of APB bus 2. */
+uint32_t g_FrequencyFIC0 = MSS_SYS_FIC_0_CLK_FREQ;      /*!< Clock frequecny of FPGA fabric interface controller 1. */
+uint32_t g_FrequencyFIC1 = MSS_SYS_FIC_1_CLK_FREQ;      /*!< Clock frequecny of FPGA fabric inteface controller 2. */
+uint32_t g_FrequencyFIC64 = MSS_SYS_FIC64_CLK_FREQ;     /*!< Clock frequecny of 64-bit FPGA fabric interface controller. */
+
+/*------------------------------------------------------------------------------
+ * System configuration tables generated by Libero.
+ */
+#if MSS_SYS_MDDR_CONFIG_BY_CORTEX
+extern MDDR_TypeDef * const g_m2s_mddr_addr;
+extern const ddr_subsys_cfg_t g_m2s_mddr_subsys_config;
+#endif
+
+#if MSS_SYS_FDDR_CONFIG_BY_CORTEX
+extern FDDR_TypeDef * const g_m2s_fddr_addr;
+extern const ddr_subsys_cfg_t g_m2s_fddr_subsys_config;
+#endif
+
+#define MSS_SYS_SERDES_CONFIG_BY_CORTEX     (MSS_SYS_SERDES_0_CONFIG_BY_CORTEX || MSS_SYS_SERDES_1_CONFIG_BY_CORTEX || MSS_SYS_SERDES_2_CONFIG_BY_CORTEX || MSS_SYS_SERDES_3_CONFIG_BY_CORTEX)
+
+#if MSS_SYS_SERDES_0_CONFIG_BY_CORTEX
+extern const cfg_addr_value_pair_t g_m2s_serdes_0_config[SERDES_0_CFG_NB_OF_PAIRS];
+#endif
+
+#if MSS_SYS_SERDES_1_CONFIG_BY_CORTEX
+extern const cfg_addr_value_pair_t g_m2s_serdes_1_config[SERDES_1_CFG_NB_OF_PAIRS];
+#endif
+
+#if MSS_SYS_SERDES_2_CONFIG_BY_CORTEX
+extern const cfg_addr_value_pair_t g_m2s_serdes_2_config[SERDES_2_CFG_NB_OF_PAIRS];
+#endif
+
+#if MSS_SYS_SERDES_3_CONFIG_BY_CORTEX
+extern const cfg_addr_value_pair_t g_m2s_serdes_3_config[SERDES_3_CFG_NB_OF_PAIRS];
+#endif
+
+#define MSS_SYS_CORESF2RESET_USED  (MSS_SYS_MDDR_CONFIG_BY_CORTEX || MSS_SYS_FDDR_CONFIG_BY_CORTEX || MSS_SYS_SERDES_CONFIG_BY_CORTEX)
+
+/*------------------------------------------------------------------------------
+ * Local functions:
+ */
+static uint32_t get_silicon_revision(void);
+static void silicon_workarounds(void);
+static void m2s050_rev_a_workarounds(void);
+
+#if (MSS_SYS_FACC_INIT_BY_CORTEX == 1)
+static void complete_clock_config(void);
+#endif
+
+#if MSS_SYS_SERDES_CONFIG_BY_CORTEX
+static void configure_serdes_intf(void);
+#endif
+
+#if (MSS_SYS_MDDR_CONFIG_BY_CORTEX || MSS_SYS_FDDR_CONFIG_BY_CORTEX)
+static void config_ddr_subsys
+(
+    const ddr_subsys_cfg_t * p_ddr_subsys_cfg,
+    DDRCore_TypeDef * p_ddr_subsys_regs
+);
+#endif
+
+#if MSS_SYS_SERDES_CONFIG_BY_CORTEX
+static void config_by_addr_value
+(
+    const cfg_addr_value_pair_t * p_addr_value_pair,
+    uint32_t nb_of_cfg_pairs
+);
+#endif
+
+static uint32_t get_rcosc_25_50mhz_frequency(void);
+static void set_clock_frequency_globals(uint32_t fclk);
+
+/***************************************************************************//**
+ * See system_m2sxxx.h for details.
+ */
+void SystemInit(void)
+{
+    /*
+     * Do not make use of global variables or make any asumptions regarding
+     * memory content if modifying this function. The memory content has not been
+     * initialised by the time this function is called by the start-up code.
+     */
+#if (MSS_SYS_FACC_INIT_BY_CORTEX == 1)
+    complete_clock_config();
+#endif
+
+    silicon_workarounds();
+    
+    /*--------------------------------------------------------------------------
+     * Set STKALIGN to ensure exception stacking starts on 8 bytes address
+     * boundary. This ensures compliance with the "Procedure Call Standards for
+     * the ARM Architecture" (AAPCS).
+     */
+    SCB->CCR |= SCB_CCR_STKALIGN_Msk;
+    
+    /*--------------------------------------------------------------------------
+     * MDDR configuration
+     */
+#if MSS_SYS_MDDR_CONFIG_BY_CORTEX
+    config_ddr_subsys(&g_m2s_mddr_subsys_config, &g_m2s_mddr_addr->core);
+#endif
+
+    /*--------------------------------------------------------------------------
+     * MDDR configuration
+     */
+#if MSS_SYS_FDDR_CONFIG_BY_CORTEX
+    config_ddr_subsys(&g_m2s_fddr_subsys_config, &g_m2s_fddr_addr->core);
+#endif
+
+    /*--------------------------------------------------------------------------
+     * SERDES interfaces configuration.
+     */
+#if MSS_SYS_SERDES_CONFIG_BY_CORTEX
+    configure_serdes_intf();
+#endif
+
+    /*--------------------------------------------------------------------------
+     * Call user defined configuration function.
+     */
+    mscc_post_hw_cfg_init();
+    
+    /*--------------------------------------------------------------------------
+     * Synchronize with CoreSF2Reset controlling resets from the fabric.
+     */
+#if MSS_SYS_CORESF2RESET_USED
+    CORE_SF2_CFG->CONFIG_DONE = 1u; /* Signal to CoreSF2Reset that peripheral 
+                                       configuration registers have been written.*/
+    while(!CORE_SF2_CFG->INIT_DONE)
+    {
+        ;   /* Wait for INIT_DONE from CoreSF2Reset. */
+    }
+#endif
+}
+
+/***************************************************************************//**
+ * SystemCoreClockUpdate()
+ */
+#define RCOSC_25_50MHZ_CLK_SRC  0u
+#define CLK_XTAL_CLK_SRC        1u
+#define RCOSC_1_MHZ_CLK_SRC     2u
+#define CCC2ASCI_CLK_SRC        3u
+
+#define FACC_STANDBY_SHIFT      6u
+#define FACC_STANDBY_SEL_MASK   0x00000007u
+
+#define FREQ_32KHZ   32768u
+#define FREQ_1MHZ    1000000u
+#define FREQ_25MHZ   25000000u
+#define FREQ_50MHZ   50000000u
+
+void SystemCoreClockUpdate(void)
+{
+#if 1
+    uint32_t controller_pll_init;
+    uint32_t clk_src;
+
+    controller_pll_init = SYSREG->MSSDDR_FACC1_CR & CONTROLLER_PLL_INIT_MASK;
+    
+    if(0u == controller_pll_init)
+    {
+        /* Normal operations. */
+        uint32_t global_mux_sel;
+        
+        global_mux_sel = SYSREG->MSSDDR_FACC1_CR & FACC_GLMUX_SEL_MASK;
+        if(0u == global_mux_sel)
+        {
+            /* MSS clocked from MSS PLL. Use Libero flow defines. */
+            SystemCoreClock = MSS_SYS_M3_CLK_FREQ;
+            g_FrequencyPCLK0 = MSS_SYS_APB_0_CLK_FREQ;
+            g_FrequencyPCLK1 = MSS_SYS_APB_1_CLK_FREQ;
+            g_FrequencyPCLK2 = MSS_SYS_APB_2_CLK_FREQ;
+            g_FrequencyFIC0 = MSS_SYS_FIC_0_CLK_FREQ;
+            g_FrequencyFIC1 = MSS_SYS_FIC_1_CLK_FREQ;
+            g_FrequencyFIC64 = MSS_SYS_FIC64_CLK_FREQ;
+        }
+        else
+        {
+            /* MSS clocked from standby clock. */
+            const uint8_t standby_clock_lut[8] = { RCOSC_25_50MHZ_CLK_SRC,
+                                                   CLK_XTAL_CLK_SRC,
+                                                   RCOSC_25_50MHZ_CLK_SRC,
+                                                   CLK_XTAL_CLK_SRC,
+                                                   RCOSC_1_MHZ_CLK_SRC,
+                                                   RCOSC_1_MHZ_CLK_SRC,
+                                                   CCC2ASCI_CLK_SRC,
+                                                   CCC2ASCI_CLK_SRC };
+            
+            uint32_t standby_sel;
+            uint8_t clock_source;
+            
+            standby_sel = (SYSREG->MSSDDR_FACC2_CR >> FACC_STANDBY_SHIFT) & FACC_STANDBY_SEL_MASK;
+            clock_source = standby_clock_lut[standby_sel];
+            switch(clock_source)
+            {
+                case RCOSC_25_50MHZ_CLK_SRC:
+                    clk_src = get_rcosc_25_50mhz_frequency();
+                    set_clock_frequency_globals(clk_src);
+                break;
+                
+                case CLK_XTAL_CLK_SRC:
+                    set_clock_frequency_globals(FREQ_32KHZ);
+                break;
+                
+                case RCOSC_1_MHZ_CLK_SRC:
+                    set_clock_frequency_globals(FREQ_1MHZ);
+                break;
+                
+                case CCC2ASCI_CLK_SRC:
+                    /* Fall through. */
+                default:
+                    set_clock_frequency_globals(FREQ_1MHZ);
+                break;
+            }   
+        }
+    }
+    else
+    {
+        /* PLL initialization mode. Running from 25/50MHZ RC oscillator. */
+        clk_src = get_rcosc_25_50mhz_frequency();
+        set_clock_frequency_globals(clk_src);
+    }
+    
+#else
+    /*
+     * Reset the clock frequency global variables to the values delected in the
+     * Libero flow.
+     */
+    SystemCoreClock = MSS_SYS_M3_CLK_FREQ;
+    g_FrequencyPCLK0 = MSS_SYS_APB_0_CLK_FREQ;
+    g_FrequencyPCLK1 = MSS_SYS_APB_1_CLK_FREQ;
+    g_FrequencyPCLK2 = MSS_SYS_APB_2_CLK_FREQ;
+    g_FrequencyFIC0 = MSS_SYS_FIC_0_CLK_FREQ;
+    g_FrequencyFIC1 = MSS_SYS_FIC_1_CLK_FREQ;
+    g_FrequencyFIC64 = MSS_SYS_FIC64_CLK_FREQ;
+#endif
+}
+
+/***************************************************************************//**
+ * Find out frequency generated by the 25_50mhz RC osciallator.
+ */
+static uint32_t get_rcosc_25_50mhz_frequency(void)
+{
+    uint32_t rcosc_div2;
+    uint32_t rcosc_frequency;
+    
+    rcosc_div2 = SYSREG->MSSDDR_PLL_STATUS & RCOSC_DIV2_MASK;
+    if(0u == rcosc_div2)
+    {
+        /* 25_50mhz oscillator is configured for 25 MHz operations. */
+        rcosc_frequency = FREQ_25MHZ;
+    }
+    else
+    {
+        /* 25_50mhz oscillator is configured for 50 MHz operations. */
+        rcosc_frequency = FREQ_50MHZ;
+    }
+    
+    return rcosc_frequency;
+}
+
+/***************************************************************************//**
+   Set the value of the clock frequency global variables based on the value of
+   standby_clk passed as parameter.
+   The following global variables are set by this function:
+        - SystemCoreClock
+        - g_FrequencyPCLK0
+        - g_FrequencyPCLK1
+        - g_FrequencyPCLK2
+        - g_FrequencyFIC0
+        - g_FrequencyFIC1
+        - g_FrequencyFIC64
+ */
+static void set_clock_frequency_globals(uint32_t standby_clk)
+{
+    SystemCoreClock = standby_clk;
+    g_FrequencyPCLK0 = standby_clk;
+    g_FrequencyPCLK1 = standby_clk;
+    g_FrequencyPCLK2 = MSS_SYS_APB_2_CLK_FREQ;
+    g_FrequencyFIC0 = standby_clk;
+    g_FrequencyFIC1 = standby_clk;
+    g_FrequencyFIC64 = standby_clk;
+}
+
+/***************************************************************************//**
+ * Write 16-bit configuration values into 32-bit word aligned registers.
+ */
+#if (MSS_SYS_MDDR_CONFIG_BY_CORTEX || MSS_SYS_FDDR_CONFIG_BY_CORTEX)
+static void copy_cfg16_to_regs
+(
+    volatile uint32_t * p_regs,
+    const uint16_t * p_cfg,
+    uint32_t nb_16bit_words
+)
+{
+    uint32_t inc;
+    
+    for(inc = 0u; inc < nb_16bit_words; ++inc)
+    {
+        p_regs[inc] = p_cfg[inc];
+    }
+}
+#endif
+
+/***************************************************************************//**
+ * Configure peripheral using register address and register value pairs.
+ */
+#if MSS_SYS_SERDES_CONFIG_BY_CORTEX
+static void config_by_addr_value
+(
+    const cfg_addr_value_pair_t * p_addr_value_pair,
+    uint32_t nb_of_cfg_pairs
+)
+{
+    uint32_t inc;
+    
+    for(inc = 0u; inc < nb_of_cfg_pairs; ++inc)
+    {
+        *p_addr_value_pair[inc].p_reg = p_addr_value_pair[inc].value;
+    }
+}
+#endif
+
+/***************************************************************************//**
+ * DDR subsystem configuration.
+ */
+#if (MSS_SYS_MDDR_CONFIG_BY_CORTEX || MSS_SYS_FDDR_CONFIG_BY_CORTEX)
+
+#define NB_OF_DDRC_REGS_TO_CONFIG       57u
+#define NB_OF_DDR_PHY_REGS_TO_CONFIG    65u
+
+static void config_ddr_subsys
+(
+    const ddr_subsys_cfg_t * p_ddr_subsys_cfg,
+    DDRCore_TypeDef * p_ddr_subsys_regs
+)
+{
+    volatile uint32_t * p_regs;
+    const uint16_t * p_cfg;
+    
+    /*--------------------------------------------------------------------------
+     * Configure DDR controller part of the MDDR subsystem.
+     */
+    p_cfg = &p_ddr_subsys_cfg->ddrc.DYN_SOFT_RESET_CR;
+    p_regs = &p_ddr_subsys_regs->ddrc.DYN_SOFT_RESET_CR;
+
+    copy_cfg16_to_regs(p_regs, p_cfg, NB_OF_DDRC_REGS_TO_CONFIG);
+    
+    /*--------------------------------------------------------------------------
+     * Configure DDR PHY.
+     */
+    p_cfg = &p_ddr_subsys_cfg->phy.LOOPBACK_TEST_CR;
+    p_regs = &p_ddr_subsys_regs->phy.LOOPBACK_TEST_CR;
+
+    copy_cfg16_to_regs(p_regs, p_cfg, NB_OF_DDR_PHY_REGS_TO_CONFIG);
+    
+    /*--------------------------------------------------------------------------
+     * Configure DDR FIC.
+     */
+    p_ddr_subsys_regs->fic.NB_ADDR_CR = p_ddr_subsys_cfg->fic.NB_ADDR_CR;
+    p_ddr_subsys_regs->fic.NBRWB_SIZE_CR = p_ddr_subsys_cfg->fic.NBRWB_SIZE_CR;
+    p_ddr_subsys_regs->fic.WB_TIMEOUT_CR = p_ddr_subsys_cfg->fic.WB_TIMEOUT_CR;
+    p_ddr_subsys_regs->fic.HPD_SW_RW_EN_CR = p_ddr_subsys_cfg->fic.HPD_SW_RW_EN_CR;
+    p_ddr_subsys_regs->fic.HPD_SW_RW_INVAL_CR = p_ddr_subsys_cfg->fic.HPD_SW_RW_INVAL_CR;
+    p_ddr_subsys_regs->fic.SW_WR_ERCLR_CR = p_ddr_subsys_cfg->fic.SW_WR_ERCLR_CR;
+    p_ddr_subsys_regs->fic.ERR_INT_ENABLE_CR = p_ddr_subsys_cfg->fic.ERR_INT_ENABLE_CR;
+    p_ddr_subsys_regs->fic.NUM_AHB_MASTERS_CR = p_ddr_subsys_cfg->fic.NUM_AHB_MASTERS_CR;
+    p_ddr_subsys_regs->fic.LOCK_TIMEOUTVAL_CR[0] = p_ddr_subsys_cfg->fic.LOCK_TIMEOUTVAL_1_CR;
+    p_ddr_subsys_regs->fic.LOCK_TIMEOUTVAL_CR[1] = p_ddr_subsys_cfg->fic.LOCK_TIMEOUTVAL_2_CR;
+    p_ddr_subsys_regs->fic.LOCK_TIMEOUT_EN_CR = p_ddr_subsys_cfg->fic.LOCK_TIMEOUT_EN_CR;
+
+    /*--------------------------------------------------------------------------
+     * Enable DDR.
+     */
+    p_ddr_subsys_regs->ddrc.DYN_SOFT_RESET_CR = 0x01u;
+    
+    while(0x0000u == p_ddr_subsys_regs->ddrc.DDRC_SR)
+    {
+        ;
+    }        
+}
+
+#endif
+
+/***************************************************************************//**
+ * Configure SERDES interfaces.
+ */
+#if MSS_SYS_SERDES_CONFIG_BY_CORTEX
+
+static void configure_serdes_intf(void)
+{
+#if MSS_SYS_SERDES_0_CONFIG_BY_CORTEX
+    config_by_addr_value(g_m2s_serdes_0_config, SERDES_0_CFG_NB_OF_PAIRS);
+#endif
+
+#if MSS_SYS_SERDES_1_CONFIG_BY_CORTEX
+    config_by_addr_value(g_m2s_serdes_1_config, SERDES_1_CFG_NB_OF_PAIRS);
+#endif
+
+#if MSS_SYS_SERDES_2_CONFIG_BY_CORTEX
+    config_by_addr_value(g_m2s_serdes_2_config, SERDES_2_CFG_NB_OF_PAIRS);
+#endif
+
+#if MSS_SYS_SERDES_3_CONFIG_BY_CORTEX
+    config_by_addr_value(g_m2s_serdes_3_config, SERDES_3_CFG_NB_OF_PAIRS);
+#endif
+}
+
+#endif
+
+/*------------------------------------------------------------------------------
+  Retrieve silicon revision from system registers.
+ */
+static uint32_t get_silicon_revision(void)
+{
+    uint32_t silicon_revision;
+    uint32_t device_version;
+    
+    device_version = SYSREG->DEVICE_VERSION;
+    switch(device_version)
+    {
+        case 0x0000F802:
+            silicon_revision = M2S050_REV_A_SILICON;
+            break;
+            
+        case 0x0001F802:
+            silicon_revision = M2S050_REV_B_SILICON;
+            break;
+            
+        default:
+            silicon_revision = UNKNOWN_SILICON_REV;
+            break;
+    }
+    
+    return silicon_revision;
+}
+
+/*------------------------------------------------------------------------------
+  Workarounds for various silicon versions.
+ */
+static void silicon_workarounds(void)
+{
+    uint32_t silicon_revision;
+    
+    silicon_revision = get_silicon_revision();
+    
+    switch(silicon_revision)
+    {
+        case M2S050_REV_A_SILICON:
+            m2s050_rev_a_workarounds();
+            break;
+            
+        case M2S050_REV_B_SILICON:
+            /* Fall through. */
+        case UNKNOWN_SILICON_REV:
+            /* Fall through. */
+        default:
+            break;
+    }
+}
+
+/*------------------------------------------------------------------------------
+  Silicon workarounds for M2S050 rev A.
+ */
+static void m2s050_rev_a_workarounds(void)
+{
+    /*--------------------------------------------------------------------------
+     * Work around a couple of silicon issues:
+     */
+    /* DDR_CLK_EN <- 1 */
+    SYSREG->MSSDDR_FACC1_CR |= (uint32_t)1 << DDR_CLK_EN_SHIFT;
+    
+    /* CONTROLLER_PLL_INIT <- 0 */
+    SYSREG->MSSDDR_FACC1_CR = SYSREG->MSSDDR_FACC1_CR & ~CONTROLLER_PLL_INIT_MASK;
+}
+
+/*------------------------------------------------------------------------------
+  Complete clock configuration if requested by Libero.
+ */
+#if (MSS_SYS_FACC_INIT_BY_CORTEX == 1)
+static void complete_clock_config(void)
+{
+    uint32_t pll_locked;
+    
+    /* Wait for fabric PLL to lock. */
+    do {
+        pll_locked = SYSREG->MSSDDR_PLL_STATUS & FAB_PLL_LOCK_MASK;
+    } while(!pll_locked);
+    
+    /* Negate MPLL bypass. */
+    SYSREG->MSSDDR_PLL_STATUS_HIGH_CR &= ~FACC_PLL_BYPASS_MASK;
+    
+    /* Wait for MPLL to lock. */
+    do {
+        pll_locked = SYSREG->MSSDDR_PLL_STATUS & MPLL_LOCK_MASK;
+    } while(!pll_locked);
+    
+    /* Switch FACC from standby to run mode. */
+    SYSREG->MSSDDR_FACC1_CR &= ~FACC_GLMUX_SEL_MASK;
+
+    /* Negate FPGA_SOFTRESET to de-assert MSS_RESET_N_M2F in the fabric */
+    SYSREG->SOFT_RST_CR &= ~SYSREG_FPGA_SOFTRESET_MASK;
+}
+#endif
+
diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/CMSIS/system_m2sxxx.h b/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/CMSIS/system_m2sxxx.h
new file mode 100644
index 000000000..3b753767a
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/CMSIS/system_m2sxxx.h
@@ -0,0 +1,49 @@
+/*******************************************************************************
+ * (c) Copyright 2012-2013 Microsemi SoC Products Group. All rights reserved.
+ * 
+ *  SmartFusion2 CMSIS system initialization.
+ *
+ * SVN $Revision: 5280 $
+ * SVN $Date: 2013-03-22 20:51:50 +0000 (Fri, 22 Mar 2013) $
+ */
+
+#ifndef SYSTEM_M2SXXX_H
+#define SYSTEM_M2SXXX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif 
+
+/* Standard CMSIS global variables. */
+extern uint32_t SystemCoreClock;    /*!< System Clock Frequency (Core Clock) */
+
+/* SmartFusion2 specific clocks. */
+extern uint32_t g_FrequencyPCLK0;   /*!< Clock frequency of APB bus 0. */  
+extern uint32_t g_FrequencyPCLK1;   /*!< Clock frequency of APB bus 1. */
+extern uint32_t g_FrequencyPCLK2;   /*!< Clock frequency of APB bus 2. */
+extern uint32_t g_FrequencyFIC0;    /*!< Clock frequecny of FPGA fabric interface controller 1. */
+extern uint32_t g_FrequencyFIC1;    /*!< Clock frequecny of FPGA fabric inteface controller 2. */
+extern uint32_t g_FrequencyFIC64;   /*!< Clock frequecny of 64-bit FPGA fabric interface controller. */
+
+
+/***************************************************************************//**
+ * The SystemInit() is a standard CMSIS function called during system startup.
+ * It is meant to perform low level hardware setup such as configuring DDR and
+ * SERDES controllers.
+ */
+void SystemInit(void);
+
+/***************************************************************************//**
+ * The SystemCoreClockUpdate() is a standard CMSIS function which can be called
+ * by the application in order to ensure that the SystemCoreClock global
+ * variable contains the up to date Cortex-M3 core frequency. Calling this
+ * function also updates the global variables containing the frequencies of the
+ * APB busses connecting the peripherals.
+ */
+void SystemCoreClockUpdate(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/RTOSDemo_hw_platform.h b/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/RTOSDemo_hw_platform.h
new file mode 100644
index 000000000..1fffa7163
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/RTOSDemo_hw_platform.h
@@ -0,0 +1,16 @@
+#ifndef RTOSDemo_HW_PLATFORM_H_
+#define RTOSDemo_HW_PLATFORM_H_
+/*****************************************************************************
+*
+*Created by Actel SmartDesign  Sun May 05 13:23:22 2013
+*
+*Memory map specification for peripherals in RTOSDemo
+*/
+
+/*-----------------------------------------------------------------------------
+* CM3 subsystem memory map
+* Master(s) for this subsystem: CM3 
+*---------------------------------------------------------------------------*/
+
+
+#endif /* RTOSDemo_HW_PLATFORM_H_*/
diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_gpio/mss_gpio.c b/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_gpio/mss_gpio.c
new file mode 100644
index 000000000..096a82794
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_gpio/mss_gpio.c
@@ -0,0 +1,296 @@
+/*******************************************************************************
+ * (c) Copyright 2008-2013 Microsemi SoC Products Group.  All rights reserved.
+ * 
+ * SmartFusion2 microcontroller subsystem GPIO bare metal driver implementation.
+ *
+ * SVN $Revision: 5394 $
+ * SVN $Date: 2013-03-27 20:56:36 +0000 (Wed, 27 Mar 2013) $
+ */
+#include "mss_gpio.h"
+#include "../../CMSIS/mss_assert.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif 
+
+/*-------------------------------------------------------------------------*//**
+ * Defines.
+ */
+#define GPIO_INT_ENABLE_MASK        ((uint32_t)0x00000008uL)
+#define OUTPUT_BUFFER_ENABLE_MASK   0x00000004u
+
+#define NB_OF_GPIO  ((uint32_t)32)
+
+/*-------------------------------------------------------------------------*//**
+ * Lookup table of GPIO configuration registers address indexed on GPIO ID.
+ */
+static uint32_t volatile * const g_config_reg_lut[NB_OF_GPIO] =
+{
+    &(GPIO->GPIO_0_CFG),
+    &(GPIO->GPIO_1_CFG),
+    &(GPIO->GPIO_2_CFG),
+    &(GPIO->GPIO_3_CFG),
+    &(GPIO->GPIO_4_CFG),
+    &(GPIO->GPIO_5_CFG),
+    &(GPIO->GPIO_6_CFG),
+    &(GPIO->GPIO_7_CFG),
+    &(GPIO->GPIO_8_CFG),
+    &(GPIO->GPIO_9_CFG),
+    &(GPIO->GPIO_10_CFG),
+    &(GPIO->GPIO_11_CFG),
+    &(GPIO->GPIO_12_CFG),
+    &(GPIO->GPIO_13_CFG),
+    &(GPIO->GPIO_14_CFG),
+    &(GPIO->GPIO_15_CFG),
+    &(GPIO->GPIO_16_CFG),
+    &(GPIO->GPIO_17_CFG),
+    &(GPIO->GPIO_18_CFG),
+    &(GPIO->GPIO_19_CFG),
+    &(GPIO->GPIO_20_CFG),
+    &(GPIO->GPIO_21_CFG),
+    &(GPIO->GPIO_22_CFG),
+    &(GPIO->GPIO_23_CFG),
+    &(GPIO->GPIO_24_CFG),
+    &(GPIO->GPIO_25_CFG),
+    &(GPIO->GPIO_26_CFG),
+    &(GPIO->GPIO_27_CFG),
+    &(GPIO->GPIO_28_CFG),
+    &(GPIO->GPIO_29_CFG),
+    &(GPIO->GPIO_30_CFG),
+    &(GPIO->GPIO_31_CFG)
+};
+
+/*-------------------------------------------------------------------------*//**
+ * Lookup table of Cortex-M3 GPIO interrupt number indexed on GPIO ID.
+ */
+static const IRQn_Type g_gpio_irqn_lut[NB_OF_GPIO] =
+{
+    GPIO0_IRQn,
+    GPIO1_IRQn,
+    GPIO2_IRQn,
+    GPIO3_IRQn,
+    GPIO4_IRQn,
+    GPIO5_IRQn,
+    GPIO6_IRQn,
+    GPIO7_IRQn,
+    GPIO8_IRQn,
+    GPIO9_IRQn,
+    GPIO10_IRQn,
+    GPIO11_IRQn,
+    GPIO12_IRQn,
+    GPIO13_IRQn,
+    GPIO14_IRQn,
+    GPIO15_IRQn,
+    GPIO16_IRQn,
+    GPIO17_IRQn,
+    GPIO18_IRQn,
+    GPIO19_IRQn,
+    GPIO20_IRQn,
+    GPIO21_IRQn,
+    GPIO22_IRQn,
+    GPIO23_IRQn,
+    GPIO24_IRQn,
+    GPIO25_IRQn,
+    GPIO26_IRQn,
+    GPIO27_IRQn,
+    GPIO28_IRQn,
+    GPIO29_IRQn,
+    GPIO30_IRQn,
+    GPIO31_IRQn
+};
+
+/*-------------------------------------------------------------------------*//**
+ * MSS_GPIO_init
+ * See "mss_gpio.h" for details of how to use this function.
+ */
+void MSS_GPIO_init( void )
+{
+    uint32_t inc;
+    
+    /* reset MSS GPIO hardware */
+    SYSREG->SOFT_RST_CR |= SYSREG_GPIO_SOFTRESET_MASK;
+    SYSREG->SOFT_RST_CR |= (SYSREG_GPIO_7_0_SOFTRESET_MASK |
+                            SYSREG_GPIO_15_8_SOFTRESET_MASK |
+                            SYSREG_GPIO_23_16_SOFTRESET_MASK |
+                            SYSREG_GPIO_31_24_SOFTRESET_MASK);
+                            
+    /* Clear any previously pended MSS GPIO interrupt */
+    for(inc = 0U; inc < NB_OF_GPIO; ++inc)
+    {
+        NVIC_DisableIRQ(g_gpio_irqn_lut[inc]);
+        NVIC_ClearPendingIRQ(g_gpio_irqn_lut[inc]);
+    }
+    /* Take MSS GPIO hardware out of reset. */
+    SYSREG->SOFT_RST_CR &= ~(SYSREG_GPIO_7_0_SOFTRESET_MASK |
+                             SYSREG_GPIO_15_8_SOFTRESET_MASK |
+                             SYSREG_GPIO_23_16_SOFTRESET_MASK |
+                             SYSREG_GPIO_31_24_SOFTRESET_MASK);
+    SYSREG->SOFT_RST_CR &= ~SYSREG_GPIO_SOFTRESET_MASK;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * MSS_GPIO_config
+ * See "mss_gpio.h" for details of how to use this function.
+ */
+void MSS_GPIO_config
+(
+    mss_gpio_id_t port_id,
+    uint32_t config
+)
+{
+    uint32_t gpio_idx = (uint32_t)port_id;
+    
+    ASSERT(gpio_idx < NB_OF_GPIO);
+
+    if(gpio_idx < NB_OF_GPIO)
+    {
+        *(g_config_reg_lut[gpio_idx]) = config;
+    }
+}
+
+/*-------------------------------------------------------------------------*//**
+ * MSS_GPIO_set_output
+ * See "mss_gpio.h" for details of how to use this function.
+ */
+void MSS_GPIO_set_output
+(
+    mss_gpio_id_t port_id,
+    uint8_t value
+)
+{
+    uint32_t gpio_setting;
+    uint32_t gpio_idx = (uint32_t)port_id;
+    
+    ASSERT(gpio_idx < NB_OF_GPIO);
+    
+    if(gpio_idx < NB_OF_GPIO)
+    {
+        gpio_setting = GPIO->GPIO_OUT;
+        gpio_setting &= ~((uint32_t)0x01u << gpio_idx);
+        gpio_setting |= ((uint32_t)value & 0x01u) << gpio_idx;
+        GPIO->GPIO_OUT = gpio_setting;
+    }
+}
+
+/*-------------------------------------------------------------------------*//**
+ * MSS_GPIO_drive_inout
+ * See "mss_gpio.h" for details of how to use this function.
+ */
+void MSS_GPIO_drive_inout
+(
+    mss_gpio_id_t port_id,
+    mss_gpio_inout_state_t inout_state
+)
+{
+    uint32_t outputs_state;
+    uint32_t config;
+    uint32_t gpio_idx = (uint32_t)port_id;
+    
+    ASSERT(gpio_idx < NB_OF_GPIO);
+    
+    if(gpio_idx < NB_OF_GPIO)
+    {
+        switch(inout_state)
+        {
+            case MSS_GPIO_DRIVE_HIGH:
+                /* Set output high */
+                outputs_state = GPIO->GPIO_OUT;
+                outputs_state |= (uint32_t)1 << gpio_idx;
+                GPIO->GPIO_OUT = outputs_state;
+                /* Enable output buffer */
+                config = *(g_config_reg_lut[gpio_idx]);
+                config |= OUTPUT_BUFFER_ENABLE_MASK;
+                *(g_config_reg_lut[gpio_idx]) = config;
+            break;
+                
+            case MSS_GPIO_DRIVE_LOW:
+                /* Set output low */
+                outputs_state = GPIO->GPIO_OUT;
+                outputs_state &= ~((uint32_t)((uint32_t)1 << gpio_idx));
+                GPIO->GPIO_OUT = outputs_state;
+                /* Enable output buffer */
+                config = *(g_config_reg_lut[gpio_idx]);
+                config |= OUTPUT_BUFFER_ENABLE_MASK;
+                *(g_config_reg_lut[gpio_idx]) = config;
+            break;
+                
+            case MSS_GPIO_HIGH_Z:
+                /* Disable output buffer */
+                config = *(g_config_reg_lut[gpio_idx]);
+                config &= ~OUTPUT_BUFFER_ENABLE_MASK;
+                *(g_config_reg_lut[gpio_idx]) = config;
+            break;
+                
+            default:
+                ASSERT(0);
+            break;
+        }
+    }
+}
+
+/*-------------------------------------------------------------------------*//**
+ * MSS_GPIO_enable_irq
+ * See "mss_gpio.h" for details of how to use this function.
+ */
+void MSS_GPIO_enable_irq
+(
+    mss_gpio_id_t port_id
+)
+{
+    uint32_t cfg_value;
+    uint32_t gpio_idx = (uint32_t)port_id;
+    
+    ASSERT(gpio_idx < NB_OF_GPIO);
+    
+    if(gpio_idx < NB_OF_GPIO)
+    {
+        cfg_value = *(g_config_reg_lut[gpio_idx]);
+        *(g_config_reg_lut[gpio_idx]) = (cfg_value | GPIO_INT_ENABLE_MASK);
+        NVIC_EnableIRQ(g_gpio_irqn_lut[gpio_idx]);
+    }
+}
+
+/*-------------------------------------------------------------------------*//**
+ * MSS_GPIO_disable_irq
+ * See "mss_gpio.h" for details of how to use this function.
+ */
+void MSS_GPIO_disable_irq
+(
+    mss_gpio_id_t port_id
+)
+{
+    uint32_t cfg_value;
+    uint32_t gpio_idx = (uint32_t)port_id;
+    
+    ASSERT(gpio_idx < NB_OF_GPIO);
+
+    if(gpio_idx < NB_OF_GPIO)
+    {
+        cfg_value = *(g_config_reg_lut[gpio_idx]);
+        *(g_config_reg_lut[gpio_idx]) = (cfg_value & ~GPIO_INT_ENABLE_MASK);
+    }
+}
+
+/*-------------------------------------------------------------------------*//**
+ * MSS_GPIO_clear_irq
+ * See "mss_gpio.h" for details of how to use this function.
+ */
+void MSS_GPIO_clear_irq
+(
+    mss_gpio_id_t port_id
+)
+{
+    uint32_t gpio_idx = (uint32_t)port_id;
+    
+    ASSERT(gpio_idx < NB_OF_GPIO);
+    
+    if(gpio_idx < NB_OF_GPIO)
+    {
+        GPIO->GPIO_IRQ = ((uint32_t)1) << gpio_idx;
+    }
+}
+
+#ifdef __cplusplus
+}
+#endif
+
diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_gpio/mss_gpio.h b/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_gpio/mss_gpio.h
new file mode 100644
index 000000000..b3ecb867a
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_gpio/mss_gpio.h
@@ -0,0 +1,507 @@
+/*******************************************************************************
+ * (c) Copyright 2008-2013 Microsemi SoC Products Group.  All rights reserved.
+ * 
+ *  SmartFusion2 Microcontroller Subsystem GPIO bare metal software driver public
+ *  API.
+ *
+ * SVN $Revision: 5487 $
+ * SVN $Date: 2013-03-29 15:33:22 +0000 (Fri, 29 Mar 2013) $
+ */
+
+/*=========================================================================*//**
+  @mainpage SmartFusion2 MSS GPIO Bare Metal Driver.
+
+  @section intro_sec Introduction
+  The SmartFusion2 Microcontroller Subsystem (MSS) includes a block of 32 general
+  purpose input/outputs (GPIO).
+  This software driver provides a set of functions for controlling the MSS GPIO
+  block as part of a bare metal system where no operating system is available.
+  This driver can be adapted for use as part of an operating system but the
+  implementation of the adaptation layer between this driver and the operating
+  system's driver model is outside the scope of this driver.
+  
+  @section hw_dependencies Hardware Flow Dependencies
+  The configuration of all features of the MSS GPIOs is covered by this driver
+  with the exception of the SmartFusion2 IOMUX configuration. SmartFusion2
+  allows multiple non-concurrent uses of some external pins through IOMUX
+  configuration. This feature allows optimization of external pin usage by
+  assigning external pins for use by either the microcontroller subsystem or the
+  FPGA fabric. The MSS GPIOs share SmartFusion2 device external pins with the
+  FPGA fabric and with other MSS peripherals via an IOMUX. The MSS GPIO ports
+  can alternatively be routed to the FPGA fabric through an IOMUX. 
+  The IOMUXs are configured using the SmartFusion2 MSS configurator tool. You
+  must ensure that the MSS GPIOs are enabled and configured in the SmartFusion2
+  MSS configurator if you wish to use them. For more information on IOMUXs,
+  refer to the IOMUX section of the SmartFusion2 Microcontroller Subsystem (MSS)
+  User’s Guide.
+  The base address, register addresses and interrupt number assignment for the
+  MSS GPIO block are defined as constants in the SmartFusion2 CMSIS HAL. You
+  must ensure that the latest SmartFusion2 CMSIS HAL is included in the project
+  settings of the software tool chain used to build your project and that it is
+  generated into your project.
+  
+  @section theory_op Theory of Operation
+  The MSS GPIO driver functions are grouped into the following categories:
+    - Initialization
+    - Configuration
+    - Reading and setting GPIO state
+    - Interrupt control
+    
+  Initialization
+  The MSS GPIO driver is initialized through a call to the MSS_GPIO_init()
+  function. The MSS_GPIO_init() function must be called before any other MSS
+  GPIO driver functions can be called.
+  
+  Configuration
+  Each GPIO port is individually configured through a call to the
+  MSS_GPIO_config() function. Configuration includes deciding if a GPIO port
+  will be used as an input, an output or both. GPIO ports configured as inputs
+  can be further configured to generate interrupts based on the input's state.
+  Interrupts can be level or edge sensitive.
+  
+  Reading and Setting GPIO State
+  The state of the GPIO ports can be read and set using the following functions:
+    - MSS_GPIO_get_inputs()
+    - MSS_GPIO_get_outputs()
+    - MSS_GPIO_set_outputs()
+    - MSS_GPIO_set_output()
+    - MSS_GPIO_drive_inout()
+  
+  Interrupt Control
+  Interrupts generated by GPIO ports configured as inputs are controlled using
+  the following functions:
+    - MSS_GPIO_enable_irq()
+    - MSS_GPIO_disable_irq()
+    - MSS_GPIO_clear_irq()
+  
+ *//*=========================================================================*/
+#ifndef MSS_GPIO_H_
+#define MSS_GPIO_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif 
+
+#include "../../CMSIS/m2sxxx.h"
+
+/*-------------------------------------------------------------------------*//**
+  The mss_gpio_id_t enumeration is used to identify individual GPIO ports as an
+  argument to functions:
+    - MSS_GPIO_config()
+    - MSS_GPIO_set_output() and MSS_GPIO_drive_inout()
+    - MSS_GPIO_enable_irq(), MSS_GPIO_disable_irq() and MSS_GPIO_clear_irq()
+ */
+typedef enum __mss_gpio_id_t
+{
+    MSS_GPIO_0 = 0,
+    MSS_GPIO_1 = 1,
+    MSS_GPIO_2 = 2,
+    MSS_GPIO_3 = 3,
+    MSS_GPIO_4 = 4,
+    MSS_GPIO_5 = 5,
+    MSS_GPIO_6 = 6,
+    MSS_GPIO_7 = 7,
+    MSS_GPIO_8 = 8,
+    MSS_GPIO_9 = 9,
+    MSS_GPIO_10 = 10,
+    MSS_GPIO_11 = 11,
+    MSS_GPIO_12 = 12,
+    MSS_GPIO_13 = 13,
+    MSS_GPIO_14 = 14,
+    MSS_GPIO_15 = 15,
+    MSS_GPIO_16 = 16,
+    MSS_GPIO_17 = 17,
+    MSS_GPIO_18 = 18,
+    MSS_GPIO_19 = 19,
+    MSS_GPIO_20 = 20,
+    MSS_GPIO_21 = 21,
+    MSS_GPIO_22 = 22,
+    MSS_GPIO_23 = 23,
+    MSS_GPIO_24 = 24,
+    MSS_GPIO_25 = 25,
+    MSS_GPIO_26 = 26,
+    MSS_GPIO_27 = 27,
+    MSS_GPIO_28 = 28,
+    MSS_GPIO_29 = 29,
+    MSS_GPIO_30 = 30,
+    MSS_GPIO_31 = 31
+} mss_gpio_id_t;
+
+/*-------------------------------------------------------------------------*//**
+  These constant definitions are used as an argument to the
+  MSS_GPIO_set_outputs() function to identify GPIO ports. A logical OR of these
+  constants can be used to specify multiple GPIO ports.
+  These definitions can also be used to identify GPIO ports through logical
+  operations on the return value of the MSS_GPIO_get_inputs() function.
+ */
+#define MSS_GPIO_0_MASK         0x00000001uL
+#define MSS_GPIO_1_MASK         0x00000002uL
+#define MSS_GPIO_2_MASK         0x00000004uL
+#define MSS_GPIO_3_MASK         0x00000008uL
+#define MSS_GPIO_4_MASK         0x00000010uL
+#define MSS_GPIO_5_MASK         0x00000020uL
+#define MSS_GPIO_6_MASK         0x00000040uL
+#define MSS_GPIO_7_MASK         0x00000080uL
+#define MSS_GPIO_8_MASK         0x00000100uL
+#define MSS_GPIO_9_MASK         0x00000200uL
+#define MSS_GPIO_10_MASK        0x00000400uL
+#define MSS_GPIO_11_MASK        0x00000800uL
+#define MSS_GPIO_12_MASK        0x00001000uL
+#define MSS_GPIO_13_MASK        0x00002000uL
+#define MSS_GPIO_14_MASK        0x00004000uL
+#define MSS_GPIO_15_MASK        0x00008000uL
+#define MSS_GPIO_16_MASK        0x00010000uL
+#define MSS_GPIO_17_MASK        0x00020000uL
+#define MSS_GPIO_18_MASK        0x00040000uL
+#define MSS_GPIO_19_MASK        0x00080000uL
+#define MSS_GPIO_20_MASK        0x00100000uL
+#define MSS_GPIO_21_MASK        0x00200000uL
+#define MSS_GPIO_22_MASK        0x00400000uL
+#define MSS_GPIO_23_MASK        0x00800000uL
+#define MSS_GPIO_24_MASK        0x01000000uL
+#define MSS_GPIO_25_MASK        0x02000000uL
+#define MSS_GPIO_26_MASK        0x04000000uL
+#define MSS_GPIO_27_MASK        0x08000000uL
+#define MSS_GPIO_28_MASK        0x10000000uL
+#define MSS_GPIO_29_MASK        0x20000000uL
+#define MSS_GPIO_30_MASK        0x40000000uL
+#define MSS_GPIO_31_MASK        0x80000000uL
+
+/*-------------------------------------------------------------------------*//**
+  These constant definitions are used as an argument to the MSS_GPIO_config()
+  function to specify the I/O mode of each GPIO port.
+ */
+#define MSS_GPIO_INPUT_MODE              0x0000000002uL
+#define MSS_GPIO_OUTPUT_MODE             0x0000000005uL
+#define MSS_GPIO_INOUT_MODE              0x0000000003uL
+
+/*-------------------------------------------------------------------------*//**
+  These constant definitions are used as an argument to the MSS_GPIO_config()
+  function to specify the interrupt mode of each GPIO port.
+ */
+#define MSS_GPIO_IRQ_LEVEL_HIGH           0x0000000000uL
+#define MSS_GPIO_IRQ_LEVEL_LOW            0x0000000020uL
+#define MSS_GPIO_IRQ_EDGE_POSITIVE        0x0000000040uL
+#define MSS_GPIO_IRQ_EDGE_NEGATIVE        0x0000000060uL
+#define MSS_GPIO_IRQ_EDGE_BOTH            0x0000000080uL
+
+/*-------------------------------------------------------------------------*//**
+  The mss_gpio_inout_state_t enumeration is used to specify the output state of
+  an INOUT GPIO port as an argument to the MSS_GPIO_drive_inout() function.
+ */
+typedef enum mss_gpio_inout_state
+{
+    MSS_GPIO_DRIVE_LOW = 0,
+    MSS_GPIO_DRIVE_HIGH,
+    MSS_GPIO_HIGH_Z
+} mss_gpio_inout_state_t;
+
+/*-------------------------------------------------------------------------*//**
+  The MSS_GPIO_init() function initializes the SmartFusion2 MSS GPIO block. It
+  resets the MSS GPIO hardware block and it also clears any pending MSS GPIO
+  interrupts in the ARM Cortex-M3 interrupt controller. When the function exits,
+  it takes the MSS GPIO block out of reset.
+  
+   @param
+    This function has no parameters.
+    
+   @return
+    This function does not return a value.
+ */
+void MSS_GPIO_init( void );
+
+/*-------------------------------------------------------------------------*//**
+  The MSS_GPIO_config() function is used to configure an individual GPIO port.
+ 
+  @param port_id
+    The port_id parameter identifies the GPIO port to be configured. An
+    enumeration item of the form MSS_GPIO_n, where n is the number of the GPIO
+    port, is used to identify the GPIO port. For example, MSS_GPIO_0 identifies
+    the first GPIO port and MSS_GPIO_31 is the last one.
+    
+  @param config
+    The config parameter specifies the configuration to be applied to the GPIO
+    port identified by the port_id parameter. It is a logical OR of the required
+    I/O mode and the required interrupt mode. The interrupt mode is not relevant
+    if the GPIO is configured as an output only.
+       These I/O mode constants are allowed:
+           - MSS_GPIO_INPUT_MODE
+           - MSS_GPIO_OUTPUT_MODE
+           - MSS_GPIO_INOUT_MODE
+       These interrupt mode constants are allowed:
+           - MSS_GPIO_IRQ_LEVEL_HIGH
+           - MSS_GPIO_IRQ_LEVEL_LOW
+           - MSS_GPIO_IRQ_EDGE_POSITIVE
+           - MSS_GPIO_IRQ_EDGE_NEGATIVE
+           - MSS_GPIO_IRQ_EDGE_BOTH
+  
+   @return
+    none.
+
+  Example:
+  The following call will configure GPIO 4 as an input generating interrupts on
+  a Low to High transition of the input:
+  @code
+  MSS_GPIO_config( MSS_GPIO_4, MSS_GPIO_INPUT_MODE | MSS_GPIO_IRQ_EDGE_POSITIVE );
+  @endcode
+ */
+void MSS_GPIO_config
+(
+    mss_gpio_id_t port_id,
+    uint32_t config
+);
+
+/*-------------------------------------------------------------------------*//**
+  The MSS_GPIO_set_outputs() function is used to set the state of all GPIO ports
+  configured as outputs.
+ 
+  @param value
+    The value parameter specifies the state of the GPIO ports configured as
+    outputs. It is a bit mask of the form (MSS_GPIO_n_MASK | MSS_GPIO_m_MASK)
+    where n and m are numbers identifying GPIOs. For example, (MSS_GPIO_0_MASK |
+    MSS_GPIO_1_MASK | MSS_GPIO_2_MASK ) specifies that the first, second and
+    third GPIO outputs must be set High and all other GPIO outputs set Low. The
+    driver provides 32 mask constants, MSS_GPIO_0_MASK to MSS_GPIO_31_MASK
+    inclusive, for this purpose.
+  
+  @return
+    none.
+
+  Example 1:
+    Set GPIOs outputs 0 and 8 high and all other GPIO outputs low.
+    @code
+        MSS_GPIO_set_outputs( MSS_GPIO_0_MASK | MSS_GPIO_8_MASK );
+    @endcode
+
+  Example 2:
+    Set GPIOs outputs 2 and 4 low without affecting other GPIO outputs.
+    @code
+        uint32_t gpio_outputs;
+        gpio_outputs = MSS_GPIO_get_outputs();
+        gpio_outputs &= ~( MSS_GPIO_2_MASK | MSS_GPIO_4_MASK );
+        MSS_GPIO_set_outputs(  gpio_outputs );
+    @endcode
+
+  @see MSS_GPIO_get_outputs()
+ */
+static __INLINE void
+MSS_GPIO_set_outputs
+(
+   uint32_t value
+)
+{
+    GPIO->GPIO_OUT = value;
+}
+
+/*-------------------------------------------------------------------------*//**
+  The MSS_GPIO_set_output() function is used to set the state of a single GPIO
+  port configured as an output.
+  Note: Using bit-band writes might be a better option than this function for
+        performance critical applications where the application code is not
+        intended to be ported to a processor other than the ARM Cortex-M3 in
+        SmartFusion2. The bit-band write equivalent to this function would be:
+            GPIO_BITBAND->GPIO_OUT[port_id] = (uint32_t)value;
+ 
+  @param port_id
+    The port_id parameter identifies the GPIO port that is to have its output
+    set. An enumeration item of the form MSS_GPIO_n, where n is the number of
+    the GPIO port, is used to identify the GPIO port. For example, MSS_GPIO_0
+    identifies the first GPIO port and MSS_GPIO_31 is the last one.
+  
+  @param value
+    The value parameter specifies the desired state for the GPIO output. A value
+    of 0 will set the output Low and a value of 1 will set the output High.
+  
+  @return
+    This function does not return a value.
+    
+  Example:
+  The following call will set GPIO output 12 High, leaving all other GPIO
+  outputs unaffected:
+  @code
+    _GPIO_set_output(MSS_GPIO_12, 1);
+  @endcode
+ */
+void MSS_GPIO_set_output
+(
+    mss_gpio_id_t       port_id,
+    uint8_t             value
+);
+
+/*-------------------------------------------------------------------------*//**
+  The MSS_GPIO_get_inputs() function is used to read the current state all GPIO
+  ports configured as inputs.
+ 
+  @return
+    This function returns a 32-bit unsigned integer where each bit represents
+    the state of a GPIO input. The least significant bit represents the state of
+    GPIO input 0 and the most significant bit the state of GPIO input 31.
+
+  Example:
+    Read and assign the current state of the GPIO outputs to a variable.
+    @code
+        uint32_t gpio_inputs;
+        gpio_inputs = MSS_GPIO_get_inputs();
+    @endcode
+ */
+static __INLINE uint32_t
+MSS_GPIO_get_inputs( void )
+{
+    return GPIO->GPIO_IN;
+}
+
+/*-------------------------------------------------------------------------*//**
+  The MSS_GPIO_get_outputs() function is used to read the current state all GPIO
+  ports configured as outputs.
+ 
+  @return
+     This function returns a 32-bit unsigned integer where each bit represents
+     the state of a GPIO output. The least significant bit represents the state
+     of GPIO output 0 and the most significant bit the state of GPIO output 31.
+
+  Example:
+    Read and assign the current state of the GPIO outputs to a variable.
+    @code
+        uint32_t gpio_outputs;
+        gpio_outputs = MSS_GPIO_get_outputs();
+    @endcode
+ */
+static __INLINE uint32_t
+MSS_GPIO_get_outputs( void )
+{
+    return GPIO->GPIO_OUT;
+}
+
+/*-------------------------------------------------------------------------*//**
+  The MSS_GPIO_drive_inout() function is used to set the output state of a
+  single GPIO port configured as an INOUT. An INOUT GPIO can be in one of three
+  states:
+    - High
+    - Low
+    - High impedance
+  An INOUT output would typically be used where several devices can drive the
+  state of a shared signal line. The High and Low states are equivalent to the
+  High and Low states of a GPIO configured as an output. The High impedance
+  state is used to prevent the GPIO from driving its output state onto the
+  signal line, while at the same time allowing the input state of the GPIO to
+  be read.
+  
+  @param port_id
+    The port_id parameter identifies the GPIO port for which you want to change
+    the output state. An enumeration item of the form MSS_GPIO_n, where n is the
+    number of the GPIO port, is used to identify the GPIO port. For example,
+    MSS_GPIO_0 identifies the first GPIO port and MSS_GPIO_31 is the last one.
+    
+  @param inout_state
+    The inout_state parameter specifies the state of the GPIO port identified by
+    the port_id parameter. Allowed values of type mss_gpio_inout_state_t are as
+    follows:
+        - MSS_GPIO_DRIVE_HIGH
+        - MSS_GPIO_DRIVE_LOW
+        - MSS_GPIO_HIGH_Z  (High impedance)
+        
+  @return
+    This function does not return a value.
+
+  Example:
+    The call to MSS_GPIO_drive_inout() below will set the GPIO 7 output to the
+    high impedance state.
+    @code
+    MSS_GPIO_drive_inout( MSS_GPIO_7, MSS_GPIO_HIGH_Z );
+    @endcode
+ */
+void MSS_GPIO_drive_inout
+(
+    mss_gpio_id_t           port_id,
+    mss_gpio_inout_state_t  inout_state
+);
+
+/*-------------------------------------------------------------------------*//**
+  The MSS_GPIO_enable_irq() function is used to enable interrupt generation for
+  the specified GPIO input. Interrupts are generated based on the state of the
+  GPIO input and the interrupt mode configured for it by MSS_GPIO_config().
+ 
+  @param port_id
+    The port_id parameter identifies the GPIO port for which you want to enable
+    interrupt generation. An enumeration item of the form MSS_GPIO_n, where n is
+    the number of the GPIO port, is used to identify the GPIO port. For example,
+    MSS_GPIO_0 identifies the first GPIO port and MSS_GPIO_31 is the last one.
+    
+  @return
+    This function does not return a value.
+
+  Example:
+    The call to MSS_GPIO_enable_irq() below will allow GPIO 8 to generate
+    interrupts.
+    @code
+    MSS_GPIO_enable_irq( MSS_GPIO_8 );
+    @endcode
+ */
+void MSS_GPIO_enable_irq
+(
+    mss_gpio_id_t port_id
+);
+
+/*-------------------------------------------------------------------------*//**
+  The MSS_GPIO_disable_irq() function is used to disable interrupt generation
+  for the specified GPIO input.
+ 
+  @param port_id
+    The port_id parameter identifies the GPIO port for which you want to disable
+    interrupt generation. An enumeration item of the form MSS_GPIO_n, where n is
+    the number of the GPIO port, is used to identify the GPIO port. For example,
+    MSS_GPIO_0 identifies the first GPIO port and MSS_GPIO_31 is the last one.
+ 
+  @return
+    This function does not return a value.
+
+  Example:
+    The call to MSS_GPIO_disable_irq() below will prevent GPIO 8 from generating
+    interrupts.
+    @code
+    MSS_GPIO_disable_irq( MSS_GPIO_8 );
+    @endcode
+ */
+void MSS_GPIO_disable_irq
+(
+    mss_gpio_id_t port_id
+);
+
+/*-------------------------------------------------------------------------*//**
+  The MSS_GPIO_clear_irq() function is used to clear a pending interrupt from
+  the specified GPIO input.
+  Note: The MSS_GPIO_clear_irq() function must be called as part of any GPIO
+        interrupt service routine (ISR) in order to prevent the same interrupt
+        event retriggering a call to the GPIO ISR.
+ 
+  @param port_id
+    The port_id parameter identifies the GPIO port for which you want to clear
+    the interrupt. An enumeration item of the form MSS_GPIO_n, where n is the
+    number of the GPIO port, is used to identify the GPIO port. For example,
+    MSS_GPIO_0 identifies the first GPIO port and MSS_GPIO_31 is the last one.
+    
+  @return
+    none.
+
+  Example:
+    The example below demonstrates the use of the MSS_GPIO_clear_irq() function
+    as part of the GPIO 9 interrupt service routine.  
+    @code
+    void GPIO9_IRQHandler( void )
+    {
+        do_interrupt_processing();
+        
+        MSS_GPIO_clear_irq( MSS_GPIO_9 );
+    }
+    @endcode
+ */
+void MSS_GPIO_clear_irq
+(
+    mss_gpio_id_t port_id
+);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* MSS_GPIO_H_ */
diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_hpdma/mss_hpdma.c b/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_hpdma/mss_hpdma.c
new file mode 100644
index 000000000..f43eadb4c
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_hpdma/mss_hpdma.c
@@ -0,0 +1,344 @@
+/*******************************************************************************
+ * (c) Copyright 2010-2013 Microsemi SoC Products Group.  All rights reserved.
+ * 
+ * SmartFusion2 MSS HPDMA bare metal driver implementation.
+ *
+ * SVN $Revision: 5148 $
+ * SVN $Date: 2013-02-27 16:42:01 +0000 (Wed, 27 Feb 2013) $
+ */
+#include "mss_hpdma.h"
+
+/*==============================================================================
+ * Design Notes
+ *------------------------------------------------------------------------------
+  This SmartFusion2 MSS HPDMA driver only makes use of the first HPDMA
+  descriptor. The rationale for this choice is that the pause and clear bits of
+  each individual descriptor have undocumented side effects to the other
+  descriptors in the HPDMA hardware block. This prevents independent operations
+  of the descriptors in particular when it comes to error handling where error
+  recovery requires clearing a descriptor. An error on one descriptor would
+  result in aborting transfers on the other descriptors. Likewise, it is not
+  possible to pause individual descriptors. Setting the pause bit in one
+  descriptor results in all descriptors being paused.
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif 
+
+/*-------------------------------------------------------------------------*//**
+ * Constants
+ */
+#define HPDMA_ENABLE    1u
+#define HPDMA_DISABLE   0u
+#define NULL_HANDLER    ((mss_hpdma_handler_t)0)
+
+/* 64 K DMA Transfer */
+#define MAX_SIZE_PER_DMA_XFR   0x10000u
+
+#define DESC0       0u
+
+/*-------------------------------------------------------------------------*//**
+ * Mask Constants
+ */
+#define HPDMA_SOFT_RESET            0x00020000u
+#define HPDMA_XFR_SIZE_MASK         0xFFFF0000u
+
+#define HPDMACR_XFR_CMP_INT_MASK    0x00100000u
+#define HPDMACR_XFR_ERR_INT_MASK    0x00200000u
+#define HPDMACR_NON_WORD_INT_MASK   0x00400000u
+
+#define HPDMACR_ALL_IRQ_ENABLE_MASK (HPDMACR_XFR_CMP_INT_MASK | HPDMACR_XFR_ERR_INT_MASK | HPDMACR_NON_WORD_INT_MASK)
+
+#define HPDMAICR_CLEAR_ALL_IRQ      0x000000FFu
+
+#define HPDMAEDR_DCP_ERR_MASK           0x00000100u
+
+#define HPDMAEDR_NON_WORD_ERR_MASK      0x00001000u
+
+/*-------------------------------------------------------------------------*//**
+  Current transfer state information.
+ */
+typedef struct hpdma_xfer_info
+{
+    hpdma_status_t          state;
+    mss_hpdma_handler_t     completion_handler;
+    uint32_t                src_addr;
+    uint32_t                des_addr;
+    uint32_t                xfr_size;
+    uint8_t                 xfr_dir;
+} hpdma_xfer_info_t;
+
+/*-------------------------------------------------------------------------*//**
+  Current transfer state information.
+ */
+static hpdma_xfer_info_t g_transfer;
+
+/*-------------------------------------------------------------------------*//**
+  Interrupt service routines function prototypes.
+  The name of these interrupt service routines must match the name of the ISRs
+  defined in startup_m2sxxx.s distributed as part of the SmartFusion2 CMSIS.
+ */
+#if defined(__GNUC__)
+__attribute__((__interrupt__)) void HPDMA_Complete_IRQHandler(void);
+#else
+void HPDMA_Complete_IRQHandler(void);
+#endif 
+
+#if defined(__GNUC__)
+__attribute__((__interrupt__)) void HPDMA_Error_IRQHandler(void);
+#else
+void HPDMA_Error_IRQHandler(void);
+#endif 
+
+/*-------------------------------------------------------------------------*//**
+ * See "mss_hpdma.h" for details of how to use this function.
+ */
+void
+MSS_HPDMA_init
+(
+    void
+)
+{
+    /* Reset HPDMA block. */
+    SYSREG->SOFT_RST_CR |= HPDMA_SOFT_RESET;
+
+    /* Take HPDMA controller out of reset. */
+    SYSREG->SOFT_RST_CR &= ~HPDMA_SOFT_RESET;
+
+    /* Initialize data structures. */
+    g_transfer.xfr_size = 0u;
+    g_transfer.completion_handler = NULL_HANDLER;
+    g_transfer.state = HPDMA_COMPLETED;
+    
+    /* Disable Interrupt. */
+    HPDMA->Descriptor[DESC0].HPDMACR_REG &= ~HPDMACR_ALL_IRQ_ENABLE_MASK;
+
+    /* Clear any previously pended MSS HPDMA interrupt. */
+    NVIC_ClearPendingIRQ(HPDMA_Error_IRQn);
+    NVIC_ClearPendingIRQ(HPDMA_Complete_IRQn);
+    
+    /* Clear all interrupts. */
+    HPDMA->HPDMAICR_REG = HPDMAICR_CLEAR_ALL_IRQ;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * See "mss_hpdma.h" for details of how to use this function.
+ */
+void
+MSS_HPDMA_start
+(
+    uint32_t src_addr,
+    uint32_t dest_addr,
+    uint32_t transfer_size,
+    uint8_t transfer_dir
+)
+{
+    /* Pause transfer. */
+    HPDMA_BITBAND->Descriptor[DESC0].HPDMACR_DCP_PAUSE = HPDMA_ENABLE;
+    
+    /*
+     * Disable all interrupts for the current descriptor. Treat this function as a
+     * critical section. Pausing the descriptor transfer is not sufficient in case
+     * of non-aligned errors.
+     */
+    HPDMA->Descriptor[DESC0].HPDMACR_REG &= ~HPDMACR_ALL_IRQ_ENABLE_MASK;
+    
+    /* Set descriptor transfer direction */
+    HPDMA_BITBAND->Descriptor[DESC0].HPDMACR_DCP_XFR_DIR = transfer_dir;
+
+    /* Store Source and destination Address */
+    HPDMA->Descriptor[DESC0].HPDMASAR_REG = src_addr;
+    HPDMA->Descriptor[DESC0].HPDMADAR_REG = dest_addr;
+
+    /* Set the transfer size to 64K */
+    HPDMA->Descriptor[DESC0].HPDMACR_REG &= HPDMA_XFR_SIZE_MASK;
+
+    g_transfer.state = HPDMA_IN_PROGRESS;
+    if(transfer_size <= MAX_SIZE_PER_DMA_XFR)
+    {
+        /* Set descriptor transfer size */
+        HPDMA->Descriptor[DESC0].HPDMACR_REG |= (uint16_t)transfer_size;
+        g_transfer.xfr_size = 0u;
+    }
+    else
+    {
+        g_transfer.xfr_size = transfer_size - MAX_SIZE_PER_DMA_XFR;
+        g_transfer.des_addr = dest_addr + MAX_SIZE_PER_DMA_XFR;
+        g_transfer.src_addr = src_addr + MAX_SIZE_PER_DMA_XFR;
+        g_transfer.xfr_dir = transfer_dir;
+    }
+
+    /* Enable interrupts for the requested descriptor. */
+    HPDMA->Descriptor[DESC0].HPDMACR_REG |= HPDMACR_ALL_IRQ_ENABLE_MASK;
+    NVIC_EnableIRQ(HPDMA_Complete_IRQn);
+    NVIC_EnableIRQ(HPDMA_Error_IRQn);
+    
+    /* Set valid descriptor to start transfer */
+    HPDMA_BITBAND->Descriptor[DESC0].HPDMACR_DCP_VALID = HPDMA_ENABLE;
+
+    /* Start transfer */
+    HPDMA_BITBAND->Descriptor[DESC0].HPDMACR_DCP_PAUSE = HPDMA_DISABLE;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * See "mss_hpdma.h" for details of how to use this function.
+ */
+void
+MSS_HPDMA_pause
+(
+    void
+)
+{
+    /* Pause transfer */
+    HPDMA_BITBAND->Descriptor[DESC0].HPDMACR_DCP_PAUSE = HPDMA_ENABLE;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * See "mss_hpdma.h" for details of how to use this function.
+ */
+void
+MSS_HPDMA_resume
+(
+    void
+)
+{
+    /* Resume transfer */
+    HPDMA_BITBAND->Descriptor[DESC0].HPDMACR_DCP_PAUSE = HPDMA_DISABLE;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * See "mss_hpdma.h" for details of how to use this function.
+ */
+void
+MSS_HPDMA_abort
+(
+    void
+)
+{
+    HPDMA_BITBAND->Descriptor[DESC0].HPDMACR_DCP_CLR = HPDMA_ENABLE;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * See "mss_hpdma.h" for details of how to use this function.
+ */
+hpdma_status_t
+MSS_HPDMA_get_transfer_status
+(
+    void
+)
+{
+    return g_transfer.state;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * See "mss_hpdma.h" for details of how to use this function.
+ */
+void MSS_HPDMA_set_handler
+(
+    mss_hpdma_handler_t handler
+)
+{
+    if(handler == NULL_HANDLER)
+    {
+        g_transfer.completion_handler = NULL_HANDLER;
+    }
+    else
+    {
+        g_transfer.completion_handler = handler;
+    }
+}
+
+/*------------------------------------------------------------------------------
+  HPDMA Transfer complete service routine.
+  This function will be called as a result of any descriptor transfer
+  is completed by HPDMA controller .
+ */
+#if defined(__GNUC__)
+__attribute__((__interrupt__)) void HPDMA_Complete_IRQHandler(void)
+#else
+void HPDMA_Complete_IRQHandler(void)
+#endif 
+{
+    /* Clear interrupt */
+    HPDMA_BITBAND->HPDMAICR_CLR_XFR_INT[DESC0] = HPDMA_ENABLE;
+
+    if(g_transfer.xfr_size > 0u)
+    {
+        MSS_HPDMA_start(g_transfer.src_addr,
+                        g_transfer.des_addr,
+                        g_transfer.xfr_size,
+                        g_transfer.xfr_dir);
+    }
+    else
+    {
+        g_transfer.state = HPDMA_COMPLETED;
+        if(g_transfer.completion_handler != NULL_HANDLER)
+        {
+            (*(g_transfer.completion_handler))(HPDMA_COMPLETED);
+        }
+    }
+}
+
+/*------------------------------------------------------------------------------
+  HPDMA Transfer Error service routine.
+  This function will be called as a result of any descriptor transfer
+  has an error condition or it there is non word transfer size error.
+ */
+#if defined(__GNUC__)
+__attribute__((__interrupt__)) void HPDMA_Error_IRQHandler(void)
+#else
+void HPDMA_Error_IRQHandler(void)
+#endif 
+{
+    uint32_t error_bits;
+
+    /*
+     * Handle source/destination errors.
+     */
+    error_bits = HPDMA->HPDMAEDR_REG & HPDMAEDR_DCP_ERR_MASK;
+    if(error_bits != 0u)
+    {
+        if(g_transfer.completion_handler != NULL_HANDLER)
+        {
+            if(HPDMA_BITBAND->Descriptor[DESC0].HPDMASR_DCP_SERR)
+            {
+                g_transfer.state = HPDMA_SOURCE_ERROR;
+                (*(g_transfer.completion_handler))(HPDMA_SOURCE_ERROR);
+            }
+            
+            if(HPDMA_BITBAND->Descriptor[DESC0].HPDMASR_DCP_DERR)
+            {
+                g_transfer.state = HPDMA_DESTINATION_ERROR;
+                (*(g_transfer.completion_handler))(HPDMA_DESTINATION_ERROR);
+            }
+        }
+        /* Abort transfer. */
+        HPDMA_BITBAND->Descriptor[DESC0].HPDMACR_DCP_CLR = HPDMA_ENABLE;
+        /* Clear interrupt. */
+        HPDMA_BITBAND->HPDMAICR_CLR_XFR_INT[DESC0] = HPDMA_ENABLE;
+    }
+    
+    /*
+     * Handle non word aligned errors.
+     */
+    error_bits = HPDMA->HPDMAEDR_REG & HPDMAEDR_NON_WORD_ERR_MASK;
+    if(error_bits != 0u)
+    {
+        g_transfer.state = HPDMA_WORD_ALIGN_ERROR;
+        /* Call handler. */
+        if(g_transfer.completion_handler != NULL_HANDLER)
+        {
+            (*(g_transfer.completion_handler))(HPDMA_WORD_ALIGN_ERROR);
+        }
+        /* Abort transfer. */
+        HPDMA_BITBAND->Descriptor[DESC0].HPDMACR_DCP_CLR = HPDMA_ENABLE;
+        /* Clear interrupt. */
+        HPDMA_BITBAND->HPDMAICR_NON_WORD_INT[DESC0] = HPDMA_ENABLE;
+    }
+}
+
+#ifdef __cplusplus
+}
+#endif
+
diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_hpdma/mss_hpdma.h b/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_hpdma/mss_hpdma.h
new file mode 100644
index 000000000..636bc4439
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_hpdma/mss_hpdma.h
@@ -0,0 +1,361 @@
+/*******************************************************************************
+ * (c) Copyright 2010-2013 Microsemi SoC Products Group.  All rights reserved.
+ * 
+ *  SmartFusion2 MSS HPDMA bare metal software driver public API.
+ *
+ * SVN $Revision: 5583 $
+ * SVN $Date: 2013-04-04 12:29:18 +0100 (Thu, 04 Apr 2013) $
+ */
+
+/*=========================================================================*//**
+  @mainpage SmartFusion2 MSS HPDMA Bare Metal Driver.
+
+  @section intro_sec Introduction
+  The SmartFusion2 Microcontroller Subsystem (MSS) includes a High Performance
+  Direct Memory Access (HPDMA) controller which performs fast data transfer
+  between any MSS memory connected to the AHB bus matrix and MSS DDR-Bridge
+  memory. This software driver provides a set of functions for controlling the
+  MSS HPDMA as part of a bare metal system where no operating system is
+  available. The driver can be adapted for use as part of an operating system
+  but the implementation of the adaptation layer between the driver and the
+  operating system's driver model is outside the scope of the driver.
+  
+  @section hw_dependencies Hardware Flow Dependencies
+  The configuration of all features of the MSS HPDMA is covered by this driver.
+  There are no dependencies on the hardware flow when configuring the MSS HPDMA.
+  The base address, register addresses and interrupt number assignment for the
+  MSS HPDMA blocks are defined as constants in the SmartFusion2 CMSIS HAL. You
+  must ensure that the latest SmartFusion2 CMSIS HAL is included in the project
+  settings of the software tool chain used to build your project and that it is
+  generated into your project.
+  
+  @section theory_op Theory of Operation
+  The MSS HPDMA driver functions are grouped into the following categories:
+    - Initialization of the MSS HPDMA driver and hardware
+    - Data transfer control 
+    - Data transfer status
+    - Interrupt handling
+    
+  Initialization
+  The MSS HPDMA driver is initialized through a call to the MSS_HPDMA_init()
+  function. The MSS_HPDMA_init() function must be called before any other MSS
+  HPDMA driver functions can be called.
+  
+  Data Transfer Control
+  The driver provides the following functions to control HPDMA data transfers:
+    - MSS_HPDMA_start()  � This function starts a HPDMA data transfer. You must
+                           provide the source and destination addresses along
+                           with transfer size and transfer direction.
+    - MSS_HPDMA_pause()  � This function pauses the HPDMA transfer that is
+                           currently in progress.
+    - MSS_HPDMA_resume() � This function resumes a HPDMA transfer that was
+                           previously paused.
+    - MSS_HPDMA_abort()  � This function aborts the HPDMA transfer that is
+                           currently in progress.
+    
+  Data Transfer Status
+  The status of the HPDMA transfer initiated by the last call to
+  MSS_HPDMA_start() can be retrieved using the MSS_HPDMA_get_transfer_status()
+  function.
+  
+  Interrupt Handling
+  The MSS_HPDMA_set_handler() function is used to register a handler function
+  that will be called by the driver when the HPDMA transfer completes. You must
+  create and register a transfer completion handler function to suit your
+  application.
+
+ *//*=========================================================================*/
+#ifndef MSS_HPDMA_H_
+#define MSS_HPDMA_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif 
+
+#include "../../CMSIS/m2sxxx.h"
+
+/*-------------------------------------------------------------------------*//**
+  The HPDMA_TO_DDR constant is used to specify the data transfer direction. It
+  indicates a transfer from memory connected to the AHB bus matrix to MSS
+  DDR-Bridge memory. It is used as a parameter by the MSS_HPDMA_start()
+  function.
+ */
+#define HPDMA_TO_DDR        0u
+
+/*-------------------------------------------------------------------------*//**
+  The HPDMA_FROM_DDR constant is used to specify the data transfer direction. It
+  indicates a transter from MSS DDR-Bridge memory to memory connected to the AHB
+  bus matrix. It is used as a parameter by the MSS_HPDMA_start() function.
+ */
+#define HPDMA_FROM_DDR      1u
+
+/*-------------------------------------------------------------------------*//**
+  The hpdma_status_t type is used to communicate the status of the HPDMA
+  transfer initiated by the most recent call to HPDMA_start(). It indicates if
+  a transfer is still currently in progress or the outcome of the latest
+  transfer. This type is returned by the MSS_HPDMA_get_transfer_status()
+  function and used as parameter to handler functions registered with the MSS
+  HPDMA driver by the application.
+  
+  - HPDMA_IN_PROGRESS       - A HPDMA transfer is taking place.
+  - HPDMA_COMPLETED         - The most recent HPDMA transfer initiated by a call
+                              to HPDMA_start() has completed successfully.
+  - HPDMA_SOURCE_ERROR      - The most recent HPDMA transfer failed because of a
+                              problem with the source address passed to
+                              HPDMA_start().
+  - HPDMA_DESTINATION_ERROR - The most recent HPDMA transfer failed because of a
+                              problem with the destination address passed to
+                              HPDMA_start().
+  - HPDMA_WORD_ALIGN_ERROR  - The most recent HPDMA transfer failed because the
+                              transfer size was not word aligned. This means
+                              that the transfer size passed to HPDMA_start() was
+                              not a multiple of four.
+ */
+typedef enum
+{
+    HPDMA_IN_PROGRESS,
+    HPDMA_COMPLETED,
+    HPDMA_SOURCE_ERROR,
+    HPDMA_DESTINATION_ERROR,
+    HPDMA_WORD_ALIGN_ERROR
+} hpdma_status_t;
+
+/*-------------------------------------------------------------------------*//**
+  This type definition specifies the prototype of a function that can be
+  registered with this driver as a HPDMA transfer completion handler function
+  through a call to MSS_HPDMA_set_handler(). The HPDMA transfer completion
+  handler will be called by the driver when a HPDMA transfer completes. The MSS
+  HPDMA driver passes the outcome of the transfer to the completion handler in
+  the form of a hpdma_status_t parameter indicating if the transfer was
+  successful or the type of error that occurred during the transfer.
+ */
+typedef void (*mss_hpdma_handler_t)(hpdma_status_t status);
+
+/*-------------------------------------------------------------------------*//**
+  The MSS_HPDMA_init() function initializes the MSS HPDMA driver. It resets the
+  HPDMA controller. It clears all pending HPDMA interrupts. It initializes
+  internal data structures used by the MSS HPDMA driver. It disables interrupts
+  related to HPDMA data transfers.
+
+  @param
+    This function has no parameters.
+
+  @return
+    This function does not return a value.
+ */
+void
+MSS_HPDMA_init
+(
+    void
+);
+
+/*-------------------------------------------------------------------------*//**
+  The MSS_HPDMA_start() function starts a HPDMA data transfer. Its parameters
+  specify the source and destination addresses of the transfer as well as its
+  size and direction. HPDMA data transfers always use DDR memory as the source
+  or destination of the transfer. The HPDMA controller transfers data in 32-bit
+  chunks located on 32-bit word aligned address boundaries.
+
+  @param src_addr
+    The parameter src_addr is the address of the data that will be transferred
+    by the HPDMA. This address must be 32-bit word aligned. The memory location
+    specified by this address must be located in DDR memory if the transfer_dir
+    parameter is set to HPDM_FROM_DDR.
+
+  @param dest_addr
+    The parameter dest_addr is the address of the location at which the data
+    will be transferred. This address must be 32-bit word aligned. The memory
+    location specified by this address must be located in DDR memory if the
+    transfer_dir parameter is set to HPDM_TO_DDR.
+
+  @param transfer_size
+    The parameter transfer_size specifies the size in bytes of the requested
+    transfer. The value of transfer_size must be a multiple of four.
+
+  @param transfer_dir
+     The parameter transfer_dir is used for specifying the data transfer
+     direction. Allowed values for transfer_dir are as follows:
+        - HPDMA_TO_DDR
+        - HPDMA_FROM_DDR
+
+  @return
+    This function does not return a value.
+ */
+void
+MSS_HPDMA_start
+(
+    uint32_t src_addr,
+    uint32_t dest_addr,
+    uint32_t transfer_size,
+    uint8_t transfer_dir
+);
+
+/*-------------------------------------------------------------------------*//**
+  The MSS_HPDMA_pause() function pauses the current HPDMA transfer. The HPDMA
+  transfer can be resumed later  by calling MSS_HPDMA_resume().
+
+  @param
+    This function has no parameters.
+    
+  @return
+    This function does not return a value.
+ */
+void
+MSS_HPDMA_pause
+(
+    void
+);
+
+/*-------------------------------------------------------------------------*//**
+  The MSS_HPDMA_pause() function resumes the current HPDMA transfer after it was
+  previously paused through a call to MSS_HPDMA_pause().
+
+  @param
+    This function has no parameters.
+    
+  @return
+    This function does not return a value.
+ */
+void
+MSS_HPDMA_resume
+(
+    void
+);
+
+/*-------------------------------------------------------------------------*//**
+  The MSS_HPDMA_abort() function aborts the current HPDMA transfer.
+
+  @param
+    This function has no parameters.
+    
+  @return
+    This function does not return a value.
+ */
+void
+MSS_HPDMA_abort
+(
+    void
+);
+
+/*-------------------------------------------------------------------------*//**
+ The MSS_HPDMA_get_transfer_status() function returns the status of the HPDMA
+ transfer initiated by a call to MSS_HPDMA_start(). 
+
+  @param
+    This function has no parameters.
+    
+  @return
+    The MSS_HPDMA_get_transfer_status() function returns the status of the HPDMA
+    transfer as a value of  type hpdma_status_t. The possible return values are:
+        - HPDMA_IN_PROGRESS
+        - HPDMA_COMPLETED
+        - HPDMA_SOURCE_ERROR
+        - HPDMA_DESTINATION_ERROR
+        - HPDMA_WORD_ALIGN_ERROR
+      
+  The example code below demonstrates the use of the
+  MSS_HPDMA_get_transfer_status() function to detect the completion of the
+  transfer of the content of eNVM into MDDR memory.
+  @code
+    void copy_envm_to_mddr(void)
+    {
+        MSS_HPDMA_start(ENVM_BASE_ADDR,
+                        MDDR_BASE_ADDR,
+                        ENVM_SIZE_BYTE,
+                        HPDMA_TO_DDR);
+        
+        do {
+            xfer_state = MSS_HPDMA_get_transfer_status();
+        } while(HPDMA_IN_PROGRESS == xfer_state);
+    }
+  @endcode
+ */
+hpdma_status_t
+MSS_HPDMA_get_transfer_status
+(
+    void
+);
+
+/*-------------------------------------------------------------------------*//**
+  The MSS_HPDMA_set_handler() function is used to register a handler function
+  that will be called by the driver when the HPDMA transfer completes. You must
+  create and register a transfer completion handler function to suit your
+  application. The MSS HPDMA driver passes the outcome of the transfer to the
+  completion handler in the form of a hpdma_status_t parameter indicating if the
+  transfer was successful or the type of error that occurred during the transfer
+  if the transfer failed.
+
+  @param handler
+    The handler parameter is a pointer to a handler function provided by your
+    application. This handler is of type mss_hpdma_handler_t. The handler
+    function must take one parameter of type hpdma_status_t and must not return
+    a value.
+
+  @return
+    This function does not return a value.
+    
+  This example code demonstrates the use of the MSS_HPDMA_set_handler()
+  function:
+  @code
+    void transfer_complete_handler(hpdma_status_t status);
+
+    volatile uint32_t g_xfer_in_progress = 0;
+
+    void demo_transfer(void)
+    {
+        MSS_HPDMA_init();
+        
+        MSS_HPDMA_set_handler(transfer_complete_handler);
+        
+        g_xfer_in_progress = 1;
+        MSS_HPDMA_start((uint32_t)0x20000000,
+                        (uint32_t)0x00000000,
+                        20,
+                        HPDMA_FROM_DDR);
+        
+        while(g_xfer_in_progress)
+        {
+            ;
+        }
+    }
+
+    void transfer_complete_handler(hpdma_status_t status)
+    {
+        g_xfer_in_progress = 0;
+        
+        switch(status)
+        {
+            case HPDMA_COMPLETED:
+                display("Transfer complete");
+            break;
+
+            case HPDMA_SOURCE_ERROR:
+                display("Transfer failed: source error");
+            break;
+
+            case HPDMA_DESTINATION_ERROR:
+                display("Transfer failed: destination error");
+            break;
+
+            case HPDMA_WORD_ALIGN_ERROR:
+                display("Transfer failed: word alignment error");
+            break;
+
+            default:
+                display("Unexpected status");
+            break;
+        }
+    }
+  @endcode
+ */
+void
+MSS_HPDMA_set_handler
+(
+    mss_hpdma_handler_t handler
+);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* MSS_HPDMA_H_ */
diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_nvm/mss_nvm.c b/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_nvm/mss_nvm.c
new file mode 100644
index 000000000..2ba657176
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_nvm/mss_nvm.c
@@ -0,0 +1,694 @@
+/*******************************************************************************
+ * (c) Copyright 2011-2013 Microsemi SoC Products Group.  All rights reserved.
+ *
+ * This source file contains SmartFusion2 eNVM driver code.
+ *
+ * SVN $Revision: 5316 $
+ * SVN $Date: 2013-03-24 12:33:15 +0000 (Sun, 24 Mar 2013) $
+ */
+
+#include "../../CMSIS/m2sxxx.h"
+#include "../../CMSIS/mss_assert.h"
+#include "../../CMSIS/system_m2sxxx.h"
+#include "mss_nvm.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**************************************************************************/
+/* Preprocessor definitions                                               */
+/**************************************************************************/
+/*     eNVM command codes       */
+#define PROG_ADS       0x08000000u  /* One shot program with data in WD */
+#define VERIFY_ADS     0x10000000u  /* One shot verification with data in WD */
+#define USER_UNLOCK    0x13000000u  /* User unlock */
+
+#define BITS_PER_PAGE  1024u                   /* Number of bits per page */
+#define BYTES_PER_PAGE (BITS_PER_PAGE / 8u)    /* Number of bytes per page */
+
+#define NVM_OFFSET_SIGNIFICANT_BITS     0x0007FFFFu
+#define NVM1_BOTTOM_OFFSET              0x00040000u
+#define NVM1_TOP_OFFSET                 0x0007FFFFu
+
+#define NVM_BASE_ADDRESS                0x60000000u
+
+#define PAGE_ADDR_MASK                  0xFFFFFF80u
+
+#define BLOCK1_FIRST_WORD_OFFSET        0x00010000u
+
+#define WD_WORD_SIZE        32u
+
+#define NB_OF_BYTES_IN_A_WORD           4u
+
+#define WRITE_ERROR_MASK    (MSS_NVM_VERIFY_FAIL | \
+                             MSS_NVM_EVERIFY_FAIL | \
+                             MSS_NVM_WVERIFY_FAIL | \
+                             MSS_NVM_PEFAIL_LOCK | \
+                             MSS_NVM_WRCNT_OVER | \
+                             MSS_NVM_WR_DENIED)
+
+/*******************************************************************************
+ * Combined status definitions
+ * Below definitions should be used to decoded the bit encoded status returned 
+ * by the function MSS_NVM_get_status().
+ */
+#define MSS_NVM_BUSY_B              (1u)        /* NVM is performing an internal operation */
+#define MSS_NVM_VERIFY_FAIL         ((uint32_t)1 << 1u)     /* NVM verify operation failed */
+#define MSS_NVM_EVERIFY_FAIL        ((uint32_t)1 << 2u)     /* NVM erase verify operation failed */
+#define MSS_NVM_WVERIFY_FAIL        ((uint32_t)1 << 3u)     /* NVM write verify operation failed */
+#define MSS_NVM_PEFAIL_LOCK         ((uint32_t)1 << 4u)     /* NVM program / erase operation failed due to page lock */
+#define MSS_NVM_WRCNT_OVER          ((uint32_t)1 << 5u)     /* NVM write count overflowed */
+#define MSS_NVM_WR_DENIED           ((uint32_t)1 << 18u)    /* NVM write is denied due to protection */
+
+/*******************************************************************************
+ * 
+ */
+#define NVM_BLOCK_0     0u
+#define NVM_BLOCK_1     1u
+
+/*******************************************************************************
+ * 
+ */
+#define MAX_512K_OFFSET     0x00080000u
+
+/**************************************************************************/
+/* Global data definitions                                                */
+/**************************************************************************/
+/**************************************************************************//**
+ * Look-up table for NVM blocks.
+ */
+static NVM_TypeDef * const g_nvm[] = 
+{
+    ENVM_1 ,
+    ENVM_2
+};
+
+static NVM32_TypeDef * const g_nvm32[] =
+{
+    (NVM32_TypeDef *)ENVM1_BASE ,
+    (NVM32_TypeDef *)ENVM2_BASE
+};
+
+/**************************************************************************/
+/* Private function declarations                                          */
+/**************************************************************************/
+static nvm_status_t request_nvm_access
+(
+    uint32_t nvm_block_id
+);
+
+static nvm_status_t get_ctrl_access
+(
+    uint32_t nvm_offset,
+    uint32_t  length
+);
+
+static void release_ctrl_access(void);
+
+static uint32_t get_remaining_page_length
+(
+    uint32_t offset,
+    uint32_t  length
+);
+
+static void fill_wd_buffer
+(
+    const uint8_t * p_data,
+    uint32_t  length,
+    uint32_t block,
+    uint32_t offset
+);
+
+static uint32_t 
+write_nvm
+(
+    uint32_t addr,
+    const uint8_t * pidata,
+    uint32_t  length,
+    uint32_t  lock_page,
+    uint32_t * p_status
+);
+
+static uint32_t 
+wait_nvm_ready
+(
+    uint32_t block
+);
+
+static nvm_status_t get_error_code(uint32_t nvm_hw_status);
+
+/**************************************************************************/
+/* Public function definitions                                            */
+/**************************************************************************/
+
+/**************************************************************************//**
+ * See mss_nvm.h for details of how to use this function.
+ */
+nvm_status_t 
+NVM_write
+(
+    uint32_t start_addr,
+    const uint8_t * pidata,
+    uint32_t  length,
+    uint32_t  lock_page
+)
+{
+    nvm_status_t status;
+    uint32_t nvm_offset;
+    uint32_t device_version;
+    
+    /*
+     * Prevent pages being locked for silicon versions which do not allow
+     * locked pages to be unlocked.
+     */
+    device_version = SYSREG->DEVICE_VERSION;
+    if((0x0000F802u == device_version) || (0x0001F802u == device_version))
+    {
+        lock_page = NVM_DO_NOT_LOCK_PAGE;
+    }
+    
+    /* Ignore upper address bits to ignore remapping setting. */
+    nvm_offset = start_addr & NVM_OFFSET_SIGNIFICANT_BITS;  /* Ignore remapping. */
+    
+    /* Check against attempt to write data larger than eNVM. */
+    ASSERT((nvm_offset + length) < MAX_512K_OFFSET);
+    if((nvm_offset + length) < MAX_512K_OFFSET)
+    {
+        /* Gain exclusive access to eNVM controller */
+        status = get_ctrl_access(nvm_offset, length);
+
+        /* Write eNVM one page at a time. */
+        if(NVM_SUCCESS == status)
+        {
+            uint32_t remaining_length = length;
+            
+            while((remaining_length > 0u) && (NVM_SUCCESS == status))
+            {
+                uint32_t length_written;
+                uint32_t nvm_hw_status = 0u;
+                
+                length_written = write_nvm(start_addr + (length - remaining_length), 
+                                           &pidata[length - remaining_length],
+                                           remaining_length,
+                                           lock_page,
+                                           &nvm_hw_status);
+                
+                if(0u == length_written)
+                {
+                    status = get_error_code(nvm_hw_status);
+                }
+                else if(remaining_length > length_written)
+                {
+                    remaining_length -= length_written;
+                }
+                else
+                {
+                    remaining_length = 0u;
+                }
+            }
+            
+            /* Release eNVM controllers so that other masters can gain access to it. */
+            release_ctrl_access();
+        }
+    }
+    else
+    {
+        status = NVM_INVALID_PARAMETER;
+    }
+
+    return status;
+}
+
+/**************************************************************************//**
+  Generate error code based on NVM status value.
+  
+  The hardware nvm status passed as parameter is expected to be masked using the
+  following mask:
+                (MSS_NVM_VERIFY_FAIL | \
+                 MSS_NVM_EVERIFY_FAIL | \
+                 MSS_NVM_WVERIFY_FAIL | \
+                 MSS_NVM_PEFAIL_LOCK | \
+                 MSS_NVM_WRCNT_OVER | \
+                 MSS_NVM_WR_DENIED)
+  
+ */
+static nvm_status_t get_error_code(uint32_t nvm_hw_status)
+{
+    nvm_status_t status;
+    if(nvm_hw_status & MSS_NVM_WR_DENIED)
+    {
+        status = NVM_PROTECTION_ERROR;
+    }
+    else if(nvm_hw_status & MSS_NVM_WRCNT_OVER)
+    {
+        status = NVM_WRITE_THRESHOLD_ERROR;
+    }
+    else if(nvm_hw_status & MSS_NVM_PEFAIL_LOCK)
+    {
+        status = NVM_PAGE_LOCK_ERROR;
+    }
+    else
+    {
+        status = NVM_VERIFY_FAILURE;
+    }
+    
+    return status;
+}
+
+/**************************************************************************//**
+ * See mss_nvm.h for details of how to use this function.
+ */
+nvm_status_t
+NVM_unlock
+(
+    uint32_t start_addr,
+    uint32_t length
+)
+{
+    nvm_status_t status;
+    uint32_t nvm_offset;
+    uint32_t first_page;
+    uint32_t last_page;
+    uint32_t current_page;
+    uint32_t current_offset;
+    
+    /* Ignore upper address bits to ignore remapping setting. */
+    nvm_offset = start_addr & NVM_OFFSET_SIGNIFICANT_BITS;  /* Ignore remapping. */
+    
+    /* Check against attempt to write data larger than eNVM. */
+    ASSERT((nvm_offset + length) < MAX_512K_OFFSET);
+    if((nvm_offset + length) < MAX_512K_OFFSET)
+    {
+        current_offset = nvm_offset;
+        
+        first_page = nvm_offset / BYTES_PER_PAGE;
+        last_page = (nvm_offset + length) / BYTES_PER_PAGE;
+
+        /* Gain exclusive access to eNVM controller */
+        status = get_ctrl_access(nvm_offset, length);
+
+        /* Unlock eNVM one page at a time. */
+        if(NVM_SUCCESS == status)
+        {
+            uint32_t block;
+            uint32_t inc;
+            uint32_t first_word;
+            uint32_t word_offset;
+            uint32_t * p_nvm32;
+            uint32_t errors;
+            
+            p_nvm32 = (uint32_t *)NVM_BASE_ADDRESS;
+            
+            first_word = nvm_offset / 4u;
+            word_offset = first_word;
+            
+            for(current_page = first_page;
+                (current_page <= last_page) && (NVM_SUCCESS == status);
+                ++current_page)
+            {
+                uint32_t ctrl_status;
+            
+                if(word_offset >= BLOCK1_FIRST_WORD_OFFSET)
+                {
+                    block = NVM_BLOCK_1;
+                }
+                else
+                {
+                    block = NVM_BLOCK_0;
+                }
+                
+                for(inc = 0u; inc < WD_WORD_SIZE; ++inc)
+                {
+                    g_nvm32[block]->WD[inc] = p_nvm32[word_offset];
+                    ++word_offset;
+                }
+                
+                g_nvm[block]->PAGE_LOCK = NVM_DO_NOT_LOCK_PAGE;
+                g_nvm[block]->CMD = USER_UNLOCK;
+
+                /* Issue program command */
+                g_nvm[block]->CMD = PROG_ADS | (current_offset & PAGE_ADDR_MASK);
+                current_offset += BYTES_PER_PAGE;
+                
+                /* Wait for NVM to become ready. */
+                ctrl_status = wait_nvm_ready(block);
+
+                /* Check for errors. */
+                errors = ctrl_status & WRITE_ERROR_MASK;
+                if(errors)
+                {
+                    uint32_t nvm_hw_status;
+                    nvm_hw_status = g_nvm[block]->STATUS;
+                    status = get_error_code(nvm_hw_status);
+                }
+            }
+            
+            /* Release eNVM controllers so that other masters can gain access to it. */
+            release_ctrl_access();
+        }
+    }
+    else
+    {
+        status = NVM_INVALID_PARAMETER;
+    }
+    
+    return status;
+}
+
+/**************************************************************************/
+/* Private function definitions                                            */
+/**************************************************************************/
+
+/**************************************************************************//**
+ * 
+ */
+#define ACCESS_REQUEST_TIMEOUT      0x00800000u
+#define REQUEST_NVM_ACCESS          0x01u
+#define CORTEX_M3_ACCESS_GRANTED    0x05u
+
+static uint8_t g_envm_ctrl_locks = 0x00u;
+
+static nvm_status_t
+request_nvm_access
+(
+    uint32_t nvm_block_id
+)
+{
+    nvm_status_t status = NVM_SUCCESS;
+    volatile uint32_t timeout_counter;
+    uint32_t access;
+    
+    /*
+     * Use the SystemCoreClock frequency to compute a delay counter value giving
+     * us a delay in the 500ms range. This is a very approximate delay.
+     */
+    timeout_counter = SystemCoreClock / 16u;
+    
+    /*
+     * Gain access to eNVM controller.
+     */
+    do {
+        g_nvm[nvm_block_id]->REQ_ACCESS = REQUEST_NVM_ACCESS;
+        access = g_nvm[nvm_block_id]->REQ_ACCESS;
+        if(access != CORTEX_M3_ACCESS_GRANTED)
+        {
+            /*
+             * Time out if another AHB master locked access to eNVM to prevent
+             * the Cortex-M3 from locking up on eNVM write if some other part
+             * of the system fails from releasing the eNVM.
+             */
+            --timeout_counter;
+            if(0u == timeout_counter)
+            {
+                status = NVM_IN_USE_BY_OTHER_MASTER;
+            }
+        }
+    } while((access != CORTEX_M3_ACCESS_GRANTED) && (NVM_SUCCESS == status));
+    
+    /*
+     * Mark controller as locked if successful so that it will be unlocked by a
+     * call to release_ctrl_access.
+     */
+    if(NVM_SUCCESS == status)
+    {
+        g_envm_ctrl_locks |= (uint8_t)((uint32_t)0x01 << nvm_block_id);
+    }
+    
+    return status;
+}
+
+
+/**************************************************************************//**
+ * 
+ */
+static nvm_status_t
+get_ctrl_access
+(
+    uint32_t nvm_offset,
+    uint32_t  length
+)
+{
+    nvm_status_t access_req_status;
+    
+    /*
+     * Gain access to eNVM controller(s).
+     */
+    if(nvm_offset < NVM1_BOTTOM_OFFSET)
+    {
+        access_req_status = request_nvm_access(NVM_BLOCK_0);
+        if(NVM_SUCCESS == access_req_status)
+        {
+            uint32_t last_offset;
+            last_offset = nvm_offset + length;
+            if(last_offset >= NVM1_BOTTOM_OFFSET)
+            {
+                access_req_status = request_nvm_access(NVM_BLOCK_1);
+                if(NVM_IN_USE_BY_OTHER_MASTER == access_req_status)
+                {
+                    release_ctrl_access();
+                }
+            }
+        }
+    }
+    else
+    {
+        access_req_status = request_nvm_access(NVM_BLOCK_1);
+    }
+    
+    return access_req_status;
+}
+
+/**************************************************************************//**
+ * Release access to eNVM controllers.
+ */
+#define NVM_BLOCK_0_LOCK_MASK   0x01u
+#define NVM_BLOCK_1_LOCK_MASK   0x02u
+
+static void release_ctrl_access(void)
+{
+    uint8_t block_locked;
+    
+    block_locked = g_envm_ctrl_locks & NVM_BLOCK_0_LOCK_MASK;
+    if(block_locked)
+    {
+        g_nvm[NVM_BLOCK_0]->REQ_ACCESS = 0x00u;
+        g_envm_ctrl_locks &= ~NVM_BLOCK_0_LOCK_MASK;
+    }
+    
+    block_locked = g_envm_ctrl_locks & NVM_BLOCK_1_LOCK_MASK;
+    if(block_locked)
+    {
+        g_nvm[NVM_BLOCK_1]->REQ_ACCESS = 0x00u;
+        g_envm_ctrl_locks &= ~NVM_BLOCK_1_LOCK_MASK;
+    }
+}
+
+/**************************************************************************//**
+ * 
+ */
+static uint32_t wait_nvm_ready(uint32_t block) 
+{
+    volatile uint32_t ctrl_status;
+    uint32_t ctrl_ready;
+    uint32_t inc;
+    
+    /*
+     * Wait for NVM to become ready.
+     * We must ensure that we can read the ready bit set to 1 twice before we
+     * can assume that the other status bits are valid. See SmartFusion2 errata.
+     */
+    for(inc = 0u; inc < 2u; ++inc)
+    {
+        do {
+            ctrl_status = g_nvm[block]->STATUS;
+            ctrl_ready = ctrl_status  & MSS_NVM_BUSY_B;
+        } while(0u == ctrl_ready);
+    }
+    
+    return ctrl_status;
+}
+
+/**************************************************************************//**
+  Write as much data as will fit into the eNVM page corresponding to the
+  address "addr" passed as parameter. Return the number of bytes written into
+  the page.
+  In case of error, return the content of the eNVM controller status register
+  into the 32-bit word pointed to by p_status.
+ */
+static uint32_t 
+write_nvm
+(
+    uint32_t addr,
+    const uint8_t * pidata,
+    uint32_t  length,
+    uint32_t  lock_page,
+    uint32_t * p_status
+)
+{
+    uint32_t length_written;
+    uint32_t offset;
+    
+    *p_status = 0u;
+    
+    offset = addr & NVM_OFFSET_SIGNIFICANT_BITS;  /* Ignore remapping. */
+
+    ASSERT(offset <= NVM1_TOP_OFFSET);
+    
+    /* Adjust length to fit within one page. */
+    length_written = get_remaining_page_length(offset, length);
+    
+    if(offset <= NVM1_TOP_OFFSET)
+    {
+        uint32_t block;
+        volatile uint32_t ctrl_status;
+        uint32_t errors;
+        
+        if(offset < NVM1_BOTTOM_OFFSET)
+        {
+            block = NVM_BLOCK_0;
+        }
+        else
+        {
+            block = NVM_BLOCK_1;
+            offset = offset - NVM1_BOTTOM_OFFSET;
+        }
+        
+        fill_wd_buffer(pidata, length_written, block, offset);
+
+        /* Set requested locking option. */
+        g_nvm[block]->PAGE_LOCK = lock_page;
+        
+        /* Issue program command */
+        g_nvm[block]->CMD = PROG_ADS | (offset & PAGE_ADDR_MASK);
+        
+        /* Wait for NVM to become ready. */
+        ctrl_status = wait_nvm_ready(block);
+
+        /* Check for errors. */
+        errors = ctrl_status & WRITE_ERROR_MASK;
+        if(errors)
+        {
+            /* Signal that an error occured by returning 0 a a number of bytes written. */
+            length_written = 0u;
+            *p_status = g_nvm[block]->STATUS;
+        }
+        else
+        {
+            /* Perform a verify. */
+            g_nvm[block]->CMD = VERIFY_ADS | (offset & PAGE_ADDR_MASK);
+            /* Wait for NVM to become ready. */
+            ctrl_status = wait_nvm_ready(block);
+
+            /* Check for errors. */
+            errors = ctrl_status & WRITE_ERROR_MASK;
+            if(errors)
+            {
+                /* Signal that an error occured by returning 0 a a number of bytes written. */
+                length_written = 0u;
+                *p_status = g_nvm[block]->STATUS;
+            }
+        }
+    }
+    
+    return length_written;
+}
+
+/*******************************************************************************
+  Return the number of bytes between the offset location and the end of the page
+  containing the first offset location. This tells us how many actual bytes can
+  be programmed with a single ProgramADS command.
+  This also tells us if we are programming a full page. If the return value is
+  equal to BYTES_PER_PAGE then we will be pragramming an entire NVM page.
+  Alternatively, this function returning a value other than BYTES_PER_PAGE
+  indicates that the WD[] buffer will have to be seeded with the existing
+  content of the eNVM before copying the data to program to eNVM into the WD[]
+  buffer.
+ */
+static uint32_t get_remaining_page_length
+(
+    uint32_t offset,
+    uint32_t  length
+)
+{
+    uint32_t start_page_plus_one;
+    uint32_t last_page;
+    
+    start_page_plus_one = (offset / BYTES_PER_PAGE) + 1u;
+    last_page = (offset + length) / BYTES_PER_PAGE;
+    if(last_page >= start_page_plus_one)
+    {
+        length = BYTES_PER_PAGE - (offset % BYTES_PER_PAGE);
+    }
+    
+    return length;
+}
+
+/**************************************************************************//**
+ * 
+ */
+static void fill_wd_buffer
+(
+    const uint8_t * p_data,
+    uint32_t  length,
+    uint32_t block,
+    uint32_t offset
+)
+{
+    uint32_t inc;
+    uint32_t wd_offset;
+    
+    if(length != BYTES_PER_PAGE)
+    {
+        uint32_t * p_nvm32;
+        uint32_t nb_non_written_words;
+        uint32_t first_non_written_word;
+        /* 
+         * Fill beginning of WD[] with current content of NVM page that must not
+         * be overwritten.
+         */
+        p_nvm32 = (uint32_t *)((NVM_BASE_ADDRESS + offset) & PAGE_ADDR_MASK);
+        nb_non_written_words = (offset % BYTES_PER_PAGE) / NB_OF_BYTES_IN_A_WORD;
+        if((offset % NB_OF_BYTES_IN_A_WORD) > 0u)
+        {
+            ++nb_non_written_words;
+        }
+        for(inc = 0u; (inc < WD_WORD_SIZE) && (inc < nb_non_written_words); ++inc)
+        {
+            g_nvm32[block]->WD[inc] = p_nvm32[inc];
+        }
+        
+        /*
+         * Fill end of WD[] with current content of NVM page that must not be
+         * overwritten.
+         */
+        first_non_written_word = ((offset + length) % BYTES_PER_PAGE) / NB_OF_BYTES_IN_A_WORD;
+        nb_non_written_words = (BYTES_PER_PAGE / NB_OF_BYTES_IN_A_WORD) - first_non_written_word;
+        
+        for(inc = 0u; inc < nb_non_written_words; ++inc)
+        {
+            g_nvm32[block]->WD[first_non_written_word + inc] = p_nvm32[first_non_written_word + inc];
+        }
+    }
+    
+    /*
+     * Fill WD[] with data requested to be written into NVM.
+     */
+    wd_offset = offset % BYTES_PER_PAGE;
+    for(inc = 0u; inc < length; ++inc)
+    {
+        g_nvm[block]->WD[wd_offset + inc] = p_data[inc];
+    }
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+/******************************** END OF FILE ******************************/
+
+
+
+
+
+
diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_nvm/mss_nvm.h b/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_nvm/mss_nvm.h
new file mode 100644
index 000000000..d9812aa12
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_nvm/mss_nvm.h
@@ -0,0 +1,249 @@
+/*******************************************************************************
+ * (c) Copyright 2011-2013 Microsemi SoC Products Group.  All rights reserved.
+ * 
+ * This file contains public APIs for SmartFusion2 eNVM software driver.
+ * 
+ * SVN $Revision: 5362 $
+ * SVN $Date: 2013-03-26 21:37:53 +0000 (Tue, 26 Mar 2013) $
+ */
+/*=========================================================================*//**
+  @mainpage SmartFusion2 MSS eNVM Bare Metal Driver.
+  
+  @section intro_sec Introduction
+  The SmartFusion2 microcontroller subsystem (MSS) includes up to two embedded
+  non-volatile memory (eNVM) blocks. Each of these eNVM blocks can be a maximum
+  size of 256kB. This software driver provides a set of functions for accessing
+  and controlling the MSS eNVM as part of a bare metal system where no operating
+  system is available. The driver can be adapted for use as part of an operating
+  system, but the implementation of the adaptation layer between the driver and
+  the operating system's driver model is outside the scope of the driver.
+  
+  The MSS eNVM driver provides support for the following features:
+    - eNVM write (program) operations.
+    - eNVM page unlocking
+  The MSS eNVM driver is provided as C source code.
+
+  
+  @section configuration Driver Configuration
+  The size of the MSS eNVM varies with different SmartFusion2 device types. You
+  must only use this driver to access memory locations within the valid MSS eNVM
+  address space for the targeted device. The size of the valid MSS eNVM address
+  space corresponds to the size of the MSS eNVM in the device. Some pages of the
+  MSS eNVM may be write protected by the SmartFusion2 MSS configurator as part
+  of the hardware design flow. The driver cannot unlock or write to these
+  protected pages.
+  The base address, register addresses and interrupt number assignment for the
+  MSS eNVM blocks are defined as constants in the SmartFusion2 CMSIS HAL. You
+  must ensure that the latest SmartFusion2 CMSIS HAL is included in the project
+  settings of the software tool chain used to build your project and that it is
+  generated into your project.
+
+  @section theory_op Theory of Operation
+  The total amount of eNVM available in a SmartFusion device ranges from 128kB
+  to 512kB, provided in one or two physical eNVM blocks. The eNVM blocks are
+  divided into pages, with each page holding 128 bytes of data. The MSS eNVM
+  driver treats the entire eNVM as a contiguous memory space. It provides write
+  access to all pages that are in the valid eNVM address range for the
+  SmartFusion device and that are not write-protected. The driver imposes no
+  restrictions on writing data across eNVM block or page boundaries. The driver
+  supports random access writes to the eNVM memory. 
+
+ *//*=========================================================================*/
+#ifndef __MSS_NVM_H
+#define __MSS_NVM_H
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/******************************************************************************/
+/* Public definitions                                                         */
+/******************************************************************************/
+/*******************************************************************************
+ * Page Locking constants:
+ */
+/*
+ * Indicates that the NVM_write() function should not lock the addressed pages
+ * after programming the data.
+ */
+#define NVM_DO_NOT_LOCK_PAGE    0u
+
+/*
+ * Indicates that the NVM_write() function should lock the addressed pages after
+ * programming the data.
+ */
+#define NVM_LOCK_PAGE           1u
+
+/*******************************************************************************
+  The nvm_status_t enumeration specifies the possible return values from the
+  NVM_write() and NVM_unlock() functions.
+  
+    NVM_SUCCESS:
+      Indicates that the programming was successful.
+        
+    NVM_PROTECTION_ERROR:
+      Indicates that the operation could not be completed because of a
+      protection error. This happens when attempting to program a page that was
+      set as protected in the hardware flow.
+      
+    NVM_VERIFY_FAILURE:
+      Indicates that one of the verify operations failed.
+      
+    NVM_PAGE_LOCK_ERROR:
+      Indicates that the operation could not complete because one of the pages
+      is locked. This may happen if the page was locked during a previous call
+      to NVM_write() or if the page was locked in the hardware design flow.
+      
+    NVM_WRITE_THRESHOLD_ERROR:
+      Indicates that the NVM maximum number of programming cycles has been
+      reached.
+      
+    NVM_IN_USE_BY_OTHER_MASTER:
+      Indicates that some other MSS AHB Bus Matrix master is accessing the NVM.
+      This could be due to the FPGA logic or the system controller programming
+      the NVM.
+      
+    NVM_INVALID_PARAMETER:
+      Indicates that one of more of the function parameters has an invalid
+      value. This is typically  returned when attempting to write or unlock more
+      eNVM than is available on  the device.
+ */
+typedef enum nvm_status
+{
+    NVM_SUCCESS = 0,
+    NVM_PROTECTION_ERROR,
+    NVM_VERIFY_FAILURE,
+    NVM_PAGE_LOCK_ERROR,
+    NVM_WRITE_THRESHOLD_ERROR,
+    NVM_IN_USE_BY_OTHER_MASTER,
+    NVM_INVALID_PARAMETER
+} nvm_status_t;
+
+/******************************************************************************/
+/* Public variables                                                           */
+/******************************************************************************/
+
+
+/******************************************************************************/
+/* Public function declarations                                               */
+/******************************************************************************/
+
+/***************************************************************************//**
+  The NVM_write() function is used to program (or write) data into the eNVM.
+  This function treats the two eNVM blocks contiguously, so a total of 512kB of
+  memory can be accessed linearly. The start address and end address of the
+  memory range to be programmed do not need to be page aligned. This function
+  supports programming of data that spans multiple pages. This function is a
+  blocking function.
+  Note: The NVM_write() function performs a verify operation on each page 
+        programmed to ensure the eNVM is programmed with the expected data.
+
+  @param start_addr
+    The start_addr parameter is the byte aligned start address in the eNVM
+    address space, to which the data is to be programmed.
+
+  @param pidata
+    The pidata parameter is the byte aligned start address of the input data.
+
+  @param length
+    The length parameter is the number of bytes of data to be programmed.
+
+  @param lock_page
+    The lock_page parameter specifies whether the pages that are programmed
+    must be locked or not once programmed. Locking the programmed pages prevents
+    them from being overwritten by mistake. Subsequent programming of these
+    pages will require the pages to be unlocked prior to calling NVM_write().
+    Allowed values for lock_page are:
+        - NVM_DO_NOT_LOCK_PAGE
+        - NVM_LOCK_PAGE
+        
+  @return
+    This function returns NVM_SUCCESS on successful execution. 
+    It returns one of the following error codes if the programming of the eNVM
+    fails:
+        - NVM_PROTECTION_ERROR
+        - NVM_VERIFY_FAILURE
+        - NVM_PAGE_LOCK_ERROR
+        - NVM_WRITE_THRESHOLD_ERROR
+        - NVM_IN_USE_BY_OTHER_MASTER
+        - NVM_INVALID_PARAMETER
+        
+  Example:
+  @code
+    uint8_t idata[815] = {"Z"};
+    status = NVM_write(0x0, idata, sizeof(idata), NVM_DO_NOT_LOCK_PAGE);
+  @endcode
+ */
+nvm_status_t 
+NVM_write
+(
+    uint32_t start_addr,
+    const uint8_t * pidata,
+    uint32_t  length,
+    uint32_t  lock_page
+);
+
+/***************************************************************************//**
+  The NVM_unlock() function is used to unlock the eNVM pages for a specified
+  range of eNVM addresses in preparation for writing data into the unlocked
+  locations. This function treats the two eNVM blocks contiguously, so a total
+  of 512kB of memory can be accessed linearly. The start address and end address
+  of the memory range to be unlocked do not need to be page aligned. This
+  function supports unlocking of an eNVM address range that spans multiple
+  pages. This function is a blocking function.
+
+  @param start_addr
+    The start_addr parameter is the byte aligned start address, in the eNVM
+    address space, of the memory range to be unlocked.
+    
+  @param length
+    The length parameter is the size in bytes of the memory range to be
+    unlocked.
+
+  @return
+    This function returns NVM_SUCCESS on successful execution. 
+    It returns one of the following error codes if the unlocking of the eNVM fails:
+        - NVM_PROTECTION_ERROR
+        - NVM_VERIFY_FAILURE
+        - NVM_PAGE_LOCK_ERROR
+        - NVM_WRITE_THRESHOLD_ERROR
+        - NVM_IN_USE_BY_OTHER_MASTER
+        - NVM_INVALID_PARAMETER
+        
+  The example code below demonstrates the intended use of the NVM_unlock()
+  function:
+  @code
+    int program_locked_nvm(uint32_t target_addr, uint32_t length)
+    {
+        nvm_status_t status;
+        int success = 0;
+        
+        status = NVM_unlock(target_addr, length);
+        if(NVM_SUCCESS == status)
+        {
+            status = NVM_write(target_addr, buffer, length, NVM_LOCK_PAGE);
+            if(NVM_SUCCESS == status)
+            {
+                success = 1; 
+            }
+        }
+        return success;
+    }
+  @endcode
+ */
+nvm_status_t
+NVM_unlock
+(
+    uint32_t start_addr,
+    uint32_t length
+);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MSS_NVM_H */
+
+
diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_rtc/mss_rtc.c b/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_rtc/mss_rtc.c
new file mode 100644
index 000000000..2af1f0eec
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_rtc/mss_rtc.c
@@ -0,0 +1,666 @@
+/*******************************************************************************
+ * (c) Copyright 2008-2013 Microsemi SoC Products Group.  All rights reserved.
+ * 
+ * SmartFusion2 MSS RTC bare metal driver implementation.
+ *
+ * SVN $Revision: 5090 $
+ * SVN $Date: 2013-02-18 12:13:31 +0000 (Mon, 18 Feb 2013) $
+ */
+#include "mss_rtc.h"
+#include "../../CMSIS/mss_assert.h"
+#include <string.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif 
+
+/*-------------------------------------------------------------------------*//**
+ * CONTROL_REG register masks.
+ */
+#define CONTROL_RUNNING_MASK        0x00000001u
+
+#define CONTROL_RTC_START_MASK      0x00000001u
+#define CONTROL_RTC_STOP_MASK       0x00000002u
+#define CONTROL_ALARM_ON_MASK       0x00000004u
+#define CONTROL_ALARM_OFF_MASK      0x00000008u
+#define CONTROL_RESET_MASK          0x00000010u
+#define CONTROL_UPLOAD_MASK         0x00000020u
+#define CONTROL_WAKEUP_CLR_MASK     0x00000100u
+#define CONTROL_UPDATED_MASK        0x00000400u
+
+/*-------------------------------------------------------------------------*//**
+ * MODE_REG register masks.
+ */
+#define MODE_CLK_MODE_MASK          0x00000001u
+#define MODE_WAKEUP_EN_MASK         0x00000002u
+#define MODE_WAKEUP_RESET_MASK      0x00000004u
+#define MODE_WAKEUP_CONTINUE_MASK   0x00000008u
+
+/*-------------------------------------------------------------------------*//**
+ * Other masks.
+ */
+#define MAX_BINARY_HIGHER_COUNT     0x7FFu
+#define MASK_32_BIT                 0xFFFFFFFFu
+#define MAX_PRESCALAR_COUNT         0x03FFFFFFu
+#define CALENDAR_SHIFT              8u
+
+#define COMPARE_ALL_BITS            0xFFFFFFFFu
+
+#define SYSREG_RTC_WAKEUP_M3_EN_MASK    0x00000001u
+
+/*-------------------------------------------------------------------------*//**
+ * Index into look-up table.
+ */
+#define SECONDS     0
+#define MINUTES     1
+#define HOURS       2
+#define DAYS        3
+#define MONTHS      4
+#define YEARS       5
+#define WEEKDAYS    6
+#define WEEKS       7
+
+/*-------------------------------------------------------------------------*//**
+  Local functions.
+ */
+static uint8_t
+get_clock_mode
+(
+    void
+);
+
+static void set_rtc_mode(uint8_t requested_mode);
+
+static void add_alarm_cfg_values
+(
+    uint8_t calendar_item,
+    uint32_t * p_calendar_value,
+    uint32_t * p_compare_mask
+    
+);
+
+/*-------------------------------------------------------------------------*//**
+ * See "mss_rtc.h" for details of how to use this function.
+ */
+void
+MSS_RTC_init
+(
+    uint8_t mode,
+    uint32_t prescaler
+)
+{
+    ASSERT(prescaler <= MAX_PRESCALAR_COUNT);
+
+    if(prescaler <= MAX_PRESCALAR_COUNT)
+    {
+        /* Stop the RTC. */
+        MSS_RTC_stop();
+        
+        /* Disable alarm. */
+        RTC->CONTROL_REG = CONTROL_ALARM_OFF_MASK;
+        
+        /* Disable Interrupt */
+        MSS_RTC_disable_irq();
+        NVIC_ClearPendingIRQ(RTC_Wakeup_IRQn);
+
+        /* Clear RTC wake up interrupt signal */
+        MSS_RTC_clear_irq();
+
+        /* Enable the RTC to interrupt the Cortex-M3. */
+        SYSREG->RTC_WAKEUP_CR |= SYSREG_RTC_WAKEUP_M3_EN_MASK;
+        
+        /* Select mode of operation, including the wake configuration. */
+        if(MSS_RTC_CALENDAR_MODE == mode)
+        {
+            RTC->MODE_REG = MODE_CLK_MODE_MASK;
+        }
+        else
+        {
+            RTC->MODE_REG = 0u;
+        }
+        
+        /* Reset the alarm and compare registers to a known value. */
+        RTC->ALARM_LOWER_REG = 0u;
+        RTC->ALARM_UPPER_REG = 0u;
+        RTC->COMPARE_LOWER_REG = 0u;
+        RTC->COMPARE_UPPER_REG = 0u;
+
+        /* Reset the calendar counters */
+        MSS_RTC_reset_counter();
+
+        /* Set new Prescaler value */
+        RTC->PRESCALER_REG = prescaler;
+    }
+}
+
+/*-------------------------------------------------------------------------*//**
+  See "mss_rtc.h" for details of how to use this function.
+ */
+void
+MSS_RTC_set_calendar_count
+(
+    const mss_rtc_calendar_t *new_rtc_value
+)
+{
+    uint8_t error = 0u;
+    uint8_t clock_mode;
+    
+    const uint8_t g_rtc_max_count_lut[] =
+    {
+       /* Calendar mode */
+        59u,    /* Seconds */
+        59u,    /* Minutes */
+        23u,    /* Hours   */
+        31u,    /* Days    */
+        12u,    /* Months  */
+        254u,   /* Years   */
+        7u,     /* Weekdays*/
+        52u     /* Week    */
+    };
+
+    const uint8_t g_rtc_min_count_lut[] =
+    {
+       /* Calendar mode */
+        0u, /* Seconds */
+        0u, /* Minutes */
+        0u, /* Hours   */
+        1u, /* Days    */
+        1u, /* Months  */
+        0u, /* Years   */
+        1u, /* Weekdays*/
+        1u  /* Week    */
+    };
+    
+    /* Assert if the values cross the limit */
+    ASSERT(new_rtc_value->second >= g_rtc_min_count_lut[SECONDS]);
+    ASSERT(new_rtc_value->second <= g_rtc_max_count_lut[SECONDS]);
+    ASSERT(new_rtc_value->minute >= g_rtc_min_count_lut[MINUTES]);
+    ASSERT(new_rtc_value->minute <= g_rtc_max_count_lut[MINUTES]);
+    ASSERT(new_rtc_value->hour >= g_rtc_min_count_lut[HOURS]);
+    ASSERT(new_rtc_value->hour <= g_rtc_max_count_lut[HOURS]);
+    ASSERT(new_rtc_value->day >= g_rtc_min_count_lut[DAYS]);
+    ASSERT(new_rtc_value->day <= g_rtc_max_count_lut[DAYS]);
+    ASSERT(new_rtc_value->month >= g_rtc_min_count_lut[MONTHS]);
+    ASSERT(new_rtc_value->month <= g_rtc_max_count_lut[MONTHS]);
+    ASSERT(new_rtc_value->year >= g_rtc_min_count_lut[YEARS]);
+    ASSERT(new_rtc_value->year <= g_rtc_max_count_lut[YEARS]);
+    ASSERT(new_rtc_value->weekday >= g_rtc_min_count_lut[WEEKDAYS]);
+    ASSERT(new_rtc_value->weekday <= g_rtc_max_count_lut[WEEKDAYS]);
+    ASSERT(new_rtc_value->week >= g_rtc_min_count_lut[WEEKS]);
+    ASSERT(new_rtc_value->week <= g_rtc_max_count_lut[WEEKS]);
+
+    if(new_rtc_value->second < g_rtc_min_count_lut[SECONDS]) {error = 1u;}
+    if(new_rtc_value->second > g_rtc_max_count_lut[SECONDS]) {error = 1u;}
+    if(new_rtc_value->minute < g_rtc_min_count_lut[MINUTES]) {error = 1u;}
+    if(new_rtc_value->minute > g_rtc_max_count_lut[MINUTES]) {error = 1u;}
+    if(new_rtc_value->hour < g_rtc_min_count_lut[HOURS]) {error = 1u;}
+    if(new_rtc_value->hour > g_rtc_max_count_lut[HOURS]) {error = 1u;}
+    if(new_rtc_value->day < g_rtc_min_count_lut[DAYS]) {error = 1u;}
+    if(new_rtc_value->day > g_rtc_max_count_lut[DAYS]) {error = 1u;}
+    if(new_rtc_value->month < g_rtc_min_count_lut[MONTHS]) {error = 1u;}
+    if(new_rtc_value->month > g_rtc_max_count_lut[MONTHS]) {error = 1u;}
+    if(new_rtc_value->year < g_rtc_min_count_lut[YEARS]) {error = 1u;}
+    if(new_rtc_value->year > g_rtc_max_count_lut[YEARS]) {error = 1u;}
+    if(new_rtc_value->weekday < g_rtc_min_count_lut[WEEKDAYS]) {error = 1u;}
+    if(new_rtc_value->weekday > g_rtc_max_count_lut[WEEKDAYS]) {error = 1u;}
+    if(new_rtc_value->week < g_rtc_min_count_lut[WEEKS]) {error = 1u;}
+    if(new_rtc_value->week > g_rtc_max_count_lut[WEEKS]) {error = 1u;}
+
+    /* 
+     * This function can only be used when the RTC is configured to operate in
+     * calendar counter mode. 
+     */
+    clock_mode = get_clock_mode();
+    ASSERT(MSS_RTC_CALENDAR_MODE == clock_mode);
+    
+    if((0u == error) && (MSS_RTC_CALENDAR_MODE == clock_mode))
+    {
+        uint32_t upload_in_progress;
+        
+        /*
+         * Write the RTC new value. 
+         */
+        RTC->SECONDS_REG = new_rtc_value->second;
+        RTC->MINUTES_REG = new_rtc_value->minute;
+        RTC->HOURS_REG = new_rtc_value->hour;
+        RTC->DAY_REG = new_rtc_value->day;
+        RTC->MONTH_REG = new_rtc_value->month;
+        RTC->YEAR_REG = new_rtc_value->year;
+        RTC->WEEKDAY_REG = new_rtc_value->weekday;
+        RTC->WEEK_REG = new_rtc_value->week;
+
+        /* Data is copied, now issue upload command */
+        RTC->CONTROL_REG = CONTROL_UPLOAD_MASK ;
+        
+        /* Wait for the upload to complete. */
+        do {
+            upload_in_progress = RTC->CONTROL_REG & CONTROL_UPLOAD_MASK;
+        } while(upload_in_progress);
+    }
+}
+
+/*-------------------------------------------------------------------------*//**
+ * See "mss_rtc.h" for details of how to use this function.
+ */
+void
+MSS_RTC_set_binary_count
+(
+    uint64_t new_rtc_value
+)
+{
+    uint8_t clock_mode;
+
+    /* 
+     * This function can only be used when the RTC is configured to operate in
+     * binary counter mode. 
+     */
+    clock_mode = get_clock_mode();
+    ASSERT(MSS_RTC_BINARY_MODE == clock_mode);
+    
+    if(MSS_RTC_BINARY_MODE == clock_mode)
+    {
+        uint32_t rtc_upper_32_bit_value;
+        
+        rtc_upper_32_bit_value = (uint32_t)(new_rtc_value >> 32u) & MASK_32_BIT;
+
+        /* Assert if the values cross the limit */
+        ASSERT(rtc_upper_32_bit_value <= MAX_BINARY_HIGHER_COUNT);
+
+        if(rtc_upper_32_bit_value <= MAX_BINARY_HIGHER_COUNT)
+        {
+            uint32_t upload_in_progress;
+            
+            /*
+             * Write the RTC new value. 
+             */
+            RTC->DATE_TIME_LOWER_REG = (uint32_t)new_rtc_value;
+            RTC->DATE_TIME_UPPER_REG =
+                    (uint32_t)(( new_rtc_value >> 32u) & MAX_BINARY_HIGHER_COUNT);
+
+            /* Data is copied, now issue upload command */
+            RTC->CONTROL_REG = CONTROL_UPLOAD_MASK;
+            
+            /* Wait for the upload to complete. */
+            do {
+                upload_in_progress = RTC->CONTROL_REG & CONTROL_UPLOAD_MASK;
+            } while(upload_in_progress);
+        }
+    }
+}
+
+/*-------------------------------------------------------------------------*//**
+ * See "mss_rtc.h" for details of how to use this function.
+ */
+void
+MSS_RTC_get_calendar_count
+(
+    mss_rtc_calendar_t *p_rtc_calendar
+)
+{
+    uint8_t clock_mode;
+    /* 
+     * This function can only be used when the RTC is configured to operate in
+     * calendar counter mode. 
+     */
+    clock_mode = get_clock_mode();
+    ASSERT(MSS_RTC_CALENDAR_MODE == clock_mode);
+    
+    if(MSS_RTC_CALENDAR_MODE == clock_mode)
+    {
+        p_rtc_calendar->second = (uint8_t)RTC->SECONDS_REG;
+        p_rtc_calendar->minute = (uint8_t)RTC->MINUTES_REG;
+        p_rtc_calendar->hour = (uint8_t)RTC->HOURS_REG;
+        p_rtc_calendar->day = (uint8_t)RTC->DAY_REG;
+        p_rtc_calendar->month = (uint8_t)RTC->MONTH_REG;
+        p_rtc_calendar->year = (uint8_t)RTC->YEAR_REG;
+        p_rtc_calendar->weekday = (uint8_t)RTC->WEEKDAY_REG;
+        p_rtc_calendar->week = (uint8_t)RTC->WEEK_REG;
+    }
+    else
+    {
+        /*
+         * Set returned calendar count to zero if the RTC is not configured for
+         * calendar counter mode. This should make incorrect release application
+         * code behave consistently and help application debugging.
+         */
+        memset(p_rtc_calendar, 0, sizeof(mss_rtc_calendar_t));
+    }
+}
+
+/*-------------------------------------------------------------------------*//**
+ * See "mss_rtc.h" for details of how to use this function.
+ */
+uint64_t
+MSS_RTC_get_binary_count
+(
+    void
+)
+{
+    uint64_t rtc_count;
+    uint8_t clock_mode;
+
+    /* 
+     * This function can only be used when the RTC is configured to operate in
+     * binary counter mode. 
+     */
+    clock_mode = get_clock_mode();
+    ASSERT(MSS_RTC_BINARY_MODE == clock_mode);
+    
+    if(MSS_RTC_BINARY_MODE == clock_mode)
+    {
+        rtc_count = RTC->DATE_TIME_LOWER_REG;
+        rtc_count = rtc_count | ((uint64_t)RTC->DATE_TIME_UPPER_REG << 32u) ;
+    }
+    else
+    {
+        /*
+         * Set returned binary count to zero if the RTC is not configured for
+         * binary counter mode. This should make incorrect release application
+         * code behave consistently and help application debugging.
+         */
+        rtc_count = 0u;
+    }
+
+    return rtc_count;
+}
+
+/*-------------------------------------------------------------------------*//**
+ *
+ */
+static void add_alarm_cfg_values
+(
+    uint8_t calendar_item,
+    uint32_t * p_calendar_value,
+    uint32_t * p_compare_mask
+    
+)
+{
+    if(MSS_RTC_CALENDAR_DONT_CARE == calendar_item)
+    {
+        *p_calendar_value = (uint32_t)(*p_calendar_value << CALENDAR_SHIFT);
+        *p_compare_mask = (uint32_t)(*p_compare_mask << CALENDAR_SHIFT);
+    }
+    else
+    {
+        *p_calendar_value = (uint32_t)((*p_calendar_value << CALENDAR_SHIFT) | (uint32_t)calendar_item);
+        *p_compare_mask = (uint32_t)((*p_compare_mask << CALENDAR_SHIFT) | (uint32_t)0xFFu);
+    }
+}
+
+/*-------------------------------------------------------------------------*//**
+ * See "mss_rtc.h" for details of how to use this function.
+ */
+void MSS_RTC_set_calendar_count_alarm
+(
+    const mss_rtc_calendar_t * alarm_value
+)
+{
+    uint32_t calendar_value;
+    uint32_t compare_mask;
+    uint8_t mode;
+    
+    mode = (uint8_t)(RTC->MODE_REG & MODE_CLK_MODE_MASK);
+    /*
+     * This function can only be used with the RTC set to operate in calendar
+     * mode.
+     */
+    ASSERT(MSS_RTC_CALENDAR_MODE == mode);
+    if(MSS_RTC_CALENDAR_MODE == mode)
+    {
+        uint8_t required_mode_reg;
+        
+        /* Disable the alarm before updating*/
+        RTC->CONTROL_REG = CONTROL_ALARM_OFF_MASK;
+
+        /* Set alarm and compare lower registers. */
+        calendar_value = 0u;
+        compare_mask = 0u;
+        
+        add_alarm_cfg_values(alarm_value->day, &calendar_value, &compare_mask);
+        add_alarm_cfg_values(alarm_value->hour, &calendar_value, &compare_mask);
+        add_alarm_cfg_values(alarm_value->minute, &calendar_value, &compare_mask);
+        add_alarm_cfg_values(alarm_value->second, &calendar_value, &compare_mask);
+
+        RTC->ALARM_LOWER_REG = calendar_value;
+        RTC->COMPARE_LOWER_REG = compare_mask;
+
+        /* Set alarm and compare upper registers. */
+        calendar_value = 0u;
+        compare_mask = 0u;
+        
+        add_alarm_cfg_values(alarm_value->week, &calendar_value, &compare_mask);
+        add_alarm_cfg_values(alarm_value->weekday, &calendar_value, &compare_mask);
+        add_alarm_cfg_values(alarm_value->year, &calendar_value, &compare_mask);
+        add_alarm_cfg_values(alarm_value->month, &calendar_value, &compare_mask);
+
+        RTC->ALARM_UPPER_REG = calendar_value;
+        RTC->COMPARE_UPPER_REG = compare_mask;
+        
+        /* Configure the RTC to enable the alarm. */
+        required_mode_reg = mode | MODE_WAKEUP_EN_MASK | MODE_WAKEUP_CONTINUE_MASK;
+        set_rtc_mode(required_mode_reg);
+        
+        /* Enable the alarm */
+        RTC->CONTROL_REG = CONTROL_ALARM_ON_MASK ;
+    }
+}
+
+/*-------------------------------------------------------------------------*//**
+  We only write the RTC mode register if really required because the RTC needs
+  to be stopped for the mode register to be written. Stopping the RTC everytime
+  the wakeup alarm configuration is set might induce drift on the RTC time.
+  This function is intended to be used when setting alarms.
+ */
+static void set_rtc_mode(uint8_t requested_mode)
+{
+    if(RTC->MODE_REG != requested_mode)
+    {
+        uint32_t rtc_running;
+        rtc_running = RTC->CONTROL_REG & CONTROL_RUNNING_MASK;
+        if(rtc_running)
+        {
+            /* Stop the RTC in order to change the mode register content.*/
+            MSS_RTC_stop();
+            RTC->MODE_REG = requested_mode;
+            MSS_RTC_start();
+        }
+        else
+        {
+            RTC->MODE_REG = requested_mode;
+        }
+    }
+}
+
+/*-------------------------------------------------------------------------*//**
+ * See "mss_rtc.h" for details of how to use this function.
+ */
+void MSS_RTC_set_binary_count_alarm
+(
+    uint64_t alarm_value,
+    mss_rtc_alarm_type_t alarm_type
+)
+{
+    uint8_t mode;
+    
+    mode = (uint8_t)(RTC->MODE_REG & MODE_CLK_MODE_MASK);
+    /*
+     * This function can only be used with the RTC set to operate in binary
+     * counter mode.
+     */
+    ASSERT(MSS_RTC_BINARY_MODE == mode);
+    if(MSS_RTC_BINARY_MODE == mode)
+    {
+        uint8_t required_mode_reg;
+        
+        /* Disable the alarm before updating*/
+        RTC->CONTROL_REG = CONTROL_ALARM_OFF_MASK;
+
+        /* Set the alarm value. */
+        RTC->COMPARE_LOWER_REG = COMPARE_ALL_BITS;
+        RTC->COMPARE_UPPER_REG = COMPARE_ALL_BITS;
+        RTC->ALARM_LOWER_REG = (uint32_t)alarm_value;
+        RTC->ALARM_UPPER_REG = (uint32_t)(alarm_value >> 32u);
+
+        /*
+         * Configure the RTC to enable the alarm.
+         */
+        required_mode_reg = mode | MODE_WAKEUP_EN_MASK | MODE_WAKEUP_CONTINUE_MASK;
+        if(MSS_RTC_PERIODIC_ALARM == alarm_type)
+        {
+            /*
+             * The RTC binary counter will be fully reset when the alarm occurs.
+             * The counter will continue counting while the wake-up interrupt is
+             * active.
+             */
+            required_mode_reg |= MODE_WAKEUP_RESET_MASK;
+        }
+        set_rtc_mode(required_mode_reg);
+        
+        /* Enable the alarm */
+        RTC->CONTROL_REG = CONTROL_ALARM_ON_MASK;
+    }
+}
+
+/*-------------------------------------------------------------------------*//**
+ * See "mss_rtc.h" for details of how to use this function.
+ */
+void
+MSS_RTC_start
+(
+    void
+)
+{
+    RTC->CONTROL_REG = CONTROL_RTC_START_MASK;
+}
+
+/*-------------------------------------------------------------------------*//**
+ * See "mss_rtc.h" for details of how to use this function.
+ */
+void
+MSS_RTC_stop
+(
+    void
+)
+{
+    uint32_t rtc_running;
+    
+    /*
+     * Send command to stop RTC.
+     */
+    RTC->CONTROL_REG = CONTROL_RTC_STOP_MASK;
+    
+    /* 
+     * Wait for RTC internal synchronization to take place and RTC to actually
+     * stop.
+     */
+    do {
+        rtc_running =  RTC->CONTROL_REG & CONTROL_RUNNING_MASK;
+    } while(rtc_running);
+}
+
+/*-------------------------------------------------------------------------*//**
+  See "mss_rtc.h" for details of how to use this function.
+ */
+void
+MSS_RTC_reset_counter
+(
+    void
+)
+{
+    uint32_t upload_in_progress;
+    
+    RTC->CONTROL_REG = CONTROL_RESET_MASK;
+    
+    /* Wait for the upload to complete. */
+    do {
+        upload_in_progress = RTC->CONTROL_REG & CONTROL_UPLOAD_MASK;
+    } while(upload_in_progress);
+}
+
+/*-------------------------------------------------------------------------*//**
+  See "mss_rtc.h" for details of how to use this function.
+ */
+uint32_t MSS_RTC_get_update_flag(void)
+{
+    uint32_t updated;
+    updated = RTC->CONTROL_REG & CONTROL_UPDATED_MASK;
+    return updated;
+}
+
+/*-------------------------------------------------------------------------*//**
+  See "mss_rtc.h" for details of how to use this function.
+ */
+void MSS_RTC_clear_update_flag(void)
+{
+    /* Clear the "updated" control bit. */
+    RTC->CONTROL_REG = CONTROL_UPDATED_MASK;
+}
+
+/*-------------------------------------------------------------------------*//**
+  See "mss_rtc.h" for details of how to use this function.
+ */
+void MSS_RTC_enable_irq(void)
+{
+    /*
+     * Only the NVIC level interrupt enable is performed within this function.
+     * The RTC level interrupt enable is performed within the alarm setting
+     * functions.
+     * This avoid the MODE register being modified whenever Cortex-M3 RTC
+     * interrupts are enabled/disabled. 
+     */
+    NVIC_EnableIRQ(RTC_Wakeup_IRQn);
+}
+
+/*-------------------------------------------------------------------------*//**
+  See "mss_rtc.h" for details of how to use this function.
+ */
+void
+MSS_RTC_disable_irq
+(
+    void
+)
+{
+    /*
+     * Only the NVIC level interrupt disable is performed within this function.
+     * This avoid the MODE register being modified whenever Cortex-M3 RTC
+     * interrupts are enabled/disabled. 
+     */
+    NVIC_DisableIRQ(RTC_Wakeup_IRQn);
+}
+
+/*-------------------------------------------------------------------------*//**
+ * See "mss_rtc.h" for details of how to use this function.
+ */
+void
+MSS_RTC_clear_irq
+(
+    void
+)
+{
+    /* Clear wake up interrupt signal */
+    RTC->CONTROL_REG = CONTROL_WAKEUP_CLR_MASK;
+}
+
+/*-------------------------------------------------------------------------*//**
+  The get_clock_mode() function gets the clock mode of RTC hardware.
+  Possible clock modes are:
+    MSS_RTC_CALENDAR_MODE
+    MSS_RTC_BINARY_MODE
+ */
+static uint8_t
+get_clock_mode
+(
+    void
+)
+{
+    uint8_t clock_mode;
+
+    clock_mode = (uint8_t)(RTC->MODE_REG & MODE_CLK_MODE_MASK);
+
+    return(clock_mode);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_rtc/mss_rtc.h b/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_rtc/mss_rtc.h
new file mode 100644
index 000000000..af7c106f6
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_rtc/mss_rtc.h
@@ -0,0 +1,710 @@
+/*******************************************************************************
+ * (c) Copyright 2008-2013 Microsemi SoC Products Group.  All rights reserved.
+ * 
+ *  SmartFusion2 MSS RTC bare metal software driver public API.
+ *
+ * SVN $Revision: 5396 $
+ * SVN $Date: 2013-03-27 21:57:50 +0000 (Wed, 27 Mar 2013) $
+ */
+
+/*=========================================================================*//**
+  @mainpage SmartFusion2 MSS RTC Bare Metal Driver.
+
+  @section intro_sec Introduction
+  The SmartFusion2 microcontroller subsystem (MSS) includes a real time counter
+  (RTC) that can generate alarms and wakeup interrupts in real time. This
+  software driver provides a set of functions for controlling the MSS RTC as
+  part of a bare metal system where no operating system is available. The driver
+  can be adapted for use as part of an operating system, but the implementation
+  of the adaptation layer between the driver and the operating system's driver
+  model is outside the scope of the driver.
+  
+  The MSS RTC driver provides support for the following features:
+    - Initialization of the RTC
+    - Configuration of the RTC timebase
+    - Configuration as a calendar or binary mode counter
+    - Set the current calendar or binary mode count
+    - Get the current calendar or binary mode count
+    - Start and stop the RTC counting
+    - Set alarm conditions
+    - Enable, disable and clear the wakeup interrupt
+    
+  @section hw_dependencies Hardware Flow Dependencies
+  The configuration of all features of the MSS RTC is covered by this driver
+  with the exception of the clock source driving the MSS RTC clock (RTCCLK)
+  input. The SmartFusion2 MSS clock controller can supply one of three clock
+  sources to the MSS RTC clock input:
+    - Crystal Oscillator 32.768 kHz
+    - 1MHz Oscillator
+    - 50MHz Oscillator.  (25 MHz in a 1.0v part).
+  The SmartFusion2 MSS configurator tool in the hardware flow configures one
+  of these clocks as the RTCCLK input source.
+  The base address and register addresses and interrupt number assignment for
+  the MSS RTC block are defined as constants in the SmartFusion2 CMSIS HAL. You
+  must ensure that the SmartFusion2 CMSIS HAL is either included in the software
+  tool chain used to build your project or is included in your project.
+  
+  @section theory_op Theory of Operation
+  The MSS RTC driver functions are grouped into the following categories:
+    - Initialization of the RTC driver and hardware
+    - Setting and reading the RTC counter current value
+    - Setting RTC alarm values
+    - Starting and stopping the RTC
+    - Interrupt Control
+    
+  Initialization
+  The MSS RTC driver is initialized through a call to the MSS_RTC_init()
+  function. The MSS_RTC_init() function must be called before any other MSS RTC
+  driver functions are called.
+  The MSS_RTC_init() function:
+    - Stops the RTC counters and disables the RTC alarm
+    - Disables the RTC wakeup interrupt in the RTC and in the Cortex-M3
+      interrupt controller (NVIC).
+    - Clears any pending RTC wakeup interrupt in the RTC and in the Cortex-M3
+      interrupt controller (NVIC).
+    - Enables the RTC_WAKEUP_CR[0] mask bit in the MSS System Register to
+      connect the RTC wakeup interrupt to the Cortex-M3 interrupt controller.
+    - Resets the RTC counters and the alarm and compare registers
+    - Sets the RTC's operating mode to binary counter mode or calendar counter
+      mode, as specified by the mode parameter
+    - Sets the RTC's prescaler register to the value specified by the prescaler
+      parameter. The frequency of the clock source driving the MSS RTC clock
+      (RTCCLK) input is required to calculate the prescaler value.
+    
+  Setting and Reading the RTC Counter Value
+  The MSS RTC supports two mode of operation � binary mode and calendar mode.
+  The following functions are used to set and read the current value of the
+  counter when the MSS RTC is configured to operate in binary mode:
+    - MSS_RTC_set_binary_count() � This function is used to set the current
+      value of the RTC binary counter.
+    - MSS_RTC_get_binary_count() � This function is used to read the current
+      value of the RTC binary counter.
+  The following functions are used to set and read the current value of the
+  counter the MSS RTC is configured to operate in calendar mode:
+    - MSS_RTC_set_calendar_count() � This function is used to set the current
+      value of the RTC calendar counter.
+    - MSS_RTC_get_calendar_count() � This function is used to read the current
+      value of the RTC calendar counter.
+ 
+  The following functions resets the RTC counter in either binary and calendar
+  operating mode:
+    - MSS_RTC_reset_counter() � This function resets the RTC counter.
+    
+  Setting RTC Alarms
+  The MSS RTC can generate alarms when the counter matches a specified count
+  value in binary mode or a date and time in calendar mode.
+  The following functions are used to set up alarms:
+    - MSS_RTC_set_binary_count_alarm() � This function sets up one-shot or
+      periodic alarms when the MSS RTC is configured to operate in binary mode.
+    - MSS_RTC_set_calendar_count_alarm() � This function sets up one-shot or
+      periodic alarms when the MSS RTC is configured to operate in calendar
+      mode.
+  Note: The alarm asserts a wakeup interrupt to the Cortex-M3. This function
+        enables the RTC�s wakeup interrupt output, however the RTC wakeup
+        interrupt input to the Cortex-M3 NVIC must be enabled separately by
+        calling the MSS_RTC_enable_irq() function. The alarm can be disabled at
+        any time by calling the MSS_RTC_disable_irq() function. activate
+  
+  Starting and Stopping the RTC Counter
+  The following functions start and stop the RTC counter:
+    - MSS_RTC_start() � This function starts the RTC counter.
+    - MSS_RTC_stop() � This function stops the RTC counter.
+    
+  Interrupt Control
+  The MSS_RTC_init() function enables the RTC_WAKEUP_CR[0] mask bit in the MSS
+  System Register to connect the RTC wakeup interrupt to the Cortex-M3 interrupt
+  controller.
+  An RTC_Wakeup_IRQHandler() default implementation is defined, with weak
+  linkage, in the SmartFusion2 CMSIS HAL. You must provide your own
+  implementation of the RTC_Wakeup_IRQHandler() function, which will override
+  the default implementation, to suit your application.
+  The function prototype for the RTC wakeup interrupt handler is as follows:
+    void RTC_Wakeup_IRQHandler ( void )
+  The RTC wakeup interrupt is controlled using the following functions:
+    - MSS_RTC_enable_irq() � The MSS_RTC_enable_irq() function enables the RTC
+      to interrupt the Cortex-M3 when a wakeup alarm occurs.
+    - MSS_RTC_disable_irq() � The MSS_RTC_disable_irq() function disables the
+      RTC from interrupting the Cortex-M3 when a wakeup alarm occurs.
+    - MSS_RTC_clear_irq() � The MSS_RTC_clear_irq() function clears a pending
+      RTC wakeup interrupt at the RTC wakeup output. You must call the
+      MSS_RTC_clear_irq() function as part of your implementation of the
+      RTC_Wakeup_IRQHandler() interrupt service routine (ISR) in order to
+      prevent the same interrupt event retriggering a call to the ISR.
+
+ *//*=========================================================================*/
+#ifndef MSS_RTC_H_
+#define MSS_RTC_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif 
+
+#include "../../CMSIS/m2sxxx.h"
+
+/*-------------------------------------------------------------------------*//**
+  The MSS_RTC_BINARY_MODE constant is used to specify the mode parameter to the
+  MSS_RTC_init() function. The RTC will run in binary mode if this constant is
+  used. In binary mode, the calendar counter counts consecutively from 0 all the
+  way to 2^43.
+ */
+#define MSS_RTC_BINARY_MODE               0u
+
+/*-------------------------------------------------------------------------*//**
+  The MSS_RTC_CALENDAR_MODE constant is used to specify the mode parameter to
+  the MSS_RTC_init() function. The RTC will run in calendar mode if this
+  constant is used. In calendar mode, the calendar counter counts seconds,
+  minutes, hours, days, months, years, weekdays and weeks.
+ */
+#define MSS_RTC_CALENDAR_MODE             1u
+
+/*-------------------------------------------------------------------------*//**
+  The alarm_value parameter of the MSS_RTC_set_calendar_count_alarm() function
+  is a pointer to an mss_rtc_calendar_t data structure specifying the date and
+  time at which the alarm is to occur. You must assign the required date and
+  time values to the mss_rtc_calendar_t structure before calling the function.
+  Any of the fields of the mss_rtc_calendar_t structure can be set to
+  MSS_RTC_CALENDAR_DONT_CARE, to indicate that they are not to be considered in
+  deciding when the alarm will occur; this is necessary when setting periodic
+  alarms. 
+ */
+#define MSS_RTC_CALENDAR_DONT_CARE      0xFFu
+
+/*-------------------------------------------------------------------------*//**
+  Days of the week.
+ */
+#define MSS_RTC_SUNDAY      1u
+#define MSS_RTC_MONDAY      2u
+#define MSS_RTC_TUESDAY     3u
+#define MSS_RTC_WEDNESDAY   4u
+#define MSS_RTC_THRUSDAY    5u
+#define MSS_RTC_FRIDAY      6u
+#define MSS_RTC_SATURDAY    7u
+
+/*-------------------------------------------------------------------------*//**
+  The mss_rtc_alarm_type_t enumeration is used as the alarm_type parameter for
+  the MSS_RTC_set_calendar_count_alarm() and MSS_RTC_set_binary_count_alarm()
+  functions to specify whether the requested alarm should occur only one time or
+  periodically.
+ */
+typedef enum {
+    MSS_RTC_SINGLE_SHOT_ALARM,
+    MSS_RTC_PERIODIC_ALARM
+} mss_rtc_alarm_type_t;
+
+/*-------------------------------------------------------------------------*//**
+  A pointer to an instance of the mss_rtc_calender_t data structure is used to
+  write new date and time values to the RTC using the
+  MSS_RTC_set_rtc_calendar_count() and MSS_RTC_set_calendar_count_alarm()
+  functions. The MSS_RTC_get_calendar_count() function also uses a pointer to an
+  instance of the mss_rtc_calender_t data structure to read the current date and
+  time value from the RTC.
+ */
+typedef struct mss_rtc_calendar
+{
+     uint8_t second;
+     uint8_t minute;
+     uint8_t hour;
+     uint8_t day;
+     uint8_t month;
+     uint8_t year;
+     uint8_t weekday;
+     uint8_t week;
+} mss_rtc_calendar_t ;
+
+/*-------------------------------------------------------------------------*//**
+  The MSS_RTC_init() function initializes the RTC driver and hardware to a known
+  state. 
+  To initialize the RTC hardware, this function:
+    - Stops the RTC counters and disables the RTC alarm
+    - Disables the RTC wakeup interrupt in the RTC and in the Cortex-M3
+      interrupt controller (NVIC).
+    - Clears any pending RTC wakeup interrupt in the RTC and in the Cortex-M3
+      interrupt controller (NVIC).
+    - Resets the RTC counters and the alarm and compare registers
+    - Sets the RTC's operating mode to binary counter mode or calendar counter
+      mode, as specified by the mode parameter
+    - Sets the RTC's prescaler register to the value specified by the prescaler
+      parameter
+  The MSS clock controller can supply one of three clock sources to the RTC
+  clock input (RTCCLK):
+    - Crystal Oscillator 32.768 kHz
+    - 1MHz Oscillator
+    - 50MHz Oscillator.  (25 MHz in a 1.0v part).
+  For calendar mode, program the prescaler register to generate a 1Hz signal
+  from the active RTCCLK according to the following equation:
+    prescaler = RTCCLK � 1 (where RTCCLK unit is Hz)
+  For a 32.768 kHz clock, set the prescaler to 32768 - 1 = 32767. The prescaler
+  register is 26 bits wide, allowing clock sources of up to 67 MHz to generate
+  the 1Hz time base.
+  For binary mode, the prescaler register can be programmed to generate a 1Hz
+  time base or a different time base, as required.
+  
+  @param mode
+    The mode parameter is used to specify the operating mode of the RTC. The
+    allowed values for mode are:
+      - MSS_RTC_BINARY_MODE
+      - MSS_RTC_CALENDAR_MODE
+    
+  @param prescaler
+    The prescaler parameter specifies the value to divide the incoming RTC clock
+    by, to generate the RTC time base signal. For calendar mode, set the
+    prescaler value to generate a 1Hz time base from the incoming RTC clock
+    according to the following equation:
+        prescaler = RTCCLK � 1    (where the RTCCLK unit is Hz)
+    For binary mode, set the prescaler value to generate a 1Hz time base or a
+    different time base, as required.
+    The prescaler parameter can be any integer value in the range 2 to 2^26.
+    
+  @return
+    This function does not return a value.
+    
+  The example code below shows how the RTC can be initialized only after a power-on
+  reset.
+  @code
+    #define PO_RESET_DETECT_MASK    0x00000001u
+    
+    void init_application(void)
+    {
+        uint32_t power_on_reset;
+        power_on_reset = SYSREG->RESET_SOURCE_CR & PO_RESET_DETECT_MASK;
+        if(power_on_reset)
+        {
+            MSS_RTC_init(MSS_RTC_CALENDAR_MODE, 32767);
+            SYSREG->RESET_SOURCE_CR = PO_RESET_DETECT_MASK;
+        }
+    }
+  @endcode
+ */
+void
+MSS_RTC_init
+(
+    uint8_t mode,
+    uint32_t prescaler
+);
+
+/*-------------------------------------------------------------------------*//**
+  The MSS_RTC_set_rtc_calendar_count() function sets the current value of the
+  RTC calendar counter.
+  Note: This function must only be used when the RTC is configured to operate in
+        calendar counter mode.
+        
+  @param new_rtc_value
+    The new_rtc_value parameter is a pointer to an mss_rtc_calendar_t data
+    structure specifying the new date and time value from which the RTC will
+    increment. You must populate the mss_rtc_calendar_t structure with the
+    required date and time values before calling this function.
+    
+  @return
+    This function does not return a value.
+ */
+
+void
+MSS_RTC_set_calendar_count
+(
+    const mss_rtc_calendar_t *new_rtc_value
+);
+
+/*-------------------------------------------------------------------------*//**
+  The MSS_RTC_set_binary_count() function sets the current value of the RTC
+  binary counter.
+  Note: This function must only be used when the RTC is configured to operate in
+        binary counter mode.
+        
+  @param new_rtc_value
+    The new_rtc_value parameter specifies the new count value from which the RTC
+    will increment. The binary counter is 43 bits wide, so the maximum allowed
+    binary value is 2^43.
+
+  @return
+    This function does not return a value.
+ */
+
+void
+MSS_RTC_set_binary_count
+(
+    uint64_t new_rtc_value
+);
+
+/*-------------------------------------------------------------------------*//**
+  The MSS_RTC_get_calendar_count() function returns the current value of the RTC
+  calendar counter via the data structure pointed to by the p_rtc_calendar
+  parameter.
+  Note: This function must only be used when the RTC is configured to operate in
+        calendar counter mode.
+        
+  @param p_rtc_calendar
+    The p_rtc_calendar parameter is a pointer to an mss_rtc_calendar_t data
+    structure where the current value of the calendar counter will be written by
+    the MSS_RTC_get_calendar_count() function
+    
+  @return
+    This function does not return a value.
+ */
+void
+MSS_RTC_get_calendar_count
+(
+    mss_rtc_calendar_t *p_rtc_calendar
+);
+
+/*-------------------------------------------------------------------------*//**
+  The MSS_RTC_get_binary_count() function returns the current value of the RTC
+  binary counter. 
+  Note: This function must only be used when the RTC is configured to operate in
+        binary counter mode.
+        
+  @param
+    This function takes no parameters.
+
+  @return
+    This function returns the current value of the RTC binary counter as an
+    unsigned 64-bit integer.
+ */
+uint64_t
+MSS_RTC_get_binary_count(void);
+
+/*-------------------------------------------------------------------------*//**
+  The MSS_RTC_start() function starts the RTC incrementing.
+
+  @param
+    This function takes no parameters.
+
+  @return
+    This function does not return a value.
+ */
+void MSS_RTC_start(void);
+
+/*-------------------------------------------------------------------------*//**
+  The MSS_RTC_stop() function stops the RTC from incrementing.
+
+  @param
+    This function takes no parameters.
+
+  @return
+    This function does not return a value.
+ */
+void MSS_RTC_stop(void);
+
+/*-------------------------------------------------------------------------*//**
+  The MSS_RTC_reset_counter() function resets the RTC counters. If the counter
+  was running before calling this function, then it continues incrementing from
+  the counter�s reset value.
+  
+  @param
+    This function takes no parameters.
+
+  @return
+    This function does not return a value.
+ */
+void MSS_RTC_reset_counter(void);
+
+/*-------------------------------------------------------------------------*//**
+  The MSS_RTC_enable_irq() function enables the RTC wakeup output to interrupt
+  the Cortex-M3 when an alarm occurs. It enables the RTC wakeup interrupt
+  (RTC_Wakeup_IRQn) in the Cortex-M3 interrupt controller (NVIC). The
+  RTC_Wakeup_IRQHandler() function will be called when an RTC wakeup interrupt
+  occurs.
+  Note: An RTC_Wakeup_IRQHandler() default implementation is defined, with weak
+        linkage, in the SmartFusion2 CMSIS HAL. You must provide your own
+        implementation of the RTC_Wakeup_IRQHandler() function, which will
+        override the default implementation, to suit your application.
+  Note: This function only enables the RTC wakeup interrupt at the Cortex-M3
+        NVIC level. The alarm setting functions enable the wakeup interrupt
+        output from the RTC.
+ */
+void MSS_RTC_enable_irq(void);
+
+/*-------------------------------------------------------------------------*//**
+  The MSS_RTC_disable_irq() function disables the RTC wakeup interrupt
+  (RTC_Wakeup_IRQn) in the Cortex-M3 interrupt controller (NVIC).
+  Note: This function only disables the RTC wakeup interrupt at the Cortex-M3
+        NVIC level. It does not disable the wakeup interrupt output from the
+        RTC.
+        
+   @param
+     This function takes no parameters.
+
+   @return
+     This function does not return a value.
+ */
+void MSS_RTC_disable_irq(void);
+
+/*-------------------------------------------------------------------------*//**
+  The MSS_RTC_clear_irq() function clears a pending wakeup interrupt from the
+  RTC. This function does not clear the interrupt in the Cortex-M3 interrupt
+  controller (NVIC); it only clears the wakeup output from the RTC.
+  Note: You must call the MSS_RTC_clear_irq() function as part of your
+        implementation of the RTC_Wakeup_IRQHandler() RTC wakeup interrupt
+        service routine (ISR) in order to prevent the same interrupt event
+        retriggering a call to the ISR.
+        
+  @param
+    This function takes no parameters.
+
+  @return
+    This function does not return a value.
+  
+  Example:
+  The example code below demoinstrates how the MSS_RTC_clear_irq() function is
+  intended to be used as part of the RTC wakeup interrupt servicer routine used
+  by an application to handle RTC alarms.
+  @code
+    #if defined(__GNUC__)
+    __attribute__((__interrupt__)) void RTC_Wakeup_IRQHandler( void )
+    #else
+    void RTC_Wakeup_IRQHandler( void )
+    #endif
+    {
+        process_alarm();
+        MSS_RTC_clear_irq();
+    }
+  @endcode
+*/
+void MSS_RTC_clear_irq(void);
+
+/*-------------------------------------------------------------------------*//**
+  The MSS_RTC_set_calendar_count_alarm() function sets up the RTC to generate an
+  alarm when the RTC count reaches the time/date specified by the alarm_value
+  parameter. The alarm asserts a wakeup interrupt to the Cortex-M3. This
+  function enables the RTC�s wakeup interrupt output, however the RTC wakeup
+  interrupt input to the Cortex-M3 NVIC must be enabled separately by calling
+  the MSS_RTC_enable_irq() function. The alarm can be disabled at any time by
+  calling the MSS_RTC_disable_irq() function.
+  
+  Single-shot alarm
+  The alarm can be a single-shot alarm, which will generate a single wakeup
+  interrupt the first time the RTC count reaches the time/date specified by
+  alarm_value. A single shot alarm is achieved by specifying a value for every
+  field of the mss_rtc_calendar_t data structure pointed to by the alarm_value
+  parameter. The RTC counter will keep incrementing after a single shot alarm
+  occurs.
+  
+  Periodic alarm
+  The alarm can also be a periodic alarm, which will generate a wakeup interrupt
+  every time the RTC count reaches the time/date specified by alarm_value, with
+  the counter running in a continuous loop. The periodic alarm can be set to
+  occur every minute, hour, day, month, year, week, day of the week, or any
+  valid combination of these. This is achieved by setting some of the fields of
+  the mss_rtc_calendar_t data structure pointed to by the alarm_value parameter,
+  to MSS_RTC_CALENDAR_DONT_CARE. For example, setting the weekday field to
+  MSS_RTC_MONDAY and all other fields to MSS_RTC_CALENDAR_DONT_CARE will result
+  in an alarm occurring every Monday. You can refine the time at which the alarm
+  will occur by specifying values for the hour, minute and second fields.
+  Note: This function must only be used when the RTC is configured to operate in
+        calendar counter mode.
+  
+  @param alarm_value
+    The alarm_value parameter is a pointer to an mss_rtc_calendar_t data
+    structure specifying the date and time at which the alarm is to occur. You
+    must assign the required date and time values to the mss_rtc_calendar_t
+    structure before calling this function. Some of the fields within the
+    mss_rtc_calendar_t structure can be set to MSS_RTC_CALENDAR_DONT_CARE, to
+    indicate that they are not to be considered in deciding when the alarm will
+    occur; this is necessary when setting periodic alarms.
+  
+  @return
+    This function does not return a value.
+     
+  Examples:
+  
+  The following example code demonstrates how to configure the RTC to generate a
+  single calendar alarm at a specific date and time. The alarm will only occur
+  once and the RTC will keep incrementing regardless of the alarm taking place.
+  
+  @code
+    const mss_rtc_calendar_t initial_calendar_count =
+    {
+        15u,     second
+        30u,     minute
+        6u,      hour
+        6u,      day
+        9u,      month
+        12u,     year
+        5u,      weekday
+        37u      week
+    };
+    
+    mss_rtc_calendar_t alarm_calendar_count =
+    {
+        17u,     second
+        30u,     minute
+        6u,      hour
+        6u,      day
+        9u,      month
+        12u,     year
+        5u,      weekday
+        37u      week
+    };
+    
+    MSS_RTC_init(MSS_RTC_CALENDAR_MODE, RTC_PRESCALER);
+    MSS_RTC_clear_irq();
+    MSS_RTC_set_calendar_count(&initial_calendar_count);
+    MSS_RTC_enable_irq();
+    MSS_RTC_start();
+    
+    MSS_RTC_set_calendar_count_alarm(&alarm_calendar_count);
+  @endcode
+  
+  The following example code demonstrates how to configure the RTC to generate a
+  periodic calendar alarm. The RTC is configured to generate an alarm every
+  Tuesday at 16:45:00. The alarm will reoccur every week until the RTC wakeup
+  interrupt is disabled using a call to MSS_RTC_disable_irq().
+  
+  @code
+    mss_rtc_calendar_t initial_calendar_count =
+    {
+        58u,                            <--second
+        59u,                            <--minute
+        23u,                            <--hour
+        10u,                            <--day
+        9u,                             <--month
+        12u,                            <--year
+        MSS_RTC_MONDAY,                 <--weekday
+        37u                             <--week
+    };
+    
+    mss_rtc_calendar_t alarm_calendar_count =
+    {
+        MSS_RTC_CALENDAR_DONT_CARE,     <--second
+        45u,                            <--minute
+        16u,                            <--hour
+        MSS_RTC_CALENDAR_DONT_CARE,     <--day
+        MSS_RTC_CALENDAR_DONT_CARE,     <--month
+        MSS_RTC_CALENDAR_DONT_CARE,     <--year
+        MSS_RTC_TUESDAY,                <--weekday
+        MSS_RTC_CALENDAR_DONT_CARE      <--week
+    };
+    
+    MSS_RTC_init(MSS_RTC_CALENDAR_MODE, RTC_PRESCALER);
+    MSS_RTC_set_calendar_count(&initial_calendar_count);
+    MSS_RTC_enable_irq();
+    MSS_RTC_start();
+    
+    MSS_RTC_set_calendar_count_alarm(&alarm_calendar_count);
+  @endcode
+  
+  The following example code demonstrates the code that you need to include in
+  your application to handle alarms. It is the interrupt service routine for the
+  RTC wakeup interrupt input to the Cortex-M3 NVIC. You need to add your
+  application code in this function in place of the process_alarm() function but
+  you must retain the call to MSS_RTC_clear_irq() to ensure that the same alarm
+  does not retrigger the interrupt.
+  
+  @code
+    #if defined(__GNUC__)
+    __attribute__((__interrupt__)) void RTC_Wakeup_IRQHandler( void )
+    #else
+    void RTC_Wakeup_IRQHandler( void )
+    #endif
+    {
+        process_alarm();
+        MSS_RTC_clear_irq();
+    }
+  @endcode
+ */
+void MSS_RTC_set_calendar_count_alarm
+(
+    const mss_rtc_calendar_t * alarm_value
+);
+
+/*-------------------------------------------------------------------------*//**
+  The MSS_RTC_set_binary_count_alarm() function sets up the RTC to generate an
+  alarm when the RTC count reaches the value specified by the alarm_value
+  parameter. The alarm asserts a wakeup interrupt to the Cortex-M3. This
+  function enables the RTC�s wakeup interrupt output, however the RTC wakeup
+  interrupt input to the Cortex-M3 NVIC must be enabled separately by calling
+  the MSS_RTC_enable_irq() function. The alarm can be disabled at any time by
+  calling the MSS_RTC_disable_irq() function.
+
+  Single-shot alarm
+  The alarm can be a single-shot alarm, which will generate a single wakeup
+  interrupt the first time the RTC count reaches the value specified by the
+  alarm_value parameter. Setting the alarm_value parameter to
+  MSS_RTC_PERIODIC_ALARM produces a single-shot alarm. The RTC counter continues
+  incrementing when a single shot alarm occurs.
+
+  Periodic alarm
+  The alarm can also be a periodic alarm, which will generate a wakeup interrupt
+  every time the RTC count reaches the value specified by the alarm_value
+  parameter. Setting the alarm_value parameter to MSS_RTC_SINGLE_SHOT_ALARM
+  produces a periodic alarm. The RTC counter automatically wraps around to zero
+  and continues incrementing when a periodic alarm occurs.
+  Note: This function must only be used when the RTC is configured to operate in
+        binary counter mode
+  
+  @param alarm_value
+    The alarm_value parameter is a 64-bit unsigned value specifying the RTC
+    counter value that must be reached for the requested alarm to occur.
+  
+  @param alarm_type
+    The alarm_type parameter specifies whether the requested alarm is a single
+    shot or periodic alarm. It can only take one of these two values:
+     - MSS_RTC_SINGLE_SHOT_ALARM,
+     - MSS_RTC_PERIODIC_ALARM
+  
+  @return
+    This function does not return a value.
+ */
+void MSS_RTC_set_binary_count_alarm
+(
+    uint64_t alarm_value,
+    mss_rtc_alarm_type_t alarm_type
+);
+
+/*-------------------------------------------------------------------------*//**
+  The MSS_RTC_get_update_flag() function indicates if the RTC counter has
+  incremented since the last call to MSS_RTC_clear_update_flag(). It returns
+  zero if no RTC counter increment has occurred. It returns a non-zero value if
+  the RTC counter has incremented. This function can be used whether the RTC is
+  configured to operate in calendar or binary counter mode.
+  
+  @return
+   This function returns, 
+   zero:     if the RTC has not incremented since the last call to
+             MSS_RTC_clear_update_flag(), 
+   non-zero: if the RTC has incremented since the last call to
+             MSS_RTC_clear_update_flag().
+
+   
+  Example
+  This example waits for the RTC timer to increment by one second.
+  @code
+    void wait_start_of_second(void)
+    {
+        uint32_t rtc_count_updated;
+        MSS_RTC_clear_update_flag();
+        do {
+            rtc_count_updated = MSS_RTC_get_update_flag();
+        } while(!rtc_count_updated)
+    }
+  @endcode
+ */
+uint32_t MSS_RTC_get_update_flag(void);
+
+/*-------------------------------------------------------------------------*//**
+  The MSS_RTC_clear_update_flag() function clears the CONTROL register flag that
+  is set when the RTC counter increments. It is used alongside function
+  MSS_RTC_get_update_flag() to detect RTC counter increments.
+  
+  @return
+    This function does not return a value.
+    
+  Example
+  The example below will wait for the RTC timer to increment by one second.
+  @code
+  void wait_start_of_second(void)
+  {
+      uint32_t rtc_count_updated;
+      MSS_RTC_clear_update_flag();
+      do {
+          rtc_count_updated = MSS_RTC_get_update_flag();
+      } while(!rtc_count_updated)
+  }
+  @endcode
+ */
+void MSS_RTC_clear_update_flag(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* MSS_RTC_H_ */
diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_sys_services/mss_comblk.c b/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_sys_services/mss_comblk.c
new file mode 100644
index 000000000..c0c2e3a43
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_sys_services/mss_comblk.c
@@ -0,0 +1,703 @@
+/*******************************************************************************
+ * (c) Copyright 2012 Microsemi SoC Products Group.  All rights reserved.
+ *
+ * SmartFusion2 COMBLK access functions.
+ *
+ * SVN $Revision: 5615 $
+ * SVN $Date: 2013-04-05 14:48:10 +0100 (Fri, 05 Apr 2013) $
+ */
+ 
+#include "mss_comblk.h"
+#include "../../CMSIS/mss_assert.h"
+
+/*==============================================================================
+ *
+ */
+/*------------------------------------------------------------------------------
+ * Control register bit masks.
+ */
+#define CR_FLUSHOUT_MASK    0x01u
+#define CR_SIZETX_MASK      0x04u
+#define CR_ENABLE_MASK      0x10u
+#define CR_LOOPBACK_MASK    0x20u
+
+/*------------------------------------------------------------------------------
+ * Status and interrupt enable registers bit masks.
+ */
+#define TXTOKAY_MASK    0x01u
+#define RCVOKAY_MASK    0x02u
+
+/*------------------------------------------------------------------------------
+ * DATA8 register bit masks.
+ */
+#define DATA8_COMMAND_MASK  0x8000u
+
+/*------------------------------------------------------------------------------
+ * COMBLK driver states.
+ */
+#define COMBLK_IDLE             0u
+#define COMBLK_TX_CMD           1u
+#define COMBLK_TX_DATA          2u
+#define COMBLK_WAIT_RESPONSE    3u
+#define COMBLK_RX_RESPONSE      4u
+#define COMBLK_TX_PAGED_DATA    5u
+
+/*==============================================================================
+ * COMBLK interrupt servcie routine.
+ */
+void ComBlk_IRQHandler(void);
+
+/*==============================================================================
+ * Local functions.
+ */
+static void abort_current_cmd(void);
+static void send_cmd_opcode(uint8_t opcode);
+static uint32_t fill_tx_fifo(const uint8_t * p_cmd, uint32_t cmd_size);
+static void handle_tx_okay_irq(void);
+static void handle_rx_okay_irq(void);
+static void complete_request(uint16_t response_length);
+static void process_sys_ctrl_command(uint8_t cmd_opcode);
+
+/*==============================================================================
+ * Global variables:
+ */
+static volatile uint8_t g_comblk_cmd_opcode = 0u;
+static const uint8_t * g_comblk_p_cmd = 0u;
+static volatile uint16_t g_comblk_cmd_size = 0u;
+static const uint8_t * g_comblk_p_data = 0u;
+static volatile uint32_t g_comblk_data_size = 0u;
+static uint8_t * g_comblk_p_response = 0u;
+static uint16_t g_comblk_response_size = 0u;
+static volatile uint16_t g_comblk_response_idx = 0u;
+static comblk_completion_handler_t g_comblk_completion_handler = 0;
+
+/*typedef uint32_t (*comblk_page_handler_t)(uint8_t const ** pp_next_page);
+*/
+static uint32_t (*g_comblk_page_handler)(uint8_t const ** pp_next_page) = 0;
+
+static uint8_t g_request_in_progress = 0u;
+
+static uint8_t g_comblk_state = COMBLK_IDLE;
+
+static comblk_async_event_handler_t g_async_event_handler = 0;
+
+/*==============================================================================
+ *
+ */
+void MSS_COMBLK_init(comblk_async_event_handler_t async_event_handler)
+{
+    /*
+     * Disable and clear previous interrupts.
+     */
+    NVIC_DisableIRQ(ComBlk_IRQn);
+    COMBLK->INT_ENABLE = 0u;
+    NVIC_ClearPendingIRQ(ComBlk_IRQn);
+    
+    g_async_event_handler = async_event_handler;
+    
+    /*
+     * Initialialize COMBLK driver state variables:
+     */
+    g_request_in_progress = 0u;
+    g_comblk_cmd_opcode = 0u;
+    g_comblk_p_cmd = 0u;
+    g_comblk_cmd_size = 0u;
+    g_comblk_p_data = 0u;
+    g_comblk_data_size = 0u;
+    g_comblk_p_response = 0u;
+    g_comblk_response_size = 0u;
+    g_comblk_response_idx = 0u;
+    g_comblk_completion_handler = 0;
+    
+    g_comblk_state = COMBLK_IDLE;
+    
+    COMBLK->CONTROL |= CR_ENABLE_MASK;
+    COMBLK->CONTROL &= ~CR_LOOPBACK_MASK;
+    
+    /*--------------------------------------------------------------------------
+     * Enable receive interrupt to receive asynchronous events from the system
+     * controller.
+     */
+    COMBLK->INT_ENABLE &= ~TXTOKAY_MASK;
+    COMBLK->INT_ENABLE |= RCVOKAY_MASK;
+    NVIC_EnableIRQ(ComBlk_IRQn);
+}
+
+/*==============================================================================
+ *
+ */
+void MSS_COMBLK_send_cmd_with_ptr
+(
+    uint8_t cmd_opcode,
+    uint32_t cmd_params_ptr,
+    uint8_t * p_response,
+    uint16_t response_size,
+    comblk_completion_handler_t completion_handler
+)
+{
+    uint32_t tx_okay;
+    
+    /*--------------------------------------------------------------------------
+     * Disable and clear previous interrupts.
+     */
+    NVIC_DisableIRQ(ComBlk_IRQn);
+    COMBLK->INT_ENABLE = 0u;
+    NVIC_ClearPendingIRQ(ComBlk_IRQn);
+    
+    /*--------------------------------------------------------------------------
+     * Abort current command if any.
+     */
+    abort_current_cmd();
+    
+    /*--------------------------------------------------------------------------
+     * Initialialize COMBLK driver state variables:
+     */
+    g_request_in_progress = 1u;
+    g_comblk_cmd_opcode = cmd_opcode;
+    g_comblk_p_cmd = 0u;
+    g_comblk_cmd_size = 0u;
+    g_comblk_p_data = 0u;
+    g_comblk_data_size = 0u;
+    g_comblk_p_response = p_response;
+    g_comblk_response_size = response_size;
+    g_comblk_response_idx = 0u;
+    g_comblk_page_handler = 0u;
+    g_comblk_completion_handler = completion_handler;
+    
+    /*--------------------------------------------------------------------------
+     * Send command opcode as a single byte write to the Tx FIFO.
+     */
+    send_cmd_opcode(g_comblk_cmd_opcode);
+    
+    /*--------------------------------------------------------------------------
+     * Send the command parameters pointer to the Tx FIFO as a single 4 bytes
+     * write to the Tx FIFO.
+     */
+    COMBLK->CONTROL |= CR_SIZETX_MASK;
+    
+    /* Wait for space to become available in Tx FIFO. */
+    do {
+        tx_okay = COMBLK->STATUS & TXTOKAY_MASK;
+    } while(0u == tx_okay);
+    
+    /* Send command opcode. */
+    COMBLK->DATA32 = cmd_params_ptr;
+    
+    COMBLK->CONTROL &= ~CR_SIZETX_MASK;
+    
+    g_comblk_state = COMBLK_WAIT_RESPONSE;
+    
+    /*--------------------------------------------------------------------------
+     * Enable interrupt.
+     */
+    COMBLK->INT_ENABLE |= RCVOKAY_MASK;
+    NVIC_EnableIRQ(ComBlk_IRQn);
+}
+
+/*==============================================================================
+ *
+ */
+void MSS_COMBLK_send_cmd
+(
+    const uint8_t * p_cmd,
+    uint16_t cmd_size,
+    const uint8_t * p_data,
+    uint32_t data_size,
+    uint8_t * p_response,
+    uint16_t response_size,
+    comblk_completion_handler_t completion_handler
+)
+{
+    uint32_t size_sent;
+    
+    ASSERT(cmd_size > 0);
+    
+    /*
+     * Disable and clear previous interrupts.
+     */
+    NVIC_DisableIRQ(ComBlk_IRQn);
+    COMBLK->INT_ENABLE = 0u;
+    NVIC_ClearPendingIRQ(ComBlk_IRQn);
+    
+    /*
+     * Abort current command if any.
+     */
+    abort_current_cmd();
+    
+    /*
+     * Initialialize COMBLK driver state variables:
+     */
+    g_request_in_progress = 1u;
+    g_comblk_cmd_opcode = p_cmd[0];
+    g_comblk_p_cmd = p_cmd;
+    g_comblk_cmd_size = cmd_size;
+    g_comblk_p_data = p_data;
+    g_comblk_data_size = data_size;
+    g_comblk_p_response = p_response;
+    g_comblk_response_size = response_size;
+    g_comblk_response_idx = 0u;
+    g_comblk_page_handler = 0u;
+    g_comblk_completion_handler = completion_handler;
+    
+    COMBLK->INT_ENABLE |= RCVOKAY_MASK;
+
+    /*
+     * Fill FIFO with command.
+     */
+    send_cmd_opcode(g_comblk_cmd_opcode);
+    size_sent = fill_tx_fifo(&p_cmd[1], cmd_size - 1u);
+    ++size_sent;    /* Adjust for opcode byte sent. */
+    if(size_sent < cmd_size)
+    {
+        g_comblk_cmd_size = g_comblk_cmd_size - (uint16_t)size_sent;
+        g_comblk_p_cmd = &g_comblk_p_cmd[size_sent];
+        
+        g_comblk_state = COMBLK_TX_CMD;
+    }
+    else
+    {
+        g_comblk_cmd_size = 0u;
+        if(g_comblk_data_size > 0u)
+        {
+            g_comblk_state = COMBLK_TX_DATA;
+        }
+        else
+        {
+            g_comblk_state = COMBLK_WAIT_RESPONSE;
+        }
+    }
+
+    /*
+     * Enable interrupt.
+     */
+    NVIC_EnableIRQ(ComBlk_IRQn);
+}
+
+/*==============================================================================
+ *
+ */
+void MSS_COMBLK_send_paged_cmd
+(
+    const uint8_t * p_cmd,
+    uint16_t cmd_size,
+    uint8_t * p_response,
+    uint16_t response_size,
+    uint32_t (*page_read_handler)(uint8_t const **),
+    void (*completion_handler)(uint8_t *, uint16_t)
+)
+{
+    uint32_t size_sent;
+    uint8_t irq_enable = 0u;
+    
+    ASSERT(cmd_size > 0u);
+    
+    /*
+     * Disable and clear previous interrupts.
+     */
+    NVIC_DisableIRQ(ComBlk_IRQn);
+    COMBLK->INT_ENABLE = 0u;
+    NVIC_ClearPendingIRQ(ComBlk_IRQn);
+    
+    /*
+     * Abort current command if any.
+     */
+    abort_current_cmd();
+    
+    /*
+     * Initialialize COMBLK driver state variables:
+     */
+    g_request_in_progress = 1u;
+    g_comblk_cmd_opcode = p_cmd[0];
+    g_comblk_p_cmd = p_cmd;
+    g_comblk_cmd_size = cmd_size;
+    g_comblk_p_data = 0;
+    g_comblk_data_size = 0u;
+    g_comblk_p_response = p_response;
+    g_comblk_response_size = response_size;
+    g_comblk_response_idx = 0u;
+    g_comblk_page_handler = page_read_handler;
+    g_comblk_completion_handler = completion_handler;
+    
+    /*
+     * Fill FIFO with command.
+     */
+    send_cmd_opcode(g_comblk_cmd_opcode);
+    size_sent = fill_tx_fifo(&p_cmd[1], cmd_size - 1u);
+    ++size_sent;    /* Adjust for opcode byte sent. */
+    if(size_sent < cmd_size)
+    {
+        g_comblk_cmd_size = g_comblk_cmd_size - (uint16_t)size_sent;
+        g_comblk_p_cmd = &g_comblk_p_cmd[size_sent];
+        
+        g_comblk_state = COMBLK_TX_CMD;
+        irq_enable = TXTOKAY_MASK | RCVOKAY_MASK;
+    }
+    else
+    {
+        g_comblk_cmd_size = 0u;
+        g_comblk_state = COMBLK_TX_PAGED_DATA;
+        irq_enable = TXTOKAY_MASK | RCVOKAY_MASK;
+    }
+
+    /*
+     * Enable interrupt.
+     */
+    COMBLK->INT_ENABLE |= irq_enable;
+    NVIC_EnableIRQ(ComBlk_IRQn);
+}
+
+/*==============================================================================
+ * COMBLK interrupt handler.
+ */
+void ComBlk_IRQHandler(void)
+{
+    uint8_t status;
+    uint8_t tx_okay;
+    uint8_t rcv_okay;
+    
+    status = (uint8_t)COMBLK->STATUS;
+    
+    /* Mask off interrupt that are not enabled.*/
+    status &= COMBLK->INT_ENABLE;
+    
+    rcv_okay = status & RCVOKAY_MASK;
+    if(rcv_okay)
+    {
+        handle_rx_okay_irq();
+    }
+        
+    tx_okay = status & TXTOKAY_MASK;
+    if(tx_okay)
+    {
+        handle_tx_okay_irq();
+    }
+}
+
+/*==============================================================================
+ *
+ */
+static void handle_tx_okay_irq(void)
+{
+    switch(g_comblk_state)
+    {
+        /*----------------------------------------------------------------------
+         * The TX_OKAY interrupt should only be enabled for states COMBLK_TX_CMD
+         * and COMBLK_TX_DATA. 
+         */
+        case COMBLK_TX_CMD:
+            if(g_comblk_cmd_size > 0u)
+            {
+                uint32_t size_sent;
+                size_sent = fill_tx_fifo(g_comblk_p_cmd, g_comblk_cmd_size);
+                if(size_sent < g_comblk_cmd_size)
+                {
+                    g_comblk_cmd_size = g_comblk_cmd_size - (uint16_t)size_sent;
+                    g_comblk_p_cmd = &g_comblk_p_cmd[size_sent];
+                }
+                else
+                {
+                    g_comblk_cmd_size = 0u;
+                    if(g_comblk_data_size > 0u)
+                    {
+                        g_comblk_state = COMBLK_TX_DATA;
+                    }
+                    else
+                    {
+                        g_comblk_state = COMBLK_WAIT_RESPONSE;
+                    }
+                }
+            }
+            else
+            {
+                /*
+                 * This is an invalid situation indicating a bug in the driver
+                 * or corrupted memory.
+                 */
+                ASSERT(0);
+                abort_current_cmd();
+            }
+        break;
+            
+        case COMBLK_TX_DATA:
+            if(g_comblk_data_size > 0u)
+            {
+                uint32_t size_sent;
+                size_sent = fill_tx_fifo(g_comblk_p_data, g_comblk_data_size);
+                if(size_sent < g_comblk_data_size)
+                {
+                    g_comblk_data_size = g_comblk_data_size - size_sent;
+                    g_comblk_p_data = &g_comblk_p_data[size_sent];
+                }
+                else
+                {
+                    COMBLK->INT_ENABLE &= ~TXTOKAY_MASK;
+                    g_comblk_state = COMBLK_WAIT_RESPONSE;
+                }
+            }
+            else
+            {
+                /*
+                 * This is an invalid situation indicating a bug in the driver
+                 * or corrupted memory.
+                 */
+                ASSERT(0);
+                abort_current_cmd();
+            }
+        break;
+           
+        case COMBLK_TX_PAGED_DATA:
+            /*
+             * Read a page of data if required.
+             */
+            if(0u == g_comblk_data_size)
+            {
+                if(g_comblk_page_handler != 0)
+                {
+                    g_comblk_data_size = g_comblk_page_handler(&g_comblk_p_data);
+                    if(0u == g_comblk_data_size)
+                    {
+                        COMBLK->INT_ENABLE &= ~TXTOKAY_MASK;
+                        g_comblk_state = COMBLK_WAIT_RESPONSE;
+                    }
+                }
+                else
+                {
+                    ASSERT(0);
+                    abort_current_cmd();
+                }
+            }
+            
+            /*
+             * Transmit the page data or move to COMBLK_WAIT_RESPONSE state if
+             * no further page data could be obtained by the call to the page
+             * handler above.
+             */
+            if(0u == g_comblk_data_size)
+            {
+                COMBLK->INT_ENABLE &= ~TXTOKAY_MASK;
+                g_comblk_state = COMBLK_WAIT_RESPONSE;
+            }
+            else
+            {
+                uint32_t size_sent;
+                size_sent = fill_tx_fifo(g_comblk_p_data, g_comblk_data_size);
+                g_comblk_data_size = g_comblk_data_size - size_sent;
+                g_comblk_p_data = &g_comblk_p_data[size_sent];
+            }
+        break;
+            
+        /*----------------------------------------------------------------------
+         * The TX_OKAY interrupt should NOT be enabled for states COMBLK_IDLE,
+         * COMBLK_WAIT_RESPONSE and COMBLK_RX_RESPONSE.
+         */
+        case COMBLK_IDLE:
+            /* Fall through */
+        case COMBLK_WAIT_RESPONSE:
+            /* Fall through */
+        case COMBLK_RX_RESPONSE:
+            /* Fall through */
+        default:
+            COMBLK->INT_ENABLE &= ~TXTOKAY_MASK;
+            complete_request(0u);
+            g_comblk_state = COMBLK_IDLE;
+        break;
+    }
+}
+
+/*==============================================================================
+ *
+ */
+static void handle_rx_okay_irq(void)
+{
+    uint16_t data16;
+    uint16_t is_command;
+    
+    data16 = (uint16_t)COMBLK->DATA8;
+    is_command = data16 & DATA8_COMMAND_MASK;
+            
+    switch(g_comblk_state)
+    {
+        /*----------------------------------------------------------------------
+         * The RCV_OKAY interrupt should only be enabled for states
+         * COMBLK_WAIT_RESPONSE and COMBLK_RX_RESPONSE. 
+         */
+        case COMBLK_WAIT_RESPONSE:
+            if(is_command)
+            {
+                uint8_t rxed_opcode;
+                rxed_opcode = (uint8_t)data16;
+                if(rxed_opcode == g_comblk_cmd_opcode)
+                {
+                    g_comblk_response_idx = 0u;
+                    g_comblk_p_response[g_comblk_response_idx] = rxed_opcode;
+                    ++g_comblk_response_idx;
+                    g_comblk_state = COMBLK_RX_RESPONSE;
+                }
+                else
+                {
+                    process_sys_ctrl_command(rxed_opcode);
+                }
+            }
+        break;
+            
+        case COMBLK_RX_RESPONSE:
+            if(is_command)
+            {
+                uint8_t rxed_opcode;
+                rxed_opcode = (uint8_t)data16;
+                process_sys_ctrl_command(rxed_opcode);
+            }
+            else
+            {
+                if(g_comblk_response_idx < g_comblk_response_size)
+                {
+                    uint8_t rxed_data;
+                    
+                    rxed_data = (uint8_t)data16;
+                    g_comblk_p_response[g_comblk_response_idx] = rxed_data;
+                    ++g_comblk_response_idx;
+                }
+                
+                if(g_comblk_response_idx == g_comblk_response_size)
+                {
+                    complete_request(g_comblk_response_idx);
+                    g_comblk_state = COMBLK_IDLE;
+                }
+            }
+        break;
+            
+        /*----------------------------------------------------------------------
+         * The RCV_OKAY interrupt should NOT be enabled for states
+         * COMBLK_IDLE, COMBLK_TX_CMD and COMBLK_TX_DATA. 
+         */
+        case COMBLK_TX_PAGED_DATA:
+            /* This is needed because when there is an error, we need to terminate loading the data */
+            if(!is_command)
+            {
+                g_comblk_p_response[1] = (uint8_t)data16;
+                complete_request(2u);
+                g_comblk_state = COMBLK_IDLE;
+            }
+        break;
+        case COMBLK_IDLE:
+            /* Fall through */
+        case COMBLK_TX_CMD:
+            /* Fall through */
+        case COMBLK_TX_DATA:
+            /* Fall through */
+            if(is_command)
+            {
+                uint8_t rxed_opcode;
+                rxed_opcode = (uint8_t)data16;
+                process_sys_ctrl_command(rxed_opcode);
+            }
+        break;
+        
+        default:
+            complete_request(0u);
+            g_comblk_state = COMBLK_IDLE;
+        break;
+    }
+}
+
+/*==============================================================================
+ *
+ */
+static void complete_request
+(
+    uint16_t response_length
+)
+{
+    if(g_comblk_completion_handler != 0)
+    {
+        g_comblk_completion_handler(g_comblk_p_response, response_length);
+        g_comblk_completion_handler = 0;
+        g_request_in_progress = 0u;
+    }
+}
+
+/*==============================================================================
+ *
+ */
+static void abort_current_cmd(void)
+{
+    if(g_request_in_progress)
+    {
+        uint32_t flush_in_progress;
+        
+        /*
+         * Call completion handler just in case we are in a multi threaded system
+         * to avoid a task lockup.
+         */
+        complete_request(g_comblk_response_idx);
+        
+        /*
+         * Flush the FIFOs
+         */
+        COMBLK->CONTROL |= CR_FLUSHOUT_MASK;
+        do {
+            flush_in_progress = COMBLK->CONTROL & CR_FLUSHOUT_MASK;
+        } while(flush_in_progress);
+    }
+}
+
+/*==============================================================================
+ *
+ */
+static void send_cmd_opcode
+(
+    uint8_t opcode
+)
+{
+    uint32_t tx_okay;
+    
+    /* Set transmit FIFO to transfer bytes. */
+    COMBLK->CONTROL &= ~CR_SIZETX_MASK;
+    
+    /* Wait for space to become available in Tx FIFO. */
+    do {
+        tx_okay = COMBLK->STATUS & TXTOKAY_MASK;
+    } while(0u == tx_okay);
+    
+    /* Send command opcode. */
+    COMBLK->FRAME_START8 = opcode;
+}
+
+/*==============================================================================
+ *
+ */
+static uint32_t fill_tx_fifo
+(
+    const uint8_t * p_cmd,
+    uint32_t cmd_size
+)
+{
+    volatile uint32_t tx_okay;
+    uint32_t size_sent;
+
+    /* Set transmit FIFO to transfer bytes. */
+    COMBLK->CONTROL &= ~CR_SIZETX_MASK;
+    
+    size_sent = 0u;
+    tx_okay = COMBLK->STATUS & TXTOKAY_MASK;
+    while((tx_okay != 0u) && (size_sent < cmd_size))
+    {
+        COMBLK->DATA8 = p_cmd[size_sent];
+        ++size_sent;
+        tx_okay = COMBLK->STATUS & TXTOKAY_MASK;
+    }
+    
+    return size_sent;
+}
+
+/*==============================================================================
+ *
+ */
+static void process_sys_ctrl_command(uint8_t cmd_opcode)
+{
+    if(g_async_event_handler != 0)
+    {
+        g_async_event_handler(cmd_opcode);
+    }
+}
+
diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_sys_services/mss_comblk.h b/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_sys_services/mss_comblk.h
new file mode 100644
index 000000000..7f9ba7f62
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_sys_services/mss_comblk.h
@@ -0,0 +1,87 @@
+/*******************************************************************************
+ * (c) Copyright 2012 Microsemi SoC Products Group.  All rights reserved.
+ *
+ * SmartFusion2 COMBLK access functions.
+ *
+ * SVN $Revision: 5160 $
+ * SVN $Date: 2013-03-14 14:50:49 +0000 (Thu, 14 Mar 2013) $
+ */
+#ifndef __MSS_COMBLK_H_
+#define __MSS_COMBLK_H_ 1
+
+#include "../../CMSIS/m2sxxx.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*------------------------------------------------------------------------------
+ *
+ */
+typedef void(*comblk_completion_handler_t)(uint8_t * p_response, uint16_t response_size);
+
+typedef uint32_t (*comblk_page_handler_t)(uint8_t const ** pp_next_page);
+
+typedef void (*comblk_async_event_handler_t)(uint8_t event_opcode);
+
+/*------------------------------------------------------------------------------
+ *
+ */
+void MSS_COMBLK_init(comblk_async_event_handler_t async_event_handler);
+
+/*------------------------------------------------------------------------------
+ *
+ */
+void MSS_COMBLK_send_cmd_with_ptr
+(
+    uint8_t cmd_opcode,
+    uint32_t cmd_params_ptr,
+    uint8_t * p_response,
+    uint16_t response_size,
+    comblk_completion_handler_t completion_handler
+);
+
+/*------------------------------------------------------------------------------
+ *
+ */
+void MSS_COMBLK_send_cmd
+(
+    const uint8_t * p_cmd,
+    uint16_t cmd_size,
+    const uint8_t * p_data,
+    uint32_t data_size,
+    uint8_t * p_response,
+    uint16_t response_size,
+    comblk_completion_handler_t completion_handler
+);
+
+/*------------------------------------------------------------------------------
+ *
+ */
+void MSS_COMBLK_read
+(
+    const uint8_t * p_data,
+    uint16_t cmd_size,
+    uint8_t * p_response,
+    uint16_t response_size,
+    comblk_completion_handler_t completion_handler
+);
+
+/*------------------------------------------------------------------------------
+ *
+ */
+void MSS_COMBLK_send_paged_cmd
+(
+    const uint8_t * p_cmd,
+    uint16_t cmd_size,
+    uint8_t * p_response,
+    uint16_t response_size,
+    uint32_t (*)(uint8_t const **),
+    void (*completion_handler)(uint8_t *, uint16_t)
+);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MSS_COMBLK_H_ */
diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_sys_services/mss_sys_services.c b/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_sys_services/mss_sys_services.c
new file mode 100644
index 000000000..e7453b51f
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_sys_services/mss_sys_services.c
@@ -0,0 +1,813 @@
+/*******************************************************************************
+ * (c) Copyright 2012 Microsemi SoC Products Group.  All rights reserved.
+ *
+ * SmartFusion2 system services.
+ *
+ * SVN $Revision: 5615 $
+ * SVN $Date: 2013-04-05 14:48:10 +0100 (Fri, 05 Apr 2013) $
+ */
+#include "mss_sys_services.h"
+#include "mss_comblk.h"
+#include "../../CMSIS/mss_assert.h"
+#include <string.h>
+
+/*==============================================================================
+ *
+ */
+/*
+ * Service request command opcodes:
+ */
+#define DEVICE_CERTIFICATE_REQUEST_CMD      0u
+#define SERIAL_NUMBER_REQUEST_CMD           1u
+#define FLASH_FREEZE_REQUEST_CMD            2u
+#define AES128_REQUEST_CMD                  3u
+#define USERCODE_REQUEST_CMD                4u
+#define DESIGNVER_REQUEST_CMD               5u
+#define AES256_REQUEST_CMD                  6u
+#define KEYTREE_REQUEST_CMD                 9u
+#define SHA256_REQUEST_CMD                  10u
+#define HMAC_REQUEST_CMD                    12u
+#define PPUF_CHALLENGE_RESP_REQUEST_CMD     14u
+#define ISP_PROGRAMMING_REQUEST_CMD         21u
+#define DIGEST_CHECK_REQUEST_CMD            23u
+#define NRBG_SELF_TEST_REQUEST_CMD          40u
+#define NRBG_INSTANTIATE_REQUEST_CMD        41u
+#define NRBG_GENERATE_REQUEST_CMD           42u
+#define NRBG_RESEED_REQUEST_CMD             43u
+#define NRBG_UNINSTANTIATE_REQUEST_CMD      44u
+#define NRBG_RESET_REQUEST_CMD              45u
+#define FLASHFREEZE_SHUTDOWN_CMD            224u
+#define ZEROIZATION_REQUEST_CMD             240u
+
+#define POWER_ON_RESET_DIGEST_ERROR_CMD     241u
+
+/*
+ * System Services requests length:
+ */
+#define FLASH_FREEZE_REQUEST_LENGTH         2u
+
+/*
+ * Service response lengths:
+ */
+#define STANDARD_SERV_RESP_LENGTH           6u
+
+#define SERIAL_NUMBER_SERV_RESP_LENGTH      6u
+#define USERCODE_SERV_RESP_LENGTH           6u
+#define DESIGNVER_SERV_RESP_LENGTH          6u
+#define DEVICE_CERT_SERV_RESP_LENGTH        6u
+#define ISP_PROG_SERV_RESP_LENGTH           2u
+#define NRBG_RESET_SERV_RESP_LENGTH         2u
+#define NRBG_SELF_TEST_SERV_RESP_LENGTH     2u
+#define NRBG_UNINST_SERV_RESP_LENGTH        3u
+
+#define DIGEST_CHECK_SERV_RESP_LENGTH       2u
+#define FLASH_FREEZE_SERV_RESP_LENGTH       2u
+
+/*
+ * Non Deterministic Random Bit Generator defines:
+ */
+#define INVALID_NRBG_HANDLE     0xFFu
+
+/*
+ * RTC_WAKEUP_CR system register bit masks:
+ */
+#define RTC_WAKEUP_G4C_EN_MASK      0x00000004u
+#define RTC_WAKEUP_FAB_EN_MASK      0x00000002u
+
+/*==============================================================================
+ * Local functions.
+ */
+static void request_completion_handler(uint8_t * p_response, uint16_t response_size);
+static void signal_request_start(void);
+static uint16_t wait_for_request_completion(void);
+static uint8_t execute_service
+(
+    uint8_t cmd_opcode,
+    uint8_t * cmd_params_ptr,
+    uint8_t * response,
+    uint16_t response_length
+);
+
+static void asynchronous_event_handler(uint8_t event_opcode);
+
+static void write_ptr_value_into_array
+(
+    const uint8_t * pointer,
+    uint8_t target_array[],
+    uint32_t array_index
+);
+
+/*==============================================================================
+ * Global variables
+ */
+static volatile uint8_t g_request_in_progress = 0u;
+static volatile uint16_t g_last_response_length = 0u;
+static sys_serv_async_event_handler_t g_event_handler = 0;
+
+/*==============================================================================
+ *
+ */
+void MSS_SYS_init(sys_serv_async_event_handler_t event_handler)
+{
+    MSS_COMBLK_init(asynchronous_event_handler);
+    
+    g_event_handler = event_handler;
+    
+    g_request_in_progress = 0u;
+    g_last_response_length = 0u;
+}
+
+/*==============================================================================
+ *
+ */
+static void asynchronous_event_handler(uint8_t event_opcode)
+{
+    if(g_event_handler != 0)
+    {
+    switch(event_opcode)
+        {
+            case FLASH_FREEZE_SHUTDOWN_OPCODE:
+            case FLASH_FREEZE_EXIT_OPCODE:
+                g_event_handler(event_opcode);
+            break;
+            
+            default:
+                /* Ignore all other events. */
+            break;
+        }
+    }
+}
+
+/*==============================================================================
+ * See mss_sys_services.h for details.
+ */
+uint8_t MSS_SYS_get_serial_number
+(
+    uint8_t * p_serial_number
+)
+{
+    uint8_t response[SERIAL_NUMBER_SERV_RESP_LENGTH];
+    uint8_t status;
+    
+    status = execute_service(SERIAL_NUMBER_REQUEST_CMD,
+                             p_serial_number,
+                             response,
+                             SERIAL_NUMBER_SERV_RESP_LENGTH);
+    
+    return status;
+}
+
+/*==============================================================================
+ * See mss_sys_services.h for details.
+ */
+uint8_t MSS_SYS_get_user_code
+(
+    uint8_t * p_user_code
+)
+{
+    uint8_t response[USERCODE_SERV_RESP_LENGTH];
+    uint8_t status;
+    
+    status = execute_service(USERCODE_REQUEST_CMD,
+                             p_user_code,
+                             response,
+                             USERCODE_SERV_RESP_LENGTH);
+    
+    return status;
+}
+
+/*==============================================================================
+ * See mss_sys_services.h for details.
+ */
+uint8_t MSS_SYS_get_design_version
+(
+    uint8_t * p_design_version
+)
+{
+    uint8_t response[DESIGNVER_SERV_RESP_LENGTH];
+    uint8_t status;
+    
+    status = execute_service(DESIGNVER_REQUEST_CMD,
+                             p_design_version,
+                             response,
+                             DESIGNVER_SERV_RESP_LENGTH);
+    
+    return status;
+}
+
+/*==============================================================================
+ * See mss_sys_services.h for details.
+ */
+uint8_t MSS_SYS_get_device_certificate
+(
+    uint8_t * p_device_certificate
+)
+{
+    uint8_t response[DEVICE_CERT_SERV_RESP_LENGTH];
+    uint8_t status;
+    
+    status = execute_service(DEVICE_CERTIFICATE_REQUEST_CMD,
+                             p_device_certificate,
+                             response,
+                             DEVICE_CERT_SERV_RESP_LENGTH);
+    
+    return status;
+}
+
+/*==============================================================================
+ * See mss_sys_services.h for details.
+ */
+uint8_t MSS_SYS_flash_freeze(uint8_t options)
+{
+    uint8_t status;
+    uint16_t actual_response_length;
+    uint8_t flash_freeze_req[FLASH_FREEZE_REQUEST_LENGTH];
+    uint8_t response[FLASH_FREEZE_SERV_RESP_LENGTH];
+
+    /*
+     * The Flash Freeze system service is not available on M2S050 rev A and rev B.
+     */
+    ASSERT(0x0000F802u != SYSREG->DEVICE_VERSION);
+    ASSERT(0x0001F802u != SYSREG->DEVICE_VERSION);
+    
+    /*
+     * Enable RTC wake-up interrupt to System Controller and FPGA fabric.
+     */
+    SYSREG->RTC_WAKEUP_CR |= (RTC_WAKEUP_G4C_EN_MASK | RTC_WAKEUP_FAB_EN_MASK);
+
+    signal_request_start();
+
+    flash_freeze_req[0] = FLASH_FREEZE_REQUEST_CMD;
+    flash_freeze_req[1] = options;
+
+    MSS_COMBLK_send_cmd(flash_freeze_req,               /* p_cmd */
+                        FLASH_FREEZE_REQUEST_LENGTH,    /* cmd_size */
+                        0,                              /* p_data */
+                        0u,                             /* data_size */
+                        response,                       /* p_response */
+                        FLASH_FREEZE_SERV_RESP_LENGTH,  /* response_size */
+                        request_completion_handler);    /* completion_handler */
+
+    actual_response_length = wait_for_request_completion();
+    
+    if((FLASH_FREEZE_SERV_RESP_LENGTH == actual_response_length) &&
+       (FLASH_FREEZE_REQUEST_CMD == response[0]))
+    {
+        status = response[1];
+    }
+    else
+    {
+        status = MSS_SYS_UNEXPECTED_ERROR;
+    }
+    
+    return status;
+}
+
+/*==============================================================================
+ * See mss_sys_services.h for details.
+ */
+#define AES128_KEY_LENGTH   16u
+#define IV_LENGTH           16u
+
+#define AES256_KEY_LENGTH   32u
+
+#define HMAC_KEY_LENGTH     32u
+
+uint8_t MSS_SYS_128bit_aes
+(
+    const uint8_t * key,
+    const uint8_t * iv,
+    uint16_t nb_blocks,
+    uint8_t mode,
+    uint8_t * dest_addr,
+    const uint8_t * src_addr)
+{
+    uint8_t response[STANDARD_SERV_RESP_LENGTH];
+    uint8_t params[44];
+    uint8_t status;
+    
+    memcpy(&params[0], key, AES128_KEY_LENGTH);
+    memcpy(&params[16], iv, IV_LENGTH);
+    
+    params[32] = (uint8_t)nb_blocks;
+    params[33] = (uint8_t)(nb_blocks >> 8u);
+    params[34] = mode;
+    params[35] = 0u;
+#if 1
+    write_ptr_value_into_array(dest_addr, params, 36u);
+    write_ptr_value_into_array(src_addr, params, 40u);
+#else    
+    params[36] = (uint8_t)((uint32_t)dest_addr);
+    params[37] = (uint8_t)((uint32_t)dest_addr >> 8u);
+    params[38] = (uint8_t)((uint32_t)dest_addr >> 16u);
+    params[39] = (uint8_t)((uint32_t)dest_addr >> 24u);
+
+    params[40] = (uint8_t)((uint32_t)src_addr);
+    params[41] = (uint8_t)((uint32_t)src_addr >> 8u);
+    params[42] = (uint8_t)((uint32_t)src_addr >> 16u);
+    params[43] = (uint8_t)((uint32_t)src_addr >> 24u);
+#endif
+    status = execute_service(AES128_REQUEST_CMD,
+                             params,
+                             response,
+                             STANDARD_SERV_RESP_LENGTH);
+                             
+    return status;
+}
+
+/*==============================================================================
+ * See mss_sys_services.h for details.
+ */
+uint8_t MSS_SYS_256bit_aes
+( 
+    const uint8_t * key,
+    const uint8_t * iv,
+    uint16_t nb_blocks,
+    uint8_t mode,
+    uint8_t * dest_addr,
+    const uint8_t * src_addr
+)
+{
+    uint8_t response[STANDARD_SERV_RESP_LENGTH];
+    uint8_t params[60];
+    uint8_t status;
+    
+    memcpy(&params[0], key, AES256_KEY_LENGTH);
+    memcpy(&params[32], iv, IV_LENGTH);
+    
+    params[48] = (uint8_t)nb_blocks;
+    params[49] = (uint8_t)(nb_blocks >> 8u);
+    params[50] = mode;
+    params[51] = 0u;
+#if 1
+    write_ptr_value_into_array(dest_addr, params, 52u);
+    write_ptr_value_into_array(src_addr, params, 56u);
+#else    
+    params[52] = (uint8_t)((uint32_t)dest_addr);
+    params[53] = (uint8_t)((uint32_t)dest_addr >> 8u);
+    params[54] = (uint8_t)((uint32_t)dest_addr >> 16u);
+    params[55] = (uint8_t)((uint32_t)dest_addr >> 24u);
+
+    params[56] = (uint8_t)((uint32_t)src_addr);
+    params[57] = (uint8_t)((uint32_t)src_addr >> 8u);
+    params[58] = (uint8_t)((uint32_t)src_addr >> 16u);
+    params[59] = (uint8_t)((uint32_t)src_addr >> 24u);
+#endif
+    status = execute_service(AES256_REQUEST_CMD,
+                             params,
+                             response,
+                             STANDARD_SERV_RESP_LENGTH);
+                             
+    return status;
+}
+
+/*==============================================================================
+ * See mss_sys_services.h for details.
+ */
+uint8_t MSS_SYS_sha256
+(
+    const uint8_t * p_data_in,
+    uint32_t length,
+    uint8_t * result
+)
+{
+    uint8_t response[STANDARD_SERV_RESP_LENGTH];
+    uint8_t params[12];
+    uint8_t status;
+    
+    params[0] = (uint8_t)((uint32_t)length);
+    params[1] = (uint8_t)((uint32_t)length >> 8u);
+    params[2] = (uint8_t)((uint32_t)length >> 16u);
+    params[3] = (uint8_t)((uint32_t)length >> 24u);
+    
+#if 1
+    write_ptr_value_into_array(result, params, 4u);
+    write_ptr_value_into_array(p_data_in, params, 8u);
+#else
+    params[4] = (uint8_t)((uint32_t)result);
+    params[5] = (uint8_t)((uint32_t)result >> 8u);
+    params[6] = (uint8_t)((uint32_t)result >> 16u);
+    params[7] = (uint8_t)((uint32_t)result >> 24u);
+
+    params[8] = (uint8_t)((uint32_t)p_data_in);
+    params[9] = (uint8_t)((uint32_t)p_data_in >> 8u);
+    params[10] = (uint8_t)((uint32_t)p_data_in >> 16u);
+    params[11] = (uint8_t)((uint32_t)p_data_in >> 24u);
+#endif
+    status = execute_service(SHA256_REQUEST_CMD,
+                             params,
+                             response,
+                             STANDARD_SERV_RESP_LENGTH);
+                             
+    return status;
+}
+
+/*==============================================================================
+ * See mss_sys_services.h for details.
+ */
+uint8_t MSS_SYS_hmac
+(
+    const uint8_t * key,
+    const uint8_t * p_data_in,
+    uint32_t length,
+    uint8_t * p_result
+)
+{
+    uint8_t response[STANDARD_SERV_RESP_LENGTH];
+    uint8_t params[58];
+    uint8_t status;
+    
+    memcpy(&params[0], key, HMAC_KEY_LENGTH);
+    
+    params[32] = (uint8_t)((uint32_t)length);
+    params[33] = (uint8_t)((uint32_t)length >> 8u);
+    params[34] = (uint8_t)((uint32_t)length >> 16u);
+    params[35] = (uint8_t)((uint32_t)length >> 24u);
+#if 1
+    write_ptr_value_into_array(p_data_in, params, 36u);
+    write_ptr_value_into_array(p_result, params, 40u);
+#else    
+    params[36] = (uint8_t)((uint32_t)p_data_in);
+    params[37] = (uint8_t)((uint32_t)p_data_in >> 8u);
+    params[38] = (uint8_t)((uint32_t)p_data_in >> 16u);
+    params[39] = (uint8_t)((uint32_t)p_data_in >> 24u);
+
+    params[40] = (uint8_t)((uint32_t)p_result);
+    params[41] = (uint8_t)((uint32_t)p_result >> 8u);
+    params[42] = (uint8_t)((uint32_t)p_result >> 16u);
+    params[43] = (uint8_t)((uint32_t)p_result >> 24u);
+#endif
+    status = execute_service(HMAC_REQUEST_CMD,
+                             params,
+                             response,
+                             STANDARD_SERV_RESP_LENGTH);
+                             
+    return status;
+}
+
+/*==============================================================================
+ * See mss_sys_services.h for details.
+ */
+uint8_t MSS_SYS_nrbg_self_test(void)
+{
+    uint8_t status;
+    uint16_t actual_response_length;
+    uint8_t self_test;
+    uint8_t response[NRBG_SELF_TEST_SERV_RESP_LENGTH];
+    
+    signal_request_start();
+    
+    self_test = NRBG_SELF_TEST_REQUEST_CMD;
+
+    MSS_COMBLK_send_cmd(&self_test,                         /* p_cmd */
+                        sizeof(self_test),                  /* cmd_size */
+                        0,                                  /* p_data */
+                        0,                                  /* data_size */
+                        response,                           /* p_response */
+                        NRBG_SELF_TEST_SERV_RESP_LENGTH,    /* response_size */
+                        request_completion_handler);        /* completion_handler */
+    
+    actual_response_length = wait_for_request_completion();
+    
+    if((NRBG_SELF_TEST_SERV_RESP_LENGTH == actual_response_length) &&
+       (NRBG_SELF_TEST_REQUEST_CMD == response[0]))
+    {
+        status = response[1];
+    }
+    else
+    {
+        status = MSS_SYS_UNEXPECTED_ERROR;
+    }
+    
+    return status;
+}
+
+/*==============================================================================
+ * See mss_sys_services.h for details.
+ */
+uint8_t MSS_SYS_nrbg_instantiate
+(
+    const uint8_t * personalization_str,
+    uint16_t personalization_str_length,
+    uint8_t * p_nrbg_handle
+)
+{
+    uint8_t response[STANDARD_SERV_RESP_LENGTH];
+    uint8_t intantiate_params[7];
+    uint8_t status;
+#if 1
+    write_ptr_value_into_array(personalization_str, intantiate_params, 0u);
+#else    
+    intantiate_params[0] = (uint8_t)((uint32_t)personalization_str);
+    intantiate_params[1] = (uint8_t)((uint32_t)personalization_str >> 8u);
+    intantiate_params[2] = (uint8_t)((uint32_t)personalization_str >> 16u);
+    intantiate_params[3] = (uint8_t)((uint32_t)personalization_str >> 24u);
+#endif
+    intantiate_params[4] = (uint8_t)personalization_str_length;
+    intantiate_params[5] = (uint8_t)(personalization_str_length >> 8u);
+    intantiate_params[6] = INVALID_NRBG_HANDLE;
+    
+    status = execute_service(NRBG_INSTANTIATE_REQUEST_CMD,
+                             intantiate_params,
+                             response,
+                             STANDARD_SERV_RESP_LENGTH);
+                             
+    if(MSS_SYS_SUCCESS == status)
+    {
+        *p_nrbg_handle = intantiate_params[6];
+    }
+    
+    return status;
+}
+
+/*==============================================================================
+ * See mss_sys_services.h for details.
+ */
+uint8_t MSS_SYS_nrbg_generate
+(
+    const uint8_t * p_requested_data,
+    const uint8_t * p_additional_input,
+    uint8_t requested_length,
+    uint8_t additional_input_length,
+    uint8_t pr_req,
+    uint8_t nrbg_handle
+)
+{
+    uint8_t response[STANDARD_SERV_RESP_LENGTH];
+    uint8_t generate_params[12];
+    uint8_t status;
+#if 1
+    write_ptr_value_into_array(p_requested_data, generate_params, 0u);
+    write_ptr_value_into_array(p_additional_input, generate_params, 4u);
+#else
+    generate_params[0] = (uint8_t)((uint32_t)p_requested_data);
+    generate_params[1] = (uint8_t)((uint32_t)p_requested_data >> 8u);
+    generate_params[2] = (uint8_t)((uint32_t)p_requested_data >> 16u);
+    generate_params[3] = (uint8_t)((uint32_t)p_requested_data >> 24u);
+    generate_params[4] = (uint8_t)((uint32_t)p_additional_input);
+    generate_params[5] = (uint8_t)((uint32_t)p_additional_input >> 8u);
+    generate_params[6] = (uint8_t)((uint32_t)p_additional_input >> 16u);
+    generate_params[7] = (uint8_t)((uint32_t)p_additional_input >> 24u);
+#endif
+    generate_params[8] = requested_length;
+    generate_params[9] = additional_input_length;
+    generate_params[10] = pr_req;
+    generate_params[11] = nrbg_handle;
+    
+    status = execute_service(NRBG_GENERATE_REQUEST_CMD,
+                             generate_params,
+                             response,
+                             STANDARD_SERV_RESP_LENGTH);
+    
+    return status;
+}
+
+/*==============================================================================
+ * See mss_sys_services.h for details.
+ */
+uint8_t MSS_SYS_nrbg_reseed
+(
+    const uint8_t * p_additional_input,
+    uint8_t additional_input_length,
+    uint8_t nrbg_handle
+)
+{
+    uint8_t response[STANDARD_SERV_RESP_LENGTH];
+    uint8_t params[6];
+    uint8_t status;
+#if 1
+    write_ptr_value_into_array(p_additional_input, params, 0u);
+#else
+    params[0] = (uint8_t)((uint32_t)p_additional_input);
+    params[1] = (uint8_t)((uint32_t)p_additional_input >> 8u);
+    params[2] = (uint8_t)((uint32_t)p_additional_input >> 16u);
+    params[3] = (uint8_t)((uint32_t)p_additional_input >> 24u);
+#endif
+    params[4] = (uint8_t)additional_input_length;
+    params[5] = nrbg_handle;
+    
+    status = execute_service(NRBG_RESEED_REQUEST_CMD,
+                             params,
+                             response,
+                             STANDARD_SERV_RESP_LENGTH);
+    
+    return status;
+}
+
+/*==============================================================================
+ * See mss_sys_services.h for details.
+ */
+uint8_t MSS_SYS_nrbg_uninstantiate
+(
+    uint8_t nrbg_handle
+)
+{
+    uint8_t status;
+    uint16_t actual_response_length;
+    uint8_t uninstantiate_req[2];
+    uint8_t response[NRBG_UNINST_SERV_RESP_LENGTH];
+    
+    signal_request_start();
+    
+    uninstantiate_req[0] = NRBG_UNINSTANTIATE_REQUEST_CMD;
+    uninstantiate_req[1] = nrbg_handle;
+
+    MSS_COMBLK_send_cmd(uninstantiate_req,              /* p_cmd */
+                        sizeof(uninstantiate_req),      /* cmd_size */
+                        0,                              /* p_data */
+                        0,                              /* data_size */
+                        response,                       /* p_response */
+                        NRBG_UNINST_SERV_RESP_LENGTH,   /* response_size */
+                        request_completion_handler);    /* completion_handler */
+    
+    actual_response_length = wait_for_request_completion();
+    
+    if((NRBG_UNINST_SERV_RESP_LENGTH == actual_response_length) &&
+       (NRBG_UNINSTANTIATE_REQUEST_CMD == response[0]))
+    {
+        status = response[1];
+    }
+    else
+    {
+        status = MSS_SYS_UNEXPECTED_ERROR;
+    }
+    
+    return status;
+}
+
+/*==============================================================================
+ * See mss_sys_services.h for details.
+ */
+static uint8_t g_isp_response[ISP_PROG_SERV_RESP_LENGTH];
+void (*g_isp_completion_handler)(uint32_t) = 0;
+
+static void isp_sys_completion_handler
+(
+    uint8_t * p_response, 
+    uint16_t length
+)
+{
+    if(g_isp_completion_handler != 0)
+    {
+        g_isp_completion_handler(p_response[1]);
+    }
+}
+
+void MSS_SYS_start_isp
+(
+    uint8_t mode,
+    uint32_t (*page_read_handler)(uint8_t const **),
+    void (*isp_completion_handler)(uint32_t)
+)
+{
+    uint8_t isp_prog_request[2];
+    
+    signal_request_start();
+    
+    isp_prog_request[0] = ISP_PROGRAMMING_REQUEST_CMD;
+    isp_prog_request[1] = mode;
+    
+    g_isp_completion_handler = isp_completion_handler;
+
+    MSS_COMBLK_send_paged_cmd(isp_prog_request,                 /* p_cmd */
+                              sizeof(isp_prog_request),         /* cmd_size */
+                              g_isp_response,                   /* p_response */
+                              ISP_PROG_SERV_RESP_LENGTH, /* response_size */
+                              page_read_handler,                /* page_handler */
+                              isp_sys_completion_handler);      /* completion_handler */
+}
+
+/*==============================================================================
+ * See mss_sys_services.h for details.
+ */
+uint8_t MSS_SYS_check_digest
+(
+    uint8_t options
+)
+{
+    uint8_t status;
+    uint16_t actual_response_length;
+    uint8_t digest_check_req[2];
+    uint8_t response[DIGEST_CHECK_SERV_RESP_LENGTH];
+    
+    signal_request_start();
+    
+    digest_check_req[0] = DIGEST_CHECK_REQUEST_CMD;
+    digest_check_req[1] = options;
+
+    MSS_COMBLK_send_cmd(digest_check_req,               /* p_cmd */
+                        sizeof(digest_check_req),       /* cmd_size */
+                        0,                              /* p_data */
+                        0u,                             /* data_size */
+                        response,                       /* p_response */
+                        DIGEST_CHECK_SERV_RESP_LENGTH,  /* response_size */
+                        request_completion_handler);    /* completion_handler */
+    
+    actual_response_length = wait_for_request_completion();
+    
+    if((DIGEST_CHECK_SERV_RESP_LENGTH == actual_response_length) &&
+       (DIGEST_CHECK_REQUEST_CMD == response[0]))
+    {
+        status = response[1];
+    }
+    else
+    {
+        status = MSS_SYS_UNEXPECTED_ERROR;
+    }
+    
+    return status;
+}
+
+/*==============================================================================
+ *
+ */
+static uint8_t execute_service
+(
+    uint8_t cmd_opcode,
+    uint8_t * cmd_params_ptr,
+    uint8_t * response,
+    uint16_t response_length
+)
+{
+    uint8_t status;
+    uint16_t actual_response_length;
+    
+    signal_request_start();
+    
+    MSS_COMBLK_send_cmd_with_ptr(cmd_opcode,                    /* cmd_opcode */
+                                 (uint32_t)cmd_params_ptr,      /* cmd_params_ptr */
+                                 response,                      /* p_response */
+                                 response_length,               /* response_size */
+                                 request_completion_handler);   /* completion_handler */
+    
+    actual_response_length = wait_for_request_completion();
+    
+    if((response_length == actual_response_length) && (cmd_opcode == response[0]))
+    {
+        status = response[1];
+    }
+    else
+    {
+        status = MSS_SYS_UNEXPECTED_ERROR;
+    }
+    
+    return status;
+}
+
+/*==============================================================================
+ *
+ */
+static void request_completion_handler
+(
+    uint8_t * p_response,
+    uint16_t response_size
+)
+{
+    g_request_in_progress = 0u;
+    g_last_response_length = response_size;
+}
+
+/*==============================================================================
+ *
+ */
+static void signal_request_start(void)
+{
+    /* Wait for current request to complete. */
+    while(g_request_in_progress)
+    {
+        ;
+    }
+    
+    g_request_in_progress = 1u;
+    g_last_response_length = 0u;
+}
+
+/*==============================================================================
+ *
+ */
+static uint16_t wait_for_request_completion(void)
+{
+    while(g_request_in_progress)
+    {
+        ;
+    }
+    
+    return g_last_response_length;
+}
+
+/*==============================================================================
+ *
+ */
+static void write_ptr_value_into_array
+(
+    const uint8_t * pointer,
+    uint8_t target_array[],
+    uint32_t array_index
+)
+{
+    target_array[array_index] = (uint8_t)((uint32_t)pointer);
+    target_array[array_index + 1] = (uint8_t)((uint32_t)pointer >> 8u);
+    target_array[array_index + 2] = (uint8_t)((uint32_t)pointer >> 16u);
+    target_array[array_index + 3] = (uint8_t)((uint32_t)pointer >> 24u);
+}
+
diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_sys_services/mss_sys_services.h b/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_sys_services/mss_sys_services.h
new file mode 100644
index 000000000..c8efcc32a
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_sys_services/mss_sys_services.h
@@ -0,0 +1,883 @@
+/*******************************************************************************
+ * (c) Copyright 2012 Microsemi SoC Products Group.  All rights reserved.
+ *
+ * SmartFusion2 MSS System Services bare metal software driver public API.
+ *
+ * SVN $Revision: 5591 $
+ * SVN $Date: 2013-04-04 15:55:11 +0100 (Thu, 04 Apr 2013) $
+ */
+
+/*=========================================================================*//**
+  @mainpage SmartFusion2 MSS System Services Bare Metal Driver.
+
+  @section intro_sec Introduction
+  The SmartFusion2 microcontroller subsystem (MSS) includes a communication
+  block (COMM_BLK) allowing it to communicate with the SmartFusion2 System
+  Controller. The SmartFusion2 System Controller performs a variety of system
+  wide services. This software driver provides a set of functions to access
+  these System Services. The driver can be adapted for use as part of an
+  operating system, but the implementation of the adaptation layer between the
+  driver and the operating system's driver model is outside the scope of the
+  driver.
+  
+  @section hw_dependencies Hardware Flow Dependencies
+  The MSS System Services driver does not require any configuration. It relies
+  on the SmartFusion2 communication block (MSS_COMM_BLK) to communicate with the
+  System Controller. The MSS_COMM_BLK is always enabled.
+  The base address, register addresses and interrupt number assignment for the
+  MSS_COMM_BLK are defined as constants in the SmartFusion2 CMSIS HAL. You must
+  ensure that the latest SmartFusion2 CMSIS HAL is included in the project
+  settings of the software tool chain used to build your project and that it is
+  generated into your project.
+  
+  @section theory_op Theory of Operation
+  The System Services driver provides access to the SmartFusion2 System
+  Controller services. These system services are loosely grouped into the
+  following features:
+    - Reading system information
+    - Cryptography
+    - Non-deterministic random bit generator
+    - Flash*Freeze
+  Note: Refer to the function descriptions for further details about the
+        features of each individual service.
+
+  Reading System Information
+  The System Services driver can be used to read information about the
+  SmartFusion2 device and the design programmed into it using the following
+  functions:
+    - MSS_SYS_get_serial_number()
+    - MSS_SYS_get_user_code()
+    - MSS_SYS_get_design_version()
+    - MSS_SYS_get_device_certificate()
+    
+  Cryptography Services
+  The System Services driver provides cryptographic services using the following
+  functions:
+    - MSS_SYS_128bit_aes()
+    - MSS_SYS_256bit_aes()
+    - MSS_SYS_sha256()
+    - MSS_SYS_hmac()
+    
+  Non-Deterministic Random Bit Generator
+  The System Services driver provides random number generation services using
+  the following functions:
+    - MSS_SYS_nrbg_instantiate()
+    - MSS_SYS_nrbg_self_test()
+    - MSS_SYS_nrbg_generate()
+    - MSS_SYS_nrbg_reseed()
+    - MSS_SYS_nrbg_uninstantiate()
+    
+  Flash*Freeze
+  The System Services driver can be used to request the system to enter
+  Flash*Freeze mode using the following function:
+    - MSS_SYS_flash_freeze()
+    
+ *//*=========================================================================*/
+
+#ifndef __MSS_SYS_SERVICES_H_
+#define __MSS_SYS_SERVICES_H_ 1
+
+#include "../../CMSIS/m2sxxx.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*==============================================================================
+ * Status codes:
+ */
+/*-------------------------------------------------------------------------*//**
+  These constants are used by multiple services to communicate the outcome of a
+  system services request. These status codes are used across all types of
+  services.
+  
+  - MSS_SYS_SUCCESS:
+      Indicates that the system services completed successfully. 
+      
+  - MSS_SYS_UNEXPECTED_ERROR:
+      Indicates that the system failed in an unexpected way.
+      
+  - MSS_SYS_MEM_ACCESS_ERROR:
+      Indicates that the System Controller could not access the memory used to
+      pass parameters to the System Controller or to return a service result to
+      the Cortex-M3.
+      
+  - MSS_SYS_SERVICE_DISABLED_BY_FACTORY:
+      Indicates that the requested system service is not available on the
+      SmartFusion2 device.
+      
+  - MSS_SYS_SERVICE_DISABLED_BY_USER:
+      Indicates that the requested system service has been disabled as part of
+      the hardware design.
+ */
+#define MSS_SYS_SUCCESS                         0u
+#define MSS_SYS_UNEXPECTED_ERROR                200u
+
+#define MSS_SYS_MEM_ACCESS_ERROR                127u
+#define MSS_SYS_SERVICE_DISABLED_BY_FACTORY     254u
+#define MSS_SYS_SERVICE_DISABLED_BY_USER        255u
+
+/*-------------------------------------------------------------------------*//**
+ * Programming services specific status codes:
+ */
+#define MSS_SYS_CHAINING_MISMATCH                   1u
+#define MSS_SYS_UNEXPECTED_DATA_RECEIVED            2u
+#define MSS_SYS_INVALID_ENCRYPTION_KEY              3u
+#define MSS_SYS_INVALID_COMPONENT_HEADER            4u
+#define MSS_SYS_BACK_LEVEL_NOT_SATISFIED            5u
+#define MSS_SYS_DSN_BINDING_MISMATCH                7u
+#define MSS_SYS_ILLEGAL_COMPONENT_SEQUENCE          8u
+#define MSS_SYS_INSUFFICIENT_DEV_CAPABILITIES       9u
+#define MSS_SYS_INCORRECT_DEVICE_ID                 10u
+#define MSS_SYS_UNSUPPORTED_BITSTREAM_PROT_VER      11u
+#define MSS_SYS_VERIFY_NOT_PERMITTED_ON_BITSTR      12u
+#define MSS_SYS_ABORT                               127u
+#define MSS_SYS_NVM_VERIFY_FAILED                   129u
+#define MSS_SYS_DEVICE_SECURITY_PROTECTED           130u
+#define MSS_SYS_PROGRAMMING_MODE_NOT_ENABLED        131u
+
+/*-------------------------------------------------------------------------*//**
+  These constants are used to specify the event_opcode parameter for the
+  event_handler() function registered with the MSS_SYS_init() function. They are
+  used to specify which asynchronous event is notified to the Cortex-M3 software
+  by the System Controller. Asynchronous events are sent by the System
+  Controller to the Cortex-M3 when some system events of interest occur.
+  
+  - FLASH_FREEZE_SHUTDOWN_OPCODE:
+      Indicates that the system is being shutdown as a result of entering the
+      Flash*Freeze mode.
+      
+  - FLASH_FREEZE_EXIT_OPCODE:
+      Indicates that the system is exiting Flash*Freeze mode.
+ */
+#define FLASH_FREEZE_SHUTDOWN_OPCODE    0xE0u
+#define FLASH_FREEZE_EXIT_OPCODE        0xE1u
+
+/*-------------------------------------------------------------------------*//**
+  These constants are used to specify the options parameter for the
+  MSS_SYS_flash_freeze() function.
+  
+  - MSS_SYS_FPGA_POWER_DOWN:
+      Indicates that the MSS_SYS_flash_freeze() function should request the FPGA
+      fabric to enter Flash*Freeze mode.
+      
+  - MSS_SYS_ENVM0_POWER_DOWN:
+      Indicates that the MSS_SYS_flash_freeze() function should request eNVM0 to
+      enter Flash*Freeze mode.
+      
+  - MSS_SYS_ENVM1_POWER_DOWN:
+      Indicates that the MSS_SYS_flash_freeze() function should request eNVM1 to
+      enter Flash*Freeze mode.
+      
+  - MSS_SYS_MPLL_POWER_DOWN:
+      Indicates that the MSS_SYS_flash_freeze() function should request the MSS
+      PLL to enter Flash*Freeze mode.
+ */
+#define MSS_SYS_FPGA_POWER_DOWN     0x00u
+#define MSS_SYS_ENVM0_POWER_DOWN    0x01u
+#define MSS_SYS_ENVM1_POWER_DOWN    0x02u
+#define MSS_SYS_MPLL_POWER_DOWN     0x04u
+
+/*-------------------------------------------------------------------------*//**
+  These constants are used to specify the mode parameter for the
+  MSS_SYS_128aes() and MSS_SYS_256bit_aes() functions.
+  
+  - MSS_SYS_ECB_ENCRYPT:
+      Indicates that the cryptography function should perform encryption using
+      the Electronic Codebook (ECB) mode.
+      
+  - MSS_SYS_ECB_DECRYPT:
+      Indicates that the cryptography function should perform decryption using
+      the Electronic Codebook (ECB) mode.
+      
+  - MSS_SYS_CBC_ENCRYPT:
+      Indicates that the cryptography function should perform encryption using
+      the Cipher-Block Chaining (CBC) mode.
+      
+  - MSS_SYS_CBC_DECRYPT:
+      Indicates that the cryptography function should perform decryption using
+      the Cipher-Block Chaining (CBC) mode.
+      
+  - MSS_SYS_OFB_ENCRYPT:
+      Indicates that the cryptography function should perform encryption using
+      the Output Feedback (OFB) mode.
+      
+  - MSS_SYS_OFB_DECRYPT:
+      Indicates that the cryptography function should perform decryption using
+      the Output Feedback (OFB) mode.
+      
+  - MSS_SYS_CTR_ENCRYPT:
+      Indicates that the cryptography function should perform encryption using
+      the Counter (CTR) mode.
+      
+  - MSS_SYS_CTR_DECRYPT:
+      Indicates that the cryptography function should perform decryption using
+      the Counter (CTR) mode.
+ */
+#define MSS_SYS_ECB_ENCRYPT     0x00u
+#define MSS_SYS_ECB_DECRYPT     0x80u
+#define MSS_SYS_CBC_ENCRYPT     0x01u
+#define MSS_SYS_CBC_DECRYPT     0x81u
+#define MSS_SYS_OFB_ENCRYPT     0x02u
+#define MSS_SYS_OFB_DECRYPT     0x82u
+#define MSS_SYS_CTR_ENCRYPT     0x03u
+#define MSS_SYS_CTR_DECRYPT     0x83u
+
+/*------------------------------------------------------------------------------
+  These constants are used by non deterministic random bit generator (NDRBG)
+  services to communicate the outcome of a system services request. These status
+  codes are only used by NDRBG services.
+  
+  - MSS_SYS_NRBG_CATASTROPHIC_ERROR:
+      Indicates that a catastrophic error occurred. 
+      
+  - MSS_SYS_NRBG_MAX_INST_EXCEEDED:
+      Indicates that the maximum number of NDRBG instances has been exceeded.
+      You need to release already instantiated NDRBG instances using the
+      MSS_SYS_ndrbg_uninstantiate() function.
+      
+  - MSS_SYS_NRBG_INVALID_HANDLE:
+      Indicates that the handle parameter has an invalid value.
+      
+  - MSS_SYS_NRBG_GEN_REQ_TOO_BIG:
+      Indicates that the requested random number is too long. The requested
+      length is larger than the maximum number of digits that can be generated.
+      
+  - MSS_SYS_NRBG_MAX_LENGTH_EXCEEDED:
+      Indicates that the supplied additional data length is exceeded.
+ */
+#define MSS_SYS_NRBG_CATASTROPHIC_ERROR     1u
+#define MSS_SYS_NRBG_MAX_INST_EXCEEDED      2u
+#define MSS_SYS_NRBG_INVALID_HANDLE         3u
+#define MSS_SYS_NRBG_GEN_REQ_TOO_BIG        4u
+#define MSS_SYS_NRBG_MAX_LENGTH_EXCEEDED    5u
+
+
+/*-------------------------------------------------------------------------*//**
+  The sys_serv_async_event_handler_t typedef specifies the function prototype of
+  an asynchronous event handler that can be registered with the System Services
+  driver to handle asynchronous events. This is the prototype of a function can
+  be optionally implemented by the application to handle asynchronous events
+  such as Flash*Freeze shutdown and Flash*Freeze exit.
+ */
+typedef void (*sys_serv_async_event_handler_t)(uint8_t event_opcode);
+ 
+/*-------------------------------------------------------------------------*//**
+  This constant is used as parameter to the MSS_SYS_init() function to indicate
+  that the application code does not supply an asynchronous event handler
+  function.
+ */
+#define MSS_SYS_NO_EVENT_HANDLER    ((sys_serv_async_event_handler_t)0)
+
+/*-------------------------------------------------------------------------*//**
+  The MSS_SYS_init function initializes the system services communication with
+  the System Controller.
+   
+  @param
+    The event_handler parameter specifies an optional asynchronous event
+    handler function. This event handler function is provided by the
+    application. It will be called by the System Services driver whenever an
+    asynchronous event is received from the SmartFusion2 System controller.
+    This event handler is typically used to handle entry and exit of
+    Flash*Freeze mode.
+    
+  @return
+    This function does not return a value.
+ */
+void MSS_SYS_init(sys_serv_async_event_handler_t event_handler);
+
+/*==============================================================================
+ * Device and Design Information Services.
+ */
+ 
+/*-------------------------------------------------------------------------*//**
+  The MSS_SYS_get_serial_number function fetches the 128-bit Device Serial
+  Number (DSN).
+  
+  @param p_serial_number
+    The p_serial_number parameter is a pointer to the 16-bytes buffer where the
+    serial number will be written by this system service.
+  
+  @return
+    The MSS_SYS_get_serial_number function returns one of following status codes:
+        - MSS_SYS_SUCCESS
+        - MSS_SYS_MEM_ACCESS_ERROR
+        - MSS_SYS_UNEXPECTED_ERROR
+ */
+uint8_t MSS_SYS_get_serial_number
+(
+    uint8_t * p_serial_number
+);
+
+/*-------------------------------------------------------------------------*//**
+   The MSS_SYS_get_user_code functions fetches the 32-bit USERCODE.
+  
+  @param p_user_code
+    The p_user_code parameter is a pointer to the 4-bytes buffer where the
+    USERCODE will be written by this system service.
+  
+  @return
+    The MSS_SYS_get_user_code function returns one of following status codes:
+        - MSS_SYS_SUCCESS
+        - MSS_SYS_MEM_ACCESS_ERROR
+        - MSS_SYS_UNEXPECTED_ERROR
+ */
+uint8_t MSS_SYS_get_user_code
+(
+    uint8_t * p_user_code
+);
+
+/*-------------------------------------------------------------------------*//**
+  The MSS_SYS_get_design_version function fetches the design version.
+  
+  @param p_design_version
+    The p_design_version parameter is a pointer to the 2-bytes buffer where the
+    design version will be written by this system service.
+  
+  @return
+    The MSS_SYS_get_design_version function returns one of following status codes:
+        - MSS_SYS_SUCCESS
+        - MSS_SYS_MEM_ACCESS_ERROR
+        - MSS_SYS_UNEXPECTED_ERROR
+ */
+uint8_t MSS_SYS_get_design_version
+(
+    uint8_t * p_design_version
+);
+
+/*-------------------------------------------------------------------------*//**
+  The MSS_SYS_get_device_certificate function fetches the device certificate.
+  
+  @param p_device_certificate
+    The p_device_certificate parameter is a pointer to the 512-bytes buffer
+    where the device certificate will be written by this system service.
+  
+  @return
+    The MSS_SYS_get_device_certificate function returns one of following status
+    codes:
+        - MSS_SYS_SUCCESS
+        - MSS_SYS_MEM_ACCESS_ERROR
+        - MSS_SYS_UNEXPECTED_ERROR
+ */
+uint8_t MSS_SYS_get_device_certificate
+(
+    uint8_t * p_device_certificate
+);
+
+/*-------------------------------------------------------------------------*//**
+  The MSS_SYS_flash_freeze function requests the FPGA to enter the Flash*Freeze
+  mode.
+  
+  @param options
+    The options parameter can be used to power down additional parts of
+    SmartFusion2 when the FPGA fabric enters Flash*Freeze mode. This parameter
+    is a bit mask of the following options:
+        - MSS_SYS_FPGA_POWER_DOWN
+        - MSS_SYS_ENVM0_POWER_DOWN
+        - MSS_SYS_ENVM1_POWER_DOWN
+        - MSS_SYS_MPLL_POWER_DOWN
+    MSS_SYS_FPGA_POWER_DOWN on its own will only power down the FPGA fabric.
+    MSS_SYS_ENVM0_POWER_DOWN and MSS_SYS_ENVM1_POWER_DOWN specify that eNVM
+    blocks 0 and 1 respectively should enter the deep power down state during
+    Flash*Freeze.
+    MSS_SYS_MPLL_POWER_DOWN specifies that the MSS PLL is powered down during
+    the Flash*Freeze period.
+    
+  @return
+    The MSS_SYS_flash_freeze function returns one of following status codes:
+        - MSS_SYS_SUCCESS
+        - MSS_SYS_MEM_ACCESS_ERROR
+        - MSS_SYS_UNEXPECTED_ERROR
+        
+  The following example demonstrates how to request the FPGA fabric and both
+  eNVM0 and eNVM1 to enter the Flash*Freeze mode:
+  @code
+    MSS_SYS_flash_freeze(MSS_SYS_FPGA_POWER_DOWN | MSS_SYS_ENVM0_POWER_DOWN | MSS_SYS_MPLL_POWER_DOWN);
+  @endcode
+ */
+uint8_t MSS_SYS_flash_freeze(uint8_t options);
+
+/*==============================================================================
+ * Cryptographic Services.
+ */
+
+/*-------------------------------------------------------------------------*//**
+  The MSS_SYS_128bit_aes function provides access to the SmartFusion2 AES-128
+  cryptography service.
+  
+  @param key
+    The key parameter is a pointer to a 16-bytes array containing the key to use
+    for the requested encryption/decryption operation.
+  
+  @param iv
+    The iv parameter is a pointer to a 16-bytes array containing the
+    intialization vector that will be used as part of the requested 
+    encryption/decryption operation. Its use is different depending on the mode.
+        -----------------------------------------
+        | Mode |             Usage              |
+        -----------------------------------------
+        | ECB  | Ignored.                       |
+        -----------------------------------------
+        | CBC  | Randomization.                 |
+        -----------------------------------------
+        | OFB  | Randomization.                 |
+        -----------------------------------------
+        | CTR  | Used as initial counter value. |
+        -----------------------------------------
+  
+  @param nb_blocks
+    The nb_blocks parameter specifies the number of 128-bit blocks of
+    plaintext/ciphertext to be processed by the AES-128 system service.
+  
+  @param mode
+    The mode parameter specifies the cipher mode of operation and whether the
+    source text must be encrypted or decrypted. The modes of operation are:
+        - Electronic Codebook (ECB)
+        - Cipher-Block Chaining (CBC)
+        - Output Feedback (OFB)
+        - Counter (CTR)
+    The CTR mode uses the content of the initialization vector as its intial
+    counter value. The counter increment is 2^64.
+    Allowed values for the mode parameter are:
+        - MSS_SYS_ECB_ENCRYPT
+        - MSS_SYS_ECB_DECRYPT
+        - MSS_SYS_CBC_ENCRYPT
+        - MSS_SYS_CBC_DECRYPT
+        - MSS_SYS_OFB_ENCRYPT
+        - MSS_SYS_OFB_DECRYPT
+        - MSS_SYS_CTR_ENCRYPT
+        - MSS_SYS_CTR_DECRYPT
+    
+  @param dest_addr
+    The dest_addr parameter is a pointer to the memory buffer where the result
+    of the encryption/decryption operation will be stored.
+  
+  @param src_addr
+    The src_addr parameter is a pointer to the memory buffer containg the source
+    plaintext/ciphertext to be encrypted/decrypted.
+  
+  @return
+    The MSS_SYS_128bit_aes function returns one of following status codes:
+        - MSS_SYS_SUCCESS
+        - MSS_SYS_MEM_ACCESS_ERROR
+        - MSS_SYS_SERVICE_DISABLED_BY_USER
+ */
+uint8_t MSS_SYS_128bit_aes
+(
+    const uint8_t * key,
+    const uint8_t * iv,
+    uint16_t nb_blocks,
+    uint8_t mode,
+    uint8_t * dest_addr,
+    const uint8_t * src_addr
+);
+
+/*-------------------------------------------------------------------------*//**
+  The MSS_SYS_256bit_aes function provides access to the SmartFusion2 AES-256
+  cryptography service.
+  
+  @param key
+    The key parameter is a pointer to a 32-bytes array containing the key to use
+    for the requested encryption/decryption operation.
+  
+  @param iv
+    The iv parameter is a pointer to a 16-bytes array containing the
+    intialization vector that will be used as part of the requested 
+    encryption/decryption operation. Its use is different depending on the mode.
+        -----------------------------------------
+        | Mode |             Usage              |
+        -----------------------------------------
+        | ECB  | Ignored.                       |
+        -----------------------------------------
+        | CBC  | Randomization.                 |
+        -----------------------------------------
+        | OFB  | Randomization.                 |
+        -----------------------------------------
+        | CTR  | Used as initial counter value. |
+        -----------------------------------------
+  
+  @param nb_blocks
+    The nb_blocks parameter specifies the number of 128-bit blocks of
+    plaintext/ciphertext requested to be processed by the AES-128 system service.
+  
+  @param mode
+    The mode parameter specifies the cipher mode of operation and whether the
+    source text must be encrypted or decrypted. The modes of operation are:
+        - Electronic Codebook (ECB)
+        - Cypher-Block Chaining (CBC)
+        - Output Feedback (OFB)
+        - Counter (CTR)
+    The CTR mode uses the content of the initialization vector as its intial
+    counter value. The counter increment is 2^64.
+    Allowed values for the mode parameter are:
+        - MSS_SYS_ECB_ENCRYPT
+        - MSS_SYS_ECB_DECRYPT
+        - MSS_SYS_CBC_ENCRYPT
+        - MSS_SYS_CBC_DECRYPT
+        - MSS_SYS_OFB_ENCRYPT
+        - MSS_SYS_OFB_DECRYPT
+        - MSS_SYS_CTR_ENCRYPT
+        - MSS_SYS_CTR_DECRYPT
+    
+  @param dest_addr
+    The dest_addr parameter is a pointer to the memory buffer where the result
+    of the encryption/decryption operation will be stored.
+  
+  @param src_addr
+    The src_addr parameter is a pointer to the memory buffer containg the source
+    plaintext/ciphertext to be encrypted/decrypted.
+  
+  @return
+    The MSS_SYS_256bit_aes function returns one of following status codes:
+        - MSS_SYS_SUCCESS
+        - MSS_SYS_MEM_ACCESS_ERROR
+        - MSS_SYS_SERVICE_DISABLED_BY_USER
+ */
+uint8_t MSS_SYS_256bit_aes
+( 
+    const uint8_t * key,
+    const uint8_t * iv,
+    uint16_t nb_blocks,
+    uint8_t mode,
+    uint8_t * dest_addr,
+    const uint8_t * src_addr
+);
+
+/*-------------------------------------------------------------------------*//**
+  The MSS_SYS_sha256 function provides access to the SmartFusion2 SHA-256
+  cryptography service.
+  
+  @param p_data_in
+    The p_data_in parameter is a pointer to the memory location containing the
+    data that will be hashed using the SHA-256 system service.
+  
+  @param length
+    The length parameter specifies the length in bits of the data to hash.
+  
+  @param result
+    The result parameter is a pointer to a 32 bytes buffer where the hash result
+    will be stored.
+  
+  @return
+    The MSS_SYS_sha256 function returns one of following status codes:
+        - MSS_SYS_SUCCESS
+        - MSS_SYS_MEM_ACCESS_ERROR
+        - MSS_SYS_SERVICE_DISABLED_BY_USER
+ */
+uint8_t MSS_SYS_sha256
+(
+    const uint8_t * p_data_in,
+    uint32_t length,
+    uint8_t * result
+);
+
+/*-------------------------------------------------------------------------*//**
+  The MSS_SYS_hmac function provides access to the SmartFusion2 HMAC
+  cryptography service. The HMAC system service generates message authentication
+  codes using the SHA-256 hash function.
+  
+  @param key
+    The key parameter is a pointer to a 32 bytes array containing the key used
+    to generate the message authentication code.
+  
+  @param p_data_in
+    The p_data_in parameter is a pointer to the data to be authenticated.
+  
+  @param length
+    The length parameter specifies the number of data bytes for which to generate
+    the authentication code. It is the size of the data pointed to by the
+    p_data_in parameter.
+  
+  @param p_result
+    The p_result parameter is a pointer to a 32 bytes buffer where the
+    authentication code generated by the HMAC system service will be stored.
+  
+  @return
+    The MSS_SYS_hmac function returns one of following status codes:
+        - MSS_SYS_SUCCESS
+        - MSS_SYS_MEM_ACCESS_ERROR
+        - MSS_SYS_SERVICE_DISABLED_BY_USER
+ */
+uint8_t MSS_SYS_hmac
+(
+    const uint8_t * key,
+    const uint8_t * p_data_in,
+    uint32_t length,
+    uint8_t * p_result
+);
+
+/*==============================================================================
+ * CRI Licensed Services.
+ */
+#define SYS_SERVICE_NOT_LICENCED        243u
+
+/*==============================================================================
+ * Non Deterministic Random Bit Generator Services.
+ */
+/*-------------------------------------------------------------------------*//**
+  The MSS_SYS_nrbg_self_test() function performs a self test of the
+  non-deterministic random bit generator (NRBG).
+  
+  @return
+    The MSS_SYS_nrbg_self_test function returns one of following status codes:
+        - MSS_SYS_SUCCESS
+        - MSS_SYS_NRBG_CATASTROPHIC_ERROR
+        - MSS_SYS_NRBG_MAX_INST_EXCEEDED
+        - MSS_SYS_NRBG_INVALID_HANDLE
+        - MSS_SYS_NRBG_GEN_REQ_TOO_BIG
+        - MSS_SYS_NRBG_MAX_LENGTH_EXCEEDED
+        - MSS_SYS_SERVICE_DISABLED_BY_FACTORY
+        - MSS_SYS_SERVICE_DISABLED_BY_USER
+ */
+uint8_t MSS_SYS_nrbg_self_test(void);
+
+/*-------------------------------------------------------------------------*//**
+  The MSS_SYS_nrbg_instantiate() function instantiates a non-deterministic
+  random bit generator (NRBG) instance. A maximum of two concurrent instances
+  are available.
+  
+  @param personalization_str
+    The personalization_str parameter is a pointer to a buffer containing a
+    random bit generator personalization string. The personalization string
+    can be up to 128 bytes long.
+  
+  @param personalization_str_length
+    The personalization_str_length parameter specifies the byte length of the
+    personalization string pointed to by personalization_str.
+  
+  @param p_nrbg_handle
+    The p_nrbg_handle parameter is a pointer to a byte that will contain the
+    handle of the instantiated NRBG if this function call suceeds.
+  
+  @return
+    The MSS_SYS_nrbg_instantiate function returns one of following status codes:
+        - MSS_SYS_SUCCESS
+        - MSS_SYS_NRBG_CATASTROPHIC_ERROR
+        - MSS_SYS_NRBG_MAX_INST_EXCEEDED
+        - MSS_SYS_NRBG_INVALID_HANDLE
+        - MSS_SYS_NRBG_GEN_REQ_TOO_BIG
+        - MSS_SYS_NRBG_MAX_LENGTH_EXCEEDED
+        - MSS_SYS_SERVICE_DISABLED_BY_FACTORY
+        - MSS_SYS_SERVICE_DISABLED_BY_USER
+ */
+uint8_t MSS_SYS_nrbg_instantiate
+(
+    const uint8_t * personalization_str,
+    uint16_t personalization_str_length,
+    uint8_t * p_nrbg_handle
+);
+
+/*-------------------------------------------------------------------------*//**
+  The MSS_SYS_nrbg_generate function generates a random bit sequence up to
+  128 bytes long.
+  
+  @param p_requested_data
+    The p_requested_data parameter is a pointer to the buffer where the requested
+    random data will be stored on completion of this system servide.
+  
+  @param p_additional_input
+    The p_additional_input parameter is a pointer to the buffer containing
+    additional input data for the random bit generation.
+  
+  @param requested_length
+    The requested_length parameter specifies the number of random data bytes
+    requested to be generated. The maximum generated data length is 128 bytes.
+  
+  @param additional_input_length
+    The additional_input_length parameter specifies the number of addditonal
+    input bytes to use in the random data generation.
+  
+  @param pr_req
+    The pr_req parameter specifies if prediction resistance is requested.
+  
+  @param nrbg_handle
+    The nrbg_handle parameter specifies which non-deterministic random bit
+    generator (NRBG) instance will be used to generate the random data. The
+    value of nrbg_handle is obtained as a result of a previous call to the
+    MSS_SYS_nrbg_instantiate() function.
+  
+  @return
+    The MSS_SYS_nrbg_generate function returns one of following status codes:
+        - MSS_SYS_SUCCESS
+        - MSS_SYS_NRBG_CATASTROPHIC_ERROR
+        - MSS_SYS_NRBG_MAX_INST_EXCEEDED
+        - MSS_SYS_NRBG_INVALID_HANDLE
+        - MSS_SYS_NRBG_GEN_REQ_TOO_BIG
+        - MSS_SYS_NRBG_MAX_LENGTH_EXCEEDED
+        - MSS_SYS_SERVICE_DISABLED_BY_FACTORY
+        - MSS_SYS_SERVICE_DISABLED_BY_USER
+   
+ */
+uint8_t MSS_SYS_nrbg_generate
+(
+    const uint8_t * p_requested_data,
+    const uint8_t * p_additional_input,
+    uint8_t requested_length,
+    uint8_t additional_input_length,
+    uint8_t pr_req,
+    uint8_t nrbg_handle
+);
+
+/*-------------------------------------------------------------------------*//**
+  The MSS_SYS_nrbg_reseed() function is used to reseed the non-deterministic
+  random bit generator (NRBG) identified by the nrbg_handle parameter.
+  
+  @param p_additional_input
+    The additional_input_length parameter specifies the number of additional
+    input bytes used to reseed the NRBG identified by the nrbg_handle parameter.
+  
+  @param additional_input_length
+    The additional_input_length parameter specifies the number of additional
+    input bytes used to reseed the NRBG.
+  
+  @param nrbg_handle
+    The nrbg_handle parameter specifies which NRBG instance to reseed. The value
+    of nrbg_handle is obtained as a result of a previous call to the
+    MSS_SYS_nrbg_instantiate() function.
+  
+  @return
+    The MSS_SYS_nrbg_reseed function returns one of following status codes:
+        - MSS_SYS_SUCCESS
+        - MSS_SYS_NRBG_CATASTROPHIC_ERROR
+        - MSS_SYS_NRBG_MAX_INST_EXCEEDED
+        - MSS_SYS_NRBG_INVALID_HANDLE
+        - MSS_SYS_NRBG_GEN_REQ_TOO_BIG
+        - MSS_SYS_NRBG_MAX_LENGTH_EXCEEDED
+        - MSS_SYS_SERVICE_DISABLED_BY_FACTORY
+        - MSS_SYS_SERVICE_DISABLED_BY_USER
+   
+ */
+uint8_t MSS_SYS_nrbg_reseed
+(
+    const uint8_t * p_additional_input,
+    uint8_t additional_input_length,
+    uint8_t nrbg_handle
+);
+
+/*-------------------------------------------------------------------------*//**
+  The MSS_SYS_nrbg_uninstantiate() function releases the non-deterministic
+  random bit generator (NRBG) identified by the nrbg_handle parameter.
+  
+  @param nrbg_handle
+    The nrbg_handle parameter specifies which NRBG instance will be released.
+    The value of nrbg_handle is obtained as a result of a previous call to the
+    MSS_SYS_nrbg_instantiate() function.
+  
+  @return
+    The MSS_SYS_nrbg_uninstantiate function returns one of following status codes:
+        - MSS_SYS_SUCCESS
+        - MSS_SYS_NRBG_CATASTROPHIC_ERROR
+        - MSS_SYS_NRBG_MAX_INST_EXCEEDED
+        - MSS_SYS_NRBG_INVALID_HANDLE
+        - MSS_SYS_NRBG_GEN_REQ_TOO_BIG
+        - MSS_SYS_NRBG_MAX_LENGTH_EXCEEDED
+        - MSS_SYS_SERVICE_DISABLED_BY_FACTORY
+        - MSS_SYS_SERVICE_DISABLED_BY_USER
+   
+ */
+uint8_t MSS_SYS_nrbg_uninstantiate
+(
+    uint8_t nrbg_handle
+);
+
+/*==============================================================================
+ * Programming Services.
+ */
+
+#define MSS_SYS_PROG_AUTHENTICATE    0u
+#define MSS_SYS_PROG_PROGRAM         1u
+#define MSS_SYS_PROG_VERIFY          2u
+   
+/*-------------------------------------------------------------------------*//**
+  The ISP Service allows the MSS Cortex-M3 processor to directly provide a
+  bitstream for programming. The ISP Service is initiated by a call to
+  MSS_SYS_start_isp(). The ISP Service can:
+    - authenticate a programming bitstream
+    - program a bitstream
+    - verify that a programming bitstream has been correctly programmed
+
+  The application must provide two functions as parameter to the
+  MSS_SYS_start_isp() function. The first function will be used by the ISP
+  Service to read the programming bitstream. The second function will be used by
+  the ISP Service to notify the application that the ISP Service completed.
+  
+  @param mode
+    The mode parameter specifies ISP service to perform. It can be one of:
+        - MSS_SYS_PROG_AUTHENTICATE
+        - MSS_SYS_PROG_PROGRAM
+        - MSS_SYS_PROG_VERIFY
+ 
+  @param page_read_handler
+    The page_read_handler parameter is a pointer to a function with the
+    following prototype:
+        uint32_t page_read_handler(uint8 const ** pp_next_page);
+ 
+  @param isp_completion_handler
+    The isp_completion_handler parameter is a pointer to a function with the
+    following prototype. This function will be called when the ISP service
+    completes.
+ 
+    The isp_completion_handler function will receive one of the following status
+    codes:
+        - MSS_SYS_SUCCESS
+        - MSS_SYS_CHAINING_MISMATCH
+        - MSS_SYS_UNEXPECTED_DATA_RECEIVED
+        - MSS_SYS_INVALID_ENCRYPTION_KEY
+        - MSS_SYS_INVALID_COMPONENT_HEADER
+        - MSS_SYS_BACK_LEVEL_NOT_SATISFIED
+        - MSS_SYS_DSN_BINDING_MISMATCH
+        - MSS_SYS_ILLEGAL_COMPONENT_SEQUENCE
+        - MSS_SYS_INSUFFICIENT_DEV_CAPABILITIES
+        - MSS_SYS_INCORRECT_DEVICE_ID
+        - MSS_SYS_UNSUPPORTED_BITSTREAM_PROT_VER
+        - MSS_SYS_VERIFY_NOT_PERMITTED_ON_BITSTR
+        - MSS_SYS_ABORT
+        - MSS_SYS_NVM_VERIFY_FAILED
+        - MSS_SYS_DEVICE_SECURITY_PROTECTED
+        - MSS_SYS_PROGRAMMING_MODE_NOT_ENABLED
+        - MSS_SYS_SERVICE_DISABLED_BY_USER
+        
+  @return
+    This function does not return a value.
+ */
+void MSS_SYS_start_isp
+(
+    uint8_t mode,
+    uint32_t (*page_read_handler)(uint8_t const **),
+    void (*isp_completion_handler)(uint32_t)
+);
+
+/*-------------------------------------------------------------------------*//**
+  Recalculates and compares digests of selected components.
+  
+  @param options
+    The options parameter specifies which components' digest will be recalculated
+    and checked. Each bit is used to identify a componetn as follows:
+        - bit 0: FPGA fabric
+        - bit 1: eNVM0
+        - bit 2: eNVM1
+    Note: The FPGA fabric will enter the FlashFreeze state if powered up when
+          its digest is checked.
+ 
+  @return
+    The MSS_SYS_check_digest function returns the result of the digest check. The
+    meaning of the digest check return value is as follows:
+        bit 0: Fabric digest error
+        bit 1: ENVM0 digest error
+        bit 2: ENVM1 digest error
+    A '1' in one of the above bits indicates a digest mismatch.
+ */
+#define MSS_SYS_DIGEST_CHECK_FABRIC     0x01u
+#define MSS_SYS_DIGEST_CHECK_ENVM0      0x02u
+#define MSS_SYS_DIGEST_CHECK_ENVM1      0x04u
+
+uint8_t MSS_SYS_check_digest
+(
+    uint8_t options
+);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MSS_SYS_SERVICES_H_ */
diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_timer/mss_timer.h b/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_timer/mss_timer.h
new file mode 100644
index 000000000..cb5e0517e
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_timer/mss_timer.h
@@ -0,0 +1,595 @@
+/*******************************************************************************
+ * (c) Copyright 2010-2013 Microsemi SoC Products Group.  All rights reserved.
+ * 
+ * SmartFusion2 microcontroller subsystem (MSS) timer driver API.
+ *
+ * SVN $Revision: 5111 $
+ * SVN $Date: 2013-02-18 17:03:09 +0000 (Mon, 18 Feb 2013) $
+ */
+/*=========================================================================*//**
+  @mainpage SmartFusion2 MSS Timer Bare Metal Driver.
+
+  @section intro_sec Introduction
+  The SmartFusion2 Microcontroller Subsystem (MSS) includes a timer hardware
+  block which can be used as two independent 32-bits timers or as a single
+  64-bits timer in periodic or one-shot mode. 
+
+  This driver provides a set of functions for controlling the MSS timer as part
+  of a bare metal system where no operating system is available. These drivers
+  can be adapted for use as part of an operating system but the implementation
+  of the adaptation layer between this driver and the operating system's driver
+  model is outside the scope of this driver.
+  
+  @section theory_op Theory of Operation
+  The MSS Timer driver uses the SmartFusion2 "Cortex Microcontroler Software
+  Interface Standard - Peripheral Access Layer" (CMSIS-PAL) to access hadware
+  registers. You must ensure that the SmartFusion2 CMSIS-PAL is either included
+  in the software toolchain used to build your project or is included in your
+  project. The most up-to-date SmartFusion2 CMSIS-PAL files can be obtained using
+  the Actel Firmware Catalog.
+  The SmartFusion2 MSS Timer can be used in one of two mutually exclusive modes;
+  either as a single 64-bits timer or as two independent 32-bits timers. The MSS
+  Timer can be used in either periodic mode or one-shot mode. A timer configured
+  for periodic mode operations will generate an interrupt and reload its
+  down-counter when it reaches 0. The timer will then continue decrementing from
+  its reload value without waiting for the interrupt to be cleared. A timer
+  configured for one-shot mode will only generate an interrupt once when its
+  down-counter reaches 0. It must be explitcitly reloaded to start decrementing
+  again.
+  
+  The MSS Timer driver functions are grouped into the following categories:
+    - Initialization and Configuration
+    - Timer control
+    - Interrupt control
+  
+  The MSS Timer driver provides three initialization functions:
+    - MSS_TIM1_init()
+    - MSS_TIM2_init()
+    - MSS_TIM64_init()
+  The MSS Timer driver is initialized through calls to these functions and at
+  least one of them must be called before any other MSS Timer driver functions
+  can be called.
+  You should only use the MSS_TIM1_init() and MSS_TIM2_init() functions if you
+  intend to use the timer in 32-bits mode. Use the MSS_TIM64_init() function is
+  you intend to use the MSS Timer as a single 64-bits timer. The initialization
+  functions take a single parameter specifying the operating mode of the timer
+  being initialized.
+  
+  Once initialized a timer can be controlled using the following functions:
+    - MSS_TIM1_load_immediate()
+    - MSS_TIM1_load_background()
+    - MSS_TIM1_get_current_value()
+    - MSS_TIM1_start()
+    - MSS_TIM1_stop()
+    - MSS_TIM2_load_immediate()
+    - MSS_TIM2_load_background()
+    - MSS_TIM2_get_current_value()
+    - MSS_TIM2_start()
+    - MSS_TIM2_stop()
+    - MSS_TIM64_load_immediate()
+    - MSS_TIM64_load_background()
+    - MSS_TIM64_get_current_value()
+    - MSS_TIM64_start()
+    - MSS_TIM64_stop()
+  
+  Timer interrupts are controlled using the following functions:
+    - MSS_TIM1_enable_irq()
+    - MSS_TIM1_disable_irq()
+    - MSS_TIM1_clear_irq()
+    - MSS_TIM2_enable_irq()
+    - MSS_TIM2_disable_irq()
+    - MSS_TIM2_clear_irq()
+    - MSS_TIM64_enable_irq()
+    - MSS_TIM64_disable_irq()
+    - MSS_TIM64_clear_irq()
+  
+  The function prototypes for the timer interrupt handlers are:
+    - void Timer1_IRQHandler( void )
+    - void Timer2_IRQHandler( void )
+  Entries for these interrupt handlers are provided in the SmartFusion2 CMSIS-PAL
+  vector table. To add a Timer 1 interrupt handler, you must implement a
+  Timer1_IRQHandler( ) function as part of your application code. To add a
+  Timer 2 interrupt handler, you must implement a Timer2_IRQHandler( ) function
+  as part of your application code. When using the MSS Timer as a 64-bit timer,
+  you must implement a Timer1_IRQHandler( ) function as part of your
+  application code. The Timer 2 interrupt is not used when the MSS Timer is
+  configured as a 64-bit timer.
+  
+ *//*=========================================================================*/
+#ifndef MSS_TIMER_H_
+#define MSS_TIMER_H_
+
+
+#include "../../CMSIS/m2sxxx.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif 
+
+/*-------------------------------------------------------------------------*//**
+ * Timer mode selection. This enumeration is used to select between the two
+ * possible timer modes of operation: periodic and one-shot mode. It is used as
+ * an argument to the MSS_TIM1_init(), MSS_TIM2_init() and MSS_TIM64_init()
+ * functions.
+ * MSS_TIMER_PERIODIC_MODE:
+ *  In periodic mode the timer generates interrupts at constant intervals. On 
+ *  reaching zero, the timer's counter is reloaded with a value held in a
+ *  register and begins counting down again.
+ * MSS_TIMER_ONE_SHOT_MODE:
+ *  The timer generates a single interrupt in this mode. On reaching zero, the
+ *  timer's counter halts until reprogrammed by the user.
+ */
+typedef enum __mss_timer_mode_t
+{
+    MSS_TIMER_PERIODIC_MODE = 0,
+    MSS_TIMER_ONE_SHOT_MODE = 1
+} mss_timer_mode_t;
+
+/*-------------------------------------------------------------------------*//**
+  The MSS_TIM1_init() function initializes the SmartFusion2 MSS Timer block for
+  use as a 32-bit timer and selects the operating mode for Timer 1. This function
+  takes the MSS Timer block out of reset in case this hasn�t been done already,
+  stops Timer 1, disables its interrupt and sets the Timer 1 operating mode.
+  Please note that the SmartFusion2 MSS Timer block cannot be used both as a
+  64-bit and 32-bit timer. Calling MSS_TIM1_init() will overwrite any previous
+  configuration of the MSS Timer as a 64-bit timer.
+
+ 
+  @param mode
+    The mode parameter specifies whether the timer will operate in periodic or
+    one-shot mode. Allowed values for this parameter are:
+        - MSS_TIMER_PERIODIC_MODE
+        - MSS_TIMER_ONE_SHOT_MODE
+ */
+static __INLINE void MSS_TIM1_init(mss_timer_mode_t mode)
+{
+    NVIC_DisableIRQ(Timer1_IRQn);             /* Disable timer 1 irq in the Cortex-M3 NVIC */  
+    
+    SYSREG->SOFT_RST_CR &= ~SYSREG_TIMER_SOFTRESET_MASK; /* Take timer block out of reset */
+    
+    TIMER->TIM64_MODE = 0u;                     /* switch to 32 bits mode */
+    
+    TIMER_BITBAND->TIM1ENABLE = 0u;             /* disable timer */
+    TIMER_BITBAND->TIM1INTEN = 0u;              /* disable interrupt */
+    TIMER_BITBAND->TIM1MODE = (uint32_t)mode;   /* set mode (continuous/one-shot) */
+    
+    TIMER->TIM1_RIS = 1u;                       /* clear timer 1 interrupt */
+    NVIC_ClearPendingIRQ(Timer1_IRQn);        /* clear timer 1 interrupt within NVIC */
+}
+
+/*-------------------------------------------------------------------------*//**
+  The MSS_TIM1_start() function enables Timer 1 and starts its down-counter
+  decrementing from the load_value specified in previous calls to the
+  MSS_TIM1_load_immediate() or MSS_TIM1_load_background() functions.
+ */
+static __INLINE void MSS_TIM1_start(void)
+{
+    TIMER_BITBAND->TIM1ENABLE = 1u;    /* enable timer */
+}
+
+/*-------------------------------------------------------------------------*//**
+  The MSS_TIM1_stop() function disables Timer 1 and stops its down-counter
+  decrementing.
+ */
+static __INLINE void MSS_TIM1_stop(void)
+{
+    TIMER_BITBAND->TIM1ENABLE = 0u;    /* disable timer */
+}
+
+/*-------------------------------------------------------------------------*//**
+  The MSS_TIM1_get_current_value() returns the current value of the Timer 1
+  down-counter.
+  
+  @return
+    This function returns the 32-bits current value of the Timer 1 down-counter.
+ */
+static __INLINE uint32_t MSS_TIM1_get_current_value(void)
+{
+    return TIMER->TIM1_VAL;
+}
+
+/*-------------------------------------------------------------------------*//**
+  The MSS_TIM1_load_immediate() function loads the value passed by the
+  load_value parameter into the Timer 1 down-counter. The counter will decrement
+  immediately from this value once Timer 1 is enabled. The MSS Timer will
+  generate an interrupt when the counter reaches zero if Timer 1 interrupts are
+  enabled. This function is intended to be used when Timer 1 is configured for
+  one-shot mode to time a single delay.
+ 
+  @param load_value
+    The load_value parameter specifies the value from which the Timer 1 down-counter
+    will start decrementing from.
+ */
+static __INLINE void MSS_TIM1_load_immediate(uint32_t load_value)
+{
+    TIMER->TIM1_LOADVAL = load_value;
+}
+
+/*-------------------------------------------------------------------------*//**
+  The MSS_TIM1_load_background() function is used to specify the value that will
+  be reloaded into the Timer 1 down-counter the next time the counter reaches
+  zero. This function is typically used when Timer 1 is configured for periodic
+  mode operation to select or change the delay period between the interrupts
+  generated by Timer 1.
+ 
+  @param load_value
+    The load_value parameter specifies the value that will be loaded into the
+    Timer 1 down-counter the next time the down-counter reaches zero. The Timer
+    1 down-counter will start decrementing from this value after the current
+    count expires.
+ */
+static __INLINE void MSS_TIM1_load_background(uint32_t load_value)
+{
+    TIMER->TIM1_BGLOADVAL = load_value;
+}
+
+/*-------------------------------------------------------------------------*//**
+  The MSS_TIM1_enable_irq() function is used to enable interrupt generation for
+  Timer 1. This function also enables the interrupt in the Cortex-M3 interrupt
+  controller. The Timer1_IRQHandler() function will be called when a Timer 1
+  interrupt occurs.
+  Note: Note: 	A Timer1_IRQHandler() default implementation is defined, with
+  weak linkage, in the SmartFusion2 CMSIS-PAL. You must provide your own
+  implementation of the Timer1_IRQHandler() function, that will override the
+  default implementation, to suit your application.
+
+ */
+static __INLINE void MSS_TIM1_enable_irq(void)
+{
+    TIMER_BITBAND->TIM1INTEN = 1u;
+    NVIC_EnableIRQ(Timer1_IRQn);
+}
+
+/*-------------------------------------------------------------------------*//**
+  The MSS_TIM1_disable_irq() function is used to disable interrupt generation
+  for Timer 1. This function also disables the interrupt in the Cortex-M3
+  interrupt controller.
+ */
+static __INLINE void MSS_TIM1_disable_irq(void)
+{
+    TIMER_BITBAND->TIM1INTEN = 0u;
+    NVIC_DisableIRQ(Timer1_IRQn);
+}
+
+/*-------------------------------------------------------------------------*//**
+  The MSS_TIM1_clear_irq() function is used to clear a pending interrupt from
+  Timer 1. This function also clears the interrupt in the Cortex-M3 interrupt
+  controller.
+  Note: You must call the MSS_TIM1_clear_irq() function as part of your
+  implementation of the Timer1_IRQHandler() Timer 1 interrupt service routine
+  (ISR) in order to prevent the same interrupt event retriggering a call to the
+  ISR.
+
+ */
+static __INLINE void MSS_TIM1_clear_irq(void)
+{
+    TIMER->TIM1_RIS = 1u;
+}
+
+/*-------------------------------------------------------------------------*//**
+  The MSS_TIM2_init() function initializes the SmartFusion2 MSS Timer block for
+  use as a 32-bit timer and selects the operating mode for Timer 2. This function
+  takes the MSS Timer block out of reset in case this hasn�t been done already,
+  stops Timer 2, disables its interrupt and sets the Timer 2 operating mode.
+  Note: Please note that the SmartFusion2 MSS Timer block cannot be used both as
+  a 64-bit and 32-bit timer. Calling MSS_TIM2_init() will overwrite any previous
+  configuration of the MSS Timer as a 64-bit timer.
+  
+  @param mode
+    The mode parameter specifies whether the timer will operate in periodic or
+    one-shot mode. Allowed values for this parameter are:
+        - MSS_TIMER_PERIODIC_MODE
+        - MSS_TIMER_ONE_SHOT_MODE 
+ */
+static __INLINE void MSS_TIM2_init(mss_timer_mode_t mode)
+{
+    NVIC_DisableIRQ(Timer2_IRQn);             /* Disable timer 2 irq in the Cortex-M3 NVIC */  
+    
+    SYSREG->SOFT_RST_CR &= ~SYSREG_TIMER_SOFTRESET_MASK; /* Take timer block out of reset */
+    
+    TIMER->TIM64_MODE = 0u;                     /* switch to 32 bits mode */
+    
+    TIMER_BITBAND->TIM2ENABLE = 0u;             /* disable timer */
+    TIMER_BITBAND->TIM2INTEN = 0u;              /* disable interrupt */
+    TIMER_BITBAND->TIM2MODE = (uint32_t)mode;   /* set mode (continuous/one-shot) */
+    
+    TIMER->TIM2_RIS = 1u;                       /* clear timer 2 interrupt */
+    NVIC_ClearPendingIRQ(Timer2_IRQn);        /* clear timer 2 interrupt within NVIC */
+}
+
+/*-------------------------------------------------------------------------*//**
+  The MSS_TIM2_start() function enables Timer 2 and  starts its down-counter
+  decrementing from the load_value specified in previous calls to the
+  MSS_TIM2_load_immediate() or MSS_TIM2_load_background() functions.
+ */
+static __INLINE void MSS_TIM2_start(void)
+{
+    TIMER_BITBAND->TIM2ENABLE = 1u;    /* enable timer */
+}
+
+/*-------------------------------------------------------------------------*//**
+  The MSS_TIM2_stop() function disables Timer 2 and stops its down-counter
+  decrementing.
+ */
+static __INLINE void MSS_TIM2_stop(void)
+{
+    TIMER_BITBAND->TIM2ENABLE = 0u;    /* disable timer */
+}
+
+/*-------------------------------------------------------------------------*//**
+  The MSS_TIM2_get_current_value() returns the current value of the Timer 2
+  down-counter.
+ */
+static __INLINE uint32_t MSS_TIM2_get_current_value(void)
+{
+    return TIMER->TIM2_VAL;
+}
+
+/*-------------------------------------------------------------------------*//**
+  The MSS_TIM2_load_immediate() function loads the value passed by the
+  load_value parameter into the Timer 2 down-counter. The counter will decrement
+  immediately from this value once Timer 2 is enabled. The MSS Timer will
+  generate an interrupt when the counter reaches zero if Timer 2 interrupts are
+  enabled. This function is intended to be used when Timer 2 is configured for
+  one-shot mode to time a single delay.
+  
+  @param load_value
+    The load_value parameter specifies the value from which the Timer 2
+    down-counter will start decrementing. 
+ */
+static __INLINE void MSS_TIM2_load_immediate(uint32_t load_value)
+{
+    TIMER->TIM2_LOADVAL = load_value;
+}
+
+/*-------------------------------------------------------------------------*//**
+  The MSS_TIM2_load_background() function is used to specify the value that will
+  be reloaded into the Timer 2 down-counter the next time the counter reaches
+  zero. This function is typically used when Timer 2 is configured for periodic
+  mode operation to select or change the delay period between the interrupts
+  generated by Timer 2.
+  
+  @param load_value
+    The load_value parameter specifies the value that will be loaded into the
+    Timer 2 down-counter the next time the down-counter reaches zero. The Timer
+    2 down-counter will start decrementing from this value after the current
+    count expires.
+ */
+static __INLINE void MSS_TIM2_load_background(uint32_t load_value)
+{
+    TIMER->TIM2_BGLOADVAL = load_value;
+}
+
+/*-------------------------------------------------------------------------*//**
+  The MSS_TIM2_enable_irq() function is used to enable interrupt generation for
+  Timer 2. This function also enables the interrupt in the Cortex-M3 interrupt
+  controller. The Timer2_IRQHandler() function will be called when a Timer 2
+  interrupt occurs.
+  Note: A Timer2_IRQHandler() default implementation is defined, with weak
+  linkage, in the SmartFusion2 CMSIS-PAL. You must provide your own implementation
+  of the Timer2_IRQHandler() function, that will override the default
+  implementation, to suit your application.
+ */
+static __INLINE void MSS_TIM2_enable_irq(void)
+{
+    TIMER_BITBAND->TIM2INTEN = 1u;
+    NVIC_EnableIRQ( Timer2_IRQn );
+}
+
+/*-------------------------------------------------------------------------*//**
+  The MSS_TIM2_disable_irq() function is used to disable interrupt generation
+  for Timer 2. This function also disables the interrupt in the Cortex-M3
+  interrupt controller.
+ */
+static __INLINE void MSS_TIM2_disable_irq(void)
+{
+    TIMER_BITBAND->TIM2INTEN = 0u;
+    NVIC_DisableIRQ(Timer2_IRQn);
+}
+
+/*-------------------------------------------------------------------------*//**
+  The MSS_TIM2_clear_irq() function is used to clear a pending interrupt from
+  Timer 2. This function also clears the interrupt in the Cortex-M3 interrupt
+  controller.
+  Note: You must call the MSS_TIM2_clear_irq() function as part of your
+  implementation of the Timer2_IRQHandler() Timer 2 interrupt service routine
+  (ISR) in order to prevent the same interrupt event retriggering a call to the
+  ISR.
+ */
+static __INLINE void MSS_TIM2_clear_irq(void)
+{
+    TIMER->TIM2_RIS = 1u;
+}
+
+/*-------------------------------------------------------------------------*//**
+  The MSS_TIM64_init() function initializes the SmartFusion2 MSS Timer block for
+  use as a single 64-bit timer and selects the operating mode of the timer. This
+  function takes the MSS Timer block out of reset in case this hasn�t been done
+  already, stops the timer, disables its interrupts and sets the timer's
+  operating mode.
+  Note: Please note that the SmartFusion2 MSS Timer block cannot be used both as
+  a 64-bit and 32-bit timer. Calling MSS_TIM64_init() will overwrite any previous
+  configuration of the MSS Timer as a 32-bit timer.
+
+  @param mode
+    The mode parameter specifies whether the timer will operate in periodic or
+    one-shot mode. Allowed values for this parameter are:
+        - MSS_TIMER_PERIODIC_MODE
+        - MSS_TIMER_ONE_SHOT_MODE 
+ */
+static __INLINE void MSS_TIM64_init(mss_timer_mode_t mode)
+{
+    NVIC_DisableIRQ(Timer1_IRQn);         /* disable timer 1 interrupt within NVIC */
+    NVIC_DisableIRQ(Timer2_IRQn);         /* disable timer 2 interrupt within NVIC */
+    
+    SYSREG->SOFT_RST_CR &= ~SYSREG_TIMER_SOFTRESET_MASK; /* Take timer block out of reset */
+    
+    TIMER->TIM64_MODE = 1u;                     /* switch to 64 bits mode */
+    
+    TIMER_BITBAND->TIM64ENABLE = 0u;            /* disable timer */
+    TIMER_BITBAND->TIM64INTEN = 0u;             /* disable interrupt */
+    TIMER_BITBAND->TIM64MODE = (uint32_t)mode;  /* set mode (continuous/one-shot) */
+    
+    TIMER->TIM1_RIS = 1u;                   /* clear timer 1 interrupt */
+    TIMER->TIM2_RIS = 1u;                   /* clear timer 2 interrupt */
+    NVIC_ClearPendingIRQ(Timer1_IRQn);    /* clear timer 1 interrupt within NVIC */
+    NVIC_ClearPendingIRQ(Timer2_IRQn);    /* clear timer 2 interrupt within NVIC */
+}
+
+/*-------------------------------------------------------------------------*//**
+  The MSS_TIM64_start() function enables the 64-bit timer and starts its
+  down-counter decrementing from the load_value specified in previous calls to
+  the MSS_TIM64_load_immediate() or MSS_TIM64_load_background() functions.
+ */
+static __INLINE void MSS_TIM64_start(void)
+{
+    TIMER_BITBAND->TIM64ENABLE = 1u;    /* enable timer */
+}
+
+/*-------------------------------------------------------------------------*//**
+  The MSS_TIM64_stop() function disables the 64-bit timer and stops its
+  down-counter decrementing.
+ */
+static __INLINE void MSS_TIM64_stop(void)
+{
+    TIMER_BITBAND->TIM64ENABLE = 0u;    /* disable timer */
+}
+
+/*-------------------------------------------------------------------------*//**
+  The MSS_TIM64_get_current_value() is used to read the current value of the
+  64-bit timer down-counter. 
+ 
+  @param load_value_u
+    The load_value_u parameter is a pointer to a 32-bit variable where the upper
+    32 bits of the current value of the 64-bit timer down-counter will be copied.
+    
+  @param load_value_l
+    The load_value_l parameter is a pointer to a 32-bit variable where the lower
+    32 bits of the current value of the 64-bit timer down-counter will be copied.
+    
+  Example:
+  @code
+    uint32_t current_value_u = 0;
+    uint32_t current_value_l = 0;
+    MSS_TIM64_get_current_value( &current_value_u, &current_value_l );
+  @endcode
+ */
+static __INLINE void MSS_TIM64_get_current_value
+(
+    uint32_t * load_value_u,
+    uint32_t * load_value_l
+)
+{
+    *load_value_l = TIMER->TIM64_VAL_L;
+    *load_value_u = TIMER->TIM64_VAL_U;
+}
+
+/*-------------------------------------------------------------------------*//**
+  The MSS_TIM64_load_immediate() function loads the values passed by the
+  load_value_u and load_value_l parameters into the 64-bit timer down-counter.
+  The counter will decrement immediately from the concatenated 64-bit value once
+  the 64-bit timer is enabled. The MSS Timer will generate an interrupt when the
+  counter reaches zero if 64-bit timer interrupts are enabled. This function is
+  intended to be used when the 64-bit timer is configured for one-shot mode to
+  time a single delay.
+ 
+  @param load_value_u
+    The load_value_u parameter specifies the upper 32 bits of the 64-bit timer
+    load value from which the 64-bit timer down-counter will start decrementing.
+    
+  @param load_value_l
+    The load_value_l parameter specifies the lower 32 bits of the 64-bit timer
+    load value from which the 64-bit timer down-counter will start decrementing.
+ */
+static __INLINE void MSS_TIM64_load_immediate
+(
+    uint32_t load_value_u,
+    uint32_t load_value_l
+)
+{
+    TIMER->TIM64_LOADVAL_U = load_value_u;
+    TIMER->TIM64_LOADVAL_L = load_value_l;
+}
+
+/*-------------------------------------------------------------------------*//**
+  The MSS_TIM64_load_background() function is used to specify the 64-bit value
+  that will be reloaded into the 64-bit timer down-counter the next time the
+  counter reaches zero. This function is typically used when the 64-bit timer is
+  configured for periodic mode operation to select or change the delay period
+  between the interrupts generated by the 64-bit timer.
+ 
+  @param load_value_u
+    The load_value_u parameter specifies the upper 32 bits of the 64-bit timer
+    load value. The concatenated 64-bit value formed from load_value_u and
+    load_value_l will be loaded into the 64-bit timer down-counter the next
+    time the down-counter reaches zero. The 64-bit timer down-counter will start
+    decrementing from the concatenated 64-bit value after the current count
+    expires.
+    
+  @param load_value_l
+    The load_value_l parameter specifies the lower 32 bits of the 64-bit timer
+    load value. The concatenated 64-bit value formed from load_value_u and
+    load_value_l will be loaded into the 64-bit timer down-counter the next time
+    the down-counter reaches zero. The 64-bit timer down-counter will start
+    decrementing from the concatenated 64-bit value after the current count
+    expires.
+ 
+ */
+static __INLINE void MSS_TIM64_load_background
+(
+    uint32_t load_value_u,
+    uint32_t load_value_l
+)
+{
+    TIMER->TIM64_BGLOADVAL_U = load_value_u;
+    TIMER->TIM64_BGLOADVAL_L = load_value_l;
+}
+
+/*-------------------------------------------------------------------------*//**
+  The MSS_TIM64_enable_irq() function is used to enable interrupt generation for
+  the 64-bit timer. This function also enables the interrupt in the Cortex-M3
+  interrupt controller. The Timer1_IRQHandler() function will be called when a
+  64-bit timer interrupt occurs.
+  Note: A Timer1_IRQHandler() default implementation is defined, with weak
+  linkage, in the SmartFusion2 CMSIS-PAL. You must provide your own
+  implementation of the Timer1_IRQHandler() function, that will override the
+  default implementation, to suit your application.
+  Note: The MSS_TIM64_enable_irq() function enables and uses Timer 1 interrupts
+  for the 64-bit timer. Timer 2 interrupts remain disabled.
+ */
+static __INLINE void MSS_TIM64_enable_irq(void)
+{
+    TIMER_BITBAND->TIM64INTEN = 1u;
+    NVIC_EnableIRQ(Timer1_IRQn);
+}
+
+/*-------------------------------------------------------------------------*//**
+  The MSS_TIM64_disable_irq() function is used to disable interrupt generation
+  for the 64-bit timer. This function also disables the interrupt in the
+  Cortex-M3 interrupt controller.
+ */
+static __INLINE void MSS_TIM64_disable_irq(void)
+{
+    TIMER_BITBAND->TIM64INTEN = 0u;
+    NVIC_DisableIRQ(Timer1_IRQn);
+}
+
+/*-------------------------------------------------------------------------*//**
+  The MSS_TIM64_clear_irq() function is used to clear a pending interrupt from
+  the 64-bit timer. This function also clears the interrupt in the Cortex-M3
+  interrupt controller.
+  Note: You must call the MSS_TIM64_clear_irq() function as part of your
+  implementation of the Timer1_IRQHandler() 64-bit timer interrupt service
+  routine (ISR) in order to prevent the same interrupt event retriggering a
+  call to the ISR.
+ */
+static __INLINE void MSS_TIM64_clear_irq(void)
+{
+    TIMER->TIM64_RIS = 1u;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*MSS_TIMER_H_*/
diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_uart/mss_uart.c b/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_uart/mss_uart.c
new file mode 100644
index 000000000..3db4c72c6
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_uart/mss_uart.c
@@ -0,0 +1,1762 @@
+/*******************************************************************************
+ * (c) Copyright 2011-2013 Microsemi SoC Products Group.  All rights reserved.
+ *
+ * SmartFusion2 Microcontroller Subsystem MMUART bare metal software driver
+ * implementation.
+ *
+ * SVN $Revision: 5610 $
+ * SVN $Date: 2013-04-05 14:19:30 +0100 (Fri, 05 Apr 2013) $
+ */
+#include "mss_uart.h"
+#include "mss_uart_regs.h"
+#include "../../CMSIS/mss_assert.h"
+#include "../../CMSIS/hw_reg_io.h"
+#include "../../CMSIS/system_m2sxxx.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif 
+
+/*******************************************************************************
+ * Defines
+ */
+#define TX_COMPLETE            0u
+#define TX_FIFO_SIZE           16u
+
+#define FCR_TRIG_LEVEL_MASK    0xC0u
+
+#define IIRF_MASK              0x0Fu
+
+#define INVALID_INTERRUPT      0u
+#define INVALID_IRQ_HANDLER    ((mss_uart_irq_handler_t) 0)
+#define NULL_HANDLER           ((mss_uart_irq_handler_t) 0)
+
+#define MSS_UART_DATA_READY    ((uint8_t) 0x01)
+
+#define SYNC_ASYNC_MODE_MASK   (0x7u)
+
+/*******************************************************************************
+ * Possible values for Interrupt Identification Register Field.
+ */
+#define IIRF_MODEM_STATUS   0x00u
+#define IIRF_THRE           0x02u
+#define IIRF_MMI            0x03u
+#define IIRF_RX_DATA        0x04u
+#define IIRF_RX_LINE_STATUS 0x06u
+#define IIRF_DATA_TIMEOUT   0x0Cu
+
+/*******************************************************************************
+ * Receiver error status mask.
+ */
+#define STATUS_ERROR_MASK    ( MSS_UART_OVERUN_ERROR | MSS_UART_PARITY_ERROR | \
+                               MSS_UART_FRAMING_ERROR  | MSS_UART_BREAK_ERROR | \
+                               MSS_UART_FIFO_ERROR)
+
+/*******************************************************************************
+ * Cortex-M3 interrupt handler functions implemented as part of the MSS UART
+ * driver.
+ */
+#if defined(__GNUC__)
+__attribute__((__interrupt__)) void UART0_IRQHandler(void);
+#else
+void UART0_IRQHandler(void);
+#endif
+
+#if defined(__GNUC__)
+__attribute__((__interrupt__)) void UART1_IRQHandler(void);
+#else
+void UART1_IRQHandler(void);
+#endif
+
+/*******************************************************************************
+ * Local functions.
+ */
+static void global_init(mss_uart_instance_t * this_uart, uint32_t baud_rate, 
+                        uint8_t line_config);
+static void MSS_UART_isr(mss_uart_instance_t * this_uart);
+static void default_tx_handler(mss_uart_instance_t * this_uart);
+
+static void config_baud_divisors
+(
+    mss_uart_instance_t * this_uart,
+    uint32_t baudrate    
+);
+
+/*******************************************************************************
+ * Instance definitions
+ */
+mss_uart_instance_t g_mss_uart0;
+mss_uart_instance_t g_mss_uart1;
+
+
+/*******************************************************************************
+ * Public Functions
+ *******************************************************************************/
+/***************************************************************************//**
+ * See mss_uart.h for details of how to use this function.
+ */
+void 
+MSS_UART_init
+(
+    mss_uart_instance_t* this_uart, 
+    uint32_t baud_rate,
+    uint8_t line_config
+)
+{
+    /* The driver expects g_mss_uart0 and g_mss_uart1 to be the only
+     * mss_uart_instance_t instances used to identify UART0 and UART1. */
+    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
+
+    /* Perform generic initialization */
+    global_init(this_uart, baud_rate, line_config);
+
+    /* Disable LIN mode */
+    clear_bit_reg8(&this_uart->hw_reg->MM0, ELIN);
+
+    /* Disable IrDA mode */
+    clear_bit_reg8(&this_uart->hw_reg->MM1, EIRD);
+
+    /* Disable SmartCard Mode */
+    clear_bit_reg8(&this_uart->hw_reg->MM2, EERR);
+
+    /* set default tx handler for automated TX using interrupt in USART mode */
+    this_uart->tx_handler = default_tx_handler;
+}
+
+/***************************************************************************//**
+ * See mss_uart.h for details of how to use this function.
+ */
+void MSS_UART_lin_init
+(
+    mss_uart_instance_t* this_uart, 
+    uint32_t baud_rate,
+    uint8_t line_config
+)
+{
+    /* The driver expects g_mss_uart0 and g_mss_uart1 to be the only
+     * mss_uart_instance_t instances used to identify UART0 and UART1. */
+    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
+
+    /* Perform generic initialization */
+    global_init(this_uart, baud_rate, line_config);
+
+     /* Enable LIN mode */
+    set_bit_reg8(&this_uart->hw_reg->MM0, ELIN);
+
+    /* Disable IrDA mode */
+    clear_bit_reg8(&this_uart->hw_reg->MM1, EIRD);
+
+    /* Disable SmartCard Mode */
+    clear_bit_reg8(&this_uart->hw_reg->MM2, EERR);
+}
+
+/***************************************************************************//**
+ * See mss_uart.h for details of how to use this function.
+ */
+void 
+MSS_UART_irda_init
+(
+    mss_uart_instance_t* this_uart, 
+    uint32_t baud_rate,
+    uint8_t line_config,
+    mss_uart_rzi_polarity_t rxpol,
+    mss_uart_rzi_polarity_t txpol,
+    mss_uart_rzi_pulsewidth_t pw
+)
+{
+    /* The driver expects g_mss_uart0 and g_mss_uart1 to be the only
+     * mss_uart_instance_t instances used to identify UART0 and UART1. */
+    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
+
+    /* Perform generic initialization */
+    global_init(this_uart, baud_rate, line_config);
+
+     /* Enable LIN mode */
+    clear_bit_reg8(&this_uart->hw_reg->MM0, ELIN);
+
+    /* Disable IrDA mode */
+    set_bit_reg8(&this_uart->hw_reg->MM1, EIRD);
+    ((rxpol == MSS_UART_ACTIVE_LOW) ? clear_bit_reg8(&this_uart->hw_reg->MM1,EIRX) : 
+                                      set_bit_reg8(&this_uart->hw_reg->MM1,EIRX));
+                                      
+    ((txpol == MSS_UART_ACTIVE_LOW) ? clear_bit_reg8(&this_uart->hw_reg->MM1,EITX) : 
+                                      set_bit_reg8(&this_uart->hw_reg->MM1,EITX));
+                                      
+    ((pw == MSS_UART_3_BY_16) ? clear_bit_reg8(&this_uart->hw_reg->MM1,EITP) : 
+                                      set_bit_reg8(&this_uart->hw_reg->MM1,EITP));
+    /* Disable SmartCard Mode */
+    clear_bit_reg8(&this_uart->hw_reg->MM2, EERR);
+}
+
+/***************************************************************************//**
+ * See mss_uart.h for details of how to use this function.
+ */
+void 
+MSS_UART_smartcard_init
+(
+    mss_uart_instance_t* this_uart, 
+    uint32_t baud_rate,
+    uint8_t line_config
+)
+{
+    /* The driver expects g_mss_uart0 and g_mss_uart1 to be the only
+     * mss_uart_instance_t instances used to identify UART0 and UART1. */
+    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
+
+    /* Perform generic initialization */
+    global_init(this_uart, baud_rate, line_config);
+    
+    /* Disable LIN mode */
+    clear_bit_reg8(&this_uart->hw_reg->MM0, ELIN);
+
+    /* Disable IrDA mode */
+    clear_bit_reg8(&this_uart->hw_reg->MM1, EIRD);
+
+    /* Enable SmartCard Mode : Only when data is 8-bit and 2 stop bits*/
+    if( ( MSS_UART_DATA_8_BITS | MSS_UART_TWO_STOP_BITS) == 
+        (line_config & (MSS_UART_DATA_8_BITS | MSS_UART_TWO_STOP_BITS)))
+    {
+        set_bit_reg8(&this_uart->hw_reg->MM2, EERR);    
+        /* Enable single wire half-duplex mode */
+        set_bit_reg8(&this_uart->hw_reg->MM2,ESWM);
+    }
+}
+
+/***************************************************************************//**
+ * See mss_uart.h for details of how to use this function.
+ */
+void
+MSS_UART_polled_tx
+(
+    mss_uart_instance_t * this_uart,
+    const uint8_t * pbuff,
+    uint32_t tx_size
+)
+{
+    uint32_t char_idx = 0u;
+    uint32_t size_sent;
+    uint8_t status;
+
+    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
+    ASSERT(pbuff != ( (uint8_t *)0));
+    ASSERT(tx_size > 0u);
+
+    if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) &&
+        (pbuff != ((uint8_t *)0)) && (tx_size > 0u))
+    {
+         /* Remain in this loop until the entire input buffer
+          * has been transferred to the UART.
+          */
+        do {
+            /* Read the Line Status Register and update the sticky record */
+            status = this_uart->hw_reg->LSR;
+            this_uart->status |= status;
+
+            /* Check if TX FIFO is empty. */
+            if(status & MSS_UART_THRE)
+            {
+                uint32_t fill_size = TX_FIFO_SIZE;
+
+                /* Calculate the number of bytes to transmit. */
+                if(tx_size < TX_FIFO_SIZE)
+                {
+                    fill_size = tx_size;
+                }
+
+                /* Fill the TX FIFO with the calculated the number of bytes. */
+                for(size_sent = 0u; size_sent < fill_size; ++size_sent)
+                {
+                    /* Send next character in the buffer. */
+                    this_uart->hw_reg->THR = pbuff[char_idx];
+                    char_idx++;
+                }
+
+                /* Calculate the number of untransmitted bytes remaining. */
+                tx_size -= size_sent;
+            }
+        } while(tx_size);
+    }
+}
+
+/***************************************************************************//**
+ * See mss_uart.h for details of how to use this function.
+ */
+void
+MSS_UART_polled_tx_string
+(
+    mss_uart_instance_t * this_uart,
+    const uint8_t * p_sz_string
+)
+{
+    uint32_t char_idx = 0u;
+    uint32_t fill_size;
+    uint8_t data_byte;
+    uint8_t status;
+
+    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
+    ASSERT(p_sz_string != ((uint8_t *)0));
+
+    if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) &&
+       (p_sz_string != ((uint8_t *)0)))
+    {
+        /* Get the first data byte from the input buffer */
+        data_byte = p_sz_string[char_idx];
+
+        /* First check for the NULL terminator byte.
+         * Then remain in this loop until the entire string in the input buffer
+         * has been transferred to the UART.
+         */
+        while(0u != data_byte)
+        {
+            /* Wait until TX FIFO is empty. */
+            do {
+                status = this_uart->hw_reg->LSR;
+                this_uart->status |= status;
+            } while (0u == (status & MSS_UART_THRE));
+
+            /* Send bytes from the input buffer until the TX FIFO is full
+             * or we reach the NULL terminator byte.
+             */
+            fill_size = 0u;
+            while((0u != data_byte) && (fill_size < TX_FIFO_SIZE))
+            {
+                /* Send the data byte */
+                this_uart->hw_reg->THR = data_byte;
+                ++fill_size;
+                char_idx++;
+                /* Get the next data byte from the input buffer */
+                data_byte = p_sz_string[char_idx];
+            }
+        }
+    }
+}
+
+/***************************************************************************//**
+ * See mss_uart.h for details of how to use this function.
+ */
+void
+MSS_UART_irq_tx
+(
+    mss_uart_instance_t * this_uart,
+    const uint8_t * pbuff,
+    uint32_t tx_size
+)
+{
+    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
+    ASSERT(pbuff != ((uint8_t *)0));
+    ASSERT(tx_size > 0u);
+
+    if((tx_size > 0u) && ( pbuff != ((uint8_t *)0)) &&
+      ((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)))
+    {
+        /*Initialise the transmit info for the UART instance with the arguments.*/
+        this_uart->tx_buffer = pbuff;
+        this_uart->tx_buff_size = tx_size;
+        this_uart->tx_idx = (uint16_t)0;
+
+        /* Clear any previously pended interrupts */
+        NVIC_ClearPendingIRQ(this_uart->irqn);
+
+        /* assign default handler for data transfer */
+        this_uart->tx_handler = default_tx_handler;
+
+        /* enables TX interrupt */
+        set_bit_reg8(&this_uart->hw_reg->IER,ETBEI);
+
+        /* Enable UART instance interrupt in Cortex-M3 NVIC. */
+        NVIC_EnableIRQ(this_uart->irqn);
+    }
+}
+
+/***************************************************************************//**
+ * See mss_uart.h for details of how to use this function.
+ */
+int8_t
+MSS_UART_tx_complete
+(
+    mss_uart_instance_t * this_uart
+)
+{
+    int8_t ret_value = 0;
+    uint8_t status = 0u;
+
+    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
+
+    if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1))
+    {
+        /* Read the Line Status Register and update the sticky record. */
+        status = this_uart->hw_reg->LSR;
+        this_uart->status |= status;
+
+        if((TX_COMPLETE == this_uart->tx_buff_size) &&
+           ((status & MSS_UART_TEMT) != 0u))
+        {
+            ret_value = (int8_t)1;
+        }
+    }
+    return ret_value;
+}
+
+
+/***************************************************************************//**
+ * See mss_uart.h for details of how to use this function.
+ */
+size_t
+MSS_UART_get_rx
+(
+    mss_uart_instance_t * this_uart,
+    uint8_t * rx_buff,
+    size_t buff_size
+)
+{
+    size_t rx_size = 0u;
+    uint8_t status = 0u;
+
+    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
+    ASSERT(rx_buff != ((uint8_t *)0));
+    ASSERT(buff_size > 0u);
+
+    if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) &&
+       (rx_buff != ((uint8_t *)0)) && (buff_size > 0u))
+    {
+        status = this_uart->hw_reg->LSR;
+        this_uart->status |= status;
+
+        while(((status & MSS_UART_DATA_READY) != 0u) &&
+              (rx_size < buff_size))
+        {
+            rx_buff[rx_size] = this_uart->hw_reg->RBR;
+            ++rx_size;
+            status = this_uart->hw_reg->LSR;
+            this_uart->status |= status;
+        }
+    }
+    return rx_size;
+}
+/***************************************************************************//**
+ * See mss_uart.h for details of how to use this function.
+ */
+void
+MSS_UART_enable_irq
+(
+    mss_uart_instance_t * this_uart,
+    mss_uart_irq_t irq_mask
+)
+{
+    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
+    ASSERT(MSS_UART_INVALID_IRQ > irq_mask);
+
+    if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) && 
+       (MSS_UART_INVALID_IRQ > irq_mask))
+    {
+        /* Clear any previously pended interrupts */
+        NVIC_ClearPendingIRQ(this_uart->irqn);
+
+        /* irq_mask encoding: 1- enable
+         * bit 0 - Receive Data Available Interrupt
+         * bit 1 - Transmitter Holding  Register Empty Interrupt
+         * bit 2 - Receiver Line Status Interrupt
+         * bit 3 - Modem Status Interrupt
+         */
+        this_uart->hw_reg->IER |= (uint8_t)irq_mask & IIRF_MASK;
+
+        /* 
+         * bit 4 - Receiver time-out interrupt
+         * bit 5 - NACK / ERR signal interrupt
+         * bit 6 - PID parity error interrupt 
+         * bit 7 - LIN break detection interrupt
+         * bit 8 - LIN Sync detection interrupt
+         */
+        this_uart->hw_reg->IEM |= (uint8_t)(((uint32_t)irq_mask & ~((uint32_t)IIRF_MASK)) >> 4u);
+
+        /* Enable UART instance interrupt in Cortex-M3 NVIC. */
+        NVIC_EnableIRQ(this_uart->irqn);
+    }
+}
+
+/***************************************************************************//**
+ * See mss_uart.h for details of how to use this function.
+ */
+void
+MSS_UART_disable_irq
+(
+    mss_uart_instance_t * this_uart,
+    mss_uart_irq_t irq_mask
+)
+{
+    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
+
+    if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1))
+    {
+        /* irq_mask encoding: 1 - disable
+         * bit 0 - Receive Data Available Interrupt
+         * bit 1 - Transmitter Holding  Register Empty Interrupt
+         * bit 2 - Receiver Line Status Interrupt
+         * bit 3 - Modem Status Interrupt
+         */
+        this_uart->hw_reg->IER &= ((uint8_t)(~((uint32_t)irq_mask & (uint32_t)IIRF_MASK)));
+
+        /* 
+         * bit 4 - Receiver time-out interrupt
+         * bit 5 - NACK / ERR signal interrupt
+         * bit 6 - PID parity error interrupt 
+         * bit 7 - LIN break detection interrupt
+         * bit 8 - LIN Sync detection interrupt
+         */
+        this_uart->hw_reg->IEM |= (uint8_t)(~(((uint32_t)irq_mask & ~((uint32_t)IIRF_MASK)) >> 8u));
+
+        /* Clear any previously pended interrupts */
+        NVIC_ClearPendingIRQ(this_uart->irqn);
+
+        if(irq_mask == IIRF_MASK)
+        {
+            /* Disable UART instance interrupt in Cortex-M3 NVIC. */
+            NVIC_DisableIRQ(this_uart->irqn);
+
+        }
+    }
+}
+
+/***************************************************************************//**
+ * See mss_uart.h for details of how to use this function.
+ */
+void
+MSS_UART_set_rx_handler
+(
+    mss_uart_instance_t *       this_uart,
+    mss_uart_irq_handler_t      handler,
+    mss_uart_rx_trig_level_t    trigger_level
+)
+{
+    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
+    ASSERT(handler != INVALID_IRQ_HANDLER );
+    ASSERT(trigger_level < MSS_UART_FIFO_INVALID_TRIG_LEVEL);
+
+    if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) &&
+       (handler != INVALID_IRQ_HANDLER) &&
+       (trigger_level < MSS_UART_FIFO_INVALID_TRIG_LEVEL))
+    {
+        this_uart->rx_handler = handler;
+
+        /* Set the receive interrupt trigger level. */
+        this_uart->hw_reg->FCR = (this_uart->hw_reg->FCR &
+                                 (uint8_t)(~((uint8_t)FCR_TRIG_LEVEL_MASK))) |
+                                 (uint8_t)trigger_level;
+        /* Clear any previously pended interrupts */
+        NVIC_ClearPendingIRQ(this_uart->irqn);
+
+        /* Enable receive interrupt. */
+        set_bit_reg8(&this_uart->hw_reg->IER,ERBFI);
+
+        /* Enable UART instance interrupt in Cortex-M3 NVIC. */
+        NVIC_EnableIRQ(this_uart->irqn);
+    }
+}
+
+/***************************************************************************//**
+ * See mss_uart.h for details of how to use this function.
+ */
+void
+MSS_UART_set_loopback
+(
+    mss_uart_instance_t *   this_uart,
+    mss_uart_loopback_t     loopback
+)
+{
+    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
+    ASSERT(MSS_UART_INVALID_LOOPBACK > loopback);
+
+    if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) ||
+       (MSS_UART_INVALID_LOOPBACK > loopback))
+    {
+        switch(loopback)
+        {
+            case MSS_UART_LOCAL_LOOPBACK_OFF:
+                /* Disable local loopback */
+                clear_bit_reg8(&this_uart->hw_reg->MCR,LOOP);
+                break;
+                
+            case MSS_UART_LOCAL_LOOPBACK_ON:
+                /* Enable local loopback */
+                set_bit_reg8(&this_uart->hw_reg->MCR,LOOP);
+                break;
+            
+            case MSS_UART_REMOTE_LOOPBACK_OFF:
+            case MSS_UART_AUTO_ECHO_OFF:
+                /* Disable remote loopback & automatic echo*/
+                this_uart->hw_reg->MCR &= ~RLOOP_MASK;
+                break;
+            
+            case MSS_UART_REMOTE_LOOPBACK_ON:
+                /* Enable remote loopback */
+                this_uart->hw_reg->MCR |= (1u << RLOOP);
+                break;
+                
+            case MSS_UART_AUTO_ECHO_ON:
+                /* Enable automatic echo */
+                this_uart->hw_reg->MCR |= (1u << ECHO);
+                break;
+                
+            case MSS_UART_INVALID_LOOPBACK:
+                /* Fall through to default. */
+            default:
+                ASSERT(0);
+                break;
+        }
+    }
+}
+
+/***************************************************************************//**
+ * UART0 interrupt service routine.
+ * UART0_IRQHandler is included within the Cortex-M3 vector table as part of the
+ * Fusion 2 CMSIS.
+ */
+#if defined(__GNUC__)
+__attribute__((__interrupt__)) void UART0_IRQHandler(void)
+#else
+void UART0_IRQHandler(void)
+#endif
+{
+    MSS_UART_isr(&g_mss_uart0);
+}
+
+/***************************************************************************//**
+ * UART1 interrupt service routine.
+ * UART2_IRQHandler is included within the Cortex-M3 vector table as part of the
+ * Fusion 2 CMSIS.
+ */
+#if defined(__GNUC__)
+__attribute__((__interrupt__)) void UART1_IRQHandler(void)
+#else
+void UART1_IRQHandler(void)
+#endif
+{
+    MSS_UART_isr(&g_mss_uart1);
+}
+
+/***************************************************************************//**
+ * See mss_uart.h for details of how to use this function.
+ */
+void
+MSS_UART_set_rxstatus_handler
+(
+    mss_uart_instance_t * this_uart,
+    mss_uart_irq_handler_t handler
+)
+{
+    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
+    ASSERT(handler != INVALID_IRQ_HANDLER);
+
+    if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) &&
+       (handler != INVALID_IRQ_HANDLER))
+    {
+        this_uart->linests_handler = handler;
+
+        /* Clear any previously pended interrupts */
+        NVIC_ClearPendingIRQ(this_uart->irqn);
+
+        /* Enable receiver line status interrupt. */
+        set_bit_reg8(&this_uart->hw_reg->IER,ELSI);
+
+        /* Enable UART instance interrupt in Cortex-M3 NVIC. */
+        NVIC_EnableIRQ(this_uart->irqn);
+    }
+}
+
+/***************************************************************************//**
+ * See mss_uart.h for details of how to use this function.
+ */
+void
+MSS_UART_set_tx_handler
+(
+    mss_uart_instance_t * this_uart,
+    mss_uart_irq_handler_t handler
+)
+{
+    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
+    ASSERT(handler != INVALID_IRQ_HANDLER);
+
+    if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) &&
+       (handler != INVALID_IRQ_HANDLER))
+    {
+        this_uart->tx_handler = handler;
+
+        /* Make TX buffer info invalid */
+        this_uart->tx_buffer = (const uint8_t *)0;
+        this_uart->tx_buff_size = 0u;
+
+        /* Clear any previously pended interrupts */
+        NVIC_ClearPendingIRQ(this_uart->irqn);
+
+        /* Enable transmitter holding register Empty interrupt. */
+        set_bit_reg8(&this_uart->hw_reg->IER,ETBEI);
+
+        /* Enable UART instance interrupt in Cortex-M3 NVIC. */
+        NVIC_EnableIRQ(this_uart->irqn);
+    }
+}
+
+/***************************************************************************//**
+ * See mss_uart.h for details of how to use this function.
+ */
+void
+MSS_UART_set_modemstatus_handler
+(
+    mss_uart_instance_t * this_uart,
+    mss_uart_irq_handler_t handler
+)
+{
+    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
+    ASSERT(handler != INVALID_IRQ_HANDLER);
+
+    if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) &&
+       (handler != INVALID_IRQ_HANDLER))
+    {
+        this_uart->modemsts_handler = handler;
+
+        /* Clear any previously pended interrupts */
+        NVIC_ClearPendingIRQ(this_uart->irqn);
+
+        /* Enable modem status interrupt. */
+        set_bit_reg8(&this_uart->hw_reg->IER,EDSSI);
+
+        /* Enable UART instance interrupt in Cortex-M3 NVIC. */
+        NVIC_EnableIRQ(this_uart->irqn);
+    }
+}
+
+/***************************************************************************//**
+ * See mss_uart.h for details of how to use this function.
+ */
+size_t
+MSS_UART_fill_tx_fifo
+(
+    mss_uart_instance_t * this_uart,
+    const uint8_t * tx_buffer,
+    size_t tx_size
+)
+{
+    uint8_t status = 0u;
+    size_t size_sent = 0u;
+
+    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
+    ASSERT(tx_buffer != ( (uint8_t *)0));
+    ASSERT(tx_size > 0);
+
+    /* Fill the UART's Tx FIFO until the FIFO is full or the complete input
+     * buffer has been written. */
+    if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) &&
+       (tx_buffer != ((uint8_t *)0))   &&
+       (tx_size > 0u))
+    {
+        status = this_uart->hw_reg->LSR;
+        this_uart->status |= status;
+
+        if(status & MSS_UART_THRE)
+        {
+            uint32_t fill_size = TX_FIFO_SIZE;
+
+            if(tx_size < TX_FIFO_SIZE)
+            {
+                fill_size = tx_size;
+            }
+            /* Fill up FIFO */
+            for(size_sent = 0u; size_sent < fill_size; ++size_sent)
+            {
+
+                /* Send next character in the buffer. */
+                this_uart->hw_reg->THR = tx_buffer[size_sent];
+            }
+        }
+    }
+    return size_sent;
+}
+
+/***************************************************************************//**
+ * See mss_uart.h for details of how to use this function.
+ */
+uint8_t
+MSS_UART_get_rx_status
+(
+    mss_uart_instance_t * this_uart
+)
+{
+    uint8_t status = MSS_UART_INVALID_PARAM;
+
+    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
+
+    if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1))
+    {
+        /*
+         * Extract UART receive error status.
+         * Bit 1 - Overflow error status
+         * Bit 2 - Parity error status
+         * Bit 3 - Frame error status
+         * Bit 4 - Break interrupt indicator
+         * Bit 7 - FIFO data error status
+         */
+        this_uart->status |= (this_uart->hw_reg->LSR);
+        status = (this_uart->status & STATUS_ERROR_MASK);
+        /* Clear the sticky status after reading */
+        this_uart->status = 0u;
+    }
+    return status;
+}
+
+/***************************************************************************//**
+ * See mss_uart.h for details of how to use this function.
+ */
+uint8_t
+MSS_UART_get_modem_status
+(
+    mss_uart_instance_t * this_uart
+)
+{
+    uint8_t status = MSS_UART_INVALID_PARAM;
+
+    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
+
+    if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1))
+    {
+        /*
+         * Extract UART modem status and place in lower bits of "status".
+         * Bit 0 - Delta Clear to Send Indicator
+         * Bit 1 - Delta Clear to Receive Indicator
+         * Bit 2 - Trailing edge of Ring Indicator detector
+         * Bit 3 - Delta Data Carrier Detect indicator
+         * Bit 4 - Clear To Send
+         * Bit 5 - Data Set Ready
+         * Bit 6 - Ring Indicator
+         * Bit 7 - Data Carrier Detect
+         */
+        status = this_uart->hw_reg->MSR;
+    }
+    return status;
+}
+
+/***************************************************************************//**
+ * MSS_UART_get_tx_status.
+ * See mss_uart.h for details of how to use this function.
+ */
+uint8_t
+MSS_UART_get_tx_status
+(
+    mss_uart_instance_t * this_uart
+)
+{
+    uint8_t status = MSS_UART_TX_BUSY;
+
+    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
+
+    if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1))
+    {
+        /* Read the Line Status Register and update the sticky record. */
+        status = this_uart->hw_reg->LSR;
+        this_uart->status |= status;
+        /*
+         * Extract the transmit status bits from the UART's Line Status Register.
+         * Bit 5 - Transmitter Holding Register/FIFO Empty (THRE) status. (If = 1, TX FIFO is empty)
+         * Bit 6 - Transmitter Empty (TEMT) status. (If = 1, both TX FIFO and shift register are empty)
+         */
+        status &= (MSS_UART_THRE | MSS_UART_TEMT);
+    }
+    return status;
+}
+
+/***************************************************************************//**
+ * See mss_uart.h for details of how to use this function.
+ */
+void
+MSS_UART_set_break
+(
+    mss_uart_instance_t * this_uart
+)
+{
+    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
+    if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1))
+    {
+        /* set break charecter on Tx line */
+        set_bit_reg8(&this_uart->hw_reg->LCR,SB);
+    }
+}
+
+/***************************************************************************//**
+ * See mss_uart.h for details of how to use this function.
+ */
+void
+MSS_UART_clear_break
+(
+    mss_uart_instance_t * this_uart
+)
+{
+    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
+    if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1))
+    {
+        /* remove break charecter from Tx line */
+        clear_bit_reg8(&this_uart->hw_reg->LCR,SB);
+    }
+}
+
+/***************************************************************************//**
+ * See mss_uart.h for details of how to use this function.
+ */
+void
+MSS_UART_set_pidpei_handler
+(
+    mss_uart_instance_t * this_uart,
+    mss_uart_irq_handler_t handler
+)
+{
+    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
+    ASSERT(handler != INVALID_IRQ_HANDLER);
+
+    if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) &&
+       (handler != INVALID_IRQ_HANDLER))
+    {
+        this_uart->pid_pei_handler = handler;
+
+        /* Clear any previously pended interrupts */
+        NVIC_ClearPendingIRQ( this_uart->irqn );
+
+        /* Enable PID parity error interrupt. */
+        set_bit_reg8(&this_uart->hw_reg->IEM,EPID_PEI);
+
+        /* Enable UART instance interrupt in Cortex-M3 NVIC. */
+        NVIC_EnableIRQ(this_uart->irqn);
+    }
+}
+
+/***************************************************************************//**
+ * See mss_uart.h for details of how to use this function.
+ */
+void
+MSS_UART_set_linbreak_handler
+(
+    mss_uart_instance_t * this_uart,
+    mss_uart_irq_handler_t handler
+)
+{
+    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
+    ASSERT(handler != INVALID_IRQ_HANDLER);
+
+    if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) &&
+       (handler != INVALID_IRQ_HANDLER))
+    {
+        this_uart->break_handler = handler;
+
+        /* Clear any previously pended interrupts */
+        NVIC_ClearPendingIRQ( this_uart->irqn );
+
+        /* Enable LIN break detection interrupt. */
+        set_bit_reg8(&this_uart->hw_reg->IEM,ELINBI);
+
+        /* Enable UART instance interrupt in Cortex-M3 NVIC. */
+        NVIC_EnableIRQ(this_uart->irqn);
+    }
+}
+
+/***************************************************************************//**
+ * See mss_uart.h for details of how to use this function.
+ */
+void
+MSS_UART_set_linsync_handler
+(
+    mss_uart_instance_t * this_uart,
+    mss_uart_irq_handler_t handler
+)
+{
+    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
+    ASSERT(handler != INVALID_IRQ_HANDLER);
+
+    if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) &&
+       (handler != INVALID_IRQ_HANDLER))
+    {
+        this_uart->sync_handler = handler;
+
+        /* Clear any previously pended interrupts */
+        NVIC_ClearPendingIRQ( this_uart->irqn );
+
+        /* Enable LIN sync detection interrupt. */
+        set_bit_reg8(&this_uart->hw_reg->IEM,ELINSI);
+
+        /* Enable UART instance interrupt in Cortex-M3 NVIC. */
+        NVIC_EnableIRQ(this_uart->irqn);
+    }
+}
+
+/***************************************************************************//**
+ * See mss_uart.h for details of how to use this function.
+ */
+void
+MSS_UART_set_nack_handler
+(
+    mss_uart_instance_t * this_uart,
+    mss_uart_irq_handler_t handler
+)
+{
+    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
+    ASSERT(handler != INVALID_IRQ_HANDLER);
+
+    if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) &&
+       (handler != INVALID_IRQ_HANDLER))
+    {
+        this_uart->nack_handler = handler;
+
+        /* Clear any previously pended interrupts */
+        NVIC_ClearPendingIRQ( this_uart->irqn );
+
+        /* Enable LIN sync detection interrupt. */
+        set_bit_reg8(&this_uart->hw_reg->IEM,ENACKI);
+
+        /* Enable UART instance interrupt in Cortex-M3 NVIC. */
+        NVIC_EnableIRQ(this_uart->irqn);
+    }
+}
+
+/***************************************************************************//**
+ * See mss_uart.h for details of how to use this function.
+ */
+void
+MSS_UART_set_rx_timeout_handler
+(
+    mss_uart_instance_t * this_uart,
+    mss_uart_irq_handler_t handler
+)
+{
+    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
+    ASSERT(handler != INVALID_IRQ_HANDLER);
+
+    if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) &&
+       (handler != INVALID_IRQ_HANDLER))
+    {
+        this_uart->rto_handler = handler;
+
+        /* Clear any previously pended interrupts */
+        NVIC_ClearPendingIRQ( this_uart->irqn );
+
+        /* Enable receiver timeout interrupt. */
+        set_bit_reg8(&this_uart->hw_reg->IEM,ERTOI);
+
+        /* Enable UART instance interrupt in Cortex-M3 NVIC. */
+        NVIC_EnableIRQ(this_uart->irqn);
+    }
+}
+
+/***************************************************************************//**
+ * See mss_uart.h for details of how to use this function.
+ */
+void 
+MSS_UART_enable_half_duplex
+(
+    mss_uart_instance_t * this_uart
+)
+{
+    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
+    if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1))
+    {
+        /* enable single wire half-duplex mode */
+        set_bit_reg8(&this_uart->hw_reg->MM2,ESWM);
+    }
+}
+
+/***************************************************************************//**
+ * See mss_uart.h for details of how to use this function.
+ */
+void 
+MSS_UART_disable_half_duplex
+(
+    mss_uart_instance_t * this_uart
+)
+{
+    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
+    if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1))
+    {
+        /* enable single wire half-duplex mode */
+        clear_bit_reg8(&this_uart->hw_reg->MM2,ESWM);
+    }
+}
+
+/***************************************************************************//**
+ * See mss_uart.h for details of how to use this function.
+ */
+void
+MSS_UART_set_rx_endian
+(
+    mss_uart_instance_t * this_uart,
+    mss_uart_endian_t endian    
+)
+{
+    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
+    ASSERT(MSS_UART_INVALID_ENDIAN > endian);
+
+    if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) && 
+       (MSS_UART_INVALID_ENDIAN > endian))
+    {
+        /* Configure MSB first / LSB first for receiver */
+        ((MSS_UART_LITTLEEND == endian) ? (clear_bit_reg8(&this_uart->hw_reg->MM1,E_MSB_RX)) :
+                                          (set_bit_reg8(&this_uart->hw_reg->MM1,E_MSB_RX)));
+    }
+}
+
+/***************************************************************************//**
+ * See mss_uart.h for details of how to use this function.
+ */
+void
+MSS_UART_set_tx_endian
+(
+    mss_uart_instance_t * this_uart,
+    mss_uart_endian_t endian    
+)
+{
+    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
+    ASSERT(MSS_UART_INVALID_ENDIAN > endian);
+
+    if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) && 
+       (MSS_UART_INVALID_ENDIAN > endian))
+    {
+        /* Configure MSB first / LSB first for transmitter */
+        ((MSS_UART_LITTLEEND == endian) ? (clear_bit_reg8(&this_uart->hw_reg->MM1,E_MSB_TX)) :
+                                          (set_bit_reg8(&this_uart->hw_reg->MM1,E_MSB_TX)) ) ;
+    }
+}
+
+/***************************************************************************//**
+ * See mss_uart.h for details of how to use this function.
+ */
+void
+MSS_UART_set_filter_length
+(
+    mss_uart_instance_t * this_uart,
+    mss_uart_filter_length_t length
+)
+{
+    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
+    ASSERT(MSS_UART_INVALID_FILTER_LENGTH > length);
+    
+    if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) && 
+       (MSS_UART_INVALID_FILTER_LENGTH > length))
+    {
+        /* Configure glitch filter length */
+        this_uart->hw_reg->GFR = (uint8_t)length;
+    }
+}
+
+/***************************************************************************//**
+ * See mss_uart.h for details of how to use this function.
+ */
+void
+MSS_UART_enable_afm
+(
+     mss_uart_instance_t * this_uart
+)
+{
+    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
+
+    if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1))
+    {
+        /* Disable RX FIFO till address flag with correct address is received */
+        set_bit_reg8(&this_uart->hw_reg->MM2,EAFM);
+    }
+}
+
+/***************************************************************************//**
+ * See mss_uart.h for details of how to use this function.
+ */
+void
+MSS_UART_disable_afm
+(
+     mss_uart_instance_t * this_uart
+)
+{
+    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
+
+    if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1))
+    {
+        /* Enable RX FIFO irrespective of address flag and
+           correct address is received */
+        clear_bit_reg8(&this_uart->hw_reg->MM2,EAFM);
+    }
+}
+
+/***************************************************************************//**
+ * See mss_uart.h for details of how to use this function.
+ */
+void
+MSS_UART_enable_afclear
+(
+     mss_uart_instance_t * this_uart
+)
+{
+    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
+
+    if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1))
+    {
+        /* Enable address flag clearing */
+        /* Disable RX FIFO till another address flag with 
+           correct address is received */
+        set_bit_reg8(&this_uart->hw_reg->MM2,EAFC);
+    }
+}
+
+/***************************************************************************//**
+ * See mss_uart.h for details of how to use this function.
+ */
+void
+MSS_UART_disable_afclear
+(
+     mss_uart_instance_t * this_uart
+)
+{
+    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
+
+    if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1))
+    {
+        /* Disable address flag clearing */
+        clear_bit_reg8(&this_uart->hw_reg->MM2,EAFC);
+    }
+}
+
+/***************************************************************************//**
+ * See mss_uart.h for details of how to use this function.
+ */
+void 
+MSS_UART_enable_rx_timeout
+(
+    mss_uart_instance_t * this_uart,
+    uint8_t timeout
+)
+{
+    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
+
+    if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1))
+    {
+        /* Load the receive timeout value */
+        this_uart->hw_reg->RTO = timeout;
+        /*Enable receiver time-out */
+        set_bit_reg8(&this_uart->hw_reg->MM0,ERTO);
+    }
+}
+
+/***************************************************************************//**
+ * See mss_uart.h for details of how to use this function.
+ */
+void 
+MSS_UART_disable_rx_timeout
+(
+    mss_uart_instance_t * this_uart
+)
+{
+    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
+
+    if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1))
+    {
+        /*Disable receiver time-out */
+        clear_bit_reg8(&this_uart->hw_reg->MM0,ERTO);
+    }
+}
+
+/***************************************************************************//**
+ * See mss_uart.h for details of how to use this function.
+ */
+void 
+MSS_UART_enable_tx_time_guard
+(
+    mss_uart_instance_t * this_uart,
+    uint8_t timeguard
+)
+{
+    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
+
+    if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1))
+    {
+        /* Load the transmitter time guard value */
+        this_uart->hw_reg->TTG = timeguard;
+        /*Enable transmitter time guard */
+        set_bit_reg8(&this_uart->hw_reg->MM0,ETTG);
+    }
+}
+
+/***************************************************************************//**
+ * See mss_uart.h for details of how to use this function.
+ */
+void 
+MSS_UART_disable_tx_time_guard
+(
+    mss_uart_instance_t * this_uart
+)
+{
+    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
+
+    if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1))
+    {
+        /*Disable transmitter time guard */
+        clear_bit_reg8(&this_uart->hw_reg->MM0,ETTG);
+    }
+}
+
+/***************************************************************************//**
+ * See mss_uart.h for details of how to use this function.
+ */
+void
+MSS_UART_set_address
+(
+    mss_uart_instance_t * this_uart,
+    uint8_t address
+)
+{
+    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
+
+    if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1))
+    {
+        this_uart->hw_reg->ADR = address;
+    }
+}
+
+/***************************************************************************//**
+ * See mss_uart.h for details of how to use this function.
+ */
+void 
+MSS_UART_set_ready_mode
+(
+    mss_uart_instance_t * this_uart,
+    mss_uart_ready_mode_t mode    
+)
+{
+    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
+    ASSERT(MSS_UART_INVALID_READY_MODE > mode);
+
+    if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) &&
+       (MSS_UART_INVALID_READY_MODE > mode ) )
+    {
+        /* Configure mode 0 or mode 1 for TXRDY and RXRDY */
+        ((MSS_UART_READY_MODE0 == mode) ? clear_bit_reg8(&this_uart->hw_reg->FCR,RDYMODE) :
+                                 set_bit_reg8(&this_uart->hw_reg->FCR,RDYMODE) );    
+    }
+}
+
+/***************************************************************************//**
+ * Configure baud divisors using fractional baud rate if possible.
+ */
+static void
+config_baud_divisors
+(
+    mss_uart_instance_t * this_uart,
+    uint32_t baudrate    
+)
+{
+    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
+    
+    if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1))
+    {
+        uint32_t baud_value;
+        uint32_t baud_value_by_64;
+        uint32_t baud_value_by_128;
+        uint32_t fractional_baud_value;
+        uint32_t pclk_freq;
+
+        this_uart->baudrate = baudrate;
+
+        /* Force the value of the CMSIS global variables holding the various system
+          * clock frequencies to be updated. */
+        SystemCoreClockUpdate();
+        if(this_uart == &g_mss_uart0)
+        {
+            pclk_freq = g_FrequencyPCLK0;
+        }
+        else
+        {
+            pclk_freq = g_FrequencyPCLK1;
+        }
+
+        /*
+         * Compute baud value based on requested baud rate and PCLK frequency.
+         * The baud value is computed using the following equation:
+         *      baud_value = PCLK_Frequency / (baud_rate * 16)
+         */
+        baud_value_by_128 = (8u * pclk_freq) / baudrate;
+        baud_value_by_64 = baud_value_by_128 / 2u;
+        baud_value = baud_value_by_64 / 64u;
+        fractional_baud_value = baud_value_by_64 - (baud_value * 64u);
+        fractional_baud_value += (baud_value_by_128 - (baud_value * 128u)) - (fractional_baud_value * 2u);
+        
+        /* Assert if integer baud value fits in 16-bit. */
+        ASSERT(baud_value <= UINT16_MAX);
+    
+        if(baud_value <= (uint32_t)UINT16_MAX)
+        {
+            if(baud_value > 1u)
+            {
+                /* 
+                 * Use Frational baud rate divisors
+                 */
+                /* set divisor latch */
+                set_bit_reg8(&this_uart->hw_reg->LCR,DLAB);
+            
+                /* msb of baud value */
+                this_uart->hw_reg->DMR = (uint8_t)(baud_value >> 8);
+                /* lsb of baud value */
+                this_uart->hw_reg->DLR = (uint8_t)baud_value;
+            
+                /* reset divisor latch */
+                clear_bit_reg8(&this_uart->hw_reg->LCR,DLAB);
+        
+                /* Enable Fractional baud rate */
+                set_bit_reg8(&this_uart->hw_reg->MM0,EFBR);
+        
+                /* Load the fractional baud rate register */
+                ASSERT(fractional_baud_value <= (uint32_t)UINT8_MAX);
+                this_uart->hw_reg->DFR = (uint8_t)fractional_baud_value;
+            }
+            else
+            {
+                /*
+                 * Do NOT use Frational baud rate divisors.
+                 */
+                /* set divisor latch */
+                set_bit_reg8(&this_uart->hw_reg->LCR,DLAB);
+            
+                /* msb of baud value */
+                this_uart->hw_reg->DMR = (uint8_t)(baud_value >> 8u);
+                /* lsb of baud value */
+                this_uart->hw_reg->DLR = (uint8_t)baud_value;
+            
+                /* reset divisor latch */
+                clear_bit_reg8(&this_uart->hw_reg->LCR,DLAB);
+                
+                /* Disable Fractional baud rate */
+                clear_bit_reg8(&this_uart->hw_reg->MM0,EFBR);
+            }
+        }
+    }
+}
+
+/***************************************************************************//**
+ * See mss_uart.h for details of how to use this function.
+ */
+void 
+MSS_UART_set_usart_mode
+(
+    mss_uart_instance_t * this_uart,
+    mss_uart_usart_mode_t mode
+)
+{
+    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
+    ASSERT(MSS_UART_INVALID_SYNC_MODE > mode);
+
+    if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) &&
+       (MSS_UART_INVALID_SYNC_MODE > mode))
+    {
+        /* Nothing to do for the baudrate: operates at PCLK / 2 + glitch filter length */
+        /* Clear the ESYN bits 2:0 */
+        this_uart->hw_reg->MM0 &= ~SYNC_ASYNC_MODE_MASK;
+        this_uart->hw_reg->MM0 |= (uint8_t)mode;
+    }
+}
+
+/*******************************************************************************
+ * Local Functions
+ *******************************************************************************/
+/*******************************************************************************
+ * Global initialization for all modes
+ */
+static void global_init
+(
+    mss_uart_instance_t * this_uart,
+    uint32_t baud_rate,
+    uint8_t line_config
+)
+{
+    /* The driver expects g_mss_uart0 and g_mss_uart1 to be the only
+     * mss_uart_instance_t instances used to identify UART0 and UART1. */
+    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
+
+    if(this_uart == &g_mss_uart0)
+    {
+        this_uart->hw_reg = UART0;
+        this_uart->irqn = UART0_IRQn;
+        /* reset UART0 */
+        SYSREG->SOFT_RST_CR |= SYSREG_MMUART0_SOFTRESET_MASK;
+        /* Clear any previously pended UART0 interrupt */
+        NVIC_ClearPendingIRQ(UART0_IRQn);
+        /* Take UART0 out of reset. */
+        SYSREG->SOFT_RST_CR &= ~SYSREG_MMUART0_SOFTRESET_MASK;
+    }
+    else
+    {
+        this_uart->hw_reg = UART1;
+        this_uart->irqn = UART1_IRQn;
+        /* Reset UART1 */
+        SYSREG->SOFT_RST_CR |= SYSREG_MMUART1_SOFTRESET_MASK;
+        /* Clear any previously pended UART1 interrupt */
+        NVIC_ClearPendingIRQ(UART1_IRQn);
+        /* Take UART1 out of reset. */
+        SYSREG->SOFT_RST_CR &= ~SYSREG_MMUART1_SOFTRESET_MASK;
+    }
+
+    /* disable interrupts */
+    this_uart->hw_reg->IER = 0u;
+
+    /* FIFO configuration */
+    this_uart->hw_reg->FCR = (uint8_t)MSS_UART_FIFO_SINGLE_BYTE;
+    /* clear receiver FIFO */
+    set_bit_reg8(&this_uart->hw_reg->FCR,CLEAR_RX_FIFO);
+    /* clear transmitter FIFO */
+    set_bit_reg8(&this_uart->hw_reg->FCR,CLEAR_TX_FIFO);
+
+    /* set default READY mode : Mode 0*/
+    /* enable RXRDYN and TXRDYN pins. The earlier FCR write to set the TX FIFO
+     * trigger level inadvertently disabled the FCR_RXRDY_TXRDYN_EN bit. */
+    set_bit_reg8(&this_uart->hw_reg->FCR,RXRDY_TXRDYN_EN);
+
+    /* disable loopback : local * remote */
+    clear_bit_reg8(&this_uart->hw_reg->MCR,LOOP);
+    clear_bit_reg8(&this_uart->hw_reg->MCR,RLOOP);
+
+    /* set default TX endian */
+    clear_bit_reg8(&this_uart->hw_reg->MM1,E_MSB_TX);
+    /* set default RX endian */
+    clear_bit_reg8(&this_uart->hw_reg->MM1,E_MSB_RX);
+
+    /* default AFM : disabled */
+    clear_bit_reg8(&this_uart->hw_reg->MM2,EAFM);
+
+    /* disable TX time gaurd */
+    clear_bit_reg8(&this_uart->hw_reg->MM0,ETTG); 
+
+    /* set default RX timeout */
+    clear_bit_reg8(&this_uart->hw_reg->MM0,ERTO); 
+
+    /* disable fractional baud-rate */
+    clear_bit_reg8(&this_uart->hw_reg->MM0,EFBR); 
+
+    /* disable single wire mode */
+    clear_bit_reg8(&this_uart->hw_reg->MM2,ESWM);
+
+    /* set filter to minimum value */
+    this_uart->hw_reg->GFR = 0u;
+    /* set default TX time gaurd */
+    this_uart->hw_reg->TTG = 0u;
+    /* set default RX timeout */
+    this_uart->hw_reg->RTO = 0u;
+    
+    /* 
+     * Configure baud rate divisors. This uses the frational baud rate divisor
+     * where possible to provide the most accurate baud rat possible.
+     */
+    config_baud_divisors(this_uart, baud_rate);
+
+    /* set the line control register (bit length, stop bits, parity) */
+    this_uart->hw_reg->LCR = line_config;
+
+    /* Instance setup */
+    this_uart->baudrate = baud_rate;
+    this_uart->lineconfig = line_config;
+    this_uart->tx_buff_size = TX_COMPLETE;
+    this_uart->tx_buffer = (const uint8_t *)0;
+    this_uart->tx_idx = 0u;
+
+    /* Default handlers for MSS UART interrupts */
+    this_uart->rx_handler       = NULL_HANDLER;
+    this_uart->tx_handler       = NULL_HANDLER;
+    this_uart->linests_handler  = NULL_HANDLER;
+    this_uart->modemsts_handler = NULL_HANDLER;
+    this_uart->rto_handler      = NULL_HANDLER;    
+    this_uart->nack_handler     = NULL_HANDLER;   
+    this_uart->pid_pei_handler  = NULL_HANDLER;
+    this_uart->break_handler    = NULL_HANDLER;    
+    this_uart->sync_handler     = NULL_HANDLER;   
+
+    /* Initialize the sticky status */
+    this_uart->status = 0u;
+}
+
+/***************************************************************************//**
+ * Interrupt service routine triggered by any MSS UART interrupt. This routine
+ * will call the handler function appropriate to the interrupt from the
+ * handlers previously registered with the driver through calls to the
+ * MSS_UART_set_*_handler() functions, or it will call the default_tx_handler()
+ * function in response to transmit interrupts if MSS_UART_irq_tx() is used to
+ * transmit data.
+ */
+static void
+MSS_UART_isr
+(
+    mss_uart_instance_t * this_uart
+)
+{
+    uint8_t iirf;
+
+    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
+
+    if((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1))
+    {
+        iirf = this_uart->hw_reg->IIR & IIRF_MASK;
+
+        switch (iirf)
+        {
+            case IIRF_MODEM_STATUS:  /* Modem status interrupt */
+            {
+                ASSERT(NULL_HANDLER != this_uart->modemsts_handler);
+                if(NULL_HANDLER != this_uart->modemsts_handler)
+                {
+                   (*(this_uart->modemsts_handler))(this_uart);
+                }
+            }
+            break;
+
+            case IIRF_THRE: /* Transmitter Holding Register Empty */
+            {
+                ASSERT(NULL_HANDLER != this_uart->tx_handler);
+                if(NULL_HANDLER != this_uart->tx_handler)
+                {
+                    (*(this_uart->tx_handler))(this_uart);
+                }
+            }
+            break;
+
+            case IIRF_RX_DATA:      /* Received Data Available */
+            case IIRF_DATA_TIMEOUT: /* Received Data Timed-out */
+            {
+                ASSERT(NULL_HANDLER != this_uart->rx_handler);
+                if(NULL_HANDLER != this_uart->rx_handler)
+                {
+                    (*(this_uart->rx_handler))(this_uart);
+                }
+            }
+            break;
+
+            case IIRF_RX_LINE_STATUS:  /* Line Status Interrupt */
+            {
+                ASSERT(NULL_HANDLER != this_uart->linests_handler);
+                if(NULL_HANDLER != this_uart->linests_handler)
+                {
+                   (*(this_uart->linests_handler))(this_uart);
+                }
+            }
+            break;
+
+            case IIRF_MMI:
+            {
+                /* Identify multimode interrupts and handle */
+
+                /* Receiver time-out interrupt */
+                if(read_bit_reg8(&this_uart->hw_reg->IIM,ERTOI))
+                {
+                    ASSERT(NULL_HANDLER != this_uart->rto_handler);
+                    if(NULL_HANDLER != this_uart->rto_handler)
+                    {
+                        (*(this_uart->rto_handler))(this_uart);
+                    }
+                }
+                /* NACK interrupt */
+                if(read_bit_reg8(&this_uart->hw_reg->IIM,ENACKI))
+                {
+                    ASSERT(NULL_HANDLER != this_uart->nack_handler);
+                    if(NULL_HANDLER != this_uart->nack_handler)
+                    {
+                        (*(this_uart->nack_handler))(this_uart);
+                    }
+                }
+
+                /* PID parity error interrupt */
+                if(read_bit_reg8(&this_uart->hw_reg->IIM,EPID_PEI))
+                {
+                    ASSERT(NULL_HANDLER != this_uart->pid_pei_handler);
+                    if(NULL_HANDLER != this_uart->pid_pei_handler)
+                    {
+                        (*(this_uart->pid_pei_handler))(this_uart);
+                    }
+                }
+
+                /* LIN break detection interrupt */
+                if(read_bit_reg8(&this_uart->hw_reg->IIM,ELINBI))
+                {
+                    ASSERT(NULL_HANDLER != this_uart->break_handler);
+                    if(NULL_HANDLER != this_uart->break_handler)
+                    {
+                        (*(this_uart->break_handler))(this_uart);
+                    }
+                }
+
+                /* LIN Sync detection interrupt */
+                if(read_bit_reg8(&this_uart->hw_reg->IIM,ELINSI))
+                {
+                    ASSERT(NULL_HANDLER != this_uart->sync_handler);
+                    if(NULL_HANDLER != this_uart->sync_handler)
+                    {
+                        (*(this_uart->sync_handler))(this_uart);
+                    }
+                }
+                break;
+            }
+
+            default:
+            {
+                ASSERT(INVALID_INTERRUPT);
+            }
+            break;
+        }
+    }
+}
+
+/***************************************************************************//**
+ * See mss_uart.h for details of how to use this function.
+ */
+static void
+default_tx_handler
+(
+    mss_uart_instance_t * this_uart
+)
+{
+    uint8_t status;
+
+    ASSERT((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1));
+    ASSERT(( (uint8_t *)0 ) != this_uart->tx_buffer);
+    ASSERT(0u < this_uart->tx_buff_size);
+
+    if(((this_uart == &g_mss_uart0) || (this_uart == &g_mss_uart1)) &&
+       (((uint8_t *)0 ) != this_uart->tx_buffer) &&
+       (0u < this_uart->tx_buff_size))
+    {
+        /* Read the Line Status Register and update the sticky record. */
+        status = this_uart->hw_reg->LSR;
+        this_uart->status |= status;
+
+        /*
+         * This function should only be called as a result of a THRE interrupt.
+         * Verify that this is true before proceeding to transmit data.
+         */
+        if(status & MSS_UART_THRE)
+        {
+            uint32_t i;
+            uint32_t fill_size = TX_FIFO_SIZE;
+            uint32_t tx_remain = this_uart->tx_buff_size - this_uart->tx_idx;
+
+            /* Calculate the number of bytes to transmit. */
+            if(tx_remain < TX_FIFO_SIZE)
+            {
+                fill_size = tx_remain;
+            }
+
+            /* Fill the TX FIFO with the calculated the number of bytes. */
+            for(i = 0u; i < fill_size; ++i)
+            {
+                /* Send next character in the buffer. */
+                this_uart->hw_reg->THR = this_uart->tx_buffer[this_uart->tx_idx];
+                ++this_uart->tx_idx;
+            }
+        }
+
+        /* Flag Tx as complete if all data has been pushed into the Tx FIFO. */
+        if(this_uart->tx_idx == this_uart->tx_buff_size)
+        {
+            this_uart->tx_buff_size = TX_COMPLETE;
+            /* disables TX interrupt */
+            clear_bit_reg8(&this_uart->hw_reg->IER,ETBEI);
+        }
+    }
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_uart/mss_uart.h b/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_uart/mss_uart.h
new file mode 100644
index 000000000..cdabb786a
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_uart/mss_uart.h
@@ -0,0 +1,2639 @@
+/*******************************************************************************
+ * (c) Copyright 2011-2013 Microsemi SoC Products Group.  All rights reserved.
+ *
+ * SmartFusion2 Microcontroller Subsystem MMUART bare metal software driver
+ * public API.
+ *
+ * SVN $Revision: 5610 $
+ * SVN $Date: 2013-04-05 14:19:30 +0100 (Fri, 05 Apr 2013) $
+ */
+/*=========================================================================*//**
+  @mainpage SmartFusion2 MSS UART Bare Metal Driver.
+  ==============================================================================
+  @section intro_sec Introduction
+  ==============================================================================
+  The SmartFusion2 microcontroller subsystem (MSS) includes two multi-mode UART
+  (MMUART) peripherals for serial communication. This driver provides a set of
+  functions for controlling the MSS MMUARTs  as part of a bare metal system
+  where no operating system is available. These drivers can be adapted for use
+  as part of an operating system, but the implementation of the adaptation layer
+  between this driver and the operating system's driver model is outside the
+  scope of this driver.
+  Note: MSS UART is synonymous with MSS MMUART in this document.
+  
+  ==============================================================================
+  @section hw_dependencies Hardware Flow Dependencies
+  ==============================================================================
+  The configuration of all features of the MSS MMUART peripherals is covered by
+  this driver with the exception of the SmartFusion2 IOMUX configuration.
+  SmartFusion2 allows multiple non-concurrent uses of some external pins through
+  IOMUX configuration. This feature allows optimization of external pin usage by
+  assigning external pins for use by either the microcontroller subsystem or the
+  FPGA fabric. The MSS MMUART serial signals are routed through IOMUXs to the
+  SmartFusion2 device external pins. The MSS MMUART serial signals may also be
+  routed through IOMUXs to the SmartFusion2 FPGA fabric. For more information on
+  IOMUX, refer to the IOMUX section of the SmartFusion2 Microcontroller
+  Subsystem (MSS) User�s Guide.
+  The IOMUXs are configured using the SmartFusion2 MSS configurator tool. You
+  must ensure that the MSS MMUART peripherals are enabled and configured in the
+  SmartFusion2 MSS configurator if you wish to use them. For more information on
+  IOMUXs, refer to the IOMUX section of the SmartFusion2 Microcontroller
+  Subsystem (MSS) User�s Guide.
+  The base address, register addresses and interrupt number assignment for the
+  MSS MMUART peripherals are defined as constants in the SmartFusion2 CMSIS HAL.
+  You must ensure that the latest SmartFusion2 CMSIS HAL is included in the
+  project settings of the software tool chain used to build your project and
+  that it is generated into your project.
+  
+  ==============================================================================
+  @section theory_op Theory of Operation
+  ==============================================================================
+  The MSS MMUART driver functions are grouped into the following categories:
+    - Initialization and configuration functions
+    - Polled transmit and receive functions
+    - Interrupt driven transmit and receive functions
+    
+  --------------------------------
+  Initialization and Configuration
+  --------------------------------
+  The MSS MMUART supports the following four broad modes of operation:
+    - UART or USART mode
+    - LIN mode
+    - IrDA mode
+    - Smartcard or ISO 7816 mode
+  The MSS MMUART driver provides the MSS_UART_init(), MSS_UART_lin_init(),
+  MSS_UART_irda_init() and MSS_UART_smartcard_init() functions to initialize the
+  MSS MMUARTs for operation in one of these modes. One of these initialization
+  functions must be called before any other MSS MMUART driver functions can be
+  called. The MSS MMUART operating modes are mutually exclusive; therefore only
+  one of the initialization functions must be called. The first parameter of the
+  initialization functions is a pointer to one of two global data structures
+  used to store state information for each MSS MMUART. A pointer to these data
+  structures is also used as the first parameter to many of the driver functions
+  to identify which MSS MMUART will be used by the called function. The names of
+  these two data structures are g_mss_uart0 and g_mss_uart1. Therefore, any call
+  to an MSS MMUART function should be of the form 
+  MSS_UART_function_name( &g_mss_uart0, ... ) or
+  MSS_UART_function_name( &g_mss_uart1, ... ).
+  
+  UART or USART Mode
+  For the UART or USART modes of operation, the MSS MMUART driver is initialized
+  through a call to the MSS_UART_init() function. This function takes the UART�s
+  configuration as its parameters. The MSS_UART_init() function must be called
+  before any other MSS MMUART driver functions can be called.
+  The MSS_UART_init() function configures the baud rate based on the input baud
+  rate parameter and if possible uses a fractional baud rate for greater
+  precision. This function disables the LIN, IrDA and SmartCard modes.
+  
+  LIN mode
+  For the LIN mode of operation, the MSS MMUART driver is initialized through a
+  call to the MSS_UART_lin_init() function. This function takes the LIN node�s
+  configuration as its parameters. The MSS_UART_lin_init() function must be
+  called before any other MSS MMUART driver functions can be called. The
+  MSS_UART_lin_init() function configures the baud rate based on the input baud
+  rate parameter and if possible uses a fractional baud rate for greater
+  precision. This function disables the IrDA and SmartCard modes.
+  The driver also provides the following LIN mode configuration functions:
+    - MSS_UART_set_break()
+    - MSS_UART_clear_break()
+    - MSS_UART_set_pidpei_handler()
+    - MSS_UART_set_linbreak_handler()
+    - MSS_UART_set_linsync_handler()
+  Note: These LIN mode configuration functions can only be called after the
+  MSS_UART_lin_init() function is called.
+  
+  IrDA mode
+  For the IrDA mode of operation, the driver is initialized through a call to
+  the MSS_UART_irda_init() function. This function takes the IrDA node�s
+  configuration as its parameters. The MSS_UART_irda_init() function must be
+  called before any other MSS MMUART driver functions can be called. The
+  MSS_UART_irda_init() function configures the baud rate based on the input baud
+  rate parameter and if possible uses a fractional baud rate for greater
+  precision. This function disables the LIN and SmartCard modes.
+  
+  Smartcard or ISO 7816 mode
+  For the Smartcard or ISO 7816 mode of operation, the driver is initialized
+  through a call to the MSS_UART_smartcard_init() function. This function takes
+  the smartcard configuration as its parameters. The MSS_UART_smartcard_init()
+  function must be called before any other MSS MMUART driver functions can be
+  called. The MSS_UART_smartcard_init() function configures the baud rate based
+  on the input baud rate parameter and if possible uses a fractional baud rate
+  for greater precision. This function disables the LIN and IrDA modes.
+  The driver also provides the following Smartcard mode configuration functions:
+    - MSS_UART_enable_halfduplex()
+    - MSS_UART_disable_halfduplex()
+    - MSS_UART_set_nack_handler()
+  Note: These Smartcard mode configuration functions can only be called after
+  the MSS_UART_smartcard_init() function is called.
+  
+  Common Configuration Functions
+  The driver also provides the configuration functions that can be used with all
+  MSS MMUART operating modes. These common configuration functions are as
+  follows:
+    - MSS_UART_set_rx_endian()
+    - MSS_UART_set_tx_endian()
+    - MSS_UART_enable_afclear()
+    - MSS_UART_disable_afclear()
+    - MSS_UART_enable_rx_timeout()
+    - MSS_UART_disable_rx_timeout()
+    - MSS_UART_enable_tx_time_guard()
+    - MSS_UART_disable_tx_time_guard()
+    - MSS_UART_set_address()
+    - MSS_UART_set_ready_mode()
+    - MSS_UART_set_usart_mode()
+    - MSS_UART_set_filter_length()
+    - MSS_UART_enable_afm()
+    - MSS_UART_disable_afm()
+  Note: These configuration functions can only be called after one of the
+        MSS_UART_init(), MSS_UART_lin_init(), MSS_UART_irda_init() or
+        MSS_UART_smartcard_init() functions is called.
+  
+  --------------------------------------  
+  Polled Transmit and Receive Operations
+  --------------------------------------
+  The driver can be used to transmit and receive data once initialized. 
+  Data is transmitted using the MSS_UART_polled_tx() function. This function is
+  blocking, meaning that it will only return once the data passed to the
+  function has been sent to the MSS MMUART hardware transmitter. Data received
+  by the MSS MMUART hardware receiver can be read by the MSS_UART_get_rx()
+  function.
+  The MSS_UART_polled_tx_string() function is provided to transmit a NULL (�\0�)
+  terminated string in polled mode. This function is blocking, meaning that it
+  will only return once the data passed to the function has been sent to the MSS
+  MMUART hardware transmitter.
+  The MSS_UART_fill_tx_fifo() function fills the MSS MMUART hardware transmit
+  FIFO with data from a buffer passed as a parameter and returns the number of
+  bytes transferred to the FIFO. If the transmit FIFO is not empty when the
+  MSS_UART_fill_tx_fifo() function is called it returns immediately without
+  transferring any data to the FIFO.
+  
+  ---------------------------
+  Interrupt Driven Operations
+  ---------------------------
+  The driver can also transmit or receive data under interrupt control, freeing
+  your application to perform other tasks until an interrupt occurs indicating
+  that the driver�s attention is required.
+  
+  Interrupt Handlers
+  The MSS MMUART driver supports all types of interrupt triggered by the MSS
+  MMUART. The driver�s internal top level interrupt handler identifies the
+  source of the MSS MMUART interrupt and calls the corresponding lower level
+  handler function that you previously registered with the driver through calls
+  to the MSS_UART_set_rx_handler(), MSS_UART_set_tx_handler(),
+  MSS_UART_set_rxstatus_handler(), and MSS_UART_set_modemstatus_handler()
+  functions. You are responsible for creating these lower level interrupt
+  handlers as part of your application program and registering them with the
+  driver.
+  Note: The SmartFusion2 CMSIS-PAL defines the UART0_IRQHandler() and
+        UART1_IRQHandler() functions (with weak linkage) and assigns them as the
+        interrupt service routines (ISR) for the MSS MMUART interrupt inputs to
+        the Cortex-M3 NVIC. The MSS MMUART driver provides the implementation
+        functions for both of these ISRs from which it calls its own internal
+        top level, interrupt handler function.
+  The MSS_UART_enable_irq() and MSS_UART_disable_irq() functions are used to
+  enable or disable the received line status, received data available/character
+  timeout, transmit holding register empty and modem status interrupts at the
+  MSS MMUART level. The MSS_UART_enable_irq() function also enables the MSS
+  MMUART instance interrupt at the Cortex-M3 level.
+  
+  Transmitting Data
+  Interrupt-driven transmit is initiated by a call to MSS_UART_irq_tx(),
+  specifying the block of data to transmit. Your application is then free to
+  perform other tasks and inquire later whether transmit has completed by
+  calling the MSS_UART_tx_complete() function. The MSS_UART_irq_tx() function
+  enables the UART�s transmit holding register empty (THRE) interrupt and then,
+  when the interrupt goes active, the driver�s default THRE interrupt handler
+  transfers the data block to the UART until the entire block is transmitted.
+  Note: You can use the MSS_UART_set_tx_handler() function to assign an
+        alternative handler to the THRE interrupt. In this case, you must not
+        use the MSS_UART_irq_tx() function to initiate the transmit, as this
+        will re-assign the driver�s default THRE interrupt handler to the THRE
+        interrupt. Instead, your alternative THRE interrupt handler must include
+        a call to the MSS_UART_fill_tx_fifo() function to transfer the data to
+        the UART.
+  
+  Receiving Data
+  Interrupt-driven receive is performed by first calling
+  MSS_UART_set_rx_handler() to register a receive handler function that will be
+  called by the driver whenever receive data is available. You must provide this
+  receive handler function which must include a call to the MSS_UART_get_rx()
+  function to actually read the received data.
+  
+  -----------
+  UART Status
+  -----------
+  The function MSS_UART_get_rx_status() is used to read the receiver error
+  status. This function returns the overrun, parity, framing, break, and FIFO
+  error status of the receiver.
+  The function MSS_UART_get_tx_status() is used to read the transmitter status.
+  This function returns the transmit empty (TEMT) and transmit holding register
+  empty (THRE) status of the transmitter.
+  The function MSS_UART_get_modem_status() is used to read the modem status
+  flags. This function returns the current value of the modem status register.
+  
+  --------
+  Loopback
+  --------
+  The MSS_UART_set_loopback() function can be used to locally loopback the Tx
+  and Rx lines of a UART. This is not to be confused with the loopback of UART0
+  to UART1, which can be achieved through the microcontroller subsystem�s system
+  registers.
+  
+ *//*=========================================================================*/
+#ifndef __MSS_UART_H_
+#define __MSS_UART_H_ 1
+
+#include "../../CMSIS/m2sxxx.h"
+#include <stddef.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/***************************************************************************//**
+  Baud rates
+  The following definitions are used to specify standard baud rates as a
+  parameter to the MSS_UART_init() function.
+ */
+#define MSS_UART_110_BAUD       110
+#define MSS_UART_300_BAUD       300
+#define MSS_UART_1200_BAUD      1200
+#define MSS_UART_2400_BAUD      2400
+#define MSS_UART_4800_BAUD      4800
+#define MSS_UART_9600_BAUD      9600
+#define MSS_UART_19200_BAUD     19200
+#define MSS_UART_38400_BAUD     38400
+#define MSS_UART_57600_BAUD     57600
+#define MSS_UART_115200_BAUD    115200
+#define MSS_UART_230400_BAUD    230400
+#define MSS_UART_460800_BAUD    460800
+#define MSS_UART_921600_BAUD    921600
+
+/***************************************************************************//**
+  Data Bits Length
+  The following defines are used to build the value of the MSS_UART_init()
+  function line_config parameter.
+ */
+#define MSS_UART_DATA_5_BITS     ( (uint8_t) 0x00 )
+#define MSS_UART_DATA_6_BITS     ( (uint8_t) 0x01 )
+#define MSS_UART_DATA_7_BITS     ( (uint8_t) 0x02 )
+#define MSS_UART_DATA_8_BITS     ( (uint8_t) 0x03 )
+
+/***************************************************************************//**
+  Parity
+  The following defines are used to build the value of the MSS_UART_init()
+  function line_config parameter.
+ */
+#define MSS_UART_NO_PARITY           ( (uint8_t) 0x00 )
+#define MSS_UART_ODD_PARITY          ( (uint8_t) 0x08 )
+#define MSS_UART_EVEN_PARITY         ( (uint8_t) 0x18 )
+#define MSS_UART_STICK_PARITY_0      ( (uint8_t) 0x38 )
+#define MSS_UART_STICK_PARITY_1      ( (uint8_t) 0x28 )
+
+/***************************************************************************//**
+  Number of Stop Bits
+  The following defines are used to build the value of the MSS_UART_init()
+  function line_config parameter.
+ */
+#define MSS_UART_ONE_STOP_BIT        ( (uint8_t) 0x00 )
+#define MSS_UART_ONEHALF_STOP_BIT    ( (uint8_t) 0x04 )
+#define MSS_UART_TWO_STOP_BITS       ( (uint8_t) 0x04 )
+
+/***************************************************************************//**
+  Receiver Error Status
+  The following defines are used to determine the UART receiver error type.
+  These bit mask constants are used with the return value of the
+  MSS_UART_get_rx_status() function to find out if any errors occurred while
+  receiving data.
+ */
+#define MSS_UART_INVALID_PARAM    ( (uint8_t)0xFF )
+#define MSS_UART_NO_ERROR         ( (uint8_t)0x00 )
+#define MSS_UART_OVERUN_ERROR     ( (uint8_t)0x02 )
+#define MSS_UART_PARITY_ERROR     ( (uint8_t)0x04 )
+#define MSS_UART_FRAMING_ERROR    ( (uint8_t)0x08 )
+#define MSS_UART_BREAK_ERROR      ( (uint8_t)0x10 )
+#define MSS_UART_FIFO_ERROR       ( (uint8_t)0x80 )
+
+/***************************************************************************//**
+  Transmitter Status
+  The following definitions are used to determine the UART transmitter status.
+  These bit mask constants are used with the return value of the
+  MSS_UART_get_tx_status() function to find out the status of the transmitter.
+ */
+#define MSS_UART_TX_BUSY          ( (uint8_t) 0x00 )
+#define MSS_UART_THRE             ( (uint8_t) 0x20 )
+#define MSS_UART_TEMT             ( (uint8_t) 0x40 )
+
+/***************************************************************************//**
+  Modem Status
+  The following defines are used to determine the modem status. These bit
+  mask constants are used with the return value of the
+  MSS_UART_get_modem_status() function to find out the modem status of
+  the UART.
+ */
+#define MSS_UART_DCTS             ( (uint8_t) 0x01 )
+#define MSS_UART_DDSR             ( (uint8_t) 0x02 )
+#define MSS_UART_TERI             ( (uint8_t) 0x04 )
+#define MSS_UART_DDCD             ( (uint8_t) 0x08 )
+#define MSS_UART_CTS              ( (uint8_t) 0x10 )
+#define MSS_UART_DSR              ( (uint8_t) 0x20 )
+#define MSS_UART_RI               ( (uint8_t) 0x40 )
+#define MSS_UART_DCD              ( (uint8_t) 0x80 )
+
+/***************************************************************************//**
+  This typedef specifies the irq_mask parameter for the MSS_UART_enable_irq()
+  and MSS_UART_disable_irq() functions. The driver defines a set of bit masks
+  that are used to build the value of the irq_mask parameter. A bitwise OR of
+  these bit masks is used to enable or disable multiple MSS MMUART interrupts.
+ */
+typedef uint16_t mss_uart_irq_t;
+
+/***************************************************************************//**
+  The following defines specify the interrupt masks to enable and disable MSS
+  MMUART interrupts. They are used to build the value of the irq_mask parameter
+  for the MSS_UART_enable_irq() and MSS_UART_disable_irq() functions. A bitwise
+  OR of these constants is used to enable or disable multiple interrupts.
+ */
+#define MSS_UART_RBF_IRQ        0x001
+#define MSS_UART_TBE_IRQ        0x002
+#define MSS_UART_LS_IRQ         0x004
+#define MSS_UART_MS_IRQ         0x008
+#define MSS_UART_RTO_IRQ        0x010
+#define MSS_UART_NACK_IRQ       0x020
+#define MSS_UART_PIDPE_IRQ      0x040
+#define MSS_UART_LINB_IRQ       0x080
+#define MSS_UART_LINS_IRQ       0x100
+#define MSS_UART_INVALID_IRQ    UINT16_MAX
+
+/***************************************************************************//**
+  This enumeration specifies the receiver FIFO trigger level. This is the number
+  of bytes that must be received before the UART generates a receive data
+  available interrupt. It provides the allowed values for the
+  MSS_UART_set_rx_handler() function trigger_level parameter.
+ */
+typedef enum {
+    MSS_UART_FIFO_SINGLE_BYTE    = 0x00,
+    MSS_UART_FIFO_FOUR_BYTES     = 0x40,
+    MSS_UART_FIFO_EIGHT_BYTES    = 0x80,
+    MSS_UART_FIFO_FOURTEEN_BYTES = 0xC0,
+    MSS_UART_FIFO_INVALID_TRIG_LEVEL
+} mss_uart_rx_trig_level_t;
+
+/***************************************************************************//**
+  This enumeration specifies the loopback configuration of the UART. It provides
+  the allowed values for the MSS_UART_set_loopback() function�s loopback
+  parameter. Use MSS_UART_LOCAL_LOOPBACK_ON to set up the UART to locally
+  loopback its Tx and Rx lines. Use MSS_UART_REMOTE_LOOPBACK_ON to set up the
+  UART in remote loopback mode.
+ */
+typedef enum {
+    MSS_UART_LOCAL_LOOPBACK_OFF,
+    MSS_UART_LOCAL_LOOPBACK_ON,
+    MSS_UART_REMOTE_LOOPBACK_OFF,
+    MSS_UART_REMOTE_LOOPBACK_ON,
+    MSS_UART_AUTO_ECHO_OFF,
+    MSS_UART_AUTO_ECHO_ON,
+    MSS_UART_INVALID_LOOPBACK
+} mss_uart_loopback_t;
+
+/***************************************************************************//**
+  IrDA input / output polarity.
+  This enumeration specifies the RZI modem polarity for input and output signals. 
+  This is passed as parameters in MSS_UART_irda_init() function.
+ */
+typedef enum {
+    MSS_UART_ACTIVE_LOW = 0u,
+    MSS_UART_ACTIVE_HIGH = 1u,
+    MSS_UART_INVALID_POLARITY
+} mss_uart_rzi_polarity_t;
+
+/***************************************************************************//**
+  IrDA input / output pulse width.
+  This enumeration specifies the RZI modem pulse width for input and output signals. 
+  This is passed as parameters in MSS_UART_irda_init() function.
+ */
+typedef enum {
+    MSS_UART_3_BY_16 = 0u,
+    MSS_UART_1_BY_4 = 1u,
+    MSS_UART_INVALID_PW
+} mss_uart_rzi_pulsewidth_t;
+
+/***************************************************************************//**
+  Tx / Rx endianess.
+  This enumeration specifies the MSB first or LSB first for MSS UART transmitter 
+  and receiver. The parameter of this type shall be passed in 
+  MSS_UART_set_rx_endian()and MSS_UART_set_tx_endian() functions.
+ */
+typedef enum {
+    MSS_UART_LITTLEEND,
+    MSS_UART_BIGEND,
+    MSS_UART_INVALID_ENDIAN
+} mss_uart_endian_t;
+
+/***************************************************************************//**
+  Glitch filter length.
+  This enumeration specifies the glitch filter length. The function 
+  MSS_UART_set_filter_length() accepts the parameter of this type.
+ */
+typedef enum {
+    MSS_UART_LEN0 = 0,
+    MSS_UART_LEN1 = 1,
+    MSS_UART_LEN2 = 2,
+    MSS_UART_LEN3 = 3,
+    MSS_UART_LEN4 = 4,
+    MSS_UART_LEN5 = 5,
+    MSS_UART_LEN6 = 6,
+    MSS_UART_LEN7 = 7,
+    MSS_UART_INVALID_FILTER_LENGTH = 8
+} mss_uart_filter_length_t;
+
+/***************************************************************************//**
+  TXRDY and RXRDY mode.
+  This enumeration specifies the TXRDY and RXRDY signal modes. The function 
+  MSS_UART_set_ready_mode() accepts the parameter of this type.
+ */
+typedef enum {
+    MSS_UART_READY_MODE0,
+    MSS_UART_READY_MODE1,
+    MSS_UART_INVALID_READY_MODE
+} mss_uart_ready_mode_t;
+
+/***************************************************************************//**
+  USART mode of operation.
+  This enumeration specifies the mode of operation of MSS UART when operating 
+  as USART. The function MSS_UART_set_usart_mode() accepts the parameter of this type.
+ */
+typedef enum {
+    MSS_UART_ASYNC_MODE               = 0,
+    MSS_UART_SYNC_SLAVE_POS_EDGE_CLK  = 1,
+    MSS_UART_SYNC_SLAVE_NEG_EDGE_CLK  = 2,
+    MSS_UART_SYNC_MASTER_POS_EDGE_CLK = 3,
+    MSS_UART_SYNC_MASTER_NEG_EDGE_CLK = 4,
+    MSS_UART_INVALID_SYNC_MODE        = 5
+} mss_uart_usart_mode_t;
+
+
+/***************************************************************************//**
+  MSS UART instance type.
+  This is type definition for MSS UART instance. You need to create and
+  maintain a record of this type. This holds all data regarding the MSS UART
+  instance
+ */
+typedef struct  mss_uart_instance mss_uart_instance_t;
+
+/***************************************************************************//**
+  Interrupt handler prototype.
+  This typedef specifies the function prototype for MSS UART interrupt handlers.
+  All interrupt handlers registered with the MSS UART driver must be of this type.
+  The interrupt handlers are registered with the driver through the
+  MSS_UART_set_rx_handler(), MSS_UART_set_tx_handler(),
+  MSS_UART_set_rxstatus_handler(), and MSS_UART_set_modemstatus_handler()
+  functions.
+  The this_uart parameter is a pointer to either g_mss_uart0 or g_mss_uart1 to
+  identify the MSS UART to associate with the handler function.
+ */
+typedef void (*mss_uart_irq_handler_t)( mss_uart_instance_t * this_uart );
+
+/***************************************************************************//**
+  mss_uart_instance.
+  There is one instance of this structure for each instance of the
+  microcontroller subsystem�s UARTs. Instances of this structure are used to
+  identify a specific UART. A pointer to an initialized instance of the
+  mss_uart_instance_t structure is passed as the first parameter to
+  MSS UART driver functions to identify which UART should perform the
+  requested operation.
+ */
+struct mss_uart_instance{
+    /* CMSIS related defines identifying the UART hardware. */
+    UART_TypeDef *          hw_reg;     /*!< Pointer to UART registers. */
+    IRQn_Type               irqn;       /*!< UART's Cortex-M3 NVIC interrupt number. */
+    uint32_t                baudrate;   /*!< Operating baud rate. */
+    uint8_t                 lineconfig; /*!< Line configuration parameters. */
+    uint8_t                 status;     /*!< Sticky line status. */
+
+    /* transmit related info (used with interrupt driven transmit): */
+    const uint8_t * tx_buffer;          /*!< Pointer to transmit buffer. */
+    uint32_t        tx_buff_size;       /*!< Transmit buffer size. */
+    uint32_t        tx_idx;             /*!< Index within transmit buffer of next byte to transmit.*/
+
+    /* line status interrupt handler:*/
+    mss_uart_irq_handler_t linests_handler;   /*!< Pointer to user registered line status handler. */
+    /* receive interrupt handler:*/
+    mss_uart_irq_handler_t rx_handler;        /*!< Pointer to user registered receiver handler. */
+    /* transmit interrupt handler:*/
+    mss_uart_irq_handler_t tx_handler;        /*!< Pointer to user registered transmit handler. */
+    /* modem status interrupt handler:*/
+    mss_uart_irq_handler_t modemsts_handler;  /*!< Pointer to user registered modem status handler. */
+    /* receiver timeout interrupt handler */
+    mss_uart_irq_handler_t rto_handler;       /*!< Pointer to user registered receiver timeout handler. */
+    /* NACK interrupt handler */
+    mss_uart_irq_handler_t nack_handler;      /*!< Pointer to user registered NACK handler. */
+    /* PID parity prror interrup handler */
+    mss_uart_irq_handler_t pid_pei_handler;   /*!< Pointer to user registered PID parity error handler. */
+    /* LIN break interrupt handler */
+    mss_uart_irq_handler_t break_handler;     /*!< Pointer to user registered LIN break handler. */
+    /* LIN sync detection interrupt handler */
+    mss_uart_irq_handler_t sync_handler;      /*!< Pointer to user registered LIN sync dectection handler. */
+};
+
+/***************************************************************************//**
+  This instance of mss_uart_instance_t holds all data related to the operations
+  performed by UART0. The function MSS_UART_init() initializes this structure.
+  A pointer to g_mss_uart0 is passed as the first parameter to MSS UART driver
+  functions to indicate that UART0 should perform the requested operation.
+ */
+extern mss_uart_instance_t g_mss_uart0;
+
+/***************************************************************************//**
+  This instance of mss_uart_instance_t holds all data related to the operations
+  performed by UART1. The function MSS_UART_init() initializes this structure.
+  A pointer to g_mss_uart1 is passed as the first parameter to MSS UART driver
+  functions to indicate that UART1 should perform the requested operation.
+ */
+extern mss_uart_instance_t g_mss_uart1;
+
+/***************************************************************************//**
+  The MSS_UART_init() function initializes and configures one of the SmartFusion2
+  MSS UARTs with the configuration passed as a parameter. The configuration
+  parameters are the baud_rate which is used to generate the baud value and the
+  line_config which is used to specify the line configuration (bit length,
+  stop bits and parity).
+
+  @param this_uart
+    The this_uart parameter is a pointer to an mss_uart_instance_t structure
+    identifying the MSS UART hardware block to be initialized. There are two
+    such data structures, g_mss_uart0 and g_mss_uart1, associated with MSS
+    UART0 and MSS UART1 respectively. This parameter must point to either
+    the g_mss_uart0 or g_mss_uart1 global data structure defined within
+    the UART driver..
+
+  @param baud_rate
+    The baud_rate parameter specifies the baud rate. It can be specified for
+    common baud rates� using the following defines:
+    �   MSS_UART_110_BAUD
+    �   MSS_UART_300_BAUD
+    �   MSS_UART_1200_BAUD
+    �   MSS_UART_2400_BAUD
+    �   MSS_UART_4800_BAUD
+    �   MSS_UART_9600_BAUD
+    �   MSS_UART_19200_BAUD
+    �   MSS_UART_38400_BAUD
+    �   MSS_UART_57600_BAUD
+    �   MSS_UART_115200_BAUD
+    �   MSS_UART_230400_BAUD
+    �   MSS_UART_460800_BAUD
+    �   MSS_UART_921600_BAUD
+    Alternatively, any nonstandard baud rate can be specified by simply passing
+    the actual required baud rate as the value for this parameter.
+
+  @param line_config
+    The line_config parameter is the line configuration specifying the bit length,
+    number of stop bits and parity settings. This is a bitwise OR of one value
+    from each of the following groups of allowed values:
+    �   One of the following to specify the transmit/receive data bit length:
+        MSS_UART_DATA_5_BITS
+        MSS_UART_DATA_6_BITS,
+        MSS_UART_DATA_7_BITS
+        MSS_UART_DATA_8_BITS
+    �   One of the following to specify the parity setting:
+        MSS_UART_NO_PARITY
+        MSS_UART_EVEN_PARITY
+        MSS_UART_ODD_PARITY
+        MSS_UART_STICK_PARITY_0
+        MSS_UART_STICK_PARITY_1
+    �   One of the following to specify the number of stop bits:
+        MSS_UART_ONE_STOP_BIT
+        MSS_UART_ONEHALF_STOP_BIT
+        MSS_UART_TWO_STOP_BITS
+
+  @return
+    This function does not return a value.
+
+  Example:
+  @code
+  #include "mss_uart.h"
+
+  int main(void)
+  {
+     MSS_UART_init(&g_mss_uart0,
+                   MSS_UART_57600_BAUD,
+                   MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT);
+                   
+     return(0);
+  }
+  @endcode
+ */
+void
+MSS_UART_init
+(
+    mss_uart_instance_t* this_uart,
+    uint32_t baud_rate,
+    uint8_t line_config
+);
+
+/***************************************************************************//**
+ The MSS_UART_lin_init() function is used to initialize the MSS UART for 
+ LIN mode of operation. The configuration parameters are the baud_rate which is 
+ used to generate the baud value and the line_config which is used to specify 
+ the line configuration (bit length, stop bits and parity).
+
+  @param this_uart
+    The this_uart parameter is a pointer to an mss_uart_instance_t
+    structure identifying the MSS UART hardware block that will perform
+    the requested function. There are two such data structures,
+    g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1.
+    This parameter must point to either the g_mss_uart0 or g_mss_uart1
+    global data structure defined within the UART driver.
+
+  @param baud_rate
+    The baud_rate parameter specifies the baud rate. It can be specified for
+    common baud rates� using the following defines:
+    �   MSS_UART_110_BAUD
+    �   MSS_UART_300_BAUD
+    �   MSS_UART_1200_BAUD
+    �   MSS_UART_2400_BAUD
+    �   MSS_UART_4800_BAUD
+    �   MSS_UART_9600_BAUD
+    �   MSS_UART_19200_BAUD
+    �   MSS_UART_38400_BAUD
+    �   MSS_UART_57600_BAUD
+    �   MSS_UART_115200_BAUD
+    �   MSS_UART_230400_BAUD
+    �   MSS_UART_460800_BAUD
+    �   MSS_UART_921600_BAUD
+    Alternatively, any nonstandard baud rate can be specified by simply passing
+    the actual required baud rate as the value for this parameter.
+
+  @param line_config
+    The line_config parameter is the line configuration specifying the bit length,
+    number of stop bits and parity settings. This is a bitwise OR of one value
+    from each of the following groups of allowed values:
+    �   One of the following to specify the transmit/receive data bit length:
+        MSS_UART_DATA_5_BITS
+        MSS_UART_DATA_6_BITS,
+        MSS_UART_DATA_7_BITS
+        MSS_UART_DATA_8_BITS
+    �   One of the following to specify the parity setting:
+        MSS_UART_NO_PARITY
+        MSS_UART_EVEN_PARITY
+        MSS_UART_ODD_PARITY
+        MSS_UART_STICK_PARITY_0
+        MSS_UART_STICK_PARITY_1
+    �   One of the following to specify the number of stop bits:
+        MSS_UART_ONE_STOP_BIT
+        MSS_UART_ONEHALF_STOP_BIT
+        MSS_UART_TWO_STOP_BITS
+
+  @return
+    This function does not return a value.
+
+  Example:
+  @code
+  #include "mss_uart.h"
+
+  int main(void)
+  {
+     MSS_UART_lin_init(&g_mss_uart0,
+                       MSS_UART_57600_BAUD,
+                       MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT);
+                       
+     return(0);
+  }
+  @endcode
+ */
+void 
+MSS_UART_lin_init
+(
+    mss_uart_instance_t* this_uart, 
+    uint32_t baud_rate,
+    uint8_t line_config
+);
+
+/***************************************************************************//**
+  The MSS_UART_irda_init() function is used to initialize the MSS UART instance 
+  referenced by the parameter this_uart  for IrDA mode of operation. This 
+  function must be called before calling any other IrDA functionality specific 
+  functions.
+
+  @param this_uart
+    The this_uart parameter is a pointer to an mss_uart_instance_t
+    structure identifying the MSS UART hardware block that will perform
+    the requested function. There are two such data structures,
+    g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1.
+    This parameter must point to either the g_mss_uart0 or g_mss_uart1
+    global data structure defined within the UART driver.
+
+  @param baud_rate
+    The baud_rate parameter specifies the baud rate. It can be specified for
+    common baud rates� using the following defines:
+    �   MSS_UART_110_BAUD
+    �   MSS_UART_300_BAUD
+    �   MSS_UART_1200_BAUD
+    �   MSS_UART_2400_BAUD
+    �   MSS_UART_4800_BAUD
+    �   MSS_UART_9600_BAUD
+    �   MSS_UART_19200_BAUD
+    �   MSS_UART_38400_BAUD
+    �   MSS_UART_57600_BAUD
+    �   MSS_UART_115200_BAUD
+    �   MSS_UART_230400_BAUD
+    �   MSS_UART_460800_BAUD
+    �   MSS_UART_921600_BAUD
+    Alternatively, any nonstandard baud rate can be specified by simply passing
+    the actual required baud rate as the value for this parameter.
+
+  @param line_config
+    The line_config parameter is the line configuration specifying the bit length,
+    number of stop bits and parity settings. This is a bitwise OR of one value
+    from each of the following groups of allowed values:
+    �   One of the following to specify the transmit/receive data bit length:
+        MSS_UART_DATA_5_BITS
+        MSS_UART_DATA_6_BITS,
+        MSS_UART_DATA_7_BITS
+        MSS_UART_DATA_8_BITS
+    �   One of the following to specify the parity setting:
+        MSS_UART_NO_PARITY
+        MSS_UART_EVEN_PARITY
+        MSS_UART_ODD_PARITY
+        MSS_UART_STICK_PARITY_0
+        MSS_UART_STICK_PARITY_1
+    �   One of the following to specify the number of stop bits:
+        MSS_UART_ONE_STOP_BIT
+        MSS_UART_ONEHALF_STOP_BIT
+        MSS_UART_TWO_STOP_BITS
+
+  @return
+    This function does not return a value.
+
+  Example:
+  @code
+    MSS_UART_irda_init(&g_mss_uart0,
+                       MSS_UART_57600_BAUD,
+                       MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT,
+                       MSS_UART_ACTIVE_LOW,
+                       MSS_UART_ACTIVE_LOW,
+                       MSS_UART_3_BY_16);
+  @endcode
+ */
+void 
+MSS_UART_irda_init
+(
+    mss_uart_instance_t* this_uart, 
+    uint32_t baud_rate,
+    uint8_t line_config,
+    mss_uart_rzi_polarity_t rxpol,
+    mss_uart_rzi_polarity_t txpol,
+    mss_uart_rzi_pulsewidth_t pw
+);
+
+/***************************************************************************//**
+  The MSS_UART_smartcard_init() function is used to initialize the MSS UART 
+  for ISO 7816 (smartcard) mode of operation. The configuration parameters are 
+  the baud_rate which is used to generate the baud value and the line_config 
+  which is used to specify the line configuration (bit length, stop bits and parity). 
+  This function disables all other modes of the MSS UART instance pointed by 
+  the parameter this_uart.
+  
+  @param this_uart
+    The this_uart parameter is a pointer to an mss_uart_instance_t
+    structure identifying the MSS UART hardware block that will perform
+    the requested function. There are two such data structures,
+    g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1.
+    This parameter must point to either the g_mss_uart0 or g_mss_uart1
+    global data structure defined within the UART driver.
+
+  @param baud_rate
+    The baud_rate parameter specifies the baud rate. It can be specified for
+    common baud rates� using the following defines:
+    �   MSS_UART_110_BAUD
+    �   MSS_UART_300_BAUD
+    �   MSS_UART_1200_BAUD
+    �   MSS_UART_2400_BAUD
+    �   MSS_UART_4800_BAUD
+    �   MSS_UART_9600_BAUD
+    �   MSS_UART_19200_BAUD
+    �   MSS_UART_38400_BAUD
+    �   MSS_UART_57600_BAUD
+    �   MSS_UART_115200_BAUD
+    �   MSS_UART_230400_BAUD
+    �   MSS_UART_460800_BAUD
+    �   MSS_UART_921600_BAUD
+    Alternatively, any nonstandard baud rate can be specified by simply passing
+    the actual required baud rate as the value for this parameter.
+
+  @param line_config
+    The line_config parameter is the line configuration specifying the bit length,
+    number of stop bits and parity settings. This is a bitwise OR of one value
+    from each of the following groups of allowed values:
+    �   One of the following to specify the transmit/receive data bit length:
+        MSS_UART_DATA_5_BITS
+        MSS_UART_DATA_6_BITS,
+        MSS_UART_DATA_7_BITS
+        MSS_UART_DATA_8_BITS
+    �   One of the following to specify the parity setting:
+        MSS_UART_NO_PARITY
+        MSS_UART_EVEN_PARITY
+        MSS_UART_ODD_PARITY
+        MSS_UART_STICK_PARITY_0
+        MSS_UART_STICK_PARITY_1
+    �   One of the following to specify the number of stop bits:
+        MSS_UART_ONE_STOP_BIT
+        MSS_UART_ONEHALF_STOP_BIT
+        MSS_UART_TWO_STOP_BITS
+
+  @return
+    This function does not return a value.
+
+  Example:
+  @code
+    #include "mss_uart.h"
+
+      int main(void)
+      {
+         MSS_UART_smartcard_init(&g_mss_uart0,
+                                 MSS_UART_57600_BAUD,
+                                 MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT);
+                                 
+         return(0);
+      }
+  @endcode
+ */
+void 
+MSS_UART_smartcard_init
+(
+    mss_uart_instance_t* this_uart, 
+    uint32_t baud_rate,
+    uint8_t line_config
+);
+
+/***************************************************************************//**
+  The function MSS_UART_polled_tx() is used to transmit data. It transfers the
+  contents of the transmitter data buffer, passed as a function parameter, into
+  the UART�s hardware transmitter FIFO. It returns when the full content of the
+  transmit data buffer has been transferred to the UART�s transmit FIFO. It is
+  safe to release or reuse the memory used as the transmitter data buffer once
+  this function returns.
+
+  Note:     This function reads the UART�s line status register (LSR) to poll
+  for the active state of the transmitter holding register empty (THRE) bit
+  before transferring data from the data buffer to the transmitter FIFO. It
+  transfers data to the transmitter FIFO in blocks of 16 bytes or less and
+  allows the FIFO to empty before transferring the next block of data.
+
+  Note:     The actual transmission over the serial connection will still be
+  in progress when this function returns. Use the MSS_UART_get_tx_status()
+  function if you need to know when the transmitter is empty.
+
+  @param this_uart
+    The this_uart parameter is a pointer to an mss_uart_instance_t
+    structure identifying the MSS UART hardware block that will perform
+    the requested function. There are two such data structures,
+    g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1.
+    This parameter must point to either the g_mss_uart0 or g_mss_uart1
+    global data structure defined within the UART driver.
+
+  @param pbuff
+    The pbuff parameter is a pointer to a buffer containing the data to
+    be transmitted.
+
+  @param tx_size
+    The tx_size parameter specifies the size, in bytes, of the data to
+    be transmitted.
+
+  @return
+    This function does not return a value.
+
+  Example:
+  @code
+  #include "mss_uart.h"
+
+  int main(void)
+  {
+     uint8_t message[12] = "Hello World";
+
+     MSS_UART_init(&g_mss_uart0,
+                   MSS_UART_57600_BAUD,
+                   MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT);
+                   
+     MSS_UART_polled_tx(&g_mss_uart0, message, sizeof(message));
+     
+     return(0);
+  }
+  @endcode
+ */
+void
+MSS_UART_polled_tx
+(
+    mss_uart_instance_t * this_uart,
+    const uint8_t * pbuff,
+    uint32_t tx_size
+);
+
+/***************************************************************************//**
+  The function MSS_UART_polled_tx_string() is used to transmit a NULL ('\0')
+  terminated string. It transfers the text string, from the buffer starting at
+  the address pointed to by p_sz_string into the UART�s hardware transmitter
+  FIFO. It returns when the complete string has been transferred to the UART's
+  transmit FIFO. It is safe to release or reuse the memory used as the string
+  buffer once this function returns.
+
+  Note:     This function reads the UART�s line status register (LSR) to poll
+  for the active state of the transmitter holding register empty (THRE) bit
+  before transferring data from the data buffer to the transmitter FIFO. It
+  transfers data to the transmitter FIFO in blocks of 16 bytes or less and
+  allows the FIFO to empty before transferring the next block of data.
+
+  Note:     The actual transmission over the serial connection will still be
+  in progress when this function returns. Use the MSS_UART_get_tx_status()
+  function if you need to know when the transmitter is empty.
+
+  @param this_uart
+    The this_uart parameter is a pointer to an mss_uart_instance_t
+    structure identifying the MSS UART hardware block that will perform
+    the requested function. There are two such data structures,
+    g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1.
+    This parameter must point to either the g_mss_uart0 or g_mss_uart1
+    global data structure defined within the UART driver.
+
+  @param p_sz_string
+    The p_sz_string parameter is a pointer to a buffer containing the NULL
+    ('\0') terminated string to be transmitted.
+
+  @return
+    This function does not return a value.
+
+  Example:
+  @code
+  #include "mss_uart.h"
+
+  int main(void)
+  {
+     uint8_t message[12] = "Hello World";
+
+     MSS_UART_init(&g_mss_uart0,
+                   MSS_UART_57600_BAUD,
+                   MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT);
+                   
+     MSS_UART_polled_tx_string(&g_mss_uart0, message);
+     
+     return(0);
+  }
+  @endcode
+
+ */
+void
+MSS_UART_polled_tx_string
+(
+    mss_uart_instance_t * this_uart,
+    const uint8_t * p_sz_string
+);
+
+
+/***************************************************************************//**
+  The function MSS_UART_irq_tx() is used to initiate an interrupt-driven
+  transmit. It returns immediately after making a note of the transmit buffer
+  location and enabling transmit interrupts both at the UART and Cortex-M3 NVIC
+  level. This function takes a pointer via the pbuff parameter to a memory
+  buffer containing the data to transmit. The memory buffer specified through
+  this pointer must remain allocated and contain the data to transmit until
+  the transmit completion has been detected through calls to function
+  MSS_UART_tx_complete(). The actual transmission over the serial connection
+  is still in progress until calls to the MSS_UART_tx_complete() function
+  indicate transmit completion.
+
+  Note:     The MSS_UART_irq_tx() function enables both the transmit holding
+  register empty (THRE) interrupt in the UART and the MSS UART instance
+  interrupt in the Cortex-M3 NVIC as part of its implementation.
+
+  Note:     The MSS_UART_irq_tx() function assigns an internal default transmit
+  interrupt handler function to the UART�s THRE interrupt. This interrupt
+  handler overrides any custom interrupt handler that you may have previously
+  registered using the MSS_UART_set_tx_handler() function.
+
+  Note:     The MSS_UART_irq_tx() function�s default transmit interrupt
+  handler disables the UART�s THRE interrupt when all of the data has
+  been transferred to the UART's transmit FIFO.
+
+
+  @param this_uart
+    The this_uart parameter is a pointer to an mss_uart_instance_t
+    structure identifying the MSS UART hardware block that will perform
+    the requested function. There are two such data structures,
+    g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1.
+    This parameter must point to either the g_mss_uart0 or g_mss_uart1
+    global data structure defined within the UART driver.
+
+  @param pbuff
+    The pbuff parameter is a pointer to a buffer containing the data
+    to be transmitted.
+
+  @param tx_size
+    The tx_size parameter specifies the size, in bytes, of the data
+    to be transmitted.
+
+  @return
+    This function does not return a value.
+
+  Example:
+  @code
+  #include "mss_uart.h"
+
+  int main(void)
+  {
+     uint8_t tx_buff[10] = "abcdefghi";
+     
+     MSS_UART_init(&g_mss_uart0,
+                   MSS_UART_57600_BAUD,
+                   MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT);
+                   
+     MSS_UART_irq_tx(&g_mss_uart0, tx_buff, sizeof(tx_buff));
+     
+     while(0 == MSS_UART_tx_complete(&g_mss_uart0))
+     {
+         ;
+     }
+     return(0);
+  }
+  @endcode
+ */
+void
+MSS_UART_irq_tx
+(
+    mss_uart_instance_t * this_uart,
+    const uint8_t * pbuff,
+    uint32_t tx_size
+);
+
+/***************************************************************************//**
+  The MSS_UART_tx_complete() function is used to find out if the interrupt-driven
+  transmit previously initiated through a call to MSS_UART_irq_tx() is complete.
+  This is typically used to find out when it is safe to reuse or release the
+  memory buffer holding transmit data.
+
+  Note:     The transfer of all of the data from the memory buffer to the UART�s
+  transmit FIFO and the actual transmission over the serial connection are both
+  complete when a call to the MSS_UART_tx_complete() function indicates transmit
+  completion.
+
+  @param this_uart
+    The this_uart parameter is a pointer to an mss_uart_instance_t
+    structure identifying the MSS UART hardware block that will perform
+    the requested function. There are two such data structures,
+    g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1.
+    This parameter must point to either the g_mss_uart0 or g_mss_uart1
+    global data structure defined within the UART driver.
+
+  @return
+    This function return a non-zero value if transmit has completed, otherwise
+    it returns zero.
+
+  Example:
+    See the MSS_UART_irq_tx() function for an example that uses the
+    MSS_UART_tx_complete() function.
+ */
+int8_t
+MSS_UART_tx_complete
+(
+   mss_uart_instance_t * this_uart
+);
+
+/***************************************************************************//**
+  The MSS_UART_get_rx() function reads the content of the UART receiver�s FIFO
+  and stores it in the receive buffer that is passed via the rx_buff function
+  parameter. It copies either the full contents of the FIFO into the receive
+  buffer, or just enough data from the FIFO to fill the receive buffer,
+  dependent upon the size of the receive buffer passed by the buff_size
+  parameter. The MSS_UART_get_rx() function returns the number of bytes copied
+  into the receive buffer .This function is non-blocking and will return 0
+  immediately if no data has been received.
+
+  Note:     The MSS_UART_get_rx() function reads and accumulates the receiver
+  status of the MSS UART instance before reading each byte from the receiver's
+  data register/FIFO. This allows the driver to maintain a sticky record of any
+  receiver errors that occur as the UART receives each data byte; receiver
+  errors would otherwise be lost after each read from the receiver's data register.
+  A call to the MSS_UART_get_rx_status() function returns any receiver errors
+  accumulated during the execution of the MSS_UART_get_rx() function.
+
+  Note:     If you need to read the error status for each byte received, set
+  the buff_size to 1 and read the receive line error status for each byte
+  using the MSS_UART_get_rx_status() function.
+  The MSS_UART_get_rx() function can be used in polled mode, where it is called
+  at regular intervals to find out if any data has been received, or in interrupt
+  driven-mode, where it is called as part of a receive handler that is called
+  by the driver as a result of data being received.
+
+  Note:     In interrupt driven mode you should call the MSS_UART_get_rx()
+  function as part of the receive handler function that you register with
+  the MSS UART driver through a call to MSS_UART_set_rx_handler().
+
+  @param this_uart
+    The this_uart parameter is a pointer to an mss_uart_instance_t
+    structure identifying the MSS UART hardware block that will perform
+    the requested function. There are two such data structures,
+    g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1.
+    This parameter must point to either the g_mss_uart0 or g_mss_uart1
+    global data structure defined within the UART driver.
+
+  @param rx_buff
+    The rx_buff parameter is a pointer to a buffer where the received
+    data is copied.
+
+  @param buff_size
+    The buff_size parameter specifies the size of the receive buffer in bytes.
+
+  @return
+    This function returns the number of bytes that were copied into the
+    rx_buff buffer. It returns 0 if no data has been received.
+
+  Polled mode example:
+  @code
+   int main( void )
+   {
+      uint8_t rx_buff[RX_BUFF_SIZE];
+      uint32_t rx_idx  = 0;
+
+      MSS_UART_init(&g_mss_uart0,
+                    MSS_UART_57600_BAUD,
+                    MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT);
+                    
+      while(1)
+      {
+          rx_size = MSS_UART_get_rx(&g_mss_uart0, rx_buff, sizeof(rx_buff));
+          if(rx_size > 0)
+          {
+              process_rx_data(rx_buff, rx_size);
+          }
+          task_a();
+          task_b();
+      }
+      return 0;
+   }
+  @endcode
+
+  Interrupt driven example:
+  @code
+   int main( void )
+   {
+      MSS_UART_init(&g_mss_uart1,
+                    MSS_UART_57600_BAUD,
+                    MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT);
+                    
+      MSS_UART_set_rx_handler(&g_mss_uart1,
+                              uart1_rx_handler,
+                              MSS_UART_FIFO_SINGLE_BYTE);
+      
+      while(1)
+      {
+          task_a();
+          task_b();
+      }
+      return 0;
+   }
+
+   void uart1_rx_handler(mss_uart_instance_t * this_uart)
+   {
+      uint8_t rx_buff[RX_BUFF_SIZE];
+      uint32_t rx_idx  = 0;
+      rx_size = MSS_UART_get_rx(this_uart, rx_buff, sizeof(rx_buff));
+      process_rx_data(rx_buff, rx_size);
+   }
+  @endcode
+ */
+size_t
+MSS_UART_get_rx
+(
+   mss_uart_instance_t * this_uart,
+   uint8_t * rx_buff,
+   size_t buff_size
+);
+
+/***************************************************************************//**
+  The MSS_UART_set_rx_handler() function is used to register a receive handler
+  function that is called by the driver when a UART receive data available (RDA)
+  interrupt occurs. You must create and register the receive handler function
+  to suit your application and it must include a call to the MSS_UART_get_rx()
+  function to actually read the received data.
+
+  Note:     The MSS_UART_set_rx_handler() function enables both the RDA
+  interrupt in the UART and the MSS UART instance interrupt in the Cortex-M3
+  NVIC as part
+  of its implementation.
+
+  Note:     You can disable the RDA interrupt once the data is received by
+  calling the MSS_UART_disable_irq() function. This is your choice and is
+  dependent upon your application.
+
+
+  @param this_uart
+    The this_uart parameter is a pointer to an mss_uart_instance_t
+    structure identifying the MSS UART hardware block that will perform
+    the requested function. There are two such data structures,
+    g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1.
+    This parameter must point to either the g_mss_uart0 or g_mss_uart1
+    global data structure defined within the UART driver.
+
+  @param handler
+    The handler parameter is a pointer to a receive interrupt handler function
+    provided by your application that will be called as a result of a UART RDA
+    interrupt. This handler function must be of type mss_uart_irq_handler_t.
+
+  @param trigger_level
+    The trigger_level parameter is the receive FIFO trigger level. This
+    specifies the number of bytes that must be received before the UART
+    triggers an RDA interrupt.
+
+  @return
+    This function does not return a value.
+
+  Example:
+  @code
+  #include "mss_uart.h"
+
+  #define RX_BUFF_SIZE    64
+
+  uint8_t g_rx_buff[RX_BUFF_SIZE];
+
+  void uart0_rx_handler(mss_uart_instance_t * this_uart)
+  {
+      MSS_UART_get_rx(this_uart, &g_rx_buff[g_rx_idx], sizeof(g_rx_buff));
+  }
+
+  int main(void)
+  {
+      MSS_UART_init(&g_mss_uart0,
+                    MSS_UART_57600_BAUD,
+                    MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT);
+                    
+      MSS_UART_set_rx_handler(&g_mss_uart0,
+                              uart0_rx_handler,
+                              MSS_UART_FIFO_SINGLE_BYTE);
+                              
+      while(1)
+      {
+         ;
+      }
+      return(0);
+   }
+  @endcode
+ */
+void
+MSS_UART_set_rx_handler
+(
+    mss_uart_instance_t *       this_uart,
+    mss_uart_irq_handler_t          handler,
+    mss_uart_rx_trig_level_t    trigger_level
+);
+
+/***************************************************************************//**
+  The MSS_UART_set_loopback() function is used to locally loopback the Tx and
+  Rx lines of a UART. This is not to be confused with the loopback of UART0
+  to UART1, which can be achieved through the microcontroller subsystem�s
+  system registers.
+
+  @param this_uart
+    The this_uart parameter is a pointer to an mss_uart_instance_t
+    structure identifying the MSS UART hardware block that will perform
+    the requested function. There are two such data structures,
+    g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1.
+    This parameter must point to either the g_mss_uart0 or g_mss_uart1
+    global data structure defined within the UART driver.
+
+  @param loopback
+    The loopback parameter indicates whether or not the UART�s transmit
+    and receive lines should be looped back. Allowed values are as follows:
+      - MSS_UART_LOCAL_LOOPBACK_ON
+      - MSS_UART_LOCAL_LOOPBACK_OFF 
+      - MSS_UART_REMOTE_LOOPBACK_ON
+      - MSS_UART_REMOTE_LOOPBACK_OFF 
+      - MSS_UART_AUTO_ECHO_ON
+      - MSS_UART_AUTO_ECHO_OFF
+      
+  @return
+    This function does not return a value.
+
+  Example:
+  @code
+    MSS_UART_init(&g_mss_uart0,
+                  MSS_UART_57600_BAUD,
+                  MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT); 
+
+      MSS_UART_set_loopback(&g_mss_uart0, MSS_UART_LOCAL_LOOPBACK_OFF);
+  @endcode
+ */
+void
+MSS_UART_set_loopback
+(
+    mss_uart_instance_t *   this_uart,
+    mss_uart_loopback_t     loopback
+);
+
+/***************************************************************************//**
+  The MSS_UART_enable_irq() function enables the MSS UART interrupts specified
+  by the irq_mask parameter. The irq_mask parameter identifies the MSS UART
+  interrupts by bit position, as defined in the interrupt enable register (IER)
+  of MSS UART. The MSS UART interrupts and their identifying irq_mask bit
+  positions are as follows:
+  When an irq_mask bit position is set to 1, this function enables the
+  corresponding MSS UART interrupt in the IER register. When an irq_mask bit
+  position is set to 0, the corresponding interrupt�s state remains unchanged in
+  the IER register.
+  Note: The MSS_UART_enable_irq() function also enables the MSS UART instance
+        interrupt in the Cortex-M3 NVIC.
+        
+  @param this_uart
+    The this_uart parameter is a pointer to an mss_uart_instance_t structure
+    identifying the MSS UART hardware block that will perform the requested
+    function. There are two such data structures, g_mss_uart0 and g_mss_uart1,
+    associated with MSS UART0 and MSS UART1. This parameter must point to either
+    the g_mss_uart0 or g_mss_uart1 global data structure defined within the UART
+    driver.
+
+  @param irq_mask
+    The irq_mask parameter is used to select which of the MSS UART�s interrupts
+    you want to enable. The allowed value for the irq_mask parameter is one of
+    the following constants or a bitwise OR of more than one:
+      - MSS_UART_RBF_IRQ		(bit mask = 0x001)
+      - MSS_UART_TBE_IRQ		(bit mask = 0x002)
+      - MSS_UART_LS_IRQ		(bit mask = 0x004)
+      - MSS_UART_MS_IRQ		(bit mask = 0x008)
+      - MSS_UART_RTO_IRQ		(bit mask = 0x010)
+      - MSS_UART_NACK_IRQ	(bit mask = 0x020)
+      - MSS_UART_PIDPE_IRQ	(bit mask = 0x040)
+      - MSS_UART_LINB_IRQ		(bit mask = 0x080)
+      - MSS_UART_LINS_IRQ		(bit mask = 0x100)
+      
+  @return
+     This function does not return a value.
+
+  Example:
+  @code
+    MSS_UART_enable_irq(&g_mss_uart0,(MSS_UART_RBF_IRQ | MSS_UART_TBE_IRQ));
+  @endcode
+ */
+void
+MSS_UART_enable_irq
+(
+    mss_uart_instance_t * this_uart,
+    mss_uart_irq_t irq_mask
+);
+
+/***************************************************************************//**
+  The MSS_UART_disable_irq() function disables the MSS UART interrupts specified
+  by the irq_mask parameter. The irq_mask parameter identifies the MSS UART
+  interrupts by bit position, as defined in the interrupt enable register (IER)
+  of MSS UART. The MSS UART interrupts and their identifying bit positions are
+  as follows:
+  When an irq_mask bit position is set to 1, this function disables the
+  corresponding MSS UART interrupt in the IER register. When an irq_mask bit
+  position is set to 0, the corresponding interrupt�s state remains unchanged in
+  the IER register.
+  Note: If you disable all four of the UART�s interrupts, the
+        MSS_UART_disable_irq() function also disables the MSS UART instance
+        interrupt in the Cortex-M3 NVIC.
+        
+  @param this_uart
+    The this_uart parameter is a pointer to an mss_uart_instance_t
+    structure identifying the MSS UART hardware block that will perform
+    the requested function. There are two such data structures,
+    g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1.
+    This parameter must point to either the g_mss_uart0 or g_mss_uart1
+    global data structure defined within the UART driver.
+
+  @param irq_mask
+    The irq_mask parameter is used to select which of the MSS UART�s interrupts
+    you want to disable. The allowed value for the irq_mask parameter is one of
+    the following constants or a bitwise OR of more than one:
+      - MSS_UART_RBF_IRQ    (bit mask = 0x001)
+      - MSS_UART_TBE_IRQ    (bit mask = 0x002)
+      - MSS_UART_LS_IRQ     (bit mask = 0x004)
+      - MSS_UART_MS_IRQ     (bit mask = 0x008)
+      - MSS_UART_RTO_IRQ    (bit mask = 0x010)
+      - MSS_UART_NACK_IRQ   (bit mask = 0x020)
+      - MSS_UART_PIDPE_IRQ  (bit mask = 0x040)
+      - MSS_UART_LINB_IRQ   (bit mask = 0x080)
+      - MSS_UART_LINS_IRQ   (bit mask = 0x100)
+      
+  @return
+     This function does not return a value.
+
+  Example:
+  @code
+    MSS_UART_disable_irq(&g_mss_uart0, (MSS_UART_RBF_IRQ | MSS_UART_TBE_IRQ));
+  @endcode
+ */
+void
+MSS_UART_disable_irq
+(
+    mss_uart_instance_t * this_uart,
+    mss_uart_irq_t irq_mask
+);
+
+/***************************************************************************//**
+  The MSS_UART_set_pidpei_handler() function is used assign a custom interrupt 
+  handler for the PIDPEI (PID parity error interrupt) when the MSS UART is 
+  operating in LIN mode.
+
+  @param this_uart
+    The this_uart parameter is a pointer to an mss_uart_instance_t
+    structure identifying the MSS UART hardware block that will perform
+    the requested function. There are two such data structures,
+    g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1.
+    This parameter must point to either the g_mss_uart0 or g_mss_uart1
+    global data structure defined within the UART driver.
+
+  @param handler
+    The handler parameter is the pointer to the custom handler function. 
+    This parameter is of type mss_uart_irq_handler_t.
+
+  @return
+    This function does not return a value.
+
+  Example:
+  @code
+    MSS_UART_ set_pidpei_handler(&g_mss_uart0, my_pidpei_handler);
+  @endcode
+ */
+void
+MSS_UART_set_pidpei_handler
+(
+    mss_uart_instance_t * this_uart,
+    mss_uart_irq_handler_t handler
+);
+
+/***************************************************************************//**
+  The MSS_UART_set_linbreak_handler () function is used assign a custom 
+  interrupt handler for the LIN Break detection interrupt  when the MSS UART 
+  is operating in LIN mode.
+
+  @param this_uart
+    The this_uart parameter is a pointer to an mss_uart_instance_t
+    structure identifying the MSS UART hardware block that will perform
+    the requested function. There are two such data structures,
+    g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1.
+    This parameter must point to either the g_mss_uart0 or g_mss_uart1
+    global data structure defined within the UART driver.
+
+  @param handler
+    The handler parameter is the pointer to the custom handler function. 
+    This parameter is of type mss_uart_irq_handler_t.
+
+  @return
+    This function does not return a value.
+  Example:
+  @code
+    MSS_UART_set_linbreak_handler(&g_mss_uart0, my_break_handler);
+  @endcode
+ */
+void
+MSS_UART_set_linbreak_handler
+(
+    mss_uart_instance_t * this_uart,
+    mss_uart_irq_handler_t handler
+);
+
+/***************************************************************************//**
+  The MSS_UART_set_linsync_handler() function is used assign a custom interrupt 
+  handler for the LIN Sync character detection interrupt  when the MSS UART 
+  is operating in LIN mode.
+
+  @param this_uart
+    The this_uart parameter is a pointer to an mss_uart_instance_t
+    structure identifying the MSS UART hardware block that will perform
+    the requested function. There are two such data structures,
+    g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1.
+    This parameter must point to either the g_mss_uart0 or g_mss_uart1
+    global data structure defined within the UART driver.
+
+  @param handler
+    The handler parameter is the pointer to the custom handler function. 
+    This parameter is of type mss_uart_irq_handler_t.
+
+  @return
+    This function does not return a value.
+  Example:
+  @code
+    MSS_UART_set_linsync_handler(&g_mss_uart0, my_linsync_handler);
+  @endcode
+ */
+void
+MSS_UART_set_linsync_handler
+(
+    mss_uart_instance_t * this_uart,
+    mss_uart_irq_handler_t handler
+);
+
+/***************************************************************************//**
+  The MSS_UART_set_nack_handler() function is used assign a custom interrupt 
+  handler for the NACK character detection interrupt  when the MSS UART 
+  is operating in Smartcard mode.
+
+  @param this_uart
+    The this_uart parameter is a pointer to an mss_uart_instance_t
+    structure identifying the MSS UART hardware block that will perform
+    the requested function. There are two such data structures,
+    g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1.
+    This parameter must point to either the g_mss_uart0 or g_mss_uart1
+    global data structure defined within the UART driver.
+
+  @param handler
+    The handler parameter is the pointer to the custom handler function. 
+    This parameter is of type mss_uart_irq_handler_t.
+
+  @return
+    This function does not return a value.
+  Example:
+  @code
+    MSS_UART_set_nack_handler(&g_mss_uart0, my_nack_handler);
+  @endcode
+ */
+void
+MSS_UART_set_nack_handler
+(
+    mss_uart_instance_t * this_uart,
+    mss_uart_irq_handler_t handler
+);
+
+/***************************************************************************//**
+  The MSS_UART_set_rx_timeout_handler() function is used assign a custom 
+  interrupt handler for the receiver timeout interrupt  when the MSS UART is 
+  operating in mode. It finds application in IrDA mode of operation.
+
+  @param this_uart
+    The this_uart parameter is a pointer to an mss_uart_instance_t
+    structure identifying the MSS UART hardware block that will perform
+    the requested function. There are two such data structures,
+    g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1.
+    This parameter must point to either the g_mss_uart0 or g_mss_uart1
+    global data structure defined within the UART driver.
+
+  @param handler
+    The handler parameter is the pointer to the custom handler function. 
+    This parameter is of type mss_uart_irq_handler_t.
+
+  @return
+    This function does not return a value.
+  Example:
+  @code
+    MSS_UART_set_rx_timeout_handler(&g_mss_uart0, my_rxtimeout_handler);
+  @endcode
+ */
+void
+MSS_UART_set_rx_timeout_handler
+(
+    mss_uart_instance_t * this_uart,
+    mss_uart_irq_handler_t handler
+);
+
+/***************************************************************************//**
+  The MSS_UART_set_rxstatus_handler() function is used to register a receiver
+  status handler function that is called by the driver when a UART receiver
+  line status (RLS) interrupt occurs. You must create and register the handler
+  function to suit your application.
+
+  Note:     The MSS_UART_set_rxstatus_handler() function enables both the RLS
+  interrupt in the UART and the MSS UART instance interrupt in the Cortex-M3
+  NVIC as part of its implementation.
+
+  Note:     You can disable the RLS interrupt when required by calling the
+  MSS_UART_disable_irq() function. This is your choice and is dependent upon
+  your application.
+
+  @param this_uart
+    The this_uart parameter is a pointer to an mss_uart_instance_t
+    structure identifying the MSS UART hardware block that will perform
+    the requested function. There are two such data structures,
+    g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1.
+    This parameter must point to either the g_mss_uart0 or g_mss_uart1
+    global data structure defined within the UART driver.
+
+  @param handler
+     The handler parameter is a pointer to a receiver line status interrupt
+     handler function provided by your application that will be called as a
+     result of a UART RLS interrupt. This handler function must be of type
+     mss_uart_irq_handler_t.
+
+  @return
+     This function does not return a value.
+
+  Example:
+  @code
+  #include "mss_uart.h"
+
+  void uart_rxsts_handler(mss_uart_instance_t * this_uart)
+  {
+    uint8_t status;
+    status = MSS_UART_get_rx_status(this_uart);
+    if(status & MSS_UART_OVERUN_ERROR)
+    {
+        discard_rx_data();
+    }
+  }
+
+  int main(void)
+  {
+    MSS_UART_init( &g_mss_uart0,
+                   MSS_UART_57600_BAUD,
+                   MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY |
+                                       MSS_UART_ONE_STOP_BIT );
+                                       
+    MSS_UART_set_rxstatus_handler(&g_mss_uart0, uart_rxsts_handler);
+
+    while(1)
+    {
+        ;
+    }
+    return(0);
+  }
+  @endcode
+ */
+void
+MSS_UART_set_rxstatus_handler
+(
+    mss_uart_instance_t * this_uart,
+    mss_uart_irq_handler_t handler
+);
+
+/***************************************************************************//**
+  The MSS_UART_set_tx_handler() function is used to register a transmit handler
+  function that is called by the driver when a UART transmit holding register
+  empty (THRE) interrupt occurs. You must create and register the transmit
+  handler function to suit your application. You can use the
+  MSS_UART_fill_tx_fifo() function in your transmit handler function to
+  write data to the transmitter.
+
+  Note:     The MSS_UART_set_tx_handler() function enables both the THRE
+  interrupt in the UART and the MSS UART instance interrupt in the Cortex-M3
+  NVIC as part of its implementation.
+
+  Note:     You can disable the THRE interrupt when required by calling the
+  MSS_UART_disable_irq() function. This is your choice and is dependent upon
+  your application.
+
+  Note:     The MSS_UART_irq_tx() function does not use the transmit handler
+  function that you register with the MSS_UART_set_tx_handler() function.
+  It uses its own internal THRE interrupt handler function that overrides
+  any custom interrupt handler that you register using the
+  MSS_UART_set_tx_handler() function.
+
+  @param this_uart
+    The this_uart parameter is a pointer to an mss_uart_instance_t
+    structure identifying the MSS UART hardware block that will perform
+    the requested function. There are two such data structures,
+    g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1.
+    This parameter must point to either the g_mss_uart0 or g_mss_uart1
+    global data structure defined within the UART driver.
+
+   @param handler
+     The handler parameter is a pointer to a transmit interrupt handler
+     function provided by your application that will be called as a result
+     of a UART THRE interrupt. This handler function must be of type
+     mss_uart_irq_handler_t.
+
+   @return
+     This function does not return a value.
+
+   Example:
+   @code
+    #include "mss_uart.h"
+
+    uint8_t * g_tx_buffer;
+    size_t g_tx_size = 0;
+
+    void uart_tx_handler(mss_uart_instance_t * this_uart)
+    {
+        size_t size_in_fifo;
+        size_in_fifo = MSS_UART_fill_tx_fifo(this_uart,
+                                             (const uint8_t *)g_tx_buffer,
+                                             g_tx_size);
+                                             
+        if(size_in_fifo  ==  g_tx_size)
+        {
+            g_tx_size = 0;
+            MSS_UART_disable_irq(this_uart, MSS_UART_TBE_IRQ);
+        }
+        else
+        {
+            g_tx_buffer = &g_tx_buffer[size_in_fifo];
+            g_tx_size = g_tx_size - size_in_fifo;
+        }
+    }
+
+    int main(void)
+    {
+        uint8_t message[12] = "Hello world";
+
+        MSS_UART_init(&g_mss_uart0,
+                      MSS_UART_57600_BAUD,
+                      MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY |
+                                           MSS_UART_ONE_STOP_BIT);
+
+        g_tx_buffer = message;
+        g_tx_size = sizeof(message);
+
+        MSS_UART_set_tx_handler(&g_mss_uart0, uart_tx_handler);
+
+        while(1)
+        {
+            ;
+        }
+        return(0);
+    }
+   @endcode
+ */
+void
+MSS_UART_set_tx_handler
+(
+    mss_uart_instance_t * this_uart,
+    mss_uart_irq_handler_t handler
+);
+
+/***************************************************************************//**
+  The MSS_UART_set_modemstatus_handler() function is used to register a modem
+  status handler function that is called by the driver when a UART modem status
+  (MS) interrupt occurs. You must create and register the handler function to
+  suit your application.
+
+  Note:     The MSS_UART_set_modemstatus_handler() function enables both the MS
+  interrupt in the UART and the MSS UART instance interrupt in the Cortex-M3 NVIC
+  as part of its implementation.
+
+  Note:     You can disable the MS interrupt when required by calling the
+  MSS_UART_disable_irq() function. This is your choice and is dependent
+  upon your application.
+
+  @param this_uart
+    The this_uart parameter is a pointer to an mss_uart_instance_t
+    structure identifying the MSS UART hardware block that will perform
+    the requested function. There are two such data structures,
+    g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1.
+    This parameter must point to either the g_mss_uart0 or g_mss_uart1
+    global data structure defined within the UART driver.
+
+   @param handler
+     The handler parameter is a pointer to a modem status interrupt handler
+     function provided by your application that will be called as a result
+     of a UART MS interrupt. This handler function must be of type
+     mss_uart_irq_handler_t.
+
+   @return
+     This function does not return a value.
+
+   Example:
+   @code
+   #include "mss_uart.h"
+
+   void uart_modem_handler(mss_uart_instance_t * this_uart)
+   {
+     uint8_t status;
+     status = MSS_UART_get_modem_status(this_uart);
+     if(status & MSS_UART_CTS)
+     {
+        uart_cts_handler();
+     }
+   }
+
+   int main(void)
+   {
+      MSS_UART_init(&g_mss_uart0,
+                    MSS_UART_57600_BAUD,
+                    MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY |
+                                       MSS_UART_ONE_STOP_BIT);
+      MSS_UART_set_modemstatus_handler(&g_mss_uart0, uart_modem_handler);
+
+      while(1)
+      {
+        ;
+      }
+      return(0);
+   }
+   @endcode
+ */
+
+void
+MSS_UART_set_modemstatus_handler
+(
+    mss_uart_instance_t * this_uart,
+    mss_uart_irq_handler_t handler
+);
+
+/***************************************************************************//**
+  The MSS_UART_fill_tx_fifo() function fills the UART's hardware transmitter
+  FIFO with the data found in the transmitter buffer that is passed via the
+  tx_buffer function parameter. If the transmitter FIFO is not empty when
+  the function is called, the function returns immediately without transferring
+  any data to the FIFO; otherwise, the function transfers data from the
+  transmitter buffer to the FIFO until it is full or until the complete
+  contents of the transmitter buffer have been copied into the FIFO. The
+  function returns the number of bytes copied into the UART's transmitter FIFO.
+
+  Note:     This function reads the UART�s line status register (LSR) to check
+  for the active state of the transmitter holding register empty (THRE) bit
+  before transferring data from the data buffer to the transmitter FIFO. If
+  THRE is 0, the function returns immediately, without transferring any data
+  to the FIFO. If THRE is 1, the function transfers up to 16 bytes of data
+  to the FIFO and then returns.
+
+  Note:     The actual transmission over the serial connection will still be
+  in progress when this function returns. Use the MSS_UART_get_tx_status()
+  function if you need to know when the transmitter is empty.
+
+  @param this_uart
+    The this_uart parameter is a pointer to an mss_uart_instance_t
+    structure identifying the MSS UART hardware block that will perform
+    the requested function. There are two such data structures,
+    g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1.
+    This parameter must point to either the g_mss_uart0 or g_mss_uart1
+    global data structure defined within the UART driver.
+
+  @param tx_buffer
+    The tx_buffer parameter is a pointer to a buffer containing the data
+    to be transmitted.
+
+  @param tx_size
+    The tx_size parameter is the size in bytes, of the data to be transmitted.
+
+  @return
+    This function returns the number of bytes copied into the UART's
+    transmitter FIFO.
+
+  Example:
+  @code
+     void send_using_interrupt(uint8_t * pbuff, size_t tx_size)
+     {
+        size_t size_in_fifo;
+        size_in_fifo = MSS_UART_fill_tx_fifo(&g_mss_uart0, pbuff, tx_size);
+     }
+  @endcode
+ */
+size_t
+MSS_UART_fill_tx_fifo
+(
+    mss_uart_instance_t * this_uart,
+    const uint8_t * tx_buffer,
+    size_t tx_size
+);
+
+/***************************************************************************//**
+  The MSS_UART_get_rx_status() function returns the receiver error status of the
+  MSS UART instance. It reads both the current error status of the receiver from
+  the UART�s line status register (LSR) and the accumulated error status from
+  preceding calls to the MSS_UART_get_rx() function, and it combines them using
+  a bitwise OR. It returns the cumulative overrun, parity, framing, break and
+  FIFO error status of the receiver, since the previous call to
+  MSS_UART_get_rx_status(), as an 8-bit encoded value.
+
+  Note:     The MSS_UART_get_rx() function reads and accumulates the receiver
+  status of the MSS UART instance before reading each byte from the receiver�s
+  data register/FIFO. The driver maintains a sticky record of the cumulative
+  receiver error status, which persists after the MSS_UART_get_rx() function
+  returns. The MSS_UART_get_rx_status() function clears the driver�s sticky
+  receiver error record before returning.
+
+  Note:     The driver�s transmit functions also read the line status
+  register (LSR) as part of their implementation. When the driver reads the
+  LSR, the UART clears any active receiver error bits in the LSR. This could
+  result in the driver losing receiver errors. To avoid any loss of receiver
+  errors, the transmit functions also update the driver�s sticky record of the
+  cumulative receiver error status whenever they read the LSR.
+
+  @param this_uart
+    The this_uart parameter is a pointer to an mss_uart_instance_t
+    structure identifying the MSS UART hardware block that will perform
+    the requested function. There are two such data structures,
+    g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1.
+    This parameter must point to either the g_mss_uart0 or g_mss_uart1
+    global data structure defined within the UART driver.
+
+  @return
+    This function returns the UART�s receiver error status as an 8-bit unsigned
+    integer. The returned value is 0 if no receiver errors occurred. The driver
+    provides a set of bit mask constants that should be compared with and/or
+    used to mask the returned value to determine the receiver error status.
+    When the return value is compared to the following bit masks, a non-zero
+    result indicates that the corresponding error occurred:
+        �   MSS_UART_OVERRUN_ERROR      (bit mask = 0x02)
+        �   MSS_UART_PARITY_ERROR       (bit mask = 0x04)
+        �   MSS_UART_FRAMING_ERROR      (bit mask = 0x08)
+        �   MSS_UART_BREAK_ERROR        (bit mask = 0x10)
+        �   MSS_UART_FIFO_ERROR     (bit mask = 0x80)
+    When the return value is compared to the following bit mask, a non-zero
+    result indicates that no error occurred:
+        �   MSS_UART_NO_ERROR       (bit mask = 0x00)
+    Upon unsuccessful execution, this function returns:
+        �   MSS_UART_INVALID_PARAM      (bit mask = 0xFF)
+
+  Example:
+  @code
+    uint8_t rx_data[MAX_RX_DATA_SIZE];
+    uint8_t err_status;
+    err_status = MSS_UART_get_rx_status(&g_mss_uart0);
+
+    if(MSS_UART_NO_ERROR == err_status)
+    {
+       rx_size = MSS_UART_get_rx(&g_mss_uart0, rx_data, MAX_RX_DATA_SIZE);
+    }
+  @endcode
+ */
+uint8_t
+MSS_UART_get_rx_status
+(
+    mss_uart_instance_t * this_uart
+);
+
+/***************************************************************************//**
+  The MSS_UART_get_modem_status() function returns the modem status of the
+  MSS UART instance. It reads the modem status register (MSR) and returns
+  the 8 bit value. The bit encoding of the returned value is exactly the
+  same as the definition of the bits in the MSR.
+
+  @param this_uart
+    The this_uart parameter is a pointer to an mss_uart_instance_t
+    structure identifying the MSS UART hardware block that will perform
+    the requested function. There are two such data structures,
+    g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1.
+    This parameter must point to either the g_mss_uart0 or g_mss_uart1
+    global data structure defined within the UART driver.
+
+  @return
+    This function returns current state of the UART's MSR as an 8 bit
+    unsigned integer. The driver provides the following set of bit mask
+    constants that should be compared with and/or used to mask the
+    returned value to determine the modem status:
+        �   MSS_UART_DCTS   (bit mask = 0x01)
+        �   MSS_UART_DDSR   (bit mask = 0x02)
+        �   MSS_UART_TERI   (bit mask = 0x04)
+        �   MSS_UART_DDCD   (bit mask = 0x08)
+        �   MSS_UART_CTS    (bit mask = 0x10)
+        �   MSS_UART_DSR    (bit mask = 0x20)
+        �   MSS_UART_RI     (bit mask = 0x40)
+        �   MSS_UART_DCD    (bit mask = 0x80)
+
+  Example:
+  @code
+    void uart_modem_status_isr(mss_uart_instance_t * this_uart)
+    {
+        uint8_t status;
+        status = MSS_UART_get_modem_status(this_uart);
+        if( status & MSS_UART_DCTS )
+        {
+            uart_dcts_handler();
+        }
+        if( status & MSS_UART_CTS )
+        {
+            uart_cts_handler();
+        }
+    }
+  @endcode
+ */
+uint8_t
+MSS_UART_get_modem_status
+(
+    mss_uart_instance_t * this_uart
+);
+
+/***************************************************************************//**
+  The MSS_UART_get_tx_status() function returns the transmitter status of the
+  MSS UART instance. It reads both the UART�s line status register (LSR) and
+  returns the status of the transmit holding register empty (THRE) and
+  transmitter empty (TEMT) bits.*
+
+  @param this_uart
+    The this_uart parameter is a pointer to an mss_uart_instance_t
+    structure identifying the MSS UART hardware block that will perform
+    the requested function. There are two such data structures,
+    g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1.
+    This parameter must point to either the g_mss_uart0 or g_mss_uart1
+    global data structure defined within the UART driver.
+
+  @return
+    This function returns the UART�s transmitter status as an 8-bit unsigned
+    integer. The returned value is 0 if the transmitter status bits are not
+    set or the function execution failed. The driver provides a set of bit
+    mask constants that should be compared with and/or used to mask the
+    returned value to determine the transmitter status.
+    When the return value is compared to the following bit mask, a non-zero
+    result indicates that the corresponding transmitter status bit is set:
+        �   MSS_UART_THRE       (bit mask = 0x20)
+        �   MSS_UART_TEMT       (bit mask = 0x40)
+    When the return value is compared to the following bit mask, a non-zero
+    result indicates that the transmitter is busy or the function execution
+    failed.
+        �   MSS_UART_TX_BUSY        (bit mask = 0x00)
+
+  Example:
+  @code
+    uint8_t tx_buff[10] = "abcdefghi";
+    MSS_UART_init(&g_mss_uart0,
+                  MSS_UART_57600_BAUD,
+                  MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT); 
+
+    MSS_UART_polled_tx(&g_mss_uart0, tx_buff, sizeof(tx_buff));
+
+    while(!(MSS_UART_TEMT & MSS_UART_get_tx_status(&g_mss_uart0)))
+    {
+        ;
+    }
+  @endcode
+ */
+uint8_t
+MSS_UART_get_tx_status
+(
+    mss_uart_instance_t * this_uart
+);
+
+/***************************************************************************//**
+  The MSS_UART_set_break() function is used to send the break 
+  (9 zeros after stop bit) signal on the TX line. This function can be used 
+  only when the MSS UART is initialized in LIN mode by using MSS_UART_lin_init().
+
+  @param this_uart
+    The this_uart parameter is a pointer to an mss_uart_instance_t
+    structure identifying the MSS UART hardware block that will perform
+    the requested function. There are two such data structures,
+    g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1.
+    This parameter must point to either the g_mss_uart0 or g_mss_uart1
+    global data structure defined within the UART driver.
+
+  @return
+    This function does not return a value. 
+
+  Example:
+  @code
+    MSS_UART_init(&g_mss_uart0,
+                  MSS_UART_57600_BAUD,
+                  MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT); 
+  
+    MSS_UART_set_break(&g_mss_uart0);
+  @endcode
+ */
+void
+MSS_UART_set_break
+(
+    mss_uart_instance_t * this_uart
+);
+
+/***************************************************************************//**
+  The MSS_UART_clear_break() function is used to remove the break signal on the 
+  TX line. This function can be used only when the MSS UART is initialized in 
+  LIN mode by using MSS_UART_lin_init().
+
+  @param this_uart
+    The this_uart parameter is a pointer to an mss_uart_instance_t
+    structure identifying the MSS UART hardware block that will perform
+    the requested function. There are two such data structures,
+    g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1.
+    This parameter must point to either the g_mss_uart0 or g_mss_uart1
+    global data structure defined within the UART driver.
+
+  @return
+    This function does not return a value. 
+
+  Example:
+  @code
+    MSS_UART_init(&g_mss_uart0,
+                  MSS_UART_57600_BAUD,
+                  MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT); 
+
+    MSS_UART_clear_break(&g_mss_uart0);
+  @endcode
+ */
+void
+MSS_UART_clear_break
+(
+    mss_uart_instance_t * this_uart
+);
+
+/***************************************************************************//**
+  The MSS_UART_enable_half_duplex() function is used to enable the half-duplex 
+  (single wire) mode for the MSS UART. Though it finds application in Smartcard 
+  mode, half-duplex mode can be used in other modes as well.
+
+  @param this_uart
+    The this_uart parameter is a pointer to an mss_uart_instance_t
+    structure identifying the MSS UART hardware block that will perform
+    the requested function. There are two such data structures,
+    g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1.
+    This parameter must point to either the g_mss_uart0 or g_mss_uart1
+    global data structure defined within the UART driver.
+
+  @return
+    This function does not return a value.
+
+  Example:
+  @code
+    MSS_UART_init(&g_mss_uart0,
+                  MSS_UART_57600_BAUD,
+                  MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT); 
+
+    MSS_UART_enable_half_duplex(&g_mss_uart0);
+  @endcode
+ */
+void 
+MSS_UART_enable_half_duplex
+(
+    mss_uart_instance_t * this_uart
+);
+
+/***************************************************************************//**
+  The MSS_UART_disable_half_duplex() function is used to disable the half-duplex 
+  (single wire) mode for the MSS UART. Though it finds application in Smartcard 
+  mode, half-duplex mode can be used in other modes as well.
+
+  @param this_uart
+    The this_uart parameter is a pointer to an mss_uart_instance_t
+    structure identifying the MSS UART hardware block that will perform
+    the requested function. There are two such data structures,
+    g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1.
+    This parameter must point to either the g_mss_uart0 or g_mss_uart1
+    global data structure defined within the UART driver.
+
+  @return
+    This function does not return a value.
+
+  Example:
+  @code
+    MSS_UART_init(&g_mss_uart0,
+                  MSS_UART_57600_BAUD,
+                  MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT); 
+
+    MSS_UART_disable_half_duplex(&g_mss_uart0);
+  @endcode
+ */
+void 
+MSS_UART_disable_half_duplex
+(
+    mss_uart_instance_t * this_uart
+);
+
+/***************************************************************************//**
+  The MSS_UART_set_rx_endian() function is used to configure the LSB first or 
+  MSB first setting for MSS UART receiver
+
+  @param this_uart
+    The this_uart parameter is a pointer to an mss_uart_instance_t
+    structure identifying the MSS UART hardware block that will perform
+    the requested function. There are two such data structures,
+    g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1.
+    This parameter must point to either the g_mss_uart0 or g_mss_uart1
+    global data structure defined within the UART driver.
+  
+  @param endian
+    The endian parameter tells the LSB first or MSB first configuration. 
+    This parameter is of type mss_uart_endian_t.
+
+  @return
+    This function does not return a value.
+
+  Example:
+  @code
+    MSS_UART_init(&g_mss_uart0,
+                  MSS_UART_57600_BAUD,
+                  MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT); 
+
+    MSS_UART_set_rx_endian(&g_mss_uart0, MSS_UART_LITTLEEND);
+  @endcode
+ */
+void
+MSS_UART_set_rx_endian
+(
+    mss_uart_instance_t * this_uart,
+    mss_uart_endian_t endian    
+);
+
+/***************************************************************************//**
+  The MSS_UART_set_tx_endian() function is used to configure the LSB first or 
+  MSB first setting for MSS UART transmitter.
+
+  @param this_uart
+    The this_uart parameter is a pointer to an mss_uart_instance_t
+    structure identifying the MSS UART hardware block that will perform
+    the requested function. There are two such data structures,
+    g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1.
+    This parameter must point to either the g_mss_uart0 or g_mss_uart1
+    global data structure defined within the UART driver.
+
+  @param endian
+    The endian parameter tells the LSB first or MSB first configuration. 
+    This parameter is of type mss_uart_endian_t.
+
+  @return
+    This function does not return a value.
+
+  Example:
+  @code
+    MSS_UART_init(&g_mss_uart0,
+                  MSS_UART_57600_BAUD,
+                  MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT); 
+
+    MSS_UART_set_tx_endian(&g_mss_uart0, MSS_UART_LITTLEEND);
+  @endcode
+ */
+void
+MSS_UART_set_tx_endian
+(
+    mss_uart_instance_t * this_uart,
+    mss_uart_endian_t endian    
+);
+
+/***************************************************************************//**
+  The MSS_UART_set_filter_length () function is used to configure the glitch 
+  filter length of the MSS UART. This should be configured in accordance with 
+  the chosen baud rate.
+
+  @param this_uart
+    The this_uart parameter is a pointer to an mss_uart_instance_t
+    structure identifying the MSS UART hardware block that will perform
+    the requested function. There are two such data structures,
+    g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1.
+    This parameter must point to either the g_mss_uart0 or g_mss_uart1
+    global data structure defined within the UART driver.
+
+  @param length
+    The length parameter is of mss_uart_filter_length_t type that determines 
+    the length of the glitch filter.
+
+  @return
+    This function does not return a value.
+
+  Example:
+  @code
+    MSS_UART_init(&g_mss_uart0,
+                  MSS_UART_57600_BAUD,
+                  MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT); 
+
+    MSS_UART_set_filter_length(&g_mss_uart0, MSS_UART_LEN2);
+  @endcode
+ */
+void
+MSS_UART_set_filter_length
+(
+    mss_uart_instance_t * this_uart,
+    mss_uart_filter_length_t length
+);
+
+/***************************************************************************//**
+  The MSS_UART_enable_afm() function is used to enable address flag detection 
+  mode of the MSS UART
+
+  @param this_uart
+    The this_uart parameter is a pointer to an mss_uart_instance_t
+    structure identifying the MSS UART hardware block that will perform
+    the requested function. There are two such data structures,
+    g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1.
+    This parameter must point to either the g_mss_uart0 or g_mss_uart1
+    global data structure defined within the UART driver.
+
+  @return
+    This function does not return a value.
+
+  Example:
+  @code
+    MSS_UART_init(&g_mss_uart0,
+                  MSS_UART_57600_BAUD,
+                  MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT); 
+
+    MSS_UART_enable_afm(&g_mss_uart0);
+  @endcode
+ */
+void
+MSS_UART_enable_afm
+(
+     mss_uart_instance_t * this_uart
+);
+
+/***************************************************************************//**
+  The MSS_UART_disable_afm() function is used to disable address flag detection 
+  mode of the MSS UART.
+
+  @param this_uart
+    The this_uart parameter is a pointer to an mss_uart_instance_t
+    structure identifying the MSS UART hardware block that will perform
+    the requested function. There are two such data structures,
+    g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1.
+    This parameter must point to either the g_mss_uart0 or g_mss_uart1
+    global data structure defined within the UART driver.
+
+  @return
+    This function does not return a value.
+
+  Example:
+  @code
+    MSS_UART_init(&g_mss_uart0,
+                  MSS_UART_57600_BAUD,
+                  MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT); 
+
+    MSS_UART_disable_afm(&g_mss_uart0);
+  @endcode
+ */
+void
+MSS_UART_disable_afm
+(
+     mss_uart_instance_t * this_uart
+);
+
+/***************************************************************************//**
+  The MSS_UART_enable_afclear () function is used to enable address flag clear 
+  of the MSS UART. This should be used in conjunction with address flag 
+  detection mode (AFM).
+
+  @param this_uart
+    The this_uart parameter is a pointer to an mss_uart_instance_t
+    structure identifying the MSS UART hardware block that will perform
+    the requested function. There are two such data structures,
+    g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1.
+    This parameter must point to either the g_mss_uart0 or g_mss_uart1
+    global data structure defined within the UART driver.
+
+  @return
+    This function does not return a value.
+
+  Example:
+  @code
+    MSS_UART_init(&g_mss_uart0,
+                  MSS_UART_57600_BAUD,
+                  MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT); 
+
+    MSS_UART_enable_afclear(&g_mss_uart0);
+  @endcode
+ */
+void
+MSS_UART_enable_afclear
+(
+     mss_uart_instance_t * this_uart
+);
+
+/***************************************************************************//**
+  The MSS_UART_disable_afclear () function is used to disable address flag 
+  clear of the MSS UART. This should be used in conjunction with address flag 
+  detection mode (AFM).
+
+  @param this_uart
+    The this_uart parameter is a pointer to an mss_uart_instance_t
+    structure identifying the MSS UART hardware block that will perform
+    the requested function. There are two such data structures,
+    g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1.
+    This parameter must point to either the g_mss_uart0 or g_mss_uart1
+    global data structure defined within the UART driver.
+
+  @return
+    This function does not return a value.
+  
+  Example:
+  @code
+    MSS_UART_init(&g_mss_uart0,
+                  MSS_UART_57600_BAUD,
+                  MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT); 
+
+    MSS_UART_disable_afclear(&g_mss_uart0);
+  @endcode
+ */
+void
+MSS_UART_disable_afclear
+(
+     mss_uart_instance_t * this_uart
+);
+
+/***************************************************************************//**
+  The MSS_UART_enable_rx_timeout() function is used to enable and configure 
+  the receiver timeout functionality of MSS UART. This function accepts the 
+  timeout parameter and applies the timeout based up on the baud rate as per 
+  the formula 4 x timeout x bit time.
+
+  @param this_uart
+    The this_uart parameter is a pointer to an mss_uart_instance_t
+    structure identifying the MSS UART hardware block that will perform
+    the requested function. There are two such data structures,
+    g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1.
+    This parameter must point to either the g_mss_uart0 or g_mss_uart1
+    global data structure defined within the UART driver.
+
+  @param timeout
+    The timeout parameter specifies the receiver timeout multiple. 
+    It should be configured according to the baud rate in use.
+
+  @return
+    This function does not return a value.
+
+  Example:
+  @code
+    MSS_UART_init(&g_mss_uart0,
+                  MSS_UART_57600_BAUD,
+                  MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT); 
+
+    MSS_UART_enable_rx_timeout(&g_mss_uart0 , 24);
+  @endcode
+ */
+void 
+MSS_UART_enable_rx_timeout
+(
+    mss_uart_instance_t * this_uart,
+    uint8_t timeout
+);
+
+/***************************************************************************//**
+  The MSS_UART_disable_rx_timeout() function is used to disable the receiver 
+  timeout functionality of MSS UART. 
+
+  @param this_uart
+    The this_uart parameter is a pointer to an mss_uart_instance_t
+    structure identifying the MSS UART hardware block that will perform
+    the requested function. There are two such data structures,
+    g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1.
+    This parameter must point to either the g_mss_uart0 or g_mss_uart1
+    global data structure defined within the UART driver.
+
+  @return
+    This function does not return a value.
+
+  Example:
+  @code
+    MSS_UART_init(&g_mss_uart0,
+                  MSS_UART_57600_BAUD,
+                  MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT); 
+
+    MSS_UART_disable_rx_timeout(&g_mss_uart0);
+  @endcode
+ */
+void 
+MSS_UART_disable_rx_timeout
+(
+    mss_uart_instance_t * this_uart
+);
+
+/***************************************************************************//**
+  The MSS_UART_enable_tx_time_guard() function is used to enable and configure 
+  the transmitter time guard functionality of MSS UART. This function accepts 
+  the timeguard parameter and applies the timeguard based up on the baud rate
+  as per the formula timeguard x bit time.
+
+  @param this_uart
+    The this_uart parameter is a pointer to an mss_uart_instance_t
+    structure identifying the MSS UART hardware block that will perform
+    the requested function. There are two such data structures,
+    g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1.
+    This parameter must point to either the g_mss_uart0 or g_mss_uart1
+    global data structure defined within the UART driver.
+
+  @return
+    This function does not return a value.
+
+  Example:
+  @code
+    MSS_UART_init(&g_mss_uart0,
+                  MSS_UART_57600_BAUD,
+                  MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT); 
+
+    MSS_UART_enable_tx_time_guard(&g_mss_uart0 , 24);
+  @endcode
+ */
+void 
+MSS_UART_enable_tx_time_guard
+(
+    mss_uart_instance_t * this_uart,
+    uint8_t timeguard
+);
+
+/***************************************************************************//**
+  The MSS_UART_disable_tx_time_guard() function is used to disable the 
+  transmitter time guard functionality of MSS UART. 
+
+  @param this_uart
+    The this_uart parameter is a pointer to an mss_uart_instance_t
+    structure identifying the MSS UART hardware block that will perform
+    the requested function. There are two such data structures,
+    g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1.
+    This parameter must point to either the g_mss_uart0 or g_mss_uart1
+    global data structure defined within the UART driver.
+
+  @return
+    This function does not return a value.
+
+  Example:
+  @code
+    MSS_UART_init(&g_mss_uart0,
+                  MSS_UART_57600_BAUD,
+                  MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT); 
+                  
+    MSS_UART_disable_tx_time_guard(&g_mss_uart0);
+  @endcode
+ */
+void 
+MSS_UART_disable_tx_time_guard
+(
+    mss_uart_instance_t * this_uart
+);
+
+/***************************************************************************//**
+  The MSS_UART_set_address() function is used to set the 8-bit address for 
+  the MSS UART referenced by this_uart parameter. 
+
+  @param this_uart
+    The this_uart parameter is a pointer to an mss_uart_instance_t
+    structure identifying the MSS UART hardware block that will perform
+    the requested function. There are two such data structures,
+    g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1.
+    This parameter must point to either the g_mss_uart0 or g_mss_uart1
+    global data structure defined within the UART driver.
+
+  @param address
+    The address parameter is the 8-bit address which is to be configured 
+    to the MSS UART referenced by this_uart parameter.
+
+  @return
+    This function does not return a value.
+
+  Example:
+  @code
+    MSS_UART_init(&g_mss_uart0,
+                  MSS_UART_57600_BAUD,
+                  MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT); 
+                  
+    MSS_UART_set_address(&g_mss_uart0, 0xAA);
+  @endcode
+ */
+void
+MSS_UART_set_address
+(
+    mss_uart_instance_t * this_uart,
+    uint8_t address
+);
+
+/***************************************************************************//**
+  The MSS_UART_set_ready_mode() function is used to configure the MODE0 or MODE1 
+  to the TXRDY and RXRDY signals of the MSS UART referenced by this_uart 
+  parameter. The mode parameter is used to provide the mode to be configured.
+
+  @param this_uart
+    The this_uart parameter is a pointer to an mss_uart_instance_t
+    structure identifying the MSS UART hardware block that will perform
+    the requested function. There are two such data structures,
+    g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1.
+    This parameter must point to either the g_mss_uart0 or g_mss_uart1
+    global data structure defined within the UART driver.
+
+  @param mode
+    The mode parameter is the mss_uart_ready_mode_t type which is used to 
+    configure the TXRDY and RXRDY signal modes.
+
+  @return
+    This function does not return a value.
+
+  Example:
+  @code
+    MSS_UART_init(&g_mss_uart0,
+                  MSS_UART_57600_BAUD,
+                  MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT); 
+
+    MSS_UART_set_ready_mode(&g_mss_uart0, MSS_UART_READY_MODE0);    
+  @endcode
+ */
+void 
+MSS_UART_set_ready_mode
+(
+    mss_uart_instance_t * this_uart,
+    mss_uart_ready_mode_t mode    
+);
+
+/***************************************************************************//**
+  The MSS_UART_set_usart_mode() function is used to configure the MSS UART 
+  referenced by the parameter this_uart in USART mode. Various USART modes 
+  are supported which can be configured by the parameter mode of type 
+  mss_uart_usart_mode_t.
+
+  @param this_uart
+    The this_uart parameter is a pointer to an mss_uart_instance_t
+    structure identifying the MSS UART hardware block that will perform
+    the requested function. There are two such data structures,
+    g_mss_uart0 and g_mss_uart1, associated with MSS UART0 and MSS UART1.
+    This parameter must point to either the g_mss_uart0 or g_mss_uart1
+    global data structure defined within the UART driver.
+
+  @param mode
+    The mode parameter is the USART mode to be configured. 
+    This parameter is of type mss_uart_usart_mode_t.
+
+  @return
+    This function does not return a value.
+
+  Example:
+  @code
+    MSS_UART_init(&g_mss_uart0,
+                  MSS_UART_57600_BAUD,
+                  MSS_UART_DATA_8_BITS | MSS_UART_NO_PARITY | MSS_UART_ONE_STOP_BIT);  
+
+    MSS_UART_set_usart_mode(&g_mss_uart0, MSS_UART_SYNC_MASTER_POS_EDGE_CLK);
+  @endcode
+ */
+void 
+MSS_UART_set_usart_mode
+(
+    mss_uart_instance_t * this_uart,
+    mss_uart_usart_mode_t mode
+);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MSS_UART_H_ */
diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_uart/mss_uart_regs.h b/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_uart/mss_uart_regs.h
new file mode 100644
index 000000000..2367525a0
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers/mss_uart/mss_uart_regs.h
@@ -0,0 +1,83 @@
+/*******************************************************************************
+ * (c) Copyright 2011-2013 Microsemi SoC Products Group.  All rights reserved.
+ * 
+ * Register bit offsets and masks defintions for SmartFusion2 MSS MMUART.
+ * 
+ * SVN $Revision: 5610 $
+ * SVN $Date: 2013-04-05 14:19:30 +0100 (Fri, 05 Apr 2013) $
+ */
+#ifndef MSS_UART_REGS_H_
+#define MSS_UART_REGS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*******************************************************************************
+ Register Bit definitions
+ */
+
+/* Line Control register bit definitions */
+#define SB                  6u      /* Set break */
+#define DLAB                7u      /* Divisor latch access bit */
+
+/* FIFO Control register bit definitions */
+#define RXRDY_TXRDYN_EN     0u      /* Enable TXRDY and RXRDY signals */
+#define CLEAR_RX_FIFO       1u      /* Clear receiver FIFO */
+#define CLEAR_TX_FIFO       2u      /* Clear transimtter FIFO */
+#define RDYMODE             3u      /* Mode 0 or Mode 1 for TXRDY and RXRDY */
+
+/* Modem Control register bit definitions */
+#define LOOP                4u      /* Local loopback */
+#define RLOOP               5u      /* Remote loopback */
+#define ECHO                6u      /* Automatic echo */
+#define RLOOP_MASK          0x6u    /* Remote loopback & Automatic echo*/
+
+/* Line Status register bit definitions   */
+#define DR                  0u      /* Data ready */
+#define THRE                5u      /* Transmitter holding register empty */
+#define TEMT                6u      /* Transitter empty */
+
+/* Interrupt Enable register bit definitions */
+#define ERBFI               0u      /* Enable receiver buffer full interrupt */
+#define ETBEI               1u      /* Enable transmitter buffer empty interrupt */
+#define ELSI                2u      /* Enable line status interrupt */
+#define EDSSI               3u      /* Enable modem status interrupt */
+
+/* Multimode register 0 bit definitions */
+#define ELIN                3u      /* Enable LIN header detection */
+#define ETTG                5u      /* Enable transmitter time guard */
+#define ERTO                6u      /* Enable receiver time-out */
+#define EFBR                7u      /* Enable fractional baud rate mode */
+
+/* Multimode register 1 bit definitions */
+#define E_MSB_RX            0u      /* MSB / LSB first for receiver */
+#define E_MSB_TX            1u      /* MSB / LSB first for transmitter */
+#define EIRD                2u      /* Enable IrDA modem */
+#define EIRX                3u      /* Input polarity for IrDA modem */
+#define EITX                4u      /* Output polarity for IrDA modem */
+#define EITP                5u      /* Output pulse width for IrDA modem */      
+
+/* Multimode register 2 bit definitions */
+#define EERR                0u      /* Enable ERR / NACK during stop time */
+#define EAFM                1u      /* Enable 9-bit address flag mode */
+#define EAFC                2u      /* Enable address flag clear */
+#define ESWM                3u      /* Enable single wire half-duplex mode */
+
+/* Multimode Interrupt Enable register and
+   Multimode Interrupt Identification register definitions */
+#define ERTOI               0u      /* Enable receiver timeout interrupt */
+#define ENACKI              1u      /* Enable NACK / ERR interrupt */
+#define EPID_PEI            2u      /* Enable PID parity error interrupt */
+#define ELINBI              3u      /* Enable LIN break interrupt */
+#define ELINSI              4u      /* Enable LIN sync detection interrupt */
+
+
+#ifdef __cplusplus                       
+}
+#endif
+
+#endif /* MSS_UART_REGS_H_ */
+
+
+
diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers_config/sys_config/sys_config.c b/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers_config/sys_config/sys_config.c
new file mode 100644
index 000000000..9184e99ec
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers_config/sys_config/sys_config.c
@@ -0,0 +1,385 @@
+/*******************************************************************************
+ * (c) Copyright 2012 Microsemi SoC Products Group.  All rights reserved.
+ *
+ *  Smartfusion2 system configuration. This file is automatically generated
+ *  by the Libero tools. It contains the Smartfusion2 system configuration that
+ *  was selected during the hardware configuration flow. 
+ *
+ */
+
+#include "../../CMSIS/m2sxxx.h"
+#include "../../CMSIS/sys_init_cfg_types.h"
+#include "sys_config.h"
+
+/*==============================================================================
+ *                             !!! WARNING !!!
+ *==============================================================================
+ * The project including this file must be linked so that the content of this
+ * file is located in internal eNVM at run time. The content of this file is
+ * used to configure the system prior to RAM content initialization. This means
+ * that the content of the data structures below will be used before the copy
+ * from LMA to VMA takes place. The LMA and VMA locations of the content of this
+ * file must be identical for the system to be seamlessly configured as part of
+ * the CMSIS boot process.
+ */
+ 
+/*==============================================================================
+ * Clock configuration
+ */
+/* No configuration data structure required. */
+
+/*==============================================================================
+ * Memory remapping configuration
+ */
+/* TBD. */
+
+/*==============================================================================
+ * MDDR configuration
+ */
+#if MSS_SYS_MDDR_CONFIG_BY_CORTEX
+
+#include "sys_config_mddr_define.h"
+
+MDDR_TypeDef * const g_m2s_mddr_addr = (MDDR_TypeDef *)0x40020800;
+
+const ddr_subsys_cfg_t g_m2s_mddr_subsys_config =
+{
+    /*---------------------------------------------------------------------
+     * DDR Controller registers.
+     * All registers are 16-bit wide unless mentioned beside the definition.
+     */
+    {
+        MDDR_DDRC_DYN_SOFT_RESET_CR,
+        MDDR_DDRC_RESERVED0,
+        MDDR_DDRC_DYN_REFRESH_1_CR,
+        MDDR_DDRC_DYN_REFRESH_2_CR,
+        MDDR_DDRC_DYN_POWERDOWN_CR,
+        MDDR_DDRC_DYN_DEBUG_CR,
+        MDDR_DDRC_MODE_CR,
+        MDDR_DDRC_ADDR_MAP_BANK_CR,
+        MDDR_DDRC_ECC_DATA_MASK_CR,
+        MDDR_DDRC_ADDR_MAP_COL_1_CR,
+        MDDR_DDRC_ADDR_MAP_COL_2_CR,
+        MDDR_DDRC_ADDR_MAP_ROW_1_CR,
+        MDDR_DDRC_ADDR_MAP_ROW_2_CR,
+        MDDR_DDRC_INIT_1_CR,
+        MDDR_DDRC_CKE_RSTN_CYCLES_1_CR,
+        MDDR_DDRC_CKE_RSTN_CYCLES_2_CR,
+        MDDR_DDRC_INIT_MR_CR,
+        MDDR_DDRC_INIT_EMR_CR,
+        MDDR_DDRC_INIT_EMR2_CR,
+        MDDR_DDRC_INIT_EMR3_CR,
+        MDDR_DDRC_DRAM_BANK_TIMING_PARAM_CR,
+        MDDR_DDRC_DRAM_RD_WR_LATENCY_CR,
+        MDDR_DDRC_DRAM_RD_WR_PRE_CR,
+        MDDR_DDRC_DRAM_MR_TIMING_PARAM_CR,
+        MDDR_DDRC_DRAM_RAS_TIMING_CR,
+        MDDR_DDRC_DRAM_RD_WR_TRNARND_TIME_CR,
+        MDDR_DDRC_DRAM_T_PD_CR,
+        MDDR_DDRC_DRAM_BANK_ACT_TIMING_CR,
+        MDDR_DDRC_ODT_PARAM_1_CR,
+        MDDR_DDRC_ODT_PARAM_2_CR,
+        MDDR_DDRC_ADDR_MAP_COL_3_CR,
+        MDDR_DDRC_MODE_REG_RD_WR_CR,
+        MDDR_DDRC_MODE_REG_DATA_CR,
+        MDDR_DDRC_PWR_SAVE_1_CR,
+        MDDR_DDRC_PWR_SAVE_2_CR,
+        MDDR_DDRC_ZQ_LONG_TIME_CR,
+        MDDR_DDRC_ZQ_SHORT_TIME_CR,
+        MDDR_DDRC_ZQ_SHORT_INT_REFRESH_MARGIN_1_CR,
+        MDDR_DDRC_ZQ_SHORT_INT_REFRESH_MARGIN_2_CR,
+        MDDR_DDRC_PERF_PARAM_1_CR,
+        MDDR_DDRC_HPR_QUEUE_PARAM_1_CR,
+        MDDR_DDRC_HPR_QUEUE_PARAM_2_CR,
+        MDDR_DDRC_LPR_QUEUE_PARAM_1_CR,
+        MDDR_DDRC_LPR_QUEUE_PARAM_2_CR,
+        MDDR_DDRC_WR_QUEUE_PARAM_CR,
+        MDDR_DDRC_PERF_PARAM_2_CR,
+        MDDR_DDRC_PERF_PARAM_3_CR,
+        MDDR_DDRC_DFI_RDDATA_EN_CR,
+        MDDR_DDRC_DFI_MIN_CTRLUPD_TIMING_CR,
+        MDDR_DDRC_DFI_MAX_CTRLUPD_TIMING_CR,
+        MDDR_DDRC_DFI_WR_LVL_CONTROL_1_CR,
+        MDDR_DDRC_DFI_WR_LVL_CONTROL_2_CR,
+        MDDR_DDRC_DFI_RD_LVL_CONTROL_1_CR,
+        MDDR_DDRC_DFI_RD_LVL_CONTROL_2_CR,
+        MDDR_DDRC_DFI_CTRLUPD_TIME_INTERVAL_CR,
+        MDDR_DDRC_DYN_SOFT_RESET_ALIAS_CR,
+        MDDR_DDRC_AXI_FABRIC_PRI_ID_CR,
+    },
+
+    /*---------------------------------------------------------------------
+     * DDR PHY configuration registers
+     */
+    {
+        MDDR_PHY_LOOPBACK_TEST_CR,
+        MDDR_PHY_BOARD_LOOPBACK_CR,
+        MDDR_PHY_CTRL_SLAVE_RATIO_CR,
+        MDDR_PHY_CTRL_SLAVE_FORCE_CR,
+        MDDR_PHY_CTRL_SLAVE_DELAY_CR,
+        MDDR_PHY_DATA_SLICE_IN_USE_CR,
+        MDDR_PHY_LVL_NUM_OF_DQ0_CR,
+        MDDR_PHY_DQ_OFFSET_1_CR,
+        MDDR_PHY_DQ_OFFSET_2_CR,
+        MDDR_PHY_DQ_OFFSET_3_CR,
+        MDDR_PHY_DIS_CALIB_RST_CR,
+        MDDR_PHY_DLL_LOCK_DIFF_CR,
+        MDDR_PHY_FIFO_WE_IN_DELAY_1_CR,
+        MDDR_PHY_FIFO_WE_IN_DELAY_2_CR,
+        MDDR_PHY_FIFO_WE_IN_DELAY_3_CR,
+        MDDR_PHY_FIFO_WE_IN_FORCE_CR,
+        MDDR_PHY_FIFO_WE_SLAVE_RATIO_1_CR,
+        MDDR_PHY_FIFO_WE_SLAVE_RATIO_2_CR,
+        MDDR_PHY_FIFO_WE_SLAVE_RATIO_3_CR,
+        MDDR_PHY_FIFO_WE_SLAVE_RATIO_4_CR,
+        MDDR_PHY_GATELVL_INIT_MODE_CR,
+        MDDR_PHY_GATELVL_INIT_RATIO_1_CR,
+        MDDR_PHY_GATELVL_INIT_RATIO_2_CR,
+        MDDR_PHY_GATELVL_INIT_RATIO_3_CR,
+        MDDR_PHY_GATELVL_INIT_RATIO_4_CR,
+        MDDR_PHY_LOCAL_ODT_CR,
+        MDDR_PHY_INVERT_CLKOUT_CR,
+        MDDR_PHY_RD_DQS_SLAVE_DELAY_1_CR,
+        MDDR_PHY_RD_DQS_SLAVE_DELAY_2_CR,
+        MDDR_PHY_RD_DQS_SLAVE_DELAY_3_CR,
+        MDDR_PHY_RD_DQS_SLAVE_FORCE_CR,
+        MDDR_PHY_RD_DQS_SLAVE_RATIO_1_CR,
+        MDDR_PHY_RD_DQS_SLAVE_RATIO_2_CR,
+        MDDR_PHY_RD_DQS_SLAVE_RATIO_3_CR,
+        MDDR_PHY_RD_DQS_SLAVE_RATIO_4_CR,
+        MDDR_PHY_WR_DQS_SLAVE_DELAY_1_CR,
+        MDDR_PHY_WR_DQS_SLAVE_DELAY_2_CR,
+        MDDR_PHY_WR_DQS_SLAVE_DELAY_3_CR,
+        MDDR_PHY_WR_DQS_SLAVE_FORCE_CR,
+        MDDR_PHY_WR_DQS_SLAVE_RATIO_1_CR,
+        MDDR_PHY_WR_DQS_SLAVE_RATIO_2_CR,
+        MDDR_PHY_WR_DQS_SLAVE_RATIO_3_CR,
+        MDDR_PHY_WR_DQS_SLAVE_RATIO_4_CR,
+        MDDR_PHY_WR_DATA_SLAVE_DELAY_1_CR,
+        MDDR_PHY_WR_DATA_SLAVE_DELAY_2_CR,
+        MDDR_PHY_WR_DATA_SLAVE_DELAY_3_CR,
+        MDDR_PHY_WR_DATA_SLAVE_FORCE_CR,
+        MDDR_PHY_WR_DATA_SLAVE_RATIO_1_CR,
+        MDDR_PHY_WR_DATA_SLAVE_RATIO_2_CR,
+        MDDR_PHY_WR_DATA_SLAVE_RATIO_3_CR,
+        MDDR_PHY_WR_DATA_SLAVE_RATIO_4_CR,
+        MDDR_PHY_WRLVL_INIT_MODE_CR,
+        MDDR_PHY_WRLVL_INIT_RATIO_1_CR,
+        MDDR_PHY_WRLVL_INIT_RATIO_2_CR,
+        MDDR_PHY_WRLVL_INIT_RATIO_3_CR,
+        MDDR_PHY_WRLVL_INIT_RATIO_4_CR,
+        MDDR_PHY_WR_RD_RL_CR,
+        MDDR_PHY_RDC_FIFO_RST_ERR_CNT_CLR_CR,
+        MDDR_PHY_RDC_WE_TO_RE_DELAY_CR,
+        MDDR_PHY_USE_FIXED_RE_CR,
+        MDDR_PHY_USE_RANK0_DELAYS_CR,
+        MDDR_PHY_USE_LVL_TRNG_LEVEL_CR,
+        MDDR_PHY_DYN_CONFIG_CR,
+        MDDR_PHY_RD_WR_GATE_LVL_CR,
+        MDDR_PHY_DYN_RESET_CR
+    },
+    
+    /*---------------------------------------------------------------------
+     * FIC-64 registers
+     * These registers are 16-bit wide and 32-bit aligned.
+     */
+    {
+        MDDR_DDR_FIC_NB_ADDR_CR,
+        MDDR_DDR_FIC_NBRWB_SIZE_CR,
+        MDDR_DDR_FIC_WB_TIMEOUT_CR,
+        MDDR_DDR_FIC_HPD_SW_RW_EN_CR,
+        MDDR_DDR_FIC_HPD_SW_RW_INVAL_CR,
+        MDDR_DDR_FIC_SW_WR_ERCLR_CR,
+        MDDR_DDR_FIC_ERR_INT_ENABLE_CR,
+        MDDR_DDR_FIC_NUM_AHB_MASTERS_CR,
+        MDDR_DDR_FIC_LOCK_TIMEOUTVAL_1_CR,
+        MDDR_DDR_FIC_LOCK_TIMEOUTVAL_2_CR,
+        MDDR_DDR_FIC_LOCK_TIMEOUT_EN_CR
+    }
+};
+
+#endif
+
+/*==============================================================================
+ * FDDR configuration
+ */
+#if MSS_SYS_FDDR_CONFIG_BY_CORTEX
+
+#include "sys_config_fddr_define.h"
+
+FDDR_TypeDef * const g_m2s_fddr_addr = (FDDR_TypeDef *)0x40021000;
+
+const fddr_sysreg_t g_m2s_fddr_sysreg_subsys_config =
+{
+    0x0001u,    /* PLL_CONFIG_LOW_1 */
+    0x0002u,    /* PLL_CONFIG_LOW_2 */
+    0x0003u,    /* PLL_CONFIG_HIGH */
+    0x0004u,    /* FACC_CLK_EN */
+    0x0005u,    /* FACC_MUX_CONFIG */
+    0x0006u,    /* FACC_DIVISOR_RATIO */
+    0x0007u,    /* PLL_DELAY_LINE_SEL */
+    0x0008u,    /* SOFT_RESET */
+    0x0009u,    /* IO_CALIB */
+    0x000Au,    /* INTERRUPT_ENABLE */
+    0x000Bu,    /* AXI_AHB_MODE_SEL */
+    0x000Cu     /* PHY_SELF_REF_EN */
+};
+
+const ddr_subsys_cfg_t g_m2s_fddr_subsys_config = 
+{
+    /*---------------------------------------------------------------------
+     * DDR Controller registers.
+     * All registers are 16-bit wide unless mentioned beside the definition.
+     */
+    {
+        FDDR_DDRC_DYN_SOFT_RESET_CR,
+        FDDR_DDRC_RESERVED0,
+        FDDR_DDRC_DYN_REFRESH_1_CR,
+        FDDR_DDRC_DYN_REFRESH_2_CR,
+        FDDR_DDRC_DYN_POWERDOWN_CR,
+        FDDR_DDRC_DYN_DEBUG_CR,
+        FDDR_DDRC_MODE_CR,
+        FDDR_DDRC_ADDR_MAP_BANK_CR,
+        FDDR_DDRC_ECC_DATA_MASK_CR,
+        FDDR_DDRC_ADDR_MAP_COL_1_CR,
+        FDDR_DDRC_ADDR_MAP_COL_2_CR,
+        FDDR_DDRC_ADDR_MAP_ROW_1_CR,
+        FDDR_DDRC_ADDR_MAP_ROW_2_CR,
+        FDDR_DDRC_INIT_1_CR,
+        FDDR_DDRC_CKE_RSTN_CYCLES_1_CR,
+        FDDR_DDRC_CKE_RSTN_CYCLES_2_CR,
+        FDDR_DDRC_INIT_MR_CR,
+        FDDR_DDRC_INIT_EMR_CR,
+        FDDR_DDRC_INIT_EMR2_CR,
+        FDDR_DDRC_INIT_EMR3_CR,
+        FDDR_DDRC_DRAM_BANK_TIMING_PARAM_CR,
+        FDDR_DDRC_DRAM_RD_WR_LATENCY_CR,
+        FDDR_DDRC_DRAM_RD_WR_PRE_CR,
+        FDDR_DDRC_DRAM_MR_TIMING_PARAM_CR,
+        FDDR_DDRC_DRAM_RAS_TIMING_CR,
+        FDDR_DDRC_DRAM_RD_WR_TRNARND_TIME_CR,
+        FDDR_DDRC_DRAM_T_PD_CR,
+        FDDR_DDRC_DRAM_BANK_ACT_TIMING_CR,
+        FDDR_DDRC_ODT_PARAM_1_CR,
+        FDDR_DDRC_ODT_PARAM_2_CR,
+        FDDR_DDRC_ADDR_MAP_COL_3_CR,
+        FDDR_DDRC_MODE_REG_RD_WR_CR,
+        FDDR_DDRC_MODE_REG_DATA_CR,
+        FDDR_DDRC_PWR_SAVE_1_CR,
+        FDDR_DDRC_PWR_SAVE_2_CR,
+        FDDR_DDRC_ZQ_LONG_TIME_CR,
+        FDDR_DDRC_ZQ_SHORT_TIME_CR,
+        FDDR_DDRC_ZQ_SHORT_INT_REFRESH_MARGIN_1_CR,
+        FDDR_DDRC_ZQ_SHORT_INT_REFRESH_MARGIN_2_CR,
+        FDDR_DDRC_PERF_PARAM_1_CR,
+        FDDR_DDRC_HPR_QUEUE_PARAM_1_CR,
+        FDDR_DDRC_HPR_QUEUE_PARAM_2_CR,
+        FDDR_DDRC_LPR_QUEUE_PARAM_1_CR,
+        FDDR_DDRC_LPR_QUEUE_PARAM_2_CR,
+        FDDR_DDRC_WR_QUEUE_PARAM_CR,
+        FDDR_DDRC_PERF_PARAM_2_CR,
+        FDDR_DDRC_PERF_PARAM_3_CR,
+        FDDR_DDRC_DFI_RDDATA_EN_CR,
+        FDDR_DDRC_DFI_MIN_CTRLUPD_TIMING_CR,
+        FDDR_DDRC_DFI_MAX_CTRLUPD_TIMING_CR,
+        FDDR_DDRC_DFI_WR_LVL_CONTROL_1_CR,
+        FDDR_DDRC_DFI_WR_LVL_CONTROL_2_CR,
+        FDDR_DDRC_DFI_RD_LVL_CONTROL_1_CR,
+        FDDR_DDRC_DFI_RD_LVL_CONTROL_2_CR,
+        FDDR_DDRC_DFI_CTRLUPD_TIME_INTERVAL_CR,
+        FDDR_DDRC_DYN_SOFT_RESET_ALIAS_CR,
+        FDDR_DDRC_AXI_FABRIC_PRI_ID_CR
+    },
+
+    /*---------------------------------------------------------------------
+     * DDR PHY configuration registers
+     */
+    {
+        FDDR_PHY_LOOPBACK_TEST_CR,
+        FDDR_PHY_BOARD_LOOPBACK_CR,
+        FDDR_PHY_CTRL_SLAVE_RATIO_CR,
+        FDDR_PHY_CTRL_SLAVE_FORCE_CR,
+        FDDR_PHY_CTRL_SLAVE_DELAY_CR,
+        FDDR_PHY_DATA_SLICE_IN_USE_CR,
+        FDDR_PHY_LVL_NUM_OF_DQ0_CR,
+        FDDR_PHY_DQ_OFFSET_1_CR,
+        FDDR_PHY_DQ_OFFSET_2_CR,
+        FDDR_PHY_DQ_OFFSET_3_CR,
+        FDDR_PHY_DIS_CALIB_RST_CR,
+        FDDR_PHY_DLL_LOCK_DIFF_CR,
+        FDDR_PHY_FIFO_WE_IN_DELAY_1_CR,
+        FDDR_PHY_FIFO_WE_IN_DELAY_2_CR,
+        FDDR_PHY_FIFO_WE_IN_DELAY_3_CR,
+        FDDR_PHY_FIFO_WE_IN_FORCE_CR,
+        FDDR_PHY_FIFO_WE_SLAVE_RATIO_1_CR,
+        FDDR_PHY_FIFO_WE_SLAVE_RATIO_2_CR,
+        FDDR_PHY_FIFO_WE_SLAVE_RATIO_3_CR,
+        FDDR_PHY_FIFO_WE_SLAVE_RATIO_4_CR,
+        FDDR_PHY_GATELVL_INIT_MODE_CR,
+        FDDR_PHY_GATELVL_INIT_RATIO_1_CR,
+        FDDR_PHY_GATELVL_INIT_RATIO_2_CR,
+        FDDR_PHY_GATELVL_INIT_RATIO_3_CR,
+        FDDR_PHY_GATELVL_INIT_RATIO_4_CR,
+        FDDR_PHY_LOCAL_ODT_CR,
+        FDDR_PHY_INVERT_CLKOUT_CR,
+        FDDR_PHY_RD_DQS_SLAVE_DELAY_1_CR,
+        FDDR_PHY_RD_DQS_SLAVE_DELAY_2_CR,
+        FDDR_PHY_RD_DQS_SLAVE_DELAY_3_CR,
+        FDDR_PHY_RD_DQS_SLAVE_FORCE_CR,
+        FDDR_PHY_RD_DQS_SLAVE_RATIO_1_CR,
+        FDDR_PHY_RD_DQS_SLAVE_RATIO_2_CR,
+        FDDR_PHY_RD_DQS_SLAVE_RATIO_3_CR,
+        FDDR_PHY_RD_DQS_SLAVE_RATIO_4_CR,
+        FDDR_PHY_WR_DQS_SLAVE_DELAY_1_CR,
+        FDDR_PHY_WR_DQS_SLAVE_DELAY_2_CR,
+        FDDR_PHY_WR_DQS_SLAVE_DELAY_3_CR,
+        FDDR_PHY_WR_DQS_SLAVE_FORCE_CR,
+        FDDR_PHY_WR_DQS_SLAVE_RATIO_1_CR,
+        FDDR_PHY_WR_DQS_SLAVE_RATIO_2_CR,
+        FDDR_PHY_WR_DQS_SLAVE_RATIO_3_CR,
+        FDDR_PHY_WR_DQS_SLAVE_RATIO_4_CR,
+        FDDR_PHY_WR_DATA_SLAVE_DELAY_1_CR,
+        FDDR_PHY_WR_DATA_SLAVE_DELAY_2_CR,
+        FDDR_PHY_WR_DATA_SLAVE_DELAY_3_CR,
+        FDDR_PHY_WR_DATA_SLAVE_FORCE_CR,
+        FDDR_PHY_WR_DATA_SLAVE_RATIO_1_CR,
+        FDDR_PHY_WR_DATA_SLAVE_RATIO_2_CR,
+        FDDR_PHY_WR_DATA_SLAVE_RATIO_3_CR,
+        FDDR_PHY_WR_DATA_SLAVE_RATIO_4_CR,
+        FDDR_PHY_WRLVL_INIT_MODE_CR,
+        FDDR_PHY_WRLVL_INIT_RATIO_1_CR,
+        FDDR_PHY_WRLVL_INIT_RATIO_2_CR,
+        FDDR_PHY_WRLVL_INIT_RATIO_3_CR,
+        FDDR_PHY_WRLVL_INIT_RATIO_4_CR,
+        FDDR_PHY_WR_RD_RL_CR,
+        FDDR_PHY_RDC_FIFO_RST_ERR_CNT_CLR_CR,
+        FDDR_PHY_RDC_WE_TO_RE_DELAY_CR,
+        FDDR_PHY_USE_FIXED_RE_CR,
+        FDDR_PHY_USE_RANK0_DELAYS_CR,
+        FDDR_PHY_USE_LVL_TRNG_LEVEL_CR,
+        FDDR_PHY_DYN_CONFIG_CR,
+        FDDR_PHY_RD_WR_GATE_LVL_CR,
+        FDDR_PHY_DYN_RESET_CR,
+    },
+    
+    /*---------------------------------------------------------------------
+     * FIC-64 registers
+     * These registers are 16-bit wide and 32-bit aligned.
+     */
+    {
+        FDDR_DDR_FIC_NB_ADDR_CR,
+        FDDR_DDR_FIC_NBRWB_SIZE_CR,
+        FDDR_DDR_FIC_WB_TIMEOUT_CR,
+        FDDR_DDR_FIC_HPD_SW_RW_EN_CR,
+        FDDR_DDR_FIC_HPD_SW_RW_INVAL_CR,
+        FDDR_DDR_FIC_SW_WR_ERCLR_CR,
+        FDDR_DDR_FIC_ERR_INT_ENABLE_CR,
+        FDDR_DDR_FIC_NUM_AHB_MASTERS_CR,
+        FDDR_DDR_FIC_LOCK_TIMEOUTVAL_1_CR,
+        FDDR_DDR_FIC_LOCK_TIMEOUTVAL_2_CR,
+        FDDR_DDR_FIC_LOCK_TIMEOUT_EN_CR
+    }
+};
+
+#endif
+
diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers_config/sys_config/sys_config.h b/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers_config/sys_config/sys_config.h
new file mode 100644
index 000000000..2bea18b45
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers_config/sys_config/sys_config.h
@@ -0,0 +1,67 @@
+/*******************************************************************************
+ * (c) Copyright 2012 Microsemi SoC Products Group.  All rights reserved.
+ *
+ *  Smartfusion2 system configuration. This file is automatically generated
+ *  by the Libero tools.
+ *
+ */
+#ifndef MSS_SYSTEM_CONFIGURATION
+#define MSS_SYSTEM_CONFIGURATION
+
+/*==============================================================================
+ * Clock configuration
+ */
+#include "sys_config_mss_clocks.h"
+ 
+/*==============================================================================
+ * Memory remapping configuration
+ */
+/* TBD */
+
+/*==============================================================================
+ * FACC_INIT (Cortex-M3 runs the FACC INIT procedure)
+ * Only set to 1 for design targeting the M2S050T_ES device
+ */
+#define MSS_SYS_FACC_INIT_BY_CORTEX         1
+
+/*==============================================================================
+ * MDDR configuration
+ */
+#define MSS_SYS_MDDR_CONFIG_BY_CORTEX       0
+
+/*==============================================================================
+ * FDDR configuration
+ */
+#define MSS_SYS_FDDR_CONFIG_BY_CORTEX       0
+
+/*==============================================================================
+ * SERDES Interface configuration
+ */
+#define MSS_SYS_SERDES_0_CONFIG_BY_CORTEX   0
+#if MSS_SYS_SERDES_0_CONFIG_BY_CORTEX
+#include "sys_config_SERDESIF_0.h"
+#endif
+
+#define MSS_SYS_SERDES_1_CONFIG_BY_CORTEX   0
+#if MSS_SYS_SERDES_1_CONFIG_BY_CORTEX
+#include "sys_config_SERDESIF_1.h"
+#endif
+
+#define MSS_SYS_SERDES_2_CONFIG_BY_CORTEX   0
+#if MSS_SYS_SERDES_2_CONFIG_BY_CORTEX
+#include "sys_config_SERDESIF_2.h"
+#endif
+
+#define MSS_SYS_SERDES_3_CONFIG_BY_CORTEX   0
+#if MSS_SYS_SERDES_3_CONFIG_BY_CORTEX
+#include "sys_config_SERDESIF_3.h"
+#endif
+
+/*==============================================================================
+ * Cache configuration
+ */
+#define MSS_SYS_CACHE_CONFIG_BY_CORTEX      0
+
+#endif  /* MSS_SYSTEM_CONFIGURATION */
+
+
diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers_config/sys_config/sys_config_mss_clocks.h b/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers_config/sys_config/sys_config_mss_clocks.h
new file mode 100644
index 000000000..2ed3979b4
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/drivers_config/sys_config/sys_config_mss_clocks.h
@@ -0,0 +1,22 @@
+/**************************************************************************
+ * (c) Copyright 2012 Microsemi SoC Products Group.  All rights reserved.
+ *
+ * Smartfusion2 system configuration.
+ *   - Automatically created by Microsemi Libero SoC Sun May 05 13:12:03 2013
+ *
+ * Warning:  Do not modify this file, it may lead to unexpected
+ *           functional failures in your Microcontroller Subsystem.
+ */
+#ifndef SYS_CONFIG_MSS_CLOCKS
+#define SYS_CONFIG_MSS_CLOCKS
+
+#define MSS_SYS_M3_CLK_FREQ             100000000u
+#define MSS_SYS_MDDR_CLK_FREQ           100000000u
+#define MSS_SYS_APB_0_CLK_FREQ          25000000u
+#define MSS_SYS_APB_1_CLK_FREQ          25000000u
+#define MSS_SYS_APB_2_CLK_FREQ          25000000u
+#define MSS_SYS_FIC_0_CLK_FREQ          100000000u
+#define MSS_SYS_FIC_1_CLK_FREQ          100000000u
+#define MSS_SYS_FIC64_CLK_FREQ          100000000u
+
+#endif /* SYS_CONFIG_MSS_CLOCKS */
diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/hal/CortexM3/GNU/cpu_types.h b/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/hal/CortexM3/GNU/cpu_types.h
new file mode 100644
index 000000000..322764ba9
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/hal/CortexM3/GNU/cpu_types.h
@@ -0,0 +1,30 @@
+/*******************************************************************************
+ * (c) Copyright 2007-2013 Microsemi SoC Products Group. All rights reserved.
+ * 
+ * SVN $Revision: 5258 $
+ * SVN $Date: 2013-03-21 12:41:02 +0000 (Thu, 21 Mar 2013) $
+ */
+#ifndef __CPU_TYPES_H
+#define __CPU_TYPES_H   1
+
+#include <stdint.h>
+
+/*------------------------------------------------------------------------------
+ */
+typedef unsigned int size_t;
+
+/*------------------------------------------------------------------------------
+ * addr_t: address type.
+ * Used to specify the address of peripherals present in the processor's memory
+ * map.
+ */
+typedef unsigned int addr_t;
+
+/*------------------------------------------------------------------------------
+ * psr_t: processor state register.
+ * Used by HAL_disable_interrupts() and HAL_restore_interrupts() to store the
+ * processor's state between disabling and restoring interrupts.
+ */
+typedef unsigned int psr_t;
+
+#endif  /* __CPU_TYPES_H */
diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/hal/CortexM3/GNU/hal.s b/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/hal/CortexM3/GNU/hal.s
new file mode 100644
index 000000000..36753b6fd
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/hal/CortexM3/GNU/hal.s
@@ -0,0 +1,31 @@
+#-------------------------------------------------------------------------------
+# (c) Copyright 2007-2013 Microsemi SoC Products Group. All rights reserved.
+# 
+# Interrupt disabling/restoration for critical section protection.
+#
+# SVN $Revision: 5258 $
+# SVN $Date: 2013-03-21 12:41:02 +0000 (Thu, 21 Mar 2013) $
+#
+    .text
+    .global HAL_disable_interrupts
+    .global HAL_restore_interrupts
+    .code 16
+    .syntax unified
+    .type HAL_disable_interrupts, function
+    .type HAL_restore_interrupts, function
+#-------------------------------------------------------------------------------
+# 
+#
+HAL_disable_interrupts:    
+    mrs r0, PRIMASK
+    cpsid I
+    bx lr
+
+#-------------------------------------------------------------------------------
+#
+#
+HAL_restore_interrupts:    
+    msr PRIMASK, r0
+    bx lr
+
+.end
diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/hal/CortexM3/GNU/hw_macros.h b/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/hal/CortexM3/GNU/hw_macros.h
new file mode 100644
index 000000000..2142cb2ed
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/hal/CortexM3/GNU/hw_macros.h
@@ -0,0 +1,96 @@
+/*******************************************************************************
+ * (c) Copyright 2007-2013 Microsemi SoC Products Group. All rights reserved.
+ * 
+ *  Hardware registers access macros.
+ * 
+ *  THE MACROS DEFINED IN THIS FILE ARE DEPRECATED. DO NOT USED FOR NEW 
+ *  DEVELOPMENT.
+ *
+ * These macros are used to access peripheral's registers. They allow access to
+ * 8, 16 and 32 bit wide registers. All accesses to peripheral registers should
+ * be done through these macros in order to ease porting accross different 
+ * processors/bus architectures.
+ * 
+ * Some of these macros also allow to access a specific register field.
+ * 
+ * SVN $Revision: 5258 $
+ * SVN $Date: 2013-03-21 12:41:02 +0000 (Thu, 21 Mar 2013) $
+ */
+#ifndef __HW_REGISTER_MACROS_H
+#define __HW_REGISTER_MACROS_H	1
+
+/*------------------------------------------------------------------------------
+ * 32 bits registers access:
+ */
+#define HW_get_uint32_reg(BASE_ADDR, REG_OFFSET) (*((uint32_t volatile *)(BASE_ADDR + REG_OFFSET##_REG_OFFSET)))
+
+#define HW_set_uint32_reg(BASE_ADDR, REG_OFFSET, VALUE) (*((uint32_t volatile *)(BASE_ADDR + REG_OFFSET##_REG_OFFSET)) = (VALUE))
+
+#define HW_set_uint32_reg_field(BASE_ADDR, FIELD, VALUE) \
+            (*((uint32_t volatile *)(BASE_ADDR + FIELD##_OFFSET)) =  \
+                ( \
+                    (uint32_t) \
+                    ( \
+                    (*((uint32_t volatile *)(BASE_ADDR + FIELD##_OFFSET))) & ~FIELD##_MASK) | \
+                    (uint32_t)(((VALUE) << FIELD##_SHIFT) & FIELD##_MASK) \
+                ) \
+            )
+
+#define HW_get_uint32_reg_field( BASE_ADDR, FIELD ) \
+            (( (*((uint32_t volatile *)(BASE_ADDR + FIELD##_OFFSET))) & FIELD##_MASK) >> FIELD##_SHIFT)
+
+/*------------------------------------------------------------------------------
+ * 32 bits memory access:
+ */
+#define HW_get_uint32(BASE_ADDR) (*((uint32_t volatile *)(BASE_ADDR)))
+
+#define HW_set_uint32(BASE_ADDR, VALUE) (*((uint32_t volatile *)(BASE_ADDR)) = (VALUE))
+
+/*------------------------------------------------------------------------------
+ * 16 bits registers access:
+ */
+#define HW_get_uint16_reg(BASE_ADDR, REG_OFFSET) (*((uint16_t volatile *)(BASE_ADDR + REG_OFFSET##_REG_OFFSET)))
+
+#define HW_set_uint16_reg(BASE_ADDR, REG_OFFSET, VALUE) (*((uint16_t volatile *)(BASE_ADDR + REG_OFFSET##_REG_OFFSET)) = (VALUE))
+
+#define HW_set_uint16_reg_field(BASE_ADDR, FIELD, VALUE) \
+            (*((uint16_t volatile *)(BASE_ADDR + FIELD##_OFFSET)) =  \
+                ( \
+                    (uint16_t) \
+                    ( \
+                    (*((uint16_t volatile *)(BASE_ADDR + FIELD##_OFFSET))) & ~FIELD##_MASK) | \
+                    (uint16_t)(((VALUE) << FIELD##_SHIFT) & FIELD##_MASK) \
+                ) \
+            )
+
+#define HW_get_uint16_reg_field( BASE_ADDR, FIELD ) \
+            (( (*((uint16_t volatile *)(BASE_ADDR + FIELD##_OFFSET))) & FIELD##_MASK) >> FIELD##_SHIFT)
+
+/*------------------------------------------------------------------------------
+ * 8 bits registers access:
+ */
+#define HW_get_uint8_reg(BASE_ADDR, REG_OFFSET) (*((uint8_t volatile *)(BASE_ADDR + REG_OFFSET##_REG_OFFSET)))
+
+#define HW_set_uint8_reg(BASE_ADDR, REG_OFFSET, VALUE) (*((uint8_t volatile *)(BASE_ADDR + REG_OFFSET##_REG_OFFSET)) = (VALUE))
+ 
+#define HW_set_uint8_reg_field(BASE_ADDR, FIELD, VALUE) \
+            (*((uint8_t volatile *)(BASE_ADDR + FIELD##_OFFSET)) =  \
+                ( \
+                    (uint8_t) \
+                    ( \
+                    (*((uint8_t volatile *)(BASE_ADDR + FIELD##_OFFSET))) & ~FIELD##_MASK) | \
+                    (uint8_t)(((VALUE) << FIELD##_SHIFT) & FIELD##_MASK) \
+                ) \
+            )
+
+#define HW_get_uint8_reg_field( BASE_ADDR, FIELD ) \
+            (( (*((uint8_t volatile *)(BASE_ADDR + FIELD##_OFFSET))) & FIELD##_MASK) >> FIELD##_SHIFT)
+
+/*------------------------------------------------------------------------------
+ * 8 bits memory access:
+ */
+#define HW_get_uint8(BASE_ADDR) (*((uint8_t volatile *)(BASE_ADDR)))
+
+#define HW_set_uint8(BASE_ADDR, VALUE) (*((uint8_t volatile *)(BASE_ADDR)) = (VALUE))
+ 
+#endif  /* __HW_REGISTER_MACROS_H */
diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/hal/CortexM3/GNU/hw_reg_access.s b/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/hal/CortexM3/GNU/hw_reg_access.s
new file mode 100644
index 000000000..3a0b25436
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/hal/CortexM3/GNU/hw_reg_access.s
@@ -0,0 +1,165 @@
+/*******************************************************************************
+ * (c) Copyright 2008-2013 Microsemi SoC Products Group. All rights reserved.
+ * 
+ * SVN $Revision: 5258 $
+ * SVN $Date: 2013-03-21 12:41:02 +0000 (Thu, 21 Mar 2013) $
+ */
+
+    .text
+    .global HW_set_32bit_reg
+    .global HW_get_32bit_reg
+    .global HW_set_32bit_reg_field
+    .global HW_get_32bit_reg_field
+    .global HW_set_16bit_reg
+    .global HW_get_16bit_reg
+    .global HW_set_16bit_reg_field
+    .global HW_get_16bit_reg_field
+    .global HW_set_8bit_reg
+    .global HW_get_8bit_reg
+    .global HW_set_8bit_reg_field
+    .global HW_get_8bit_reg_field
+    .code 16
+    .syntax unified
+    .type HW_set_32bit_reg, function
+    .type HW_get_32bit_reg, function
+    .type HW_set_32bit_reg_field, function
+    .type HW_get_32bit_reg_field, function
+    .type HW_set_16bit_reg, function
+    .type HW_get_16bit_reg, function
+    .type HW_set_16bit_reg_field, function
+    .type HW_get_16bit_reg_field, function
+    .type HW_set_8bit_reg, function
+    .type HW_get_8bit_reg, function
+    .type HW_set_8bit_reg_field, function
+    .type HW_get_8bit_reg_field, function
+
+/*------------------------------------------------------------------------------
+ * R0:   addr_t reg_addr
+ * R1:   uint32_t value
+ */
+HW_set_32bit_reg:
+    STR R1, [R0]
+    BX LR
+
+/*------------------------------------------------------------------------------
+ * R0:   addr_t reg_addr
+ */      
+HW_get_32bit_reg:
+    LDR R0, [R0]
+    BX LR
+
+/*------------------------------------------------------------------------------
+ * R0:   addr_t reg_addr
+ * R1:   int_fast8_t shift
+ * R2:   uint32_t mask
+ * R3:   uint32_t value
+ */
+HW_set_32bit_reg_field:
+    PUSH {R1,R2,R3,LR}
+    LSL.W R3, R3, R1
+    AND.W R3, R3, R2
+    LDR R1, [R0]
+    MVN.W R2, R2
+    AND.W R1, R1, R2
+    ORR.W R1, R1, R3
+    STR R1, [R0]
+    POP {R1,R2,R3,PC}
+
+/*------------------------------------------------------------------------------
+ * R0:   addr_t reg_addr
+ * R1:   int_fast8_t shift
+ * R2:   uint32_t mask
+ */
+HW_get_32bit_reg_field:
+    LDR R0, [R0]
+    AND.W R0, R0, R2
+    LSR.W R0, R0, R1
+    BX LR
+
+/*------------------------------------------------------------------------------
+ * R0:   addr_t reg_addr
+ * R1:   uint_fast16_t value
+ */
+HW_set_16bit_reg:
+    STRH R1, [R0]
+    BX LR
+        
+/*------------------------------------------------------------------------------
+ * R0:   addr_t reg_addr
+ */
+HW_get_16bit_reg:
+    LDRH R0, [R0]
+    BX LR
+
+/*------------------------------------------------------------------------------
+ * R0:   addr_t reg_addr
+ * R1:   int_fast8_t shift
+ * R2:   uint_fast16_t mask
+ * R3:   uint_fast16_t value
+ */
+HW_set_16bit_reg_field:
+    PUSH {R1,R2,R3,LR}
+    LSL.W R3, R3, R1
+    AND.W R3, R3, R2
+    LDRH R1, [R0]
+    MVN.W R2, R2
+    AND.W R1, R1, R2
+    ORR.W R1, R1, R3
+    STRH R1, [R0]
+    POP {R1,R2,R3,PC}
+
+/*------------------------------------------------------------------------------
+ * R0:   addr_t reg_addr
+ * R1:   int_fast8_t shift
+ * R2:   uint_fast16_t mask
+ */
+HW_get_16bit_reg_field:
+    LDRH R0, [R0]
+    AND.W R0, R0, R2
+    LSR.W R0, R0, R1
+    BX LR
+
+/*------------------------------------------------------------------------------
+ * R0:   addr_t reg_addr
+ * R1:   uint_fast8_t value
+ */
+HW_set_8bit_reg:
+    STRB R1, [R0]
+    BX LR
+        
+/*------------------------------------------------------------------------------
+ * R0:   addr_t reg_addr
+ */
+HW_get_8bit_reg:
+    LDRB R0, [R0]
+    BX LR
+
+/*------------------------------------------------------------------------------
+ * R0:   addr_t reg_addr,
+ * R1:   int_fast8_t shift
+ * R2:   uint_fast8_t mask
+ * R3:   uint_fast8_t value
+ */
+HW_set_8bit_reg_field:
+    PUSH {R1,R2,R3,LR}
+    LSL.W R3, R3, R1
+    AND.W R3, R3, R2
+    LDRB R1, [R0]
+    MVN.W R2, R2
+    AND.W R1, R1, R2
+    ORR.W R1, R1, R3
+    STRB R1, [R0]
+    POP {R1,R2,R3,PC}
+
+/*------------------------------------------------------------------------------
+ * R0:   addr_t reg_addr
+ * R1:   int_fast8_t shift
+ * R2:   uint_fast8_t mask
+ */
+HW_get_8bit_reg_field:
+    LDRB R0, [R0]
+    AND.W R0, R0, R2
+    LSR.W R0, R0, R1
+    BX LR
+
+.end
diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/hal/CortexM3/cortex_nvic.c b/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/hal/CortexM3/cortex_nvic.c
new file mode 100644
index 000000000..dc7c00f79
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/hal/CortexM3/cortex_nvic.c
@@ -0,0 +1,205 @@
+/*******************************************************************************
+ * (c) Copyright 2007-2013 Microsemi SoC Products Group.  All rights reserved.
+ * 
+ * Legacy Actel HAL Cortex NVIC control functions.
+ * The use of these functions should be replaced by calls to the equivalent
+ * CMSIS function in your application code.
+ *
+ * SVN $Revision: 5259 $
+ * SVN $Date: 2013-03-21 12:58:05 +0000 (Thu, 21 Mar 2013) $
+ */
+#include "cortex_nvic.h"
+#include "../../CMSIS/mss_assert.h"
+
+
+/***************************************************************************//**
+ * 
+ */
+void NVIC_init( void )
+{
+    /*
+     * Please use the NVIC control functions provided by the SmartFusion2 CMSIS
+     * Hardware Abstraction Layer. The use of the Actel HAL NVIC control
+     * functions is obsolete on SmartFusion2 devices.
+     *
+     * Simply remove the call to NVIC_init() from your application code.
+     */
+    ASSERT(0);
+}
+
+/***************************************************************************//**
+ * 
+ */
+void NVIC_set_handler
+(
+    uint32_t interrupt_number,
+    hal_nvic_irq_handler_t handler
+)
+{
+    /*
+     * Please use the NVIC control functions provided by the SmartFusion2 CMSIS
+     * Hardware Abstraction Layer. The use of the Actel HAL NVIC control
+     * functions is obsolete on SmartFusion2 devices.
+     *
+     * Please remove the call to NVIC_set_handler() from your application code
+     * and provide a function using one of the following function prototypes to
+     * handle interrupts from peripherals implemeted in the SmartFusion2 FPGA
+     * fabric:
+     *      - void FabricIrq0_IRQHandler(void)
+     *      - void FabricIrq1_IRQHandler(void)
+     *      - void FabricIrq2_IRQHandler(void)
+     *      - void FabricIrq3_IRQHandler(void)
+     *      - void FabricIrq4_IRQHandler(void)
+     *      - void FabricIrq5_IRQHandler(void)
+     *      - void FabricIrq6_IRQHandler(void)
+     *      - void FabricIrq7_IRQHandler(void)
+     *      - void FabricIrq8_IRQHandler(void)
+     *      - void FabricIrq9_IRQHandler(void)
+     *      - void FabricIrq10_IRQHandler(void)
+     *      - void FabricIrq11_IRQHandler(void)
+     *      - void FabricIrq12_IRQHandler(void)
+     *      - void FabricIrq13_IRQHandler(void)
+     *      - void FabricIrq14_IRQHandler(void)
+     *      - void FabricIrq15_IRQHandler(void)
+     * The function to implement depends on which MSS_INT_F2M[n] signal is used
+     * in your Libero design to connect the interrupt signal of the peripheral
+     * generating the interrupt.
+     */
+    ASSERT(0);
+}
+
+/***************************************************************************//**
+ * 
+ */
+void NVIC_set_priority
+(
+    uint32_t interrupt_number,
+    uint8_t priority_level
+)
+{
+    /*
+     * Please use the NVIC control functions provided by the SmartFusion2 CMSIS
+     * Hardware Abstraction Layer. The use of the Actel HAL NVIC control
+     * functions is obsolete on SmartFusion2 devices.
+     *
+     * Please replace calls to NVIC_set_priority() with a call to the CMSIS
+     * void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) function where
+     * IRQn is one of the following values:
+     *      - FabricIrq0_IRQn
+     *      - FabricIrq1_IRQn
+     *      - FabricIrq2_IRQn
+     *      - FabricIrq3_IRQn
+     *      - FabricIrq4_IRQn
+     *      - FabricIrq5_IRQn
+     *      - FabricIrq6_IRQn
+     *      - FabricIrq7_IRQn
+     *      - FabricIrq8_IRQn
+     *      - FabricIrq9_IRQn
+     *      - FabricIrq10_IRQn
+     *      - FabricIrq11_IRQn
+     *      - FabricIrq12_IRQn
+     *      - FabricIrq13_IRQn
+     *      - FabricIrq14_IRQn
+     *      - FabricIrq15_IRQn
+     */
+    ASSERT(0);
+}
+
+/***************************************************************************//**
+ * 
+ */
+void NVIC_enable_interrupt( uint32_t interrupt_number )
+{
+    /*
+     * Please use the NVIC control functions provided by the SmartFusion2 CMSIS
+     * Hardware Abstraction Layer. The use of the Actel HAL NVIC control
+     * functions is obsolete on SmartFusion2 devices.
+     *
+     * Please replace calls to NVIC_enable_interrupt() with a call to the CMSIS
+     * void NVIC_EnableIRQ(IRQn_Type IRQn) function where IRQn is one of the
+     * following values:
+     *      - FabricIrq0_IRQn
+     *      - FabricIrq1_IRQn
+     *      - FabricIrq2_IRQn
+     *      - FabricIrq3_IRQn
+     *      - FabricIrq4_IRQn
+     *      - FabricIrq5_IRQn
+     *      - FabricIrq6_IRQn
+     *      - FabricIrq7_IRQn
+     *      - FabricIrq8_IRQn
+     *      - FabricIrq9_IRQn
+     *      - FabricIrq10_IRQn
+     *      - FabricIrq11_IRQn
+     *      - FabricIrq12_IRQn
+     *      - FabricIrq13_IRQn
+     *      - FabricIrq14_IRQn
+     *      - FabricIrq15_IRQn
+     */
+    ASSERT(0);
+}
+
+/***************************************************************************//**
+ * 
+ */
+void NVIC_disable_interrupt( uint32_t interrupt_number )
+{
+    /*
+     * Please use the NVIC control functions provided by the SmartFusion2 CMSIS
+     * Hardware Abstraction Layer. The use of the Actel HAL NVIC control
+     * functions is obsolete on SmartFusion2 devices.
+     *
+     * Please replace calls to NVIC_disable_interrupt() with a call to the CMSIS
+     * void NVIC_DisableIRQ(IRQn_Type IRQn) function where IRQn is one of the
+     * following values:
+     *      - FabricIrq0_IRQn
+     *      - FabricIrq1_IRQn
+     *      - FabricIrq2_IRQn
+     *      - FabricIrq3_IRQn
+     *      - FabricIrq4_IRQn
+     *      - FabricIrq5_IRQn
+     *      - FabricIrq6_IRQn
+     *      - FabricIrq7_IRQn
+     *      - FabricIrq8_IRQn
+     *      - FabricIrq9_IRQn
+     *      - FabricIrq10_IRQn
+     *      - FabricIrq11_IRQn
+     *      - FabricIrq12_IRQn
+     *      - FabricIrq13_IRQn
+     *      - FabricIrq14_IRQn
+     *      - FabricIrq15_IRQn
+     */
+    ASSERT(0);
+}
+
+/***************************************************************************//**
+ * 
+ */
+void NVIC_clear_interrupt( uint32_t interrupt_number )
+{
+    /*
+     * Please use the NVIC control functions provided by the SmartFusion2 CMSIS
+     * Hardware Abstraction Layer. The use of the Actel HAL NVIC control
+     * functions is obsolete on SmartFusion2 devices.
+     *
+     * Please replace calls to NVIC_clear_interrupt() with a call to the CMSIS
+     * void NVIC_ClearPendingIRQ(IRQn_Type IRQn) function where IRQn is one of the
+     * following values:
+     *      - FabricIrq0_IRQn
+     *      - FabricIrq1_IRQn
+     *      - FabricIrq2_IRQn
+     *      - FabricIrq3_IRQn
+     *      - FabricIrq4_IRQn
+     *      - FabricIrq5_IRQn
+     *      - FabricIrq6_IRQn
+     *      - FabricIrq7_IRQn
+     *      - FabricIrq8_IRQn
+     *      - FabricIrq9_IRQn
+     *      - FabricIrq10_IRQn
+     *      - FabricIrq11_IRQn
+     *      - FabricIrq12_IRQn
+     *      - FabricIrq13_IRQn
+     *      - FabricIrq14_IRQn
+     *      - FabricIrq15_IRQn
+     */
+    ASSERT(0);
+}
diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/hal/CortexM3/cortex_nvic.h b/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/hal/CortexM3/cortex_nvic.h
new file mode 100644
index 000000000..1c5b948e9
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/hal/CortexM3/cortex_nvic.h
@@ -0,0 +1,56 @@
+/*******************************************************************************
+ * (c) Copyright 2007-2013 Microsemi SoC Products Group.  All rights reserved.
+ * 
+ * Legacy Actel HAL Cortex NVIC control functions.
+ * The use of these functions should be replaced by calls to the equivalent
+ * CMSIS function in your application code.
+ *
+ * SVN $Revision: 5257 $
+ * SVN $Date: 2013-03-21 12:24:10 +0000 (Thu, 21 Mar 2013) $
+ */
+#ifndef CORTEX_NVIC_H_
+#define CORTEX_NVIC_H_
+
+#include <stdint.h>
+
+typedef void (*hal_nvic_irq_handler_t)(void);
+
+/*------------------------------------------------------------------------------
+ * 
+ */
+void NVIC_init( void );
+
+/*------------------------------------------------------------------------------
+ * 
+ */
+void NVIC_set_handler
+(
+    uint32_t interrupt_number,
+    hal_nvic_irq_handler_t handler
+);
+
+/*------------------------------------------------------------------------------
+ * 
+ */
+void NVIC_set_priority
+(
+    uint32_t interrupt_number,
+    uint8_t priority_level
+);
+
+/*------------------------------------------------------------------------------
+ * 
+ */
+void NVIC_enable_interrupt( uint32_t interrupt_number );
+
+/*------------------------------------------------------------------------------
+ * 
+ */
+void NVIC_disable_interrupt( uint32_t interrupt_number );
+
+/*------------------------------------------------------------------------------
+ * 
+ */
+void NVIC_clear_interrupt( uint32_t interrupt_number );
+
+#endif /*CORTEX_NVIC_H_*/
diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/hal/hal.h b/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/hal/hal.h
new file mode 100644
index 000000000..4722d1507
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/hal/hal.h
@@ -0,0 +1,206 @@
+/***************************************************************************//**
+ * (c) Copyright 2007-2013 Microsemi SoC Products Group. All rights reserved.
+ * 
+ * Hardware abstraction layer functions.
+ * 
+ * SVN $Revision: 5258 $
+ * SVN $Date: 2013-03-21 12:41:02 +0000 (Thu, 21 Mar 2013) $
+ */
+#ifndef HAL_H_
+#define HAL_H_
+
+#include "cpu_types.h"
+#include "hw_reg_access.h"
+
+/***************************************************************************//**
+ * Enable all interrupts at the processor level.
+ */
+void HAL_enable_interrupts( void );
+
+/***************************************************************************//**
+ * Disable all interrupts at the processor core level.
+ * Return the interrupts enable state before disabling occured so that it can 
+ * later be restored. 
+ */
+psr_t HAL_disable_interrupts( void );
+
+/***************************************************************************//**
+ * Restore the interrupts enable state at the processor core level.
+ * This function is normally passed the value returned from a previous call to
+ * HAL_disable_interrupts(). 
+ */
+void HAL_restore_interrupts( psr_t saved_psr );
+
+/***************************************************************************//**
+ */
+#define FIELD_OFFSET(FIELD_NAME)  (FIELD_NAME##_OFFSET)
+#define FIELD_SHIFT(FIELD_NAME)   (FIELD_NAME##_SHIFT)
+#define FIELD_MASK(FIELD_NAME)    (FIELD_NAME##_MASK)
+
+/***************************************************************************//**
+ * The macro HAL_set_32bit_reg() allows writing a 32 bits wide register.
+ *
+ * BASE_ADDR:   A variable of type addr_t specifying the base address of the
+ *              peripheral containing the register.
+ * REG_NAME:    A string identifying the register to write. These strings are
+ *              specified in a header file associated with the peripheral.
+ * VALUE:       A variable of type uint32_t containing the value to write.
+ */
+#define HAL_set_32bit_reg(BASE_ADDR, REG_NAME, VALUE) \
+          (HW_set_32bit_reg( ((BASE_ADDR) + (REG_NAME##_REG_OFFSET)), (VALUE) ))
+
+/***************************************************************************//**
+ * The macro HAL_get_32bit_reg() is used to read the value  of a 32 bits wide
+ * register.
+ * 
+ * BASE_ADDR:   A variable of type addr_t specifying the base address of the
+ *              peripheral containing the register.
+ * REG_NAME:    A string identifying the register to read. These strings are
+ *              specified in a header file associated with the peripheral.
+ * RETURN:		This function-like macro returns a uint32_t value.
+ */
+#define HAL_get_32bit_reg(BASE_ADDR, REG_NAME) \
+          (HW_get_32bit_reg( ((BASE_ADDR) + (REG_NAME##_REG_OFFSET)) ))
+
+/***************************************************************************//**
+ * The macro HAL_set_32bit_reg_field() is used to write a field within a
+ * 32 bits wide register. The field written can be one or more bits.
+ * 
+ * BASE_ADDR:   A variable of type addr_t specifying the base address of the
+ *              peripheral containing the register.
+ * FIELD_NAME:  A string identifying the register field to write. These strings
+ * 				are specified in a header file associated with the peripheral.
+ * VALUE:       A variable of type uint32_t containing the field value to write.
+ */
+#define HAL_set_32bit_reg_field(BASE_ADDR, FIELD_NAME, VALUE) \
+            (HW_set_32bit_reg_field(\
+                (BASE_ADDR) + FIELD_OFFSET(FIELD_NAME),\
+                FIELD_SHIFT(FIELD_NAME),\
+                FIELD_MASK(FIELD_NAME),\
+                (VALUE)))
+  
+/***************************************************************************//**
+ * The macro HAL_get_32bit_reg_field() is used to read a register field from
+ * within a 32 bit wide peripheral register. The field can be one or more bits.
+ * 
+ * BASE_ADDR:   A variable of type addr_t specifying the base address of the
+ *              peripheral containing the register.
+ * FIELD_NAME:  A string identifying the register field to write. These strings
+ * 				are specified in a header file associated with the peripheral.
+ * RETURN:		This function-like macro returns a uint32_t value.
+ */
+#define HAL_get_32bit_reg_field(BASE_ADDR, FIELD_NAME) \
+            (HW_get_32bit_reg_field(\
+                (BASE_ADDR) + FIELD_OFFSET(FIELD_NAME),\
+                FIELD_SHIFT(FIELD_NAME),\
+                FIELD_MASK(FIELD_NAME)))
+  
+/***************************************************************************//**
+ * The macro HAL_set_16bit_reg() allows writing a 16 bits wide register.
+ *
+ * BASE_ADDR:   A variable of type addr_t specifying the base address of the
+ *              peripheral containing the register.
+ * REG_NAME:    A string identifying the register to write. These strings are
+ *              specified in a header file associated with the peripheral.
+ * VALUE:       A variable of type uint_fast16_t containing the value to write.
+ */
+#define HAL_set_16bit_reg(BASE_ADDR, REG_NAME, VALUE) \
+            (HW_set_16bit_reg( ((BASE_ADDR) + (REG_NAME##_REG_OFFSET)), (VALUE) ))
+
+/***************************************************************************//**
+ * The macro HAL_get_16bit_reg() is used to read the value  of a 16 bits wide
+ * register.
+ * 
+ * BASE_ADDR:   A variable of type addr_t specifying the base address of the
+ *              peripheral containing the register.
+ * REG_NAME:    A string identifying the register to read. These strings are
+ *              specified in a header file associated with the peripheral.
+ * RETURN:		This function-like macro returns a uint16_t value.
+ */
+#define HAL_get_16bit_reg(BASE_ADDR, REG_NAME) \
+            (HW_get_16bit_reg( (BASE_ADDR) + (REG_NAME##_REG_OFFSET) ))
+
+/***************************************************************************//**
+ * The macro HAL_set_16bit_reg_field() is used to write a field within a
+ * 16 bits wide register. The field written can be one or more bits.
+ * 
+ * BASE_ADDR:   A variable of type addr_t specifying the base address of the
+ *              peripheral containing the register.
+ * FIELD_NAME:  A string identifying the register field to write. These strings
+ * 				are specified in a header file associated with the peripheral.
+ * VALUE:       A variable of type uint16_t containing the field value to write.
+ */
+#define HAL_set_16bit_reg_field(BASE_ADDR, FIELD_NAME, VALUE) \
+            (HW_set_16bit_reg_field(\
+                (BASE_ADDR) + FIELD_OFFSET(FIELD_NAME),\
+                FIELD_SHIFT(FIELD_NAME),\
+                FIELD_MASK(FIELD_NAME),\
+                (VALUE)))  
+
+/***************************************************************************//**
+ * The macro HAL_get_16bit_reg_field() is used to read a register field from
+ * within a 8 bit wide peripheral register. The field can be one or more bits.
+ * 
+ * BASE_ADDR:   A variable of type addr_t specifying the base address of the
+ *              peripheral containing the register.
+ * FIELD_NAME:  A string identifying the register field to write. These strings
+ * 				are specified in a header file associated with the peripheral.
+ * RETURN:		This function-like macro returns a uint16_t value.
+ */
+#define HAL_get_16bit_reg_field(BASE_ADDR, FIELD_NAME) \
+            (HW_get_16bit_reg_field(\
+                (BASE_ADDR) + FIELD_OFFSET(FIELD_NAME),\
+                FIELD_SHIFT(FIELD_NAME),\
+                FIELD_MASK(FIELD_NAME)))
+
+/***************************************************************************//**
+ * The macro HAL_set_8bit_reg() allows writing a 8 bits wide register.
+ *
+ * BASE_ADDR:   A variable of type addr_t specifying the base address of the
+ *              peripheral containing the register.
+ * REG_NAME:    A string identifying the register to write. These strings are
+ *              specified in a header file associated with the peripheral.
+ * VALUE:       A variable of type uint_fast8_t containing the value to write.
+ */
+#define HAL_set_8bit_reg(BASE_ADDR, REG_NAME, VALUE) \
+          (HW_set_8bit_reg( ((BASE_ADDR) + (REG_NAME##_REG_OFFSET)), (VALUE) ))
+
+/***************************************************************************//**
+ * The macro HAL_get_8bit_reg() is used to read the value of a 8 bits wide
+ * register.
+ * 
+ * BASE_ADDR:   A variable of type addr_t specifying the base address of the
+ *              peripheral containing the register.
+ * REG_NAME:    A string identifying the register to read. These strings are
+ *              specified in a header file associated with the peripheral.
+ * RETURN:		This function-like macro returns a uint8_t value.
+ */
+#define HAL_get_8bit_reg(BASE_ADDR, REG_NAME) \
+          (HW_get_8bit_reg( (BASE_ADDR) + (REG_NAME##_REG_OFFSET) ))
+
+/***************************************************************************//**
+ */
+#define HAL_set_8bit_reg_field(BASE_ADDR, FIELD_NAME, VALUE) \
+            (HW_set_8bit_reg_field(\
+                (BASE_ADDR) + FIELD_OFFSET(FIELD_NAME),\
+                FIELD_SHIFT(FIELD_NAME),\
+                FIELD_MASK(FIELD_NAME),\
+                (VALUE)))
+
+/***************************************************************************//**
+ * The macro HAL_get_8bit_reg_field() is used to read a register field from
+ * within a 8 bit wide peripheral register. The field can be one or more bits.
+ * 
+ * BASE_ADDR:   A variable of type addr_t specifying the base address of the
+ *              peripheral containing the register.
+ * FIELD_NAME:  A string identifying the register field to write. These strings
+ * 				are specified in a header file associated with the peripheral.
+ * RETURN:		This function-like macro returns a uint8_t value.
+ */
+#define HAL_get_8bit_reg_field(BASE_ADDR, FIELD_NAME) \
+            (HW_get_8bit_reg_field(\
+                (BASE_ADDR) + FIELD_OFFSET(FIELD_NAME),\
+                FIELD_SHIFT(FIELD_NAME),\
+                FIELD_MASK(FIELD_NAME)))
+  
+#endif /*HAL_H_*/
diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/hal/hal_assert.h b/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/hal/hal_assert.h
new file mode 100644
index 000000000..f669dc940
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/hal/hal_assert.h
@@ -0,0 +1,30 @@
+/*******************************************************************************
+ * (c) Copyright 2008-2013 Microsemi SoC Products Group. All rights reserved.
+ * 
+ * SVN $Revision: 5274 $
+ * SVN $Date: 2013-03-22 13:18:44 +0000 (Fri, 22 Mar 2013) $
+ */
+#ifndef HAL_ASSERT_HEADER
+#define HAL_ASSERT_HEADER
+
+#include "../CMSIS/mss_assert.h"
+
+#if defined(NDEBUG)
+/***************************************************************************//**
+ * HAL_ASSERT() is defined out when the NDEBUG symbol is used.
+ ******************************************************************************/
+#define HAL_ASSERT(CHECK)
+
+#else
+/***************************************************************************//**
+ * Default behaviour for HAL_ASSERT() macro:
+ *------------------------------------------------------------------------------
+ * Using the HAL_ASSERT() macro is the same as directly using the SmartFusion2
+ * CMSIS ASSERT() macro. The behaviour is toolchain specific and project
+ * setting specific.
+ ******************************************************************************/
+#define HAL_ASSERT(CHECK)     ASSERT(CHECK);
+
+#endif  /* NDEBUG */
+
+#endif  /* HAL_ASSERT_HEADER */
diff --git a/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/hal/hw_reg_access.h b/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/hal/hw_reg_access.h
new file mode 100644
index 000000000..8719ffe9b
--- /dev/null
+++ b/FreeRTOS/Demo/CORTEX_M2S050_Starter_Kit_SoftConsole/RTOSDemo_Hardware_Platform/hal/hw_reg_access.h
@@ -0,0 +1,227 @@
+/***************************************************************************//**
+ * (c) Copyright 2007-2013 Microsemi SoC Products Group. All rights reserved.
+ * 
+ * Hardware registers access functions.
+ * The implementation of these function is platform and toolchain specific.
+ * The functions declared here are implemented using assembler as part of the 
+ * processor/toolchain specific HAL.
+ * 
+ * SVN $Revision: 5258 $
+ * SVN $Date: 2013-03-21 12:41:02 +0000 (Thu, 21 Mar 2013) $
+ */
+#ifndef HW_REG_ACCESS
+#define HW_REG_ACCESS
+
+/***************************************************************************//**
+ * HW_set_32bit_reg is used to write the content of a 32 bits wide peripheral
+ * register.
+ * 
+ * @param reg_addr  Address in the processor's memory map of the register to
+ *                  write.
+ * @param value     Value to be written into the peripheral register.
+ */
+void
+HW_set_32bit_reg
+(
+	addr_t reg_addr,
+	uint32_t value
+);
+
+/***************************************************************************//**
+ * HW_get_32bit_reg is used to read the content of a 32 bits wide peripheral
+ * register.
+ * 
+ * @param reg_addr  Address in the processor's memory map of the register to
+ *                  read.
+ * @return          32 bits value read from the peripheral register.
+ */
+uint32_t
+HW_get_32bit_reg
+(
+	addr_t reg_addr
+);
+
+/***************************************************************************//**
+ * HW_set_32bit_reg_field is used to set the content of a field in a 32 bits 
+ * wide peripheral register.
+ * 
+ * @param reg_addr  Address in the processor's memory map of the register to
+ *                  be written.
+ * @param shift     Bit offset of the register field to be read within the 
+ *                  register.
+ * @param mask      Bit mask to be applied to the raw register value to filter
+ *                  out the other register fields values.
+ * @param value     Value to be written in the specified field.
+ */
+void
+HW_set_32bit_reg_field
+(
+    addr_t reg_addr,
+    int_fast8_t shift,
+    uint32_t mask,
+    uint32_t value
+);
+
+/***************************************************************************//**
+ * HW_get_32bit_reg_field is used to read the content of a field out of a 
+ * 32 bits wide peripheral register.
+ * 
+ * @param reg_addr  Address in the processor's memory map of the register to
+ *                  read.
+ * @param shift     Bit offset of the register field to be written within the 
+ *                  register.
+ * @param mask      Bit mask to be applied to the raw register value to filter
+ *                  out the other register fields values.
+ *
+ * @return          32 bits value containing the register field value specified
+ *                  as parameter.
+ */
+uint32_t 
+HW_get_32bit_reg_field
+(
+    addr_t reg_addr,
+    int_fast8_t shift,
+    uint32_t mask
+);
+
+/***************************************************************************//**
+ * HW_set_16bit_reg is used to write the content of a 16 bits wide peripheral
+ * register.
+ * 
+ * @param reg_addr  Address in the processor's memory map of the register to
+ *                  write.
+ * @param value     Value to be written into the peripheral register.
+ */
+void
+HW_set_16bit_reg
+(
+	addr_t reg_addr,
+	uint_fast16_t value
+);
+
+/***************************************************************************//**
+ * HW_get_16bit_reg is used to read the content of a 16 bits wide peripheral
+ * register.
+ * 
+ * @param reg_addr  Address in the processor's memory map of the register to
+ *                  read.
+ * @return          16 bits value read from the peripheral register.
+ */
+uint16_t
+HW_get_16bit_reg
+(
+	addr_t reg_addr
+);
+
+/***************************************************************************//**
+ * HW_set_16bit_reg_field is used to set the content of a field in a 16 bits 
+ * wide peripheral register.
+ * 
+ * @param reg_addr  Address in the processor's memory map of the register to
+ *                  be written.
+ * @param shift     Bit offset of the register field to be read within the 
+ *                  register.
+ * @param mask      Bit mask to be applied to the raw register value to filter
+ *                  out the other register fields values.
+ * @param value     Value to be written in the specified field.
+ */
+void HW_set_16bit_reg_field
+(
+    addr_t reg_addr,
+    int_fast8_t shift,
+    uint_fast16_t mask,
+    uint_fast16_t value
+);
+
+/***************************************************************************//**
+ * HW_get_16bit_reg_field is used to read the content of a field from a 
+ * 16 bits wide peripheral register.
+ * 
+ * @param reg_addr  Address in the processor's memory map of the register to
+ *                  read.
+ * @param shift     Bit offset of the register field to be written within the 
+ *                  register.
+ * @param mask      Bit mask to be applied to the raw register value to filter
+ *                  out the other register fields values.
+ *
+ * @return          16 bits value containing the register field value specified
+ *                  as parameter.
+ */
+uint16_t HW_get_16bit_reg_field
+(
+    addr_t reg_addr,
+    int_fast8_t shift,
+    uint_fast16_t mask
+);
+
+/***************************************************************************//**
+ * HW_set_8bit_reg is used to write the content of a 8 bits wide peripheral
+ * register.
+ * 
+ * @param reg_addr  Address in the processor's memory map of the register to
+ *                  write.
+ * @param value     Value to be written into the peripheral register.
+ */
+void
+HW_set_8bit_reg
+(
+	addr_t reg_addr,
+	uint_fast8_t value
+);
+
+/***************************************************************************//**
+ * HW_get_8bit_reg is used to read the content of a 8 bits wide peripheral
+ * register.
+ * 
+ * @param reg_addr  Address in the processor's memory map of the register to
+ *                  read.
+ * @return          8 bits value read from the peripheral register.
+ */
+uint8_t
+HW_get_8bit_reg
+(
+    addr_t reg_addr
+);
+
+/***************************************************************************//**
+ * HW_set_8bit_reg_field is used to set the content of a field in a 8 bits 
+ * wide peripheral register.
+ * 
+ * @param reg_addr  Address in the processor's memory map of the register to
+ *                  be written.
+ * @param shift     Bit offset of the register field to be read within the 
+ *                  register.
+ * @param mask      Bit mask to be applied to the raw register value to filter
+ *                  out the other register fields values.
+ * @param value     Value to be written in the specified field.
+ */
+void HW_set_8bit_reg_field
+(
+    addr_t reg_addr,
+    int_fast8_t shift,
+    uint_fast8_t mask,
+    uint_fast8_t value
+);
+
+/***************************************************************************//**
+ * HW_get_8bit_reg_field is used to read the content of a field from a 
+ * 8 bits wide peripheral register.
+ * 
+ * @param reg_addr  Address in the processor's memory map of the register to
+ *                  read.
+ * @param shift     Bit offset of the register field to be written within the 
+ *                  register.
+ * @param mask      Bit mask to be applied to the raw register value to filter
+ *                  out the other register fields values.
+ *
+ * @return          16 bits value containing the register field value specified
+ *                  as parameter.
+ */
+uint8_t HW_get_8bit_reg_field
+(
+    addr_t reg_addr,
+    int_fast8_t shift,
+    uint_fast8_t mask
+);
+
+#endif /* HW_REG_ACCESS */