mirror of
https://github.com/FreeRTOS/FreeRTOS-Kernel.git
synced 2025-08-11 13:54:16 -04:00
Add STM32L Discovery board project as a starting point to adapt to an RTOS demo.
This commit is contained in:
Richard Barry
parent
417c3d1054
commit
b89fd7c1e3
139 changed files with 71905 additions and 0 deletions
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;/******************** (C) COPYRIGHT 2012 STMicroelectronics ********************
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;* File Name : startup_stm32l1xx_md.s
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;* Author : MCD Application Team
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;* Version : V1.1.1
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;* Date : 09-March-2012
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;* Description : STM32L1xx Ultra Low Power Medium-density Devices vector
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;* table for EWARM toolchain.
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;* This module performs:
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;* - Set the initial SP
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;* - Set the initial PC == __iar_program_start,
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;* - Set the vector table entries with the exceptions ISR
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;* address.
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;* After Reset the Cortex-M3 processor is in Thread mode,
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;* priority is Privileged, and the Stack is set to Main.
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;********************************************************************************
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;*
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;* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
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;* You may not use this file except in compliance with the License.
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;* You may obtain a copy of the License at:
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;*
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;* http://www.st.com/software_license_agreement_liberty_v2
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;*
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;* Unless required by applicable law or agreed to in writing, software
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;* distributed under the License is distributed on an "AS IS" BASIS,
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;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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;* See the License for the specific language governing permissions and
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;* limitations under the License.
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;*
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;*******************************************************************************/
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;
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;
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; The modules in this file are included in the libraries, and may be replaced
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; by any user-defined modules that define the PUBLIC symbol _program_start or
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; a user defined start symbol.
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; To override the cstartup defined in the library, simply add your modified
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; version to the workbench project.
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;
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; The vector table is normally located at address 0.
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; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
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; The name "__vector_table" has special meaning for C-SPY:
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; it is where the SP start value is found, and the NVIC vector
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; table register (VTOR) is initialized to this address if != 0.
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;
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; Cortex-M version
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;
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MODULE ?cstartup
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;; Forward declaration of sections.
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SECTION CSTACK:DATA:NOROOT(3)
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SECTION .intvec:CODE:NOROOT(2)
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EXTERN __iar_program_start
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EXTERN SystemInit
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PUBLIC __vector_table
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DATA
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__vector_table
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DCD sfe(CSTACK)
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DCD Reset_Handler ; Reset Handler
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DCD NMI_Handler ; NMI Handler
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DCD HardFault_Handler ; Hard Fault Handler
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DCD MemManage_Handler ; MPU Fault Handler
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DCD BusFault_Handler ; Bus Fault Handler
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DCD UsageFault_Handler ; Usage Fault Handler
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD 0 ; Reserved
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DCD SVC_Handler ; SVCall Handler
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DCD DebugMon_Handler ; Debug Monitor Handler
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DCD 0 ; Reserved
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DCD PendSV_Handler ; PendSV Handler
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DCD SysTick_Handler ; SysTick Handler
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; External Interrupts
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DCD WWDG_IRQHandler ; Window Watchdog
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DCD PVD_IRQHandler ; PVD through EXTI Line detect
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DCD TAMPER_STAMP_IRQHandler ; Tamper and Time Stamp
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DCD RTC_WKUP_IRQHandler ; RTC Wakeup
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DCD FLASH_IRQHandler ; FLASH
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DCD RCC_IRQHandler ; RCC
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DCD EXTI0_IRQHandler ; EXTI Line 0
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DCD EXTI1_IRQHandler ; EXTI Line 1
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DCD EXTI2_IRQHandler ; EXTI Line 2
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DCD EXTI3_IRQHandler ; EXTI Line 3
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DCD EXTI4_IRQHandler ; EXTI Line 4
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DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
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DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
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DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
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DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
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DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
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DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
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DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
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DCD ADC1_IRQHandler ; ADC1
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DCD USB_HP_IRQHandler ; USB High Priority
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DCD USB_LP_IRQHandler ; USB Low Priority
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DCD DAC_IRQHandler ; DAC
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DCD COMP_IRQHandler ; COMP through EXTI Line
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DCD EXTI9_5_IRQHandler ; EXTI Line 9..5
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DCD LCD_IRQHandler ; LCD
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DCD TIM9_IRQHandler ; TIM9
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DCD TIM10_IRQHandler ; TIM10
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DCD TIM11_IRQHandler ; TIM11
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DCD TIM2_IRQHandler ; TIM2
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DCD TIM3_IRQHandler ; TIM3
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DCD TIM4_IRQHandler ; TIM4
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DCD I2C1_EV_IRQHandler ; I2C1 Event
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DCD I2C1_ER_IRQHandler ; I2C1 Error
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DCD I2C2_EV_IRQHandler ; I2C2 Event
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DCD I2C2_ER_IRQHandler ; I2C2 Error
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DCD SPI1_IRQHandler ; SPI1
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DCD SPI2_IRQHandler ; SPI2
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DCD USART1_IRQHandler ; USART1
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DCD USART2_IRQHandler ; USART2
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DCD USART3_IRQHandler ; USART3
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DCD EXTI15_10_IRQHandler ; EXTI Line 15..10
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DCD RTC_Alarm_IRQHandler ; RTC Alarm through EXTI Line
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DCD USB_FS_WKUP_IRQHandler ; USB FS Wakeup from suspend
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DCD TIM6_IRQHandler ; TIM6
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DCD TIM7_IRQHandler ; TIM7
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;
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;; Default interrupt handlers.
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;;
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THUMB
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PUBWEAK Reset_Handler
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SECTION .text:CODE:REORDER(2)
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Reset_Handler
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LDR R0, =SystemInit
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BLX R0
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LDR R0, =__iar_program_start
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BX R0
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PUBWEAK NMI_Handler
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SECTION .text:CODE:REORDER(1)
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NMI_Handler
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B NMI_Handler
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PUBWEAK HardFault_Handler
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SECTION .text:CODE:REORDER(1)
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HardFault_Handler
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B HardFault_Handler
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PUBWEAK MemManage_Handler
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SECTION .text:CODE:REORDER(1)
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MemManage_Handler
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B MemManage_Handler
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PUBWEAK BusFault_Handler
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SECTION .text:CODE:REORDER(1)
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BusFault_Handler
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B BusFault_Handler
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PUBWEAK UsageFault_Handler
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SECTION .text:CODE:REORDER(1)
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UsageFault_Handler
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B UsageFault_Handler
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PUBWEAK SVC_Handler
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SECTION .text:CODE:REORDER(1)
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SVC_Handler
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B SVC_Handler
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PUBWEAK DebugMon_Handler
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SECTION .text:CODE:REORDER(1)
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DebugMon_Handler
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B DebugMon_Handler
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PUBWEAK PendSV_Handler
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SECTION .text:CODE:REORDER(1)
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PendSV_Handler
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B PendSV_Handler
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PUBWEAK SysTick_Handler
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SECTION .text:CODE:REORDER(1)
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SysTick_Handler
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B SysTick_Handler
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PUBWEAK WWDG_IRQHandler
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SECTION .text:CODE:REORDER(1)
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WWDG_IRQHandler
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B WWDG_IRQHandler
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PUBWEAK PVD_IRQHandler
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SECTION .text:CODE:REORDER(1)
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PVD_IRQHandler
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B PVD_IRQHandler
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PUBWEAK TAMPER_STAMP_IRQHandler
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SECTION .text:CODE:REORDER(1)
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TAMPER_STAMP_IRQHandler
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B TAMPER_STAMP_IRQHandler
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PUBWEAK RTC_WKUP_IRQHandler
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SECTION .text:CODE:REORDER(1)
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RTC_WKUP_IRQHandler
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B RTC_WKUP_IRQHandler
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PUBWEAK FLASH_IRQHandler
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SECTION .text:CODE:REORDER(1)
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FLASH_IRQHandler
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B FLASH_IRQHandler
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PUBWEAK RCC_IRQHandler
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SECTION .text:CODE:REORDER(1)
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RCC_IRQHandler
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B RCC_IRQHandler
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PUBWEAK EXTI0_IRQHandler
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SECTION .text:CODE:REORDER(1)
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EXTI0_IRQHandler
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B EXTI0_IRQHandler
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PUBWEAK EXTI1_IRQHandler
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SECTION .text:CODE:REORDER(1)
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EXTI1_IRQHandler
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B EXTI1_IRQHandler
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PUBWEAK EXTI2_IRQHandler
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SECTION .text:CODE:REORDER(1)
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EXTI2_IRQHandler
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B EXTI2_IRQHandler
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PUBWEAK EXTI3_IRQHandler
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SECTION .text:CODE:REORDER(1)
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EXTI3_IRQHandler
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B EXTI3_IRQHandler
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PUBWEAK EXTI4_IRQHandler
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SECTION .text:CODE:REORDER(1)
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EXTI4_IRQHandler
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B EXTI4_IRQHandler
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PUBWEAK DMA1_Channel1_IRQHandler
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SECTION .text:CODE:REORDER(1)
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DMA1_Channel1_IRQHandler
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B DMA1_Channel1_IRQHandler
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PUBWEAK DMA1_Channel2_IRQHandler
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SECTION .text:CODE:REORDER(1)
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DMA1_Channel2_IRQHandler
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B DMA1_Channel2_IRQHandler
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PUBWEAK DMA1_Channel3_IRQHandler
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SECTION .text:CODE:REORDER(1)
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DMA1_Channel3_IRQHandler
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B DMA1_Channel3_IRQHandler
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PUBWEAK DMA1_Channel4_IRQHandler
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SECTION .text:CODE:REORDER(1)
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DMA1_Channel4_IRQHandler
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B DMA1_Channel4_IRQHandler
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PUBWEAK DMA1_Channel5_IRQHandler
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SECTION .text:CODE:REORDER(1)
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DMA1_Channel5_IRQHandler
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B DMA1_Channel5_IRQHandler
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PUBWEAK DMA1_Channel6_IRQHandler
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SECTION .text:CODE:REORDER(1)
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DMA1_Channel6_IRQHandler
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B DMA1_Channel6_IRQHandler
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PUBWEAK DMA1_Channel7_IRQHandler
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SECTION .text:CODE:REORDER(1)
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DMA1_Channel7_IRQHandler
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B DMA1_Channel7_IRQHandler
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PUBWEAK ADC1_IRQHandler
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SECTION .text:CODE:REORDER(1)
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ADC1_IRQHandler
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B ADC1_IRQHandler
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PUBWEAK USB_HP_IRQHandler
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SECTION .text:CODE:REORDER(1)
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USB_HP_IRQHandler
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B USB_HP_IRQHandler
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PUBWEAK USB_LP_IRQHandler
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SECTION .text:CODE:REORDER(1)
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USB_LP_IRQHandler
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B USB_LP_IRQHandler
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PUBWEAK DAC_IRQHandler
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SECTION .text:CODE:REORDER(1)
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DAC_IRQHandler
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B DAC_IRQHandler
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PUBWEAK COMP_IRQHandler
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SECTION .text:CODE:REORDER(1)
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COMP_IRQHandler
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B COMP_IRQHandler
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PUBWEAK EXTI9_5_IRQHandler
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SECTION .text:CODE:REORDER(1)
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EXTI9_5_IRQHandler
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B EXTI9_5_IRQHandler
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PUBWEAK LCD_IRQHandler
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SECTION .text:CODE:REORDER(1)
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LCD_IRQHandler
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B LCD_IRQHandler
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PUBWEAK TIM9_IRQHandler
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SECTION .text:CODE:REORDER(1)
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TIM9_IRQHandler
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B TIM9_IRQHandler
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PUBWEAK TIM10_IRQHandler
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SECTION .text:CODE:REORDER(1)
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TIM10_IRQHandler
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B TIM10_IRQHandler
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PUBWEAK TIM11_IRQHandler
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SECTION .text:CODE:REORDER(1)
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TIM11_IRQHandler
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B TIM11_IRQHandler
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PUBWEAK TIM2_IRQHandler
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SECTION .text:CODE:REORDER(1)
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TIM2_IRQHandler
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B TIM2_IRQHandler
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PUBWEAK TIM3_IRQHandler
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SECTION .text:CODE:REORDER(1)
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TIM3_IRQHandler
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B TIM3_IRQHandler
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PUBWEAK TIM4_IRQHandler
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SECTION .text:CODE:REORDER(1)
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TIM4_IRQHandler
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B TIM4_IRQHandler
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PUBWEAK I2C1_EV_IRQHandler
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SECTION .text:CODE:REORDER(1)
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I2C1_EV_IRQHandler
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B I2C1_EV_IRQHandler
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PUBWEAK I2C1_ER_IRQHandler
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SECTION .text:CODE:REORDER(1)
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I2C1_ER_IRQHandler
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B I2C1_ER_IRQHandler
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PUBWEAK I2C2_EV_IRQHandler
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SECTION .text:CODE:REORDER(1)
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I2C2_EV_IRQHandler
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B I2C2_EV_IRQHandler
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PUBWEAK I2C2_ER_IRQHandler
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SECTION .text:CODE:REORDER(1)
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I2C2_ER_IRQHandler
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B I2C2_ER_IRQHandler
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PUBWEAK SPI1_IRQHandler
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SECTION .text:CODE:REORDER(1)
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SPI1_IRQHandler
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B SPI1_IRQHandler
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PUBWEAK SPI2_IRQHandler
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SECTION .text:CODE:REORDER(1)
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SPI2_IRQHandler
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B SPI2_IRQHandler
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PUBWEAK USART1_IRQHandler
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SECTION .text:CODE:REORDER(1)
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USART1_IRQHandler
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B USART1_IRQHandler
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PUBWEAK USART2_IRQHandler
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SECTION .text:CODE:REORDER(1)
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USART2_IRQHandler
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B USART2_IRQHandler
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PUBWEAK USART3_IRQHandler
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SECTION .text:CODE:REORDER(1)
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USART3_IRQHandler
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B USART3_IRQHandler
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PUBWEAK EXTI15_10_IRQHandler
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SECTION .text:CODE:REORDER(1)
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EXTI15_10_IRQHandler
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B EXTI15_10_IRQHandler
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PUBWEAK RTC_Alarm_IRQHandler
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SECTION .text:CODE:REORDER(1)
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RTC_Alarm_IRQHandler
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B RTC_Alarm_IRQHandler
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PUBWEAK USB_FS_WKUP_IRQHandler
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SECTION .text:CODE:REORDER(1)
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USB_FS_WKUP_IRQHandler
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B USB_FS_WKUP_IRQHandler
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PUBWEAK TIM6_IRQHandler
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SECTION .text:CODE:REORDER(1)
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TIM6_IRQHandler
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B TIM6_IRQHandler
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PUBWEAK TIM7_IRQHandler
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SECTION .text:CODE:REORDER(1)
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TIM7_IRQHandler
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B TIM7_IRQHandler
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END
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/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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@ -0,0 +1,367 @@
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/**
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******************************************************************************
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* @file system_stm32l1xx.c
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* @author MCD Application Team
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* @version V1.0.3
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* @date May-2013
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* @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
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* This file contains the system clock configuration for STM32L1xx Ultra
|
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* Low Medium-density devices, and is generated by the clock configuration
|
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* tool "STM32L1xx_Clock_Configuration_V1.0.0.xls".
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*
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* 1. This file provides two functions and one global variable to be called from
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* user application:
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* - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
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* and Divider factors, AHB/APBx prescalers and Flash settings),
|
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* depending on the configuration made in the clock xls tool.
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* This function is called at startup just after reset and
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* before branch to main program. This call is made inside
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* the "startup_stm32l1xx_md.s" file.
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*
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* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
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* by the user application to setup the SysTick
|
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* timer or configure other parameters.
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*
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* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
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* be called whenever the core clock is changed
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* during program execution.
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*
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||||
* 2. After each device reset the MSI (2.1 MHz Range) is used as system clock source.
|
||||
* Then SystemInit() function is called, in "startup_stm32l1xx_md.s" file, to
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* configure the system clock before to branch to main program.
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*
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* 3. If the system clock source selected by user fails to startup, the SystemInit()
|
||||
* function will do nothing and MSI still used as system clock source. User can
|
||||
* add some code to deal with this issue inside the SetSysClock() function.
|
||||
*
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||||
* 4. The default value of HSE crystal is set to 8MHz, refer to "HSE_VALUE" define
|
||||
* in "stm32l1xx.h" file. When HSE is used as system clock source, directly or
|
||||
* through PLL, and you are using different crystal you have to adapt the HSE
|
||||
* value to your own configuration.
|
||||
*
|
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* 5. This file configures the system clock as follows:
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*=============================================================================
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* System Clock Configuration
|
||||
*=============================================================================
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* System clock source | HSI
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*-----------------------------------------------------------------------------
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||||
* SYSCLK | 16000000 Hz
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*-----------------------------------------------------------------------------
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* HCLK | 16000000 Hz
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*-----------------------------------------------------------------------------
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* AHB Prescaler | 1
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||||
*-----------------------------------------------------------------------------
|
||||
* APB1 Prescaler | 1
|
||||
*-----------------------------------------------------------------------------
|
||||
* APB2 Prescaler | 1
|
||||
*-----------------------------------------------------------------------------
|
||||
* HSE Frequency | 8000000 Hz
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL DIV | Not Used
|
||||
*-----------------------------------------------------------------------------
|
||||
* PLL MUL | Not Used
|
||||
*-----------------------------------------------------------------------------
|
||||
* VDD | 3.3 V
|
||||
*-----------------------------------------------------------------------------
|
||||
* Vcore | 1.8 V (Range 1)
|
||||
*-----------------------------------------------------------------------------
|
||||
* Flash Latency | 0 WS
|
||||
*-----------------------------------------------------------------------------
|
||||
* Require 48MHz for USB clock | Disabled
|
||||
*-----------------------------------------------------------------------------
|
||||
*=============================================================================
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
|
||||
* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
|
||||
* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
|
||||
* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
|
||||
* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2010 STMicroelectronics</center></h2>
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/** @addtogroup CMSIS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup stm32l1xx_system
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32L1xx_System_Private_Includes
|
||||
* @{
|
||||
*/
|
||||
|
||||
#include "stm32l1xx.h"
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32L1xx_System_Private_TypesDefinitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32L1xx_System_Private_Defines
|
||||
* @{
|
||||
*/
|
||||
/*!< Uncomment the following line if you need to relocate your vector Table in
|
||||
Internal SRAM. */
|
||||
/* #define VECT_TAB_SRAM */
|
||||
#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field.
|
||||
This value must be a multiple of 0x200. */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32L1xx_System_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32L1xx_System_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
uint32_t SystemCoreClock = 16000000;
|
||||
__I uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48};
|
||||
__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32L1xx_System_Private_FunctionPrototypes
|
||||
* @{
|
||||
*/
|
||||
|
||||
static void SetSysClock(void);
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup STM32L1xx_System_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Setup the microcontroller system.
|
||||
* Initialize the Embedded Flash Interface, the PLL and update the
|
||||
* SystemCoreClock variable.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SystemInit (void)
|
||||
{
|
||||
/*!< Set MSION bit */
|
||||
RCC->CR |= (uint32_t)0x00000100;
|
||||
|
||||
/*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */
|
||||
RCC->CFGR &= (uint32_t)0x88FFC00C;
|
||||
|
||||
/*!< Reset HSION, HSEON, CSSON and PLLON bits */
|
||||
RCC->CR &= (uint32_t)0xEEFEFFFE;
|
||||
|
||||
/*!< Reset HSEBYP bit */
|
||||
RCC->CR &= (uint32_t)0xFFFBFFFF;
|
||||
|
||||
/*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */
|
||||
RCC->CFGR &= (uint32_t)0xFF02FFFF;
|
||||
|
||||
/*!< Disable all interrupts */
|
||||
RCC->CIR = 0x00000000;
|
||||
|
||||
/* Configure the System clock frequency, AHB/APBx prescalers and Flash settings */
|
||||
SetSysClock();
|
||||
|
||||
#ifdef VECT_TAB_SRAM
|
||||
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
|
||||
#else
|
||||
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
|
||||
#endif
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Update SystemCoreClock according to Clock Register Values
|
||||
* @note - The system frequency computed by this function is not the real
|
||||
* frequency in the chip. It is calculated based on the predefined
|
||||
* constant and the selected clock source:
|
||||
*
|
||||
* - If SYSCLK source is MSI, SystemCoreClock will contain the MSI
|
||||
* value as defined by the MSI range.
|
||||
*
|
||||
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
|
||||
*
|
||||
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
|
||||
*
|
||||
* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
|
||||
* or HSI_VALUE(*) multiplied/divided by the PLL factors.
|
||||
*
|
||||
* (*) HSI_VALUE is a constant defined in stm32l1xx.h file (default value
|
||||
* 16 MHz) but the real value may vary depending on the variations
|
||||
* in voltage and temperature.
|
||||
*
|
||||
* (**) HSE_VALUE is a constant defined in stm32l1xx.h file (default value
|
||||
* 8 MHz), user has to ensure that HSE_VALUE is same as the real
|
||||
* frequency of the crystal used. Otherwise, this function may
|
||||
* have wrong result.
|
||||
*
|
||||
* - The result of this function could be not correct when using fractional
|
||||
* value for HSE crystal.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SystemCoreClockUpdate (void)
|
||||
{
|
||||
uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, msirange = 0;
|
||||
|
||||
/* Get SYSCLK source -------------------------------------------------------*/
|
||||
tmp = RCC->CFGR & RCC_CFGR_SWS;
|
||||
|
||||
switch (tmp)
|
||||
{
|
||||
case 0x00: /* MSI used as system clock */
|
||||
msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
|
||||
SystemCoreClock = (32768 * (1 << (msirange + 1)));
|
||||
break;
|
||||
case 0x04: /* HSI used as system clock */
|
||||
SystemCoreClock = HSI_VALUE;
|
||||
break;
|
||||
case 0x08: /* HSE used as system clock */
|
||||
SystemCoreClock = HSE_VALUE;
|
||||
break;
|
||||
case 0x0C: /* PLL used as system clock */
|
||||
/* Get PLL clock source and multiplication factor ----------------------*/
|
||||
pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;
|
||||
plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;
|
||||
pllmul = PLLMulTable[(pllmul >> 18)];
|
||||
plldiv = (plldiv >> 22) + 1;
|
||||
|
||||
pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
|
||||
|
||||
if (pllsource == 0x00)
|
||||
{
|
||||
/* HSI oscillator clock selected as PLL clock entry */
|
||||
SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* HSE selected as PLL clock entry */
|
||||
SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv);
|
||||
}
|
||||
break;
|
||||
default: /* MSI used as system clock */
|
||||
msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
|
||||
SystemCoreClock = (32768 * (1 << (msirange + 1)));
|
||||
break;
|
||||
}
|
||||
/* Compute HCLK clock frequency --------------------------------------------*/
|
||||
/* Get HCLK prescaler */
|
||||
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
|
||||
/* HCLK clock frequency */
|
||||
SystemCoreClock >>= tmp;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures the System clock frequency, AHB/APBx prescalers and Flash
|
||||
* settings.
|
||||
* @note This function should be called only once the RCC clock configuration
|
||||
* is reset to the default reset state (done in SystemInit() function).
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
static void SetSysClock(void)
|
||||
{
|
||||
__IO uint32_t StartUpCounter = 0, HSIStatus = 0;
|
||||
|
||||
/* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
|
||||
/* Enable HSI */
|
||||
RCC->CR |= ((uint32_t)RCC_CR_HSION);
|
||||
|
||||
/* Wait till HSI is ready and if Time out is reached exit */
|
||||
do
|
||||
{
|
||||
HSIStatus = RCC->CR & RCC_CR_HSIRDY;
|
||||
} while((HSIStatus == 0) && (StartUpCounter != HSI_STARTUP_TIMEOUT));
|
||||
|
||||
if ((RCC->CR & RCC_CR_HSIRDY) != RESET)
|
||||
{
|
||||
HSIStatus = (uint32_t)0x01;
|
||||
}
|
||||
else
|
||||
{
|
||||
HSIStatus = (uint32_t)0x00;
|
||||
}
|
||||
|
||||
if (HSIStatus == (uint32_t)0x01)
|
||||
{
|
||||
/* Flash 0 wait state */
|
||||
FLASH->ACR &= ~FLASH_ACR_LATENCY;
|
||||
|
||||
/* Disable Prefetch Buffer */
|
||||
FLASH->ACR &= ~FLASH_ACR_PRFTEN;
|
||||
|
||||
/* Disable 64-bit access */
|
||||
FLASH->ACR &= ~FLASH_ACR_ACC64;
|
||||
|
||||
|
||||
/* Power enable */
|
||||
RCC->APB1ENR |= RCC_APB1ENR_PWREN;
|
||||
|
||||
/* Select the Voltage Range 1 (1.8 V) */
|
||||
PWR->CR = PWR_CR_VOS_0;
|
||||
|
||||
|
||||
/* Wait Until the Voltage Regulator is ready */
|
||||
while((PWR->CSR & PWR_CSR_VOSF) != RESET)
|
||||
{
|
||||
}
|
||||
|
||||
/* HCLK = SYSCLK /1*/
|
||||
RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK /1*/
|
||||
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
|
||||
|
||||
/* PCLK1 = HCLK /1*/
|
||||
RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
|
||||
|
||||
/* Select HSI as system clock source */
|
||||
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
|
||||
RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSI;
|
||||
|
||||
/* Wait till HSI is used as system clock source */
|
||||
while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_HSI)
|
||||
{
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* If HSI fails to start-up, the application will have wrong clock
|
||||
configuration. User can add here some code to deal with this error */
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/******************* (C) COPYRIGHT 2010 STMicroelectronics *****END OF FILE****/
|
||||
Loading…
Add table
Add a link
Reference in a new issue