mirror of
https://github.com/FreeRTOS/FreeRTOS-Kernel.git
synced 2025-06-04 03:19:04 -04:00
Add STM32L Discovery board project as a starting point to adapt to an RTOS demo.
This commit is contained in:
Richard Barry
parent
417c3d1054
commit
b89fd7c1e3
1328
FreeRTOS/Demo/CORTEX_STM32L152_Discovery_IAR/RTOSDemo.ewd
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FreeRTOS/Demo/CORTEX_STM32L152_Discovery_IAR/RTOSDemo.ewd
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FreeRTOS/Demo/CORTEX_STM32L152_Discovery_IAR/RTOSDemo.ewp
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FreeRTOS/Demo/CORTEX_STM32L152_Discovery_IAR/RTOSDemo.ewp
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FreeRTOS/Demo/CORTEX_STM32L152_Discovery_IAR/RTOSDemo.eww
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FreeRTOS/Demo/CORTEX_STM32L152_Discovery_IAR/RTOSDemo.eww
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@ -0,0 +1,10 @@
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<?xml version="1.0" encoding="iso-8859-1"?>
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<workspace>
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<project>
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<path>$WS_DIR$\RTOSDemo.ewp</path>
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</project>
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<batchBuild/>
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</workspace>
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@ -0,0 +1,104 @@
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/**
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******************************************************************************
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* @file system_stm32l1xx.h
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* @author MCD Application Team
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* @version V1.1.1
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* @date 09-March-2012
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* @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Header File.
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
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*
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* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
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* You may not use this file except in compliance with the License.
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* You may obtain a copy of the License at:
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*
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||||
* http://www.st.com/software_license_agreement_liberty_v2
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*
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* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
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* limitations under the License.
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*
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******************************************************************************
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*/
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/** @addtogroup CMSIS
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* @{
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*/
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/** @addtogroup stm32l1xx_system
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* @{
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*/
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/**
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* @brief Define to prevent recursive inclusion
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*/
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#ifndef __SYSTEM_STM32L1XX_H
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#define __SYSTEM_STM32L1XX_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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|
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/** @addtogroup STM32L1xx_System_Includes
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* @{
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*/
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/**
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* @}
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*/
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/** @addtogroup STM32L1xx_System_Exported_types
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* @{
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*/
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extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
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/**
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* @}
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*/
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/** @addtogroup STM32L1xx_System_Exported_Constants
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* @{
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*/
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/**
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* @}
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*/
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|
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/** @addtogroup STM32L1xx_System_Exported_Macros
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* @{
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*/
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|
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/**
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* @}
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*/
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/** @addtogroup STM32L1xx_System_Exported_Functions
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* @{
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*/
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extern void SystemInit(void);
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extern void SystemCoreClockUpdate(void);
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif
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#endif /*__SYSTEM_STM32L1XX_H */
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|
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/**
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* @}
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*/
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|
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/**
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* @}
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*/
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/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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@ -0,0 +1,38 @@
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/* ----------------------------------------------------------------------
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* Copyright (C) 2010 ARM Limited. All rights reserved.
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*
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* $Date: 11. November 2010
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* $Revision: V1.0.2
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*
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* Project: CMSIS DSP Library
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* Title: arm_common_tables.h
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*
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* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
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*
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* Target Processor: Cortex-M4/Cortex-M3
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*
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* Version 1.0.2 2010/11/11
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* Documentation updated.
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*
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* Version 1.0.1 2010/10/05
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* Production release and review comments incorporated.
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*
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* Version 1.0.0 2010/09/20
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* Production release and review comments incorporated.
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* -------------------------------------------------------------------- */
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#ifndef _ARM_COMMON_TABLES_H
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#define _ARM_COMMON_TABLES_H
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#include "arm_math.h"
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extern const uint16_t armBitRevTable[1024];
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extern const q15_t armRecipTableQ15[64];
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extern const q31_t armRecipTableQ31[64];
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extern const q31_t realCoefAQ31[1024];
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extern const q31_t realCoefBQ31[1024];
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extern const float32_t twiddleCoef[6144];
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extern const q31_t twiddleCoefQ31[6144];
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extern const q15_t twiddleCoefQ15[6144];
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#endif /* ARM_COMMON_TABLES_H */
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/**************************************************************************//**
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* @file core_cmFunc.h
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* @brief CMSIS Cortex-M Core Function Access Header File
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* @version V3.01
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* @date 06. March 2012
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*
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* @note
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* Copyright (C) 2009-2012 ARM Limited. All rights reserved.
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*
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* @par
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* ARM Limited (ARM) is supplying this software for use with Cortex-M
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* processor based microcontrollers. This file can be freely distributed
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* within development tools that are supporting such ARM based processors.
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*
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* @par
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* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
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* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
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* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
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*
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******************************************************************************/
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#ifndef __CORE_CMFUNC_H
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#define __CORE_CMFUNC_H
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/* ########################### Core Function Access ########################### */
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/** \ingroup CMSIS_Core_FunctionInterface
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\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
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@{
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*/
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#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
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/* ARM armcc specific functions */
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#if (__ARMCC_VERSION < 400677)
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#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
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#endif
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/* intrinsic void __enable_irq(); */
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/* intrinsic void __disable_irq(); */
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/** \brief Get Control Register
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This function returns the content of the Control Register.
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\return Control Register value
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*/
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__STATIC_INLINE uint32_t __get_CONTROL(void)
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{
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register uint32_t __regControl __ASM("control");
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return(__regControl);
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}
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/** \brief Set Control Register
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This function writes the given value to the Control Register.
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\param [in] control Control Register value to set
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*/
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__STATIC_INLINE void __set_CONTROL(uint32_t control)
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{
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register uint32_t __regControl __ASM("control");
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__regControl = control;
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}
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/** \brief Get IPSR Register
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This function returns the content of the IPSR Register.
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\return IPSR Register value
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*/
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__STATIC_INLINE uint32_t __get_IPSR(void)
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{
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register uint32_t __regIPSR __ASM("ipsr");
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return(__regIPSR);
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}
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/** \brief Get APSR Register
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This function returns the content of the APSR Register.
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\return APSR Register value
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*/
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__STATIC_INLINE uint32_t __get_APSR(void)
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{
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register uint32_t __regAPSR __ASM("apsr");
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return(__regAPSR);
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}
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/** \brief Get xPSR Register
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This function returns the content of the xPSR Register.
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\return xPSR Register value
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*/
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__STATIC_INLINE uint32_t __get_xPSR(void)
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{
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register uint32_t __regXPSR __ASM("xpsr");
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return(__regXPSR);
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}
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/** \brief Get Process Stack Pointer
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This function returns the current value of the Process Stack Pointer (PSP).
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\return PSP Register value
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*/
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__STATIC_INLINE uint32_t __get_PSP(void)
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{
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register uint32_t __regProcessStackPointer __ASM("psp");
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return(__regProcessStackPointer);
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}
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/** \brief Set Process Stack Pointer
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This function assigns the given value to the Process Stack Pointer (PSP).
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\param [in] topOfProcStack Process Stack Pointer value to set
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*/
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__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
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{
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register uint32_t __regProcessStackPointer __ASM("psp");
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__regProcessStackPointer = topOfProcStack;
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}
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/** \brief Get Main Stack Pointer
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This function returns the current value of the Main Stack Pointer (MSP).
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\return MSP Register value
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*/
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__STATIC_INLINE uint32_t __get_MSP(void)
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{
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register uint32_t __regMainStackPointer __ASM("msp");
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return(__regMainStackPointer);
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}
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/** \brief Set Main Stack Pointer
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This function assigns the given value to the Main Stack Pointer (MSP).
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\param [in] topOfMainStack Main Stack Pointer value to set
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*/
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__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
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{
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register uint32_t __regMainStackPointer __ASM("msp");
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__regMainStackPointer = topOfMainStack;
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}
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/** \brief Get Priority Mask
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This function returns the current state of the priority mask bit from the Priority Mask Register.
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\return Priority Mask value
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*/
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__STATIC_INLINE uint32_t __get_PRIMASK(void)
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{
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register uint32_t __regPriMask __ASM("primask");
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return(__regPriMask);
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}
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/** \brief Set Priority Mask
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This function assigns the given value to the Priority Mask Register.
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\param [in] priMask Priority Mask
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*/
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__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
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{
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register uint32_t __regPriMask __ASM("primask");
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__regPriMask = (priMask);
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}
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#if (__CORTEX_M >= 0x03)
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/** \brief Enable FIQ
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This function enables FIQ interrupts by clearing the F-bit in the CPSR.
|
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Can only be executed in Privileged modes.
|
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*/
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#define __enable_fault_irq __enable_fiq
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|
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/** \brief Disable FIQ
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|
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This function disables FIQ interrupts by setting the F-bit in the CPSR.
|
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Can only be executed in Privileged modes.
|
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*/
|
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#define __disable_fault_irq __disable_fiq
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|
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/** \brief Get Base Priority
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This function returns the current value of the Base Priority register.
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|
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\return Base Priority register value
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*/
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__STATIC_INLINE uint32_t __get_BASEPRI(void)
|
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{
|
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register uint32_t __regBasePri __ASM("basepri");
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return(__regBasePri);
|
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}
|
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|
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|
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/** \brief Set Base Priority
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|
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This function assigns the given value to the Base Priority register.
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|
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\param [in] basePri Base Priority value to set
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*/
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__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
|
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{
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register uint32_t __regBasePri __ASM("basepri");
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__regBasePri = (basePri & 0xff);
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}
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|
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|
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/** \brief Get Fault Mask
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|
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This function returns the current value of the Fault Mask register.
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|
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\return Fault Mask register value
|
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*/
|
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__STATIC_INLINE uint32_t __get_FAULTMASK(void)
|
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{
|
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register uint32_t __regFaultMask __ASM("faultmask");
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return(__regFaultMask);
|
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}
|
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|
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/** \brief Set Fault Mask
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|
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This function assigns the given value to the Fault Mask register.
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|
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\param [in] faultMask Fault Mask value to set
|
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*/
|
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__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
|
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{
|
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register uint32_t __regFaultMask __ASM("faultmask");
|
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__regFaultMask = (faultMask & (uint32_t)1);
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}
|
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|
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#endif /* (__CORTEX_M >= 0x03) */
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|
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#if (__CORTEX_M == 0x04)
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|
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/** \brief Get FPSCR
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This function returns the current value of the Floating Point Status/Control register.
|
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|
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\return Floating Point Status/Control register value
|
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*/
|
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__STATIC_INLINE uint32_t __get_FPSCR(void)
|
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{
|
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#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
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register uint32_t __regfpscr __ASM("fpscr");
|
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return(__regfpscr);
|
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#else
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return(0);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set FPSCR
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|
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This function assigns the given value to the Floating Point Status/Control register.
|
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|
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\param [in] fpscr Floating Point Status/Control value to set
|
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*/
|
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__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
|
||||
{
|
||||
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
||||
register uint32_t __regfpscr __ASM("fpscr");
|
||||
__regfpscr = (fpscr);
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif /* (__CORTEX_M == 0x04) */
|
||||
|
||||
|
||||
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
|
||||
/* IAR iccarm specific functions */
|
||||
|
||||
#include <cmsis_iar.h>
|
||||
|
||||
|
||||
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
|
||||
/* TI CCS specific functions */
|
||||
|
||||
#include <cmsis_ccs.h>
|
||||
|
||||
|
||||
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
|
||||
/* GNU gcc specific functions */
|
||||
|
||||
/** \brief Enable IRQ Interrupts
|
||||
|
||||
This function enables IRQ interrupts by clearing the I-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
|
||||
{
|
||||
__ASM volatile ("cpsie i");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Disable IRQ Interrupts
|
||||
|
||||
This function disables IRQ interrupts by setting the I-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
|
||||
{
|
||||
__ASM volatile ("cpsid i");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Control Register
|
||||
|
||||
This function returns the content of the Control Register.
|
||||
|
||||
\return Control Register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, control" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Control Register
|
||||
|
||||
This function writes the given value to the Control Register.
|
||||
|
||||
\param [in] control Control Register value to set
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
|
||||
{
|
||||
__ASM volatile ("MSR control, %0" : : "r" (control) );
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get IPSR Register
|
||||
|
||||
This function returns the content of the IPSR Register.
|
||||
|
||||
\return IPSR Register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, ipsr" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get APSR Register
|
||||
|
||||
This function returns the content of the APSR Register.
|
||||
|
||||
\return APSR Register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, apsr" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get xPSR Register
|
||||
|
||||
This function returns the content of the xPSR Register.
|
||||
|
||||
\return xPSR Register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, xpsr" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Process Stack Pointer
|
||||
|
||||
This function returns the current value of the Process Stack Pointer (PSP).
|
||||
|
||||
\return PSP Register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
|
||||
{
|
||||
register uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, psp\n" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Process Stack Pointer
|
||||
|
||||
This function assigns the given value to the Process Stack Pointer (PSP).
|
||||
|
||||
\param [in] topOfProcStack Process Stack Pointer value to set
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
|
||||
{
|
||||
__ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) );
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Main Stack Pointer
|
||||
|
||||
This function returns the current value of the Main Stack Pointer (MSP).
|
||||
|
||||
\return MSP Register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
|
||||
{
|
||||
register uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, msp\n" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Main Stack Pointer
|
||||
|
||||
This function assigns the given value to the Main Stack Pointer (MSP).
|
||||
|
||||
\param [in] topOfMainStack Main Stack Pointer value to set
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
|
||||
{
|
||||
__ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) );
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Priority Mask
|
||||
|
||||
This function returns the current state of the priority mask bit from the Priority Mask Register.
|
||||
|
||||
\return Priority Mask value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, primask" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Priority Mask
|
||||
|
||||
This function assigns the given value to the Priority Mask Register.
|
||||
|
||||
\param [in] priMask Priority Mask
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
|
||||
{
|
||||
__ASM volatile ("MSR primask, %0" : : "r" (priMask) );
|
||||
}
|
||||
|
||||
|
||||
#if (__CORTEX_M >= 0x03)
|
||||
|
||||
/** \brief Enable FIQ
|
||||
|
||||
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
|
||||
{
|
||||
__ASM volatile ("cpsie f");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Disable FIQ
|
||||
|
||||
This function disables FIQ interrupts by setting the F-bit in the CPSR.
|
||||
Can only be executed in Privileged modes.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
|
||||
{
|
||||
__ASM volatile ("cpsid f");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Base Priority
|
||||
|
||||
This function returns the current value of the Base Priority register.
|
||||
|
||||
\return Base Priority register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Base Priority
|
||||
|
||||
This function assigns the given value to the Base Priority register.
|
||||
|
||||
\param [in] basePri Base Priority value to set
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
|
||||
{
|
||||
__ASM volatile ("MSR basepri, %0" : : "r" (value) );
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Fault Mask
|
||||
|
||||
This function returns the current value of the Fault Mask register.
|
||||
|
||||
\return Fault Mask register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("MRS %0, faultmask" : "=r" (result) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Fault Mask
|
||||
|
||||
This function assigns the given value to the Fault Mask register.
|
||||
|
||||
\param [in] faultMask Fault Mask value to set
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
|
||||
{
|
||||
__ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
|
||||
}
|
||||
|
||||
#endif /* (__CORTEX_M >= 0x03) */
|
||||
|
||||
|
||||
#if (__CORTEX_M == 0x04)
|
||||
|
||||
/** \brief Get FPSCR
|
||||
|
||||
This function returns the current value of the Floating Point Status/Control register.
|
||||
|
||||
\return Floating Point Status/Control register value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
|
||||
{
|
||||
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
|
||||
return(result);
|
||||
#else
|
||||
return(0);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set FPSCR
|
||||
|
||||
This function assigns the given value to the Floating Point Status/Control register.
|
||||
|
||||
\param [in] fpscr Floating Point Status/Control value to set
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
|
||||
{
|
||||
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
||||
__ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) );
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif /* (__CORTEX_M == 0x04) */
|
||||
|
||||
|
||||
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
|
||||
/* TASKING carm specific functions */
|
||||
|
||||
/*
|
||||
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||||
* Please use "carm -?i" to get an up to date list of all instrinsics,
|
||||
* Including the CMSIS ones.
|
||||
*/
|
||||
|
||||
#endif
|
||||
|
||||
/*@} end of CMSIS_Core_RegAccFunctions */
|
||||
|
||||
|
||||
#endif /* __CORE_CMFUNC_H */
|
||||
|
|
@ -0,0 +1,618 @@
|
|||
/**************************************************************************//**
|
||||
* @file core_cmInstr.h
|
||||
* @brief CMSIS Cortex-M Core Instruction Access Header File
|
||||
* @version V3.01
|
||||
* @date 06. March 2012
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2009-2012 ARM Limited. All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* ARM Limited (ARM) is supplying this software for use with Cortex-M
|
||||
* processor based microcontrollers. This file can be freely distributed
|
||||
* within development tools that are supporting such ARM based processors.
|
||||
*
|
||||
* @par
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
******************************************************************************/
|
||||
|
||||
#ifndef __CORE_CMINSTR_H
|
||||
#define __CORE_CMINSTR_H
|
||||
|
||||
|
||||
/* ########################## Core Instruction Access ######################### */
|
||||
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
|
||||
Access to dedicated instructions
|
||||
@{
|
||||
*/
|
||||
|
||||
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
|
||||
/* ARM armcc specific functions */
|
||||
|
||||
#if (__ARMCC_VERSION < 400677)
|
||||
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
|
||||
#endif
|
||||
|
||||
|
||||
/** \brief No Operation
|
||||
|
||||
No Operation does nothing. This instruction can be used for code alignment purposes.
|
||||
*/
|
||||
#define __NOP __nop
|
||||
|
||||
|
||||
/** \brief Wait For Interrupt
|
||||
|
||||
Wait For Interrupt is a hint instruction that suspends execution
|
||||
until one of a number of events occurs.
|
||||
*/
|
||||
#define __WFI __wfi
|
||||
|
||||
|
||||
/** \brief Wait For Event
|
||||
|
||||
Wait For Event is a hint instruction that permits the processor to enter
|
||||
a low-power state until one of a number of events occurs.
|
||||
*/
|
||||
#define __WFE __wfe
|
||||
|
||||
|
||||
/** \brief Send Event
|
||||
|
||||
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
|
||||
*/
|
||||
#define __SEV __sev
|
||||
|
||||
|
||||
/** \brief Instruction Synchronization Barrier
|
||||
|
||||
Instruction Synchronization Barrier flushes the pipeline in the processor,
|
||||
so that all instructions following the ISB are fetched from cache or
|
||||
memory, after the instruction has been completed.
|
||||
*/
|
||||
#define __ISB() __isb(0xF)
|
||||
|
||||
|
||||
/** \brief Data Synchronization Barrier
|
||||
|
||||
This function acts as a special kind of Data Memory Barrier.
|
||||
It completes when all explicit memory accesses before this instruction complete.
|
||||
*/
|
||||
#define __DSB() __dsb(0xF)
|
||||
|
||||
|
||||
/** \brief Data Memory Barrier
|
||||
|
||||
This function ensures the apparent order of the explicit memory operations before
|
||||
and after the instruction, without ensuring their completion.
|
||||
*/
|
||||
#define __DMB() __dmb(0xF)
|
||||
|
||||
|
||||
/** \brief Reverse byte order (32 bit)
|
||||
|
||||
This function reverses the byte order in integer value.
|
||||
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#define __REV __rev
|
||||
|
||||
|
||||
/** \brief Reverse byte order (16 bit)
|
||||
|
||||
This function reverses the byte order in two unsigned short values.
|
||||
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
|
||||
{
|
||||
rev16 r0, r0
|
||||
bx lr
|
||||
}
|
||||
|
||||
|
||||
/** \brief Reverse byte order in signed short value
|
||||
|
||||
This function reverses the byte order in a signed short value with sign extension to integer.
|
||||
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
|
||||
{
|
||||
revsh r0, r0
|
||||
bx lr
|
||||
}
|
||||
|
||||
|
||||
/** \brief Rotate Right in unsigned value (32 bit)
|
||||
|
||||
This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
|
||||
|
||||
\param [in] value Value to rotate
|
||||
\param [in] value Number of Bits to rotate
|
||||
\return Rotated value
|
||||
*/
|
||||
#define __ROR __ror
|
||||
|
||||
|
||||
#if (__CORTEX_M >= 0x03)
|
||||
|
||||
/** \brief Reverse bit order of value
|
||||
|
||||
This function reverses the bit order of the given value.
|
||||
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
#define __RBIT __rbit
|
||||
|
||||
|
||||
/** \brief LDR Exclusive (8 bit)
|
||||
|
||||
This function performs a exclusive LDR command for 8 bit value.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint8_t at (*ptr)
|
||||
*/
|
||||
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
|
||||
|
||||
|
||||
/** \brief LDR Exclusive (16 bit)
|
||||
|
||||
This function performs a exclusive LDR command for 16 bit values.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint16_t at (*ptr)
|
||||
*/
|
||||
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
|
||||
|
||||
|
||||
/** \brief LDR Exclusive (32 bit)
|
||||
|
||||
This function performs a exclusive LDR command for 32 bit values.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint32_t at (*ptr)
|
||||
*/
|
||||
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
|
||||
|
||||
|
||||
/** \brief STR Exclusive (8 bit)
|
||||
|
||||
This function performs a exclusive STR command for 8 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
#define __STREXB(value, ptr) __strex(value, ptr)
|
||||
|
||||
|
||||
/** \brief STR Exclusive (16 bit)
|
||||
|
||||
This function performs a exclusive STR command for 16 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
#define __STREXH(value, ptr) __strex(value, ptr)
|
||||
|
||||
|
||||
/** \brief STR Exclusive (32 bit)
|
||||
|
||||
This function performs a exclusive STR command for 32 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
#define __STREXW(value, ptr) __strex(value, ptr)
|
||||
|
||||
|
||||
/** \brief Remove the exclusive lock
|
||||
|
||||
This function removes the exclusive lock which is created by LDREX.
|
||||
|
||||
*/
|
||||
#define __CLREX __clrex
|
||||
|
||||
|
||||
/** \brief Signed Saturate
|
||||
|
||||
This function saturates a signed value.
|
||||
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (1..32)
|
||||
\return Saturated value
|
||||
*/
|
||||
#define __SSAT __ssat
|
||||
|
||||
|
||||
/** \brief Unsigned Saturate
|
||||
|
||||
This function saturates an unsigned value.
|
||||
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (0..31)
|
||||
\return Saturated value
|
||||
*/
|
||||
#define __USAT __usat
|
||||
|
||||
|
||||
/** \brief Count leading zeros
|
||||
|
||||
This function counts the number of leading zeros of a data value.
|
||||
|
||||
\param [in] value Value to count the leading zeros
|
||||
\return number of leading zeros in value
|
||||
*/
|
||||
#define __CLZ __clz
|
||||
|
||||
#endif /* (__CORTEX_M >= 0x03) */
|
||||
|
||||
|
||||
|
||||
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
|
||||
/* IAR iccarm specific functions */
|
||||
|
||||
#include <cmsis_iar.h>
|
||||
|
||||
|
||||
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
|
||||
/* TI CCS specific functions */
|
||||
|
||||
#include <cmsis_ccs.h>
|
||||
|
||||
|
||||
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
|
||||
/* GNU gcc specific functions */
|
||||
|
||||
/** \brief No Operation
|
||||
|
||||
No Operation does nothing. This instruction can be used for code alignment purposes.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
|
||||
{
|
||||
__ASM volatile ("nop");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Wait For Interrupt
|
||||
|
||||
Wait For Interrupt is a hint instruction that suspends execution
|
||||
until one of a number of events occurs.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
|
||||
{
|
||||
__ASM volatile ("wfi");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Wait For Event
|
||||
|
||||
Wait For Event is a hint instruction that permits the processor to enter
|
||||
a low-power state until one of a number of events occurs.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
|
||||
{
|
||||
__ASM volatile ("wfe");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Send Event
|
||||
|
||||
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
|
||||
{
|
||||
__ASM volatile ("sev");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Instruction Synchronization Barrier
|
||||
|
||||
Instruction Synchronization Barrier flushes the pipeline in the processor,
|
||||
so that all instructions following the ISB are fetched from cache or
|
||||
memory, after the instruction has been completed.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
|
||||
{
|
||||
__ASM volatile ("isb");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Data Synchronization Barrier
|
||||
|
||||
This function acts as a special kind of Data Memory Barrier.
|
||||
It completes when all explicit memory accesses before this instruction complete.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
|
||||
{
|
||||
__ASM volatile ("dsb");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Data Memory Barrier
|
||||
|
||||
This function ensures the apparent order of the explicit memory operations before
|
||||
and after the instruction, without ensuring their completion.
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
|
||||
{
|
||||
__ASM volatile ("dmb");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Reverse byte order (32 bit)
|
||||
|
||||
This function reverses the byte order in integer value.
|
||||
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Reverse byte order (16 bit)
|
||||
|
||||
This function reverses the byte order in two unsigned short values.
|
||||
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Reverse byte order in signed short value
|
||||
|
||||
This function reverses the byte order in a signed short value with sign extension to integer.
|
||||
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Rotate Right in unsigned value (32 bit)
|
||||
|
||||
This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
|
||||
|
||||
\param [in] value Value to rotate
|
||||
\param [in] value Number of Bits to rotate
|
||||
\return Rotated value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
|
||||
__ASM volatile ("ror %0, %0, %1" : "+r" (op1) : "r" (op2) );
|
||||
return(op1);
|
||||
}
|
||||
|
||||
|
||||
#if (__CORTEX_M >= 0x03)
|
||||
|
||||
/** \brief Reverse bit order of value
|
||||
|
||||
This function reverses the bit order of the given value.
|
||||
|
||||
\param [in] value Value to reverse
|
||||
\return Reversed value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief LDR Exclusive (8 bit)
|
||||
|
||||
This function performs a exclusive LDR command for 8 bit value.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint8_t at (*ptr)
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
|
||||
{
|
||||
uint8_t result;
|
||||
|
||||
__ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief LDR Exclusive (16 bit)
|
||||
|
||||
This function performs a exclusive LDR command for 16 bit values.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint16_t at (*ptr)
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
|
||||
{
|
||||
uint16_t result;
|
||||
|
||||
__ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief LDR Exclusive (32 bit)
|
||||
|
||||
This function performs a exclusive LDR command for 32 bit values.
|
||||
|
||||
\param [in] ptr Pointer to data
|
||||
\return value of type uint32_t at (*ptr)
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief STR Exclusive (8 bit)
|
||||
|
||||
This function performs a exclusive STR command for 8 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief STR Exclusive (16 bit)
|
||||
|
||||
This function performs a exclusive STR command for 16 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("strexh %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief STR Exclusive (32 bit)
|
||||
|
||||
This function performs a exclusive STR command for 32 bit values.
|
||||
|
||||
\param [in] value Value to store
|
||||
\param [in] ptr Pointer to location
|
||||
\return 0 Function succeeded
|
||||
\return 1 Function failed
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("strex %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
||||
/** \brief Remove the exclusive lock
|
||||
|
||||
This function removes the exclusive lock which is created by LDREX.
|
||||
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
|
||||
{
|
||||
__ASM volatile ("clrex");
|
||||
}
|
||||
|
||||
|
||||
/** \brief Signed Saturate
|
||||
|
||||
This function saturates a signed value.
|
||||
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (1..32)
|
||||
\return Saturated value
|
||||
*/
|
||||
#define __SSAT(ARG1,ARG2) \
|
||||
({ \
|
||||
uint32_t __RES, __ARG1 = (ARG1); \
|
||||
__ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
|
||||
__RES; \
|
||||
})
|
||||
|
||||
|
||||
/** \brief Unsigned Saturate
|
||||
|
||||
This function saturates an unsigned value.
|
||||
|
||||
\param [in] value Value to be saturated
|
||||
\param [in] sat Bit position to saturate to (0..31)
|
||||
\return Saturated value
|
||||
*/
|
||||
#define __USAT(ARG1,ARG2) \
|
||||
({ \
|
||||
uint32_t __RES, __ARG1 = (ARG1); \
|
||||
__ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
|
||||
__RES; \
|
||||
})
|
||||
|
||||
|
||||
/** \brief Count leading zeros
|
||||
|
||||
This function counts the number of leading zeros of a data value.
|
||||
|
||||
\param [in] value Value to count the leading zeros
|
||||
\return number of leading zeros in value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
|
||||
{
|
||||
uint8_t result;
|
||||
|
||||
__ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
#endif /* (__CORTEX_M >= 0x03) */
|
||||
|
||||
|
||||
|
||||
|
||||
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
|
||||
/* TASKING carm specific functions */
|
||||
|
||||
/*
|
||||
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||||
* Please use "carm -?i" to get an up to date list of all intrinsics,
|
||||
* Including the CMSIS ones.
|
||||
*/
|
||||
|
||||
#endif
|
||||
|
||||
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
|
||||
|
||||
#endif /* __CORE_CMINSTR_H */
|
||||
|
|
@ -0,0 +1,798 @@
|
|||
/**************************************************************************//**
|
||||
* @file core_sc000.h
|
||||
* @brief CMSIS SC000 Core Peripheral Access Layer Header File
|
||||
* @version V3.01
|
||||
* @date 22. March 2012
|
||||
*
|
||||
* @note
|
||||
* Copyright (C) 2009-2012 ARM Limited. All rights reserved.
|
||||
*
|
||||
* @par
|
||||
* ARM Limited (ARM) is supplying this software for use with Cortex-M
|
||||
* processor based microcontrollers. This file can be freely distributed
|
||||
* within development tools that are supporting such ARM based processors.
|
||||
*
|
||||
* @par
|
||||
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
|
||||
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
|
||||
*
|
||||
******************************************************************************/
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#ifndef __CORE_SC000_H_GENERIC
|
||||
#define __CORE_SC000_H_GENERIC
|
||||
|
||||
/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
|
||||
CMSIS violates the following MISRA-C:2004 rules:
|
||||
|
||||
\li Required Rule 8.5, object/function definition in header file.<br>
|
||||
Function definitions in header files are used to allow 'inlining'.
|
||||
|
||||
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
|
||||
Unions are used for effective representation of core registers.
|
||||
|
||||
\li Advisory Rule 19.7, Function-like macro defined.<br>
|
||||
Function-like macros are used to allow more efficient code.
|
||||
*/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* CMSIS definitions
|
||||
******************************************************************************/
|
||||
/** \ingroup SC000
|
||||
@{
|
||||
*/
|
||||
|
||||
/* CMSIS SC000 definitions */
|
||||
#define __SC000_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
|
||||
#define __SC000_CMSIS_VERSION_SUB (0x01) /*!< [15:0] CMSIS HAL sub version */
|
||||
#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16) | \
|
||||
__SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
|
||||
|
||||
#define __CORTEX_SC (0) /*!< Cortex secure core */
|
||||
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#define __ASM __asm /*!< asm keyword for ARM Compiler */
|
||||
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
|
||||
#define __STATIC_INLINE static __inline
|
||||
|
||||
#elif defined ( __ICCARM__ )
|
||||
#define __ASM __asm /*!< asm keyword for IAR Compiler */
|
||||
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
|
||||
#define __STATIC_INLINE static inline
|
||||
|
||||
#elif defined ( __GNUC__ )
|
||||
#define __ASM __asm /*!< asm keyword for GNU Compiler */
|
||||
#define __INLINE inline /*!< inline keyword for GNU Compiler */
|
||||
#define __STATIC_INLINE static inline
|
||||
|
||||
#elif defined ( __TASKING__ )
|
||||
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
|
||||
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
|
||||
#define __STATIC_INLINE static inline
|
||||
|
||||
#endif
|
||||
|
||||
/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
|
||||
*/
|
||||
#define __FPU_USED 0
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#if defined __TARGET_FPU_VFP
|
||||
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __ICCARM__ )
|
||||
#if defined __ARMVFP__
|
||||
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __GNUC__ )
|
||||
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
|
||||
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __TASKING__ )
|
||||
#if defined __FPU_VFP__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#include <stdint.h> /* standard types definitions */
|
||||
#include <core_cmInstr.h> /* Core Instruction Access */
|
||||
#include <core_cmFunc.h> /* Core Function Access */
|
||||
|
||||
#endif /* __CORE_SC000_H_GENERIC */
|
||||
|
||||
#ifndef __CMSIS_GENERIC
|
||||
|
||||
#ifndef __CORE_SC000_H_DEPENDANT
|
||||
#define __CORE_SC000_H_DEPENDANT
|
||||
|
||||
/* check device defines and use defaults */
|
||||
#if defined __CHECK_DEVICE_DEFINES
|
||||
#ifndef __SC000_REV
|
||||
#define __SC000_REV 0x0000
|
||||
#warning "__SC000_REV not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
#ifndef __MPU_PRESENT
|
||||
#define __MPU_PRESENT 0
|
||||
#warning "__MPU_PRESENT not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
#ifndef __NVIC_PRIO_BITS
|
||||
#define __NVIC_PRIO_BITS 2
|
||||
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
#ifndef __Vendor_SysTickConfig
|
||||
#define __Vendor_SysTickConfig 0
|
||||
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* IO definitions (access restrictions to peripheral registers) */
|
||||
/**
|
||||
\defgroup CMSIS_glob_defs CMSIS Global Defines
|
||||
|
||||
<strong>IO Type Qualifiers</strong> are used
|
||||
\li to specify the access to peripheral variables.
|
||||
\li for automatic generation of peripheral register debug information.
|
||||
*/
|
||||
#ifdef __cplusplus
|
||||
#define __I volatile /*!< Defines 'read only' permissions */
|
||||
#else
|
||||
#define __I volatile const /*!< Defines 'read only' permissions */
|
||||
#endif
|
||||
#define __O volatile /*!< Defines 'write only' permissions */
|
||||
#define __IO volatile /*!< Defines 'read / write' permissions */
|
||||
|
||||
/*@} end of group SC000 */
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Register Abstraction
|
||||
Core Register contain:
|
||||
- Core Register
|
||||
- Core NVIC Register
|
||||
- Core SCB Register
|
||||
- Core SysTick Register
|
||||
- Core MPU Register
|
||||
******************************************************************************/
|
||||
/** \defgroup CMSIS_core_register Defines and Type Definitions
|
||||
\brief Type definitions and defines for Cortex-M processor based devices.
|
||||
*/
|
||||
|
||||
/** \ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_CORE Status and Control Registers
|
||||
\brief Core Register type definitions.
|
||||
@{
|
||||
*/
|
||||
|
||||
/** \brief Union type to access the Application Program Status Register (APSR).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
#if (__CORTEX_M != 0x04)
|
||||
uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
|
||||
#else
|
||||
uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
|
||||
uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
|
||||
uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
|
||||
#endif
|
||||
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
|
||||
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
||||
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
||||
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
|
||||
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} APSR_Type;
|
||||
|
||||
|
||||
/** \brief Union type to access the Interrupt Program Status Register (IPSR).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
||||
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} IPSR_Type;
|
||||
|
||||
|
||||
/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
||||
#if (__CORTEX_M != 0x04)
|
||||
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
|
||||
#else
|
||||
uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
|
||||
uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
|
||||
uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
|
||||
#endif
|
||||
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
|
||||
uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
|
||||
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
|
||||
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
||||
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
||||
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
|
||||
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} xPSR_Type;
|
||||
|
||||
|
||||
/** \brief Union type to access the Control Registers (CONTROL).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
|
||||
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
|
||||
uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
|
||||
uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} CONTROL_Type;
|
||||
|
||||
/*@} end of group CMSIS_CORE */
|
||||
|
||||
|
||||
/** \ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
|
||||
\brief Type definitions for the NVIC Registers
|
||||
@{
|
||||
*/
|
||||
|
||||
/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
|
||||
uint32_t RESERVED0[31];
|
||||
__IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
|
||||
uint32_t RSERVED1[31];
|
||||
__IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
|
||||
uint32_t RESERVED2[31];
|
||||
__IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
|
||||
uint32_t RESERVED3[31];
|
||||
uint32_t RESERVED4[64];
|
||||
__IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
|
||||
} NVIC_Type;
|
||||
|
||||
/*@} end of group CMSIS_NVIC */
|
||||
|
||||
|
||||
/** \ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_SCB System Control Block (SCB)
|
||||
\brief Type definitions for the System Control Block Registers
|
||||
@{
|
||||
*/
|
||||
|
||||
/** \brief Structure type to access the System Control Block (SCB).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
|
||||
__IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
|
||||
__IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
|
||||
__IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
|
||||
__IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
|
||||
__IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
|
||||
uint32_t RESERVED0[1];
|
||||
__IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
|
||||
__IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
|
||||
uint32_t RESERVED1[154];
|
||||
__IO uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Register */
|
||||
} SCB_Type;
|
||||
|
||||
/* SCB CPUID Register Definitions */
|
||||
#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
|
||||
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
|
||||
|
||||
#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
|
||||
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
|
||||
|
||||
#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
|
||||
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
|
||||
|
||||
#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
|
||||
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
|
||||
|
||||
#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
|
||||
#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
|
||||
|
||||
/* SCB Interrupt Control State Register Definitions */
|
||||
#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
|
||||
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
|
||||
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
|
||||
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
|
||||
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
|
||||
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
|
||||
|
||||
#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
|
||||
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
|
||||
|
||||
#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
|
||||
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
|
||||
|
||||
#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
|
||||
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
|
||||
|
||||
#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
|
||||
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
|
||||
|
||||
/* SCB Interrupt Control State Register Definitions */
|
||||
#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
|
||||
#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
|
||||
|
||||
/* SCB Application Interrupt and Reset Control Register Definitions */
|
||||
#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
|
||||
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
|
||||
|
||||
#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
|
||||
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
|
||||
|
||||
#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
|
||||
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
|
||||
|
||||
#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
|
||||
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
|
||||
|
||||
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
|
||||
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
|
||||
|
||||
/* SCB System Control Register Definitions */
|
||||
#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
|
||||
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
|
||||
|
||||
#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
|
||||
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
|
||||
|
||||
#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
|
||||
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
|
||||
|
||||
/* SCB Configuration Control Register Definitions */
|
||||
#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
|
||||
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
|
||||
|
||||
#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
|
||||
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
|
||||
|
||||
/* SCB System Handler Control and State Register Definitions */
|
||||
#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
|
||||
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
|
||||
|
||||
/* SCB Security Features Register Definitions */
|
||||
#define SCB_SFCR_UNIBRTIMING_Pos 0 /*!< SCB SFCR: UNIBRTIMING Position */
|
||||
#define SCB_SFCR_UNIBRTIMING_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SFCR: UNIBRTIMING Mask */
|
||||
|
||||
#define SCB_SFCR_SECKEY_Pos 16 /*!< SCB SFCR: SECKEY Position */
|
||||
#define SCB_SFCR_SECKEY_Msk (0xFFFFUL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SFCR: SECKEY Mask */
|
||||
|
||||
/*@} end of group CMSIS_SCB */
|
||||
|
||||
|
||||
/** \ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
|
||||
\brief Type definitions for the System Control and ID Register not in the SCB
|
||||
@{
|
||||
*/
|
||||
|
||||
/** \brief Structure type to access the System Control and ID Register not in the SCB.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t RESERVED0[2];
|
||||
__IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
|
||||
} SCnSCB_Type;
|
||||
|
||||
/* Auxiliary Control Register Definitions */
|
||||
#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
|
||||
#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */
|
||||
|
||||
/*@} end of group CMSIS_SCnotSCB */
|
||||
|
||||
|
||||
/** \ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
|
||||
\brief Type definitions for the System Timer Registers.
|
||||
@{
|
||||
*/
|
||||
|
||||
/** \brief Structure type to access the System Timer (SysTick).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
|
||||
__IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
|
||||
__IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
|
||||
__I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
|
||||
} SysTick_Type;
|
||||
|
||||
/* SysTick Control / Status Register Definitions */
|
||||
#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
|
||||
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
|
||||
|
||||
#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
|
||||
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
|
||||
|
||||
#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
|
||||
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
|
||||
|
||||
#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
|
||||
#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
|
||||
|
||||
/* SysTick Reload Register Definitions */
|
||||
#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
|
||||
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
|
||||
|
||||
/* SysTick Current Register Definitions */
|
||||
#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
|
||||
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
|
||||
|
||||
/* SysTick Calibration Register Definitions */
|
||||
#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
|
||||
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
|
||||
|
||||
#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
|
||||
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
|
||||
|
||||
#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
|
||||
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
|
||||
|
||||
/*@} end of group CMSIS_SysTick */
|
||||
|
||||
#if (__MPU_PRESENT == 1)
|
||||
/** \ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_MPU Memory Protection Unit (MPU)
|
||||
\brief Type definitions for the Memory Protection Unit (MPU)
|
||||
@{
|
||||
*/
|
||||
|
||||
/** \brief Structure type to access the Memory Protection Unit (MPU).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
|
||||
__IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
|
||||
__IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
|
||||
__IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
|
||||
__IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
|
||||
} MPU_Type;
|
||||
|
||||
/* MPU Type Register */
|
||||
#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
|
||||
#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
|
||||
|
||||
#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
|
||||
#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
|
||||
|
||||
#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
|
||||
#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
|
||||
|
||||
/* MPU Control Register */
|
||||
#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
|
||||
#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
|
||||
|
||||
#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
|
||||
#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
|
||||
|
||||
#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
|
||||
#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
|
||||
|
||||
/* MPU Region Number Register */
|
||||
#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
|
||||
#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
|
||||
|
||||
/* MPU Region Base Address Register */
|
||||
#define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
|
||||
#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
|
||||
|
||||
#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
|
||||
#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
|
||||
|
||||
#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
|
||||
#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
|
||||
|
||||
/* MPU Region Attribute and Size Register */
|
||||
#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
|
||||
#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
|
||||
|
||||
#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
|
||||
#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
|
||||
|
||||
#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
|
||||
#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
|
||||
|
||||
#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
|
||||
#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
|
||||
|
||||
#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
|
||||
#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
|
||||
|
||||
#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
|
||||
#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
|
||||
|
||||
#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
|
||||
#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
|
||||
|
||||
#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
|
||||
#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
|
||||
|
||||
#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
|
||||
#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
|
||||
|
||||
#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
|
||||
#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
|
||||
|
||||
/*@} end of group CMSIS_MPU */
|
||||
#endif
|
||||
|
||||
|
||||
/** \ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
|
||||
\brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR)
|
||||
are only accessible over DAP and not via processor. Therefore
|
||||
they are not covered by the Cortex-M0 header file.
|
||||
@{
|
||||
*/
|
||||
/*@} end of group CMSIS_CoreDebug */
|
||||
|
||||
|
||||
/** \ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_core_base Core Definitions
|
||||
\brief Definitions for base addresses, unions, and structures.
|
||||
@{
|
||||
*/
|
||||
|
||||
/* Memory mapping of SC000 Hardware */
|
||||
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
|
||||
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
|
||||
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
|
||||
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
|
||||
|
||||
#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
|
||||
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
|
||||
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
|
||||
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
|
||||
|
||||
#if (__MPU_PRESENT == 1)
|
||||
#define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
|
||||
#define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
|
||||
#endif
|
||||
|
||||
/*@} */
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Hardware Abstraction Layer
|
||||
Core Function Interface contains:
|
||||
- Core NVIC Functions
|
||||
- Core SysTick Functions
|
||||
- Core Register Access Functions
|
||||
******************************************************************************/
|
||||
/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/* ########################## NVIC functions #################################### */
|
||||
/** \ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
|
||||
\brief Functions that manage interrupts and exceptions via the NVIC.
|
||||
@{
|
||||
*/
|
||||
|
||||
/* Interrupt Priorities are WORD accessible only under ARMv6M */
|
||||
/* The following MACROS handle generation of the register offset and byte masks */
|
||||
#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
|
||||
#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
|
||||
#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
|
||||
|
||||
|
||||
/** \brief Enable External Interrupt
|
||||
|
||||
The function enables a device-specific interrupt in the NVIC interrupt controller.
|
||||
|
||||
\param [in] IRQn External interrupt number. Value cannot be negative.
|
||||
*/
|
||||
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
|
||||
}
|
||||
|
||||
|
||||
/** \brief Disable External Interrupt
|
||||
|
||||
The function disables a device-specific interrupt in the NVIC interrupt controller.
|
||||
|
||||
\param [in] IRQn External interrupt number. Value cannot be negative.
|
||||
*/
|
||||
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Pending Interrupt
|
||||
|
||||
The function reads the pending register in the NVIC and returns the pending bit
|
||||
for the specified interrupt.
|
||||
|
||||
\param [in] IRQn Interrupt number.
|
||||
|
||||
\return 0 Interrupt status is not pending.
|
||||
\return 1 Interrupt status is pending.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Pending Interrupt
|
||||
|
||||
The function sets the pending bit of an external interrupt.
|
||||
|
||||
\param [in] IRQn Interrupt number. Value cannot be negative.
|
||||
*/
|
||||
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
|
||||
}
|
||||
|
||||
|
||||
/** \brief Clear Pending Interrupt
|
||||
|
||||
The function clears the pending bit of an external interrupt.
|
||||
|
||||
\param [in] IRQn External interrupt number. Value cannot be negative.
|
||||
*/
|
||||
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
|
||||
}
|
||||
|
||||
|
||||
/** \brief Set Interrupt Priority
|
||||
|
||||
The function sets the priority of an interrupt.
|
||||
|
||||
\note The priority cannot be set for every core interrupt.
|
||||
|
||||
\param [in] IRQn Interrupt number.
|
||||
\param [in] priority Priority to set.
|
||||
*/
|
||||
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
||||
{
|
||||
if(IRQn < 0) {
|
||||
SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
|
||||
(((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
|
||||
else {
|
||||
NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
|
||||
(((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
|
||||
}
|
||||
|
||||
|
||||
/** \brief Get Interrupt Priority
|
||||
|
||||
The function reads the priority of an interrupt. The interrupt
|
||||
number can be positive to specify an external (device specific)
|
||||
interrupt, or negative to specify an internal (core) interrupt.
|
||||
|
||||
|
||||
\param [in] IRQn Interrupt number.
|
||||
\return Interrupt Priority. Value is aligned automatically to the implemented
|
||||
priority bits of the microcontroller.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
|
||||
{
|
||||
|
||||
if(IRQn < 0) {
|
||||
return((uint32_t)((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for SC000 system interrupts */
|
||||
else {
|
||||
return((uint32_t)((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
|
||||
}
|
||||
|
||||
|
||||
/** \brief System Reset
|
||||
|
||||
The function initiates a system reset request to reset the MCU.
|
||||
*/
|
||||
__STATIC_INLINE void NVIC_SystemReset(void)
|
||||
{
|
||||
__DSB(); /* Ensure all outstanding memory accesses included
|
||||
buffered write are completed before reset */
|
||||
SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
|
||||
SCB_AIRCR_SYSRESETREQ_Msk);
|
||||
__DSB(); /* Ensure completion of memory access */
|
||||
while(1); /* wait until reset */
|
||||
}
|
||||
|
||||
/*@} end of CMSIS_Core_NVICFunctions */
|
||||
|
||||
|
||||
|
||||
/* ################################## SysTick function ############################################ */
|
||||
/** \ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
|
||||
\brief Functions that configure the System.
|
||||
@{
|
||||
*/
|
||||
|
||||
#if (__Vendor_SysTickConfig == 0)
|
||||
|
||||
/** \brief System Tick Configuration
|
||||
|
||||
The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
|
||||
Counter is in free running mode to generate periodic interrupts.
|
||||
|
||||
\param [in] ticks Number of ticks between two interrupts.
|
||||
|
||||
\return 0 Function succeeded.
|
||||
\return 1 Function failed.
|
||||
|
||||
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
|
||||
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
|
||||
must contain a vendor-specific implementation of this function.
|
||||
|
||||
*/
|
||||
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
|
||||
{
|
||||
if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
|
||||
|
||||
SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */
|
||||
NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
|
||||
SysTick->VAL = 0; /* Load the SysTick Counter Value */
|
||||
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
|
||||
SysTick_CTRL_TICKINT_Msk |
|
||||
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
|
||||
return (0); /* Function successful */
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
/*@} end of CMSIS_Core_SysTickFunctions */
|
||||
|
||||
|
||||
|
||||
|
||||
#endif /* __CORE_SC000_H_DEPENDANT */
|
||||
|
||||
#endif /* __CMSIS_GENERIC */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
File diff suppressed because it is too large
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|
|
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|
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|
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|
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|
||||
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|
||||
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|
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|
||||
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|
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|
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
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|
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|
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|
||||
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|
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|
||||
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|
||||
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|
||||
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
<style type="disc">
|
||||
</style><!--[if gte mso 9]><xml> <o:shapedefaults v:ext="edit" spidmax="45058"/> </xml><![endif]--><!--[if gte mso 9]><xml> <o:shapelayout v:ext="edit"> <o:idmap v:ext="edit" data="1"/> </o:shapelayout></xml><![endif]--><meta content="MCD Application Team" name="author"></head>
|
||||
<body link="blue" vlink="blue">
|
||||
<div class="Section1">
|
||||
<p class="MsoNormal"><span style="font-family: Arial;"><br>
|
||||
</span><span style="font-family: Arial;"><o:p></o:p></span></p>
|
||||
<div align="center">
|
||||
<table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" cellspacing="0" width="900">
|
||||
<tbody>
|
||||
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|
||||
<td style="padding: 0cm;" valign="top">
|
||||
<table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" cellspacing="0" width="900">
|
||||
<tbody>
|
||||
<tr style="">
|
||||
<td style="padding: 1.5pt;">
|
||||
|
||||
<h1 style="margin-bottom: 18pt; text-align: center;" align="center"><span style="font-size: 20pt; font-family: Verdana; color: rgb(51, 102, 255);">Release
|
||||
Notes for<o:p></o:p> </span><span style="font-size: 20pt; color: rgb(51, 102, 255); font-family: Verdana;">STM32L1xx Standard Peripherals Library Drivers</span><span style="font-size: 20pt; font-family: Verdana;"><o:p></o:p></span><br>
|
||||
<span style="font-size: 20pt; font-family: Verdana;"><o:p></o:p></span></h1>
|
||||
<p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;">Copyright
|
||||
© 2012 STMicroelectronics</span><span style="color: black;"><u1:p></u1:p><o:p></o:p></span></p>
|
||||
<p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt;"><img style="border: 0px solid ; width: 86px; height: 65px;" alt="" id="_x0000_i1025" src="../../_htmresc/logo.bmp"></span></p>
|
||||
</td>
|
||||
</tr>
|
||||
</tbody>
|
||||
</table>
|
||||
<p class="MsoNormal"><span style="font-family: Arial; display: none;"><o:p> </o:p></span></p>
|
||||
<table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" width="900">
|
||||
<tbody>
|
||||
<tr style="">
|
||||
<td style="padding: 0cm;" valign="top">
|
||||
<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><span style="font-size: 12pt; color: white;">Contents<o:p></o:p></span></h2>
|
||||
<ol style="margin-top: 0cm;" start="1" type="1">
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><a href="#History">STM32L1xx Standard Peripherals Library Drivers update history</a><o:p></o:p></span></li>
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><a href="#License">License</a><o:p></o:p></span></li>
|
||||
</ol>
|
||||
<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="History"></a><span style="font-size: 12pt; color: white;">STM32L1xx Standard Peripherals Library Drivers update history<o:p></o:p></span></h2>
|
||||
|
||||
<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 167px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.1.1 / 05-March-2012<o:p></o:p></span></h3>
|
||||
<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
|
||||
Changes<o:p></o:p></span></u></b></p>
|
||||
|
||||
<ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">All source files: license disclaimer text update and add link to the License file on ST Internet.</span></li></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 189px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.1.0 / 24-January-2012<o:p></o:p></span></h3>
|
||||
<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
|
||||
Changes<o:p></o:p></span></u></b></p>
|
||||
|
||||
<ul style="margin-top: 0cm;" type="square">
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Official version for <span style="font-weight: bold; font-style: italic;">STM32L1xx High-density</span> and <span style="font-weight: bold; font-style: italic;">Medium-density Plus</span> devices.</span><br>
|
||||
<span style="font-size: 10pt; font-family: Verdana;"></span></li>
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new drivers for new peripherals on </span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold; font-style: italic;">STM32L1xx High-density</span> and <span style="font-weight: bold; font-style: italic;">Medium-density Plus</span></span><span style="font-size: 10pt; font-family: Verdana;"> devices:</span></li>
|
||||
<ul style="font-weight: bold; font-style: italic;">
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32l1xx_aes.h/.c </span></li>
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32l1xx_fsmc.h/.c </span></li>
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32l1xx_opamp.h/.c </span></li>
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32l1xx_sdio.h/.c </span></li>
|
||||
</ul>
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32l1xx_adc.h/.c</span></li>
|
||||
<ul>
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new channel for ADC Bank B</span></li>
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new function to select between Bank A and Bank B: void ADC_BankSelection(ADC_TypeDef* ADCx, uint8_t ADC_BankSelection);</span></li>
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Update ADC_InjectedChannelConfig() and ADC_RegularChannelConfig() to support new ADC channels.<br>
|
||||
</span></li>
|
||||
</ul>
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32l1xx_comp.h/.c</span></li>
|
||||
<ul>
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new function: void COMP_SW1SwitchConfig(FunctionalState NewState);<br>
|
||||
</span></li>
|
||||
</ul>
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32l1xx_dbgmcu.h/.c</span></li>
|
||||
<ul>
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new parameter for TIM5<br>
|
||||
</span></li>
|
||||
</ul>
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32l1xx_dma.h/.c</span></li>
|
||||
<ul>
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add DMA2 support<br>
|
||||
</span></li>
|
||||
</ul>
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32l1xx_exti.h/.c</span></li>
|
||||
<ul>
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new EXTI Line 23 connected to TS channel acquisition event<br>
|
||||
</span></li>
|
||||
</ul>
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32l1xx_flash.h/.c</span></li>
|
||||
<ul>
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new pages definitions for Write protection</span></li>
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new flag FLASH_FLAG_OPTVERRUSR</span></li>
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add
|
||||
new functions: FLASH_OB_WRP1Config(), FLASH_OB_WRP2Config(),
|
||||
FLASH_OB_BootConfig(), FLASH_OB_GetWRP1(), FLASH_OB_GetWRP2(),
|
||||
FLASH_EraseParallelPage() and FLASH_ProgramParallelHalfPage().</span></li>
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Update
|
||||
functions to avoid STM32L1XX_MD workaround on Data EEPROM (FAST)
|
||||
halfword/byte erase: DATA_EEPROM_FastProgramByte(),
|
||||
DATA_EEPROM_FastProgramHalfWord(), DATA_EEPROM_ProgramByte() and
|
||||
DATA_EEPROM_ProgramHalfWord().</span></li>
|
||||
</ul>
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32l1xx_flash_ramfunc.c</span></li>
|
||||
<ul>
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new functions: FLASH_EraseParallelPage() and FLASH_ProgramParallelHalfPage().</span></li>
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Update
|
||||
FLASH_ProgramHalfPage(), FLASH_ProgramParallelHalfPage(),
|
||||
DATA_EEPROM_EraseDoubleWord() and DATA_EEPROM_ProgramDoubleWord()
|
||||
functions.</span></li>
|
||||
|
||||
</ul>
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32l1xx_gpio.h/.c</span></li>
|
||||
<ul>
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new GPIO port definition.</span></li>
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new alternate functions for new peripherals.<br>
|
||||
</span></li>
|
||||
</ul>
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32l1xx_i2c.h/.c</span></li>
|
||||
<ul>
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new function: void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition)<br>
|
||||
</span></li>
|
||||
</ul>
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32l1xx_rcc.h/.c</span></li>
|
||||
<ul>
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new interrupt for RCC_IT_LSECSS</span></li>
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new definitions for new peripherals</span></li>
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new function: RCC_LSEClockSecuritySystemCmd()<br>
|
||||
</span></li>
|
||||
</ul>
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32l1xx_rtc.h/.c</span></li>
|
||||
<ul>
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">SYNCH_PREDIV max value changed to 0x7FFF</span></li>
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new definitions for RTC Alarm Sub Second "RTC_Alarm_Sub_Seconds_Masks" and Alarm Sub Second max value (0x7FFF)</span></li>
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add
|
||||
new definitions for: RTC_Calib_Output_selection,
|
||||
RTC_Smooth_calib_period, RTC_Smooth_calib_Plus_pulses,
|
||||
RTC_Smooth_calib_Minus_pulses.</span></li>
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new definitions: RTC_TamperTrigger_LowLevel and RTC_TamperTrigger_HighLevel.</span></li>
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add
|
||||
new definitions for RTC_Tamper_Filter, RTC_Tamper_Sampling_Frequencies,
|
||||
RTC_Tamper_Pin_Precharge_Duration, RTC_Tamper_2 and RTC_Tamper_3.</span></li>
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new RTC_Add_1_Second_Parameter and RTC_Substract_Fraction_Of_Second_Value defintions.</span></li>
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new Backup registers definitions from RTC_BKP_DR20 to RTC_BKP_DR31.</span></li>
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new flags: RTC_FLAG_RECALPF, RTC_FLAG_TAMP3F and RTC_FLAG_TAMP2F</span></li>
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new interrupts definitions RTC_IT_TAMP2 and RTC_IT_TAMP3</span></li>
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new functions: <span style="font-style: italic;">RTC_BypassShadowCmd(),
|
||||
RTC_GetSubSecond(), RTC_AlarmSubSecondConfig(),
|
||||
RTC_GetAlarmSubSecond(), RTC_CalibOutputConfig(),
|
||||
RTC_SmoothCalibConfig(), RTC_GetTimeStampSubSecond(),
|
||||
RTC_TamperFilterConfig(), RTC_TamperSamplingFreqConfig(),
|
||||
RTC_TamperPinsPrechargeDuration(), RTC_TimeStampOnTamperDetectionCmd(),
|
||||
RTC_TamperPullUpCmd(), RTC_SynchroShiftConfig().</span><br>
|
||||
</span></li>
|
||||
</ul>
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32l1xx_spi.h/.c</span></li>
|
||||
<ul>
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add support for I2S</span></li>
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new structure "I2S_InitTypeDef"</span></li>
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new parameter: I2S_Mode, I2S_Standard, I2S_Data_Format, I2S_MCLK_Output, I2S_Audio_Frequency and I2S_Clock_Polarity.</span></li>
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add 2 interrupts: I2S_IT_UDR and SPI_I2S_IT_FRE</span></li>
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new flags: I2S_FLAG_CHSIDE, I2S_FLAG_UDR and SPI_I2S_FLAG_FRE</span></li>
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new functions: I2S_Init(), I2S_StructInit() and I2S_Cmd()<br>
|
||||
</span></li>
|
||||
</ul>
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32l1xx_syscfg.h/.c</span></li>
|
||||
<ul>
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"> Add support for new port: EXTI_PortSourceGPIOF and EXTI_PortSourceGPIOG</span></li>
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new remap for FSMC: SYSCFG_MemoryRemap_FSMC</span></li>
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new RI Channels and new RI IOSwitch</span></li>
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new functions: SYSCFG_GetBootMode() and SYSCFG_RIChannelSpeedConfig()<br>
|
||||
</span></li>
|
||||
</ul>
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32l1xx_tim.h/.c</span></li>
|
||||
<ul>
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Update to support TIM 32-bit</span></li>
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Change TIM_Period and TIM_Pulse to be declared as 32-bit</span></li>
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Remove the "TIM_DMABase_RCR": the RCR register is not present on STM32L1xx family.<br>
|
||||
</span></li>
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add </span><span style="font-size: 10pt; font-family: Verdana;">new parameter: </span><span style="font-size: 10pt; font-family: Verdana;">TIM_DMABase_OR <br>
|
||||
</span></li>
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Change "TIM_DMABurstLength_1Byte" to "TIM_DMABurstLength_1Transfer"</span></li>
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add
|
||||
new TIM_Remap: TIM2_TIM10_OC, TIM2_TIM5_TRGO, TIM3_TIM11_OC,
|
||||
TIM3_TIM5_TRGO, TIM10_ETR_LSE, TIM10_ETR_TIM9_TRGO, TIM11_ETR_LSE and
|
||||
TIM11_ETR_TIM9_TRGO.</span></li>
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Update TIM_RemapConfig() function coding.</span></li>
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Update all functions header comments to support TIM5.<br>
|
||||
</span></li>
|
||||
</ul>
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32l1xx_usart.h/.c</span></li>
|
||||
<ul>
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Update to support UART4 and UART5</span></li>
|
||||
<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Update all functions header comment<br>
|
||||
</span></li>
|
||||
</ul>
|
||||
</ul>
|
||||
<p class="MsoNormal"><br>
|
||||
</p>
|
||||
|
||||
<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 167px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.0 / 31-December-2010<o:p></o:p></span></h3><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
|
||||
Changes<o:p></o:p></span></u></b></p>
|
||||
<ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Created</span></li></ul><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;"><span style="font-weight: bold;"></span></span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="text-decoration: underline;"></span></span><span style="font-size: 10pt; font-family: Verdana;"></span><br><span style="font-size: 10pt; font-family: Verdana;"></span><ul style="margin-top: 0cm;" type="square"></ul>
|
||||
|
||||
<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="License"></a><span style="font-size: 12pt; color: white;">License<o:p></o:p></span></h2><p class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;">Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;">package</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;"> except in compliance with the License. You may obtain a copy of the License at:<br><br></span></p><div style="text-align: center;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;"> <a target="_blank" href="http://www.st.com/software_license_agreement_liberty_v2">http://www.st.com/software_license_agreement_liberty_v2</a></span><br><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;"></span></div><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;"><br>Unless
|
||||
required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS, <br>WITHOUT
|
||||
WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See
|
||||
the License for the specific language governing permissions and
|
||||
limitations under the License.</span>
|
||||
<div class="MsoNormal" style="text-align: center;" align="center"><span style="color: black;">
|
||||
<hr align="center" size="2" width="100%"></span></div>
|
||||
<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt; text-align: center;" align="center"><span style="font-size: 10pt; font-family: Verdana; color: black;">For
|
||||
complete documentation on </span><span style="font-size: 10pt; font-family: Verdana;">STM32<span style="color: black;"> Microcontrollers
|
||||
visit </span><u><span style="color: blue;"><a href="http://www.st.com/internet/mcu/class/1734.jsp" target="_blank">www.st.com/STM32</a></span></u></span><span style="font-size: 10pt; font-family: Verdana;"><a target="_blank" href="http://www.st.com/internet/mcu/family/141.jsp"><u><span style="color: blue;"></span></u></a></span><span style="color: black;"><o:p></o:p></span></p>
|
||||
</td>
|
||||
</tr>
|
||||
</tbody>
|
||||
</table>
|
||||
<p class="MsoNormal"><span style="font-size: 10pt;"><o:p></o:p></span></p>
|
||||
</td>
|
||||
</tr>
|
||||
</tbody>
|
||||
</table>
|
||||
</div>
|
||||
<p class="MsoNormal"><o:p> </o:p></p>
|
||||
</div>
|
||||
</body></html>
|
||||
|
|
@ -0,0 +1,202 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file misc.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.1
|
||||
* @date 05-March-2012
|
||||
* @brief This file contains all the functions prototypes for the miscellaneous
|
||||
* firmware library functions (add-on to CMSIS functions).
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __MISC_H
|
||||
#define __MISC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32l1xx.h"
|
||||
|
||||
/** @addtogroup STM32L1xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup MISC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief NVIC Init Structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled.
|
||||
This parameter can be a value of @ref IRQn_Type
|
||||
(For the complete STM32 Devices IRQ Channels list, please
|
||||
refer to stm32l1xx.h file) */
|
||||
|
||||
uint8_t NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel
|
||||
specified in NVIC_IRQChannel. This parameter can be a value
|
||||
between 0 and 15 as described in the table @ref NVIC_Priority_Table */
|
||||
|
||||
uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified
|
||||
in NVIC_IRQChannel. This parameter can be a value
|
||||
between 0 and 15 as described in the table @ref NVIC_Priority_Table */
|
||||
|
||||
FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel
|
||||
will be enabled or disabled.
|
||||
This parameter can be set either to ENABLE or DISABLE */
|
||||
} NVIC_InitTypeDef;
|
||||
|
||||
/**
|
||||
*
|
||||
@verbatim
|
||||
The table below gives the allowed values of the pre-emption priority and subpriority according
|
||||
to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function
|
||||
============================================================================================================================
|
||||
NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description
|
||||
============================================================================================================================
|
||||
NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption priority
|
||||
| | | 4 bits for subpriority
|
||||
----------------------------------------------------------------------------------------------------------------------------
|
||||
NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption priority
|
||||
| | | 3 bits for subpriority
|
||||
----------------------------------------------------------------------------------------------------------------------------
|
||||
NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption priority
|
||||
| | | 2 bits for subpriority
|
||||
----------------------------------------------------------------------------------------------------------------------------
|
||||
NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption priority
|
||||
| | | 1 bits for subpriority
|
||||
----------------------------------------------------------------------------------------------------------------------------
|
||||
NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption priority
|
||||
| | | 0 bits for subpriority
|
||||
============================================================================================================================
|
||||
@endverbatim
|
||||
*/
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup MISC_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup Vector_Table_Base
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define NVIC_VectTab_RAM ((uint32_t)0x20000000)
|
||||
#define NVIC_VectTab_FLASH ((uint32_t)0x08000000)
|
||||
#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \
|
||||
((VECTTAB) == NVIC_VectTab_FLASH))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup System_Low_Power
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define NVIC_LP_SEVONPEND ((uint8_t)0x10)
|
||||
#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04)
|
||||
#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02)
|
||||
#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \
|
||||
((LP) == NVIC_LP_SLEEPDEEP) || \
|
||||
((LP) == NVIC_LP_SLEEPONEXIT))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Preemption_Priority_Group
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define NVIC_PriorityGroup_0 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority
|
||||
4 bits for subpriority */
|
||||
#define NVIC_PriorityGroup_1 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority
|
||||
3 bits for subpriority */
|
||||
#define NVIC_PriorityGroup_2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority
|
||||
2 bits for subpriority */
|
||||
#define NVIC_PriorityGroup_3 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority
|
||||
1 bits for subpriority */
|
||||
#define NVIC_PriorityGroup_4 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority
|
||||
0 bits for subpriority */
|
||||
|
||||
#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \
|
||||
((GROUP) == NVIC_PriorityGroup_1) || \
|
||||
((GROUP) == NVIC_PriorityGroup_2) || \
|
||||
((GROUP) == NVIC_PriorityGroup_3) || \
|
||||
((GROUP) == NVIC_PriorityGroup_4))
|
||||
|
||||
#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
|
||||
|
||||
#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
|
||||
|
||||
#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x0005FFFF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SysTick_clock_source
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB)
|
||||
#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004)
|
||||
#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \
|
||||
((SOURCE) == SysTick_CLKSource_HCLK_Div8))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
|
||||
void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);
|
||||
void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);
|
||||
void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset);
|
||||
void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState);
|
||||
void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __MISC_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,650 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32l1xx_adc.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.1
|
||||
* @date 05-March-2012
|
||||
* @brief This file contains all the functions prototypes for the ADC firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32L1xx_ADC_H
|
||||
#define __STM32L1xx_ADC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32l1xx.h"
|
||||
|
||||
/** @addtogroup STM32L1xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup ADC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief ADC Init structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t ADC_Resolution; /*!< Selects the resolution of the conversion.
|
||||
This parameter can be a value of @ref ADC_Resolution */
|
||||
|
||||
FunctionalState ADC_ScanConvMode; /*!< Specifies whether the conversion is performed in
|
||||
Scan (multichannel) or Single (one channel) mode.
|
||||
This parameter can be set to ENABLE or DISABLE */
|
||||
|
||||
FunctionalState ADC_ContinuousConvMode; /*!< Specifies whether the conversion is performed in
|
||||
Continuous or Single mode.
|
||||
This parameter can be set to ENABLE or DISABLE. */
|
||||
|
||||
uint32_t ADC_ExternalTrigConvEdge; /*!< Selects the external trigger Edge and enables the
|
||||
trigger of a regular group. This parameter can be a value
|
||||
of @ref ADC_external_trigger_edge_for_regular_channels_conversion */
|
||||
|
||||
uint32_t ADC_ExternalTrigConv; /*!< Defines the external trigger used to start the analog
|
||||
to digital conversion of regular channels. This parameter
|
||||
can be a value of @ref ADC_external_trigger_sources_for_regular_channels_conversion */
|
||||
|
||||
uint32_t ADC_DataAlign; /*!< Specifies whether the ADC data alignment is left or right.
|
||||
This parameter can be a value of @ref ADC_data_align */
|
||||
|
||||
uint8_t ADC_NbrOfConversion; /*!< Specifies the number of ADC conversions that will be done
|
||||
using the sequencer for regular channel group.
|
||||
This parameter must range from 1 to 27. */
|
||||
}ADC_InitTypeDef;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t ADC_Prescaler; /*!< Selects the ADC prescaler.
|
||||
This parameter can be a value
|
||||
of @ref ADC_Prescaler */
|
||||
}ADC_CommonInitTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup ADC_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
#define IS_ADC_ALL_PERIPH(PERIPH) ((PERIPH) == ADC1)
|
||||
#define IS_ADC_DMA_PERIPH(PERIPH) ((PERIPH) == ADC1)
|
||||
|
||||
/** @defgroup ADC_Power_down_during_Idle_and_or_Delay_phase
|
||||
* @{
|
||||
*/
|
||||
#define ADC_PowerDown_Delay ((uint32_t)0x00010000)
|
||||
#define ADC_PowerDown_Idle ((uint32_t)0x00020000)
|
||||
#define ADC_PowerDown_Idle_Delay ((uint32_t)0x00030000)
|
||||
|
||||
#define IS_ADC_POWER_DOWN(DWON) (((DWON) == ADC_PowerDown_Delay) || \
|
||||
((DWON) == ADC_PowerDown_Idle) || \
|
||||
((DWON) == ADC_PowerDown_Idle_Delay))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup ADC_Prescaler
|
||||
* @{
|
||||
*/
|
||||
#define ADC_Prescaler_Div1 ((uint32_t)0x00000000)
|
||||
#define ADC_Prescaler_Div2 ((uint32_t)0x00010000)
|
||||
#define ADC_Prescaler_Div4 ((uint32_t)0x00020000)
|
||||
|
||||
#define IS_ADC_PRESCALER(PRESCALER) (((PRESCALER) == ADC_Prescaler_Div1) || \
|
||||
((PRESCALER) == ADC_Prescaler_Div2) || \
|
||||
((PRESCALER) == ADC_Prescaler_Div4))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/** @defgroup ADC_Resolution
|
||||
* @{
|
||||
*/
|
||||
#define ADC_Resolution_12b ((uint32_t)0x00000000)
|
||||
#define ADC_Resolution_10b ((uint32_t)0x01000000)
|
||||
#define ADC_Resolution_8b ((uint32_t)0x02000000)
|
||||
#define ADC_Resolution_6b ((uint32_t)0x03000000)
|
||||
|
||||
#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_Resolution_12b) || \
|
||||
((RESOLUTION) == ADC_Resolution_10b) || \
|
||||
((RESOLUTION) == ADC_Resolution_8b) || \
|
||||
((RESOLUTION) == ADC_Resolution_6b))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_external_trigger_edge_for_regular_channels_conversion
|
||||
* @{
|
||||
*/
|
||||
#define ADC_ExternalTrigConvEdge_None ((uint32_t)0x00000000)
|
||||
#define ADC_ExternalTrigConvEdge_Rising ((uint32_t)0x10000000)
|
||||
#define ADC_ExternalTrigConvEdge_Falling ((uint32_t)0x20000000)
|
||||
#define ADC_ExternalTrigConvEdge_RisingFalling ((uint32_t)0x30000000)
|
||||
|
||||
#define IS_ADC_EXT_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigConvEdge_None) || \
|
||||
((EDGE) == ADC_ExternalTrigConvEdge_Rising) || \
|
||||
((EDGE) == ADC_ExternalTrigConvEdge_Falling) || \
|
||||
((EDGE) == ADC_ExternalTrigConvEdge_RisingFalling))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_external_trigger_sources_for_regular_channels_conversion
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* TIM2 */
|
||||
#define ADC_ExternalTrigConv_T2_CC3 ((uint32_t)0x02000000)
|
||||
#define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x03000000)
|
||||
#define ADC_ExternalTrigConv_T2_TRGO ((uint32_t)0x06000000)
|
||||
|
||||
/* TIM3 */
|
||||
#define ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x07000000)
|
||||
#define ADC_ExternalTrigConv_T3_CC3 ((uint32_t)0x08000000)
|
||||
#define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x04000000)
|
||||
|
||||
/* TIM4 */
|
||||
#define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x05000000)
|
||||
#define ADC_ExternalTrigConv_T4_TRGO ((uint32_t)0x09000000)
|
||||
|
||||
/* TIM6 */
|
||||
#define ADC_ExternalTrigConv_T6_TRGO ((uint32_t)0x0A000000)
|
||||
|
||||
/* TIM9 */
|
||||
#define ADC_ExternalTrigConv_T9_CC2 ((uint32_t)0x00000000)
|
||||
#define ADC_ExternalTrigConv_T9_TRGO ((uint32_t)0x01000000)
|
||||
|
||||
/* EXTI */
|
||||
#define ADC_ExternalTrigConv_Ext_IT11 ((uint32_t)0x0F000000)
|
||||
|
||||
#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConv_T9_CC2) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConv_T9_TRGO) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConv_T2_CC3) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConv_T2_CC2) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConv_T3_TRGO) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConv_T4_CC4) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConv_T2_TRGO) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConv_T3_CC1) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConv_T3_CC3) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConv_T4_TRGO) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConv_T6_TRGO) || \
|
||||
((REGTRIG) == ADC_ExternalTrigConv_Ext_IT11))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_data_align
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define ADC_DataAlign_Right ((uint32_t)0x00000000)
|
||||
#define ADC_DataAlign_Left ((uint32_t)0x00000800)
|
||||
|
||||
#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \
|
||||
((ALIGN) == ADC_DataAlign_Left))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_channels
|
||||
* @{
|
||||
*/
|
||||
/* ADC Bank A Channels -------------------------------------------------------*/
|
||||
#define ADC_Channel_0 ((uint8_t)0x00)
|
||||
#define ADC_Channel_1 ((uint8_t)0x01)
|
||||
#define ADC_Channel_2 ((uint8_t)0x02)
|
||||
#define ADC_Channel_3 ((uint8_t)0x03)
|
||||
|
||||
#define ADC_Channel_6 ((uint8_t)0x06)
|
||||
#define ADC_Channel_7 ((uint8_t)0x07)
|
||||
#define ADC_Channel_8 ((uint8_t)0x08)
|
||||
#define ADC_Channel_9 ((uint8_t)0x09)
|
||||
#define ADC_Channel_10 ((uint8_t)0x0A)
|
||||
#define ADC_Channel_11 ((uint8_t)0x0B)
|
||||
#define ADC_Channel_12 ((uint8_t)0x0C)
|
||||
|
||||
|
||||
/* ADC Bank B Channels -------------------------------------------------------*/
|
||||
#define ADC_Channel_0b ADC_Channel_0
|
||||
#define ADC_Channel_1b ADC_Channel_1
|
||||
#define ADC_Channel_2b ADC_Channel_2
|
||||
#define ADC_Channel_3b ADC_Channel_3
|
||||
|
||||
#define ADC_Channel_6b ADC_Channel_6
|
||||
#define ADC_Channel_7b ADC_Channel_7
|
||||
#define ADC_Channel_8b ADC_Channel_8
|
||||
#define ADC_Channel_9b ADC_Channel_9
|
||||
#define ADC_Channel_10b ADC_Channel_10
|
||||
#define ADC_Channel_11b ADC_Channel_11
|
||||
#define ADC_Channel_12b ADC_Channel_12
|
||||
|
||||
/* ADC Common Channels (ADC Bank A and B) ------------------------------------*/
|
||||
#define ADC_Channel_4 ((uint8_t)0x04)
|
||||
#define ADC_Channel_5 ((uint8_t)0x05)
|
||||
|
||||
#define ADC_Channel_13 ((uint8_t)0x0D)
|
||||
#define ADC_Channel_14 ((uint8_t)0x0E)
|
||||
#define ADC_Channel_15 ((uint8_t)0x0F)
|
||||
#define ADC_Channel_16 ((uint8_t)0x10)
|
||||
#define ADC_Channel_17 ((uint8_t)0x11)
|
||||
#define ADC_Channel_18 ((uint8_t)0x12)
|
||||
#define ADC_Channel_19 ((uint8_t)0x13)
|
||||
#define ADC_Channel_20 ((uint8_t)0x14)
|
||||
#define ADC_Channel_21 ((uint8_t)0x15)
|
||||
#define ADC_Channel_22 ((uint8_t)0x16)
|
||||
#define ADC_Channel_23 ((uint8_t)0x17)
|
||||
#define ADC_Channel_24 ((uint8_t)0x18)
|
||||
#define ADC_Channel_25 ((uint8_t)0x19)
|
||||
|
||||
#define ADC_Channel_27 ((uint8_t)0x1B)
|
||||
#define ADC_Channel_28 ((uint8_t)0x1C)
|
||||
#define ADC_Channel_29 ((uint8_t)0x1D)
|
||||
#define ADC_Channel_30 ((uint8_t)0x1E)
|
||||
#define ADC_Channel_31 ((uint8_t)0x1F)
|
||||
|
||||
#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16)
|
||||
#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_17)
|
||||
|
||||
#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0) || ((CHANNEL) == ADC_Channel_1) || \
|
||||
((CHANNEL) == ADC_Channel_2) || ((CHANNEL) == ADC_Channel_3) || \
|
||||
((CHANNEL) == ADC_Channel_4) || ((CHANNEL) == ADC_Channel_5) || \
|
||||
((CHANNEL) == ADC_Channel_6) || ((CHANNEL) == ADC_Channel_7) || \
|
||||
((CHANNEL) == ADC_Channel_8) || ((CHANNEL) == ADC_Channel_9) || \
|
||||
((CHANNEL) == ADC_Channel_10) || ((CHANNEL) == ADC_Channel_11) || \
|
||||
((CHANNEL) == ADC_Channel_12) || ((CHANNEL) == ADC_Channel_13) || \
|
||||
((CHANNEL) == ADC_Channel_14) || ((CHANNEL) == ADC_Channel_15) || \
|
||||
((CHANNEL) == ADC_Channel_16) || ((CHANNEL) == ADC_Channel_17) || \
|
||||
((CHANNEL) == ADC_Channel_18) || ((CHANNEL) == ADC_Channel_19) || \
|
||||
((CHANNEL) == ADC_Channel_20) || ((CHANNEL) == ADC_Channel_21) || \
|
||||
((CHANNEL) == ADC_Channel_22) || ((CHANNEL) == ADC_Channel_23) || \
|
||||
((CHANNEL) == ADC_Channel_24) || ((CHANNEL) == ADC_Channel_25) || \
|
||||
((CHANNEL) == ADC_Channel_27) || ((CHANNEL) == ADC_Channel_28) || \
|
||||
((CHANNEL) == ADC_Channel_29) || ((CHANNEL) == ADC_Channel_30) || \
|
||||
((CHANNEL) == ADC_Channel_31))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_sampling_times
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define ADC_SampleTime_4Cycles ((uint8_t)0x00)
|
||||
#define ADC_SampleTime_9Cycles ((uint8_t)0x01)
|
||||
#define ADC_SampleTime_16Cycles ((uint8_t)0x02)
|
||||
#define ADC_SampleTime_24Cycles ((uint8_t)0x03)
|
||||
#define ADC_SampleTime_48Cycles ((uint8_t)0x04)
|
||||
#define ADC_SampleTime_96Cycles ((uint8_t)0x05)
|
||||
#define ADC_SampleTime_192Cycles ((uint8_t)0x06)
|
||||
#define ADC_SampleTime_384Cycles ((uint8_t)0x07)
|
||||
|
||||
#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_4Cycles) || \
|
||||
((TIME) == ADC_SampleTime_9Cycles) || \
|
||||
((TIME) == ADC_SampleTime_16Cycles) || \
|
||||
((TIME) == ADC_SampleTime_24Cycles) || \
|
||||
((TIME) == ADC_SampleTime_48Cycles) || \
|
||||
((TIME) == ADC_SampleTime_96Cycles) || \
|
||||
((TIME) == ADC_SampleTime_192Cycles) || \
|
||||
((TIME) == ADC_SampleTime_384Cycles))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_Delay_length
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define ADC_DelayLength_None ((uint8_t)0x00)
|
||||
#define ADC_DelayLength_Freeze ((uint8_t)0x10)
|
||||
#define ADC_DelayLength_7Cycles ((uint8_t)0x20)
|
||||
#define ADC_DelayLength_15Cycles ((uint8_t)0x30)
|
||||
#define ADC_DelayLength_31Cycles ((uint8_t)0x40)
|
||||
#define ADC_DelayLength_63Cycles ((uint8_t)0x50)
|
||||
#define ADC_DelayLength_127Cycles ((uint8_t)0x60)
|
||||
#define ADC_DelayLength_255Cycles ((uint8_t)0x70)
|
||||
|
||||
#define IS_ADC_DELAY_LENGTH(LENGTH) (((LENGTH) == ADC_DelayLength_None) || \
|
||||
((LENGTH) == ADC_DelayLength_Freeze) || \
|
||||
((LENGTH) == ADC_DelayLength_7Cycles) || \
|
||||
((LENGTH) == ADC_DelayLength_15Cycles) || \
|
||||
((LENGTH) == ADC_DelayLength_31Cycles) || \
|
||||
((LENGTH) == ADC_DelayLength_63Cycles) || \
|
||||
((LENGTH) == ADC_DelayLength_127Cycles) || \
|
||||
((LENGTH) == ADC_DelayLength_255Cycles))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_external_trigger_edge_for_injected_channels_conversion
|
||||
* @{
|
||||
*/
|
||||
#define ADC_ExternalTrigInjecConvEdge_None ((uint32_t)0x00000000)
|
||||
#define ADC_ExternalTrigInjecConvEdge_Rising ((uint32_t)0x00100000)
|
||||
#define ADC_ExternalTrigInjecConvEdge_Falling ((uint32_t)0x00200000)
|
||||
#define ADC_ExternalTrigInjecConvEdge_RisingFalling ((uint32_t)0x00300000)
|
||||
|
||||
#define IS_ADC_EXT_INJEC_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigInjecConvEdge_None) || \
|
||||
((EDGE) == ADC_ExternalTrigInjecConvEdge_Rising) || \
|
||||
((EDGE) == ADC_ExternalTrigInjecConvEdge_Falling) || \
|
||||
((EDGE) == ADC_ExternalTrigInjecConvEdge_RisingFalling))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup ADC_external_trigger_sources_for_injected_channels_conversion
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/* TIM2 */
|
||||
#define ADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)0x00020000)
|
||||
#define ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00030000)
|
||||
|
||||
/* TIM3 */
|
||||
#define ADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)0x00040000)
|
||||
|
||||
/* TIM4 */
|
||||
#define ADC_ExternalTrigInjecConv_T4_TRGO ((uint32_t)0x00050000)
|
||||
#define ADC_ExternalTrigInjecConv_T4_CC1 ((uint32_t)0x00060000)
|
||||
#define ADC_ExternalTrigInjecConv_T4_CC2 ((uint32_t)0x00070000)
|
||||
#define ADC_ExternalTrigInjecConv_T4_CC3 ((uint32_t)0x00080000)
|
||||
|
||||
/* TIM7 */
|
||||
#define ADC_ExternalTrigInjecConv_T7_TRGO ((uint32_t)0x000A0000)
|
||||
|
||||
/* TIM9 */
|
||||
#define ADC_ExternalTrigInjecConv_T9_CC1 ((uint32_t)0x00000000)
|
||||
#define ADC_ExternalTrigInjecConv_T9_TRGO ((uint32_t)0x00010000)
|
||||
|
||||
/* TIM10 */
|
||||
#define ADC_ExternalTrigInjecConv_T10_CC1 ((uint32_t)0x00090000)
|
||||
|
||||
/* EXTI */
|
||||
#define ADC_ExternalTrigInjecConv_Ext_IT15 ((uint32_t)0x000F0000)
|
||||
|
||||
#define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConv_T9_CC1) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConv_T9_TRGO) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConv_T2_TRGO) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConv_T2_CC1) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC4) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConv_T4_TRGO) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC1) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC2) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC3) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConv_T10_CC1) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConv_T7_TRGO) || \
|
||||
((INJTRIG) == ADC_ExternalTrigInjecConv_Ext_IT15))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_injected_channel_selection
|
||||
* @{
|
||||
*/
|
||||
#define ADC_InjectedChannel_1 ((uint8_t)0x18)
|
||||
#define ADC_InjectedChannel_2 ((uint8_t)0x1C)
|
||||
#define ADC_InjectedChannel_3 ((uint8_t)0x20)
|
||||
#define ADC_InjectedChannel_4 ((uint8_t)0x24)
|
||||
|
||||
#define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \
|
||||
((CHANNEL) == ADC_InjectedChannel_2) || \
|
||||
((CHANNEL) == ADC_InjectedChannel_3) || \
|
||||
((CHANNEL) == ADC_InjectedChannel_4))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_analog_watchdog_selection
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200)
|
||||
#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200)
|
||||
#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200)
|
||||
#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000)
|
||||
#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000)
|
||||
#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000)
|
||||
#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000)
|
||||
|
||||
#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \
|
||||
((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) || \
|
||||
((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \
|
||||
((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable) || \
|
||||
((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) || \
|
||||
((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \
|
||||
((WATCHDOG) == ADC_AnalogWatchdog_None))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_interrupts_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define ADC_IT_AWD ((uint16_t)0x0106)
|
||||
#define ADC_IT_EOC ((uint16_t)0x0205)
|
||||
#define ADC_IT_JEOC ((uint16_t)0x0407)
|
||||
#define ADC_IT_OVR ((uint16_t)0x201A)
|
||||
|
||||
#define IS_ADC_IT(IT) (((IT) == ADC_IT_AWD) || ((IT) == ADC_IT_EOC) || \
|
||||
((IT) == ADC_IT_JEOC)|| ((IT) == ADC_IT_OVR))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_flags_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define ADC_FLAG_AWD ((uint16_t)0x0001)
|
||||
#define ADC_FLAG_EOC ((uint16_t)0x0002)
|
||||
#define ADC_FLAG_JEOC ((uint16_t)0x0004)
|
||||
#define ADC_FLAG_JSTRT ((uint16_t)0x0008)
|
||||
#define ADC_FLAG_STRT ((uint16_t)0x0010)
|
||||
#define ADC_FLAG_OVR ((uint16_t)0x0020)
|
||||
#define ADC_FLAG_ADONS ((uint16_t)0x0040)
|
||||
#define ADC_FLAG_RCNR ((uint16_t)0x0100)
|
||||
#define ADC_FLAG_JCNR ((uint16_t)0x0200)
|
||||
|
||||
#define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFFC0) == 0x00) && ((FLAG) != 0x00))
|
||||
|
||||
#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_AWD) || ((FLAG) == ADC_FLAG_EOC) || \
|
||||
((FLAG) == ADC_FLAG_JEOC) || ((FLAG)== ADC_FLAG_JSTRT) || \
|
||||
((FLAG) == ADC_FLAG_STRT) || ((FLAG)== ADC_FLAG_OVR) || \
|
||||
((FLAG) == ADC_FLAG_ADONS) || ((FLAG)== ADC_FLAG_RCNR) || \
|
||||
((FLAG) == ADC_FLAG_JCNR))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_thresholds
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_injected_offset
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_injected_length
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_injected_rank
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_regular_length
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 1) && ((LENGTH) <= 28))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_regular_rank
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 1) && ((RANK) <= 28))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_regular_discontinuous_mode_number
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup ADC_Bank_Selection
|
||||
* @{
|
||||
*/
|
||||
#define ADC_Bank_A ((uint8_t)0x00)
|
||||
#define ADC_Bank_B ((uint8_t)0x01)
|
||||
#define IS_ADC_BANK(BANK) (((BANK) == ADC_Bank_A) || ((BANK) == ADC_Bank_B))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
|
||||
/* Function used to set the ADC configuration to the default reset state *****/
|
||||
void ADC_DeInit(ADC_TypeDef* ADCx);
|
||||
|
||||
/* Initialization and Configuration functions *********************************/
|
||||
void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct);
|
||||
void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct);
|
||||
void ADC_CommonInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct);
|
||||
void ADC_CommonStructInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct);
|
||||
void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
void ADC_BankSelection(ADC_TypeDef* ADCx, uint8_t ADC_Bank);
|
||||
|
||||
/* Power saving functions *****************************************************/
|
||||
void ADC_PowerDownCmd(ADC_TypeDef* ADCx, uint32_t ADC_PowerDown, FunctionalState NewState);
|
||||
void ADC_DelaySelectionConfig(ADC_TypeDef* ADCx, uint8_t ADC_DelayLength);
|
||||
|
||||
/* Analog Watchdog configuration functions ************************************/
|
||||
void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog);
|
||||
void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,uint16_t LowThreshold);
|
||||
void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel);
|
||||
|
||||
/* Temperature Sensor & Vrefint (Voltage Reference internal) management function */
|
||||
void ADC_TempSensorVrefintCmd(FunctionalState NewState);
|
||||
|
||||
/* Regular Channels Configuration functions ***********************************/
|
||||
void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
|
||||
void ADC_SoftwareStartConv(ADC_TypeDef* ADCx);
|
||||
FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx);
|
||||
void ADC_EOCOnEachRegularChannelCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
void ADC_ContinuousModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number);
|
||||
void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx);
|
||||
|
||||
/* Regular Channels DMA Configuration functions *******************************/
|
||||
void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
void ADC_DMARequestAfterLastTransferCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
|
||||
/* Injected channels Configuration functions **********************************/
|
||||
void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
|
||||
void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length);
|
||||
void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset);
|
||||
void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv);
|
||||
void ADC_ExternalTrigInjectedConvEdgeConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConvEdge);
|
||||
void ADC_SoftwareStartInjectedConv(ADC_TypeDef* ADCx);
|
||||
FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx);
|
||||
void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
|
||||
uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel);
|
||||
|
||||
/* Interrupts and flags management functions **********************************/
|
||||
void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState);
|
||||
FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint16_t ADC_FLAG);
|
||||
void ADC_ClearFlag(ADC_TypeDef* ADCx, uint16_t ADC_FLAG);
|
||||
ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT);
|
||||
void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__STM32L1xx_ADC_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,236 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32l1xx_aes.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.1
|
||||
* @date 05-March-2012
|
||||
* @brief This file contains all the functions prototypes for the AES firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32L1xx_AES_H
|
||||
#define __STM32L1xx_AES_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32l1xx.h"
|
||||
|
||||
/** @addtogroup STM32L1xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup AES
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief AES Init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t AES_Operation; /*!< Specifies the AES mode of operation.
|
||||
This parameter can be a value of @ref AES_possible_Operation_modes */
|
||||
uint32_t AES_Chaining; /*!< Specifies the AES Chaining modes: ECB, CBC or CTR.
|
||||
This parameter can be a value of @ref AES_possible_chaining_modes */
|
||||
uint32_t AES_DataType; /*!< Specifies the AES data swapping: 32-bit, 16-bit, 8-bit or 1-bit.
|
||||
This parameter can be a value of @ref AES_Data_Types */
|
||||
}AES_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief AES Key(s) structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t AES_Key0; /*!< Key[31:0] */
|
||||
uint32_t AES_Key1; /*!< Key[63:32] */
|
||||
uint32_t AES_Key2; /*!< Key[95:64] */
|
||||
uint32_t AES_Key3; /*!< Key[127:96] */
|
||||
}AES_KeyInitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief AES Initialization Vectors (IV) structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t AES_IV0; /*!< Init Vector IV[31:0] */
|
||||
uint32_t AES_IV1; /*!< Init Vector IV[63:32] */
|
||||
uint32_t AES_IV2; /*!< Init Vector IV[95:64] */
|
||||
uint32_t AES_IV3; /*!< Init Vector IV[127:96] */
|
||||
}AES_IVInitTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup AES_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup AES_possible_Operation_modes
|
||||
* @{
|
||||
*/
|
||||
#define AES_Operation_Encryp ((uint32_t)0x00000000) /*!< AES in Encryption mode */
|
||||
#define AES_Operation_KeyDeriv AES_CR_MODE_0 /*!< AES in Key Derivation mode */
|
||||
#define AES_Operation_Decryp AES_CR_MODE_1 /*!< AES in Decryption mode */
|
||||
#define AES_Operation_KeyDerivAndDecryp AES_CR_MODE /*!< AES in Key Derivation and Decryption mode */
|
||||
|
||||
#define IS_AES_MODE(OPERATION) (((OPERATION) == AES_Operation_Encryp) || \
|
||||
((OPERATION) == AES_Operation_KeyDeriv) || \
|
||||
((OPERATION) == AES_Operation_Decryp) || \
|
||||
((OPERATION) == AES_Operation_KeyDerivAndDecryp))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup AES_possible_chaining_modes
|
||||
* @{
|
||||
*/
|
||||
#define AES_Chaining_ECB ((uint32_t)0x00000000) /*!< AES in ECB chaining mode */
|
||||
#define AES_Chaining_CBC AES_CR_CHMOD_0 /*!< AES in CBC chaining mode */
|
||||
#define AES_Chaining_CTR AES_CR_CHMOD_1 /*!< AES in CTR chaining mode */
|
||||
|
||||
#define IS_AES_CHAINING(CHAINING) (((CHAINING) == AES_Chaining_ECB) || \
|
||||
((CHAINING) == AES_Chaining_CBC) || \
|
||||
((CHAINING) == AES_Chaining_CTR))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup AES_Data_Types
|
||||
* @{
|
||||
*/
|
||||
#define AES_DataType_32b ((uint32_t)0x00000000) /*!< 32-bit data. No swapping */
|
||||
#define AES_DataType_16b AES_CR_DATATYPE_0 /*!< 16-bit data. Each half word is swapped */
|
||||
#define AES_DataType_8b AES_CR_DATATYPE_1 /*!< 8-bit data. All bytes are swapped */
|
||||
#define AES_DataType_1b AES_CR_DATATYPE /*!< 1-bit data. In the word all bits are swapped */
|
||||
|
||||
#define IS_AES_DATATYPE(DATATYPE) (((DATATYPE) == AES_DataType_32b) || \
|
||||
((DATATYPE) == AES_DataType_16b)|| \
|
||||
((DATATYPE) == AES_DataType_8b) || \
|
||||
((DATATYPE) == AES_DataType_1b))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup AES_Flags
|
||||
* @{
|
||||
*/
|
||||
#define AES_FLAG_CCF AES_SR_CCF /*!< Computation Complete Flag */
|
||||
#define AES_FLAG_RDERR AES_SR_RDERR /*!< Read Error Flag */
|
||||
#define AES_FLAG_WRERR AES_SR_WRERR /*!< Write Error Flag */
|
||||
|
||||
#define IS_AES_FLAG(FLAG) (((FLAG) == AES_FLAG_CCF) || \
|
||||
((FLAG) == AES_FLAG_RDERR) || \
|
||||
((FLAG) == AES_FLAG_WRERR))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup AES_Interrupts
|
||||
* @{
|
||||
*/
|
||||
#define AES_IT_CC AES_CR_CCIE /*!< Computation Complete interrupt */
|
||||
#define AES_IT_ERR AES_CR_ERRIE /*!< Error interrupt */
|
||||
|
||||
#define IS_AES_IT(IT) ((((IT) & (uint32_t)0xFFFFF9FF) == 0x00) && ((IT) != 0x00))
|
||||
#define IS_AES_GET_IT(IT) (((IT) == AES_IT_CC) || ((IT) == AES_IT_ERR))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup AES_DMA_Transfer_modes
|
||||
* @{
|
||||
*/
|
||||
#define AES_DMATransfer_In AES_CR_DMAINEN /*!< DMA requests enabled for input transfer phase */
|
||||
#define AES_DMATransfer_Out AES_CR_DMAOUTEN /*!< DMA requests enabled for input transfer phase */
|
||||
#define AES_DMATransfer_InOut (AES_CR_DMAINEN | AES_CR_DMAOUTEN) /*!< DMA requests enabled for both input and output phases */
|
||||
|
||||
#define IS_AES_DMA_TRANSFER(TRANSFER) (((TRANSFER) == AES_DMATransfer_In) || \
|
||||
((TRANSFER) == AES_DMATransfer_Out) || \
|
||||
((TRANSFER) == AES_DMATransfer_InOut))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
|
||||
/* Initialization and configuration functions *********************************/
|
||||
void AES_DeInit(void);
|
||||
void AES_Init(AES_InitTypeDef* AES_InitStruct);
|
||||
void AES_KeyInit(AES_KeyInitTypeDef* AES_KeyInitStruct);
|
||||
void AES_IVInit(AES_IVInitTypeDef* AES_IVInitStruct);
|
||||
void AES_Cmd(FunctionalState NewState);
|
||||
|
||||
/* Structures initialization functions ****************************************/
|
||||
void AES_StructInit(AES_InitTypeDef* AES_InitStruct);
|
||||
void AES_KeyStructInit(AES_KeyInitTypeDef* AES_KeyInitStruct);
|
||||
void AES_IVStructInit(AES_IVInitTypeDef* AES_IVInitStruct);
|
||||
|
||||
/* AES Read and Write functions **********************************************/
|
||||
void AES_WriteSubData(uint32_t Data);
|
||||
uint32_t AES_ReadSubData(void);
|
||||
void AES_ReadKey(AES_KeyInitTypeDef* AES_KeyInitStruct);
|
||||
void AES_ReadIV(AES_IVInitTypeDef* AES_IVInitStruct);
|
||||
|
||||
/* DMA transfers management function ******************************************/
|
||||
void AES_DMAConfig(uint32_t AES_DMATransfer, FunctionalState NewState);
|
||||
|
||||
/* Interrupts and flags management functions **********************************/
|
||||
void AES_ITConfig(uint32_t AES_IT, FunctionalState NewState);
|
||||
FlagStatus AES_GetFlagStatus(uint32_t AES_FLAG);
|
||||
void AES_ClearFlag(uint32_t AES_FLAG);
|
||||
ITStatus AES_GetITStatus(uint32_t AES_IT);
|
||||
void AES_ClearITPendingBit(uint32_t AES_IT);
|
||||
|
||||
/* High Level AES functions **************************************************/
|
||||
ErrorStatus AES_ECB_Encrypt(uint8_t* Key, uint8_t* Input, uint32_t Ilength, uint8_t* Output);
|
||||
ErrorStatus AES_ECB_Decrypt(uint8_t* Key, uint8_t* Input, uint32_t Ilength, uint8_t* Output);
|
||||
ErrorStatus AES_CBC_Encrypt(uint8_t* Key, uint8_t InitVectors[16], uint8_t* Input, uint32_t Ilength, uint8_t* Output);
|
||||
ErrorStatus AES_CBC_Decrypt(uint8_t* Key, uint8_t InitVectors[16], uint8_t* Input, uint32_t Ilength, uint8_t* Output);
|
||||
ErrorStatus AES_CTR_Encrypt(uint8_t* Key, uint8_t InitVectors[16], uint8_t* Input, uint32_t Ilength, uint8_t* Output);
|
||||
ErrorStatus AES_CTR_Decrypt(uint8_t* Key, uint8_t InitVectors[16], uint8_t* Input, uint32_t Ilength, uint8_t* Output);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__STM32L1xx_AES_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,187 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32l1xx_comp.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.1
|
||||
* @date 05-March-2012
|
||||
* @brief This file contains all the functions prototypes for the COMP firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32L1xx_COMP_H
|
||||
#define __STM32L1xx_COMP_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32l1xx.h"
|
||||
|
||||
/** @addtogroup STM32L1xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup COMP
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief COMP Init structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t COMP_Speed; /*!< Defines the speed of comparator 2.
|
||||
This parameter can be a value of @ref COMP_Speed */
|
||||
uint32_t COMP_InvertingInput; /*!< Selects the inverting input of the comparator 2.
|
||||
This parameter can be a value of @ref COMP_InvertingInput */
|
||||
uint32_t COMP_OutputSelect; /*!< Selects the output redirection of the comparator 2.
|
||||
This parameter can be a value of @ref COMP_OutputSelect */
|
||||
|
||||
}COMP_InitTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup COMP_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define COMP_OutputLevel_High ((uint32_t)0x00000001)
|
||||
#define COMP_OutputLevel_Low ((uint32_t)0x00000000)
|
||||
|
||||
/** @defgroup COMP_Selection
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define COMP_Selection_COMP1 ((uint32_t)0x00000001)
|
||||
#define COMP_Selection_COMP2 ((uint32_t)0x00000002)
|
||||
|
||||
#define IS_COMP_ALL_PERIPH(PERIPH) (((PERIPH) == COMP_Selection_COMP1) || \
|
||||
((PERIPH) == COMP_Selection_COMP2))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_InvertingInput
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define COMP_InvertingInput_None ((uint32_t)0x00000000) /* COMP2 is disabled when this parameter is selected */
|
||||
#define COMP_InvertingInput_IO ((uint32_t)0x00040000)
|
||||
#define COMP_InvertingInput_VREFINT ((uint32_t)0x00080000)
|
||||
#define COMP_InvertingInput_3_4VREFINT ((uint32_t)0x000C0000)
|
||||
#define COMP_InvertingInput_1_2VREFINT ((uint32_t)0x00100000)
|
||||
#define COMP_InvertingInput_1_4VREFINT ((uint32_t)0x00140000)
|
||||
#define COMP_InvertingInput_DAC1 ((uint32_t)0x00180000)
|
||||
#define COMP_InvertingInput_DAC2 ((uint32_t)0x001C0000)
|
||||
|
||||
#define IS_COMP_INVERTING_INPUT(INPUT) (((INPUT) == COMP_InvertingInput_None) || \
|
||||
((INPUT) == COMP_InvertingInput_IO) || \
|
||||
((INPUT) == COMP_InvertingInput_VREFINT) || \
|
||||
((INPUT) == COMP_InvertingInput_3_4VREFINT) || \
|
||||
((INPUT) == COMP_InvertingInput_1_2VREFINT) || \
|
||||
((INPUT) == COMP_InvertingInput_1_4VREFINT) || \
|
||||
((INPUT) == COMP_InvertingInput_DAC1) || \
|
||||
((INPUT) == COMP_InvertingInput_DAC2))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_OutputSelect
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define COMP_OutputSelect_TIM2IC4 ((uint32_t)0x00000000)
|
||||
#define COMP_OutputSelect_TIM2OCREFCLR ((uint32_t)0x00200000)
|
||||
#define COMP_OutputSelect_TIM3IC4 ((uint32_t)0x00400000)
|
||||
#define COMP_OutputSelect_TIM3OCREFCLR ((uint32_t)0x00600000)
|
||||
#define COMP_OutputSelect_TIM4IC4 ((uint32_t)0x00800000)
|
||||
#define COMP_OutputSelect_TIM4OCREFCLR ((uint32_t)0x00A00000)
|
||||
#define COMP_OutputSelect_TIM10IC1 ((uint32_t)0x00C00000)
|
||||
#define COMP_OutputSelect_None ((uint32_t)0x00E00000)
|
||||
|
||||
#define IS_COMP_OUTPUT(OUTPUT) (((OUTPUT) == COMP_OutputSelect_TIM2IC4) || \
|
||||
((OUTPUT) == COMP_OutputSelect_TIM2OCREFCLR) || \
|
||||
((OUTPUT) == COMP_OutputSelect_TIM3IC4) || \
|
||||
((OUTPUT) == COMP_OutputSelect_TIM3OCREFCLR) || \
|
||||
((OUTPUT) == COMP_OutputSelect_TIM4IC4) || \
|
||||
((OUTPUT) == COMP_OutputSelect_TIM4OCREFCLR) || \
|
||||
((OUTPUT) == COMP_OutputSelect_TIM10IC1) || \
|
||||
((OUTPUT) == COMP_OutputSelect_None))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_Speed
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define COMP_Speed_Slow ((uint32_t)0x00000000)
|
||||
#define COMP_Speed_Fast ((uint32_t)0x00001000)
|
||||
|
||||
#define IS_COMP_SPEED(SPEED) (((SPEED) == COMP_Speed_Slow) || \
|
||||
((SPEED) == COMP_Speed_Fast))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
|
||||
/* Function used to set the COMP configuration to the default reset state ****/
|
||||
void COMP_DeInit(void);
|
||||
|
||||
/* Initialization and Configuration functions *********************************/
|
||||
void COMP_Init(COMP_InitTypeDef* COMP_InitStruct);
|
||||
void COMP_Cmd(FunctionalState NewState);
|
||||
uint8_t COMP_GetOutputLevel(uint32_t COMP_Selection);
|
||||
void COMP_SW1SwitchConfig(FunctionalState NewState);
|
||||
|
||||
/* Window mode control function ***********************************************/
|
||||
void COMP_WindowCmd(FunctionalState NewState);
|
||||
|
||||
/* Internal Reference Voltage (VREFINT) output function ***********************/
|
||||
void COMP_VrefintOutputCmd(FunctionalState NewState);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__STM32L1xx_COMP_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,83 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32l1xx_crc.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.1
|
||||
* @date 05-March-2012
|
||||
* @brief This file contains all the functions prototypes for the CRC firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32L1xx_CRC_H
|
||||
#define __STM32L1xx_CRC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32l1xx.h"
|
||||
|
||||
/** @addtogroup STM32L1xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup CRC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup CRC_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
|
||||
void CRC_ResetDR(void);
|
||||
uint32_t CRC_CalcCRC(uint32_t Data);
|
||||
uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength);
|
||||
uint32_t CRC_GetCRC(void);
|
||||
void CRC_SetIDRegister(uint8_t IDValue);
|
||||
uint8_t CRC_GetIDRegister(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32L1xx_CRC_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,305 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32l1xx_dac.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.1
|
||||
* @date 05-March-2012
|
||||
* @brief This file contains all the functions prototypes for the DAC firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32L1xx_DAC_H
|
||||
#define __STM32L1xx_DAC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32l1xx.h"
|
||||
|
||||
/** @addtogroup STM32L1xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DAC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief DAC Init structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel.
|
||||
This parameter can be a value of @ref DAC_trigger_selection */
|
||||
|
||||
uint32_t DAC_WaveGeneration; /*!< Specifies whether DAC channel noise waves or triangle waves
|
||||
are generated, or whether no wave is generated.
|
||||
This parameter can be a value of @ref DAC_wave_generation */
|
||||
|
||||
uint32_t DAC_LFSRUnmask_TriangleAmplitude; /*!< Specifies the LFSR mask for noise wave generation or
|
||||
the maximum amplitude triangle generation for the DAC channel.
|
||||
This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */
|
||||
|
||||
uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
|
||||
This parameter can be a value of @ref DAC_output_buffer */
|
||||
}DAC_InitTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DAC_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_trigger_selection
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DAC_Trigger_None ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register
|
||||
has been loaded, and not by external trigger */
|
||||
#define DAC_Trigger_T6_TRGO ((uint32_t)0x00000004) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_Trigger_T7_TRGO ((uint32_t)0x00000014) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_Trigger_T9_TRGO ((uint32_t)0x0000001C) /*!< TIM9 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_Trigger_T2_TRGO ((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_Trigger_T4_TRGO ((uint32_t)0x0000002C) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
|
||||
#define DAC_Trigger_Ext_IT9 ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
|
||||
#define DAC_Trigger_Software ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC channel */
|
||||
|
||||
#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \
|
||||
((TRIGGER) == DAC_Trigger_T6_TRGO) || \
|
||||
((TRIGGER) == DAC_Trigger_T7_TRGO) || \
|
||||
((TRIGGER) == DAC_Trigger_T9_TRGO) || \
|
||||
((TRIGGER) == DAC_Trigger_T2_TRGO) || \
|
||||
((TRIGGER) == DAC_Trigger_T4_TRGO) || \
|
||||
((TRIGGER) == DAC_Trigger_Ext_IT9) || \
|
||||
((TRIGGER) == DAC_Trigger_Software))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_wave_generation
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DAC_WaveGeneration_None ((uint32_t)0x00000000)
|
||||
#define DAC_WaveGeneration_Noise ((uint32_t)0x00000040)
|
||||
#define DAC_WaveGeneration_Triangle ((uint32_t)0x00000080)
|
||||
#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || \
|
||||
((WAVE) == DAC_WaveGeneration_Noise) || \
|
||||
((WAVE) == DAC_WaveGeneration_Triangle))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_lfsrunmask_triangleamplitude
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DAC_LFSRUnmask_Bit0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
|
||||
#define DAC_LFSRUnmask_Bits1_0 ((uint32_t)0x00000100) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
|
||||
#define DAC_LFSRUnmask_Bits2_0 ((uint32_t)0x00000200) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
|
||||
#define DAC_LFSRUnmask_Bits3_0 ((uint32_t)0x00000300) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
|
||||
#define DAC_LFSRUnmask_Bits4_0 ((uint32_t)0x00000400) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
|
||||
#define DAC_LFSRUnmask_Bits5_0 ((uint32_t)0x00000500) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
|
||||
#define DAC_LFSRUnmask_Bits6_0 ((uint32_t)0x00000600) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
|
||||
#define DAC_LFSRUnmask_Bits7_0 ((uint32_t)0x00000700) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
|
||||
#define DAC_LFSRUnmask_Bits8_0 ((uint32_t)0x00000800) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
|
||||
#define DAC_LFSRUnmask_Bits9_0 ((uint32_t)0x00000900) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
|
||||
#define DAC_LFSRUnmask_Bits10_0 ((uint32_t)0x00000A00) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
|
||||
#define DAC_LFSRUnmask_Bits11_0 ((uint32_t)0x00000B00) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
|
||||
#define DAC_TriangleAmplitude_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */
|
||||
#define DAC_TriangleAmplitude_3 ((uint32_t)0x00000100) /*!< Select max triangle amplitude of 3 */
|
||||
#define DAC_TriangleAmplitude_7 ((uint32_t)0x00000200) /*!< Select max triangle amplitude of 7 */
|
||||
#define DAC_TriangleAmplitude_15 ((uint32_t)0x00000300) /*!< Select max triangle amplitude of 15 */
|
||||
#define DAC_TriangleAmplitude_31 ((uint32_t)0x00000400) /*!< Select max triangle amplitude of 31 */
|
||||
#define DAC_TriangleAmplitude_63 ((uint32_t)0x00000500) /*!< Select max triangle amplitude of 63 */
|
||||
#define DAC_TriangleAmplitude_127 ((uint32_t)0x00000600) /*!< Select max triangle amplitude of 127 */
|
||||
#define DAC_TriangleAmplitude_255 ((uint32_t)0x00000700) /*!< Select max triangle amplitude of 255 */
|
||||
#define DAC_TriangleAmplitude_511 ((uint32_t)0x00000800) /*!< Select max triangle amplitude of 511 */
|
||||
#define DAC_TriangleAmplitude_1023 ((uint32_t)0x00000900) /*!< Select max triangle amplitude of 1023 */
|
||||
#define DAC_TriangleAmplitude_2047 ((uint32_t)0x00000A00) /*!< Select max triangle amplitude of 2047 */
|
||||
#define DAC_TriangleAmplitude_4095 ((uint32_t)0x00000B00) /*!< Select max triangle amplitude of 4095 */
|
||||
|
||||
#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || \
|
||||
((VALUE) == DAC_LFSRUnmask_Bits1_0) || \
|
||||
((VALUE) == DAC_LFSRUnmask_Bits2_0) || \
|
||||
((VALUE) == DAC_LFSRUnmask_Bits3_0) || \
|
||||
((VALUE) == DAC_LFSRUnmask_Bits4_0) || \
|
||||
((VALUE) == DAC_LFSRUnmask_Bits5_0) || \
|
||||
((VALUE) == DAC_LFSRUnmask_Bits6_0) || \
|
||||
((VALUE) == DAC_LFSRUnmask_Bits7_0) || \
|
||||
((VALUE) == DAC_LFSRUnmask_Bits8_0) || \
|
||||
((VALUE) == DAC_LFSRUnmask_Bits9_0) || \
|
||||
((VALUE) == DAC_LFSRUnmask_Bits10_0) || \
|
||||
((VALUE) == DAC_LFSRUnmask_Bits11_0) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_1) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_3) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_7) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_15) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_31) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_63) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_127) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_255) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_511) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_1023) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_2047) || \
|
||||
((VALUE) == DAC_TriangleAmplitude_4095))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_output_buffer
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DAC_OutputBuffer_Enable ((uint32_t)0x00000000)
|
||||
#define DAC_OutputBuffer_Disable ((uint32_t)0x00000002)
|
||||
#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \
|
||||
((STATE) == DAC_OutputBuffer_Disable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_Channel_selection
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DAC_Channel_1 ((uint32_t)0x00000000)
|
||||
#define DAC_Channel_2 ((uint32_t)0x00000010)
|
||||
#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \
|
||||
((CHANNEL) == DAC_Channel_2))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_data_alignment
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DAC_Align_12b_R ((uint32_t)0x00000000)
|
||||
#define DAC_Align_12b_L ((uint32_t)0x00000004)
|
||||
#define DAC_Align_8b_R ((uint32_t)0x00000008)
|
||||
#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \
|
||||
((ALIGN) == DAC_Align_12b_L) || \
|
||||
((ALIGN) == DAC_Align_8b_R))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_wave_generation
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DAC_Wave_Noise ((uint32_t)0x00000040)
|
||||
#define DAC_Wave_Triangle ((uint32_t)0x00000080)
|
||||
#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \
|
||||
((WAVE) == DAC_Wave_Triangle))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_data
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_interrupts_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DAC_IT_DMAUDR ((uint32_t)0x00002000)
|
||||
#define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup DAC_flags_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DAC_FLAG_DMAUDR ((uint32_t)0x00002000)
|
||||
|
||||
#define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
|
||||
/* Function used to set the DAC configuration to the default reset state *****/
|
||||
void DAC_DeInit(void);
|
||||
|
||||
/* DAC channels configuration: trigger, output buffer, data format functions */
|
||||
void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct);
|
||||
void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct);
|
||||
void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState);
|
||||
void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState);
|
||||
void DAC_DualSoftwareTriggerCmd(FunctionalState NewState);
|
||||
void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState);
|
||||
void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data);
|
||||
void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data);
|
||||
void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1);
|
||||
uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel);
|
||||
|
||||
/* DMA management functions ***************************************************/
|
||||
void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState);
|
||||
|
||||
/* Interrupts and flags management functions **********************************/
|
||||
void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState);
|
||||
FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG);
|
||||
void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG);
|
||||
ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT);
|
||||
void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__STM32L1xx_DAC_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,105 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32l1xx_dbgmcu.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.1
|
||||
* @date 05-March-2012
|
||||
* @brief This file contains all the functions prototypes for the DBGMCU
|
||||
* firmware library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32L1xx_DBGMCU_H
|
||||
#define __STM32L1xx_DBGMCU_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32l1xx.h"
|
||||
|
||||
/** @addtogroup STM32L1xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DBGMCU
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DBGMCU_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DBGMCU_SLEEP ((uint32_t)0x00000001)
|
||||
#define DBGMCU_STOP ((uint32_t)0x00000002)
|
||||
#define DBGMCU_STANDBY ((uint32_t)0x00000004)
|
||||
#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFF8) == 0x00) && ((PERIPH) != 0x00))
|
||||
|
||||
#define DBGMCU_TIM2_STOP ((uint32_t)0x00000001)
|
||||
#define DBGMCU_TIM3_STOP ((uint32_t)0x00000002)
|
||||
#define DBGMCU_TIM4_STOP ((uint32_t)0x00000004)
|
||||
#define DBGMCU_TIM5_STOP ((uint32_t)0x00000008)
|
||||
#define DBGMCU_TIM6_STOP ((uint32_t)0x00000010)
|
||||
#define DBGMCU_TIM7_STOP ((uint32_t)0x00000020)
|
||||
#define DBGMCU_RTC_STOP ((uint32_t)0x00000400)
|
||||
#define DBGMCU_WWDG_STOP ((uint32_t)0x00000800)
|
||||
#define DBGMCU_IWDG_STOP ((uint32_t)0x00001000)
|
||||
#define DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)
|
||||
#define DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000)
|
||||
#define IS_DBGMCU_APB1PERIPH(PERIPH) ((((PERIPH) & 0xFF9FE3C0) == 0x00) && ((PERIPH) != 0x00))
|
||||
|
||||
#define DBGMCU_TIM9_STOP ((uint32_t)0x00000004)
|
||||
#define DBGMCU_TIM10_STOP ((uint32_t)0x00000008)
|
||||
#define DBGMCU_TIM11_STOP ((uint32_t)0x00000010)
|
||||
#define IS_DBGMCU_APB2PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFE3) == 0x00) && ((PERIPH) != 0x00))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
|
||||
uint32_t DBGMCU_GetREVID(void);
|
||||
uint32_t DBGMCU_GetDEVID(void);
|
||||
void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState);
|
||||
void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState);
|
||||
void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32L1xx_DBGMCU_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,435 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32l1xx_dma.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.1
|
||||
* @date 05-March-2012
|
||||
* @brief This file contains all the functions prototypes for the DMA firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32L1xx_DMA_H
|
||||
#define __STM32L1xx_DMA_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32l1xx.h"
|
||||
|
||||
/** @addtogroup STM32L1xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup DMA
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief DMA Init structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Channelx. */
|
||||
|
||||
uint32_t DMA_MemoryBaseAddr; /*!< Specifies the memory base address for DMAy Channelx. */
|
||||
|
||||
uint32_t DMA_DIR; /*!< Specifies if the peripheral is the source or destination.
|
||||
This parameter can be a value of @ref DMA_data_transfer_direction */
|
||||
|
||||
uint32_t DMA_BufferSize; /*!< Specifies the buffer size, in data unit, of the specified Channel.
|
||||
The data unit is equal to the configuration set in DMA_PeripheralDataSize
|
||||
or DMA_MemoryDataSize members depending in the transfer direction. */
|
||||
|
||||
uint32_t DMA_PeripheralInc; /*!< Specifies whether the Peripheral address register is incremented or not.
|
||||
This parameter can be a value of @ref DMA_peripheral_incremented_mode */
|
||||
|
||||
uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register is incremented or not.
|
||||
This parameter can be a value of @ref DMA_memory_incremented_mode */
|
||||
|
||||
uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width.
|
||||
This parameter can be a value of @ref DMA_peripheral_data_size */
|
||||
|
||||
uint32_t DMA_MemoryDataSize; /*!< Specifies the Memory data width.
|
||||
This parameter can be a value of @ref DMA_memory_data_size */
|
||||
|
||||
uint32_t DMA_Mode; /*!< Specifies the operation mode of the DMAy Channelx.
|
||||
This parameter can be a value of @ref DMA_circular_normal_mode
|
||||
@note: The circular buffer mode cannot be used if the memory-to-memory
|
||||
data transfer is configured on the selected Channel */
|
||||
|
||||
uint32_t DMA_Priority; /*!< Specifies the software priority for the DMAy Channelx.
|
||||
This parameter can be a value of @ref DMA_priority_level */
|
||||
|
||||
uint32_t DMA_M2M; /*!< Specifies if the DMAy Channelx will be used in memory-to-memory transfer.
|
||||
This parameter can be a value of @ref DMA_memory_to_memory */
|
||||
}DMA_InitTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DMA_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Channel1) || \
|
||||
((PERIPH) == DMA1_Channel2) || \
|
||||
((PERIPH) == DMA1_Channel3) || \
|
||||
((PERIPH) == DMA1_Channel4) || \
|
||||
((PERIPH) == DMA1_Channel5) || \
|
||||
((PERIPH) == DMA1_Channel6) || \
|
||||
((PERIPH) == DMA1_Channel7) || \
|
||||
((PERIPH) == DMA2_Channel1) || \
|
||||
((PERIPH) == DMA2_Channel2) || \
|
||||
((PERIPH) == DMA2_Channel3) || \
|
||||
((PERIPH) == DMA2_Channel4) || \
|
||||
((PERIPH) == DMA2_Channel5))
|
||||
|
||||
/** @defgroup DMA_data_transfer_direction
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DMA_DIR_PeripheralDST ((uint32_t)0x00000010)
|
||||
#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000)
|
||||
#define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralDST) || \
|
||||
((DIR) == DMA_DIR_PeripheralSRC))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_peripheral_incremented_mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DMA_PeripheralInc_Enable ((uint32_t)0x00000040)
|
||||
#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000)
|
||||
#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \
|
||||
((STATE) == DMA_PeripheralInc_Disable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_memory_incremented_mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DMA_MemoryInc_Enable ((uint32_t)0x00000080)
|
||||
#define DMA_MemoryInc_Disable ((uint32_t)0x00000000)
|
||||
#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || \
|
||||
((STATE) == DMA_MemoryInc_Disable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_peripheral_data_size
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000)
|
||||
#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100)
|
||||
#define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200)
|
||||
#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \
|
||||
((SIZE) == DMA_PeripheralDataSize_HalfWord) || \
|
||||
((SIZE) == DMA_PeripheralDataSize_Word))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_memory_data_size
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000)
|
||||
#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400)
|
||||
#define DMA_MemoryDataSize_Word ((uint32_t)0x00000800)
|
||||
#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \
|
||||
((SIZE) == DMA_MemoryDataSize_HalfWord) || \
|
||||
((SIZE) == DMA_MemoryDataSize_Word))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_circular_normal_mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DMA_Mode_Circular ((uint32_t)0x00000020)
|
||||
#define DMA_Mode_Normal ((uint32_t)0x00000000)
|
||||
#define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Circular) || ((MODE) == DMA_Mode_Normal))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_priority_level
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DMA_Priority_VeryHigh ((uint32_t)0x00003000)
|
||||
#define DMA_Priority_High ((uint32_t)0x00002000)
|
||||
#define DMA_Priority_Medium ((uint32_t)0x00001000)
|
||||
#define DMA_Priority_Low ((uint32_t)0x00000000)
|
||||
#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \
|
||||
((PRIORITY) == DMA_Priority_High) || \
|
||||
((PRIORITY) == DMA_Priority_Medium) || \
|
||||
((PRIORITY) == DMA_Priority_Low))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_memory_to_memory
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DMA_M2M_Enable ((uint32_t)0x00004000)
|
||||
#define DMA_M2M_Disable ((uint32_t)0x00000000)
|
||||
#define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Enable) || ((STATE) == DMA_M2M_Disable))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_interrupts_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define DMA_IT_TC ((uint32_t)0x00000002)
|
||||
#define DMA_IT_HT ((uint32_t)0x00000004)
|
||||
#define DMA_IT_TE ((uint32_t)0x00000008)
|
||||
#define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00))
|
||||
|
||||
#define DMA1_IT_GL1 ((uint32_t)0x00000001)
|
||||
#define DMA1_IT_TC1 ((uint32_t)0x00000002)
|
||||
#define DMA1_IT_HT1 ((uint32_t)0x00000004)
|
||||
#define DMA1_IT_TE1 ((uint32_t)0x00000008)
|
||||
#define DMA1_IT_GL2 ((uint32_t)0x00000010)
|
||||
#define DMA1_IT_TC2 ((uint32_t)0x00000020)
|
||||
#define DMA1_IT_HT2 ((uint32_t)0x00000040)
|
||||
#define DMA1_IT_TE2 ((uint32_t)0x00000080)
|
||||
#define DMA1_IT_GL3 ((uint32_t)0x00000100)
|
||||
#define DMA1_IT_TC3 ((uint32_t)0x00000200)
|
||||
#define DMA1_IT_HT3 ((uint32_t)0x00000400)
|
||||
#define DMA1_IT_TE3 ((uint32_t)0x00000800)
|
||||
#define DMA1_IT_GL4 ((uint32_t)0x00001000)
|
||||
#define DMA1_IT_TC4 ((uint32_t)0x00002000)
|
||||
#define DMA1_IT_HT4 ((uint32_t)0x00004000)
|
||||
#define DMA1_IT_TE4 ((uint32_t)0x00008000)
|
||||
#define DMA1_IT_GL5 ((uint32_t)0x00010000)
|
||||
#define DMA1_IT_TC5 ((uint32_t)0x00020000)
|
||||
#define DMA1_IT_HT5 ((uint32_t)0x00040000)
|
||||
#define DMA1_IT_TE5 ((uint32_t)0x00080000)
|
||||
#define DMA1_IT_GL6 ((uint32_t)0x00100000)
|
||||
#define DMA1_IT_TC6 ((uint32_t)0x00200000)
|
||||
#define DMA1_IT_HT6 ((uint32_t)0x00400000)
|
||||
#define DMA1_IT_TE6 ((uint32_t)0x00800000)
|
||||
#define DMA1_IT_GL7 ((uint32_t)0x01000000)
|
||||
#define DMA1_IT_TC7 ((uint32_t)0x02000000)
|
||||
#define DMA1_IT_HT7 ((uint32_t)0x04000000)
|
||||
#define DMA1_IT_TE7 ((uint32_t)0x08000000)
|
||||
|
||||
#define DMA2_IT_GL1 ((uint32_t)0x10000001)
|
||||
#define DMA2_IT_TC1 ((uint32_t)0x10000002)
|
||||
#define DMA2_IT_HT1 ((uint32_t)0x10000004)
|
||||
#define DMA2_IT_TE1 ((uint32_t)0x10000008)
|
||||
#define DMA2_IT_GL2 ((uint32_t)0x10000010)
|
||||
#define DMA2_IT_TC2 ((uint32_t)0x10000020)
|
||||
#define DMA2_IT_HT2 ((uint32_t)0x10000040)
|
||||
#define DMA2_IT_TE2 ((uint32_t)0x10000080)
|
||||
#define DMA2_IT_GL3 ((uint32_t)0x10000100)
|
||||
#define DMA2_IT_TC3 ((uint32_t)0x10000200)
|
||||
#define DMA2_IT_HT3 ((uint32_t)0x10000400)
|
||||
#define DMA2_IT_TE3 ((uint32_t)0x10000800)
|
||||
#define DMA2_IT_GL4 ((uint32_t)0x10001000)
|
||||
#define DMA2_IT_TC4 ((uint32_t)0x10002000)
|
||||
#define DMA2_IT_HT4 ((uint32_t)0x10004000)
|
||||
#define DMA2_IT_TE4 ((uint32_t)0x10008000)
|
||||
#define DMA2_IT_GL5 ((uint32_t)0x10010000)
|
||||
#define DMA2_IT_TC5 ((uint32_t)0x10020000)
|
||||
#define DMA2_IT_HT5 ((uint32_t)0x10040000)
|
||||
#define DMA2_IT_TE5 ((uint32_t)0x10080000)
|
||||
|
||||
#define IS_DMA_CLEAR_IT(IT) (((((IT) & 0xF0000000) == 0x00) || (((IT) & 0xEFF00000) == 0x00)) && ((IT) != 0x00))
|
||||
|
||||
#define IS_DMA_GET_IT(IT) (((IT) == DMA1_IT_GL1) || ((IT) == DMA1_IT_TC1) || \
|
||||
((IT) == DMA1_IT_HT1) || ((IT) == DMA1_IT_TE1) || \
|
||||
((IT) == DMA1_IT_GL2) || ((IT) == DMA1_IT_TC2) || \
|
||||
((IT) == DMA1_IT_HT2) || ((IT) == DMA1_IT_TE2) || \
|
||||
((IT) == DMA1_IT_GL3) || ((IT) == DMA1_IT_TC3) || \
|
||||
((IT) == DMA1_IT_HT3) || ((IT) == DMA1_IT_TE3) || \
|
||||
((IT) == DMA1_IT_GL4) || ((IT) == DMA1_IT_TC4) || \
|
||||
((IT) == DMA1_IT_HT4) || ((IT) == DMA1_IT_TE4) || \
|
||||
((IT) == DMA1_IT_GL5) || ((IT) == DMA1_IT_TC5) || \
|
||||
((IT) == DMA1_IT_HT5) || ((IT) == DMA1_IT_TE5) || \
|
||||
((IT) == DMA1_IT_GL6) || ((IT) == DMA1_IT_TC6) || \
|
||||
((IT) == DMA1_IT_HT6) || ((IT) == DMA1_IT_TE6) || \
|
||||
((IT) == DMA1_IT_GL7) || ((IT) == DMA1_IT_TC7) || \
|
||||
((IT) == DMA1_IT_HT7) || ((IT) == DMA1_IT_TE7) || \
|
||||
((IT) == DMA2_IT_GL1) || ((IT) == DMA2_IT_TC1) || \
|
||||
((IT) == DMA2_IT_HT1) || ((IT) == DMA2_IT_TE1) || \
|
||||
((IT) == DMA2_IT_GL2) || ((IT) == DMA2_IT_TC2) || \
|
||||
((IT) == DMA2_IT_HT2) || ((IT) == DMA2_IT_TE2) || \
|
||||
((IT) == DMA2_IT_GL3) || ((IT) == DMA2_IT_TC3) || \
|
||||
((IT) == DMA2_IT_HT3) || ((IT) == DMA2_IT_TE3) || \
|
||||
((IT) == DMA2_IT_GL4) || ((IT) == DMA2_IT_TC4) || \
|
||||
((IT) == DMA2_IT_HT4) || ((IT) == DMA2_IT_TE4) || \
|
||||
((IT) == DMA2_IT_GL5) || ((IT) == DMA2_IT_TC5) || \
|
||||
((IT) == DMA2_IT_HT5) || ((IT) == DMA2_IT_TE5))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_flags_definition
|
||||
* @{
|
||||
*/
|
||||
#define DMA1_FLAG_GL1 ((uint32_t)0x00000001)
|
||||
#define DMA1_FLAG_TC1 ((uint32_t)0x00000002)
|
||||
#define DMA1_FLAG_HT1 ((uint32_t)0x00000004)
|
||||
#define DMA1_FLAG_TE1 ((uint32_t)0x00000008)
|
||||
#define DMA1_FLAG_GL2 ((uint32_t)0x00000010)
|
||||
#define DMA1_FLAG_TC2 ((uint32_t)0x00000020)
|
||||
#define DMA1_FLAG_HT2 ((uint32_t)0x00000040)
|
||||
#define DMA1_FLAG_TE2 ((uint32_t)0x00000080)
|
||||
#define DMA1_FLAG_GL3 ((uint32_t)0x00000100)
|
||||
#define DMA1_FLAG_TC3 ((uint32_t)0x00000200)
|
||||
#define DMA1_FLAG_HT3 ((uint32_t)0x00000400)
|
||||
#define DMA1_FLAG_TE3 ((uint32_t)0x00000800)
|
||||
#define DMA1_FLAG_GL4 ((uint32_t)0x00001000)
|
||||
#define DMA1_FLAG_TC4 ((uint32_t)0x00002000)
|
||||
#define DMA1_FLAG_HT4 ((uint32_t)0x00004000)
|
||||
#define DMA1_FLAG_TE4 ((uint32_t)0x00008000)
|
||||
#define DMA1_FLAG_GL5 ((uint32_t)0x00010000)
|
||||
#define DMA1_FLAG_TC5 ((uint32_t)0x00020000)
|
||||
#define DMA1_FLAG_HT5 ((uint32_t)0x00040000)
|
||||
#define DMA1_FLAG_TE5 ((uint32_t)0x00080000)
|
||||
#define DMA1_FLAG_GL6 ((uint32_t)0x00100000)
|
||||
#define DMA1_FLAG_TC6 ((uint32_t)0x00200000)
|
||||
#define DMA1_FLAG_HT6 ((uint32_t)0x00400000)
|
||||
#define DMA1_FLAG_TE6 ((uint32_t)0x00800000)
|
||||
#define DMA1_FLAG_GL7 ((uint32_t)0x01000000)
|
||||
#define DMA1_FLAG_TC7 ((uint32_t)0x02000000)
|
||||
#define DMA1_FLAG_HT7 ((uint32_t)0x04000000)
|
||||
#define DMA1_FLAG_TE7 ((uint32_t)0x08000000)
|
||||
|
||||
#define DMA2_FLAG_GL1 ((uint32_t)0x10000001)
|
||||
#define DMA2_FLAG_TC1 ((uint32_t)0x10000002)
|
||||
#define DMA2_FLAG_HT1 ((uint32_t)0x10000004)
|
||||
#define DMA2_FLAG_TE1 ((uint32_t)0x10000008)
|
||||
#define DMA2_FLAG_GL2 ((uint32_t)0x10000010)
|
||||
#define DMA2_FLAG_TC2 ((uint32_t)0x10000020)
|
||||
#define DMA2_FLAG_HT2 ((uint32_t)0x10000040)
|
||||
#define DMA2_FLAG_TE2 ((uint32_t)0x10000080)
|
||||
#define DMA2_FLAG_GL3 ((uint32_t)0x10000100)
|
||||
#define DMA2_FLAG_TC3 ((uint32_t)0x10000200)
|
||||
#define DMA2_FLAG_HT3 ((uint32_t)0x10000400)
|
||||
#define DMA2_FLAG_TE3 ((uint32_t)0x10000800)
|
||||
#define DMA2_FLAG_GL4 ((uint32_t)0x10001000)
|
||||
#define DMA2_FLAG_TC4 ((uint32_t)0x10002000)
|
||||
#define DMA2_FLAG_HT4 ((uint32_t)0x10004000)
|
||||
#define DMA2_FLAG_TE4 ((uint32_t)0x10008000)
|
||||
#define DMA2_FLAG_GL5 ((uint32_t)0x10010000)
|
||||
#define DMA2_FLAG_TC5 ((uint32_t)0x10020000)
|
||||
#define DMA2_FLAG_HT5 ((uint32_t)0x10040000)
|
||||
#define DMA2_FLAG_TE5 ((uint32_t)0x10080000)
|
||||
|
||||
#define IS_DMA_CLEAR_FLAG(FLAG) (((((FLAG) & 0xF0000000) == 0x00) || (((FLAG) & 0xEFF00000) == 0x00)) && ((FLAG) != 0x00))
|
||||
|
||||
#define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || \
|
||||
((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) || \
|
||||
((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || \
|
||||
((FLAG) == DMA1_FLAG_HT2) || ((FLAG) == DMA1_FLAG_TE2) || \
|
||||
((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) || \
|
||||
((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_TE3) || \
|
||||
((FLAG) == DMA1_FLAG_GL4) || ((FLAG) == DMA1_FLAG_TC4) || \
|
||||
((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_TE4) || \
|
||||
((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || \
|
||||
((FLAG) == DMA1_FLAG_HT5) || ((FLAG) == DMA1_FLAG_TE5) || \
|
||||
((FLAG) == DMA1_FLAG_GL6) || ((FLAG) == DMA1_FLAG_TC6) || \
|
||||
((FLAG) == DMA1_FLAG_HT6) || ((FLAG) == DMA1_FLAG_TE6) || \
|
||||
((FLAG) == DMA1_FLAG_GL7) || ((FLAG) == DMA1_FLAG_TC7) || \
|
||||
((FLAG) == DMA1_FLAG_HT7) || ((FLAG) == DMA1_FLAG_TE7) || \
|
||||
((FLAG) == DMA2_FLAG_GL1) || ((FLAG) == DMA2_FLAG_TC1) || \
|
||||
((FLAG) == DMA2_FLAG_HT1) || ((FLAG) == DMA2_FLAG_TE1) || \
|
||||
((FLAG) == DMA2_FLAG_GL2) || ((FLAG) == DMA2_FLAG_TC2) || \
|
||||
((FLAG) == DMA2_FLAG_HT2) || ((FLAG) == DMA2_FLAG_TE2) || \
|
||||
((FLAG) == DMA2_FLAG_GL3) || ((FLAG) == DMA2_FLAG_TC3) || \
|
||||
((FLAG) == DMA2_FLAG_HT3) || ((FLAG) == DMA2_FLAG_TE3) || \
|
||||
((FLAG) == DMA2_FLAG_GL4) || ((FLAG) == DMA2_FLAG_TC4) || \
|
||||
((FLAG) == DMA2_FLAG_HT4) || ((FLAG) == DMA2_FLAG_TE4) || \
|
||||
((FLAG) == DMA2_FLAG_GL5) || ((FLAG) == DMA2_FLAG_TC5) || \
|
||||
((FLAG) == DMA2_FLAG_HT5) || ((FLAG) == DMA2_FLAG_TE5))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Buffer_Size
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
|
||||
/* Function used to set the DMA configuration to the default reset state *****/
|
||||
void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx);
|
||||
|
||||
/* Initialization and Configuration functions *********************************/
|
||||
void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct);
|
||||
void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct);
|
||||
void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState);
|
||||
|
||||
/* Data Counter functions *****************************************************/
|
||||
void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber);
|
||||
uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx);
|
||||
|
||||
/* Interrupts and flags management functions **********************************/
|
||||
void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState);
|
||||
FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG);
|
||||
void DMA_ClearFlag(uint32_t DMAy_FLAG);
|
||||
ITStatus DMA_GetITStatus(uint32_t DMAy_IT);
|
||||
void DMA_ClearITPendingBit(uint32_t DMAy_IT);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__STM32L1xx_DMA_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,199 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32l1xx_exti.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.1
|
||||
* @date 05-March-2012
|
||||
* @brief This file contains all the functions prototypes for the EXTI firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32L1xx_EXTI_H
|
||||
#define __STM32L1xx_EXTI_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32l1xx.h"
|
||||
|
||||
/** @addtogroup STM32L1xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup EXTI
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief EXTI mode enumeration
|
||||
*/
|
||||
|
||||
typedef enum
|
||||
{
|
||||
EXTI_Mode_Interrupt = 0x00,
|
||||
EXTI_Mode_Event = 0x04
|
||||
}EXTIMode_TypeDef;
|
||||
|
||||
#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event))
|
||||
|
||||
/**
|
||||
* @brief EXTI Trigger enumeration
|
||||
*/
|
||||
|
||||
typedef enum
|
||||
{
|
||||
EXTI_Trigger_Rising = 0x08,
|
||||
EXTI_Trigger_Falling = 0x0C,
|
||||
EXTI_Trigger_Rising_Falling = 0x10
|
||||
}EXTITrigger_TypeDef;
|
||||
|
||||
#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \
|
||||
((TRIGGER) == EXTI_Trigger_Falling) || \
|
||||
((TRIGGER) == EXTI_Trigger_Rising_Falling))
|
||||
/**
|
||||
* @brief EXTI Init Structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled.
|
||||
This parameter can be any combination of @ref EXTI_Lines */
|
||||
|
||||
EXTIMode_TypeDef EXTI_Mode; /*!< Specifies the mode for the EXTI lines.
|
||||
This parameter can be a value of @ref EXTIMode_TypeDef */
|
||||
|
||||
EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines.
|
||||
This parameter can be a value of @ref EXTITrigger_TypeDef */
|
||||
|
||||
FunctionalState EXTI_LineCmd; /*!< Specifies the new state of the selected EXTI lines.
|
||||
This parameter can be set either to ENABLE or DISABLE */
|
||||
}EXTI_InitTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup EXTI_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_Lines
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define EXTI_Line0 ((uint32_t)0x00000001) /*!< External interrupt line 0 */
|
||||
#define EXTI_Line1 ((uint32_t)0x00000002) /*!< External interrupt line 1 */
|
||||
#define EXTI_Line2 ((uint32_t)0x00000004) /*!< External interrupt line 2 */
|
||||
#define EXTI_Line3 ((uint32_t)0x00000008) /*!< External interrupt line 3 */
|
||||
#define EXTI_Line4 ((uint32_t)0x00000010) /*!< External interrupt line 4 */
|
||||
#define EXTI_Line5 ((uint32_t)0x00000020) /*!< External interrupt line 5 */
|
||||
#define EXTI_Line6 ((uint32_t)0x00000040) /*!< External interrupt line 6 */
|
||||
#define EXTI_Line7 ((uint32_t)0x00000080) /*!< External interrupt line 7 */
|
||||
#define EXTI_Line8 ((uint32_t)0x00000100) /*!< External interrupt line 8 */
|
||||
#define EXTI_Line9 ((uint32_t)0x00000200) /*!< External interrupt line 9 */
|
||||
#define EXTI_Line10 ((uint32_t)0x00000400) /*!< External interrupt line 10 */
|
||||
#define EXTI_Line11 ((uint32_t)0x00000800) /*!< External interrupt line 11 */
|
||||
#define EXTI_Line12 ((uint32_t)0x00001000) /*!< External interrupt line 12 */
|
||||
#define EXTI_Line13 ((uint32_t)0x00002000) /*!< External interrupt line 13 */
|
||||
#define EXTI_Line14 ((uint32_t)0x00004000) /*!< External interrupt line 14 */
|
||||
#define EXTI_Line15 ((uint32_t)0x00008000) /*!< External interrupt line 15 */
|
||||
#define EXTI_Line16 ((uint32_t)0x00010000) /*!< External interrupt line 16
|
||||
Connected to the PVD Output */
|
||||
#define EXTI_Line17 ((uint32_t)0x00020000) /*!< External interrupt line 17
|
||||
Connected to the RTC Alarm
|
||||
event */
|
||||
#define EXTI_Line18 ((uint32_t)0x00040000) /*!< External interrupt line 18
|
||||
Connected to the USB Device
|
||||
FS Wakeup from suspend event */
|
||||
#define EXTI_Line19 ((uint32_t)0x00080000) /*!< External interrupt line 19
|
||||
Connected to the RTC Tamper
|
||||
and Time Stamp events */
|
||||
#define EXTI_Line20 ((uint32_t)0x00100000) /*!< External interrupt line 20
|
||||
Connected to the RTC Wakeup
|
||||
event */
|
||||
#define EXTI_Line21 ((uint32_t)0x00200000) /*!< External interrupt line 21
|
||||
Connected to the Comparator 1
|
||||
event */
|
||||
|
||||
#define EXTI_Line22 ((uint32_t)0x00400000) /*!< External interrupt line 22
|
||||
Connected to the Comparator 2
|
||||
event */
|
||||
|
||||
#define EXTI_Line23 ((uint32_t)0x00800000) /*!< External interrupt line 23
|
||||
Comparator channel acquisition event */
|
||||
|
||||
#define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xFF000000) == 0x00) && ((LINE) != (uint16_t)0x00))
|
||||
|
||||
#define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \
|
||||
((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \
|
||||
((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \
|
||||
((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \
|
||||
((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \
|
||||
((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \
|
||||
((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \
|
||||
((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \
|
||||
((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \
|
||||
((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19) || \
|
||||
((LINE) == EXTI_Line20) || ((LINE) == EXTI_Line21) || \
|
||||
((LINE) == EXTI_Line22) || ((LINE) == EXTI_Line23))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
/* Function used to set the EXTI configuration to the default reset state *****/
|
||||
void EXTI_DeInit(void);
|
||||
|
||||
/* Initialization and Configuration functions *********************************/
|
||||
void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct);
|
||||
void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct);
|
||||
void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line);
|
||||
|
||||
/* Interrupts and flags management functions **********************************/
|
||||
FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line);
|
||||
void EXTI_ClearFlag(uint32_t EXTI_Line);
|
||||
ITStatus EXTI_GetITStatus(uint32_t EXTI_Line);
|
||||
void EXTI_ClearITPendingBit(uint32_t EXTI_Line);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32L1xx_EXTI_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,464 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32l1xx_flash.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.1
|
||||
* @date 05-March-2012
|
||||
* @brief This file contains all the functions prototypes for the FLASH
|
||||
* firmware library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32L1xx_FLASH_H
|
||||
#define __STM32L1xx_FLASH_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32l1xx.h"
|
||||
|
||||
/** @addtogroup STM32L1xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASH
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief FLASH Status
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
FLASH_BUSY = 1,
|
||||
FLASH_ERROR_WRP,
|
||||
FLASH_ERROR_PROGRAM,
|
||||
FLASH_COMPLETE,
|
||||
FLASH_TIMEOUT
|
||||
}FLASH_Status;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup FLASH_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Latency
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_Latency_0 ((uint8_t)0x00) /*!< FLASH Zero Latency cycle */
|
||||
#define FLASH_Latency_1 ((uint8_t)0x01) /*!< FLASH One Latency cycle */
|
||||
|
||||
#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \
|
||||
((LATENCY) == FLASH_Latency_1))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Interrupts
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FLASH_IT_EOP FLASH_PECR_EOPIE /*!< End of programming interrupt source */
|
||||
#define FLASH_IT_ERR FLASH_PECR_ERRIE /*!< Error interrupt source */
|
||||
#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFFFCFFFF) == 0x00000000) && (((IT) != 0x00000000)))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Address
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_FLASH_DATA_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08080000) && ((ADDRESS) <= 0x08082FFF))
|
||||
#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x0805FFFF))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Option_Bytes_Write_Protection
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define OB_WRP_Pages0to15 ((uint32_t)0x00000001) /* Write protection of Sector0 */
|
||||
#define OB_WRP_Pages16to31 ((uint32_t)0x00000002) /* Write protection of Sector1 */
|
||||
#define OB_WRP_Pages32to47 ((uint32_t)0x00000004) /* Write protection of Sector2 */
|
||||
#define OB_WRP_Pages48to63 ((uint32_t)0x00000008) /* Write protection of Sector3 */
|
||||
#define OB_WRP_Pages64to79 ((uint32_t)0x00000010) /* Write protection of Sector4 */
|
||||
#define OB_WRP_Pages80to95 ((uint32_t)0x00000020) /* Write protection of Sector5 */
|
||||
#define OB_WRP_Pages96to111 ((uint32_t)0x00000040) /* Write protection of Sector6 */
|
||||
#define OB_WRP_Pages112to127 ((uint32_t)0x00000080) /* Write protection of Sector7 */
|
||||
#define OB_WRP_Pages128to143 ((uint32_t)0x00000100) /* Write protection of Sector8 */
|
||||
#define OB_WRP_Pages144to159 ((uint32_t)0x00000200) /* Write protection of Sector9 */
|
||||
#define OB_WRP_Pages160to175 ((uint32_t)0x00000400) /* Write protection of Sector10 */
|
||||
#define OB_WRP_Pages176to191 ((uint32_t)0x00000800) /* Write protection of Sector11 */
|
||||
#define OB_WRP_Pages192to207 ((uint32_t)0x00001000) /* Write protection of Sector12 */
|
||||
#define OB_WRP_Pages208to223 ((uint32_t)0x00002000) /* Write protection of Sector13 */
|
||||
#define OB_WRP_Pages224to239 ((uint32_t)0x00004000) /* Write protection of Sector14 */
|
||||
#define OB_WRP_Pages240to255 ((uint32_t)0x00008000) /* Write protection of Sector15 */
|
||||
#define OB_WRP_Pages256to271 ((uint32_t)0x00010000) /* Write protection of Sector16 */
|
||||
#define OB_WRP_Pages272to287 ((uint32_t)0x00020000) /* Write protection of Sector17 */
|
||||
#define OB_WRP_Pages288to303 ((uint32_t)0x00040000) /* Write protection of Sector18 */
|
||||
#define OB_WRP_Pages304to319 ((uint32_t)0x00080000) /* Write protection of Sector19 */
|
||||
#define OB_WRP_Pages320to335 ((uint32_t)0x00100000) /* Write protection of Sector20 */
|
||||
#define OB_WRP_Pages336to351 ((uint32_t)0x00200000) /* Write protection of Sector21 */
|
||||
#define OB_WRP_Pages352to367 ((uint32_t)0x00400000) /* Write protection of Sector22 */
|
||||
#define OB_WRP_Pages368to383 ((uint32_t)0x00800000) /* Write protection of Sector23 */
|
||||
#define OB_WRP_Pages384to399 ((uint32_t)0x01000000) /* Write protection of Sector24 */
|
||||
#define OB_WRP_Pages400to415 ((uint32_t)0x02000000) /* Write protection of Sector25 */
|
||||
#define OB_WRP_Pages416to431 ((uint32_t)0x04000000) /* Write protection of Sector26 */
|
||||
#define OB_WRP_Pages432to447 ((uint32_t)0x08000000) /* Write protection of Sector27 */
|
||||
#define OB_WRP_Pages448to463 ((uint32_t)0x10000000) /* Write protection of Sector28 */
|
||||
#define OB_WRP_Pages464to479 ((uint32_t)0x20000000) /* Write protection of Sector29 */
|
||||
#define OB_WRP_Pages480to495 ((uint32_t)0x40000000) /* Write protection of Sector30 */
|
||||
#define OB_WRP_Pages496to511 ((uint32_t)0x80000000) /* Write protection of Sector31 */
|
||||
|
||||
#define OB_WRP_AllPages ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Sectors */
|
||||
|
||||
#define OB_WRP1_Pages512to527 ((uint32_t)0x00000001) /* Write protection of Sector32 */
|
||||
#define OB_WRP1_Pages528to543 ((uint32_t)0x00000002) /* Write protection of Sector33 */
|
||||
#define OB_WRP1_Pages544to559 ((uint32_t)0x00000004) /* Write protection of Sector34 */
|
||||
#define OB_WRP1_Pages560to575 ((uint32_t)0x00000008) /* Write protection of Sector35 */
|
||||
#define OB_WRP1_Pages576to591 ((uint32_t)0x00000010) /* Write protection of Sector36 */
|
||||
#define OB_WRP1_Pages592to607 ((uint32_t)0x00000020) /* Write protection of Sector37 */
|
||||
#define OB_WRP1_Pages608to623 ((uint32_t)0x00000040) /* Write protection of Sector38 */
|
||||
#define OB_WRP1_Pages624to639 ((uint32_t)0x00000080) /* Write protection of Sector39 */
|
||||
#define OB_WRP1_Pages640to655 ((uint32_t)0x00000100) /* Write protection of Sector40 */
|
||||
#define OB_WRP1_Pages656to671 ((uint32_t)0x00000200) /* Write protection of Sector41 */
|
||||
#define OB_WRP1_Pages672to687 ((uint32_t)0x00000400) /* Write protection of Sector42 */
|
||||
#define OB_WRP1_Pages688to703 ((uint32_t)0x00000800) /* Write protection of Sector43 */
|
||||
#define OB_WRP1_Pages704to719 ((uint32_t)0x00001000) /* Write protection of Sector44 */
|
||||
#define OB_WRP1_Pages720to735 ((uint32_t)0x00002000) /* Write protection of Sector45 */
|
||||
#define OB_WRP1_Pages736to751 ((uint32_t)0x00004000) /* Write protection of Sector46 */
|
||||
#define OB_WRP1_Pages752to767 ((uint32_t)0x00008000) /* Write protection of Sector47 */
|
||||
#define OB_WRP1_Pages768to783 ((uint32_t)0x00010000) /* Write protection of Sector48 */
|
||||
#define OB_WRP1_Pages784to799 ((uint32_t)0x00020000) /* Write protection of Sector49 */
|
||||
#define OB_WRP1_Pages800to815 ((uint32_t)0x00040000) /* Write protection of Sector50 */
|
||||
#define OB_WRP1_Pages816to831 ((uint32_t)0x00080000) /* Write protection of Sector51 */
|
||||
#define OB_WRP1_Pages832to847 ((uint32_t)0x00100000) /* Write protection of Sector52 */
|
||||
#define OB_WRP1_Pages848to863 ((uint32_t)0x00200000) /* Write protection of Sector53 */
|
||||
#define OB_WRP1_Pages864to879 ((uint32_t)0x00400000) /* Write protection of Sector54 */
|
||||
#define OB_WRP1_Pages880to895 ((uint32_t)0x00800000) /* Write protection of Sector55 */
|
||||
#define OB_WRP1_Pages896to911 ((uint32_t)0x01000000) /* Write protection of Sector56 */
|
||||
#define OB_WRP1_Pages912to927 ((uint32_t)0x02000000) /* Write protection of Sector57 */
|
||||
#define OB_WRP1_Pages928to943 ((uint32_t)0x04000000) /* Write protection of Sector58 */
|
||||
#define OB_WRP1_Pages944to959 ((uint32_t)0x08000000) /* Write protection of Sector59 */
|
||||
#define OB_WRP1_Pages960to975 ((uint32_t)0x10000000) /* Write protection of Sector60 */
|
||||
#define OB_WRP1_Pages976to991 ((uint32_t)0x20000000) /* Write protection of Sector61 */
|
||||
#define OB_WRP1_Pages992to1007 ((uint32_t)0x40000000) /* Write protection of Sector62 */
|
||||
#define OB_WRP1_Pages1008to1023 ((uint32_t)0x80000000) /* Write protection of Sector63 */
|
||||
|
||||
#define OB_WRP1_AllPages ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Sectors */
|
||||
|
||||
#define OB_WRP2_Pages1024to1039 ((uint32_t)0x00000001) /* Write protection of Sector64 */
|
||||
#define OB_WRP2_Pages1040to1055 ((uint32_t)0x00000002) /* Write protection of Sector65 */
|
||||
#define OB_WRP2_Pages1056to1071 ((uint32_t)0x00000004) /* Write protection of Sector66 */
|
||||
#define OB_WRP2_Pages1072to1087 ((uint32_t)0x00000008) /* Write protection of Sector67 */
|
||||
#define OB_WRP2_Pages1088to1103 ((uint32_t)0x00000010) /* Write protection of Sector68 */
|
||||
#define OB_WRP2_Pages1104to1119 ((uint32_t)0x00000020) /* Write protection of Sector69 */
|
||||
#define OB_WRP2_Pages1120to1135 ((uint32_t)0x00000040) /* Write protection of Sector70 */
|
||||
#define OB_WRP2_Pages1136to1151 ((uint32_t)0x00000080) /* Write protection of Sector71 */
|
||||
#define OB_WRP2_Pages1152to1167 ((uint32_t)0x00000100) /* Write protection of Sector72 */
|
||||
#define OB_WRP2_Pages1168to1183 ((uint32_t)0x00000200) /* Write protection of Sector73 */
|
||||
#define OB_WRP2_Pages1184to1199 ((uint32_t)0x00000400) /* Write protection of Sector74 */
|
||||
#define OB_WRP2_Pages1200to1215 ((uint32_t)0x00000800) /* Write protection of Sector75 */
|
||||
#define OB_WRP2_Pages1216to1231 ((uint32_t)0x00001000) /* Write protection of Sector76 */
|
||||
#define OB_WRP2_Pages1232to1247 ((uint32_t)0x00002000) /* Write protection of Sector77 */
|
||||
#define OB_WRP2_Pages1248to1263 ((uint32_t)0x00004000) /* Write protection of Sector78 */
|
||||
#define OB_WRP2_Pages1264to1279 ((uint32_t)0x00008000) /* Write protection of Sector79 */
|
||||
#define OB_WRP2_Pages1280to1295 ((uint32_t)0x00010000) /* Write protection of Sector80 */
|
||||
#define OB_WRP2_Pages1296to1311 ((uint32_t)0x00020000) /* Write protection of Sector81 */
|
||||
#define OB_WRP2_Pages1312to1327 ((uint32_t)0x00040000) /* Write protection of Sector82 */
|
||||
#define OB_WRP2_Pages1328to1343 ((uint32_t)0x00080000) /* Write protection of Sector83 */
|
||||
#define OB_WRP2_Pages1344to1359 ((uint32_t)0x00100000) /* Write protection of Sector84 */
|
||||
#define OB_WRP2_Pages1360to1375 ((uint32_t)0x00200000) /* Write protection of Sector85 */
|
||||
#define OB_WRP2_Pages1376to1391 ((uint32_t)0x00400000) /* Write protection of Sector86 */
|
||||
#define OB_WRP2_Pages1392to1407 ((uint32_t)0x00800000) /* Write protection of Sector87 */
|
||||
#define OB_WRP2_Pages1408to1423 ((uint32_t)0x01000000) /* Write protection of Sector88 */
|
||||
#define OB_WRP2_Pages1424to1439 ((uint32_t)0x02000000) /* Write protection of Sector89 */
|
||||
#define OB_WRP2_Pages1440to1455 ((uint32_t)0x04000000) /* Write protection of Sector90 */
|
||||
#define OB_WRP2_Pages1456to1471 ((uint32_t)0x08000000) /* Write protection of Sector91 */
|
||||
#define OB_WRP2_Pages1472to1487 ((uint32_t)0x10000000) /* Write protection of Sector92 */
|
||||
#define OB_WRP2_Pages1488to1503 ((uint32_t)0x20000000) /* Write protection of Sector93 */
|
||||
#define OB_WRP2_Pages1504to1519 ((uint32_t)0x40000000) /* Write protection of Sector94 */
|
||||
#define OB_WRP2_Pages1520to1535 ((uint32_t)0x80000000) /* Write protection of Sector95 */
|
||||
|
||||
#define OB_WRP2_AllPages ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Sectors */
|
||||
|
||||
#define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Option_Bytes_Read_Protection
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Read Protection Level
|
||||
*/
|
||||
#define OB_RDP_Level_0 ((uint8_t)0xAA)
|
||||
#define OB_RDP_Level_1 ((uint8_t)0xBB)
|
||||
/*#define OB_RDP_Level_2 ((uint8_t)0xCC)*/ /* Warning: When enabling read protection level 2
|
||||
it's no more possible to go back to level 1 or 0 */
|
||||
|
||||
#define IS_OB_RDP(LEVEL) (((LEVEL) == OB_RDP_Level_0)||\
|
||||
((LEVEL) == OB_RDP_Level_1))/*||\
|
||||
((LEVEL) == OB_RDP_Level_2))*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Option_Bytes_IWatchdog
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define OB_IWDG_SW ((uint8_t)0x10) /*!< Software WDG selected */
|
||||
#define OB_IWDG_HW ((uint8_t)0x00) /*!< Hardware WDG selected */
|
||||
#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Option_Bytes_nRST_STOP
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define OB_STOP_NoRST ((uint8_t)0x20) /*!< No reset generated when entering in STOP */
|
||||
#define OB_STOP_RST ((uint8_t)0x00) /*!< Reset generated when entering in STOP */
|
||||
#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Option_Bytes_nRST_STDBY
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define OB_STDBY_NoRST ((uint8_t)0x40) /*!< No reset generated when entering in STANDBY */
|
||||
#define OB_STDBY_RST ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY */
|
||||
#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Option_Bytes_BOOT
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define OB_BOOT_BANK2 ((uint8_t)0x00) /*!< At startup, if boot pins are set in boot from user Flash position
|
||||
and this parameter is selected the device will boot from Bank 2
|
||||
or Bank 1, depending on the activation of the bank */
|
||||
#define OB_BOOT_BANK1 ((uint8_t)0x80) /*!< At startup, if boot pins are set in boot from user Flash position
|
||||
and this parameter is selected the device will boot from Bank1(Default) */
|
||||
#define IS_OB_BOOT_BANK(BANK) (((BANK) == OB_BOOT_BANK2) || ((BANK) == OB_BOOT_BANK1))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Option_Bytes_BOR_Level
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define OB_BOR_OFF ((uint8_t)0x00) /*!< BOR is disabled at power down, the reset is asserted when the VDD
|
||||
power supply reaches the PDR(Power Down Reset) threshold (1.5V) */
|
||||
#define OB_BOR_LEVEL1 ((uint8_t)0x08) /*!< BOR Reset threshold levels for 1.7V - 1.8V VDD power supply */
|
||||
#define OB_BOR_LEVEL2 ((uint8_t)0x09) /*!< BOR Reset threshold levels for 1.9V - 2.0V VDD power supply */
|
||||
#define OB_BOR_LEVEL3 ((uint8_t)0x0A) /*!< BOR Reset threshold levels for 2.3V - 2.4V VDD power supply */
|
||||
#define OB_BOR_LEVEL4 ((uint8_t)0x0B) /*!< BOR Reset threshold levels for 2.55V - 2.65V VDD power supply */
|
||||
#define OB_BOR_LEVEL5 ((uint8_t)0x0C) /*!< BOR Reset threshold levels for 2.8V - 2.9V VDD power supply */
|
||||
|
||||
#define IS_OB_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_OFF) || \
|
||||
((LEVEL) == OB_BOR_LEVEL1) || \
|
||||
((LEVEL) == OB_BOR_LEVEL2) || \
|
||||
((LEVEL) == OB_BOR_LEVEL3) || \
|
||||
((LEVEL) == OB_BOR_LEVEL4) || \
|
||||
((LEVEL) == OB_BOR_LEVEL5))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Flags
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */
|
||||
#define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of Programming flag */
|
||||
#define FLASH_FLAG_ENDHV FLASH_SR_ENHV /*!< FLASH End of High Voltage flag */
|
||||
#define FLASH_FLAG_READY FLASH_SR_READY /*!< FLASH Ready flag after low power mode */
|
||||
#define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< FLASH Write protected error flag */
|
||||
#define FLASH_FLAG_PGAERR FLASH_SR_PGAERR /*!< FLASH Programming Alignment error flag */
|
||||
#define FLASH_FLAG_SIZERR FLASH_SR_SIZERR /*!< FLASH Size error flag */
|
||||
#define FLASH_FLAG_OPTVERR FLASH_SR_OPTVERR /*!< FLASH Option Validity error flag */
|
||||
#define FLASH_FLAG_OPTVERRUSR FLASH_SR_OPTVERRUSR /*!< FLASH Option User Validity error flag */
|
||||
|
||||
#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFE0FD) == 0x00000000) && ((FLAG) != 0x00000000))
|
||||
|
||||
#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_EOP) || \
|
||||
((FLAG) == FLASH_FLAG_ENDHV) || ((FLAG) == FLASH_FLAG_READY ) || \
|
||||
((FLAG) == FLASH_FLAG_WRPERR) || ((FLAG) == FLASH_FLAG_PGAERR ) || \
|
||||
((FLAG) == FLASH_FLAG_SIZERR) || ((FLAG) == FLASH_FLAG_OPTVERR) || \
|
||||
((FLAG) == FLASH_FLAG_OPTVERRUSR))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Keys
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FLASH_PDKEY1 ((uint32_t)0x04152637) /*!< Flash power down key1 */
|
||||
#define FLASH_PDKEY2 ((uint32_t)0xFAFBFCFD) /*!< Flash power down key2: used with FLASH_PDKEY1
|
||||
to unlock the RUN_PD bit in FLASH_ACR */
|
||||
|
||||
#define FLASH_PEKEY1 ((uint32_t)0x89ABCDEF) /*!< Flash program erase key1 */
|
||||
#define FLASH_PEKEY2 ((uint32_t)0x02030405) /*!< Flash program erase key: used with FLASH_PEKEY2
|
||||
to unlock the write access to the FLASH_PECR register and
|
||||
data EEPROM */
|
||||
|
||||
#define FLASH_PRGKEY1 ((uint32_t)0x8C9DAEBF) /*!< Flash program memory key1 */
|
||||
#define FLASH_PRGKEY2 ((uint32_t)0x13141516) /*!< Flash program memory key2: used with FLASH_PRGKEY2
|
||||
to unlock the program memory */
|
||||
|
||||
#define FLASH_OPTKEY1 ((uint32_t)0xFBEAD9C8) /*!< Flash option key1 */
|
||||
#define FLASH_OPTKEY2 ((uint32_t)0x24252627) /*!< Flash option key2: used with FLASH_OPTKEY1 to
|
||||
unlock the write access to the option byte block */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Timeout_definition
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_ER_PRG_TIMEOUT ((uint32_t)0x8000)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup CMSIS_Legacy
|
||||
* @{
|
||||
*/
|
||||
#if defined ( __ICCARM__ )
|
||||
#define InterruptType_ACTLR_DISMCYCINT_Msk IntType_ACTLR_DISMCYCINT_Msk
|
||||
#endif
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
|
||||
/**
|
||||
* @brief FLASH memory functions that can be executed from FLASH.
|
||||
*/
|
||||
/* FLASH Interface configuration functions ************************************/
|
||||
void FLASH_SetLatency(uint32_t FLASH_Latency);
|
||||
void FLASH_PrefetchBufferCmd(FunctionalState NewState);
|
||||
void FLASH_ReadAccess64Cmd(FunctionalState NewState);
|
||||
void FLASH_SLEEPPowerDownCmd(FunctionalState NewState);
|
||||
|
||||
/* FLASH Memory Programming functions *****************************************/
|
||||
void FLASH_Unlock(void);
|
||||
void FLASH_Lock(void);
|
||||
FLASH_Status FLASH_ErasePage(uint32_t Page_Address);
|
||||
FLASH_Status FLASH_FastProgramWord(uint32_t Address, uint32_t Data);
|
||||
|
||||
/* DATA EEPROM Programming functions ******************************************/
|
||||
void DATA_EEPROM_Unlock(void);
|
||||
void DATA_EEPROM_Lock(void);
|
||||
void DATA_EEPROM_FixedTimeProgramCmd(FunctionalState NewState);
|
||||
FLASH_Status DATA_EEPROM_EraseByte(uint32_t Address);
|
||||
FLASH_Status DATA_EEPROM_EraseHalfWord(uint32_t Address);
|
||||
FLASH_Status DATA_EEPROM_EraseWord(uint32_t Address);
|
||||
FLASH_Status DATA_EEPROM_FastProgramByte(uint32_t Address, uint8_t Data);
|
||||
FLASH_Status DATA_EEPROM_FastProgramHalfWord(uint32_t Address, uint16_t Data);
|
||||
FLASH_Status DATA_EEPROM_FastProgramWord(uint32_t Address, uint32_t Data);
|
||||
FLASH_Status DATA_EEPROM_ProgramByte(uint32_t Address, uint8_t Data);
|
||||
FLASH_Status DATA_EEPROM_ProgramHalfWord(uint32_t Address, uint16_t Data);
|
||||
FLASH_Status DATA_EEPROM_ProgramWord(uint32_t Address, uint32_t Data);
|
||||
|
||||
/* Option Bytes Programming functions *****************************************/
|
||||
void FLASH_OB_Unlock(void);
|
||||
void FLASH_OB_Lock(void);
|
||||
void FLASH_OB_Launch(void);
|
||||
FLASH_Status FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState);
|
||||
FLASH_Status FLASH_OB_WRP1Config(uint32_t OB_WRP1, FunctionalState NewState);
|
||||
FLASH_Status FLASH_OB_WRP2Config(uint32_t OB_WRP2, FunctionalState NewState);
|
||||
FLASH_Status FLASH_OB_RDPConfig(uint8_t OB_RDP);
|
||||
FLASH_Status FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY);
|
||||
FLASH_Status FLASH_OB_BORConfig(uint8_t OB_BOR);
|
||||
FLASH_Status FLASH_OB_BootConfig(uint8_t OB_BOOT);
|
||||
uint8_t FLASH_OB_GetUser(void);
|
||||
uint32_t FLASH_OB_GetWRP(void);
|
||||
uint32_t FLASH_OB_GetWRP1(void);
|
||||
uint32_t FLASH_OB_GetWRP2(void);
|
||||
FlagStatus FLASH_OB_GetRDP(void);
|
||||
uint8_t FLASH_OB_GetBOR(void);
|
||||
|
||||
/* Interrupts and flags management functions **********************************/
|
||||
void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState);
|
||||
FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG);
|
||||
void FLASH_ClearFlag(uint32_t FLASH_FLAG);
|
||||
FLASH_Status FLASH_GetStatus(void);
|
||||
FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout);
|
||||
|
||||
/**
|
||||
* @brief FLASH memory functions that should be executed from internal SRAM.
|
||||
* These functions are defined inside the "stm32l1xx_flash_ramfunc.c"
|
||||
* file.
|
||||
*/
|
||||
__RAM_FUNC FLASH_RUNPowerDownCmd(FunctionalState NewState);
|
||||
__RAM_FUNC FLASH_EraseParallelPage(uint32_t Page_Address1, uint32_t Page_Address2);
|
||||
__RAM_FUNC FLASH_ProgramHalfPage(uint32_t Address, uint32_t* pBuffer);
|
||||
__RAM_FUNC FLASH_ProgramParallelHalfPage(uint32_t Address1, uint32_t* pBuffer1, uint32_t Address2, uint32_t* pBuffer2);
|
||||
__RAM_FUNC DATA_EEPROM_EraseDoubleWord(uint32_t Address);
|
||||
__RAM_FUNC DATA_EEPROM_ProgramDoubleWord(uint32_t Address, uint64_t Data);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32L1xx_FLASH_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,438 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32l1xx_fsmc.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.1
|
||||
* @date 05-March-2012
|
||||
* @brief This file contains all the functions prototypes for the FSMC firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32L1xx_FSMC_H
|
||||
#define __STM32L1xx_FSMC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32l1xx.h"
|
||||
|
||||
/** @addtogroup STM32L1xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup FSMC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief Timing parameters For NOR/SRAM Banks
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t FSMC_AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
|
||||
the duration of the address setup time.
|
||||
This parameter can be a value between 0 and 0xF.
|
||||
@note It is not used with synchronous NOR Flash memories. */
|
||||
|
||||
uint32_t FSMC_AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
|
||||
the duration of the address hold time.
|
||||
This parameter can be a value between 0 and 0xF.
|
||||
@note It is not used with synchronous NOR Flash memories.*/
|
||||
|
||||
uint32_t FSMC_DataSetupTime; /*!< Defines the number of HCLK cycles to configure
|
||||
the duration of the data setup time.
|
||||
This parameter can be a value between 0 and 0xFF.
|
||||
@note It is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */
|
||||
|
||||
uint32_t FSMC_BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
|
||||
the duration of the bus turnaround.
|
||||
This parameter can be a value between 0 and 0xF.
|
||||
@note It is only used for multiplexed NOR Flash memories. */
|
||||
|
||||
uint32_t FSMC_CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of HCLK cycles.
|
||||
This parameter can be a value between 1 and 0xF.
|
||||
@note This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */
|
||||
|
||||
uint32_t FSMC_DataLatency; /*!< Defines the number of memory clock cycles to issue
|
||||
to the memory before getting the first data.
|
||||
The parameter value depends on the memory type as shown below:
|
||||
- It must be set to 0 in case of a CRAM
|
||||
- It is don't care in asynchronous NOR, SRAM or ROM accesses
|
||||
- It may assume a value between 0 and 0xF in NOR Flash memories
|
||||
with synchronous burst mode enable */
|
||||
|
||||
uint32_t FSMC_AccessMode; /*!< Specifies the asynchronous access mode.
|
||||
This parameter can be a value of @ref FSMC_Access_Mode */
|
||||
}FSMC_NORSRAMTimingInitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief FSMC NOR/SRAM Init structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t FSMC_Bank; /*!< Specifies the NOR/SRAM memory bank that will be used.
|
||||
This parameter can be a value of @ref FSMC_NORSRAM_Bank */
|
||||
|
||||
uint32_t FSMC_DataAddressMux; /*!< Specifies whether the address and data values are
|
||||
multiplexed on the databus or not.
|
||||
This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */
|
||||
|
||||
uint32_t FSMC_MemoryType; /*!< Specifies the type of external memory attached to
|
||||
the corresponding memory bank.
|
||||
This parameter can be a value of @ref FSMC_Memory_Type */
|
||||
|
||||
uint32_t FSMC_MemoryDataWidth; /*!< Specifies the external memory device width.
|
||||
This parameter can be a value of @ref FSMC_Data_Width */
|
||||
|
||||
uint32_t FSMC_BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
|
||||
valid only with synchronous burst Flash memories.
|
||||
This parameter can be a value of @ref FSMC_Burst_Access_Mode */
|
||||
|
||||
uint32_t FSMC_AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
|
||||
valid only with asynchronous Flash memories.
|
||||
This parameter can be a value of @ref FSMC_AsynchronousWait */
|
||||
|
||||
uint32_t FSMC_WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
|
||||
the Flash memory in burst mode.
|
||||
This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */
|
||||
|
||||
uint32_t FSMC_WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
|
||||
memory, valid only when accessing Flash memories in burst mode.
|
||||
This parameter can be a value of @ref FSMC_Wrap_Mode */
|
||||
|
||||
uint32_t FSMC_WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
|
||||
clock cycle before the wait state or during the wait state,
|
||||
valid only when accessing memories in burst mode.
|
||||
This parameter can be a value of @ref FSMC_Wait_Timing */
|
||||
|
||||
uint32_t FSMC_WriteOperation; /*!< Enables or disables the write operation in the selected bank by the FSMC.
|
||||
This parameter can be a value of @ref FSMC_Write_Operation */
|
||||
|
||||
uint32_t FSMC_WaitSignal; /*!< Enables or disables the wait-state insertion via wait
|
||||
signal, valid for Flash memory access in burst mode.
|
||||
This parameter can be a value of @ref FSMC_Wait_Signal */
|
||||
|
||||
uint32_t FSMC_ExtendedMode; /*!< Enables or disables the extended mode.
|
||||
This parameter can be a value of @ref FSMC_Extended_Mode */
|
||||
|
||||
uint32_t FSMC_WriteBurst; /*!< Enables or disables the write burst operation.
|
||||
This parameter can be a value of @ref FSMC_Write_Burst */
|
||||
|
||||
FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct; /*!< Timing Parameters for write and read access if the ExtendedMode is not used*/
|
||||
|
||||
FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct; /*!< Timing Parameters for write access if the ExtendedMode is used*/
|
||||
}FSMC_NORSRAMInitTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup FSMC_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_NORSRAM_Bank
|
||||
* @{
|
||||
*/
|
||||
#define FSMC_Bank1_NORSRAM1 ((uint32_t)0x00000000)
|
||||
#define FSMC_Bank1_NORSRAM2 ((uint32_t)0x00000002)
|
||||
#define FSMC_Bank1_NORSRAM3 ((uint32_t)0x00000004)
|
||||
#define FSMC_Bank1_NORSRAM4 ((uint32_t)0x00000006)
|
||||
|
||||
#define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_Bank1_NORSRAM1) || \
|
||||
((BANK) == FSMC_Bank1_NORSRAM2) || \
|
||||
((BANK) == FSMC_Bank1_NORSRAM3) || \
|
||||
((BANK) == FSMC_Bank1_NORSRAM4))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup NOR_SRAM_Controller
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Data_Address_Bus_Multiplexing
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FSMC_DataAddressMux_Disable ((uint32_t)0x00000000)
|
||||
#define FSMC_DataAddressMux_Enable ((uint32_t)0x00000002)
|
||||
#define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) || \
|
||||
((MUX) == FSMC_DataAddressMux_Enable))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Memory_Type
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FSMC_MemoryType_SRAM ((uint32_t)0x00000000)
|
||||
#define FSMC_MemoryType_PSRAM ((uint32_t)0x00000004)
|
||||
#define FSMC_MemoryType_NOR ((uint32_t)0x00000008)
|
||||
#define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) || \
|
||||
((MEMORY) == FSMC_MemoryType_PSRAM)|| \
|
||||
((MEMORY) == FSMC_MemoryType_NOR))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Data_Width
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FSMC_MemoryDataWidth_8b ((uint32_t)0x00000000)
|
||||
#define FSMC_MemoryDataWidth_16b ((uint32_t)0x00000010)
|
||||
#define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \
|
||||
((WIDTH) == FSMC_MemoryDataWidth_16b))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Burst_Access_Mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FSMC_BurstAccessMode_Disable ((uint32_t)0x00000000)
|
||||
#define FSMC_BurstAccessMode_Enable ((uint32_t)0x00000100)
|
||||
#define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || \
|
||||
((STATE) == FSMC_BurstAccessMode_Enable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_AsynchronousWait
|
||||
* @{
|
||||
*/
|
||||
#define FSMC_AsynchronousWait_Disable ((uint32_t)0x00000000)
|
||||
#define FSMC_AsynchronousWait_Enable ((uint32_t)0x00008000)
|
||||
#define IS_FSMC_ASYNWAIT(STATE) (((STATE) == FSMC_AsynchronousWait_Disable) || \
|
||||
((STATE) == FSMC_AsynchronousWait_Enable))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Wait_Signal_Polarity
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FSMC_WaitSignalPolarity_Low ((uint32_t)0x00000000)
|
||||
#define FSMC_WaitSignalPolarity_High ((uint32_t)0x00000200)
|
||||
#define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) || \
|
||||
((POLARITY) == FSMC_WaitSignalPolarity_High))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Wrap_Mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FSMC_WrapMode_Disable ((uint32_t)0x00000000)
|
||||
#define FSMC_WrapMode_Enable ((uint32_t)0x00000400)
|
||||
#define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || \
|
||||
((MODE) == FSMC_WrapMode_Enable))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Wait_Timing
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FSMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000)
|
||||
#define FSMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800)
|
||||
#define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || \
|
||||
((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Write_Operation
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FSMC_WriteOperation_Disable ((uint32_t)0x00000000)
|
||||
#define FSMC_WriteOperation_Enable ((uint32_t)0x00001000)
|
||||
#define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) || \
|
||||
((OPERATION) == FSMC_WriteOperation_Enable))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Wait_Signal
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FSMC_WaitSignal_Disable ((uint32_t)0x00000000)
|
||||
#define FSMC_WaitSignal_Enable ((uint32_t)0x00002000)
|
||||
#define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) || \
|
||||
((SIGNAL) == FSMC_WaitSignal_Enable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Extended_Mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FSMC_ExtendedMode_Disable ((uint32_t)0x00000000)
|
||||
#define FSMC_ExtendedMode_Enable ((uint32_t)0x00004000)
|
||||
|
||||
#define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || \
|
||||
((MODE) == FSMC_ExtendedMode_Enable))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Write_Burst
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FSMC_WriteBurst_Disable ((uint32_t)0x00000000)
|
||||
#define FSMC_WriteBurst_Enable ((uint32_t)0x00080000)
|
||||
#define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) || \
|
||||
((BURST) == FSMC_WriteBurst_Enable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Address_Setup_Time
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Address_Hold_Time
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Data_Setup_Time
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Bus_Turn_around_Duration
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_CLK_Division
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Data_Latency
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Access_Mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define FSMC_AccessMode_A ((uint32_t)0x00000000)
|
||||
#define FSMC_AccessMode_B ((uint32_t)0x10000000)
|
||||
#define FSMC_AccessMode_C ((uint32_t)0x20000000)
|
||||
#define FSMC_AccessMode_D ((uint32_t)0x30000000)
|
||||
#define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) || \
|
||||
((MODE) == FSMC_AccessMode_B) || \
|
||||
((MODE) == FSMC_AccessMode_C) || \
|
||||
((MODE) == FSMC_AccessMode_D))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
/* NOR/SRAM Controller functions **********************************************/
|
||||
void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank);
|
||||
void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
|
||||
void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
|
||||
void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__STM32L1xx_FSMC_H */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,391 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32l1xx_gpio.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.1
|
||||
* @date 05-March-2012
|
||||
* @brief This file contains all the functions prototypes for the GPIO
|
||||
* firmware library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32L1xx_GPIO_H
|
||||
#define __STM32L1xx_GPIO_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32l1xx.h"
|
||||
|
||||
/** @addtogroup STM32L1xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup GPIO
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \
|
||||
((PERIPH) == GPIOB) || \
|
||||
((PERIPH) == GPIOC) || \
|
||||
((PERIPH) == GPIOD) || \
|
||||
((PERIPH) == GPIOE) || \
|
||||
((PERIPH) == GPIOH) || \
|
||||
((PERIPH) == GPIOF) || \
|
||||
((PERIPH) == GPIOG))
|
||||
|
||||
/** @defgroup Configuration_Mode_enumeration
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
GPIO_Mode_IN = 0x00, /*!< GPIO Input Mode */
|
||||
GPIO_Mode_OUT = 0x01, /*!< GPIO Output Mode */
|
||||
GPIO_Mode_AF = 0x02, /*!< GPIO Alternate function Mode */
|
||||
GPIO_Mode_AN = 0x03 /*!< GPIO Analog Mode */
|
||||
}GPIOMode_TypeDef;
|
||||
#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_IN) || ((MODE) == GPIO_Mode_OUT) || \
|
||||
((MODE) == GPIO_Mode_AF)|| ((MODE) == GPIO_Mode_AN))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Output_type_enumeration
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{ GPIO_OType_PP = 0x00,
|
||||
GPIO_OType_OD = 0x01
|
||||
}GPIOOType_TypeDef;
|
||||
#define IS_GPIO_OTYPE(OTYPE) (((OTYPE) == GPIO_OType_PP) || ((OTYPE) == GPIO_OType_OD))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Output_Maximum_frequency_enumeration
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
GPIO_Speed_400KHz = 0x00, /*!< Very Low Speed */
|
||||
GPIO_Speed_2MHz = 0x01, /*!< Low Speed */
|
||||
GPIO_Speed_10MHz = 0x02, /*!< Medium Speed */
|
||||
GPIO_Speed_40MHz = 0x03 /*!< High Speed */
|
||||
}GPIOSpeed_TypeDef;
|
||||
#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_400KHz) || ((SPEED) == GPIO_Speed_2MHz) || \
|
||||
((SPEED) == GPIO_Speed_10MHz)|| ((SPEED) == GPIO_Speed_40MHz))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Configuration_Pull-Up_Pull-Down_enumeration
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{ GPIO_PuPd_NOPULL = 0x00,
|
||||
GPIO_PuPd_UP = 0x01,
|
||||
GPIO_PuPd_DOWN = 0x02
|
||||
}GPIOPuPd_TypeDef;
|
||||
#define IS_GPIO_PUPD(PUPD) (((PUPD) == GPIO_PuPd_NOPULL) || ((PUPD) == GPIO_PuPd_UP) || \
|
||||
((PUPD) == GPIO_PuPd_DOWN))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup Bit_SET_and_Bit_RESET_enumeration
|
||||
* @{
|
||||
*/
|
||||
typedef enum
|
||||
{ Bit_RESET = 0,
|
||||
Bit_SET
|
||||
}BitAction;
|
||||
#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief GPIO Init structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t GPIO_Pin; /*!< Specifies the GPIO pins to be configured.
|
||||
This parameter can be any value of @ref GPIO_pins_define */
|
||||
|
||||
GPIOMode_TypeDef GPIO_Mode; /*!< Specifies the operating mode for the selected pins.
|
||||
This parameter can be a value of @ref GPIOMode_TypeDef */
|
||||
|
||||
GPIOSpeed_TypeDef GPIO_Speed; /*!< Specifies the speed for the selected pins.
|
||||
This parameter can be a value of @ref GPIOSpeed_TypeDef */
|
||||
|
||||
GPIOOType_TypeDef GPIO_OType; /*!< Specifies the operating output type for the selected pins.
|
||||
This parameter can be a value of @ref GPIOOType_TypeDef */
|
||||
|
||||
GPIOPuPd_TypeDef GPIO_PuPd; /*!< Specifies the operating Pull-up/Pull down for the selected pins.
|
||||
This parameter can be a value of @ref GPIOPuPd_TypeDef */
|
||||
}GPIO_InitTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup GPIO_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_pins_define
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_Pin_0 ((uint16_t)0x0001) /*!< Pin 0 selected */
|
||||
#define GPIO_Pin_1 ((uint16_t)0x0002) /*!< Pin 1 selected */
|
||||
#define GPIO_Pin_2 ((uint16_t)0x0004) /*!< Pin 2 selected */
|
||||
#define GPIO_Pin_3 ((uint16_t)0x0008) /*!< Pin 3 selected */
|
||||
#define GPIO_Pin_4 ((uint16_t)0x0010) /*!< Pin 4 selected */
|
||||
#define GPIO_Pin_5 ((uint16_t)0x0020) /*!< Pin 5 selected */
|
||||
#define GPIO_Pin_6 ((uint16_t)0x0040) /*!< Pin 6 selected */
|
||||
#define GPIO_Pin_7 ((uint16_t)0x0080) /*!< Pin 7 selected */
|
||||
#define GPIO_Pin_8 ((uint16_t)0x0100) /*!< Pin 8 selected */
|
||||
#define GPIO_Pin_9 ((uint16_t)0x0200) /*!< Pin 9 selected */
|
||||
#define GPIO_Pin_10 ((uint16_t)0x0400) /*!< Pin 10 selected */
|
||||
#define GPIO_Pin_11 ((uint16_t)0x0800) /*!< Pin 11 selected */
|
||||
#define GPIO_Pin_12 ((uint16_t)0x1000) /*!< Pin 12 selected */
|
||||
#define GPIO_Pin_13 ((uint16_t)0x2000) /*!< Pin 13 selected */
|
||||
#define GPIO_Pin_14 ((uint16_t)0x4000) /*!< Pin 14 selected */
|
||||
#define GPIO_Pin_15 ((uint16_t)0x8000) /*!< Pin 15 selected */
|
||||
#define GPIO_Pin_All ((uint16_t)0xFFFF) /*!< All pins selected */
|
||||
|
||||
#define IS_GPIO_PIN(PIN) ((PIN) != (uint16_t)0x00)
|
||||
#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \
|
||||
((PIN) == GPIO_Pin_1) || \
|
||||
((PIN) == GPIO_Pin_2) || \
|
||||
((PIN) == GPIO_Pin_3) || \
|
||||
((PIN) == GPIO_Pin_4) || \
|
||||
((PIN) == GPIO_Pin_5) || \
|
||||
((PIN) == GPIO_Pin_6) || \
|
||||
((PIN) == GPIO_Pin_7) || \
|
||||
((PIN) == GPIO_Pin_8) || \
|
||||
((PIN) == GPIO_Pin_9) || \
|
||||
((PIN) == GPIO_Pin_10) || \
|
||||
((PIN) == GPIO_Pin_11) || \
|
||||
((PIN) == GPIO_Pin_12) || \
|
||||
((PIN) == GPIO_Pin_13) || \
|
||||
((PIN) == GPIO_Pin_14) || \
|
||||
((PIN) == GPIO_Pin_15))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Pin_sources
|
||||
* @{
|
||||
*/
|
||||
#define GPIO_PinSource0 ((uint8_t)0x00)
|
||||
#define GPIO_PinSource1 ((uint8_t)0x01)
|
||||
#define GPIO_PinSource2 ((uint8_t)0x02)
|
||||
#define GPIO_PinSource3 ((uint8_t)0x03)
|
||||
#define GPIO_PinSource4 ((uint8_t)0x04)
|
||||
#define GPIO_PinSource5 ((uint8_t)0x05)
|
||||
#define GPIO_PinSource6 ((uint8_t)0x06)
|
||||
#define GPIO_PinSource7 ((uint8_t)0x07)
|
||||
#define GPIO_PinSource8 ((uint8_t)0x08)
|
||||
#define GPIO_PinSource9 ((uint8_t)0x09)
|
||||
#define GPIO_PinSource10 ((uint8_t)0x0A)
|
||||
#define GPIO_PinSource11 ((uint8_t)0x0B)
|
||||
#define GPIO_PinSource12 ((uint8_t)0x0C)
|
||||
#define GPIO_PinSource13 ((uint8_t)0x0D)
|
||||
#define GPIO_PinSource14 ((uint8_t)0x0E)
|
||||
#define GPIO_PinSource15 ((uint8_t)0x0F)
|
||||
|
||||
#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \
|
||||
((PINSOURCE) == GPIO_PinSource1) || \
|
||||
((PINSOURCE) == GPIO_PinSource2) || \
|
||||
((PINSOURCE) == GPIO_PinSource3) || \
|
||||
((PINSOURCE) == GPIO_PinSource4) || \
|
||||
((PINSOURCE) == GPIO_PinSource5) || \
|
||||
((PINSOURCE) == GPIO_PinSource6) || \
|
||||
((PINSOURCE) == GPIO_PinSource7) || \
|
||||
((PINSOURCE) == GPIO_PinSource8) || \
|
||||
((PINSOURCE) == GPIO_PinSource9) || \
|
||||
((PINSOURCE) == GPIO_PinSource10) || \
|
||||
((PINSOURCE) == GPIO_PinSource11) || \
|
||||
((PINSOURCE) == GPIO_PinSource12) || \
|
||||
((PINSOURCE) == GPIO_PinSource13) || \
|
||||
((PINSOURCE) == GPIO_PinSource14) || \
|
||||
((PINSOURCE) == GPIO_PinSource15))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Alternat_function_selection_define
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief AF 0 selection
|
||||
*/
|
||||
#define GPIO_AF_RTC_50Hz ((uint8_t)0x00) /*!< RTC 50/60 Hz Alternate Function mapping */
|
||||
#define GPIO_AF_MCO ((uint8_t)0x00) /*!< MCO Alternate Function mapping */
|
||||
#define GPIO_AF_RTC_AF1 ((uint8_t)0x00) /*!< RTC_AF1 Alternate Function mapping */
|
||||
#define GPIO_AF_WKUP ((uint8_t)0x00) /*!< Wakeup (WKUP1, WKUP2 and WKUP3) Alternate Function mapping */
|
||||
#define GPIO_AF_SWJ ((uint8_t)0x00) /*!< SWJ (SW and JTAG) Alternate Function mapping */
|
||||
#define GPIO_AF_TRACE ((uint8_t)0x00) /*!< TRACE Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 1 selection
|
||||
*/
|
||||
#define GPIO_AF_TIM2 ((uint8_t)0x01) /*!< TIM2 Alternate Function mapping */
|
||||
/**
|
||||
* @brief AF 2 selection
|
||||
*/
|
||||
#define GPIO_AF_TIM3 ((uint8_t)0x02) /*!< TIM3 Alternate Function mapping */
|
||||
#define GPIO_AF_TIM4 ((uint8_t)0x02) /*!< TIM4 Alternate Function mapping */
|
||||
#define GPIO_AF_TIM5 ((uint8_t)0x02) /*!< TIM5 Alternate Function mapping */
|
||||
/**
|
||||
* @brief AF 3 selection
|
||||
*/
|
||||
#define GPIO_AF_TIM9 ((uint8_t)0x03) /*!< TIM9 Alternate Function mapping */
|
||||
#define GPIO_AF_TIM10 ((uint8_t)0x03) /*!< TIM10 Alternate Function mapping */
|
||||
#define GPIO_AF_TIM11 ((uint8_t)0x03) /*!< TIM11 Alternate Function mapping */
|
||||
/**
|
||||
* @brief AF 4 selection
|
||||
*/
|
||||
#define GPIO_AF_I2C1 ((uint8_t)0x04) /*!< I2C1 Alternate Function mapping */
|
||||
#define GPIO_AF_I2C2 ((uint8_t)0x04) /*!< I2C2 Alternate Function mapping */
|
||||
/**
|
||||
* @brief AF 5 selection
|
||||
*/
|
||||
#define GPIO_AF_SPI1 ((uint8_t)0x05) /*!< SPI1 Alternate Function mapping */
|
||||
#define GPIO_AF_SPI2 ((uint8_t)0x05) /*!< SPI2 Alternate Function mapping */
|
||||
/**
|
||||
* @brief AF 6 selection
|
||||
*/
|
||||
#define GPIO_AF_SPI3 ((uint8_t)0x06) /*!< SPI3 Alternate Function mapping */
|
||||
/**
|
||||
* @brief AF 7 selection
|
||||
*/
|
||||
#define GPIO_AF_USART1 ((uint8_t)0x07) /*!< USART1 Alternate Function mapping */
|
||||
#define GPIO_AF_USART2 ((uint8_t)0x07) /*!< USART2 Alternate Function mapping */
|
||||
#define GPIO_AF_USART3 ((uint8_t)0x07) /*!< USART3 Alternate Function mapping */
|
||||
/**
|
||||
* @brief AF 8 selection
|
||||
*/
|
||||
#define GPIO_AF_UART4 ((uint8_t)0x08) /*!< UART4 Alternate Function mapping */
|
||||
#define GPIO_AF_UART5 ((uint8_t)0x08) /*!< UART5 Alternate Function mapping */
|
||||
/**
|
||||
* @brief AF 10 selection
|
||||
*/
|
||||
#define GPIO_AF_USB ((uint8_t)0xA) /*!< USB Full speed device Alternate Function mapping */
|
||||
/**
|
||||
* @brief AF 11 selection
|
||||
*/
|
||||
#define GPIO_AF_LCD ((uint8_t)0x0B) /*!< LCD Alternate Function mapping */
|
||||
/**
|
||||
* @brief AF 12 selection
|
||||
*/
|
||||
#define GPIO_AF_FSMC ((uint8_t)0x0C) /*!< FSMC Alternate Function mapping */
|
||||
#define GPIO_AF_SDIO ((uint8_t)0x0C) /*!< SDIO Alternate Function mapping */
|
||||
/**
|
||||
* @brief AF 14 selection
|
||||
*/
|
||||
#define GPIO_AF_RI ((uint8_t)0x0E) /*!< RI Alternate Function mapping */
|
||||
|
||||
/**
|
||||
* @brief AF 15 selection
|
||||
*/
|
||||
#define GPIO_AF_EVENTOUT ((uint8_t)0x0F) /*!< EVENTOUT Alternate Function mapping */
|
||||
|
||||
#define IS_GPIO_AF(AF) (((AF) == GPIO_AF_RTC_50Hz) || ((AF) == GPIO_AF_MCO) || \
|
||||
((AF) == GPIO_AF_RTC_AF1) || ((AF) == GPIO_AF_WKUP) || \
|
||||
((AF) == GPIO_AF_SWJ) || ((AF) == GPIO_AF_TRACE) || \
|
||||
((AF) == GPIO_AF_TIM2) || ((AF)== GPIO_AF_TIM3) || \
|
||||
((AF) == GPIO_AF_TIM4) || ((AF)== GPIO_AF_TIM9) || \
|
||||
((AF) == GPIO_AF_TIM10) || ((AF)== GPIO_AF_TIM11) || \
|
||||
((AF) == GPIO_AF_I2C1) || ((AF) == GPIO_AF_I2C2) || \
|
||||
((AF) == GPIO_AF_SPI1) || ((AF) == GPIO_AF_SPI2) || \
|
||||
((AF) == GPIO_AF_USART1) || ((AF) == GPIO_AF_USART2) || \
|
||||
((AF) == GPIO_AF_USART3) || ((AF) == GPIO_AF_USB) || \
|
||||
((AF) == GPIO_AF_LCD) || ((AF) == GPIO_AF_RI) || \
|
||||
((AF) == GPIO_AF_TIM5) || ((AF) == GPIO_AF_SPI3) || \
|
||||
((AF) == GPIO_AF_UART4) || ((AF) == GPIO_AF_UART5) || \
|
||||
((AF) == GPIO_AF_FSMC) || ((AF) == GPIO_AF_SDIO) || \
|
||||
((AF) == GPIO_AF_EVENTOUT))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Legacy
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define GPIO_Mode_AIN GPIO_Mode_AN
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
|
||||
/* Function used to set the GPIO configuration to the default reset state ****/
|
||||
void GPIO_DeInit(GPIO_TypeDef* GPIOx);
|
||||
|
||||
/* Initialization and Configuration functions *********************************/
|
||||
void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct);
|
||||
void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct);
|
||||
void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
|
||||
|
||||
/* GPIO Read and Write functions **********************************************/
|
||||
uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
|
||||
uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx);
|
||||
uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
|
||||
uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx);
|
||||
void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
|
||||
void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
|
||||
void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal);
|
||||
void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal);
|
||||
void GPIO_ToggleBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
|
||||
|
||||
/* GPIO Alternate functions configuration functions ***************************/
|
||||
void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__STM32L1xx_GPIO_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,703 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32l1xx_i2c.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.1
|
||||
* @date 05-March-2012
|
||||
* @brief This file contains all the functions prototypes for the I2C firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32L1xx_I2C_H
|
||||
#define __STM32L1xx_I2C_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32l1xx.h"
|
||||
|
||||
/** @addtogroup STM32L1xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup I2C
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief I2C Init structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t I2C_ClockSpeed; /*!< Specifies the clock frequency.
|
||||
This parameter must be set to a value lower than 400kHz */
|
||||
|
||||
uint16_t I2C_Mode; /*!< Specifies the I2C mode.
|
||||
This parameter can be a value of @ref I2C_mode */
|
||||
|
||||
uint16_t I2C_DutyCycle; /*!< Specifies the I2C fast mode duty cycle.
|
||||
This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */
|
||||
|
||||
uint16_t I2C_OwnAddress1; /*!< Specifies the first device own address.
|
||||
This parameter can be a 7-bit or 10-bit address. */
|
||||
|
||||
uint16_t I2C_Ack; /*!< Enables or disables the acknowledgement.
|
||||
This parameter can be a value of @ref I2C_acknowledgement */
|
||||
|
||||
uint16_t I2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged.
|
||||
This parameter can be a value of @ref I2C_acknowledged_address */
|
||||
}I2C_InitTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
|
||||
/** @defgroup I2C_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) || \
|
||||
((PERIPH) == I2C2))
|
||||
/** @defgroup I2C_mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_Mode_I2C ((uint16_t)0x0000)
|
||||
#define I2C_Mode_SMBusDevice ((uint16_t)0x0002)
|
||||
#define I2C_Mode_SMBusHost ((uint16_t)0x000A)
|
||||
#define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || \
|
||||
((MODE) == I2C_Mode_SMBusDevice) || \
|
||||
((MODE) == I2C_Mode_SMBusHost))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_duty_cycle_in_fast_mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /*!< I2C fast mode Tlow/Thigh = 16/9 */
|
||||
#define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /*!< I2C fast mode Tlow/Thigh = 2 */
|
||||
#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DutyCycle_16_9) || \
|
||||
((CYCLE) == I2C_DutyCycle_2))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_acknowledgement
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_Ack_Enable ((uint16_t)0x0400)
|
||||
#define I2C_Ack_Disable ((uint16_t)0x0000)
|
||||
#define IS_I2C_ACK_STATE(STATE) (((STATE) == I2C_Ack_Enable) || \
|
||||
((STATE) == I2C_Ack_Disable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_transfer_direction
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_Direction_Transmitter ((uint8_t)0x00)
|
||||
#define I2C_Direction_Receiver ((uint8_t)0x01)
|
||||
#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \
|
||||
((DIRECTION) == I2C_Direction_Receiver))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_acknowledged_address
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000)
|
||||
#define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000)
|
||||
#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \
|
||||
((ADDRESS) == I2C_AcknowledgedAddress_10bit))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_registers
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_Register_CR1 ((uint8_t)0x00)
|
||||
#define I2C_Register_CR2 ((uint8_t)0x04)
|
||||
#define I2C_Register_OAR1 ((uint8_t)0x08)
|
||||
#define I2C_Register_OAR2 ((uint8_t)0x0C)
|
||||
#define I2C_Register_DR ((uint8_t)0x10)
|
||||
#define I2C_Register_SR1 ((uint8_t)0x14)
|
||||
#define I2C_Register_SR2 ((uint8_t)0x18)
|
||||
#define I2C_Register_CCR ((uint8_t)0x1C)
|
||||
#define I2C_Register_TRISE ((uint8_t)0x20)
|
||||
#define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \
|
||||
((REGISTER) == I2C_Register_CR2) || \
|
||||
((REGISTER) == I2C_Register_OAR1) || \
|
||||
((REGISTER) == I2C_Register_OAR2) || \
|
||||
((REGISTER) == I2C_Register_DR) || \
|
||||
((REGISTER) == I2C_Register_SR1) || \
|
||||
((REGISTER) == I2C_Register_SR2) || \
|
||||
((REGISTER) == I2C_Register_CCR) || \
|
||||
((REGISTER) == I2C_Register_TRISE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_SMBus_alert_pin_level
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_SMBusAlert_Low ((uint16_t)0x2000)
|
||||
#define I2C_SMBusAlert_High ((uint16_t)0xDFFF)
|
||||
#define IS_I2C_SMBUS_ALERT(ALERT) (((ALERT) == I2C_SMBusAlert_Low) || \
|
||||
((ALERT) == I2C_SMBusAlert_High))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_PEC_position
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_PECPosition_Next ((uint16_t)0x0800)
|
||||
#define I2C_PECPosition_Current ((uint16_t)0xF7FF)
|
||||
#define IS_I2C_PEC_POSITION(POSITION) (((POSITION) == I2C_PECPosition_Next) || \
|
||||
((POSITION) == I2C_PECPosition_Current))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_NACK_position
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_NACKPosition_Next ((uint16_t)0x0800)
|
||||
#define I2C_NACKPosition_Current ((uint16_t)0xF7FF)
|
||||
#define IS_I2C_NACK_POSITION(POSITION) (((POSITION) == I2C_NACKPosition_Next) || \
|
||||
((POSITION) == I2C_NACKPosition_Current))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_interrupts_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_IT_BUF ((uint16_t)0x0400)
|
||||
#define I2C_IT_EVT ((uint16_t)0x0200)
|
||||
#define I2C_IT_ERR ((uint16_t)0x0100)
|
||||
#define IS_I2C_CONFIG_IT(IT) ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_interrupts_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2C_IT_SMBALERT ((uint32_t)0x01008000)
|
||||
#define I2C_IT_TIMEOUT ((uint32_t)0x01004000)
|
||||
#define I2C_IT_PECERR ((uint32_t)0x01001000)
|
||||
#define I2C_IT_OVR ((uint32_t)0x01000800)
|
||||
#define I2C_IT_AF ((uint32_t)0x01000400)
|
||||
#define I2C_IT_ARLO ((uint32_t)0x01000200)
|
||||
#define I2C_IT_BERR ((uint32_t)0x01000100)
|
||||
#define I2C_IT_TXE ((uint32_t)0x06000080)
|
||||
#define I2C_IT_RXNE ((uint32_t)0x06000040)
|
||||
#define I2C_IT_STOPF ((uint32_t)0x02000010)
|
||||
#define I2C_IT_ADD10 ((uint32_t)0x02000008)
|
||||
#define I2C_IT_BTF ((uint32_t)0x02000004)
|
||||
#define I2C_IT_ADDR ((uint32_t)0x02000002)
|
||||
#define I2C_IT_SB ((uint32_t)0x02000001)
|
||||
|
||||
#define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint16_t)0x20FF) == 0x00) && ((IT) != (uint16_t)0x00))
|
||||
|
||||
#define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_SMBALERT) || ((IT) == I2C_IT_TIMEOUT) || \
|
||||
((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_OVR) || \
|
||||
((IT) == I2C_IT_AF) || ((IT) == I2C_IT_ARLO) || \
|
||||
((IT) == I2C_IT_BERR) || ((IT) == I2C_IT_TXE) || \
|
||||
((IT) == I2C_IT_RXNE) || ((IT) == I2C_IT_STOPF) || \
|
||||
((IT) == I2C_IT_ADD10) || ((IT) == I2C_IT_BTF) || \
|
||||
((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_SB))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_flags_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief SR2 register flags
|
||||
*/
|
||||
|
||||
#define I2C_FLAG_DUALF ((uint32_t)0x00800000)
|
||||
#define I2C_FLAG_SMBHOST ((uint32_t)0x00400000)
|
||||
#define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00200000)
|
||||
#define I2C_FLAG_GENCALL ((uint32_t)0x00100000)
|
||||
#define I2C_FLAG_TRA ((uint32_t)0x00040000)
|
||||
#define I2C_FLAG_BUSY ((uint32_t)0x00020000)
|
||||
#define I2C_FLAG_MSL ((uint32_t)0x00010000)
|
||||
|
||||
/**
|
||||
* @brief SR1 register flags
|
||||
*/
|
||||
|
||||
#define I2C_FLAG_SMBALERT ((uint32_t)0x10008000)
|
||||
#define I2C_FLAG_TIMEOUT ((uint32_t)0x10004000)
|
||||
#define I2C_FLAG_PECERR ((uint32_t)0x10001000)
|
||||
#define I2C_FLAG_OVR ((uint32_t)0x10000800)
|
||||
#define I2C_FLAG_AF ((uint32_t)0x10000400)
|
||||
#define I2C_FLAG_ARLO ((uint32_t)0x10000200)
|
||||
#define I2C_FLAG_BERR ((uint32_t)0x10000100)
|
||||
#define I2C_FLAG_TXE ((uint32_t)0x10000080)
|
||||
#define I2C_FLAG_RXNE ((uint32_t)0x10000040)
|
||||
#define I2C_FLAG_STOPF ((uint32_t)0x10000010)
|
||||
#define I2C_FLAG_ADD10 ((uint32_t)0x10000008)
|
||||
#define I2C_FLAG_BTF ((uint32_t)0x10000004)
|
||||
#define I2C_FLAG_ADDR ((uint32_t)0x10000002)
|
||||
#define I2C_FLAG_SB ((uint32_t)0x10000001)
|
||||
|
||||
#define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0x20FF) == 0x00) && ((FLAG) != (uint16_t)0x00))
|
||||
|
||||
#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_DUALF) || ((FLAG) == I2C_FLAG_SMBHOST) || \
|
||||
((FLAG) == I2C_FLAG_SMBDEFAULT) || ((FLAG) == I2C_FLAG_GENCALL) || \
|
||||
((FLAG) == I2C_FLAG_TRA) || ((FLAG) == I2C_FLAG_BUSY) || \
|
||||
((FLAG) == I2C_FLAG_MSL) || ((FLAG) == I2C_FLAG_SMBALERT) || \
|
||||
((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_PECERR) || \
|
||||
((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_AF) || \
|
||||
((FLAG) == I2C_FLAG_ARLO) || ((FLAG) == I2C_FLAG_BERR) || \
|
||||
((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_RXNE) || \
|
||||
((FLAG) == I2C_FLAG_STOPF) || ((FLAG) == I2C_FLAG_ADD10) || \
|
||||
((FLAG) == I2C_FLAG_BTF) || ((FLAG) == I2C_FLAG_ADDR) || \
|
||||
((FLAG) == I2C_FLAG_SB))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_Events
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
===============================================================================
|
||||
I2C Master Events (Events grouped in order of communication)
|
||||
===============================================================================
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Communication start
|
||||
*
|
||||
* After sending the START condition (I2C_GenerateSTART() function) the master
|
||||
* has to wait for this event. It means that the Start condition has been correctly
|
||||
* released on the I2C bus (the bus is free, no other devices is communicating).
|
||||
*
|
||||
*/
|
||||
/* --EV5 */
|
||||
#define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */
|
||||
|
||||
/**
|
||||
* @brief Address Acknowledge
|
||||
*
|
||||
* After checking on EV5 (start condition correctly released on the bus), the
|
||||
* master sends the address of the slave(s) with which it will communicate
|
||||
* (I2C_Send7bitAddress() function, it also determines the direction of the communication:
|
||||
* Master transmitter or Receiver). Then the master has to wait that a slave acknowledges
|
||||
* his address. If an acknowledge is sent on the bus, one of the following events will
|
||||
* be set:
|
||||
*
|
||||
* 1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED
|
||||
* event is set.
|
||||
*
|
||||
* 2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED
|
||||
* is set
|
||||
*
|
||||
* 3) In case of 10-Bit addressing mode, the master (just after generating the START
|
||||
* and checking on EV5) has to send the header of 10-bit addressing mode (I2C_SendData()
|
||||
* function). Then master should wait on EV9. It means that the 10-bit addressing
|
||||
* header has been correctly sent on the bus. Then master should send the second part of
|
||||
* the 10-bit address (LSB) using the function I2C_Send7bitAddress(). Then master
|
||||
* should wait for event EV6.
|
||||
*
|
||||
*/
|
||||
|
||||
/* --EV6 */
|
||||
#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */
|
||||
#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */
|
||||
/* --EV9 */
|
||||
#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */
|
||||
|
||||
/**
|
||||
* @brief Communication events
|
||||
*
|
||||
* If a communication is established (START condition generated and slave address
|
||||
* acknowledged) then the master has to check on one of the following events for
|
||||
* communication procedures:
|
||||
*
|
||||
* 1) Master Receiver mode: The master has to wait on the event EV7 then to read
|
||||
* the data received from the slave (I2C_ReceiveData() function).
|
||||
*
|
||||
* 2) Master Transmitter mode: The master has to send data (I2C_SendData()
|
||||
* function) then to wait on event EV8 or EV8_2.
|
||||
* These two events are similar:
|
||||
* - EV8 means that the data has been written in the data register and is
|
||||
* being shifted out.
|
||||
* - EV8_2 means that the data has been physically shifted out and output
|
||||
* on the bus.
|
||||
* In most cases, using EV8 is sufficient for the application.
|
||||
* Using EV8_2 leads to a slower communication but ensure more reliable test.
|
||||
* EV8_2 is also more suitable than EV8 for testing on the last data transmission
|
||||
* (before Stop condition generation).
|
||||
*
|
||||
* @note In case the user software does not guarantee that this event EV7 is
|
||||
* managed before the current byte end of transfer, then user may check on EV7
|
||||
* and BTF flag at the same time (ie. (I2C_EVENT_MASTER_BYTE_RECEIVED | I2C_FLAG_BTF)).
|
||||
* In this case the communication may be slower.
|
||||
*
|
||||
*/
|
||||
|
||||
/* Master RECEIVER mode -----------------------------*/
|
||||
/* --EV7 */
|
||||
#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */
|
||||
|
||||
/* Master TRANSMITTER mode --------------------------*/
|
||||
/* --EV8 */
|
||||
#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */
|
||||
/* --EV8_2 */
|
||||
#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */
|
||||
|
||||
|
||||
/**
|
||||
===============================================================================
|
||||
I2C Slave Events (Events grouped in order of communication)
|
||||
===============================================================================
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @brief Communication start events
|
||||
*
|
||||
* Wait on one of these events at the start of the communication. It means that
|
||||
* the I2C peripheral detected a Start condition on the bus (generated by master
|
||||
* device) followed by the peripheral address. The peripheral generates an ACK
|
||||
* condition on the bus (if the acknowledge feature is enabled through function
|
||||
* I2C_AcknowledgeConfig()) and the events listed above are set :
|
||||
*
|
||||
* 1) In normal case (only one address managed by the slave), when the address
|
||||
* sent by the master matches the own address of the peripheral (configured by
|
||||
* I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set
|
||||
* (where XXX could be TRANSMITTER or RECEIVER).
|
||||
*
|
||||
* 2) In case the address sent by the master matches the second address of the
|
||||
* peripheral (configured by the function I2C_OwnAddress2Config() and enabled
|
||||
* by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED
|
||||
* (where XXX could be TRANSMITTER or RECEIVER) are set.
|
||||
*
|
||||
* 3) In case the address sent by the master is General Call (address 0x00) and
|
||||
* if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd())
|
||||
* the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED.
|
||||
*
|
||||
*/
|
||||
|
||||
/* --EV1 (all the events below are variants of EV1) */
|
||||
/* 1) Case of One Single Address managed by the slave */
|
||||
#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */
|
||||
#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */
|
||||
|
||||
/* 2) Case of Dual address managed by the slave */
|
||||
#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */
|
||||
#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */
|
||||
|
||||
/* 3) Case of General Call enabled for the slave */
|
||||
#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */
|
||||
|
||||
/**
|
||||
* @brief Communication events
|
||||
*
|
||||
* Wait on one of these events when EV1 has already been checked and:
|
||||
*
|
||||
* - Slave RECEIVER mode:
|
||||
* - EV2: When the application is expecting a data byte to be received.
|
||||
* - EV4: When the application is expecting the end of the communication: master
|
||||
* sends a stop condition and data transmission is stopped.
|
||||
*
|
||||
* - Slave Transmitter mode:
|
||||
* - EV3: When a byte has been transmitted by the slave and the application is expecting
|
||||
* the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and
|
||||
* I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. The second one can optionally be
|
||||
* used when the user software doesn't guarantee the EV3 is managed before the
|
||||
* current byte end of transfer.
|
||||
* - EV3_2: When the master sends a NACK in order to tell slave that data transmission
|
||||
* shall end (before sending the STOP condition). In this case slave has to stop sending
|
||||
* data bytes and expect a Stop condition on the bus.
|
||||
*
|
||||
* @note In case the user software does not guarantee that the event EV2 is
|
||||
* managed before the current byte end of transfer, then user may check on EV2
|
||||
* and BTF flag at the same time (ie. (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_BTF)).
|
||||
* In this case the communication may be slower.
|
||||
*
|
||||
*/
|
||||
|
||||
/* Slave RECEIVER mode --------------------------*/
|
||||
/* --EV2 */
|
||||
#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */
|
||||
/* --EV4 */
|
||||
#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */
|
||||
|
||||
/* Slave TRANSMITTER mode -----------------------*/
|
||||
/* --EV3 */
|
||||
#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */
|
||||
#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */
|
||||
/* --EV3_2 */
|
||||
#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */
|
||||
|
||||
/*
|
||||
===============================================================================
|
||||
End of Events Description
|
||||
===============================================================================
|
||||
*/
|
||||
|
||||
#define IS_I2C_EVENT(EVENT) (((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || \
|
||||
((EVENT) == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || \
|
||||
((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED) || \
|
||||
((EVENT) == I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED) || \
|
||||
((EVENT) == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED) || \
|
||||
((EVENT) == I2C_EVENT_SLAVE_BYTE_RECEIVED) || \
|
||||
((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF)) || \
|
||||
((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL)) || \
|
||||
((EVENT) == I2C_EVENT_SLAVE_BYTE_TRANSMITTED) || \
|
||||
((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF)) || \
|
||||
((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL)) || \
|
||||
((EVENT) == I2C_EVENT_SLAVE_STOP_DETECTED) || \
|
||||
((EVENT) == I2C_EVENT_MASTER_MODE_SELECT) || \
|
||||
((EVENT) == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) || \
|
||||
((EVENT) == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || \
|
||||
((EVENT) == I2C_EVENT_MASTER_BYTE_RECEIVED) || \
|
||||
((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || \
|
||||
((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTING) || \
|
||||
((EVENT) == I2C_EVENT_MASTER_MODE_ADDRESS10) || \
|
||||
((EVENT) == I2C_EVENT_SLAVE_ACK_FAILURE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_own_address1
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x3FF)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup I2C_clock_speed
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 400000))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
|
||||
/* Function used to set the I2C configuration to the default reset state *****/
|
||||
void I2C_DeInit(I2C_TypeDef* I2Cx);
|
||||
|
||||
/* Initialization and Configuration functions *********************************/
|
||||
void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct);
|
||||
void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct);
|
||||
void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address);
|
||||
void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert);
|
||||
void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle);
|
||||
void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction);
|
||||
|
||||
/* Data transfers functions ***************************************************/
|
||||
void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data);
|
||||
uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx);
|
||||
void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition);
|
||||
|
||||
/* PEC management functions ***************************************************/
|
||||
void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition);
|
||||
void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx);
|
||||
|
||||
/* DMA transfers management functions *****************************************/
|
||||
void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
|
||||
|
||||
|
||||
/* Interrupts, events and flags management functions **************************/
|
||||
uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register);
|
||||
void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState);
|
||||
|
||||
/*
|
||||
|
||||
===============================================================================
|
||||
I2C State Monitoring Functions
|
||||
===============================================================================
|
||||
This I2C driver provides three different ways for I2C state monitoring
|
||||
depending on the application requirements and constraints:
|
||||
|
||||
|
||||
1. Basic state monitoring (Using I2C_CheckEvent() function)
|
||||
-----------------------------------------------------------
|
||||
It compares the status registers (SR1 and SR2) content to a given event
|
||||
(can be the combination of one or more flags).
|
||||
It returns SUCCESS if the current status includes the given flags
|
||||
and returns ERROR if one or more flags are missing in the current status.
|
||||
|
||||
- When to use
|
||||
- This function is suitable for most applications as well as for startup
|
||||
activity since the events are fully described in the product reference
|
||||
manual (RM0038).
|
||||
- It is also suitable for users who need to define their own events.
|
||||
|
||||
- Limitations
|
||||
- If an error occurs (ie. error flags are set besides to the monitored
|
||||
flags), the I2C_CheckEvent() function may return SUCCESS despite
|
||||
the communication hold or corrupted real state.
|
||||
In this case, it is advised to use error interrupts to monitor
|
||||
the error events and handle them in the interrupt IRQ handler.
|
||||
|
||||
Note
|
||||
For error management, it is advised to use the following functions:
|
||||
- I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR).
|
||||
- I2Cx_ER_IRQHandler() which is called when the error interrupt occurs.
|
||||
Where x is the peripheral instance (I2C1, I2C2 ...)
|
||||
- I2C_GetFlagStatus() or I2C_GetITStatus() to be called into the
|
||||
I2Cx_ER_IRQHandler() function in order to determine which error occurred.
|
||||
- I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd()
|
||||
and/or I2C_GenerateStop() in order to clear the error flag and source
|
||||
and return to correct communciation status.
|
||||
|
||||
|
||||
2. Advanced state monitoring (Using the function I2C_GetLastEvent())
|
||||
--------------------------------------------------------------------
|
||||
Using the function I2C_GetLastEvent() which returns the image of both status
|
||||
registers in a single word (uint32_t) (Status Register 2 value is shifted left
|
||||
by 16 bits and concatenated to Status Register 1).
|
||||
|
||||
- When to use
|
||||
- This function is suitable for the same applications above but it
|
||||
allows to overcome the mentioned limitation of I2C_GetFlagStatus()
|
||||
function.
|
||||
- The returned value could be compared to events already defined in
|
||||
the library (stm32l1xx_i2c.h) or to custom values defined by user.
|
||||
This function is suitable when multiple flags are monitored at the
|
||||
same time.
|
||||
- At the opposite of I2C_CheckEvent() function, this function allows
|
||||
user to choose when an event is accepted (when all events flags are
|
||||
set and no other flags are set or just when the needed flags are set
|
||||
like I2C_CheckEvent() function.
|
||||
|
||||
- Limitations
|
||||
- User may need to define his own events.
|
||||
- Same remark concerning the error management is applicable for this
|
||||
function if user decides to check only regular communication flags
|
||||
(and ignores error flags).
|
||||
|
||||
|
||||
3. Flag-based state monitoring (Using the function I2C_GetFlagStatus())
|
||||
-----------------------------------------------------------------------
|
||||
|
||||
Using the function I2C_GetFlagStatus() which simply returns the status of
|
||||
one single flag (ie. I2C_FLAG_RXNE ...).
|
||||
|
||||
- When to use
|
||||
- This function could be used for specific applications or in debug
|
||||
phase.
|
||||
- It is suitable when only one flag checking is needed (most I2C
|
||||
events are monitored through multiple flags).
|
||||
- Limitations:
|
||||
- When calling this function, the Status register is accessed.
|
||||
Some flags are cleared when the status register is accessed.
|
||||
So checking the status of one Flag, may clear other ones.
|
||||
- Function may need to be called twice or more in order to monitor
|
||||
one single event.
|
||||
|
||||
For detailed description of Events, please refer to section I2C_Events in
|
||||
stm32l1xx_i2c.h file.
|
||||
|
||||
*/
|
||||
|
||||
/*
|
||||
===============================================================================
|
||||
1. Basic state monitoring
|
||||
===============================================================================
|
||||
*/
|
||||
ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT);
|
||||
/*
|
||||
===============================================================================
|
||||
2. Advanced state monitoring
|
||||
===============================================================================
|
||||
*/
|
||||
uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx);
|
||||
/*
|
||||
===============================================================================
|
||||
3. Flag-based state monitoring
|
||||
===============================================================================
|
||||
*/
|
||||
FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
|
||||
|
||||
|
||||
void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
|
||||
ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
|
||||
void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__STM32L1xx_I2C_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,134 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32l1xx_iwdg.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.1
|
||||
* @date 05-March-2012
|
||||
* @brief This file contains all the functions prototypes for the IWDG
|
||||
* firmware library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32L1xx_IWDG_H
|
||||
#define __STM32L1xx_IWDG_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32l1xx.h"
|
||||
|
||||
/** @addtogroup STM32L1xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup IWDG
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup IWDG_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_WriteAccess
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IWDG_WriteAccess_Enable ((uint16_t)0x5555)
|
||||
#define IWDG_WriteAccess_Disable ((uint16_t)0x0000)
|
||||
#define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \
|
||||
((ACCESS) == IWDG_WriteAccess_Disable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_prescaler
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IWDG_Prescaler_4 ((uint8_t)0x00)
|
||||
#define IWDG_Prescaler_8 ((uint8_t)0x01)
|
||||
#define IWDG_Prescaler_16 ((uint8_t)0x02)
|
||||
#define IWDG_Prescaler_32 ((uint8_t)0x03)
|
||||
#define IWDG_Prescaler_64 ((uint8_t)0x04)
|
||||
#define IWDG_Prescaler_128 ((uint8_t)0x05)
|
||||
#define IWDG_Prescaler_256 ((uint8_t)0x06)
|
||||
#define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4) || \
|
||||
((PRESCALER) == IWDG_Prescaler_8) || \
|
||||
((PRESCALER) == IWDG_Prescaler_16) || \
|
||||
((PRESCALER) == IWDG_Prescaler_32) || \
|
||||
((PRESCALER) == IWDG_Prescaler_64) || \
|
||||
((PRESCALER) == IWDG_Prescaler_128)|| \
|
||||
((PRESCALER) == IWDG_Prescaler_256))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_Flag
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IWDG_FLAG_PVU ((uint16_t)0x0001)
|
||||
#define IWDG_FLAG_RVU ((uint16_t)0x0002)
|
||||
#define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU))
|
||||
#define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
|
||||
/* Prescaler and Counter configuration functions ******************************/
|
||||
void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess);
|
||||
void IWDG_SetPrescaler(uint8_t IWDG_Prescaler);
|
||||
void IWDG_SetReload(uint16_t Reload);
|
||||
void IWDG_ReloadCounter(void);
|
||||
|
||||
/* IWDG activation function ***************************************************/
|
||||
void IWDG_Enable(void);
|
||||
|
||||
/* Flag management function ***************************************************/
|
||||
FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32L1xx_IWDG_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,452 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32l1xx_lcd.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.1
|
||||
* @date 05-March-2012
|
||||
* @brief This file contains all the functions prototypes for the LCD firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32L1xx_LCD_H
|
||||
#define __STM32L1xx_LCD_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32l1xx.h"
|
||||
|
||||
/** @addtogroup STM32L1xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup LCD
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief LCD Init structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t LCD_Prescaler; /*!< Configures the LCD Prescaler.
|
||||
This parameter can be one value of @ref LCD_Prescaler */
|
||||
uint32_t LCD_Divider; /*!< Configures the LCD Divider.
|
||||
This parameter can be one value of @ref LCD_Divider */
|
||||
uint32_t LCD_Duty; /*!< Configures the LCD Duty.
|
||||
This parameter can be one value of @ref LCD_Duty */
|
||||
uint32_t LCD_Bias; /*!< Configures the LCD Bias.
|
||||
This parameter can be one value of @ref LCD_Bias */
|
||||
uint32_t LCD_VoltageSource; /*!< Selects the LCD Voltage source.
|
||||
This parameter can be one value of @ref LCD_Voltage_Source */
|
||||
}LCD_InitTypeDef;
|
||||
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup LCD_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup LCD_Prescaler
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define LCD_Prescaler_1 ((uint32_t)0x00000000) /*!< CLKPS = LCDCLK */
|
||||
#define LCD_Prescaler_2 ((uint32_t)0x00400000) /*!< CLKPS = LCDCLK/2 */
|
||||
#define LCD_Prescaler_4 ((uint32_t)0x00800000) /*!< CLKPS = LCDCLK/4 */
|
||||
#define LCD_Prescaler_8 ((uint32_t)0x00C00000) /*!< CLKPS = LCDCLK/8 */
|
||||
#define LCD_Prescaler_16 ((uint32_t)0x01000000) /*!< CLKPS = LCDCLK/16 */
|
||||
#define LCD_Prescaler_32 ((uint32_t)0x01400000) /*!< CLKPS = LCDCLK/32 */
|
||||
#define LCD_Prescaler_64 ((uint32_t)0x01800000) /*!< CLKPS = LCDCLK/64 */
|
||||
#define LCD_Prescaler_128 ((uint32_t)0x01C00000) /*!< CLKPS = LCDCLK/128 */
|
||||
#define LCD_Prescaler_256 ((uint32_t)0x02000000) /*!< CLKPS = LCDCLK/256 */
|
||||
#define LCD_Prescaler_512 ((uint32_t)0x02400000) /*!< CLKPS = LCDCLK/512 */
|
||||
#define LCD_Prescaler_1024 ((uint32_t)0x02800000) /*!< CLKPS = LCDCLK/1024 */
|
||||
#define LCD_Prescaler_2048 ((uint32_t)0x02C00000) /*!< CLKPS = LCDCLK/2048 */
|
||||
#define LCD_Prescaler_4096 ((uint32_t)0x03000000) /*!< CLKPS = LCDCLK/4096 */
|
||||
#define LCD_Prescaler_8192 ((uint32_t)0x03400000) /*!< CLKPS = LCDCLK/8192 */
|
||||
#define LCD_Prescaler_16384 ((uint32_t)0x03800000) /*!< CLKPS = LCDCLK/16384 */
|
||||
#define LCD_Prescaler_32768 ((uint32_t)0x03C00000) /*!< CLKPS = LCDCLK/32768 */
|
||||
|
||||
#define IS_LCD_PRESCALER(PRESCALER) (((PRESCALER) == LCD_Prescaler_1) || \
|
||||
((PRESCALER) == LCD_Prescaler_2) || \
|
||||
((PRESCALER) == LCD_Prescaler_4) || \
|
||||
((PRESCALER) == LCD_Prescaler_8) || \
|
||||
((PRESCALER) == LCD_Prescaler_16) || \
|
||||
((PRESCALER) == LCD_Prescaler_32) || \
|
||||
((PRESCALER) == LCD_Prescaler_64) || \
|
||||
((PRESCALER) == LCD_Prescaler_128) || \
|
||||
((PRESCALER) == LCD_Prescaler_256) || \
|
||||
((PRESCALER) == LCD_Prescaler_512) || \
|
||||
((PRESCALER) == LCD_Prescaler_1024) || \
|
||||
((PRESCALER) == LCD_Prescaler_2048) || \
|
||||
((PRESCALER) == LCD_Prescaler_4096) || \
|
||||
((PRESCALER) == LCD_Prescaler_8192) || \
|
||||
((PRESCALER) == LCD_Prescaler_16384) || \
|
||||
((PRESCALER) == LCD_Prescaler_32768))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LCD_Divider
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define LCD_Divider_16 ((uint32_t)0x00000000) /*!< LCD frequency = CLKPS/16 */
|
||||
#define LCD_Divider_17 ((uint32_t)0x00040000) /*!< LCD frequency = CLKPS/17 */
|
||||
#define LCD_Divider_18 ((uint32_t)0x00080000) /*!< LCD frequency = CLKPS/18 */
|
||||
#define LCD_Divider_19 ((uint32_t)0x000C0000) /*!< LCD frequency = CLKPS/19 */
|
||||
#define LCD_Divider_20 ((uint32_t)0x00100000) /*!< LCD frequency = CLKPS/20 */
|
||||
#define LCD_Divider_21 ((uint32_t)0x00140000) /*!< LCD frequency = CLKPS/21 */
|
||||
#define LCD_Divider_22 ((uint32_t)0x00180000) /*!< LCD frequency = CLKPS/22 */
|
||||
#define LCD_Divider_23 ((uint32_t)0x001C0000) /*!< LCD frequency = CLKPS/23 */
|
||||
#define LCD_Divider_24 ((uint32_t)0x00200000) /*!< LCD frequency = CLKPS/24 */
|
||||
#define LCD_Divider_25 ((uint32_t)0x00240000) /*!< LCD frequency = CLKPS/25 */
|
||||
#define LCD_Divider_26 ((uint32_t)0x00280000) /*!< LCD frequency = CLKPS/26 */
|
||||
#define LCD_Divider_27 ((uint32_t)0x002C0000) /*!< LCD frequency = CLKPS/27 */
|
||||
#define LCD_Divider_28 ((uint32_t)0x00300000) /*!< LCD frequency = CLKPS/28 */
|
||||
#define LCD_Divider_29 ((uint32_t)0x00340000) /*!< LCD frequency = CLKPS/29 */
|
||||
#define LCD_Divider_30 ((uint32_t)0x00380000) /*!< LCD frequency = CLKPS/30 */
|
||||
#define LCD_Divider_31 ((uint32_t)0x003C0000) /*!< LCD frequency = CLKPS/31 */
|
||||
|
||||
#define IS_LCD_DIVIDER(DIVIDER) (((DIVIDER) == LCD_Divider_16) || \
|
||||
((DIVIDER) == LCD_Divider_17) || \
|
||||
((DIVIDER) == LCD_Divider_18) || \
|
||||
((DIVIDER) == LCD_Divider_19) || \
|
||||
((DIVIDER) == LCD_Divider_20) || \
|
||||
((DIVIDER) == LCD_Divider_21) || \
|
||||
((DIVIDER) == LCD_Divider_22) || \
|
||||
((DIVIDER) == LCD_Divider_23) || \
|
||||
((DIVIDER) == LCD_Divider_24) || \
|
||||
((DIVIDER) == LCD_Divider_25) || \
|
||||
((DIVIDER) == LCD_Divider_26) || \
|
||||
((DIVIDER) == LCD_Divider_27) || \
|
||||
((DIVIDER) == LCD_Divider_28) || \
|
||||
((DIVIDER) == LCD_Divider_29) || \
|
||||
((DIVIDER) == LCD_Divider_30) || \
|
||||
((DIVIDER) == LCD_Divider_31))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup LCD_Duty
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define LCD_Duty_Static ((uint32_t)0x00000000) /*!< Static duty */
|
||||
#define LCD_Duty_1_2 ((uint32_t)0x00000004) /*!< 1/2 duty */
|
||||
#define LCD_Duty_1_3 ((uint32_t)0x00000008) /*!< 1/3 duty */
|
||||
#define LCD_Duty_1_4 ((uint32_t)0x0000000C) /*!< 1/4 duty */
|
||||
#define LCD_Duty_1_8 ((uint32_t)0x00000010) /*!< 1/4 duty */
|
||||
|
||||
#define IS_LCD_DUTY(DUTY) (((DUTY) == LCD_Duty_Static) || \
|
||||
((DUTY) == LCD_Duty_1_2) || \
|
||||
((DUTY) == LCD_Duty_1_3) || \
|
||||
((DUTY) == LCD_Duty_1_4) || \
|
||||
((DUTY) == LCD_Duty_1_8))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup LCD_Bias
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define LCD_Bias_1_4 ((uint32_t)0x00000000) /*!< 1/4 Bias */
|
||||
#define LCD_Bias_1_2 LCD_CR_BIAS_0 /*!< 1/2 Bias */
|
||||
#define LCD_Bias_1_3 LCD_CR_BIAS_1 /*!< 1/3 Bias */
|
||||
|
||||
#define IS_LCD_BIAS(BIAS) (((BIAS) == LCD_Bias_1_4) || \
|
||||
((BIAS) == LCD_Bias_1_2) || \
|
||||
((BIAS) == LCD_Bias_1_3))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LCD_Voltage_Source
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define LCD_VoltageSource_Internal ((uint32_t)0x00000000) /*!< Internal voltage source for the LCD */
|
||||
#define LCD_VoltageSource_External LCD_CR_VSEL /*!< External voltage source for the LCD */
|
||||
|
||||
#define IS_LCD_VOLTAGE_SOURCE(SOURCE) (((SOURCE) == LCD_VoltageSource_Internal) || \
|
||||
((SOURCE) == LCD_VoltageSource_External))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LCD_Interrupts
|
||||
* @{
|
||||
*/
|
||||
#define LCD_IT_SOF LCD_FCR_SOFIE
|
||||
#define LCD_IT_UDD LCD_FCR_UDDIE
|
||||
|
||||
#define IS_LCD_IT(IT) ((((IT) & (uint32_t)0xFFFFFFF5) == 0x00) && ((IT) != 0x00))
|
||||
|
||||
#define IS_LCD_GET_IT(IT) (((IT) == LCD_IT_SOF) || ((IT) == LCD_IT_UDD))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LCD_PulseOnDuration
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define LCD_PulseOnDuration_0 ((uint32_t)0x00000000) /*!< Pulse ON duration = 0 pulse */
|
||||
#define LCD_PulseOnDuration_1 ((uint32_t)0x00000010) /*!< Pulse ON duration = 1/CK_PS */
|
||||
#define LCD_PulseOnDuration_2 ((uint32_t)0x00000020) /*!< Pulse ON duration = 2/CK_PS */
|
||||
#define LCD_PulseOnDuration_3 ((uint32_t)0x00000030) /*!< Pulse ON duration = 3/CK_PS */
|
||||
#define LCD_PulseOnDuration_4 ((uint32_t)0x00000040) /*!< Pulse ON duration = 4/CK_PS */
|
||||
#define LCD_PulseOnDuration_5 ((uint32_t)0x00000050) /*!< Pulse ON duration = 5/CK_PS */
|
||||
#define LCD_PulseOnDuration_6 ((uint32_t)0x00000060) /*!< Pulse ON duration = 6/CK_PS */
|
||||
#define LCD_PulseOnDuration_7 ((uint32_t)0x00000070) /*!< Pulse ON duration = 7/CK_PS */
|
||||
|
||||
#define IS_LCD_PULSE_ON_DURATION(DURATION) (((DURATION) == LCD_PulseOnDuration_0) || \
|
||||
((DURATION) == LCD_PulseOnDuration_1) || \
|
||||
((DURATION) == LCD_PulseOnDuration_2) || \
|
||||
((DURATION) == LCD_PulseOnDuration_3) || \
|
||||
((DURATION) == LCD_PulseOnDuration_4) || \
|
||||
((DURATION) == LCD_PulseOnDuration_5) || \
|
||||
((DURATION) == LCD_PulseOnDuration_6) || \
|
||||
((DURATION) == LCD_PulseOnDuration_7))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup LCD_DeadTime
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define LCD_DeadTime_0 ((uint32_t)0x00000000) /*!< No dead Time */
|
||||
#define LCD_DeadTime_1 ((uint32_t)0x00000080) /*!< One Phase between different couple of Frame */
|
||||
#define LCD_DeadTime_2 ((uint32_t)0x00000100) /*!< Two Phase between different couple of Frame */
|
||||
#define LCD_DeadTime_3 ((uint32_t)0x00000180) /*!< Three Phase between different couple of Frame */
|
||||
#define LCD_DeadTime_4 ((uint32_t)0x00000200) /*!< Four Phase between different couple of Frame */
|
||||
#define LCD_DeadTime_5 ((uint32_t)0x00000280) /*!< Five Phase between different couple of Frame */
|
||||
#define LCD_DeadTime_6 ((uint32_t)0x00000300) /*!< Six Phase between different couple of Frame */
|
||||
#define LCD_DeadTime_7 ((uint32_t)0x00000380) /*!< Seven Phase between different couple of Frame */
|
||||
|
||||
#define IS_LCD_DEAD_TIME(TIME) (((TIME) == LCD_DeadTime_0) || \
|
||||
((TIME) == LCD_DeadTime_1) || \
|
||||
((TIME) == LCD_DeadTime_2) || \
|
||||
((TIME) == LCD_DeadTime_3) || \
|
||||
((TIME) == LCD_DeadTime_4) || \
|
||||
((TIME) == LCD_DeadTime_5) || \
|
||||
((TIME) == LCD_DeadTime_6) || \
|
||||
((TIME) == LCD_DeadTime_7))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LCD_BlinkMode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define LCD_BlinkMode_Off ((uint32_t)0x00000000) /*!< Blink disabled */
|
||||
#define LCD_BlinkMode_SEG0_COM0 ((uint32_t)0x00010000) /*!< Blink enabled on SEG[0], COM[0] (1 pixel) */
|
||||
#define LCD_BlinkMode_SEG0_AllCOM ((uint32_t)0x00020000) /*!< Blink enabled on SEG[0], all COM (up to
|
||||
8 pixels according to the programmed duty) */
|
||||
#define LCD_BlinkMode_AllSEG_AllCOM ((uint32_t)0x00030000) /*!< Blink enabled on all SEG and all COM (all pixels) */
|
||||
|
||||
#define IS_LCD_BLINK_MODE(MODE) (((MODE) == LCD_BlinkMode_Off) || \
|
||||
((MODE) == LCD_BlinkMode_SEG0_COM0) || \
|
||||
((MODE) == LCD_BlinkMode_SEG0_AllCOM) || \
|
||||
((MODE) == LCD_BlinkMode_AllSEG_AllCOM))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LCD_BlinkFrequency
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define LCD_BlinkFrequency_Div8 ((uint32_t)0x00000000) /*!< The Blink frequency = fLCD/8 */
|
||||
#define LCD_BlinkFrequency_Div16 ((uint32_t)0x00002000) /*!< The Blink frequency = fLCD/16 */
|
||||
#define LCD_BlinkFrequency_Div32 ((uint32_t)0x00004000) /*!< The Blink frequency = fLCD/32 */
|
||||
#define LCD_BlinkFrequency_Div64 ((uint32_t)0x00006000) /*!< The Blink frequency = fLCD/64 */
|
||||
#define LCD_BlinkFrequency_Div128 ((uint32_t)0x00008000) /*!< The Blink frequency = fLCD/128 */
|
||||
#define LCD_BlinkFrequency_Div256 ((uint32_t)0x0000A000) /*!< The Blink frequency = fLCD/256 */
|
||||
#define LCD_BlinkFrequency_Div512 ((uint32_t)0x0000C000) /*!< The Blink frequency = fLCD/512 */
|
||||
#define LCD_BlinkFrequency_Div1024 ((uint32_t)0x0000E000) /*!< The Blink frequency = fLCD/1024 */
|
||||
|
||||
#define IS_LCD_BLINK_FREQUENCY(FREQUENCY) (((FREQUENCY) == LCD_BlinkFrequency_Div8) || \
|
||||
((FREQUENCY) == LCD_BlinkFrequency_Div16) || \
|
||||
((FREQUENCY) == LCD_BlinkFrequency_Div32) || \
|
||||
((FREQUENCY) == LCD_BlinkFrequency_Div64) || \
|
||||
((FREQUENCY) == LCD_BlinkFrequency_Div128) || \
|
||||
((FREQUENCY) == LCD_BlinkFrequency_Div256) || \
|
||||
((FREQUENCY) == LCD_BlinkFrequency_Div512) || \
|
||||
((FREQUENCY) == LCD_BlinkFrequency_Div1024))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LCD_Contrast
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define LCD_Contrast_Level_0 ((uint32_t)0x00000000) /*!< Maximum Voltage = 2.60V */
|
||||
#define LCD_Contrast_Level_1 ((uint32_t)0x00000400) /*!< Maximum Voltage = 2.73V */
|
||||
#define LCD_Contrast_Level_2 ((uint32_t)0x00000800) /*!< Maximum Voltage = 2.86V */
|
||||
#define LCD_Contrast_Level_3 ((uint32_t)0x00000C00) /*!< Maximum Voltage = 2.99V */
|
||||
#define LCD_Contrast_Level_4 ((uint32_t)0x00001000) /*!< Maximum Voltage = 3.12V */
|
||||
#define LCD_Contrast_Level_5 ((uint32_t)0x00001400) /*!< Maximum Voltage = 3.25V */
|
||||
#define LCD_Contrast_Level_6 ((uint32_t)0x00001800) /*!< Maximum Voltage = 3.38V */
|
||||
#define LCD_Contrast_Level_7 ((uint32_t)0x00001C00) /*!< Maximum Voltage = 3.51V */
|
||||
|
||||
#define IS_LCD_CONTRAST(CONTRAST) (((CONTRAST) == LCD_Contrast_Level_0) || \
|
||||
((CONTRAST) == LCD_Contrast_Level_1) || \
|
||||
((CONTRAST) == LCD_Contrast_Level_2) || \
|
||||
((CONTRAST) == LCD_Contrast_Level_3) || \
|
||||
((CONTRAST) == LCD_Contrast_Level_4) || \
|
||||
((CONTRAST) == LCD_Contrast_Level_5) || \
|
||||
((CONTRAST) == LCD_Contrast_Level_6) || \
|
||||
((CONTRAST) == LCD_Contrast_Level_7))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LCD_Flag
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define LCD_FLAG_ENS LCD_SR_ENS
|
||||
#define LCD_FLAG_SOF LCD_SR_SOF
|
||||
#define LCD_FLAG_UDR LCD_SR_UDR
|
||||
#define LCD_FLAG_UDD LCD_SR_UDD
|
||||
#define LCD_FLAG_RDY LCD_SR_RDY
|
||||
#define LCD_FLAG_FCRSF LCD_SR_FCRSR
|
||||
|
||||
#define IS_LCD_GET_FLAG(FLAG) (((FLAG) == LCD_FLAG_ENS) || ((FLAG) == LCD_FLAG_SOF) || \
|
||||
((FLAG) == LCD_FLAG_UDR) || ((FLAG) == LCD_FLAG_UDD) || \
|
||||
((FLAG) == LCD_FLAG_RDY) || ((FLAG) == LCD_FLAG_FCRSF))
|
||||
|
||||
#define IS_LCD_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF5) == 0x00) && ((FLAG) != 0x00))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LCD_RAMRegister
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define LCD_RAMRegister_0 ((uint32_t)0x00000000) /*!< LCD RAM Register 0 */
|
||||
#define LCD_RAMRegister_1 ((uint32_t)0x00000001) /*!< LCD RAM Register 1 */
|
||||
#define LCD_RAMRegister_2 ((uint32_t)0x00000002) /*!< LCD RAM Register 2 */
|
||||
#define LCD_RAMRegister_3 ((uint32_t)0x00000003) /*!< LCD RAM Register 3 */
|
||||
#define LCD_RAMRegister_4 ((uint32_t)0x00000004) /*!< LCD RAM Register 4 */
|
||||
#define LCD_RAMRegister_5 ((uint32_t)0x00000005) /*!< LCD RAM Register 5 */
|
||||
#define LCD_RAMRegister_6 ((uint32_t)0x00000006) /*!< LCD RAM Register 6 */
|
||||
#define LCD_RAMRegister_7 ((uint32_t)0x00000007) /*!< LCD RAM Register 7 */
|
||||
#define LCD_RAMRegister_8 ((uint32_t)0x00000008) /*!< LCD RAM Register 8 */
|
||||
#define LCD_RAMRegister_9 ((uint32_t)0x00000009) /*!< LCD RAM Register 9 */
|
||||
#define LCD_RAMRegister_10 ((uint32_t)0x0000000A) /*!< LCD RAM Register 10 */
|
||||
#define LCD_RAMRegister_11 ((uint32_t)0x0000000B) /*!< LCD RAM Register 11 */
|
||||
#define LCD_RAMRegister_12 ((uint32_t)0x0000000C) /*!< LCD RAM Register 12 */
|
||||
#define LCD_RAMRegister_13 ((uint32_t)0x0000000D) /*!< LCD RAM Register 13 */
|
||||
#define LCD_RAMRegister_14 ((uint32_t)0x0000000E) /*!< LCD RAM Register 14 */
|
||||
#define LCD_RAMRegister_15 ((uint32_t)0x0000000F) /*!< LCD RAM Register 15 */
|
||||
|
||||
#define IS_LCD_RAM_REGISTER(REGISTER) (((REGISTER) == LCD_RAMRegister_0) || \
|
||||
((REGISTER) == LCD_RAMRegister_1) || \
|
||||
((REGISTER) == LCD_RAMRegister_2) || \
|
||||
((REGISTER) == LCD_RAMRegister_3) || \
|
||||
((REGISTER) == LCD_RAMRegister_4) || \
|
||||
((REGISTER) == LCD_RAMRegister_5) || \
|
||||
((REGISTER) == LCD_RAMRegister_6) || \
|
||||
((REGISTER) == LCD_RAMRegister_7) || \
|
||||
((REGISTER) == LCD_RAMRegister_8) || \
|
||||
((REGISTER) == LCD_RAMRegister_9) || \
|
||||
((REGISTER) == LCD_RAMRegister_10) || \
|
||||
((REGISTER) == LCD_RAMRegister_11) || \
|
||||
((REGISTER) == LCD_RAMRegister_12) || \
|
||||
((REGISTER) == LCD_RAMRegister_13) || \
|
||||
((REGISTER) == LCD_RAMRegister_14) || \
|
||||
((REGISTER) == LCD_RAMRegister_15))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
|
||||
/* Function used to set the LCD configuration to the default reset state *****/
|
||||
void LCD_DeInit(void);
|
||||
|
||||
/* Initialization and Configuration functions *********************************/
|
||||
void LCD_Init(LCD_InitTypeDef* LCD_InitStruct);
|
||||
void LCD_StructInit(LCD_InitTypeDef* LCD_InitStruct);
|
||||
void LCD_Cmd(FunctionalState NewState);
|
||||
void LCD_WaitForSynchro(void);
|
||||
void LCD_HighDriveCmd(FunctionalState NewState);
|
||||
void LCD_MuxSegmentCmd(FunctionalState NewState);
|
||||
void LCD_PulseOnDurationConfig(uint32_t LCD_PulseOnDuration);
|
||||
void LCD_DeadTimeConfig(uint32_t LCD_DeadTime);
|
||||
void LCD_BlinkConfig(uint32_t LCD_BlinkMode, uint32_t LCD_BlinkFrequency);
|
||||
void LCD_ContrastConfig(uint32_t LCD_Contrast);
|
||||
|
||||
/* LCD RAM memory write functions *********************************************/
|
||||
void LCD_Write(uint32_t LCD_RAMRegister, uint32_t LCD_Data);
|
||||
void LCD_UpdateDisplayRequest(void);
|
||||
|
||||
/* Interrupts and flags management functions **********************************/
|
||||
void LCD_ITConfig(uint32_t LCD_IT, FunctionalState NewState);
|
||||
FlagStatus LCD_GetFlagStatus(uint32_t LCD_FLAG);
|
||||
void LCD_ClearFlag(uint32_t LCD_FLAG);
|
||||
ITStatus LCD_GetITStatus(uint32_t LCD_IT);
|
||||
void LCD_ClearITPendingBit(uint32_t LCD_IT);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32L1xx_LCD_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,187 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32l1xx_opamp.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.1
|
||||
* @date 05-March-2012
|
||||
* @brief This file contains all the functions prototypes for the operational
|
||||
* amplifiers (opamp) firmware library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32L1xx_OPAMP_H
|
||||
#define __STM32L1xx_OPAMP_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32l1xx.h"
|
||||
|
||||
/** @addtogroup STM32L1xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup OPAMP
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup OPAMP_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup OPAMP_Selection
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define OPAMP_Selection_OPAMP1 OPAMP_CSR_OPA1PD
|
||||
#define OPAMP_Selection_OPAMP2 OPAMP_CSR_OPA2PD
|
||||
#define OPAMP_Selection_OPAMP3 OPAMP_CSR_OPA3PD
|
||||
|
||||
#define IS_OPAMP_ALL_PERIPH(PERIPH) (((PERIPH) == OPAMP_Selection_OPAMP1) || \
|
||||
((PERIPH) == OPAMP_Selection_OPAMP2) || \
|
||||
((PERIPH) == OPAMP_Selection_OPAMP3))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup OPAMP_Switches
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* OPAMP1 Switches */
|
||||
#define OPAMP_OPAMP1Switch3 OPAMP_CSR_S3SEL1 /*!< OPAMP1 Switch 3 */
|
||||
#define OPAMP_OPAMP1Switch4 OPAMP_CSR_S4SEL1 /*!< OPAMP1 Switch 4 */
|
||||
#define OPAMP_OPAMP1Switch5 OPAMP_CSR_S5SEL1 /*!< OPAMP1 Switch 5 */
|
||||
#define OPAMP_OPAMP1Switch6 OPAMP_CSR_S6SEL1 /*!< OPAMP1 Switch 6 */
|
||||
#define OPAMP_OPAMP1SwitchANA OPAMP_CSR_ANAWSEL1 /*!< OPAMP1 Switch ANA */
|
||||
|
||||
/* OPAMP2 Switches */
|
||||
#define OPAMP_OPAMP2Switch3 OPAMP_CSR_S3SEL2 /*!< OPAMP2 Switch 3 */
|
||||
#define OPAMP_OPAMP2Switch4 OPAMP_CSR_S4SEL2 /*!< OPAMP2 Switch 4 */
|
||||
#define OPAMP_OPAMP2Switch5 OPAMP_CSR_S5SEL2 /*!< OPAMP2 Switch 5 */
|
||||
#define OPAMP_OPAMP2Switch6 OPAMP_CSR_S6SEL2 /*!< OPAMP2 Switch 6 */
|
||||
#define OPAMP_OPAMP2Switch7 OPAMP_CSR_S7SEL2 /*!< OPAMP2 Switch 7 */
|
||||
#define OPAMP_OPAMP2SwitchANA OPAMP_CSR_ANAWSEL2 /*!< OPAMP2 Switch ANA */
|
||||
|
||||
/* OPAMP3 Switches */
|
||||
#define OPAMP_OPAMP3Switch3 OPAMP_CSR_S3SEL3 /*!< OPAMP3 Switch 3 */
|
||||
#define OPAMP_OPAMP3Switch4 OPAMP_CSR_S4SEL3 /*!< OPAMP3 Switch 4 */
|
||||
#define OPAMP_OPAMP3Switch5 OPAMP_CSR_S5SEL3 /*!< OPAMP3 Switch 5 */
|
||||
#define OPAMP_OPAMP3Switch6 OPAMP_CSR_S6SEL3 /*!< OPAMP3 Switch 6 */
|
||||
#define OPAMP_OPAMP3SwitchANA OPAMP_CSR_ANAWSEL3 /*!< OPAMP3 Switch ANA */
|
||||
|
||||
#define IS_OPAMP_SWITCH(SWITCH) ((((SWITCH) & (uint32_t)0xF0E1E1E1) == 0x00) && ((SWITCH) != 0x00))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup OPAMP_Trimming
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define OPAMP_Trimming_Factory ((uint32_t)0x00000000) /*!< Factory trimming */
|
||||
#define OPAMP_Trimming_User OPAMP_OTR_OT_USER /*!< User trimming */
|
||||
|
||||
#define IS_OPAMP_TRIMMING(TRIMMING) (((TRIMMING) == OPAMP_Trimming_Factory) || \
|
||||
((TRIMMING) == OPAMP_Trimming_User))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup OPAMP_Input
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define OPAMP_Input_NMOS OPAMP_CSR_OPA1CAL_H /*!< NMOS input */
|
||||
#define OPAMP_Input_PMOS OPAMP_CSR_OPA1CAL_L /*!< PMOS input */
|
||||
|
||||
#define IS_OPAMP_INPUT(INPUT) (((INPUT) == OPAMP_Input_NMOS) || \
|
||||
((INPUT) == OPAMP_Input_PMOS))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup OPAMP_TrimValue
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_OPAMP_TRIMMINGVALUE(VALUE) ((VALUE) <= 0x0000001F) /*!< Trimming value */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup OPAMP_PowerRange
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define OPAMP_PowerRange_Low ((uint32_t)0x00000000) /*!< Low power range is selected (VDDA is lower than 2.4V) */
|
||||
#define OPAMP_PowerRange_High OPAMP_CSR_AOP_RANGE /*!< High power range is selected (VDDA is higher than 2.4V) */
|
||||
|
||||
#define IS_OPAMP_RANGE(RANGE) (((RANGE) == OPAMP_PowerRange_Low) || \
|
||||
((RANGE) == OPAMP_PowerRange_High))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
/* Initialization and Configuration functions *********************************/
|
||||
void OPAMP_DeInit(void);
|
||||
void OPAMP_SwitchCmd(uint32_t OPAMP_OPAMPxSwitchy, FunctionalState NewState);
|
||||
void OPAMP_Cmd(uint32_t OPAMP_Selection, FunctionalState NewState);
|
||||
void OPAMP_LowPowerCmd(uint32_t OPAMP_Selection, FunctionalState NewState);
|
||||
void OPAMP_PowerRangeSelect(uint32_t OPAMP_PowerRange);
|
||||
|
||||
/* Calibration functions ******************************************************/
|
||||
void OPAMP_OffsetTrimmingModeSelect(uint32_t OPAMP_Trimming);
|
||||
void OPAMP_OffsetTrimConfig(uint32_t OPAMP_Selection, uint32_t OPAMP_Input, uint32_t OPAMP_TrimValue);
|
||||
void OPAMP_OffsetTrimLowPowerConfig(uint32_t OPAMP_Selection, uint32_t OPAMP_Input, uint32_t OPAMP_TrimValue);
|
||||
FlagStatus OPAMP_GetFlagStatus(uint32_t OPAMP_Selection);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__STM32L1xx_OPAMP_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,213 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32l1xx_pwr.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.1
|
||||
* @date 05-March-2012
|
||||
* @brief This file contains all the functions prototypes for the PWR firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32L1xx_PWR_H
|
||||
#define __STM32L1xx_PWR_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32l1xx.h"
|
||||
|
||||
/** @addtogroup STM32L1xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup PWR
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup PWR_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_PVD_detection_level
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define PWR_PVDLevel_0 PWR_CR_PLS_LEV0
|
||||
#define PWR_PVDLevel_1 PWR_CR_PLS_LEV1
|
||||
#define PWR_PVDLevel_2 PWR_CR_PLS_LEV2
|
||||
#define PWR_PVDLevel_3 PWR_CR_PLS_LEV3
|
||||
#define PWR_PVDLevel_4 PWR_CR_PLS_LEV4
|
||||
#define PWR_PVDLevel_5 PWR_CR_PLS_LEV5
|
||||
#define PWR_PVDLevel_6 PWR_CR_PLS_LEV6
|
||||
#define PWR_PVDLevel_7 PWR_CR_PLS_LEV7 /* External input analog voltage
|
||||
(Compare internally to VREFINT) */
|
||||
#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_0) || ((LEVEL) == PWR_PVDLevel_1)|| \
|
||||
((LEVEL) == PWR_PVDLevel_2) || ((LEVEL) == PWR_PVDLevel_3)|| \
|
||||
((LEVEL) == PWR_PVDLevel_4) || ((LEVEL) == PWR_PVDLevel_5)|| \
|
||||
((LEVEL) == PWR_PVDLevel_6) || ((LEVEL) == PWR_PVDLevel_7))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_WakeUp_Pins
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define PWR_WakeUpPin_1 ((uint32_t)0x00000000)
|
||||
#define PWR_WakeUpPin_2 ((uint32_t)0x00000004)
|
||||
#define PWR_WakeUpPin_3 ((uint32_t)0x00000008)
|
||||
#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WakeUpPin_1) || \
|
||||
((PIN) == PWR_WakeUpPin_2) || \
|
||||
((PIN) == PWR_WakeUpPin_3))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup PWR_Voltage_Scaling_Ranges
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define PWR_VoltageScaling_Range1 PWR_CR_VOS_0
|
||||
#define PWR_VoltageScaling_Range2 PWR_CR_VOS_1
|
||||
#define PWR_VoltageScaling_Range3 PWR_CR_VOS
|
||||
|
||||
#define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_VoltageScaling_Range1) || \
|
||||
((RANGE) == PWR_VoltageScaling_Range2) || \
|
||||
((RANGE) == PWR_VoltageScaling_Range3))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_Regulator_state_is_Sleep_STOP_mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define PWR_Regulator_ON ((uint32_t)0x00000000)
|
||||
#define PWR_Regulator_LowPower PWR_CR_LPSDSR
|
||||
#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \
|
||||
((REGULATOR) == PWR_Regulator_LowPower))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_SLEEP_mode_entry
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define PWR_SLEEPEntry_WFI ((uint8_t)0x01)
|
||||
#define PWR_SLEEPEntry_WFE ((uint8_t)0x02)
|
||||
#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPEntry_WFI) || ((ENTRY) == PWR_SLEEPEntry_WFE))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_STOP_mode_entry
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define PWR_STOPEntry_WFI ((uint8_t)0x01)
|
||||
#define PWR_STOPEntry_WFE ((uint8_t)0x02)
|
||||
#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_Flag
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define PWR_FLAG_WU PWR_CSR_WUF
|
||||
#define PWR_FLAG_SB PWR_CSR_SBF
|
||||
#define PWR_FLAG_PVDO PWR_CSR_PVDO
|
||||
#define PWR_FLAG_VREFINTRDY PWR_CSR_VREFINTRDYF
|
||||
#define PWR_FLAG_VOS PWR_CSR_VOSF
|
||||
#define PWR_FLAG_REGLP PWR_CSR_REGLPF
|
||||
|
||||
#define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \
|
||||
((FLAG) == PWR_FLAG_PVDO) || ((FLAG) == PWR_FLAG_VREFINTRDY) || \
|
||||
((FLAG) == PWR_FLAG_VOS) || ((FLAG) == PWR_FLAG_REGLP))
|
||||
|
||||
#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
|
||||
/* Function used to set the PWR configuration to the default reset state ******/
|
||||
void PWR_DeInit(void);
|
||||
|
||||
/* RTC Domain Access function *************************************************/
|
||||
void PWR_RTCAccessCmd(FunctionalState NewState);
|
||||
|
||||
/* PVD configuration functions ************************************************/
|
||||
void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel);
|
||||
void PWR_PVDCmd(FunctionalState NewState);
|
||||
|
||||
/* WakeUp pins configuration functions ****************************************/
|
||||
void PWR_WakeUpPinCmd(uint32_t PWR_WakeUpPin, FunctionalState NewState);
|
||||
|
||||
/* Ultra Low Power mode configuration functions *******************************/
|
||||
void PWR_FastWakeUpCmd(FunctionalState NewState);
|
||||
void PWR_UltraLowPowerCmd(FunctionalState NewState);
|
||||
|
||||
/* Voltage Scaling configuration functions ************************************/
|
||||
void PWR_VoltageScalingConfig(uint32_t PWR_VoltageScaling);
|
||||
|
||||
/* Low Power modes configuration functions ************************************/
|
||||
void PWR_EnterLowPowerRunMode(FunctionalState NewState);
|
||||
void PWR_EnterSleepMode(uint32_t PWR_Regulator, uint8_t PWR_SLEEPEntry);
|
||||
void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);
|
||||
void PWR_EnterSTANDBYMode(void);
|
||||
|
||||
/* Flags management functions *************************************************/
|
||||
FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG);
|
||||
void PWR_ClearFlag(uint32_t PWR_FLAG);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32L1xx_PWR_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,488 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32l1xx_rcc.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.1
|
||||
* @date 05-March-2012
|
||||
* @brief This file contains all the functions prototypes for the RCC
|
||||
* firmware library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32L1xx_RCC_H
|
||||
#define __STM32L1xx_RCC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32l1xx.h"
|
||||
|
||||
/** @addtogroup STM32L1xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup RCC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t SYSCLK_Frequency;
|
||||
uint32_t HCLK_Frequency;
|
||||
uint32_t PCLK1_Frequency;
|
||||
uint32_t PCLK2_Frequency;
|
||||
}RCC_ClocksTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup RCC_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_HSE_configuration
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_HSE_OFF ((uint8_t)0x00)
|
||||
#define RCC_HSE_ON ((uint8_t)0x01)
|
||||
#define RCC_HSE_Bypass ((uint8_t)0x05)
|
||||
#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
|
||||
((HSE) == RCC_HSE_Bypass))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_MSI_Clock_Range
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_MSIRange_0 RCC_ICSCR_MSIRANGE_0 /*!< MSI = 65.536 KHz */
|
||||
#define RCC_MSIRange_1 RCC_ICSCR_MSIRANGE_1 /*!< MSI = 131.072 KHz */
|
||||
#define RCC_MSIRange_2 RCC_ICSCR_MSIRANGE_2 /*!< MSI = 262.144 KHz */
|
||||
#define RCC_MSIRange_3 RCC_ICSCR_MSIRANGE_3 /*!< MSI = 524.288 KHz */
|
||||
#define RCC_MSIRange_4 RCC_ICSCR_MSIRANGE_4 /*!< MSI = 1.048 MHz */
|
||||
#define RCC_MSIRange_5 RCC_ICSCR_MSIRANGE_5 /*!< MSI = 2.097 MHz */
|
||||
#define RCC_MSIRange_6 RCC_ICSCR_MSIRANGE_6 /*!< MSI = 4.194 MHz */
|
||||
|
||||
#define IS_RCC_MSI_CLOCK_RANGE(RANGE) (((RANGE) == RCC_MSIRange_0) || \
|
||||
((RANGE) == RCC_MSIRange_1) || \
|
||||
((RANGE) == RCC_MSIRange_2) || \
|
||||
((RANGE) == RCC_MSIRange_3) || \
|
||||
((RANGE) == RCC_MSIRange_4) || \
|
||||
((RANGE) == RCC_MSIRange_5) || \
|
||||
((RANGE) == RCC_MSIRange_6))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_PLL_Clock_Source
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_PLLSource_HSI ((uint8_t)0x00)
|
||||
#define RCC_PLLSource_HSE ((uint8_t)0x01)
|
||||
|
||||
#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI) || \
|
||||
((SOURCE) == RCC_PLLSource_HSE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_PLL_Multiplication_Factor
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_PLLMul_3 ((uint8_t)0x00)
|
||||
#define RCC_PLLMul_4 ((uint8_t)0x04)
|
||||
#define RCC_PLLMul_6 ((uint8_t)0x08)
|
||||
#define RCC_PLLMul_8 ((uint8_t)0x0C)
|
||||
#define RCC_PLLMul_12 ((uint8_t)0x10)
|
||||
#define RCC_PLLMul_16 ((uint8_t)0x14)
|
||||
#define RCC_PLLMul_24 ((uint8_t)0x18)
|
||||
#define RCC_PLLMul_32 ((uint8_t)0x1C)
|
||||
#define RCC_PLLMul_48 ((uint8_t)0x20)
|
||||
|
||||
|
||||
#define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_3) || ((MUL) == RCC_PLLMul_4) || \
|
||||
((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_8) || \
|
||||
((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_16) || \
|
||||
((MUL) == RCC_PLLMul_24) || ((MUL) == RCC_PLLMul_32) || \
|
||||
((MUL) == RCC_PLLMul_48))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_PLL_Divider_Factor
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_PLLDiv_2 ((uint8_t)0x40)
|
||||
#define RCC_PLLDiv_3 ((uint8_t)0x80)
|
||||
#define RCC_PLLDiv_4 ((uint8_t)0xC0)
|
||||
|
||||
|
||||
#define IS_RCC_PLL_DIV(DIV) (((DIV) == RCC_PLLDiv_2) || ((DIV) == RCC_PLLDiv_3) || \
|
||||
((DIV) == RCC_PLLDiv_4))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_System_Clock_Source
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_SYSCLKSource_MSI RCC_CFGR_SW_MSI
|
||||
#define RCC_SYSCLKSource_HSI RCC_CFGR_SW_HSI
|
||||
#define RCC_SYSCLKSource_HSE RCC_CFGR_SW_HSE
|
||||
#define RCC_SYSCLKSource_PLLCLK RCC_CFGR_SW_PLL
|
||||
#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_MSI) || \
|
||||
((SOURCE) == RCC_SYSCLKSource_HSI) || \
|
||||
((SOURCE) == RCC_SYSCLKSource_HSE) || \
|
||||
((SOURCE) == RCC_SYSCLKSource_PLLCLK))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_AHB_Clock_Source
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_SYSCLK_Div1 RCC_CFGR_HPRE_DIV1
|
||||
#define RCC_SYSCLK_Div2 RCC_CFGR_HPRE_DIV2
|
||||
#define RCC_SYSCLK_Div4 RCC_CFGR_HPRE_DIV4
|
||||
#define RCC_SYSCLK_Div8 RCC_CFGR_HPRE_DIV8
|
||||
#define RCC_SYSCLK_Div16 RCC_CFGR_HPRE_DIV16
|
||||
#define RCC_SYSCLK_Div64 RCC_CFGR_HPRE_DIV64
|
||||
#define RCC_SYSCLK_Div128 RCC_CFGR_HPRE_DIV128
|
||||
#define RCC_SYSCLK_Div256 RCC_CFGR_HPRE_DIV256
|
||||
#define RCC_SYSCLK_Div512 RCC_CFGR_HPRE_DIV512
|
||||
#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \
|
||||
((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \
|
||||
((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \
|
||||
((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \
|
||||
((HCLK) == RCC_SYSCLK_Div512))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_APB1_APB2_Clock_Source
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_HCLK_Div1 RCC_CFGR_PPRE1_DIV1
|
||||
#define RCC_HCLK_Div2 RCC_CFGR_PPRE1_DIV2
|
||||
#define RCC_HCLK_Div4 RCC_CFGR_PPRE1_DIV4
|
||||
#define RCC_HCLK_Div8 RCC_CFGR_PPRE1_DIV8
|
||||
#define RCC_HCLK_Div16 RCC_CFGR_PPRE1_DIV16
|
||||
#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \
|
||||
((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \
|
||||
((PCLK) == RCC_HCLK_Div16))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup RCC_Interrupt_Source
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_IT_LSIRDY ((uint8_t)0x01)
|
||||
#define RCC_IT_LSERDY ((uint8_t)0x02)
|
||||
#define RCC_IT_HSIRDY ((uint8_t)0x04)
|
||||
#define RCC_IT_HSERDY ((uint8_t)0x08)
|
||||
#define RCC_IT_PLLRDY ((uint8_t)0x10)
|
||||
#define RCC_IT_MSIRDY ((uint8_t)0x20)
|
||||
#define RCC_IT_LSECSS ((uint8_t)0x40)
|
||||
#define RCC_IT_CSS ((uint8_t)0x80)
|
||||
|
||||
#define IS_RCC_IT(IT) ((((IT) & (uint8_t)0x80) == 0x00) && ((IT) != 0x00))
|
||||
|
||||
#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
|
||||
((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
|
||||
((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_MSIRDY) || \
|
||||
((IT) == RCC_IT_CSS) || ((IT) == RCC_IT_LSECSS))
|
||||
|
||||
#define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x00) == 0x00) && ((IT) != 0x00))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_LSE_Configuration
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_LSE_OFF ((uint8_t)0x00)
|
||||
#define RCC_LSE_ON ((uint8_t)0x01)
|
||||
#define RCC_LSE_Bypass ((uint8_t)0x05)
|
||||
#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
|
||||
((LSE) == RCC_LSE_Bypass))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_RTC_Clock_Source
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_RTCCLKSource_LSE RCC_CSR_RTCSEL_LSE
|
||||
#define RCC_RTCCLKSource_LSI RCC_CSR_RTCSEL_LSI
|
||||
#define RCC_RTCCLKSource_HSE_Div2 RCC_CSR_RTCSEL_HSE
|
||||
#define RCC_RTCCLKSource_HSE_Div4 ((uint32_t)RCC_CSR_RTCSEL_HSE | RCC_CR_RTCPRE_0)
|
||||
#define RCC_RTCCLKSource_HSE_Div8 ((uint32_t)RCC_CSR_RTCSEL_HSE | RCC_CR_RTCPRE_1)
|
||||
#define RCC_RTCCLKSource_HSE_Div16 ((uint32_t)RCC_CSR_RTCSEL_HSE | RCC_CR_RTCPRE)
|
||||
#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_LSI) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div2) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div4) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div8) || \
|
||||
((SOURCE) == RCC_RTCCLKSource_HSE_Div16))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_AHB_Peripherals
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_AHBPeriph_GPIOA RCC_AHBENR_GPIOAEN
|
||||
#define RCC_AHBPeriph_GPIOB RCC_AHBENR_GPIOBEN
|
||||
#define RCC_AHBPeriph_GPIOC RCC_AHBENR_GPIOCEN
|
||||
#define RCC_AHBPeriph_GPIOD RCC_AHBENR_GPIODEN
|
||||
#define RCC_AHBPeriph_GPIOE RCC_AHBENR_GPIOEEN
|
||||
#define RCC_AHBPeriph_GPIOH RCC_AHBENR_GPIOHEN
|
||||
#define RCC_AHBPeriph_GPIOF RCC_AHBENR_GPIOFEN
|
||||
#define RCC_AHBPeriph_GPIOG RCC_AHBENR_GPIOGEN
|
||||
#define RCC_AHBPeriph_CRC RCC_AHBENR_CRCEN
|
||||
#define RCC_AHBPeriph_FLITF RCC_AHBENR_FLITFEN
|
||||
#define RCC_AHBPeriph_SRAM RCC_AHBLPENR_SRAMLPEN
|
||||
#define RCC_AHBPeriph_DMA1 RCC_AHBENR_DMA1EN
|
||||
#define RCC_AHBPeriph_DMA2 RCC_AHBENR_DMA2EN
|
||||
#define RCC_AHBPeriph_AES RCC_AHBENR_AESEN
|
||||
#define RCC_AHBPeriph_FSMC RCC_AHBENR_FSMCEN
|
||||
|
||||
#define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xB4FF6F00) == 0x00) && ((PERIPH) != 0x00))
|
||||
#define IS_RCC_AHB_LPMODE_PERIPH(PERIPH) ((((PERIPH) & 0xB4FF6F00) == 0x00) && ((PERIPH) != 0x00))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_APB2_Peripherals
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_APB2Periph_SYSCFG RCC_APB2ENR_SYSCFGEN
|
||||
#define RCC_APB2Periph_TIM9 RCC_APB2ENR_TIM9EN
|
||||
#define RCC_APB2Periph_TIM10 RCC_APB2ENR_TIM10EN
|
||||
#define RCC_APB2Periph_TIM11 RCC_APB2ENR_TIM11EN
|
||||
#define RCC_APB2Periph_ADC1 RCC_APB2ENR_ADC1EN
|
||||
#define RCC_APB2Periph_SDIO RCC_APB2ENR_SDIOEN
|
||||
#define RCC_APB2Periph_SPI1 RCC_APB2ENR_SPI1EN
|
||||
#define RCC_APB2Periph_USART1 RCC_APB2ENR_USART1EN
|
||||
|
||||
#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFA5E2) == 0x00) && ((PERIPH) != 0x00))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_APB1_Peripherals
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_APB1Periph_TIM2 RCC_APB1ENR_TIM2EN
|
||||
#define RCC_APB1Periph_TIM3 RCC_APB1ENR_TIM3EN
|
||||
#define RCC_APB1Periph_TIM4 RCC_APB1ENR_TIM4EN
|
||||
#define RCC_APB1Periph_TIM5 RCC_APB1ENR_TIM5EN
|
||||
#define RCC_APB1Periph_TIM6 RCC_APB1ENR_TIM6EN
|
||||
#define RCC_APB1Periph_TIM7 RCC_APB1ENR_TIM7EN
|
||||
#define RCC_APB1Periph_LCD RCC_APB1ENR_LCDEN
|
||||
#define RCC_APB1Periph_WWDG RCC_APB1ENR_WWDGEN
|
||||
#define RCC_APB1Periph_SPI2 RCC_APB1ENR_SPI2EN
|
||||
#define RCC_APB1Periph_SPI3 RCC_APB1ENR_SPI3EN
|
||||
#define RCC_APB1Periph_USART2 RCC_APB1ENR_USART2EN
|
||||
#define RCC_APB1Periph_USART3 RCC_APB1ENR_USART3EN
|
||||
#define RCC_APB1Periph_UART4 RCC_APB1ENR_UART4EN
|
||||
#define RCC_APB1Periph_UART5 RCC_APB1ENR_UART5EN
|
||||
#define RCC_APB1Periph_I2C1 RCC_APB1ENR_I2C1EN
|
||||
#define RCC_APB1Periph_I2C2 RCC_APB1ENR_I2C2EN
|
||||
#define RCC_APB1Periph_USB RCC_APB1ENR_USBEN
|
||||
#define RCC_APB1Periph_PWR RCC_APB1ENR_PWREN
|
||||
#define RCC_APB1Periph_DAC RCC_APB1ENR_DACEN
|
||||
#define RCC_APB1Periph_COMP RCC_APB1ENR_COMPEN
|
||||
|
||||
|
||||
#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x4F0135C0) == 0x00) && ((PERIPH) != 0x00))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_MCO_Clock_Source
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_MCOSource_NoClock ((uint8_t)0x00)
|
||||
#define RCC_MCOSource_SYSCLK ((uint8_t)0x01)
|
||||
#define RCC_MCOSource_HSI ((uint8_t)0x02)
|
||||
#define RCC_MCOSource_MSI ((uint8_t)0x03)
|
||||
#define RCC_MCOSource_HSE ((uint8_t)0x04)
|
||||
#define RCC_MCOSource_PLLCLK ((uint8_t)0x05)
|
||||
#define RCC_MCOSource_LSI ((uint8_t)0x06)
|
||||
#define RCC_MCOSource_LSE ((uint8_t)0x07)
|
||||
|
||||
#define IS_RCC_MCO_SOURCE(SOURCE) (((SOURCE) == RCC_MCOSource_NoClock) || ((SOURCE) == RCC_MCOSource_SYSCLK) || \
|
||||
((SOURCE) == RCC_MCOSource_HSI) || ((SOURCE) == RCC_MCOSource_MSI) || \
|
||||
((SOURCE) == RCC_MCOSource_HSE) || ((SOURCE) == RCC_MCOSource_PLLCLK) || \
|
||||
((SOURCE) == RCC_MCOSource_LSI) || ((SOURCE) == RCC_MCOSource_LSE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_MCO_Output_Divider
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_MCODiv_1 ((uint8_t)0x00)
|
||||
#define RCC_MCODiv_2 ((uint8_t)0x10)
|
||||
#define RCC_MCODiv_4 ((uint8_t)0x20)
|
||||
#define RCC_MCODiv_8 ((uint8_t)0x30)
|
||||
#define RCC_MCODiv_16 ((uint8_t)0x40)
|
||||
|
||||
#define IS_RCC_MCO_DIV(DIV) (((DIV) == RCC_MCODiv_1) || ((DIV) == RCC_MCODiv_2) || \
|
||||
((DIV) == RCC_MCODiv_4) || ((DIV) == RCC_MCODiv_8) || \
|
||||
((DIV) == RCC_MCODiv_16))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RCC_Flag
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RCC_FLAG_HSIRDY ((uint8_t)0x21)
|
||||
#define RCC_FLAG_MSIRDY ((uint8_t)0x29)
|
||||
#define RCC_FLAG_HSERDY ((uint8_t)0x31)
|
||||
#define RCC_FLAG_PLLRDY ((uint8_t)0x39)
|
||||
#define RCC_FLAG_LSERDY ((uint8_t)0x49)
|
||||
#define RCC_FLAG_LSECSS ((uint8_t)0x4A)
|
||||
#define RCC_FLAG_LSIRDY ((uint8_t)0x41)
|
||||
#define RCC_FLAG_OBLRST ((uint8_t)0x59)
|
||||
#define RCC_FLAG_PINRST ((uint8_t)0x5A)
|
||||
#define RCC_FLAG_PORRST ((uint8_t)0x5B)
|
||||
#define RCC_FLAG_SFTRST ((uint8_t)0x5C)
|
||||
#define RCC_FLAG_IWDGRST ((uint8_t)0x5D)
|
||||
#define RCC_FLAG_WWDGRST ((uint8_t)0x5E)
|
||||
#define RCC_FLAG_LPWRRST ((uint8_t)0x5F)
|
||||
|
||||
#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
|
||||
((FLAG) == RCC_FLAG_MSIRDY) || ((FLAG) == RCC_FLAG_PLLRDY) || \
|
||||
((FLAG) == RCC_FLAG_LSERDY) || ((FLAG) == RCC_FLAG_LSIRDY) || \
|
||||
((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \
|
||||
((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST)|| \
|
||||
((FLAG) == RCC_FLAG_WWDGRST)|| ((FLAG) == RCC_FLAG_LPWRRST)|| \
|
||||
((FLAG) == RCC_FLAG_WWDGRST)|| ((FLAG) == RCC_FLAG_LSECSS))
|
||||
|
||||
#define IS_RCC_HSI_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
|
||||
#define IS_RCC_MSI_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x3F)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
|
||||
/* Function used to set the RCC clock configuration to the default reset state */
|
||||
void RCC_DeInit(void);
|
||||
|
||||
/* Internal/external clocks, PLL, CSS and MCO configuration functions *********/
|
||||
void RCC_HSEConfig(uint8_t RCC_HSE);
|
||||
ErrorStatus RCC_WaitForHSEStartUp(void);
|
||||
void RCC_MSIRangeConfig(uint32_t RCC_MSIRange);
|
||||
void RCC_AdjustMSICalibrationValue(uint8_t MSICalibrationValue);
|
||||
void RCC_MSICmd(FunctionalState NewState);
|
||||
void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);
|
||||
void RCC_HSICmd(FunctionalState NewState);
|
||||
void RCC_LSEConfig(uint8_t RCC_LSE);
|
||||
void RCC_LSICmd(FunctionalState NewState);
|
||||
void RCC_PLLConfig(uint8_t RCC_PLLSource, uint8_t RCC_PLLMul, uint8_t RCC_PLLDiv);
|
||||
void RCC_PLLCmd(FunctionalState NewState);
|
||||
void RCC_ClockSecuritySystemCmd(FunctionalState NewState);
|
||||
void RCC_LSEClockSecuritySystemCmd(FunctionalState NewState);
|
||||
void RCC_MCOConfig(uint8_t RCC_MCOSource, uint8_t RCC_MCODiv);
|
||||
|
||||
/* System, AHB and APB busses clocks configuration functions ******************/
|
||||
void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
|
||||
uint8_t RCC_GetSYSCLKSource(void);
|
||||
void RCC_HCLKConfig(uint32_t RCC_SYSCLK);
|
||||
void RCC_PCLK1Config(uint32_t RCC_HCLK);
|
||||
void RCC_PCLK2Config(uint32_t RCC_HCLK);
|
||||
void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);
|
||||
|
||||
/* Peripheral clocks configuration functions **********************************/
|
||||
void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);
|
||||
void RCC_RTCCLKCmd(FunctionalState NewState);
|
||||
void RCC_RTCResetCmd(FunctionalState NewState);
|
||||
|
||||
void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
|
||||
void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
|
||||
void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
|
||||
|
||||
void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
|
||||
void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
|
||||
void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
|
||||
|
||||
void RCC_AHBPeriphClockLPModeCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
|
||||
void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
|
||||
void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
|
||||
|
||||
/* Interrupts and flags management functions **********************************/
|
||||
void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
|
||||
FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);
|
||||
void RCC_ClearFlag(void);
|
||||
ITStatus RCC_GetITStatus(uint8_t RCC_IT);
|
||||
void RCC_ClearITPendingBit(uint8_t RCC_IT);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32L1xx_RCC_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,896 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32l1xx_rtc.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.1
|
||||
* @date 05-March-2012
|
||||
* @brief This file contains all the functions prototypes for the RTC firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32L1xx_RTC_H
|
||||
#define __STM32L1xx_RTC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32l1xx.h"
|
||||
|
||||
/** @addtogroup STM32L1xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup RTC
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief RTC Init structures definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t RTC_HourFormat; /*!< Specifies the RTC Hour Format.
|
||||
This parameter can be a value of @ref RTC_Hour_Formats */
|
||||
|
||||
uint32_t RTC_AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value.
|
||||
This parameter must be set to a value lower than 0x7F */
|
||||
|
||||
uint32_t RTC_SynchPrediv; /*!< Specifies the RTC Synchronous Predivider value.
|
||||
This parameter must be set to a value lower than 0x7FFF */
|
||||
}RTC_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief RTC Time structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t RTC_Hours; /*!< Specifies the RTC Time Hour.
|
||||
This parameter must be set to a value in the 0-12 range
|
||||
if the RTC_HourFormat_12 is selected or 0-23 range if
|
||||
the RTC_HourFormat_24 is selected. */
|
||||
|
||||
uint8_t RTC_Minutes; /*!< Specifies the RTC Time Minutes.
|
||||
This parameter must be set to a value in the 0-59 range. */
|
||||
|
||||
uint8_t RTC_Seconds; /*!< Specifies the RTC Time Seconds.
|
||||
This parameter must be set to a value in the 0-59 range. */
|
||||
|
||||
uint8_t RTC_H12; /*!< Specifies the RTC AM/PM Time.
|
||||
This parameter can be a value of @ref RTC_AM_PM_Definitions */
|
||||
}RTC_TimeTypeDef;
|
||||
|
||||
/**
|
||||
* @brief RTC Date structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t RTC_WeekDay; /*!< Specifies the RTC Date WeekDay.
|
||||
This parameter can be a value of @ref RTC_WeekDay_Definitions */
|
||||
|
||||
uint8_t RTC_Month; /*!< Specifies the RTC Date Month (in BCD format).
|
||||
This parameter can be a value of @ref RTC_Month_Date_Definitions */
|
||||
|
||||
uint8_t RTC_Date; /*!< Specifies the RTC Date.
|
||||
This parameter must be set to a value in the 1-31 range. */
|
||||
|
||||
uint8_t RTC_Year; /*!< Specifies the RTC Date Year.
|
||||
This parameter must be set to a value in the 0-99 range. */
|
||||
}RTC_DateTypeDef;
|
||||
|
||||
/**
|
||||
* @brief RTC Alarm structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
RTC_TimeTypeDef RTC_AlarmTime; /*!< Specifies the RTC Alarm Time members. */
|
||||
|
||||
uint32_t RTC_AlarmMask; /*!< Specifies the RTC Alarm Masks.
|
||||
This parameter can be a value of @ref RTC_AlarmMask_Definitions */
|
||||
|
||||
uint32_t RTC_AlarmDateWeekDaySel; /*!< Specifies the RTC Alarm is on Date or WeekDay.
|
||||
This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */
|
||||
|
||||
uint8_t RTC_AlarmDateWeekDay; /*!< Specifies the RTC Alarm Date/WeekDay.
|
||||
If the Alarm Date is selected, this parameter
|
||||
must be set to a value in the 1-31 range.
|
||||
If the Alarm WeekDay is selected, this
|
||||
parameter can be a value of @ref RTC_WeekDay_Definitions */
|
||||
}RTC_AlarmTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup RTC_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup RTC_Hour_Formats
|
||||
* @{
|
||||
*/
|
||||
#define RTC_HourFormat_24 ((uint32_t)0x00000000)
|
||||
#define RTC_HourFormat_12 ((uint32_t)0x00000040)
|
||||
#define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_HourFormat_12) || \
|
||||
((FORMAT) == RTC_HourFormat_24))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Asynchronous_Predivider
|
||||
* @{
|
||||
*/
|
||||
#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7F)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup RTC_Synchronous_Predivider
|
||||
* @{
|
||||
*/
|
||||
#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7FFF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Time_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define IS_RTC_HOUR12(HOUR) (((HOUR) > 0) && ((HOUR) <= 12))
|
||||
#define IS_RTC_HOUR24(HOUR) ((HOUR) <= 23)
|
||||
#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59)
|
||||
#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_AM_PM_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_H12_AM ((uint8_t)0x00)
|
||||
#define RTC_H12_PM ((uint8_t)0x40)
|
||||
#define IS_RTC_H12(PM) (((PM) == RTC_H12_AM) || ((PM) == RTC_H12_PM))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Year_Date_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define IS_RTC_YEAR(YEAR) ((YEAR) <= 99)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Month_Date_Definitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Coded in BCD format */
|
||||
#define RTC_Month_January ((uint8_t)0x01)
|
||||
#define RTC_Month_February ((uint8_t)0x02)
|
||||
#define RTC_Month_March ((uint8_t)0x03)
|
||||
#define RTC_Month_April ((uint8_t)0x04)
|
||||
#define RTC_Month_May ((uint8_t)0x05)
|
||||
#define RTC_Month_June ((uint8_t)0x06)
|
||||
#define RTC_Month_July ((uint8_t)0x07)
|
||||
#define RTC_Month_August ((uint8_t)0x08)
|
||||
#define RTC_Month_September ((uint8_t)0x09)
|
||||
#define RTC_Month_October ((uint8_t)0x10)
|
||||
#define RTC_Month_November ((uint8_t)0x11)
|
||||
#define RTC_Month_December ((uint8_t)0x12)
|
||||
#define IS_RTC_MONTH(MONTH) (((MONTH) >= 1) && ((MONTH) <= 12))
|
||||
#define IS_RTC_DATE(DATE) (((DATE) >= 1) && ((DATE) <= 31))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_WeekDay_Definitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RTC_Weekday_Monday ((uint8_t)0x01)
|
||||
#define RTC_Weekday_Tuesday ((uint8_t)0x02)
|
||||
#define RTC_Weekday_Wednesday ((uint8_t)0x03)
|
||||
#define RTC_Weekday_Thursday ((uint8_t)0x04)
|
||||
#define RTC_Weekday_Friday ((uint8_t)0x05)
|
||||
#define RTC_Weekday_Saturday ((uint8_t)0x06)
|
||||
#define RTC_Weekday_Sunday ((uint8_t)0x07)
|
||||
#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \
|
||||
((WEEKDAY) == RTC_Weekday_Tuesday) || \
|
||||
((WEEKDAY) == RTC_Weekday_Wednesday) || \
|
||||
((WEEKDAY) == RTC_Weekday_Thursday) || \
|
||||
((WEEKDAY) == RTC_Weekday_Friday) || \
|
||||
((WEEKDAY) == RTC_Weekday_Saturday) || \
|
||||
((WEEKDAY) == RTC_Weekday_Sunday))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup RTC_Alarm_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) > 0) && ((DATE) <= 31))
|
||||
#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \
|
||||
((WEEKDAY) == RTC_Weekday_Tuesday) || \
|
||||
((WEEKDAY) == RTC_Weekday_Wednesday) || \
|
||||
((WEEKDAY) == RTC_Weekday_Thursday) || \
|
||||
((WEEKDAY) == RTC_Weekday_Friday) || \
|
||||
((WEEKDAY) == RTC_Weekday_Saturday) || \
|
||||
((WEEKDAY) == RTC_Weekday_Sunday))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup RTC_AlarmDateWeekDay_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_AlarmDateWeekDaySel_Date ((uint32_t)0x00000000)
|
||||
#define RTC_AlarmDateWeekDaySel_WeekDay ((uint32_t)0x40000000)
|
||||
|
||||
#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_AlarmDateWeekDaySel_Date) || \
|
||||
((SEL) == RTC_AlarmDateWeekDaySel_WeekDay))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup RTC_AlarmMask_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_AlarmMask_None ((uint32_t)0x00000000)
|
||||
#define RTC_AlarmMask_DateWeekDay ((uint32_t)0x80000000)
|
||||
#define RTC_AlarmMask_Hours ((uint32_t)0x00800000)
|
||||
#define RTC_AlarmMask_Minutes ((uint32_t)0x00008000)
|
||||
#define RTC_AlarmMask_Seconds ((uint32_t)0x00000080)
|
||||
#define RTC_AlarmMask_All ((uint32_t)0x80808080)
|
||||
#define IS_ALARM_MASK(MASK) (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Alarms_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_Alarm_A ((uint32_t)0x00000100)
|
||||
#define RTC_Alarm_B ((uint32_t)0x00000200)
|
||||
#define IS_RTC_ALARM(ALARM) (((ALARM) == RTC_Alarm_A) || ((ALARM) == RTC_Alarm_B))
|
||||
#define IS_RTC_CMD_ALARM(ALARM) (((ALARM) & (RTC_Alarm_A | RTC_Alarm_B)) != (uint32_t)RESET)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_AlarmSubSecondMask_All ((uint32_t)0x00000000) /*!< All Alarm SS fields are masked.
|
||||
There is no comparison on sub seconds
|
||||
for Alarm */
|
||||
#define RTC_AlarmSubSecondMask_SS14_1 ((uint32_t)0x01000000) /*!< SS[14:1] are don't care in Alarm
|
||||
comparison. Only SS[0] is compared. */
|
||||
#define RTC_AlarmSubSecondMask_SS14_2 ((uint32_t)0x02000000) /*!< SS[14:2] are don't care in Alarm
|
||||
comparison. Only SS[1:0] are compared */
|
||||
#define RTC_AlarmSubSecondMask_SS14_3 ((uint32_t)0x03000000) /*!< SS[14:3] are don't care in Alarm
|
||||
comparison. Only SS[2:0] are compared */
|
||||
#define RTC_AlarmSubSecondMask_SS14_4 ((uint32_t)0x04000000) /*!< SS[14:4] are don't care in Alarm
|
||||
comparison. Only SS[3:0] are compared */
|
||||
#define RTC_AlarmSubSecondMask_SS14_5 ((uint32_t)0x05000000) /*!< SS[14:5] are don't care in Alarm
|
||||
comparison. Only SS[4:0] are compared */
|
||||
#define RTC_AlarmSubSecondMask_SS14_6 ((uint32_t)0x06000000) /*!< SS[14:6] are don't care in Alarm
|
||||
comparison. Only SS[5:0] are compared */
|
||||
#define RTC_AlarmSubSecondMask_SS14_7 ((uint32_t)0x07000000) /*!< SS[14:7] are don't care in Alarm
|
||||
comparison. Only SS[6:0] are compared */
|
||||
#define RTC_AlarmSubSecondMask_SS14_8 ((uint32_t)0x08000000) /*!< SS[14:8] are don't care in Alarm
|
||||
comparison. Only SS[7:0] are compared */
|
||||
#define RTC_AlarmSubSecondMask_SS14_9 ((uint32_t)0x09000000) /*!< SS[14:9] are don't care in Alarm
|
||||
comparison. Only SS[8:0] are compared */
|
||||
#define RTC_AlarmSubSecondMask_SS14_10 ((uint32_t)0x0A000000) /*!< SS[14:10] are don't care in Alarm
|
||||
comparison. Only SS[9:0] are compared */
|
||||
#define RTC_AlarmSubSecondMask_SS14_11 ((uint32_t)0x0B000000) /*!< SS[14:11] are don't care in Alarm
|
||||
comparison. Only SS[10:0] are compared */
|
||||
#define RTC_AlarmSubSecondMask_SS14_12 ((uint32_t)0x0C000000) /*!< SS[14:12] are don't care in Alarm
|
||||
comparison.Only SS[11:0] are compared */
|
||||
#define RTC_AlarmSubSecondMask_SS14_13 ((uint32_t)0x0D000000) /*!< SS[14:13] are don't care in Alarm
|
||||
comparison. Only SS[12:0] are compared */
|
||||
#define RTC_AlarmSubSecondMask_SS14 ((uint32_t)0x0E000000) /*!< SS[14] is don't care in Alarm
|
||||
comparison.Only SS[13:0] are compared */
|
||||
#define RTC_AlarmSubSecondMask_None ((uint32_t)0x0F000000) /*!< SS[14:0] are compared and must match
|
||||
to activate alarm. */
|
||||
#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK) (((MASK) == RTC_AlarmSubSecondMask_All) || \
|
||||
((MASK) == RTC_AlarmSubSecondMask_SS14_1) || \
|
||||
((MASK) == RTC_AlarmSubSecondMask_SS14_2) || \
|
||||
((MASK) == RTC_AlarmSubSecondMask_SS14_3) || \
|
||||
((MASK) == RTC_AlarmSubSecondMask_SS14_4) || \
|
||||
((MASK) == RTC_AlarmSubSecondMask_SS14_5) || \
|
||||
((MASK) == RTC_AlarmSubSecondMask_SS14_6) || \
|
||||
((MASK) == RTC_AlarmSubSecondMask_SS14_7) || \
|
||||
((MASK) == RTC_AlarmSubSecondMask_SS14_8) || \
|
||||
((MASK) == RTC_AlarmSubSecondMask_SS14_9) || \
|
||||
((MASK) == RTC_AlarmSubSecondMask_SS14_10) || \
|
||||
((MASK) == RTC_AlarmSubSecondMask_SS14_11) || \
|
||||
((MASK) == RTC_AlarmSubSecondMask_SS14_12) || \
|
||||
((MASK) == RTC_AlarmSubSecondMask_SS14_13) || \
|
||||
((MASK) == RTC_AlarmSubSecondMask_SS14) || \
|
||||
((MASK) == RTC_AlarmSubSecondMask_None))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Alarm_Sub_Seconds_Value
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= 0x00007FFF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Wakeup_Timer_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_WakeUpClock_RTCCLK_Div16 ((uint32_t)0x00000000)
|
||||
#define RTC_WakeUpClock_RTCCLK_Div8 ((uint32_t)0x00000001)
|
||||
#define RTC_WakeUpClock_RTCCLK_Div4 ((uint32_t)0x00000002)
|
||||
#define RTC_WakeUpClock_RTCCLK_Div2 ((uint32_t)0x00000003)
|
||||
#define RTC_WakeUpClock_CK_SPRE_16bits ((uint32_t)0x00000004)
|
||||
#define RTC_WakeUpClock_CK_SPRE_17bits ((uint32_t)0x00000006)
|
||||
#define IS_RTC_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WakeUpClock_RTCCLK_Div16) || \
|
||||
((CLOCK) == RTC_WakeUpClock_RTCCLK_Div8) || \
|
||||
((CLOCK) == RTC_WakeUpClock_RTCCLK_Div4) || \
|
||||
((CLOCK) == RTC_WakeUpClock_RTCCLK_Div2) || \
|
||||
((CLOCK) == RTC_WakeUpClock_CK_SPRE_16bits) || \
|
||||
((CLOCK) == RTC_WakeUpClock_CK_SPRE_17bits))
|
||||
#define IS_RTC_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= 0xFFFF)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Time_Stamp_Edges_definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_TimeStampEdge_Rising ((uint32_t)0x00000000)
|
||||
#define RTC_TimeStampEdge_Falling ((uint32_t)0x00000008)
|
||||
#define IS_RTC_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TimeStampEdge_Rising) || \
|
||||
((EDGE) == RTC_TimeStampEdge_Falling))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Output_selection_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_Output_Disable ((uint32_t)0x00000000)
|
||||
#define RTC_Output_AlarmA ((uint32_t)0x00200000)
|
||||
#define RTC_Output_AlarmB ((uint32_t)0x00400000)
|
||||
#define RTC_Output_WakeUp ((uint32_t)0x00600000)
|
||||
|
||||
#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_Output_Disable) || \
|
||||
((OUTPUT) == RTC_Output_AlarmA) || \
|
||||
((OUTPUT) == RTC_Output_AlarmB) || \
|
||||
((OUTPUT) == RTC_Output_WakeUp))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Output_Polarity_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_OutputPolarity_High ((uint32_t)0x00000000)
|
||||
#define RTC_OutputPolarity_Low ((uint32_t)0x00100000)
|
||||
#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OutputPolarity_High) || \
|
||||
((POL) == RTC_OutputPolarity_Low))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Coarse_Calibration_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_CalibSign_Positive ((uint32_t)0x00000000)
|
||||
#define RTC_CalibSign_Negative ((uint32_t)0x00000080)
|
||||
#define IS_RTC_CALIB_SIGN(SIGN) (((SIGN) == RTC_CalibSign_Positive) || \
|
||||
((SIGN) == RTC_CalibSign_Negative))
|
||||
#define IS_RTC_CALIB_VALUE(VALUE) ((VALUE) < 0x20)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Calib_Output_selection_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_CalibOutput_512Hz ((uint32_t)0x00000000)
|
||||
#define RTC_CalibOutput_1Hz ((uint32_t)0x00080000)
|
||||
#define IS_RTC_CALIB_OUTPUT(OUTPUT) (((OUTPUT) == RTC_CalibOutput_512Hz) || \
|
||||
((OUTPUT) == RTC_CalibOutput_1Hz))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Smooth_calib_period_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_SmoothCalibPeriod_32sec ((uint32_t)0x00000000) /*!< if RTCCLK = 32768 Hz, Smooth calibation
|
||||
period is 32s, else 2exp20 RTCCLK seconds */
|
||||
#define RTC_SmoothCalibPeriod_16sec ((uint32_t)0x00002000) /*!< if RTCCLK = 32768 Hz, Smooth calibation
|
||||
period is 16s, else 2exp19 RTCCLK seconds */
|
||||
#define RTC_SmoothCalibPeriod_8sec ((uint32_t)0x00004000) /*!< if RTCCLK = 32768 Hz, Smooth calibation
|
||||
period is 8s, else 2exp18 RTCCLK seconds */
|
||||
#define IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD) (((PERIOD) == RTC_SmoothCalibPeriod_32sec) || \
|
||||
((PERIOD) == RTC_SmoothCalibPeriod_16sec) || \
|
||||
((PERIOD) == RTC_SmoothCalibPeriod_8sec))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Smooth_calib_Plus_pulses_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_SmoothCalibPlusPulses_Set ((uint32_t)0x00008000) /*!< The number of RTCCLK pulses added
|
||||
during a X -second window = Y - CALM[8:0].
|
||||
with Y = 512, 256, 128 when X = 32, 16, 8 */
|
||||
#define RTC_SmoothCalibPlusPulses_Reset ((uint32_t)0x00000000) /*!< The number of RTCCLK pulses subbstited
|
||||
during a 32-second window = CALM[8:0]. */
|
||||
#define IS_RTC_SMOOTH_CALIB_PLUS(PLUS) (((PLUS) == RTC_SmoothCalibPlusPulses_Set) || \
|
||||
((PLUS) == RTC_SmoothCalibPlusPulses_Reset))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Smooth_calib_Minus_pulses_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_DayLightSaving_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_DayLightSaving_SUB1H ((uint32_t)0x00020000)
|
||||
#define RTC_DayLightSaving_ADD1H ((uint32_t)0x00010000)
|
||||
#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DayLightSaving_SUB1H) || \
|
||||
((SAVE) == RTC_DayLightSaving_ADD1H))
|
||||
|
||||
#define RTC_StoreOperation_Reset ((uint32_t)0x00000000)
|
||||
#define RTC_StoreOperation_Set ((uint32_t)0x00040000)
|
||||
#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_StoreOperation_Reset) || \
|
||||
((OPERATION) == RTC_StoreOperation_Set))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Tamper_Trigger_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_TamperTrigger_RisingEdge ((uint32_t)0x00000000)
|
||||
#define RTC_TamperTrigger_FallingEdge ((uint32_t)0x00000001)
|
||||
#define RTC_TamperTrigger_LowLevel ((uint32_t)0x00000000)
|
||||
#define RTC_TamperTrigger_HighLevel ((uint32_t)0x00000001)
|
||||
#define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TamperTrigger_RisingEdge) || \
|
||||
((TRIGGER) == RTC_TamperTrigger_FallingEdge) || \
|
||||
((TRIGGER) == RTC_TamperTrigger_LowLevel) || \
|
||||
((TRIGGER) == RTC_TamperTrigger_HighLevel))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Tamper_Filter_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_TamperFilter_Disable ((uint32_t)0x00000000) /*!< Tamper filter is disabled */
|
||||
|
||||
#define RTC_TamperFilter_2Sample ((uint32_t)0x00000800) /*!< Tamper is activated after 2
|
||||
consecutive samples at the active level */
|
||||
#define RTC_TamperFilter_4Sample ((uint32_t)0x00001000) /*!< Tamper is activated after 4
|
||||
consecutive samples at the active level */
|
||||
#define RTC_TamperFilter_8Sample ((uint32_t)0x00001800) /*!< Tamper is activated after 8
|
||||
consecutive samples at the active leve. */
|
||||
#define IS_RTC_TAMPER_FILTER(FILTER) (((FILTER) == RTC_TamperFilter_Disable) || \
|
||||
((FILTER) == RTC_TamperFilter_2Sample) || \
|
||||
((FILTER) == RTC_TamperFilter_4Sample) || \
|
||||
((FILTER) == RTC_TamperFilter_8Sample))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Tamper_Sampling_Frequencies_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_TamperSamplingFreq_RTCCLK_Div32768 ((uint32_t)0x00000000) /*!< Each of the tamper inputs are sampled
|
||||
with a frequency = RTCCLK / 32768 */
|
||||
#define RTC_TamperSamplingFreq_RTCCLK_Div16384 ((uint32_t)0x000000100) /*!< Each of the tamper inputs are sampled
|
||||
with a frequency = RTCCLK / 16384 */
|
||||
#define RTC_TamperSamplingFreq_RTCCLK_Div8192 ((uint32_t)0x00000200) /*!< Each of the tamper inputs are sampled
|
||||
with a frequency = RTCCLK / 8192 */
|
||||
#define RTC_TamperSamplingFreq_RTCCLK_Div4096 ((uint32_t)0x00000300) /*!< Each of the tamper inputs are sampled
|
||||
with a frequency = RTCCLK / 4096 */
|
||||
#define RTC_TamperSamplingFreq_RTCCLK_Div2048 ((uint32_t)0x00000400) /*!< Each of the tamper inputs are sampled
|
||||
with a frequency = RTCCLK / 2048 */
|
||||
#define RTC_TamperSamplingFreq_RTCCLK_Div1024 ((uint32_t)0x00000500) /*!< Each of the tamper inputs are sampled
|
||||
with a frequency = RTCCLK / 1024 */
|
||||
#define RTC_TamperSamplingFreq_RTCCLK_Div512 ((uint32_t)0x00000600) /*!< Each of the tamper inputs are sampled
|
||||
with a frequency = RTCCLK / 512 */
|
||||
#define RTC_TamperSamplingFreq_RTCCLK_Div256 ((uint32_t)0x00000700) /*!< Each of the tamper inputs are sampled
|
||||
with a frequency = RTCCLK / 256 */
|
||||
#define IS_RTC_TAMPER_SAMPLING_FREQ(FREQ) (((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div32768) || \
|
||||
((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div16384) || \
|
||||
((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div8192) || \
|
||||
((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div4096) || \
|
||||
((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div2048) || \
|
||||
((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div1024) || \
|
||||
((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div512) || \
|
||||
((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div256))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Tamper_Pin_Precharge_Duration_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_TamperPrechargeDuration_1RTCCLK ((uint32_t)0x00000000) /*!< Tamper pins are pre-charged before
|
||||
sampling during 1 RTCCLK cycle */
|
||||
#define RTC_TamperPrechargeDuration_2RTCCLK ((uint32_t)0x00002000) /*!< Tamper pins are pre-charged before
|
||||
sampling during 2 RTCCLK cycles */
|
||||
#define RTC_TamperPrechargeDuration_4RTCCLK ((uint32_t)0x00004000) /*!< Tamper pins are pre-charged before
|
||||
sampling during 4 RTCCLK cycles */
|
||||
#define RTC_TamperPrechargeDuration_8RTCCLK ((uint32_t)0x00006000) /*!< Tamper pins are pre-charged before
|
||||
sampling during 8 RTCCLK cycles */
|
||||
|
||||
#define IS_RTC_TAMPER_PRECHARGE_DURATION(DURATION) (((DURATION) == RTC_TamperPrechargeDuration_1RTCCLK) || \
|
||||
((DURATION) == RTC_TamperPrechargeDuration_2RTCCLK) || \
|
||||
((DURATION) == RTC_TamperPrechargeDuration_4RTCCLK) || \
|
||||
((DURATION) == RTC_TamperPrechargeDuration_8RTCCLK))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Tamper_Pins_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_Tamper_1 RTC_TAFCR_TAMP1E /*!< Tamper detection enable for
|
||||
input tamper 1 */
|
||||
#define RTC_Tamper_2 RTC_TAFCR_TAMP2E /*!< Tamper detection enable for
|
||||
input tamper 2 */
|
||||
#define RTC_Tamper_3 RTC_TAFCR_TAMP3E /*!< Tamper detection enable for
|
||||
input tamper 3 */
|
||||
|
||||
#define IS_RTC_TAMPER(TAMPER) ((((TAMPER) & (uint32_t)0xFFFFFFD6) == 0x00) && ((TAMPER) != (uint32_t)RESET))
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Output_Type_ALARM_OUT
|
||||
* @{
|
||||
*/
|
||||
#define RTC_OutputType_OpenDrain ((uint32_t)0x00000000)
|
||||
#define RTC_OutputType_PushPull ((uint32_t)0x00040000)
|
||||
#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OutputType_OpenDrain) || \
|
||||
((TYPE) == RTC_OutputType_PushPull))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Add_1_Second_Parameter_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_ShiftAdd1S_Reset ((uint32_t)0x00000000)
|
||||
#define RTC_ShiftAdd1S_Set ((uint32_t)0x80000000)
|
||||
#define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_ShiftAdd1S_Reset) || \
|
||||
((SEL) == RTC_ShiftAdd1S_Set))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Substract_Fraction_Of_Second_Value
|
||||
* @{
|
||||
*/
|
||||
#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x00007FFF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Backup_Registers_Definitions
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RTC_BKP_DR0 ((uint32_t)0x00000000)
|
||||
#define RTC_BKP_DR1 ((uint32_t)0x00000001)
|
||||
#define RTC_BKP_DR2 ((uint32_t)0x00000002)
|
||||
#define RTC_BKP_DR3 ((uint32_t)0x00000003)
|
||||
#define RTC_BKP_DR4 ((uint32_t)0x00000004)
|
||||
#define RTC_BKP_DR5 ((uint32_t)0x00000005)
|
||||
#define RTC_BKP_DR6 ((uint32_t)0x00000006)
|
||||
#define RTC_BKP_DR7 ((uint32_t)0x00000007)
|
||||
#define RTC_BKP_DR8 ((uint32_t)0x00000008)
|
||||
#define RTC_BKP_DR9 ((uint32_t)0x00000009)
|
||||
#define RTC_BKP_DR10 ((uint32_t)0x0000000A)
|
||||
#define RTC_BKP_DR11 ((uint32_t)0x0000000B)
|
||||
#define RTC_BKP_DR12 ((uint32_t)0x0000000C)
|
||||
#define RTC_BKP_DR13 ((uint32_t)0x0000000D)
|
||||
#define RTC_BKP_DR14 ((uint32_t)0x0000000E)
|
||||
#define RTC_BKP_DR15 ((uint32_t)0x0000000F)
|
||||
#define RTC_BKP_DR16 ((uint32_t)0x00000010)
|
||||
#define RTC_BKP_DR17 ((uint32_t)0x00000011)
|
||||
#define RTC_BKP_DR18 ((uint32_t)0x00000012)
|
||||
#define RTC_BKP_DR19 ((uint32_t)0x00000013)
|
||||
#define RTC_BKP_DR20 ((uint32_t)0x00000014)
|
||||
#define RTC_BKP_DR21 ((uint32_t)0x00000015)
|
||||
#define RTC_BKP_DR22 ((uint32_t)0x00000016)
|
||||
#define RTC_BKP_DR23 ((uint32_t)0x00000017)
|
||||
#define RTC_BKP_DR24 ((uint32_t)0x00000018)
|
||||
#define RTC_BKP_DR25 ((uint32_t)0x00000019)
|
||||
#define RTC_BKP_DR26 ((uint32_t)0x0000001A)
|
||||
#define RTC_BKP_DR27 ((uint32_t)0x0000001B)
|
||||
#define RTC_BKP_DR28 ((uint32_t)0x0000001C)
|
||||
#define RTC_BKP_DR29 ((uint32_t)0x0000001D)
|
||||
#define RTC_BKP_DR30 ((uint32_t)0x0000001E)
|
||||
#define RTC_BKP_DR31 ((uint32_t)0x0000001F)
|
||||
#define IS_RTC_BKP(BKP) (((BKP) == RTC_BKP_DR0) || \
|
||||
((BKP) == RTC_BKP_DR1) || \
|
||||
((BKP) == RTC_BKP_DR2) || \
|
||||
((BKP) == RTC_BKP_DR3) || \
|
||||
((BKP) == RTC_BKP_DR4) || \
|
||||
((BKP) == RTC_BKP_DR5) || \
|
||||
((BKP) == RTC_BKP_DR6) || \
|
||||
((BKP) == RTC_BKP_DR7) || \
|
||||
((BKP) == RTC_BKP_DR8) || \
|
||||
((BKP) == RTC_BKP_DR9) || \
|
||||
((BKP) == RTC_BKP_DR10) || \
|
||||
((BKP) == RTC_BKP_DR11) || \
|
||||
((BKP) == RTC_BKP_DR12) || \
|
||||
((BKP) == RTC_BKP_DR13) || \
|
||||
((BKP) == RTC_BKP_DR14) || \
|
||||
((BKP) == RTC_BKP_DR15) || \
|
||||
((BKP) == RTC_BKP_DR16) || \
|
||||
((BKP) == RTC_BKP_DR17) || \
|
||||
((BKP) == RTC_BKP_DR18) || \
|
||||
((BKP) == RTC_BKP_DR19) || \
|
||||
((BKP) == RTC_BKP_DR20) || \
|
||||
((BKP) == RTC_BKP_DR21) || \
|
||||
((BKP) == RTC_BKP_DR22) || \
|
||||
((BKP) == RTC_BKP_DR23) || \
|
||||
((BKP) == RTC_BKP_DR24) || \
|
||||
((BKP) == RTC_BKP_DR25) || \
|
||||
((BKP) == RTC_BKP_DR26) || \
|
||||
((BKP) == RTC_BKP_DR27) || \
|
||||
((BKP) == RTC_BKP_DR28) || \
|
||||
((BKP) == RTC_BKP_DR29) || \
|
||||
((BKP) == RTC_BKP_DR30) || \
|
||||
((BKP) == RTC_BKP_DR31))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Input_parameter_format_definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_Format_BIN ((uint32_t)0x000000000)
|
||||
#define RTC_Format_BCD ((uint32_t)0x000000001)
|
||||
#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_Format_BIN) || ((FORMAT) == RTC_Format_BCD))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Flags_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_FLAG_RECALPF ((uint32_t)0x00010000)
|
||||
#define RTC_FLAG_TAMP3F ((uint32_t)0x00008000)
|
||||
#define RTC_FLAG_TAMP2F ((uint32_t)0x00004000)
|
||||
#define RTC_FLAG_TAMP1F ((uint32_t)0x00002000)
|
||||
#define RTC_FLAG_TSOVF ((uint32_t)0x00001000)
|
||||
#define RTC_FLAG_TSF ((uint32_t)0x00000800)
|
||||
#define RTC_FLAG_WUTF ((uint32_t)0x00000400)
|
||||
#define RTC_FLAG_ALRBF ((uint32_t)0x00000200)
|
||||
#define RTC_FLAG_ALRAF ((uint32_t)0x00000100)
|
||||
#define RTC_FLAG_INITF ((uint32_t)0x00000040)
|
||||
#define RTC_FLAG_RSF ((uint32_t)0x00000020)
|
||||
#define RTC_FLAG_INITS ((uint32_t)0x00000010)
|
||||
#define RTC_FLAG_SHPF ((uint32_t)0x00000008)
|
||||
#define RTC_FLAG_WUTWF ((uint32_t)0x00000004)
|
||||
#define RTC_FLAG_ALRBWF ((uint32_t)0x00000002)
|
||||
#define RTC_FLAG_ALRAWF ((uint32_t)0x00000001)
|
||||
#define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_TSOVF) || ((FLAG) == RTC_FLAG_TSF) || \
|
||||
((FLAG) == RTC_FLAG_WUTF) || ((FLAG) == RTC_FLAG_ALRBF) || \
|
||||
((FLAG) == RTC_FLAG_ALRAF) || ((FLAG) == RTC_FLAG_INITF) || \
|
||||
((FLAG) == RTC_FLAG_RSF) || ((FLAG) == RTC_FLAG_WUTWF) || \
|
||||
((FLAG) == RTC_FLAG_ALRBWF) || ((FLAG) == RTC_FLAG_ALRAWF) || \
|
||||
((FLAG) == RTC_FLAG_TAMP1F) || ((FLAG) == RTC_FLAG_TAMP2F) || \
|
||||
((FLAG) == RTC_FLAG_TAMP3F) || ((FLAG) == RTC_FLAG_RECALPF) || \
|
||||
((FLAG) == RTC_FLAG_SHPF))
|
||||
#define IS_RTC_CLEAR_FLAG(FLAG) (((FLAG) != (uint32_t)RESET) && (((FLAG) & 0xFFFF00DF) == (uint32_t)RESET))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Interrupts_Definitions
|
||||
* @{
|
||||
*/
|
||||
#define RTC_IT_TS ((uint32_t)0x00008000)
|
||||
#define RTC_IT_WUT ((uint32_t)0x00004000)
|
||||
#define RTC_IT_ALRB ((uint32_t)0x00002000)
|
||||
#define RTC_IT_ALRA ((uint32_t)0x00001000)
|
||||
#define RTC_IT_TAMP ((uint32_t)0x00000004) /* Used only to Enable the Tamper Interrupt */
|
||||
#define RTC_IT_TAMP1 ((uint32_t)0x00020000)
|
||||
#define RTC_IT_TAMP2 ((uint32_t)0x00040000)
|
||||
#define RTC_IT_TAMP3 ((uint32_t)0x00080000)
|
||||
|
||||
|
||||
#define IS_RTC_CONFIG_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFF0FFB) == (uint32_t)RESET))
|
||||
#define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_TS) || ((IT) == RTC_IT_WUT) || \
|
||||
((IT) == RTC_IT_ALRB) || ((IT) == RTC_IT_ALRA) || \
|
||||
((IT) == RTC_IT_TAMP1) || ((IT) == RTC_IT_TAMP2) || \
|
||||
((IT) == RTC_IT_TAMP3))
|
||||
#define IS_RTC_CLEAR_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFF10FFF) == (uint32_t)RESET))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RTC_Legacy
|
||||
* @{
|
||||
*/
|
||||
#define RTC_DigitalCalibConfig RTC_CoarseCalibConfig
|
||||
#define RTC_DigitalCalibCmd RTC_CoarseCalibCmd
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
|
||||
/* Function used to set the RTC configuration to the default reset state *****/
|
||||
ErrorStatus RTC_DeInit(void);
|
||||
|
||||
|
||||
/* Initialization and Configuration functions *********************************/
|
||||
ErrorStatus RTC_Init(RTC_InitTypeDef* RTC_InitStruct);
|
||||
void RTC_StructInit(RTC_InitTypeDef* RTC_InitStruct);
|
||||
void RTC_WriteProtectionCmd(FunctionalState NewState);
|
||||
ErrorStatus RTC_EnterInitMode(void);
|
||||
void RTC_ExitInitMode(void);
|
||||
ErrorStatus RTC_WaitForSynchro(void);
|
||||
ErrorStatus RTC_RefClockCmd(FunctionalState NewState);
|
||||
void RTC_BypassShadowCmd(FunctionalState NewState);
|
||||
|
||||
/* Time and Date configuration functions **************************************/
|
||||
ErrorStatus RTC_SetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct);
|
||||
void RTC_TimeStructInit(RTC_TimeTypeDef* RTC_TimeStruct);
|
||||
void RTC_GetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct);
|
||||
uint32_t RTC_GetSubSecond(void);
|
||||
ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct);
|
||||
void RTC_DateStructInit(RTC_DateTypeDef* RTC_DateStruct);
|
||||
void RTC_GetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct);
|
||||
|
||||
/* Alarms (Alarm A and Alarm B) configuration functions **********************/
|
||||
void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct);
|
||||
void RTC_AlarmStructInit(RTC_AlarmTypeDef* RTC_AlarmStruct);
|
||||
void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct);
|
||||
ErrorStatus RTC_AlarmCmd(uint32_t RTC_Alarm, FunctionalState NewState);
|
||||
void RTC_AlarmSubSecondConfig(uint32_t RTC_Alarm, uint32_t RTC_AlarmSubSecondValue, uint32_t RTC_AlarmSubSecondMask);
|
||||
uint32_t RTC_GetAlarmSubSecond(uint32_t RTC_Alarm);
|
||||
|
||||
/* WakeUp Timer configuration functions ***************************************/
|
||||
void RTC_WakeUpClockConfig(uint32_t RTC_WakeUpClock);
|
||||
void RTC_SetWakeUpCounter(uint32_t RTC_WakeUpCounter);
|
||||
uint32_t RTC_GetWakeUpCounter(void);
|
||||
ErrorStatus RTC_WakeUpCmd(FunctionalState NewState);
|
||||
|
||||
/* Daylight Saving configuration functions ************************************/
|
||||
void RTC_DayLightSavingConfig(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation);
|
||||
uint32_t RTC_GetStoreOperation(void);
|
||||
|
||||
/* Output pin Configuration function ******************************************/
|
||||
void RTC_OutputConfig(uint32_t RTC_Output, uint32_t RTC_OutputPolarity);
|
||||
|
||||
/* Coarse and Smooth Calibration configuration functions **********************/
|
||||
ErrorStatus RTC_CoarseCalibConfig(uint32_t RTC_CalibSign, uint32_t Value);
|
||||
ErrorStatus RTC_CoarseCalibCmd(FunctionalState NewState);
|
||||
void RTC_CalibOutputCmd(FunctionalState NewState);
|
||||
void RTC_CalibOutputConfig(uint32_t RTC_CalibOutput);
|
||||
ErrorStatus RTC_SmoothCalibConfig(uint32_t RTC_SmoothCalibPeriod,
|
||||
uint32_t RTC_SmoothCalibPlusPulses,
|
||||
uint32_t RTC_SmouthCalibMinusPulsesValue);
|
||||
|
||||
/* TimeStamp configuration functions ******************************************/
|
||||
void RTC_TimeStampCmd(uint32_t RTC_TimeStampEdge, FunctionalState NewState);
|
||||
void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_StampTimeStruct,
|
||||
RTC_DateTypeDef* RTC_StampDateStruct);
|
||||
uint32_t RTC_GetTimeStampSubSecond(void);
|
||||
|
||||
/* Tampers configuration functions ********************************************/
|
||||
void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger);
|
||||
void RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState);
|
||||
void RTC_TamperFilterConfig(uint32_t RTC_TamperFilter);
|
||||
void RTC_TamperSamplingFreqConfig(uint32_t RTC_TamperSamplingFreq);
|
||||
void RTC_TamperPinsPrechargeDuration(uint32_t RTC_TamperPrechargeDuration);
|
||||
void RTC_TimeStampOnTamperDetectionCmd(FunctionalState NewState);
|
||||
void RTC_TamperPullUpCmd(FunctionalState NewState);
|
||||
|
||||
/* Backup Data Registers configuration functions ******************************/
|
||||
void RTC_WriteBackupRegister(uint32_t RTC_BKP_DR, uint32_t Data);
|
||||
uint32_t RTC_ReadBackupRegister(uint32_t RTC_BKP_DR);
|
||||
|
||||
/* Output Type Config configuration functions *********************************/
|
||||
void RTC_OutputTypeConfig(uint32_t RTC_OutputType);
|
||||
|
||||
/* RTC_Shift_control_synchonisation_functions *********************************/
|
||||
ErrorStatus RTC_SynchroShiftConfig(uint32_t RTC_ShiftAdd1S, uint32_t RTC_ShiftSubFS);
|
||||
|
||||
/* Interrupts and flags management functions **********************************/
|
||||
void RTC_ITConfig(uint32_t RTC_IT, FunctionalState NewState);
|
||||
FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG);
|
||||
void RTC_ClearFlag(uint32_t RTC_FLAG);
|
||||
ITStatus RTC_GetITStatus(uint32_t RTC_IT);
|
||||
void RTC_ClearITPendingBit(uint32_t RTC_IT);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__STM32L1xx_RTC_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,535 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32l1xx_sdio.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.1
|
||||
* @date 05-March-2012
|
||||
* @brief This file contains all the functions prototypes for the SDIO firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32L1xx_SDIO_H
|
||||
#define __STM32L1xx_SDIO_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32l1xx.h"
|
||||
|
||||
/** @addtogroup STM32L1xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup SDIO
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t SDIO_ClockEdge; /*!< Specifies the clock transition on which the bit capture is made.
|
||||
This parameter can be a value of @ref SDIO_Clock_Edge */
|
||||
|
||||
uint32_t SDIO_ClockBypass; /*!< Specifies whether the SDIO Clock divider bypass is
|
||||
enabled or disabled.
|
||||
This parameter can be a value of @ref SDIO_Clock_Bypass */
|
||||
|
||||
uint32_t SDIO_ClockPowerSave; /*!< Specifies whether SDIO Clock output is enabled or
|
||||
disabled when the bus is idle.
|
||||
This parameter can be a value of @ref SDIO_Clock_Power_Save */
|
||||
|
||||
uint32_t SDIO_BusWide; /*!< Specifies the SDIO bus width.
|
||||
This parameter can be a value of @ref SDIO_Bus_Wide */
|
||||
|
||||
uint32_t SDIO_HardwareFlowControl; /*!< Specifies whether the SDIO hardware flow control is enabled or disabled.
|
||||
This parameter can be a value of @ref SDIO_Hardware_Flow_Control */
|
||||
|
||||
uint8_t SDIO_ClockDiv; /*!< Specifies the clock frequency of the SDIO controller.
|
||||
This parameter can be a value between 0x00 and 0xFF. */
|
||||
|
||||
} SDIO_InitTypeDef;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t SDIO_Argument; /*!< Specifies the SDIO command argument which is sent
|
||||
to a card as part of a command message. If a command
|
||||
contains an argument, it must be loaded into this register
|
||||
before writing the command to the command register */
|
||||
|
||||
uint32_t SDIO_CmdIndex; /*!< Specifies the SDIO command index. It must be lower than 0x40. */
|
||||
|
||||
uint32_t SDIO_Response; /*!< Specifies the SDIO response type.
|
||||
This parameter can be a value of @ref SDIO_Response_Type */
|
||||
|
||||
uint32_t SDIO_Wait; /*!< Specifies whether SDIO wait-for-interrupt request is enabled or disabled.
|
||||
This parameter can be a value of @ref SDIO_Wait_Interrupt_State */
|
||||
|
||||
uint32_t SDIO_CPSM; /*!< Specifies whether SDIO Command path state machine (CPSM)
|
||||
is enabled or disabled.
|
||||
This parameter can be a value of @ref SDIO_CPSM_State */
|
||||
} SDIO_CmdInitTypeDef;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t SDIO_DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */
|
||||
|
||||
uint32_t SDIO_DataLength; /*!< Specifies the number of data bytes to be transferred. */
|
||||
|
||||
uint32_t SDIO_DataBlockSize; /*!< Specifies the data block size for block transfer.
|
||||
This parameter can be a value of @ref SDIO_Data_Block_Size */
|
||||
|
||||
uint32_t SDIO_TransferDir; /*!< Specifies the data transfer direction, whether the transfer
|
||||
is a read or write.
|
||||
This parameter can be a value of @ref SDIO_Transfer_Direction */
|
||||
|
||||
uint32_t SDIO_TransferMode; /*!< Specifies whether data transfer is in stream or block mode.
|
||||
This parameter can be a value of @ref SDIO_Transfer_Type */
|
||||
|
||||
uint32_t SDIO_DPSM; /*!< Specifies whether SDIO Data path state machine (DPSM)
|
||||
is enabled or disabled.
|
||||
This parameter can be a value of @ref SDIO_DPSM_State */
|
||||
} SDIO_DataInitTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup SDIO_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO_Clock_Edge
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SDIO_ClockEdge_Rising ((uint32_t)0x00000000)
|
||||
#define SDIO_ClockEdge_Falling ((uint32_t)0x00002000)
|
||||
#define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_ClockEdge_Rising) || \
|
||||
((EDGE) == SDIO_ClockEdge_Falling))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO_Clock_Bypass
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SDIO_ClockBypass_Disable ((uint32_t)0x00000000)
|
||||
#define SDIO_ClockBypass_Enable ((uint32_t)0x00000400)
|
||||
#define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_ClockBypass_Disable) || \
|
||||
((BYPASS) == SDIO_ClockBypass_Enable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO_Clock_Power_Save
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SDIO_ClockPowerSave_Disable ((uint32_t)0x00000000)
|
||||
#define SDIO_ClockPowerSave_Enable ((uint32_t)0x00000200)
|
||||
#define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_ClockPowerSave_Disable) || \
|
||||
((SAVE) == SDIO_ClockPowerSave_Enable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO_Bus_Wide
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SDIO_BusWide_1b ((uint32_t)0x00000000)
|
||||
#define SDIO_BusWide_4b ((uint32_t)0x00000800)
|
||||
#define SDIO_BusWide_8b ((uint32_t)0x00001000)
|
||||
#define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BusWide_1b) || ((WIDE) == SDIO_BusWide_4b) || \
|
||||
((WIDE) == SDIO_BusWide_8b))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO_Hardware_Flow_Control
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SDIO_HardwareFlowControl_Disable ((uint32_t)0x00000000)
|
||||
#define SDIO_HardwareFlowControl_Enable ((uint32_t)0x00004000)
|
||||
#define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HardwareFlowControl_Disable) || \
|
||||
((CONTROL) == SDIO_HardwareFlowControl_Enable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO_Power_State
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SDIO_PowerState_OFF ((uint32_t)0x00000000)
|
||||
#define SDIO_PowerState_ON ((uint32_t)0x00000003)
|
||||
#define IS_SDIO_POWER_STATE(STATE) (((STATE) == SDIO_PowerState_OFF) || ((STATE) == SDIO_PowerState_ON))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup SDIO_Interrupt_soucres
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SDIO_IT_CCRCFAIL ((uint32_t)0x00000001)
|
||||
#define SDIO_IT_DCRCFAIL ((uint32_t)0x00000002)
|
||||
#define SDIO_IT_CTIMEOUT ((uint32_t)0x00000004)
|
||||
#define SDIO_IT_DTIMEOUT ((uint32_t)0x00000008)
|
||||
#define SDIO_IT_TXUNDERR ((uint32_t)0x00000010)
|
||||
#define SDIO_IT_RXOVERR ((uint32_t)0x00000020)
|
||||
#define SDIO_IT_CMDREND ((uint32_t)0x00000040)
|
||||
#define SDIO_IT_CMDSENT ((uint32_t)0x00000080)
|
||||
#define SDIO_IT_DATAEND ((uint32_t)0x00000100)
|
||||
#define SDIO_IT_STBITERR ((uint32_t)0x00000200)
|
||||
#define SDIO_IT_DBCKEND ((uint32_t)0x00000400)
|
||||
#define SDIO_IT_CMDACT ((uint32_t)0x00000800)
|
||||
#define SDIO_IT_TXACT ((uint32_t)0x00001000)
|
||||
#define SDIO_IT_RXACT ((uint32_t)0x00002000)
|
||||
#define SDIO_IT_TXFIFOHE ((uint32_t)0x00004000)
|
||||
#define SDIO_IT_RXFIFOHF ((uint32_t)0x00008000)
|
||||
#define SDIO_IT_TXFIFOF ((uint32_t)0x00010000)
|
||||
#define SDIO_IT_RXFIFOF ((uint32_t)0x00020000)
|
||||
#define SDIO_IT_TXFIFOE ((uint32_t)0x00040000)
|
||||
#define SDIO_IT_RXFIFOE ((uint32_t)0x00080000)
|
||||
#define SDIO_IT_TXDAVL ((uint32_t)0x00100000)
|
||||
#define SDIO_IT_RXDAVL ((uint32_t)0x00200000)
|
||||
#define SDIO_IT_SDIOIT ((uint32_t)0x00400000)
|
||||
#define SDIO_IT_CEATAEND ((uint32_t)0x00800000)
|
||||
#define IS_SDIO_IT(IT) ((((IT) & (uint32_t)0xFF000000) == 0x00) && ((IT) != (uint32_t)0x00))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO_Command_Index
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO_Response_Type
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SDIO_Response_No ((uint32_t)0x00000000)
|
||||
#define SDIO_Response_Short ((uint32_t)0x00000040)
|
||||
#define SDIO_Response_Long ((uint32_t)0x000000C0)
|
||||
#define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_Response_No) || \
|
||||
((RESPONSE) == SDIO_Response_Short) || \
|
||||
((RESPONSE) == SDIO_Response_Long))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO_Wait_Interrupt_State
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SDIO_Wait_No ((uint32_t)0x00000000) /*!< SDIO No Wait, TimeOut is enabled */
|
||||
#define SDIO_Wait_IT ((uint32_t)0x00000100) /*!< SDIO Wait Interrupt Request */
|
||||
#define SDIO_Wait_Pend ((uint32_t)0x00000200) /*!< SDIO Wait End of transfer */
|
||||
#define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_Wait_No) || ((WAIT) == SDIO_Wait_IT) || \
|
||||
((WAIT) == SDIO_Wait_Pend))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO_CPSM_State
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SDIO_CPSM_Disable ((uint32_t)0x00000000)
|
||||
#define SDIO_CPSM_Enable ((uint32_t)0x00000400)
|
||||
#define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_Enable) || ((CPSM) == SDIO_CPSM_Disable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO_Response_Registers
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SDIO_RESP1 ((uint32_t)0x00000000)
|
||||
#define SDIO_RESP2 ((uint32_t)0x00000004)
|
||||
#define SDIO_RESP3 ((uint32_t)0x00000008)
|
||||
#define SDIO_RESP4 ((uint32_t)0x0000000C)
|
||||
#define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || ((RESP) == SDIO_RESP2) || \
|
||||
((RESP) == SDIO_RESP3) || ((RESP) == SDIO_RESP4))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO_Data_Length
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO_Data_Block_Size
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SDIO_DataBlockSize_1b ((uint32_t)0x00000000)
|
||||
#define SDIO_DataBlockSize_2b ((uint32_t)0x00000010)
|
||||
#define SDIO_DataBlockSize_4b ((uint32_t)0x00000020)
|
||||
#define SDIO_DataBlockSize_8b ((uint32_t)0x00000030)
|
||||
#define SDIO_DataBlockSize_16b ((uint32_t)0x00000040)
|
||||
#define SDIO_DataBlockSize_32b ((uint32_t)0x00000050)
|
||||
#define SDIO_DataBlockSize_64b ((uint32_t)0x00000060)
|
||||
#define SDIO_DataBlockSize_128b ((uint32_t)0x00000070)
|
||||
#define SDIO_DataBlockSize_256b ((uint32_t)0x00000080)
|
||||
#define SDIO_DataBlockSize_512b ((uint32_t)0x00000090)
|
||||
#define SDIO_DataBlockSize_1024b ((uint32_t)0x000000A0)
|
||||
#define SDIO_DataBlockSize_2048b ((uint32_t)0x000000B0)
|
||||
#define SDIO_DataBlockSize_4096b ((uint32_t)0x000000C0)
|
||||
#define SDIO_DataBlockSize_8192b ((uint32_t)0x000000D0)
|
||||
#define SDIO_DataBlockSize_16384b ((uint32_t)0x000000E0)
|
||||
#define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DataBlockSize_1b) || \
|
||||
((SIZE) == SDIO_DataBlockSize_2b) || \
|
||||
((SIZE) == SDIO_DataBlockSize_4b) || \
|
||||
((SIZE) == SDIO_DataBlockSize_8b) || \
|
||||
((SIZE) == SDIO_DataBlockSize_16b) || \
|
||||
((SIZE) == SDIO_DataBlockSize_32b) || \
|
||||
((SIZE) == SDIO_DataBlockSize_64b) || \
|
||||
((SIZE) == SDIO_DataBlockSize_128b) || \
|
||||
((SIZE) == SDIO_DataBlockSize_256b) || \
|
||||
((SIZE) == SDIO_DataBlockSize_512b) || \
|
||||
((SIZE) == SDIO_DataBlockSize_1024b) || \
|
||||
((SIZE) == SDIO_DataBlockSize_2048b) || \
|
||||
((SIZE) == SDIO_DataBlockSize_4096b) || \
|
||||
((SIZE) == SDIO_DataBlockSize_8192b) || \
|
||||
((SIZE) == SDIO_DataBlockSize_16384b))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO_Transfer_Direction
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SDIO_TransferDir_ToCard ((uint32_t)0x00000000)
|
||||
#define SDIO_TransferDir_ToSDIO ((uint32_t)0x00000002)
|
||||
#define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TransferDir_ToCard) || \
|
||||
((DIR) == SDIO_TransferDir_ToSDIO))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO_Transfer_Type
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SDIO_TransferMode_Block ((uint32_t)0x00000000)
|
||||
#define SDIO_TransferMode_Stream ((uint32_t)0x00000004)
|
||||
#define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TransferMode_Stream) || \
|
||||
((MODE) == SDIO_TransferMode_Block))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO_DPSM_State
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SDIO_DPSM_Disable ((uint32_t)0x00000000)
|
||||
#define SDIO_DPSM_Enable ((uint32_t)0x00000001)
|
||||
#define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_Enable) || ((DPSM) == SDIO_DPSM_Disable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO_Flags
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SDIO_FLAG_CCRCFAIL ((uint32_t)0x00000001)
|
||||
#define SDIO_FLAG_DCRCFAIL ((uint32_t)0x00000002)
|
||||
#define SDIO_FLAG_CTIMEOUT ((uint32_t)0x00000004)
|
||||
#define SDIO_FLAG_DTIMEOUT ((uint32_t)0x00000008)
|
||||
#define SDIO_FLAG_TXUNDERR ((uint32_t)0x00000010)
|
||||
#define SDIO_FLAG_RXOVERR ((uint32_t)0x00000020)
|
||||
#define SDIO_FLAG_CMDREND ((uint32_t)0x00000040)
|
||||
#define SDIO_FLAG_CMDSENT ((uint32_t)0x00000080)
|
||||
#define SDIO_FLAG_DATAEND ((uint32_t)0x00000100)
|
||||
#define SDIO_FLAG_STBITERR ((uint32_t)0x00000200)
|
||||
#define SDIO_FLAG_DBCKEND ((uint32_t)0x00000400)
|
||||
#define SDIO_FLAG_CMDACT ((uint32_t)0x00000800)
|
||||
#define SDIO_FLAG_TXACT ((uint32_t)0x00001000)
|
||||
#define SDIO_FLAG_RXACT ((uint32_t)0x00002000)
|
||||
#define SDIO_FLAG_TXFIFOHE ((uint32_t)0x00004000)
|
||||
#define SDIO_FLAG_RXFIFOHF ((uint32_t)0x00008000)
|
||||
#define SDIO_FLAG_TXFIFOF ((uint32_t)0x00010000)
|
||||
#define SDIO_FLAG_RXFIFOF ((uint32_t)0x00020000)
|
||||
#define SDIO_FLAG_TXFIFOE ((uint32_t)0x00040000)
|
||||
#define SDIO_FLAG_RXFIFOE ((uint32_t)0x00080000)
|
||||
#define SDIO_FLAG_TXDAVL ((uint32_t)0x00100000)
|
||||
#define SDIO_FLAG_RXDAVL ((uint32_t)0x00200000)
|
||||
#define SDIO_FLAG_SDIOIT ((uint32_t)0x00400000)
|
||||
#define SDIO_FLAG_CEATAEND ((uint32_t)0x00800000)
|
||||
#define IS_SDIO_FLAG(FLAG) (((FLAG) == SDIO_FLAG_CCRCFAIL) || \
|
||||
((FLAG) == SDIO_FLAG_DCRCFAIL) || \
|
||||
((FLAG) == SDIO_FLAG_CTIMEOUT) || \
|
||||
((FLAG) == SDIO_FLAG_DTIMEOUT) || \
|
||||
((FLAG) == SDIO_FLAG_TXUNDERR) || \
|
||||
((FLAG) == SDIO_FLAG_RXOVERR) || \
|
||||
((FLAG) == SDIO_FLAG_CMDREND) || \
|
||||
((FLAG) == SDIO_FLAG_CMDSENT) || \
|
||||
((FLAG) == SDIO_FLAG_DATAEND) || \
|
||||
((FLAG) == SDIO_FLAG_STBITERR) || \
|
||||
((FLAG) == SDIO_FLAG_DBCKEND) || \
|
||||
((FLAG) == SDIO_FLAG_CMDACT) || \
|
||||
((FLAG) == SDIO_FLAG_TXACT) || \
|
||||
((FLAG) == SDIO_FLAG_RXACT) || \
|
||||
((FLAG) == SDIO_FLAG_TXFIFOHE) || \
|
||||
((FLAG) == SDIO_FLAG_RXFIFOHF) || \
|
||||
((FLAG) == SDIO_FLAG_TXFIFOF) || \
|
||||
((FLAG) == SDIO_FLAG_RXFIFOF) || \
|
||||
((FLAG) == SDIO_FLAG_TXFIFOE) || \
|
||||
((FLAG) == SDIO_FLAG_RXFIFOE) || \
|
||||
((FLAG) == SDIO_FLAG_TXDAVL) || \
|
||||
((FLAG) == SDIO_FLAG_RXDAVL) || \
|
||||
((FLAG) == SDIO_FLAG_SDIOIT) || \
|
||||
((FLAG) == SDIO_FLAG_CEATAEND))
|
||||
|
||||
#define IS_SDIO_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFF3FF800) == 0x00) && ((FLAG) != (uint32_t)0x00))
|
||||
|
||||
#define IS_SDIO_GET_IT(IT) (((IT) == SDIO_IT_CCRCFAIL) || \
|
||||
((IT) == SDIO_IT_DCRCFAIL) || \
|
||||
((IT) == SDIO_IT_CTIMEOUT) || \
|
||||
((IT) == SDIO_IT_DTIMEOUT) || \
|
||||
((IT) == SDIO_IT_TXUNDERR) || \
|
||||
((IT) == SDIO_IT_RXOVERR) || \
|
||||
((IT) == SDIO_IT_CMDREND) || \
|
||||
((IT) == SDIO_IT_CMDSENT) || \
|
||||
((IT) == SDIO_IT_DATAEND) || \
|
||||
((IT) == SDIO_IT_STBITERR) || \
|
||||
((IT) == SDIO_IT_DBCKEND) || \
|
||||
((IT) == SDIO_IT_CMDACT) || \
|
||||
((IT) == SDIO_IT_TXACT) || \
|
||||
((IT) == SDIO_IT_RXACT) || \
|
||||
((IT) == SDIO_IT_TXFIFOHE) || \
|
||||
((IT) == SDIO_IT_RXFIFOHF) || \
|
||||
((IT) == SDIO_IT_TXFIFOF) || \
|
||||
((IT) == SDIO_IT_RXFIFOF) || \
|
||||
((IT) == SDIO_IT_TXFIFOE) || \
|
||||
((IT) == SDIO_IT_RXFIFOE) || \
|
||||
((IT) == SDIO_IT_TXDAVL) || \
|
||||
((IT) == SDIO_IT_RXDAVL) || \
|
||||
((IT) == SDIO_IT_SDIOIT) || \
|
||||
((IT) == SDIO_IT_CEATAEND))
|
||||
|
||||
#define IS_SDIO_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFF3FF800) == 0x00) && ((IT) != (uint32_t)0x00))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO_Read_Wait_Mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SDIO_ReadWaitMode_CLK ((uint32_t)0x00000001)
|
||||
#define SDIO_ReadWaitMode_DATA2 ((uint32_t)0x00000000)
|
||||
#define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_ReadWaitMode_CLK) || \
|
||||
((MODE) == SDIO_ReadWaitMode_DATA2))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
/* Function used to set the SDIO configuration to the default reset state ****/
|
||||
void SDIO_DeInit(void);
|
||||
|
||||
/* Initialization and Configuration functions *********************************/
|
||||
void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct);
|
||||
void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct);
|
||||
void SDIO_ClockCmd(FunctionalState NewState);
|
||||
void SDIO_SetPowerState(uint32_t SDIO_PowerState);
|
||||
uint32_t SDIO_GetPowerState(void);
|
||||
|
||||
/* DMA transfers management functions *****************************************/
|
||||
void SDIO_DMACmd(FunctionalState NewState);
|
||||
|
||||
/* Command path state machine (CPSM) management functions *********************/
|
||||
void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct);
|
||||
void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct);
|
||||
uint8_t SDIO_GetCommandResponse(void);
|
||||
uint32_t SDIO_GetResponse(uint32_t SDIO_RESP);
|
||||
|
||||
/* Data path state machine (DPSM) management functions ************************/
|
||||
void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct);
|
||||
void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct);
|
||||
uint32_t SDIO_GetDataCounter(void);
|
||||
uint32_t SDIO_ReadData(void);
|
||||
void SDIO_WriteData(uint32_t Data);
|
||||
uint32_t SDIO_GetFIFOCount(void);
|
||||
|
||||
/* SDIO IO Cards mode management functions ************************************/
|
||||
void SDIO_StartSDIOReadWait(FunctionalState NewState);
|
||||
void SDIO_StopSDIOReadWait(FunctionalState NewState);
|
||||
void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode);
|
||||
void SDIO_SetSDIOOperation(FunctionalState NewState);
|
||||
void SDIO_SendSDIOSuspendCmd(FunctionalState NewState);
|
||||
|
||||
/* CE-ATA mode management functions *******************************************/
|
||||
void SDIO_CommandCompletionCmd(FunctionalState NewState);
|
||||
void SDIO_CEATAITCmd(FunctionalState NewState);
|
||||
void SDIO_SendCEATACmd(FunctionalState NewState);
|
||||
|
||||
/* Interrupts and flags management functions **********************************/
|
||||
void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState);
|
||||
FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG);
|
||||
void SDIO_ClearFlag(uint32_t SDIO_FLAG);
|
||||
ITStatus SDIO_GetITStatus(uint32_t SDIO_IT);
|
||||
void SDIO_ClearITPendingBit(uint32_t SDIO_IT);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32L1xx_SDIO_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,524 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32l1xx_spi.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.1
|
||||
* @date 05-March-2012
|
||||
* @brief This file contains all the functions prototypes for the SPI
|
||||
* firmware library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32L1xx_SPI_H
|
||||
#define __STM32L1xx_SPI_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32l1xx.h"
|
||||
|
||||
/** @addtogroup STM32L1xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup SPI
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief SPI Init structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint16_t SPI_Direction; /*!< Specifies the SPI unidirectional or bidirectional data mode.
|
||||
This parameter can be a value of @ref SPI_data_direction */
|
||||
|
||||
uint16_t SPI_Mode; /*!< Specifies the SPI operating mode.
|
||||
This parameter can be a value of @ref SPI_mode */
|
||||
|
||||
uint16_t SPI_DataSize; /*!< Specifies the SPI data size.
|
||||
This parameter can be a value of @ref SPI_data_size */
|
||||
|
||||
uint16_t SPI_CPOL; /*!< Specifies the serial clock steady state.
|
||||
This parameter can be a value of @ref SPI_Clock_Polarity */
|
||||
|
||||
uint16_t SPI_CPHA; /*!< Specifies the clock active edge for the bit capture.
|
||||
This parameter can be a value of @ref SPI_Clock_Phase */
|
||||
|
||||
uint16_t SPI_NSS; /*!< Specifies whether the NSS signal is managed by
|
||||
hardware (NSS pin) or by software using the SSI bit.
|
||||
This parameter can be a value of @ref SPI_Slave_Select_management */
|
||||
|
||||
uint16_t SPI_BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be
|
||||
used to configure the transmit and receive SCK clock.
|
||||
This parameter can be a value of @ref SPI_BaudRate_Prescaler
|
||||
@note The communication clock is derived from the master
|
||||
clock. The slave clock does not need to be set. */
|
||||
|
||||
uint16_t SPI_FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
|
||||
This parameter can be a value of @ref SPI_MSB_LSB_transmission */
|
||||
|
||||
uint16_t SPI_CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. */
|
||||
}SPI_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief I2S Init structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
|
||||
uint16_t I2S_Mode; /*!< Specifies the I2S operating mode.
|
||||
This parameter can be a value of @ref SPI_I2S_Mode */
|
||||
|
||||
uint16_t I2S_Standard; /*!< Specifies the standard used for the I2S communication.
|
||||
This parameter can be a value of @ref SPI_I2S_Standard */
|
||||
|
||||
uint16_t I2S_DataFormat; /*!< Specifies the data format for the I2S communication.
|
||||
This parameter can be a value of @ref SPI_I2S_Data_Format */
|
||||
|
||||
uint16_t I2S_MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
|
||||
This parameter can be a value of @ref SPI_I2S_MCLK_Output */
|
||||
|
||||
uint32_t I2S_AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
|
||||
This parameter can be a value of @ref SPI_I2S_Audio_Frequency */
|
||||
|
||||
uint16_t I2S_CPOL; /*!< Specifies the idle state of the I2S clock.
|
||||
This parameter can be a value of @ref SPI_I2S_Clock_Polarity */
|
||||
}I2S_InitTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup SPI_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \
|
||||
((PERIPH) == SPI2) || \
|
||||
((PERIPH) == SPI3))
|
||||
#define IS_SPI_23_PERIPH(PERIPH) (((PERIPH) == SPI2) || \
|
||||
((PERIPH) == SPI3))
|
||||
|
||||
/** @defgroup SPI_data_direction
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000)
|
||||
#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400)
|
||||
#define SPI_Direction_1Line_Rx ((uint16_t)0x8000)
|
||||
#define SPI_Direction_1Line_Tx ((uint16_t)0xC000)
|
||||
#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \
|
||||
((MODE) == SPI_Direction_2Lines_RxOnly) || \
|
||||
((MODE) == SPI_Direction_1Line_Rx) || \
|
||||
((MODE) == SPI_Direction_1Line_Tx))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_Mode_Master ((uint16_t)0x0104)
|
||||
#define SPI_Mode_Slave ((uint16_t)0x0000)
|
||||
#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \
|
||||
((MODE) == SPI_Mode_Slave))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_data_size
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_DataSize_16b ((uint16_t)0x0800)
|
||||
#define SPI_DataSize_8b ((uint16_t)0x0000)
|
||||
#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DataSize_16b) || \
|
||||
((DATASIZE) == SPI_DataSize_8b))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_Clock_Polarity
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_CPOL_Low ((uint16_t)0x0000)
|
||||
#define SPI_CPOL_High ((uint16_t)0x0002)
|
||||
#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \
|
||||
((CPOL) == SPI_CPOL_High))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_Clock_Phase
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_CPHA_1Edge ((uint16_t)0x0000)
|
||||
#define SPI_CPHA_2Edge ((uint16_t)0x0001)
|
||||
#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \
|
||||
((CPHA) == SPI_CPHA_2Edge))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_Slave_Select_management
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_NSS_Soft ((uint16_t)0x0200)
|
||||
#define SPI_NSS_Hard ((uint16_t)0x0000)
|
||||
#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \
|
||||
((NSS) == SPI_NSS_Hard))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_BaudRate_Prescaler
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000)
|
||||
#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008)
|
||||
#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010)
|
||||
#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018)
|
||||
#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020)
|
||||
#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028)
|
||||
#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030)
|
||||
#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038)
|
||||
#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \
|
||||
((PRESCALER) == SPI_BaudRatePrescaler_4) || \
|
||||
((PRESCALER) == SPI_BaudRatePrescaler_8) || \
|
||||
((PRESCALER) == SPI_BaudRatePrescaler_16) || \
|
||||
((PRESCALER) == SPI_BaudRatePrescaler_32) || \
|
||||
((PRESCALER) == SPI_BaudRatePrescaler_64) || \
|
||||
((PRESCALER) == SPI_BaudRatePrescaler_128) || \
|
||||
((PRESCALER) == SPI_BaudRatePrescaler_256))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_MSB_LSB_transmission
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_FirstBit_MSB ((uint16_t)0x0000)
|
||||
#define SPI_FirstBit_LSB ((uint16_t)0x0080)
|
||||
#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \
|
||||
((BIT) == SPI_FirstBit_LSB))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_I2S_Mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2S_Mode_SlaveTx ((uint16_t)0x0000)
|
||||
#define I2S_Mode_SlaveRx ((uint16_t)0x0100)
|
||||
#define I2S_Mode_MasterTx ((uint16_t)0x0200)
|
||||
#define I2S_Mode_MasterRx ((uint16_t)0x0300)
|
||||
#define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \
|
||||
((MODE) == I2S_Mode_SlaveRx) || \
|
||||
((MODE) == I2S_Mode_MasterTx)|| \
|
||||
((MODE) == I2S_Mode_MasterRx))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup SPI_I2S_Standard
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2S_Standard_Phillips ((uint16_t)0x0000)
|
||||
#define I2S_Standard_MSB ((uint16_t)0x0010)
|
||||
#define I2S_Standard_LSB ((uint16_t)0x0020)
|
||||
#define I2S_Standard_PCMShort ((uint16_t)0x0030)
|
||||
#define I2S_Standard_PCMLong ((uint16_t)0x00B0)
|
||||
#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \
|
||||
((STANDARD) == I2S_Standard_MSB) || \
|
||||
((STANDARD) == I2S_Standard_LSB) || \
|
||||
((STANDARD) == I2S_Standard_PCMShort) || \
|
||||
((STANDARD) == I2S_Standard_PCMLong))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_I2S_Data_Format
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2S_DataFormat_16b ((uint16_t)0x0000)
|
||||
#define I2S_DataFormat_16bextended ((uint16_t)0x0001)
|
||||
#define I2S_DataFormat_24b ((uint16_t)0x0003)
|
||||
#define I2S_DataFormat_32b ((uint16_t)0x0005)
|
||||
#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \
|
||||
((FORMAT) == I2S_DataFormat_16bextended) || \
|
||||
((FORMAT) == I2S_DataFormat_24b) || \
|
||||
((FORMAT) == I2S_DataFormat_32b))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_I2S_MCLK_Output
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2S_MCLKOutput_Enable ((uint16_t)0x0200)
|
||||
#define I2S_MCLKOutput_Disable ((uint16_t)0x0000)
|
||||
#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \
|
||||
((OUTPUT) == I2S_MCLKOutput_Disable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_I2S_Audio_Frequency
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2S_AudioFreq_192k ((uint32_t)192000)
|
||||
#define I2S_AudioFreq_96k ((uint32_t)96000)
|
||||
#define I2S_AudioFreq_48k ((uint32_t)48000)
|
||||
#define I2S_AudioFreq_44k ((uint32_t)44100)
|
||||
#define I2S_AudioFreq_32k ((uint32_t)32000)
|
||||
#define I2S_AudioFreq_22k ((uint32_t)22050)
|
||||
#define I2S_AudioFreq_16k ((uint32_t)16000)
|
||||
#define I2S_AudioFreq_11k ((uint32_t)11025)
|
||||
#define I2S_AudioFreq_8k ((uint32_t)8000)
|
||||
#define I2S_AudioFreq_Default ((uint32_t)2)
|
||||
|
||||
#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AudioFreq_8k) && \
|
||||
((FREQ) <= I2S_AudioFreq_192k)) || \
|
||||
((FREQ) == I2S_AudioFreq_Default))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_I2S_Clock_Polarity
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define I2S_CPOL_Low ((uint16_t)0x0000)
|
||||
#define I2S_CPOL_High ((uint16_t)0x0008)
|
||||
#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \
|
||||
((CPOL) == I2S_CPOL_High))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_I2S_DMA_transfer_requests
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002)
|
||||
#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001)
|
||||
#define IS_SPI_I2S_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFFFC) == 0x00) && ((DMAREQ) != 0x00))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_NSS_internal_software_management
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100)
|
||||
#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF)
|
||||
#define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \
|
||||
((INTERNAL) == SPI_NSSInternalSoft_Reset))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_CRC_Transmit_Receive
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_CRC_Tx ((uint8_t)0x00)
|
||||
#define SPI_CRC_Rx ((uint8_t)0x01)
|
||||
#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_direction_transmit_receive
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_Direction_Rx ((uint16_t)0xBFFF)
|
||||
#define SPI_Direction_Tx ((uint16_t)0x4000)
|
||||
#define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \
|
||||
((DIRECTION) == SPI_Direction_Tx))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_I2S_interrupts_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_I2S_IT_TXE ((uint8_t)0x71)
|
||||
#define SPI_I2S_IT_RXNE ((uint8_t)0x60)
|
||||
#define SPI_I2S_IT_ERR ((uint8_t)0x50)
|
||||
#define I2S_IT_UDR ((uint8_t)0x53)
|
||||
#define SPI_I2S_IT_FRE ((uint8_t)0x58)
|
||||
|
||||
#define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \
|
||||
((IT) == SPI_I2S_IT_RXNE) || \
|
||||
((IT) == SPI_I2S_IT_ERR))
|
||||
|
||||
#define SPI_I2S_IT_OVR ((uint8_t)0x56)
|
||||
#define SPI_IT_MODF ((uint8_t)0x55)
|
||||
#define SPI_IT_CRCERR ((uint8_t)0x54)
|
||||
|
||||
#define IS_SPI_I2S_CLEAR_IT(IT) (((IT) == SPI_IT_CRCERR))
|
||||
|
||||
#define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE) || ((IT) == SPI_I2S_IT_TXE) || \
|
||||
((IT) == SPI_IT_CRCERR) || ((IT) == SPI_IT_MODF) || \
|
||||
((IT) == SPI_I2S_IT_OVR) || ((IT) == I2S_IT_UDR) ||\
|
||||
((IT) == SPI_I2S_IT_FRE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_I2S_flags_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001)
|
||||
#define SPI_I2S_FLAG_TXE ((uint16_t)0x0002)
|
||||
#define I2S_FLAG_CHSIDE ((uint16_t)0x0004)
|
||||
#define I2S_FLAG_UDR ((uint16_t)0x0008)
|
||||
#define SPI_FLAG_CRCERR ((uint16_t)0x0010)
|
||||
#define SPI_FLAG_MODF ((uint16_t)0x0020)
|
||||
#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040)
|
||||
#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080)
|
||||
#define SPI_I2S_FLAG_FRE ((uint16_t)0x0100)
|
||||
|
||||
#define IS_SPI_I2S_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR))
|
||||
#define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \
|
||||
((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \
|
||||
((FLAG) == I2S_FLAG_UDR) || ((FLAG) == I2S_FLAG_CHSIDE) || \
|
||||
((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE)|| \
|
||||
((FLAG) == SPI_I2S_FLAG_FRE))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_CRC_polynomial
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_I2S_Legacy
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define SPI_DMAReq_Tx SPI_I2S_DMAReq_Tx
|
||||
#define SPI_DMAReq_Rx SPI_I2S_DMAReq_Rx
|
||||
#define SPI_IT_TXE SPI_I2S_IT_TXE
|
||||
#define SPI_IT_RXNE SPI_I2S_IT_RXNE
|
||||
#define SPI_IT_ERR SPI_I2S_IT_ERR
|
||||
#define SPI_IT_OVR SPI_I2S_IT_OVR
|
||||
#define SPI_FLAG_RXNE SPI_I2S_FLAG_RXNE
|
||||
#define SPI_FLAG_TXE SPI_I2S_FLAG_TXE
|
||||
#define SPI_FLAG_OVR SPI_I2S_FLAG_OVR
|
||||
#define SPI_FLAG_BSY SPI_I2S_FLAG_BSY
|
||||
#define SPI_DeInit SPI_I2S_DeInit
|
||||
#define SPI_ITConfig SPI_I2S_ITConfig
|
||||
#define SPI_DMACmd SPI_I2S_DMACmd
|
||||
#define SPI_SendData SPI_I2S_SendData
|
||||
#define SPI_ReceiveData SPI_I2S_ReceiveData
|
||||
#define SPI_GetFlagStatus SPI_I2S_GetFlagStatus
|
||||
#define SPI_ClearFlag SPI_I2S_ClearFlag
|
||||
#define SPI_GetITStatus SPI_I2S_GetITStatus
|
||||
#define SPI_ClearITPendingBit SPI_I2S_ClearITPendingBit
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
|
||||
/* Function used to set the SPI configuration to the default reset state *****/
|
||||
void SPI_I2S_DeInit(SPI_TypeDef* SPIx);
|
||||
|
||||
/* Initialization and Configuration functions *********************************/
|
||||
void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct);
|
||||
void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct);
|
||||
void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct);
|
||||
void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct);
|
||||
void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
|
||||
void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
|
||||
void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize);
|
||||
void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction);
|
||||
void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft);
|
||||
void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
|
||||
|
||||
/* Data transfers functions ***************************************************/
|
||||
void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data);
|
||||
uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx);
|
||||
|
||||
/* Hardware CRC Calculation functions *****************************************/
|
||||
void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState);
|
||||
void SPI_TransmitCRC(SPI_TypeDef* SPIx);
|
||||
uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC);
|
||||
uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx);
|
||||
|
||||
/* DMA transfers management functions *****************************************/
|
||||
void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState);
|
||||
|
||||
/* Interrupts and flags management functions **********************************/
|
||||
void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState);
|
||||
FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
|
||||
void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
|
||||
ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
|
||||
void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__STM32L1xx_SPI_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,476 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32l1xx_syscfg.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.1
|
||||
* @date 05-March-2012
|
||||
* @brief This file contains all the functions prototypes for the SYSCFG
|
||||
* firmware library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/*!< Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32L1xx_SYSCFG_H
|
||||
#define __STM32L1xx_SYSCFG_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*!< Includes ------------------------------------------------------------------*/
|
||||
#include "stm32l1xx.h"
|
||||
|
||||
/** @addtogroup STM32L1xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup SYSCFG
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup SYSCFG_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_Port_Sources
|
||||
* @{
|
||||
*/
|
||||
#define EXTI_PortSourceGPIOA ((uint8_t)0x00)
|
||||
#define EXTI_PortSourceGPIOB ((uint8_t)0x01)
|
||||
#define EXTI_PortSourceGPIOC ((uint8_t)0x02)
|
||||
#define EXTI_PortSourceGPIOD ((uint8_t)0x03)
|
||||
#define EXTI_PortSourceGPIOE ((uint8_t)0x04)
|
||||
#define EXTI_PortSourceGPIOH ((uint8_t)0x05)
|
||||
#define EXTI_PortSourceGPIOF ((uint8_t)0x06)
|
||||
#define EXTI_PortSourceGPIOG ((uint8_t)0x07)
|
||||
|
||||
#define IS_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == EXTI_PortSourceGPIOA) || \
|
||||
((PORTSOURCE) == EXTI_PortSourceGPIOB) || \
|
||||
((PORTSOURCE) == EXTI_PortSourceGPIOC) || \
|
||||
((PORTSOURCE) == EXTI_PortSourceGPIOD) || \
|
||||
((PORTSOURCE) == EXTI_PortSourceGPIOE) || \
|
||||
((PORTSOURCE) == EXTI_PortSourceGPIOF) || \
|
||||
((PORTSOURCE) == EXTI_PortSourceGPIOG) || \
|
||||
((PORTSOURCE) == EXTI_PortSourceGPIOH))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_Pin_sources
|
||||
* @{
|
||||
*/
|
||||
#define EXTI_PinSource0 ((uint8_t)0x00)
|
||||
#define EXTI_PinSource1 ((uint8_t)0x01)
|
||||
#define EXTI_PinSource2 ((uint8_t)0x02)
|
||||
#define EXTI_PinSource3 ((uint8_t)0x03)
|
||||
#define EXTI_PinSource4 ((uint8_t)0x04)
|
||||
#define EXTI_PinSource5 ((uint8_t)0x05)
|
||||
#define EXTI_PinSource6 ((uint8_t)0x06)
|
||||
#define EXTI_PinSource7 ((uint8_t)0x07)
|
||||
#define EXTI_PinSource8 ((uint8_t)0x08)
|
||||
#define EXTI_PinSource9 ((uint8_t)0x09)
|
||||
#define EXTI_PinSource10 ((uint8_t)0x0A)
|
||||
#define EXTI_PinSource11 ((uint8_t)0x0B)
|
||||
#define EXTI_PinSource12 ((uint8_t)0x0C)
|
||||
#define EXTI_PinSource13 ((uint8_t)0x0D)
|
||||
#define EXTI_PinSource14 ((uint8_t)0x0E)
|
||||
#define EXTI_PinSource15 ((uint8_t)0x0F)
|
||||
#define IS_EXTI_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == EXTI_PinSource0) || \
|
||||
((PINSOURCE) == EXTI_PinSource1) || \
|
||||
((PINSOURCE) == EXTI_PinSource2) || \
|
||||
((PINSOURCE) == EXTI_PinSource3) || \
|
||||
((PINSOURCE) == EXTI_PinSource4) || \
|
||||
((PINSOURCE) == EXTI_PinSource5) || \
|
||||
((PINSOURCE) == EXTI_PinSource6) || \
|
||||
((PINSOURCE) == EXTI_PinSource7) || \
|
||||
((PINSOURCE) == EXTI_PinSource8) || \
|
||||
((PINSOURCE) == EXTI_PinSource9) || \
|
||||
((PINSOURCE) == EXTI_PinSource10) || \
|
||||
((PINSOURCE) == EXTI_PinSource11) || \
|
||||
((PINSOURCE) == EXTI_PinSource12) || \
|
||||
((PINSOURCE) == EXTI_PinSource13) || \
|
||||
((PINSOURCE) == EXTI_PinSource14) || \
|
||||
((PINSOURCE) == EXTI_PinSource15))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SYSCFG_Memory_Remap_Config
|
||||
* @{
|
||||
*/
|
||||
#define SYSCFG_MemoryRemap_Flash ((uint8_t)0x00)
|
||||
#define SYSCFG_MemoryRemap_SystemFlash ((uint8_t)0x01)
|
||||
#define SYSCFG_MemoryRemap_FSMC ((uint8_t)0x02)
|
||||
#define SYSCFG_MemoryRemap_SRAM ((uint8_t)0x03)
|
||||
|
||||
#define IS_SYSCFG_MEMORY_REMAP_CONFING(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash) || \
|
||||
((REMAP) == SYSCFG_MemoryRemap_SystemFlash) || \
|
||||
((REMAP) == SYSCFG_MemoryRemap_FSMC) || \
|
||||
((REMAP) == SYSCFG_MemoryRemap_SRAM))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RI_Resistor
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RI_Resistor_10KPU COMP_CSR_10KPU
|
||||
#define RI_Resistor_400KPU COMP_CSR_400KPU
|
||||
#define RI_Resistor_10KPD COMP_CSR_10KPD
|
||||
#define RI_Resistor_400KPD COMP_CSR_400KPD
|
||||
|
||||
#define IS_RI_RESISTOR(RESISTOR) (((RESISTOR) == COMP_CSR_10KPU) || \
|
||||
((RESISTOR) == COMP_CSR_400KPU) || \
|
||||
((RESISTOR) == COMP_CSR_10KPD) || \
|
||||
((RESISTOR) == COMP_CSR_400KPD))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RI_Channel
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RI_Channel_3 ((uint32_t)0x04000000)
|
||||
#define RI_Channel_8 ((uint32_t)0x08000000)
|
||||
#define RI_Channel_13 ((uint32_t)0x10000000)
|
||||
|
||||
#define IS_RI_CHANNEL(CHANNEL) (((CHANNEL) == RI_Channel_3) || \
|
||||
((CHANNEL) == RI_Channel_8) || \
|
||||
((CHANNEL) == RI_Channel_13))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RI_ChannelSpeed
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RI_ChannelSpeed_Fast ((uint32_t)0x00000000)
|
||||
#define RI_ChannelSpeed_Slow ((uint32_t)0x00000001)
|
||||
|
||||
#define IS_RI_CHANNELSPEED(SPEED) (((SPEED) == RI_ChannelSpeed_Fast) || \
|
||||
((SPEED) == RI_ChannelSpeed_Slow))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RI_InputCapture
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RI_InputCapture_IC1 RI_ICR_IC1 /*!< Input Capture 1 */
|
||||
#define RI_InputCapture_IC2 RI_ICR_IC2 /*!< Input Capture 2 */
|
||||
#define RI_InputCapture_IC3 RI_ICR_IC3 /*!< Input Capture 3 */
|
||||
#define RI_InputCapture_IC4 RI_ICR_IC4 /*!< Input Capture 4 */
|
||||
|
||||
#define IS_RI_INPUTCAPTURE(INPUTCAPTURE) ((((INPUTCAPTURE) & (uint32_t)0xFFC2FFFF) == 0x00) && ((INPUTCAPTURE) != (uint32_t)0x00))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_Select
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define TIM_Select_None ((uint32_t)0x00000000) /*!< None selected */
|
||||
#define TIM_Select_TIM2 ((uint32_t)0x00010000) /*!< Timer 2 selected */
|
||||
#define TIM_Select_TIM3 ((uint32_t)0x00020000) /*!< Timer 3 selected */
|
||||
#define TIM_Select_TIM4 ((uint32_t)0x00030000) /*!< Timer 4 selected */
|
||||
|
||||
#define IS_RI_TIM(TIM) (((TIM) == TIM_Select_None) || \
|
||||
((TIM) == TIM_Select_TIM2) || \
|
||||
((TIM) == TIM_Select_TIM3) || \
|
||||
((TIM) == TIM_Select_TIM4))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RI_InputCaptureRouting
|
||||
* @{
|
||||
*/
|
||||
/* TIMx_IC1 TIMx_IC2 TIMx_IC3 TIMx_IC4 */
|
||||
#define RI_InputCaptureRouting_0 ((uint32_t)0x00000000) /* PA0 PA1 PA2 PA3 */
|
||||
#define RI_InputCaptureRouting_1 ((uint32_t)0x00000001) /* PA4 PA5 PA6 PA7 */
|
||||
#define RI_InputCaptureRouting_2 ((uint32_t)0x00000002) /* PA8 PA9 PA10 PA11 */
|
||||
#define RI_InputCaptureRouting_3 ((uint32_t)0x00000003) /* PA12 PA13 PA14 PA15 */
|
||||
#define RI_InputCaptureRouting_4 ((uint32_t)0x00000004) /* PC0 PC1 PC2 PC3 */
|
||||
#define RI_InputCaptureRouting_5 ((uint32_t)0x00000005) /* PC4 PC5 PC6 PC7 */
|
||||
#define RI_InputCaptureRouting_6 ((uint32_t)0x00000006) /* PC8 PC9 PC10 PC11 */
|
||||
#define RI_InputCaptureRouting_7 ((uint32_t)0x00000007) /* PC12 PC13 PC14 PC15 */
|
||||
#define RI_InputCaptureRouting_8 ((uint32_t)0x00000008) /* PD0 PD1 PD2 PD3 */
|
||||
#define RI_InputCaptureRouting_9 ((uint32_t)0x00000009) /* PD4 PD5 PD6 PD7 */
|
||||
#define RI_InputCaptureRouting_10 ((uint32_t)0x0000000A) /* PD8 PD9 PD10 PD11 */
|
||||
#define RI_InputCaptureRouting_11 ((uint32_t)0x0000000B) /* PD12 PD13 PD14 PD15 */
|
||||
#define RI_InputCaptureRouting_12 ((uint32_t)0x0000000C) /* PE0 PE1 PE2 PE3 */
|
||||
#define RI_InputCaptureRouting_13 ((uint32_t)0x0000000D) /* PE4 PE5 PE6 PE7 */
|
||||
#define RI_InputCaptureRouting_14 ((uint32_t)0x0000000E) /* PE8 PE9 PE10 PE11 */
|
||||
#define RI_InputCaptureRouting_15 ((uint32_t)0x0000000F) /* PE12 PE13 PE14 PE15 */
|
||||
|
||||
#define IS_RI_INPUTCAPTURE_ROUTING(ROUTING) (((ROUTING) == RI_InputCaptureRouting_0) || \
|
||||
((ROUTING) == RI_InputCaptureRouting_1) || \
|
||||
((ROUTING) == RI_InputCaptureRouting_2) || \
|
||||
((ROUTING) == RI_InputCaptureRouting_3) || \
|
||||
((ROUTING) == RI_InputCaptureRouting_4) || \
|
||||
((ROUTING) == RI_InputCaptureRouting_5) || \
|
||||
((ROUTING) == RI_InputCaptureRouting_6) || \
|
||||
((ROUTING) == RI_InputCaptureRouting_7) || \
|
||||
((ROUTING) == RI_InputCaptureRouting_8) || \
|
||||
((ROUTING) == RI_InputCaptureRouting_9) || \
|
||||
((ROUTING) == RI_InputCaptureRouting_10) || \
|
||||
((ROUTING) == RI_InputCaptureRouting_11) || \
|
||||
((ROUTING) == RI_InputCaptureRouting_12) || \
|
||||
((ROUTING) == RI_InputCaptureRouting_13) || \
|
||||
((ROUTING) == RI_InputCaptureRouting_14) || \
|
||||
((ROUTING) == RI_InputCaptureRouting_15))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RI_IOSwitch
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* ASCR1 I/O switch: bit 31 is set to '1' to indicate that the mask is in ASCR1 register */
|
||||
#define RI_IOSwitch_CH0 ((uint32_t)0x80000001)
|
||||
#define RI_IOSwitch_CH1 ((uint32_t)0x80000002)
|
||||
#define RI_IOSwitch_CH2 ((uint32_t)0x80000004)
|
||||
#define RI_IOSwitch_CH3 ((uint32_t)0x80000008)
|
||||
#define RI_IOSwitch_CH4 ((uint32_t)0x80000010)
|
||||
#define RI_IOSwitch_CH5 ((uint32_t)0x80000020)
|
||||
#define RI_IOSwitch_CH6 ((uint32_t)0x80000040)
|
||||
#define RI_IOSwitch_CH7 ((uint32_t)0x80000080)
|
||||
#define RI_IOSwitch_CH8 ((uint32_t)0x80000100)
|
||||
#define RI_IOSwitch_CH9 ((uint32_t)0x80000200)
|
||||
#define RI_IOSwitch_CH10 ((uint32_t)0x80000400)
|
||||
#define RI_IOSwitch_CH11 ((uint32_t)0x80000800)
|
||||
#define RI_IOSwitch_CH12 ((uint32_t)0x80001000)
|
||||
#define RI_IOSwitch_CH13 ((uint32_t)0x80002000)
|
||||
#define RI_IOSwitch_CH14 ((uint32_t)0x80004000)
|
||||
#define RI_IOSwitch_CH15 ((uint32_t)0x80008000)
|
||||
#define RI_IOSwitch_CH31 ((uint32_t)0x80010000)
|
||||
#define RI_IOSwitch_CH18 ((uint32_t)0x80040000)
|
||||
#define RI_IOSwitch_CH19 ((uint32_t)0x80080000)
|
||||
#define RI_IOSwitch_CH20 ((uint32_t)0x80100000)
|
||||
#define RI_IOSwitch_CH21 ((uint32_t)0x80200000)
|
||||
#define RI_IOSwitch_CH22 ((uint32_t)0x80400000)
|
||||
#define RI_IOSwitch_CH23 ((uint32_t)0x80800000)
|
||||
#define RI_IOSwitch_CH24 ((uint32_t)0x81000000)
|
||||
#define RI_IOSwitch_CH25 ((uint32_t)0x82000000)
|
||||
#define RI_IOSwitch_VCOMP ((uint32_t)0x84000000) /* VCOMP is an internal switch used to connect
|
||||
selected channel to COMP1 non inverting input */
|
||||
#define RI_IOSwitch_CH27 ((uint32_t)0x88000000)
|
||||
#define RI_IOSwitch_CH28 ((uint32_t)0x90000000)
|
||||
#define RI_IOSwitch_CH29 ((uint32_t)0xA0000000)
|
||||
#define RI_IOSwitch_CH30 ((uint32_t)0xC0000000)
|
||||
|
||||
/* ASCR2 IO switch: bit 31 is set to '0' to indicate that the mask is in ASCR2 register */
|
||||
#define RI_IOSwitch_GR10_1 ((uint32_t)0x00000001)
|
||||
#define RI_IOSwitch_GR10_2 ((uint32_t)0x00000002)
|
||||
#define RI_IOSwitch_GR10_3 ((uint32_t)0x00000004)
|
||||
#define RI_IOSwitch_GR10_4 ((uint32_t)0x00000008)
|
||||
#define RI_IOSwitch_GR6_1 ((uint32_t)0x00000010)
|
||||
#define RI_IOSwitch_GR6_2 ((uint32_t)0x00000020)
|
||||
#define RI_IOSwitch_GR5_1 ((uint32_t)0x00000040)
|
||||
#define RI_IOSwitch_GR5_2 ((uint32_t)0x00000080)
|
||||
#define RI_IOSwitch_GR5_3 ((uint32_t)0x00000100)
|
||||
#define RI_IOSwitch_GR4_1 ((uint32_t)0x00000200)
|
||||
#define RI_IOSwitch_GR4_2 ((uint32_t)0x00000400)
|
||||
#define RI_IOSwitch_GR4_3 ((uint32_t)0x00000800)
|
||||
#define RI_IOSwitch_GR4_4 ((uint32_t)0x00008000)
|
||||
#define RI_IOSwitch_CH0b ((uint32_t)0x00010000)
|
||||
#define RI_IOSwitch_CH1b ((uint32_t)0x00020000)
|
||||
#define RI_IOSwitch_CH2b ((uint32_t)0x00040000)
|
||||
#define RI_IOSwitch_CH3b ((uint32_t)0x00080000)
|
||||
#define RI_IOSwitch_CH6b ((uint32_t)0x00100000)
|
||||
#define RI_IOSwitch_CH7b ((uint32_t)0x00200000)
|
||||
#define RI_IOSwitch_CH8b ((uint32_t)0x00400000)
|
||||
#define RI_IOSwitch_CH9b ((uint32_t)0x00800000)
|
||||
#define RI_IOSwitch_CH10b ((uint32_t)0x01000000)
|
||||
#define RI_IOSwitch_CH11b ((uint32_t)0x02000000)
|
||||
#define RI_IOSwitch_CH12b ((uint32_t)0x04000000)
|
||||
#define RI_IOSwitch_GR6_3 ((uint32_t)0x08000000)
|
||||
#define RI_IOSwitch_GR6_4 ((uint32_t)0x10000000)
|
||||
#define RI_IOSwitch_GR5_4 ((uint32_t)0x20000000)
|
||||
|
||||
|
||||
#define IS_RI_IOSWITCH(IOSWITCH) (((IOSWITCH) == RI_IOSwitch_CH0) || \
|
||||
((IOSWITCH) == RI_IOSwitch_CH1) || \
|
||||
((IOSWITCH) == RI_IOSwitch_CH2) || \
|
||||
((IOSWITCH) == RI_IOSwitch_CH3) || \
|
||||
((IOSWITCH) == RI_IOSwitch_CH4) || \
|
||||
((IOSWITCH) == RI_IOSwitch_CH5) || \
|
||||
((IOSWITCH) == RI_IOSwitch_CH6) || \
|
||||
((IOSWITCH) == RI_IOSwitch_CH7) || \
|
||||
((IOSWITCH) == RI_IOSwitch_CH8) || \
|
||||
((IOSWITCH) == RI_IOSwitch_CH9) || \
|
||||
((IOSWITCH) == RI_IOSwitch_CH10) || \
|
||||
((IOSWITCH) == RI_IOSwitch_CH11) || \
|
||||
((IOSWITCH) == RI_IOSwitch_CH12) || \
|
||||
((IOSWITCH) == RI_IOSwitch_CH13) || \
|
||||
((IOSWITCH) == RI_IOSwitch_CH14) || \
|
||||
((IOSWITCH) == RI_IOSwitch_CH15) || \
|
||||
((IOSWITCH) == RI_IOSwitch_CH18) || \
|
||||
((IOSWITCH) == RI_IOSwitch_CH19) || \
|
||||
((IOSWITCH) == RI_IOSwitch_CH20) || \
|
||||
((IOSWITCH) == RI_IOSwitch_CH21) || \
|
||||
((IOSWITCH) == RI_IOSwitch_CH22) || \
|
||||
((IOSWITCH) == RI_IOSwitch_CH23) || \
|
||||
((IOSWITCH) == RI_IOSwitch_CH24) || \
|
||||
((IOSWITCH) == RI_IOSwitch_CH25) || \
|
||||
((IOSWITCH) == RI_IOSwitch_VCOMP) || \
|
||||
((IOSWITCH) == RI_IOSwitch_CH27) || \
|
||||
((IOSWITCH) == RI_IOSwitch_CH28) || \
|
||||
((IOSWITCH) == RI_IOSwitch_CH29) || \
|
||||
((IOSWITCH) == RI_IOSwitch_CH30) || \
|
||||
((IOSWITCH) == RI_IOSwitch_CH31) || \
|
||||
((IOSWITCH) == RI_IOSwitch_GR10_1) || \
|
||||
((IOSWITCH) == RI_IOSwitch_GR10_2) || \
|
||||
((IOSWITCH) == RI_IOSwitch_GR10_3) || \
|
||||
((IOSWITCH) == RI_IOSwitch_GR10_4) || \
|
||||
((IOSWITCH) == RI_IOSwitch_GR6_1) || \
|
||||
((IOSWITCH) == RI_IOSwitch_GR6_2) || \
|
||||
((IOSWITCH) == RI_IOSwitch_GR6_3) || \
|
||||
((IOSWITCH) == RI_IOSwitch_GR6_4) || \
|
||||
((IOSWITCH) == RI_IOSwitch_GR5_1) || \
|
||||
((IOSWITCH) == RI_IOSwitch_GR5_2) || \
|
||||
((IOSWITCH) == RI_IOSwitch_GR5_3) || \
|
||||
((IOSWITCH) == RI_IOSwitch_GR5_4) || \
|
||||
((IOSWITCH) == RI_IOSwitch_GR4_1) || \
|
||||
((IOSWITCH) == RI_IOSwitch_GR4_2) || \
|
||||
((IOSWITCH) == RI_IOSwitch_GR4_3) || \
|
||||
((IOSWITCH) == RI_IOSwitch_GR4_4) || \
|
||||
((IOSWITCH) == RI_IOSwitch_CH0b) || \
|
||||
((IOSWITCH) == RI_IOSwitch_CH1b) || \
|
||||
((IOSWITCH) == RI_IOSwitch_CH2b) || \
|
||||
((IOSWITCH) == RI_IOSwitch_CH3b) || \
|
||||
((IOSWITCH) == RI_IOSwitch_CH6b) || \
|
||||
((IOSWITCH) == RI_IOSwitch_CH7b) || \
|
||||
((IOSWITCH) == RI_IOSwitch_CH8b) || \
|
||||
((IOSWITCH) == RI_IOSwitch_CH9b) || \
|
||||
((IOSWITCH) == RI_IOSwitch_CH10b) || \
|
||||
((IOSWITCH) == RI_IOSwitch_CH11b) || \
|
||||
((IOSWITCH) == RI_IOSwitch_CH12b))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RI_Port
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define RI_PortA ((uint8_t)0x01) /*!< GPIOA selected */
|
||||
#define RI_PortB ((uint8_t)0x02) /*!< GPIOB selected */
|
||||
#define RI_PortC ((uint8_t)0x03) /*!< GPIOC selected */
|
||||
#define RI_PortD ((uint8_t)0x04) /*!< GPIOD selected */
|
||||
#define RI_PortE ((uint8_t)0x05) /*!< GPIOE selected */
|
||||
#define RI_PortF ((uint8_t)0x06) /*!< GPIOF selected */
|
||||
#define RI_PortG ((uint8_t)0x07) /*!< GPIOG selected */
|
||||
|
||||
#define IS_RI_PORT(PORT) (((PORT) == RI_PortA) || \
|
||||
((PORT) == RI_PortB) || \
|
||||
((PORT) == RI_PortC) || \
|
||||
((PORT) == RI_PortD) || \
|
||||
((PORT) == RI_PortE) || \
|
||||
((PORT) == RI_PortF) || \
|
||||
((PORT) == RI_PortG))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup RI_Pin define
|
||||
* @{
|
||||
*/
|
||||
#define RI_Pin_0 ((uint16_t)0x0001) /*!< Pin 0 selected */
|
||||
#define RI_Pin_1 ((uint16_t)0x0002) /*!< Pin 1 selected */
|
||||
#define RI_Pin_2 ((uint16_t)0x0004) /*!< Pin 2 selected */
|
||||
#define RI_Pin_3 ((uint16_t)0x0008) /*!< Pin 3 selected */
|
||||
#define RI_Pin_4 ((uint16_t)0x0010) /*!< Pin 4 selected */
|
||||
#define RI_Pin_5 ((uint16_t)0x0020) /*!< Pin 5 selected */
|
||||
#define RI_Pin_6 ((uint16_t)0x0040) /*!< Pin 6 selected */
|
||||
#define RI_Pin_7 ((uint16_t)0x0080) /*!< Pin 7 selected */
|
||||
#define RI_Pin_8 ((uint16_t)0x0100) /*!< Pin 8 selected */
|
||||
#define RI_Pin_9 ((uint16_t)0x0200) /*!< Pin 9 selected */
|
||||
#define RI_Pin_10 ((uint16_t)0x0400) /*!< Pin 10 selected */
|
||||
#define RI_Pin_11 ((uint16_t)0x0800) /*!< Pin 11 selected */
|
||||
#define RI_Pin_12 ((uint16_t)0x1000) /*!< Pin 12 selected */
|
||||
#define RI_Pin_13 ((uint16_t)0x2000) /*!< Pin 13 selected */
|
||||
#define RI_Pin_14 ((uint16_t)0x4000) /*!< Pin 14 selected */
|
||||
#define RI_Pin_15 ((uint16_t)0x8000) /*!< Pin 15 selected */
|
||||
#define RI_Pin_All ((uint16_t)0xFFFF) /*!< All pins selected */
|
||||
|
||||
#define IS_RI_PIN(PIN) ((PIN) != (uint16_t)0x00)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
|
||||
/* Function used to set the SYSCFG and RI configuration to the default reset state **/
|
||||
void SYSCFG_DeInit(void);
|
||||
void SYSCFG_RIDeInit(void);
|
||||
|
||||
/* SYSCFG Initialization and Configuration functions **************************/
|
||||
void SYSCFG_MemoryRemapConfig(uint8_t SYSCFG_MemoryRemap);
|
||||
uint32_t SYSCFG_GetBootMode(void);
|
||||
void SYSCFG_USBPuCmd(FunctionalState NewState);
|
||||
void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex);
|
||||
|
||||
/* RI Initialization and Configuration functions ******************************/
|
||||
void SYSCFG_RITIMSelect(uint32_t TIM_Select);
|
||||
void SYSCFG_RITIMInputCaptureConfig(uint32_t RI_InputCapture, uint32_t RI_InputCaptureRouting);
|
||||
void SYSCFG_RIResistorConfig(uint32_t RI_Resistor, FunctionalState NewState);
|
||||
void SYSCFG_RIChannelSpeedConfig(uint32_t RI_Channel, uint32_t RI_ChannelSpeed);
|
||||
void SYSCFG_RISwitchControlModeCmd(FunctionalState NewState);
|
||||
void SYSCFG_RIIOSwitchConfig(uint32_t RI_IOSwitch, FunctionalState NewState);
|
||||
void SYSCFG_RIHysteresisConfig(uint8_t RI_Port, uint16_t RI_Pin, FunctionalState NewState);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__STM32L1xx_SYSCFG_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,977 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32l1xx_tim.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.1
|
||||
* @date 05-March-2012
|
||||
* @brief This file contains all the functions prototypes for the TIM firmware
|
||||
* library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32L1xx_TIM_H
|
||||
#define __STM32L1xx_TIM_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32l1xx.h"
|
||||
|
||||
/** @addtogroup STM32L1xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup TIM
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief TIM Time Base Init structure definition
|
||||
* @note This structure is used with all TIMx except for TIM6 and TIM7.
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint16_t TIM_Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
|
||||
This parameter can be a number between 0x0000 and 0xFFFF */
|
||||
|
||||
uint16_t TIM_CounterMode; /*!< Specifies the counter mode.
|
||||
This parameter can be a value of @ref TIM_Counter_Mode */
|
||||
|
||||
uint32_t TIM_Period; /*!< Specifies the period value to be loaded into the active
|
||||
Auto-Reload Register at the next update event.
|
||||
This parameter must be a number between 0x0000 and 0xFFFF. */
|
||||
|
||||
uint16_t TIM_ClockDivision; /*!< Specifies the clock division.
|
||||
This parameter can be a value of @ref TIM_Clock_Division_CKD */
|
||||
|
||||
} TIM_TimeBaseInitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief TIM Output Compare Init structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint16_t TIM_OCMode; /*!< Specifies the TIM mode.
|
||||
This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
|
||||
|
||||
uint16_t TIM_OutputState; /*!< Specifies the TIM Output Compare state.
|
||||
This parameter can be a value of @ref TIM_Output_Compare_state */
|
||||
|
||||
uint32_t TIM_Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
|
||||
This parameter can be a number between 0x0000 and 0xFFFF */
|
||||
|
||||
uint16_t TIM_OCPolarity; /*!< Specifies the output polarity.
|
||||
This parameter can be a value of @ref TIM_Output_Compare_Polarity */
|
||||
|
||||
} TIM_OCInitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief TIM Input Capture Init structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
|
||||
uint16_t TIM_Channel; /*!< Specifies the TIM channel.
|
||||
This parameter can be a value of @ref TIM_Channel */
|
||||
|
||||
uint16_t TIM_ICPolarity; /*!< Specifies the active edge of the input signal.
|
||||
This parameter can be a value of @ref TIM_Input_Capture_Polarity */
|
||||
|
||||
uint16_t TIM_ICSelection; /*!< Specifies the input.
|
||||
This parameter can be a value of @ref TIM_Input_Capture_Selection */
|
||||
|
||||
uint16_t TIM_ICPrescaler; /*!< Specifies the Input Capture Prescaler.
|
||||
This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
|
||||
|
||||
uint16_t TIM_ICFilter; /*!< Specifies the input capture filter.
|
||||
This parameter can be a number between 0x0 and 0xF */
|
||||
} TIM_ICInitTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
|
||||
/** @defgroup TIM_Exported_constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM2) || \
|
||||
((PERIPH) == TIM3) || \
|
||||
((PERIPH) == TIM4) || \
|
||||
((PERIPH) == TIM5) || \
|
||||
((PERIPH) == TIM6) || \
|
||||
((PERIPH) == TIM7) || \
|
||||
((PERIPH) == TIM9) || \
|
||||
((PERIPH) == TIM10) || \
|
||||
((PERIPH) == TIM11))
|
||||
|
||||
/* LIST1: TIM2, TIM3, TIM4, TIM5, TIM9, TIM10 and TIM11 */
|
||||
#define IS_TIM_LIST1_PERIPH(PERIPH) (((PERIPH) == TIM2) || \
|
||||
((PERIPH) == TIM3) || \
|
||||
((PERIPH) == TIM4) || \
|
||||
((PERIPH) == TIM5) || \
|
||||
((PERIPH) == TIM9) || \
|
||||
((PERIPH) == TIM10) || \
|
||||
((PERIPH) == TIM11))
|
||||
|
||||
/* LIST3: TIM2, TIM3, TIM4 and TIM5 */
|
||||
#define IS_TIM_LIST3_PERIPH(PERIPH) (((PERIPH) == TIM2) || \
|
||||
((PERIPH) == TIM3) || \
|
||||
((PERIPH) == TIM4) || \
|
||||
((PERIPH) == TIM5))
|
||||
|
||||
/* LIST2: TIM2, TIM3, TIM4, TIM5 and TIM9 */
|
||||
#define IS_TIM_LIST2_PERIPH(PERIPH) (((PERIPH) == TIM2) || \
|
||||
((PERIPH) == TIM3) || \
|
||||
((PERIPH) == TIM4) || \
|
||||
((PERIPH) == TIM5) || \
|
||||
((PERIPH) == TIM9))
|
||||
|
||||
/* LIST5: TIM2, TIM3, TIM4, TIM5, TIM6, TIM7 and TIM9 */
|
||||
#define IS_TIM_LIST5_PERIPH(PERIPH) (((PERIPH) == TIM2) || \
|
||||
((PERIPH) == TIM3) || \
|
||||
((PERIPH) == TIM4) || \
|
||||
((PERIPH) == TIM5) ||\
|
||||
((PERIPH) == TIM6) || \
|
||||
((PERIPH) == TIM7) ||\
|
||||
((PERIPH) == TIM9))
|
||||
|
||||
/* LIST4: TIM2, TIM3, TIM4, TIM5, TIM6 and TIM7 */
|
||||
#define IS_TIM_LIST4_PERIPH(PERIPH) (((PERIPH) == TIM2) || \
|
||||
((PERIPH) == TIM3) || \
|
||||
((PERIPH) == TIM4) || \
|
||||
((PERIPH) == TIM5) ||\
|
||||
((PERIPH) == TIM6) || \
|
||||
((PERIPH) == TIM7))
|
||||
|
||||
/* LIST6: TIM2, TIM3, TIM9, TIM10 and TIM11 */
|
||||
#define IS_TIM_LIST6_PERIPH(PERIPH) (((PERIPH) == TIM2) || \
|
||||
((PERIPH) == TIM3) || \
|
||||
((PERIPH) == TIM9) || \
|
||||
((PERIPH) == TIM10) || \
|
||||
((PERIPH) == TIM11))
|
||||
|
||||
|
||||
|
||||
/** @defgroup TIM_Output_Compare_and_PWM_modes
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define TIM_OCMode_Timing ((uint16_t)0x0000)
|
||||
#define TIM_OCMode_Active ((uint16_t)0x0010)
|
||||
#define TIM_OCMode_Inactive ((uint16_t)0x0020)
|
||||
#define TIM_OCMode_Toggle ((uint16_t)0x0030)
|
||||
#define TIM_OCMode_PWM1 ((uint16_t)0x0060)
|
||||
#define TIM_OCMode_PWM2 ((uint16_t)0x0070)
|
||||
#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \
|
||||
((MODE) == TIM_OCMode_Active) || \
|
||||
((MODE) == TIM_OCMode_Inactive) || \
|
||||
((MODE) == TIM_OCMode_Toggle)|| \
|
||||
((MODE) == TIM_OCMode_PWM1) || \
|
||||
((MODE) == TIM_OCMode_PWM2))
|
||||
#define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \
|
||||
((MODE) == TIM_OCMode_Active) || \
|
||||
((MODE) == TIM_OCMode_Inactive) || \
|
||||
((MODE) == TIM_OCMode_Toggle)|| \
|
||||
((MODE) == TIM_OCMode_PWM1) || \
|
||||
((MODE) == TIM_OCMode_PWM2) || \
|
||||
((MODE) == TIM_ForcedAction_Active) || \
|
||||
((MODE) == TIM_ForcedAction_InActive))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_One_Pulse_Mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define TIM_OPMode_Single ((uint16_t)0x0008)
|
||||
#define TIM_OPMode_Repetitive ((uint16_t)0x0000)
|
||||
#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \
|
||||
((MODE) == TIM_OPMode_Repetitive))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_Channel
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define TIM_Channel_1 ((uint16_t)0x0000)
|
||||
#define TIM_Channel_2 ((uint16_t)0x0004)
|
||||
#define TIM_Channel_3 ((uint16_t)0x0008)
|
||||
#define TIM_Channel_4 ((uint16_t)0x000C)
|
||||
|
||||
#define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
|
||||
((CHANNEL) == TIM_Channel_2) || \
|
||||
((CHANNEL) == TIM_Channel_3) || \
|
||||
((CHANNEL) == TIM_Channel_4))
|
||||
|
||||
#define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
|
||||
((CHANNEL) == TIM_Channel_2))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_Clock_Division_CKD
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define TIM_CKD_DIV1 ((uint16_t)0x0000)
|
||||
#define TIM_CKD_DIV2 ((uint16_t)0x0100)
|
||||
#define TIM_CKD_DIV4 ((uint16_t)0x0200)
|
||||
#define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \
|
||||
((DIV) == TIM_CKD_DIV2) || \
|
||||
((DIV) == TIM_CKD_DIV4))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_Counter_Mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define TIM_CounterMode_Up ((uint16_t)0x0000)
|
||||
#define TIM_CounterMode_Down ((uint16_t)0x0010)
|
||||
#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020)
|
||||
#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040)
|
||||
#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060)
|
||||
#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) || \
|
||||
((MODE) == TIM_CounterMode_Down) || \
|
||||
((MODE) == TIM_CounterMode_CenterAligned1) || \
|
||||
((MODE) == TIM_CounterMode_CenterAligned2) || \
|
||||
((MODE) == TIM_CounterMode_CenterAligned3))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_Output_Compare_Polarity
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define TIM_OCPolarity_High ((uint16_t)0x0000)
|
||||
#define TIM_OCPolarity_Low ((uint16_t)0x0002)
|
||||
#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \
|
||||
((POLARITY) == TIM_OCPolarity_Low))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup TIM_Output_Compare_state
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define TIM_OutputState_Disable ((uint16_t)0x0000)
|
||||
#define TIM_OutputState_Enable ((uint16_t)0x0001)
|
||||
#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \
|
||||
((STATE) == TIM_OutputState_Enable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup TIM_Capture_Compare_state
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define TIM_CCx_Enable ((uint16_t)0x0001)
|
||||
#define TIM_CCx_Disable ((uint16_t)0x0000)
|
||||
#define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \
|
||||
((CCX) == TIM_CCx_Disable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_Input_Capture_Polarity
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define TIM_ICPolarity_Rising ((uint16_t)0x0000)
|
||||
#define TIM_ICPolarity_Falling ((uint16_t)0x0002)
|
||||
#define TIM_ICPolarity_BothEdge ((uint16_t)0x000A)
|
||||
#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \
|
||||
((POLARITY) == TIM_ICPolarity_Falling)|| \
|
||||
((POLARITY) == TIM_ICPolarity_BothEdge))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_Input_Capture_Selection
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be
|
||||
connected to IC1, IC2, IC3 or IC4, respectively */
|
||||
#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /*!< TIM Input 1, 2, 3 or 4 is selected to be
|
||||
connected to IC2, IC1, IC4 or IC3, respectively. */
|
||||
#define TIM_ICSelection_TRC ((uint16_t)0x0003) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */
|
||||
#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \
|
||||
((SELECTION) == TIM_ICSelection_IndirectTI) || \
|
||||
((SELECTION) == TIM_ICSelection_TRC))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_Input_Capture_Prescaler
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input. */
|
||||
#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /*!< Capture performed once every 2 events. */
|
||||
#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /*!< Capture performed once every 4 events. */
|
||||
#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /*!< Capture performed once every 8 events. */
|
||||
#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \
|
||||
((PRESCALER) == TIM_ICPSC_DIV2) || \
|
||||
((PRESCALER) == TIM_ICPSC_DIV4) || \
|
||||
((PRESCALER) == TIM_ICPSC_DIV8))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_interrupt_sources
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define TIM_IT_Update ((uint16_t)0x0001)
|
||||
#define TIM_IT_CC1 ((uint16_t)0x0002)
|
||||
#define TIM_IT_CC2 ((uint16_t)0x0004)
|
||||
#define TIM_IT_CC3 ((uint16_t)0x0008)
|
||||
#define TIM_IT_CC4 ((uint16_t)0x0010)
|
||||
#define TIM_IT_Trigger ((uint16_t)0x0040)
|
||||
#define IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFFA0) == 0x0000) && ((IT) != 0x0000))
|
||||
|
||||
#define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \
|
||||
((IT) == TIM_IT_CC1) || \
|
||||
((IT) == TIM_IT_CC2) || \
|
||||
((IT) == TIM_IT_CC3) || \
|
||||
((IT) == TIM_IT_CC4) || \
|
||||
((IT) == TIM_IT_Trigger))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_DMA_Base_address
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define TIM_DMABase_CR1 ((uint16_t)0x0000)
|
||||
#define TIM_DMABase_CR2 ((uint16_t)0x0001)
|
||||
#define TIM_DMABase_SMCR ((uint16_t)0x0002)
|
||||
#define TIM_DMABase_DIER ((uint16_t)0x0003)
|
||||
#define TIM_DMABase_SR ((uint16_t)0x0004)
|
||||
#define TIM_DMABase_EGR ((uint16_t)0x0005)
|
||||
#define TIM_DMABase_CCMR1 ((uint16_t)0x0006)
|
||||
#define TIM_DMABase_CCMR2 ((uint16_t)0x0007)
|
||||
#define TIM_DMABase_CCER ((uint16_t)0x0008)
|
||||
#define TIM_DMABase_CNT ((uint16_t)0x0009)
|
||||
#define TIM_DMABase_PSC ((uint16_t)0x000A)
|
||||
#define TIM_DMABase_ARR ((uint16_t)0x000B)
|
||||
#define TIM_DMABase_CCR1 ((uint16_t)0x000D)
|
||||
#define TIM_DMABase_CCR2 ((uint16_t)0x000E)
|
||||
#define TIM_DMABase_CCR3 ((uint16_t)0x000F)
|
||||
#define TIM_DMABase_CCR4 ((uint16_t)0x0010)
|
||||
#define TIM_DMABase_DCR ((uint16_t)0x0012)
|
||||
#define TIM_DMABase_OR ((uint16_t)0x0013)
|
||||
#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \
|
||||
((BASE) == TIM_DMABase_CR2) || \
|
||||
((BASE) == TIM_DMABase_SMCR) || \
|
||||
((BASE) == TIM_DMABase_DIER) || \
|
||||
((BASE) == TIM_DMABase_SR) || \
|
||||
((BASE) == TIM_DMABase_EGR) || \
|
||||
((BASE) == TIM_DMABase_CCMR1) || \
|
||||
((BASE) == TIM_DMABase_CCMR2) || \
|
||||
((BASE) == TIM_DMABase_CCER) || \
|
||||
((BASE) == TIM_DMABase_CNT) || \
|
||||
((BASE) == TIM_DMABase_PSC) || \
|
||||
((BASE) == TIM_DMABase_ARR) || \
|
||||
((BASE) == TIM_DMABase_CCR1) || \
|
||||
((BASE) == TIM_DMABase_CCR2) || \
|
||||
((BASE) == TIM_DMABase_CCR3) || \
|
||||
((BASE) == TIM_DMABase_CCR4) || \
|
||||
((BASE) == TIM_DMABase_DCR) || \
|
||||
((BASE) == TIM_DMABase_OR))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_DMA_Burst_Length
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000)
|
||||
#define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100)
|
||||
#define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200)
|
||||
#define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300)
|
||||
#define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400)
|
||||
#define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500)
|
||||
#define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600)
|
||||
#define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700)
|
||||
#define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800)
|
||||
#define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900)
|
||||
#define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00)
|
||||
#define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00)
|
||||
#define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00)
|
||||
#define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00)
|
||||
#define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00)
|
||||
#define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00)
|
||||
#define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000)
|
||||
#define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100)
|
||||
#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) || \
|
||||
((LENGTH) == TIM_DMABurstLength_2Transfers) || \
|
||||
((LENGTH) == TIM_DMABurstLength_3Transfers) || \
|
||||
((LENGTH) == TIM_DMABurstLength_4Transfers) || \
|
||||
((LENGTH) == TIM_DMABurstLength_5Transfers) || \
|
||||
((LENGTH) == TIM_DMABurstLength_6Transfers) || \
|
||||
((LENGTH) == TIM_DMABurstLength_7Transfers) || \
|
||||
((LENGTH) == TIM_DMABurstLength_8Transfers) || \
|
||||
((LENGTH) == TIM_DMABurstLength_9Transfers) || \
|
||||
((LENGTH) == TIM_DMABurstLength_10Transfers) || \
|
||||
((LENGTH) == TIM_DMABurstLength_11Transfers) || \
|
||||
((LENGTH) == TIM_DMABurstLength_12Transfers) || \
|
||||
((LENGTH) == TIM_DMABurstLength_13Transfers) || \
|
||||
((LENGTH) == TIM_DMABurstLength_14Transfers) || \
|
||||
((LENGTH) == TIM_DMABurstLength_15Transfers) || \
|
||||
((LENGTH) == TIM_DMABurstLength_16Transfers) || \
|
||||
((LENGTH) == TIM_DMABurstLength_17Transfers) || \
|
||||
((LENGTH) == TIM_DMABurstLength_18Transfers))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_DMA_sources
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define TIM_DMA_Update ((uint16_t)0x0100)
|
||||
#define TIM_DMA_CC1 ((uint16_t)0x0200)
|
||||
#define TIM_DMA_CC2 ((uint16_t)0x0400)
|
||||
#define TIM_DMA_CC3 ((uint16_t)0x0800)
|
||||
#define TIM_DMA_CC4 ((uint16_t)0x1000)
|
||||
#define TIM_DMA_Trigger ((uint16_t)0x4000)
|
||||
#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xA0FF) == 0x0000) && ((SOURCE) != 0x0000))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_External_Trigger_Prescaler
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000)
|
||||
#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000)
|
||||
#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000)
|
||||
#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000)
|
||||
#define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \
|
||||
((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \
|
||||
((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \
|
||||
((PRESCALER) == TIM_ExtTRGPSC_DIV8))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_Internal_Trigger_Selection
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define TIM_TS_ITR0 ((uint16_t)0x0000)
|
||||
#define TIM_TS_ITR1 ((uint16_t)0x0010)
|
||||
#define TIM_TS_ITR2 ((uint16_t)0x0020)
|
||||
#define TIM_TS_ITR3 ((uint16_t)0x0030)
|
||||
#define TIM_TS_TI1F_ED ((uint16_t)0x0040)
|
||||
#define TIM_TS_TI1FP1 ((uint16_t)0x0050)
|
||||
#define TIM_TS_TI2FP2 ((uint16_t)0x0060)
|
||||
#define TIM_TS_ETRF ((uint16_t)0x0070)
|
||||
#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
|
||||
((SELECTION) == TIM_TS_ITR1) || \
|
||||
((SELECTION) == TIM_TS_ITR2) || \
|
||||
((SELECTION) == TIM_TS_ITR3) || \
|
||||
((SELECTION) == TIM_TS_TI1F_ED) || \
|
||||
((SELECTION) == TIM_TS_TI1FP1) || \
|
||||
((SELECTION) == TIM_TS_TI2FP2) || \
|
||||
((SELECTION) == TIM_TS_ETRF))
|
||||
#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
|
||||
((SELECTION) == TIM_TS_ITR1) || \
|
||||
((SELECTION) == TIM_TS_ITR2) || \
|
||||
((SELECTION) == TIM_TS_ITR3))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_TIx_External_Clock_Source
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050)
|
||||
#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060)
|
||||
#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_External_Trigger_Polarity
|
||||
* @{
|
||||
*/
|
||||
#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000)
|
||||
#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000)
|
||||
#define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \
|
||||
((POLARITY) == TIM_ExtTRGPolarity_NonInverted))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_Prescaler_Reload_Mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define TIM_PSCReloadMode_Update ((uint16_t)0x0000)
|
||||
#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001)
|
||||
#define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \
|
||||
((RELOAD) == TIM_PSCReloadMode_Immediate))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_Forced_Action
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define TIM_ForcedAction_Active ((uint16_t)0x0050)
|
||||
#define TIM_ForcedAction_InActive ((uint16_t)0x0040)
|
||||
#define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \
|
||||
((ACTION) == TIM_ForcedAction_InActive))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_Encoder_Mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define TIM_EncoderMode_TI1 ((uint16_t)0x0001)
|
||||
#define TIM_EncoderMode_TI2 ((uint16_t)0x0002)
|
||||
#define TIM_EncoderMode_TI12 ((uint16_t)0x0003)
|
||||
#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \
|
||||
((MODE) == TIM_EncoderMode_TI2) || \
|
||||
((MODE) == TIM_EncoderMode_TI12))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/** @defgroup TIM_Event_Source
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define TIM_EventSource_Update ((uint16_t)0x0001)
|
||||
#define TIM_EventSource_CC1 ((uint16_t)0x0002)
|
||||
#define TIM_EventSource_CC2 ((uint16_t)0x0004)
|
||||
#define TIM_EventSource_CC3 ((uint16_t)0x0008)
|
||||
#define TIM_EventSource_CC4 ((uint16_t)0x0010)
|
||||
#define TIM_EventSource_Trigger ((uint16_t)0x0040)
|
||||
#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFFA0) == 0x0000) && ((SOURCE) != 0x0000))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_Update_Source
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define TIM_UpdateSource_Global ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow
|
||||
or the setting of UG bit, or an update generation
|
||||
through the slave mode controller. */
|
||||
#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /*!< Source of update is counter overflow/underflow. */
|
||||
#define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \
|
||||
((SOURCE) == TIM_UpdateSource_Regular))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_Output_Compare_Preload_State
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define TIM_OCPreload_Enable ((uint16_t)0x0008)
|
||||
#define TIM_OCPreload_Disable ((uint16_t)0x0000)
|
||||
#define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \
|
||||
((STATE) == TIM_OCPreload_Disable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_Output_Compare_Fast_State
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define TIM_OCFast_Enable ((uint16_t)0x0004)
|
||||
#define TIM_OCFast_Disable ((uint16_t)0x0000)
|
||||
#define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \
|
||||
((STATE) == TIM_OCFast_Disable))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_Output_Compare_Clear_State
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define TIM_OCClear_Enable ((uint16_t)0x0080)
|
||||
#define TIM_OCClear_Disable ((uint16_t)0x0000)
|
||||
#define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \
|
||||
((STATE) == TIM_OCClear_Disable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_Trigger_Output_Source
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define TIM_TRGOSource_Reset ((uint16_t)0x0000)
|
||||
#define TIM_TRGOSource_Enable ((uint16_t)0x0010)
|
||||
#define TIM_TRGOSource_Update ((uint16_t)0x0020)
|
||||
#define TIM_TRGOSource_OC1 ((uint16_t)0x0030)
|
||||
#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040)
|
||||
#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050)
|
||||
#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060)
|
||||
#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070)
|
||||
#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \
|
||||
((SOURCE) == TIM_TRGOSource_Enable) || \
|
||||
((SOURCE) == TIM_TRGOSource_Update) || \
|
||||
((SOURCE) == TIM_TRGOSource_OC1) || \
|
||||
((SOURCE) == TIM_TRGOSource_OC1Ref) || \
|
||||
((SOURCE) == TIM_TRGOSource_OC2Ref) || \
|
||||
((SOURCE) == TIM_TRGOSource_OC3Ref) || \
|
||||
((SOURCE) == TIM_TRGOSource_OC4Ref))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_Slave_Mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define TIM_SlaveMode_Reset ((uint16_t)0x0004)
|
||||
#define TIM_SlaveMode_Gated ((uint16_t)0x0005)
|
||||
#define TIM_SlaveMode_Trigger ((uint16_t)0x0006)
|
||||
#define TIM_SlaveMode_External1 ((uint16_t)0x0007)
|
||||
#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \
|
||||
((MODE) == TIM_SlaveMode_Gated) || \
|
||||
((MODE) == TIM_SlaveMode_Trigger) || \
|
||||
((MODE) == TIM_SlaveMode_External1))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_Master_Slave_Mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080)
|
||||
#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000)
|
||||
#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \
|
||||
((STATE) == TIM_MasterSlaveMode_Disable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_Flags
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define TIM_FLAG_Update ((uint16_t)0x0001)
|
||||
#define TIM_FLAG_CC1 ((uint16_t)0x0002)
|
||||
#define TIM_FLAG_CC2 ((uint16_t)0x0004)
|
||||
#define TIM_FLAG_CC3 ((uint16_t)0x0008)
|
||||
#define TIM_FLAG_CC4 ((uint16_t)0x0010)
|
||||
#define TIM_FLAG_Trigger ((uint16_t)0x0040)
|
||||
#define TIM_FLAG_CC1OF ((uint16_t)0x0200)
|
||||
#define TIM_FLAG_CC2OF ((uint16_t)0x0400)
|
||||
#define TIM_FLAG_CC3OF ((uint16_t)0x0800)
|
||||
#define TIM_FLAG_CC4OF ((uint16_t)0x1000)
|
||||
#define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || \
|
||||
((FLAG) == TIM_FLAG_CC1) || \
|
||||
((FLAG) == TIM_FLAG_CC2) || \
|
||||
((FLAG) == TIM_FLAG_CC3) || \
|
||||
((FLAG) == TIM_FLAG_CC4) || \
|
||||
((FLAG) == TIM_FLAG_Trigger) || \
|
||||
((FLAG) == TIM_FLAG_CC1OF) || \
|
||||
((FLAG) == TIM_FLAG_CC2OF) || \
|
||||
((FLAG) == TIM_FLAG_CC3OF) || \
|
||||
((FLAG) == TIM_FLAG_CC4OF))
|
||||
#define IS_TIM_CLEAR_FLAG(TIM_FLAG) ((((TIM_FLAG) & (uint16_t)0xE1A0) == 0x0000) && ((TIM_FLAG) != 0x0000))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_Input_Capture_Filer_Value
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_External_Trigger_Filter
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_OCReferenceClear
|
||||
* @{
|
||||
*/
|
||||
#define TIM_OCReferenceClear_ETRF ((uint16_t)0x0008)
|
||||
#define TIM_OCReferenceClear_OCREFCLR ((uint16_t)0x0000)
|
||||
#define TIM_OCREFERENCECECLEAR_SOURCE(SOURCE) (((SOURCE) == TIM_OCReferenceClear_ETRF) || \
|
||||
((SOURCE) == TIM_OCReferenceClear_OCREFCLR))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_Remap
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define TIM2_TIM10_OC ((uint32_t)0xFFFE0000)
|
||||
#define TIM2_TIM5_TRGO ((uint32_t)0xFFFE0001)
|
||||
|
||||
#define TIM3_TIM11_OC ((uint32_t)0xFFFE0000)
|
||||
#define TIM3_TIM5_TRGO ((uint32_t)0xFFFE0001)
|
||||
|
||||
#define TIM9_GPIO ((uint32_t)0xFFFC0000)
|
||||
#define TIM9_LSE ((uint32_t)0xFFFC0001)
|
||||
|
||||
#define TIM9_TIM3_TRGO ((uint32_t)0xFFFB0000)
|
||||
#define TIM9_TS_IO ((uint32_t)0xFFFB0004)
|
||||
|
||||
#define TIM10_GPIO ((uint32_t)0xFFF40000)
|
||||
#define TIM10_LSI ((uint32_t)0xFFF40001)
|
||||
#define TIM10_LSE ((uint32_t)0xFFF40002)
|
||||
#define TIM10_RTC ((uint32_t)0xFFF40003)
|
||||
#define TIM10_RI ((uint32_t)0xFFF40008)
|
||||
|
||||
#define TIM10_ETR_LSE ((uint32_t)0xFFFB0000)
|
||||
#define TIM10_ETR_TIM9_TRGO ((uint32_t)0xFFFB0004)
|
||||
|
||||
#define TIM11_GPIO ((uint32_t)0xFFF40000)
|
||||
#define TIM11_MSI ((uint32_t)0xFFF40001)
|
||||
#define TIM11_HSE_RTC ((uint32_t)0xFFF40002)
|
||||
#define TIM11_RI ((uint32_t)0xFFF40008)
|
||||
|
||||
#define TIM11_ETR_LSE ((uint32_t)0xFFFB0000)
|
||||
#define TIM11_ETR_TIM9_TRGO ((uint32_t)0xFFFB0004)
|
||||
|
||||
#define IS_TIM_REMAP(TIM_REMAP) (((TIM_REMAP) == TIM2_TIM10_OC)|| \
|
||||
((TIM_REMAP) == TIM2_TIM5_TRGO)|| \
|
||||
((TIM_REMAP) == TIM3_TIM11_OC)|| \
|
||||
((TIM_REMAP) == TIM3_TIM5_TRGO)|| \
|
||||
((TIM_REMAP) == TIM9_GPIO)|| \
|
||||
((TIM_REMAP) == TIM9_LSE)|| \
|
||||
((TIM_REMAP) == TIM9_TIM3_TRGO)|| \
|
||||
((TIM_REMAP) == TIM9_TS_IO)|| \
|
||||
((TIM_REMAP) == TIM10_GPIO)|| \
|
||||
((TIM_REMAP) == TIM10_LSI)|| \
|
||||
((TIM_REMAP) == TIM10_LSE)|| \
|
||||
((TIM_REMAP) == TIM10_RTC)|| \
|
||||
((TIM_REMAP) == TIM10_RI)|| \
|
||||
((TIM_REMAP) == TIM10_ETR_LSE)|| \
|
||||
((TIM_REMAP) == TIM10_ETR_TIM9_TRGO)|| \
|
||||
((TIM_REMAP) == TIM11_GPIO)|| \
|
||||
((TIM_REMAP) == TIM11_MSI)|| \
|
||||
((TIM_REMAP) == TIM11_HSE_RTC)|| \
|
||||
((TIM_REMAP) == TIM11_RI)|| \
|
||||
((TIM_REMAP) == TIM11_ETR_LSE)|| \
|
||||
((TIM_REMAP) == TIM11_ETR_TIM9_TRGO))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_Legacy
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer
|
||||
#define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers
|
||||
#define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers
|
||||
#define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers
|
||||
#define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers
|
||||
#define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers
|
||||
#define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers
|
||||
#define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers
|
||||
#define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers
|
||||
#define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers
|
||||
#define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers
|
||||
#define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers
|
||||
#define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers
|
||||
#define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers
|
||||
#define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers
|
||||
#define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers
|
||||
#define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers
|
||||
#define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
|
||||
/* TimeBase management ********************************************************/
|
||||
void TIM_DeInit(TIM_TypeDef* TIMx);
|
||||
void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
|
||||
void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
|
||||
void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode);
|
||||
void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode);
|
||||
void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter);
|
||||
void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload);
|
||||
uint32_t TIM_GetCounter(TIM_TypeDef* TIMx);
|
||||
uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx);
|
||||
void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
|
||||
void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource);
|
||||
void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
|
||||
void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode);
|
||||
void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD);
|
||||
void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState);
|
||||
|
||||
/* Output Compare management **************************************************/
|
||||
void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
|
||||
void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
|
||||
void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
|
||||
void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
|
||||
void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct);
|
||||
void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode);
|
||||
void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1);
|
||||
void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2);
|
||||
void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3);
|
||||
void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4);
|
||||
void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
|
||||
void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
|
||||
void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
|
||||
void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
|
||||
void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
|
||||
void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
|
||||
void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
|
||||
void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
|
||||
void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
|
||||
void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
|
||||
void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
|
||||
void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
|
||||
void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
|
||||
void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
|
||||
void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
|
||||
void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
|
||||
void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
|
||||
void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
|
||||
void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
|
||||
void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
|
||||
void TIM_SelectOCREFClear(TIM_TypeDef* TIMx, uint16_t TIM_OCReferenceClear);
|
||||
void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx);
|
||||
|
||||
/* Input Capture management ***************************************************/
|
||||
void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
|
||||
void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct);
|
||||
void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
|
||||
uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx);
|
||||
uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx);
|
||||
uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx);
|
||||
uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx);
|
||||
void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
|
||||
void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
|
||||
void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
|
||||
void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
|
||||
|
||||
/* Interrupts, DMA and flags management ***************************************/
|
||||
void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState);
|
||||
void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource);
|
||||
FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);
|
||||
void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);
|
||||
ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT);
|
||||
void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT);
|
||||
void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength);
|
||||
void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState);
|
||||
void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState);
|
||||
|
||||
/* Clocks management **********************************************************/
|
||||
void TIM_InternalClockConfig(TIM_TypeDef* TIMx);
|
||||
void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
|
||||
void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,
|
||||
uint16_t TIM_ICPolarity, uint16_t ICFilter);
|
||||
void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
|
||||
uint16_t ExtTRGFilter);
|
||||
void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
|
||||
uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter);
|
||||
|
||||
|
||||
/* Synchronization management *************************************************/
|
||||
void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
|
||||
void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource);
|
||||
void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode);
|
||||
void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode);
|
||||
void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
|
||||
uint16_t ExtTRGFilter);
|
||||
|
||||
/* Specific interface management **********************************************/
|
||||
void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,
|
||||
uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity);
|
||||
void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState);
|
||||
|
||||
/* Specific remapping management **********************************************/
|
||||
void TIM_RemapConfig(TIM_TypeDef* TIMx, uint32_t TIM_Remap);
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__STM32L1xx_TIM_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,427 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32l1xx_usart.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.1
|
||||
* @date 05-March-2012
|
||||
* @brief This file contains all the functions prototypes for the USART
|
||||
* firmware library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32L1xx_USART_H
|
||||
#define __STM32L1xx_USART_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32l1xx.h"
|
||||
|
||||
/** @addtogroup STM32L1xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup USART
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief USART Init Structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t USART_BaudRate; /*!< This member configures the USART communication baud rate.
|
||||
The baud rate is computed using the following formula:
|
||||
- IntegerDivider = ((PCLKx) / (8 * (OVR8+1) * (USART_InitStruct->USART_BaudRate)))
|
||||
- FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 8 * (OVR8+1)) + 0.5
|
||||
Where OVR8 is the "oversampling by 8 mode" configuration bit in the CR1 register. */
|
||||
|
||||
uint16_t USART_WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
|
||||
This parameter can be a value of @ref USART_Word_Length */
|
||||
|
||||
uint16_t USART_StopBits; /*!< Specifies the number of stop bits transmitted.
|
||||
This parameter can be a value of @ref USART_Stop_Bits */
|
||||
|
||||
uint16_t USART_Parity; /*!< Specifies the parity mode.
|
||||
This parameter can be a value of @ref USART_Parity
|
||||
@note When parity is enabled, the computed parity is inserted
|
||||
at the MSB position of the transmitted data (9th bit when
|
||||
the word length is set to 9 data bits; 8th bit when the
|
||||
word length is set to 8 data bits). */
|
||||
|
||||
uint16_t USART_Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
|
||||
This parameter can be a value of @ref USART_Mode */
|
||||
|
||||
uint16_t USART_HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled
|
||||
or disabled.
|
||||
This parameter can be a value of @ref USART_Hardware_Flow_Control */
|
||||
} USART_InitTypeDef;
|
||||
|
||||
/**
|
||||
* @brief USART Clock Init Structure definition
|
||||
*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
|
||||
uint16_t USART_Clock; /*!< Specifies whether the USART clock is enabled or disabled.
|
||||
This parameter can be a value of @ref USART_Clock */
|
||||
|
||||
uint16_t USART_CPOL; /*!< Specifies the steady state of the serial clock.
|
||||
This parameter can be a value of @ref USART_Clock_Polarity */
|
||||
|
||||
uint16_t USART_CPHA; /*!< Specifies the clock transition on which the bit capture is made.
|
||||
This parameter can be a value of @ref USART_Clock_Phase */
|
||||
|
||||
uint16_t USART_LastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted
|
||||
data bit (MSB) has to be output on the SCLK pin in synchronous mode.
|
||||
This parameter can be a value of @ref USART_Last_Bit */
|
||||
} USART_ClockInitTypeDef;
|
||||
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup USART_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define IS_USART_ALL_PERIPH(PERIPH) (((PERIPH) == USART1) || \
|
||||
((PERIPH) == USART2) || \
|
||||
((PERIPH) == USART3) || \
|
||||
((PERIPH) == UART4) || \
|
||||
((PERIPH) == UART5))
|
||||
|
||||
#define IS_USART_123_PERIPH(PERIPH) (((PERIPH) == USART1) || \
|
||||
((PERIPH) == USART2) || \
|
||||
((PERIPH) == USART3))
|
||||
|
||||
/** @defgroup USART_Word_Length
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_WordLength_8b ((uint16_t)0x0000)
|
||||
#define USART_WordLength_9b ((uint16_t)0x1000)
|
||||
|
||||
#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || \
|
||||
((LENGTH) == USART_WordLength_9b))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Stop_Bits
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_StopBits_1 ((uint16_t)0x0000)
|
||||
#define USART_StopBits_0_5 ((uint16_t)0x1000)
|
||||
#define USART_StopBits_2 ((uint16_t)0x2000)
|
||||
#define USART_StopBits_1_5 ((uint16_t)0x3000)
|
||||
#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || \
|
||||
((STOPBITS) == USART_StopBits_0_5) || \
|
||||
((STOPBITS) == USART_StopBits_2) || \
|
||||
((STOPBITS) == USART_StopBits_1_5))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Parity
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_Parity_No ((uint16_t)0x0000)
|
||||
#define USART_Parity_Even ((uint16_t)0x0400)
|
||||
#define USART_Parity_Odd ((uint16_t)0x0600)
|
||||
#define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || \
|
||||
((PARITY) == USART_Parity_Even) || \
|
||||
((PARITY) == USART_Parity_Odd))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Mode
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_Mode_Rx ((uint16_t)0x0004)
|
||||
#define USART_Mode_Tx ((uint16_t)0x0008)
|
||||
#define IS_USART_MODE(MODE) ((((MODE) & (uint16_t)0xFFF3) == 0x00) && ((MODE) != (uint16_t)0x00))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Hardware_Flow_Control
|
||||
* @{
|
||||
*/
|
||||
#define USART_HardwareFlowControl_None ((uint16_t)0x0000)
|
||||
#define USART_HardwareFlowControl_RTS ((uint16_t)0x0100)
|
||||
#define USART_HardwareFlowControl_CTS ((uint16_t)0x0200)
|
||||
#define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300)
|
||||
#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\
|
||||
(((CONTROL) == USART_HardwareFlowControl_None) || \
|
||||
((CONTROL) == USART_HardwareFlowControl_RTS) || \
|
||||
((CONTROL) == USART_HardwareFlowControl_CTS) || \
|
||||
((CONTROL) == USART_HardwareFlowControl_RTS_CTS))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Clock
|
||||
* @{
|
||||
*/
|
||||
#define USART_Clock_Disable ((uint16_t)0x0000)
|
||||
#define USART_Clock_Enable ((uint16_t)0x0800)
|
||||
#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || \
|
||||
((CLOCK) == USART_Clock_Enable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Clock_Polarity
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_CPOL_Low ((uint16_t)0x0000)
|
||||
#define USART_CPOL_High ((uint16_t)0x0400)
|
||||
#define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Clock_Phase
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_CPHA_1Edge ((uint16_t)0x0000)
|
||||
#define USART_CPHA_2Edge ((uint16_t)0x0200)
|
||||
#define IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Last_Bit
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_LastBit_Disable ((uint16_t)0x0000)
|
||||
#define USART_LastBit_Enable ((uint16_t)0x0100)
|
||||
#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || \
|
||||
((LASTBIT) == USART_LastBit_Enable))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Interrupt_definition
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_IT_PE ((uint16_t)0x0028)
|
||||
#define USART_IT_TXE ((uint16_t)0x0727)
|
||||
#define USART_IT_TC ((uint16_t)0x0626)
|
||||
#define USART_IT_RXNE ((uint16_t)0x0525)
|
||||
#define USART_IT_IDLE ((uint16_t)0x0424)
|
||||
#define USART_IT_LBD ((uint16_t)0x0846)
|
||||
#define USART_IT_ORE_RX ((uint16_t)0x0325) /* In case interrupt is generated if the RXNEIE bit is set */
|
||||
#define USART_IT_CTS ((uint16_t)0x096A)
|
||||
#define USART_IT_ERR ((uint16_t)0x0060)
|
||||
#define USART_IT_ORE_ER ((uint16_t)0x0360) /* In case interrupt is generated if the EIE bit is set */
|
||||
#define USART_IT_NE ((uint16_t)0x0260)
|
||||
#define USART_IT_FE ((uint16_t)0x0160)
|
||||
|
||||
/** @defgroup USART_Legacy
|
||||
* @{
|
||||
*/
|
||||
#define USART_IT_ORE USART_IT_ORE_ER
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
|
||||
((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
|
||||
((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
|
||||
((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR))
|
||||
#define IS_USART_GET_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
|
||||
((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
|
||||
((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
|
||||
((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE_RX) || \
|
||||
((IT) == USART_IT_ORE_ER) || ((IT) == USART_IT_NE) || \
|
||||
((IT) == USART_IT_FE))
|
||||
#define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
|
||||
((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_DMA_Requests
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_DMAReq_Tx ((uint16_t)0x0080)
|
||||
#define USART_DMAReq_Rx ((uint16_t)0x0040)
|
||||
#define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFF3F) == 0x00) && ((DMAREQ) != (uint16_t)0x00))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_WakeUp_methods
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_WakeUp_IdleLine ((uint16_t)0x0000)
|
||||
#define USART_WakeUp_AddressMark ((uint16_t)0x0800)
|
||||
#define IS_USART_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) || \
|
||||
((WAKEUP) == USART_WakeUp_AddressMark))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_LIN_Break_Detection_Length
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_LINBreakDetectLength_10b ((uint16_t)0x0000)
|
||||
#define USART_LINBreakDetectLength_11b ((uint16_t)0x0020)
|
||||
#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \
|
||||
(((LENGTH) == USART_LINBreakDetectLength_10b) || \
|
||||
((LENGTH) == USART_LINBreakDetectLength_11b))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_IrDA_Low_Power
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_IrDAMode_LowPower ((uint16_t)0x0004)
|
||||
#define USART_IrDAMode_Normal ((uint16_t)0x0000)
|
||||
#define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IrDAMode_LowPower) || \
|
||||
((MODE) == USART_IrDAMode_Normal))
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup USART_Flags
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define USART_FLAG_CTS ((uint16_t)0x0200)
|
||||
#define USART_FLAG_LBD ((uint16_t)0x0100)
|
||||
#define USART_FLAG_TXE ((uint16_t)0x0080)
|
||||
#define USART_FLAG_TC ((uint16_t)0x0040)
|
||||
#define USART_FLAG_RXNE ((uint16_t)0x0020)
|
||||
#define USART_FLAG_IDLE ((uint16_t)0x0010)
|
||||
#define USART_FLAG_ORE ((uint16_t)0x0008)
|
||||
#define USART_FLAG_NE ((uint16_t)0x0004)
|
||||
#define USART_FLAG_FE ((uint16_t)0x0002)
|
||||
#define USART_FLAG_PE ((uint16_t)0x0001)
|
||||
#define IS_USART_FLAG(FLAG) (((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || \
|
||||
((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || \
|
||||
((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || \
|
||||
((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || \
|
||||
((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE))
|
||||
|
||||
#define IS_USART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFC9F) == 0x00) && ((FLAG) != (uint16_t)0x00))
|
||||
|
||||
#define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x003D0901))
|
||||
#define IS_USART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF)
|
||||
#define IS_USART_DATA(DATA) ((DATA) <= 0x1FF)
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
|
||||
/* Function used to set the USART configuration to the default reset state ***/
|
||||
void USART_DeInit(USART_TypeDef* USARTx);
|
||||
|
||||
/* Initialization and Configuration functions *********************************/
|
||||
void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct);
|
||||
void USART_StructInit(USART_InitTypeDef* USART_InitStruct);
|
||||
void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct);
|
||||
void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct);
|
||||
void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler);
|
||||
void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
|
||||
/* Data transfers functions ***************************************************/
|
||||
void USART_SendData(USART_TypeDef* USARTx, uint16_t Data);
|
||||
uint16_t USART_ReceiveData(USART_TypeDef* USARTx);
|
||||
|
||||
/* Multi-Processor Communication functions ************************************/
|
||||
void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address);
|
||||
void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp);
|
||||
void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
|
||||
/* LIN mode functions *********************************************************/
|
||||
void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength);
|
||||
void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
void USART_SendBreak(USART_TypeDef* USARTx);
|
||||
|
||||
/* Half-duplex mode function **************************************************/
|
||||
void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
|
||||
/* Smartcard mode functions ***************************************************/
|
||||
void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime);
|
||||
|
||||
/* IrDA mode functions ********************************************************/
|
||||
void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode);
|
||||
void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState);
|
||||
|
||||
/* DMA transfers management functions *****************************************/
|
||||
void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState);
|
||||
|
||||
/* Interrupts and flags management functions **********************************/
|
||||
void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState);
|
||||
FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG);
|
||||
void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG);
|
||||
ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT);
|
||||
void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32L1xx_USART_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,110 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32l1xx_wwdg.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.1
|
||||
* @date 05-March-2012
|
||||
* @brief This file contains all the functions prototypes for the WWDG
|
||||
* firmware library.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __STM32L1xx_WWDG_H
|
||||
#define __STM32L1xx_WWDG_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32l1xx.h"
|
||||
|
||||
/** @addtogroup STM32L1xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup WWDG
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported constants --------------------------------------------------------*/
|
||||
|
||||
/** @defgroup WWDG_Exported_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup WWDG_Prescaler
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define WWDG_Prescaler_1 ((uint32_t)0x00000000)
|
||||
#define WWDG_Prescaler_2 ((uint32_t)0x00000080)
|
||||
#define WWDG_Prescaler_4 ((uint32_t)0x00000100)
|
||||
#define WWDG_Prescaler_8 ((uint32_t)0x00000180)
|
||||
#define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_Prescaler_1) || \
|
||||
((PRESCALER) == WWDG_Prescaler_2) || \
|
||||
((PRESCALER) == WWDG_Prescaler_4) || \
|
||||
((PRESCALER) == WWDG_Prescaler_8))
|
||||
#define IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F)
|
||||
#define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F))
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Exported macro ------------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
/* Function used to set the WWDG configuration to the default reset state ****/
|
||||
void WWDG_DeInit(void);
|
||||
|
||||
/* Prescaler, Refresh window and Counter configuration functions **************/
|
||||
void WWDG_SetPrescaler(uint32_t WWDG_Prescaler);
|
||||
void WWDG_SetWindowValue(uint8_t WindowValue);
|
||||
void WWDG_EnableIT(void);
|
||||
void WWDG_SetCounter(uint8_t Counter);
|
||||
|
||||
/* WWDG activation functions **************************************************/
|
||||
void WWDG_Enable(uint8_t Counter);
|
||||
|
||||
/* Interrupts and flags management functions **********************************/
|
||||
FlagStatus WWDG_GetFlagStatus(void);
|
||||
void WWDG_ClearFlag(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __STM32L1xx_WWDG_H */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,251 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file misc.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.1
|
||||
* @date 05-March-2012
|
||||
* @brief This file provides all the miscellaneous firmware functions (add-on
|
||||
* to CMSIS functions).
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "misc.h"
|
||||
|
||||
/** @addtogroup STM32L1xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup MISC
|
||||
* @brief MISC driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000)
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup MISC_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
/**
|
||||
*
|
||||
@verbatim
|
||||
*******************************************************************************
|
||||
##### Interrupts configuration functions #####
|
||||
*******************************************************************************
|
||||
[..] This section provide functions allowing to configure the NVIC interrupts
|
||||
(IRQ).The Cortex-M3 exceptions are managed by CMSIS functions.
|
||||
(#) Configure the NVIC Priority Grouping using NVIC_PriorityGroupConfig()
|
||||
function according to the following table.
|
||||
The table below gives the allowed values of the preemption priority
|
||||
and subpriority according to the Priority Grouping configuration
|
||||
performed by NVIC_PriorityGroupConfig function.
|
||||
============================================================================================================================
|
||||
NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description
|
||||
============================================================================================================================
|
||||
NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for preemption priority
|
||||
| | | 4 bits for subpriority
|
||||
----------------------------------------------------------------------------------------------------------------------------
|
||||
NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for preemption priority
|
||||
| | | 3 bits for subpriority
|
||||
----------------------------------------------------------------------------------------------------------------------------
|
||||
NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for preemption priority
|
||||
| | | 2 bits for subpriority
|
||||
----------------------------------------------------------------------------------------------------------------------------
|
||||
NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for preemption priority
|
||||
| | | 1 bits for subpriority
|
||||
----------------------------------------------------------------------------------------------------------------------------
|
||||
NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for preemption priority
|
||||
| | | 0 bits for subpriority
|
||||
============================================================================================================================
|
||||
|
||||
|
||||
(#) Enable and Configure the priority of the selected IRQ Channels.
|
||||
|
||||
-@- When the NVIC_PriorityGroup_0 is selected, it will no any nested interrupt,
|
||||
the IRQ priority will be managed only by subpriority.
|
||||
The sub-priority is only used to sort pending exception priorities,
|
||||
and does not affect active exceptions.
|
||||
-@- Lower priority values gives higher priority.
|
||||
-@- Priority Order:
|
||||
(#@) Lowest Preemption priority.
|
||||
(#@) Lowest Subpriority.
|
||||
(#@) Lowest hardware priority (IRQn position).
|
||||
|
||||
@endverbatim
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Configures the priority grouping: preemption priority and subpriority.
|
||||
* @param NVIC_PriorityGroup: specifies the priority grouping bits length.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg NVIC_PriorityGroup_0: 0 bits for preemption priority
|
||||
* 4 bits for subpriority.
|
||||
* @note When NVIC_PriorityGroup_0 is selected, it will no be any nested
|
||||
* interrupt. This interrupts priority is managed only with subpriority.
|
||||
* @arg NVIC_PriorityGroup_1: 1 bits for preemption priority.
|
||||
* 3 bits for subpriority.
|
||||
* @arg NVIC_PriorityGroup_2: 2 bits for preemption priority.
|
||||
* 2 bits for subpriority.
|
||||
* @arg NVIC_PriorityGroup_3: 3 bits for preemption priority.
|
||||
* 1 bits for subpriority.
|
||||
* @arg NVIC_PriorityGroup_4: 4 bits for preemption priority.
|
||||
* 0 bits for subpriority.
|
||||
* @retval None
|
||||
*/
|
||||
void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup));
|
||||
|
||||
/* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */
|
||||
SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the NVIC peripheral according to the specified
|
||||
* parameters in the NVIC_InitStruct.
|
||||
* @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
|
||||
* function should be called before.
|
||||
* @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains
|
||||
* the configuration information for the specified NVIC peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct)
|
||||
{
|
||||
uint8_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd));
|
||||
assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority));
|
||||
assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority));
|
||||
|
||||
if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)
|
||||
{
|
||||
/* Compute the Corresponding IRQ Priority --------------------------------*/
|
||||
tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08;
|
||||
tmppre = (0x4 - tmppriority);
|
||||
tmpsub = tmpsub >> tmppriority;
|
||||
|
||||
tmppriority = (uint32_t)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre;
|
||||
tmppriority |= (uint8_t)(NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub);
|
||||
tmppriority = tmppriority << 0x04;
|
||||
|
||||
NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority;
|
||||
|
||||
/* Enable the Selected IRQ Channels --------------------------------------*/
|
||||
NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
|
||||
(uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the Selected IRQ Channels -------------------------------------*/
|
||||
NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
|
||||
(uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets the vector table location and Offset.
|
||||
* @param NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg NVIC_VectTab_RAM: Vector Table in internal SRAM.
|
||||
* @arg NVIC_VectTab_FLASH: Vector Table in internal FLASH.
|
||||
* @param Offset: Vector Table base offset field. This value must be a multiple of 0x200.
|
||||
* @retval None
|
||||
*/
|
||||
void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_NVIC_VECTTAB(NVIC_VectTab));
|
||||
assert_param(IS_NVIC_OFFSET(Offset));
|
||||
|
||||
SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Selects the condition for the system to enter low power mode.
|
||||
* @param LowPowerMode: Specifies the new mode for the system to enter low power mode.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg NVIC_LP_SEVONPEND: Low Power SEV on Pend.
|
||||
* @arg NVIC_LP_SLEEPDEEP: Low Power DEEPSLEEP request.
|
||||
* @arg NVIC_LP_SLEEPONEXIT: Low Power Sleep on Exit.
|
||||
* @param NewState: new state of LP condition.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_NVIC_LP(LowPowerMode));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
SCB->SCR |= LowPowerMode;
|
||||
}
|
||||
else
|
||||
{
|
||||
SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures the SysTick clock source.
|
||||
* @param SysTick_CLKSource: specifies the SysTick clock source.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source.
|
||||
* @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source.
|
||||
* @retval None
|
||||
*/
|
||||
void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource));
|
||||
|
||||
if (SysTick_CLKSource == SysTick_CLKSource_HCLK)
|
||||
{
|
||||
SysTick->CTRL |= SysTick_CLKSource_HCLK;
|
||||
}
|
||||
else
|
||||
{
|
||||
SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,599 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32l1xx_aes.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.1
|
||||
* @date 05-March-2012
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the AES peripheral:
|
||||
* + Configuration
|
||||
* + Read/Write operations
|
||||
* + DMA transfers management
|
||||
* + Interrupts and flags management
|
||||
*
|
||||
* @verbatim
|
||||
===============================================================================
|
||||
##### AES Peripheral features #####
|
||||
===============================================================================
|
||||
....[..]
|
||||
(#) The Advanced Encryption Standard hardware accelerator (AES) can be used
|
||||
to both encipher and decipher data using AES algorithm.
|
||||
(#) The AES supports 4 operation modes:
|
||||
(++) Encryption: It consumes 214 clock cycle when processing one 128-bit block
|
||||
(++) Decryption: It consumes 214 clock cycle when processing one 128-bit block
|
||||
(++) Key derivation for decryption: It consumes 80 clock cycle when processing one 128-bit block
|
||||
(++) Key Derivation and decryption: It consumes 288 clock cycle when processing one 128-bit blobk
|
||||
(#) Moreover 3 chaining modes are supported:
|
||||
(++) Electronic codebook (ECB): Each plain text is encrypted/decrypted separately
|
||||
(++) Cipher block chaining (CBC): Each block is XORed with the previous block
|
||||
(++) Counter mode (CTR): A 128-bit counter is encrypted and then XORed with the
|
||||
plain text to give the cipher text
|
||||
(#) The AES peripheral supports data swapping: 1-bit, 8-bit, 16-bit and 32-bit.
|
||||
(#) The AES peripheral supports write/read error handling with interrupt capability.
|
||||
(#) Automatic data flow control with support of direct memory access (DMA) using
|
||||
2 channels, one for incoming data (DMA2 Channel5), and one for outcoming data
|
||||
(DMA2 Channel3).
|
||||
|
||||
##### How to use this driver #####
|
||||
===============================================================================
|
||||
[..]
|
||||
(#) AES AHB clock must be enabled to get write access to AES registers
|
||||
using RCC_AHBPeriphClockCmd(RCC_AHBPeriph_AES, ENABLE).
|
||||
(#) Initialize the key using AES_KeyInit().
|
||||
(#) Configure the AES operation mode using AES_Init().
|
||||
(#) If required, enable interrupt source using AES_ITConfig() and
|
||||
enable the AES interrupt vector using NVIC_Init().
|
||||
(#) If required, when using the DMA mode.
|
||||
(##) Configure the DMA using DMA_Init().
|
||||
(##) Enable DMA requests using AES_DMAConfig().
|
||||
(#) Enable the AES peripheral using AES_Cmd().
|
||||
@endverbatim
|
||||
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32l1xx_aes.h"
|
||||
#include "stm32l1xx_rcc.h"
|
||||
|
||||
/** @addtogroup STM32L1xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup AES
|
||||
* @brief AES driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
#define CR_CLEAR_MASK ((uint32_t)0xFFFFFF81)
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup AES_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup AES_Group1 Initialization and configuration
|
||||
* @brief Initialization and configuration.
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Initialization and configuration #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Deinitializes AES peripheral registers to their default reset values.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void AES_DeInit(void)
|
||||
{
|
||||
/* Enable AES reset state */
|
||||
RCC_AHBPeriphResetCmd(RCC_AHBPeriph_AES, ENABLE);
|
||||
/* Release AES from reset state */
|
||||
RCC_AHBPeriphResetCmd(RCC_AHBPeriph_AES, DISABLE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the AES peripheral according to the specified parameters
|
||||
* in the AES_InitStruct:
|
||||
* - AES_Operation: specifies the operation mode (encryption, decryption...).
|
||||
* - AES_Chaining: specifies the chaining mode (ECB, CBC or CTR).
|
||||
* - AES_DataType: specifies the data swapping type: 32-bit, 16-bit, 8-bit or 1-bit.
|
||||
* @note If AES is already enabled, use AES_Cmd(DISABLE) before setting the new
|
||||
* configuration (When AES is enabled, setting configuration is forbidden).
|
||||
* @param AES_InitStruct: pointer to an AES_InitTypeDef structure that contains
|
||||
* the configuration information for AES peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
void AES_Init(AES_InitTypeDef* AES_InitStruct)
|
||||
{
|
||||
uint32_t tmpreg = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_AES_MODE(AES_InitStruct->AES_Operation));
|
||||
assert_param(IS_AES_CHAINING(AES_InitStruct->AES_Chaining));
|
||||
assert_param(IS_AES_DATATYPE(AES_InitStruct->AES_DataType));
|
||||
|
||||
/* Get AES CR register value */
|
||||
tmpreg = AES->CR;
|
||||
|
||||
/* Clear DATATYPE[1:0], MODE[1:0] and CHMOD[1:0] bits */
|
||||
tmpreg &= (uint32_t)CR_CLEAR_MASK;
|
||||
|
||||
tmpreg |= (AES_InitStruct->AES_Operation | AES_InitStruct->AES_Chaining | AES_InitStruct->AES_DataType);
|
||||
|
||||
AES->CR = (uint32_t) tmpreg;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the AES Keys according to the specified parameters in the AES_KeyInitStruct.
|
||||
* @param AES_KeyInitStruct: pointer to an AES_KeyInitTypeDef structure that
|
||||
* contains the configuration information for the specified AES Keys.
|
||||
* @note This function must be called while the AES is disabled.
|
||||
* @note In encryption, key derivation and key derivation + decryption modes,
|
||||
* AES_KeyInitStruct must contain the encryption key.
|
||||
* In decryption mode, AES_KeyInitStruct must contain the decryption key.
|
||||
* @retval None
|
||||
*/
|
||||
void AES_KeyInit(AES_KeyInitTypeDef* AES_KeyInitStruct)
|
||||
{
|
||||
AES->KEYR0 = AES_KeyInitStruct->AES_Key0;
|
||||
AES->KEYR1 = AES_KeyInitStruct->AES_Key1;
|
||||
AES->KEYR2 = AES_KeyInitStruct->AES_Key2;
|
||||
AES->KEYR3 = AES_KeyInitStruct->AES_Key3;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the AES Initialization Vector IV according to
|
||||
* the specified parameters in the AES_IVInitStruct.
|
||||
* @param AES_KeyInitStruct: pointer to an AES_IVInitTypeDef structure that
|
||||
* contains the configuration information for the specified AES IV.
|
||||
* @note When ECB chaining mode is selected, Initialization Vector IV has no
|
||||
* meaning.
|
||||
* When CTR chaining mode is selected, AES_IV0 contains the CTR value.
|
||||
* AES_IV1, AES_IV2 and AES_IV3 contains nonce value.
|
||||
* @retval None
|
||||
*/
|
||||
void AES_IVInit(AES_IVInitTypeDef* AES_IVInitStruct)
|
||||
{
|
||||
AES->IVR0 = AES_IVInitStruct->AES_IV0;
|
||||
AES->IVR1 = AES_IVInitStruct->AES_IV1;
|
||||
AES->IVR2 = AES_IVInitStruct->AES_IV2;
|
||||
AES->IVR3 = AES_IVInitStruct->AES_IV3;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable or disable the AES peripheral.
|
||||
* @param NewState: new state of the AES peripheral.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @note The key must be written while AES is disabled.
|
||||
* @retval None
|
||||
*/
|
||||
void AES_Cmd(FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameter */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the AES peripheral */
|
||||
AES->CR |= (uint32_t) AES_CR_EN; /**< AES Enable */
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the AES peripheral */
|
||||
AES->CR &= (uint32_t)(~AES_CR_EN); /**< AES Disable */
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup AES_Group2 Structures initialization functions
|
||||
* @brief Structures initialization.
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Structures initialization functions #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Fills each AES_InitStruct member with its default value.
|
||||
* @param AES_InitStruct: pointer to an AES_InitTypeDef structure which will
|
||||
* be initialized.
|
||||
* @retval None
|
||||
*/
|
||||
void AES_StructInit(AES_InitTypeDef* AES_InitStruct)
|
||||
{
|
||||
AES_InitStruct->AES_Operation = AES_Operation_Encryp;
|
||||
AES_InitStruct->AES_Chaining = AES_Chaining_ECB;
|
||||
AES_InitStruct->AES_DataType = AES_DataType_32b;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Fills each AES_KeyInitStruct member with its default value.
|
||||
* @param AES_KeyInitStruct: pointer to an AES_KeyInitStruct structure which
|
||||
* will be initialized.
|
||||
* @retval None
|
||||
*/
|
||||
void AES_KeyStructInit(AES_KeyInitTypeDef* AES_KeyInitStruct)
|
||||
{
|
||||
AES_KeyInitStruct->AES_Key0 = 0x00000000;
|
||||
AES_KeyInitStruct->AES_Key1 = 0x00000000;
|
||||
AES_KeyInitStruct->AES_Key2 = 0x00000000;
|
||||
AES_KeyInitStruct->AES_Key3 = 0x00000000;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Fills each AES_IVInitStruct member with its default value.
|
||||
* @param AES_IVInitStruct: pointer to an AES_IVInitTypeDef structure which
|
||||
* will be initialized.
|
||||
* @retval None
|
||||
*/
|
||||
void AES_IVStructInit(AES_IVInitTypeDef* AES_IVInitStruct)
|
||||
{
|
||||
AES_IVInitStruct->AES_IV0 = 0x00000000;
|
||||
AES_IVInitStruct->AES_IV1 = 0x00000000;
|
||||
AES_IVInitStruct->AES_IV2 = 0x00000000;
|
||||
AES_IVInitStruct->AES_IV3 = 0x00000000;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup AES_Group3 AES Read and Write
|
||||
* @brief AES Read and Write.
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### AES Read and Write functions #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Write data in DINR register to be processed by AES peripheral.
|
||||
* @note To process 128-bit data (4 * 32-bit), this function must be called
|
||||
* four times to write the 128-bit data in the 32-bit register DINR.
|
||||
* @note When an unexpected write to DOUTR register is detected, WRERR flag is
|
||||
* set.
|
||||
* @param Data: The data to be processed.
|
||||
* @retval None
|
||||
*/
|
||||
void AES_WriteSubData(uint32_t Data)
|
||||
{
|
||||
/* Write Data */
|
||||
AES->DINR = Data;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the data in DOUTR register processed by AES peripheral.
|
||||
* @note This function must be called four times to get the 128-bit data.
|
||||
* @note When an unexpected read of DINR register is detected, RDERR flag is
|
||||
* set.
|
||||
* @retval The processed data.
|
||||
*/
|
||||
uint32_t AES_ReadSubData(void)
|
||||
{
|
||||
/* Read Data */
|
||||
return AES->DOUTR;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Read the Key value.
|
||||
* @param AES_KeyInitStruct: pointer to an AES_KeyInitTypeDef structure which
|
||||
* will contain the key.
|
||||
* @note When the key derivation mode is selected, AES must be disabled
|
||||
* (AES_Cmd(DISABLE)) before reading the decryption key.
|
||||
* Reading the key while the AES is enabled will return unpredictable
|
||||
* value.
|
||||
* @retval None
|
||||
*/
|
||||
void AES_ReadKey(AES_KeyInitTypeDef* AES_KeyInitStruct)
|
||||
{
|
||||
AES_KeyInitStruct->AES_Key0 = AES->KEYR0;
|
||||
AES_KeyInitStruct->AES_Key1 = AES->KEYR1;
|
||||
AES_KeyInitStruct->AES_Key2 = AES->KEYR2;
|
||||
AES_KeyInitStruct->AES_Key3 = AES->KEYR3;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Read the Initialization Vector IV value.
|
||||
* @param AES_IVInitStruct: pointer to an AES_IVInitTypeDef structure which
|
||||
* will contain the Initialization Vector IV.
|
||||
* @note When the AES is enabled Reading the Initialization Vector IV value
|
||||
* will return 0. The AES must be disabled using AES_Cmd(DISABLE)
|
||||
* to get the right value.
|
||||
* @note When ECB chaining mode is selected, Initialization Vector IV has no
|
||||
* meaning.
|
||||
* When CTR chaining mode is selected, AES_IV0 contains 32-bit Counter value.
|
||||
* AES_IV1, AES_IV2 and AES_IV3 contains nonce value.
|
||||
* @retval None
|
||||
*/
|
||||
void AES_ReadIV(AES_IVInitTypeDef* AES_IVInitStruct)
|
||||
{
|
||||
AES_IVInitStruct->AES_IV0 = AES->IVR0;
|
||||
AES_IVInitStruct->AES_IV1 = AES->IVR1;
|
||||
AES_IVInitStruct->AES_IV2 = AES->IVR2;
|
||||
AES_IVInitStruct->AES_IV3 = AES->IVR3;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup AES_Group4 DMA transfers management functions
|
||||
* @brief DMA transfers management function.
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### DMA transfers management functions #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Configures the AES DMA interface.
|
||||
* @param AES_DMATransfer: Specifies the AES DMA transfer.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg AES_DMATransfer_In: When selected, DMA manages the data input phase.
|
||||
* @arg AES_DMATransfer_Out: When selected, DMA manages the data output phase.
|
||||
* @arg AES_DMATransfer_InOut: When selected, DMA manages both the data input/output phases.
|
||||
* @param NewState Indicates the new state of the AES DMA interface.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @note The DMA has no action in key derivation mode.
|
||||
* @retval None
|
||||
*/
|
||||
void AES_DMAConfig(uint32_t AES_DMATransfer, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameter */
|
||||
assert_param(IS_AES_DMA_TRANSFER(AES_DMATransfer));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the DMA transfer */
|
||||
AES->CR |= (uint32_t) AES_DMATransfer;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the DMA transfer */
|
||||
AES->CR &= (uint32_t)(~AES_DMATransfer);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup AES_Group5 Interrupts and flags management functions
|
||||
* @brief Interrupts and flags management functions.
|
||||
*
|
||||
@verbatim
|
||||
|
||||
===============================================================================
|
||||
##### Interrupts and flags management functions #####
|
||||
===============================================================================
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the specified AES interrupt.
|
||||
* @param AES_IT: Specifies the AES interrupt source to enable/disable.
|
||||
* This parameter can be any combinations of the following values:
|
||||
* @arg AES_IT_CC: Computation Complete Interrupt. If enabled, once CCF
|
||||
* flag is set an interrupt is generated.
|
||||
* @arg AES_IT_ERR: Error Interrupt. If enabled, once a read error
|
||||
* flags (RDERR) or write error flag (WRERR) is set,
|
||||
* an interrupt is generated.
|
||||
* @param NewState: The new state of the AES interrupt source.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void AES_ITConfig(uint32_t AES_IT, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
assert_param(IS_AES_IT(AES_IT));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
AES->CR |= (uint32_t) AES_IT; /**< AES_IT Enable */
|
||||
}
|
||||
else
|
||||
{
|
||||
AES->CR &= (uint32_t)(~AES_IT); /**< AES_IT Disable */
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified AES flag is set or not.
|
||||
* @param AES_FLAG specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg AES_FLAG_CCF: Computation Complete Flag is set by hardware when
|
||||
* he computation phase is completed.
|
||||
* @arg AES_FLAG_RDERR: Read Error Flag is set when an unexpected read
|
||||
* operation of DOUTR register is detected.
|
||||
* @arg AES_FLAG_WRERR: Write Error Flag is set when an unexpected write
|
||||
* operation in DINR is detected.
|
||||
* @retval FlagStatus (SET or RESET)
|
||||
*/
|
||||
FlagStatus AES_GetFlagStatus(uint32_t AES_FLAG)
|
||||
{
|
||||
FlagStatus bitstatus = RESET;
|
||||
|
||||
/* Check parameters */
|
||||
assert_param(IS_AES_FLAG(AES_FLAG));
|
||||
|
||||
if ((AES->SR & AES_FLAG) != (uint32_t)RESET)
|
||||
{
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = RESET;
|
||||
}
|
||||
|
||||
/* Return the AES_FLAG status */
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the AES flags.
|
||||
* @param AES_FLAG: specifies the flag to clear.
|
||||
* This parameter can be:
|
||||
* @arg AES_FLAG_CCF: Computation Complete Flag is cleared by setting CCFC
|
||||
* bit in CR register.
|
||||
* @arg AES_FLAG_RDERR: Read Error is cleared by setting ERRC bit in
|
||||
* CR register.
|
||||
* @arg AES_FLAG_WRERR: Write Error is cleared by setting ERRC bit in
|
||||
* CR register.
|
||||
* @retval None
|
||||
*/
|
||||
void AES_ClearFlag(uint32_t AES_FLAG)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_AES_FLAG(AES_FLAG));
|
||||
|
||||
/* Check if AES_FLAG is AES_FLAG_CCF */
|
||||
if (AES_FLAG == AES_FLAG_CCF)
|
||||
{
|
||||
/* Clear CCF flag by setting CCFC bit */
|
||||
AES->CR |= (uint32_t) AES_CR_CCFC;
|
||||
}
|
||||
else /* AES_FLAG is AES_FLAG_RDERR or AES_FLAG_WRERR */
|
||||
{
|
||||
/* Clear RDERR and WRERR flags by setting ERRC bit */
|
||||
AES->CR |= (uint32_t) AES_CR_ERRC;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified AES interrupt has occurred or not.
|
||||
* @param AES_IT: Specifies the AES interrupt pending bit to check.
|
||||
* This parameter can be:
|
||||
* @arg AES_IT_CC: Computation Complete Interrupt.
|
||||
* @arg AES_IT_ERR: Error Interrupt.
|
||||
* @retval ITStatus The new state of AES_IT (SET or RESET).
|
||||
*/
|
||||
ITStatus AES_GetITStatus(uint32_t AES_IT)
|
||||
{
|
||||
ITStatus itstatus = RESET;
|
||||
uint32_t cciebitstatus = RESET, ccfbitstatus = RESET;
|
||||
|
||||
/* Check parameters */
|
||||
assert_param(IS_AES_GET_IT(AES_IT));
|
||||
|
||||
cciebitstatus = AES->CR & AES_CR_CCIE;
|
||||
ccfbitstatus = AES->SR & AES_SR_CCF;
|
||||
|
||||
/* Check if AES_IT is AES_IT_CC */
|
||||
if (AES_IT == AES_IT_CC)
|
||||
{
|
||||
/* Check the status of the specified AES interrupt */
|
||||
if (((cciebitstatus) != (uint32_t)RESET) && ((ccfbitstatus) != (uint32_t)RESET))
|
||||
{
|
||||
/* Interrupt occurred */
|
||||
itstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Interrupt didn't occur */
|
||||
itstatus = RESET;
|
||||
}
|
||||
}
|
||||
else /* AES_IT is AES_IT_ERR */
|
||||
{
|
||||
/* Check the status of the specified AES interrupt */
|
||||
if ((AES->CR & AES_CR_ERRIE) != RESET)
|
||||
{
|
||||
/* Check if WRERR or RDERR flags are set */
|
||||
if ((AES->SR & (uint32_t)(AES_SR_WRERR | AES_SR_RDERR)) != (uint16_t)RESET)
|
||||
{
|
||||
/* Interrupt occurred */
|
||||
itstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Interrupt didn't occur */
|
||||
itstatus = RESET;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Interrupt didn't occur */
|
||||
itstatus = (ITStatus) RESET;
|
||||
}
|
||||
}
|
||||
|
||||
/* Return the AES_IT status */
|
||||
return itstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the AES's interrupt pending bits.
|
||||
* @param AES_IT: specifies the interrupt pending bit to clear.
|
||||
* This parameter can be any combinations of the following values:
|
||||
* @arg AES_IT_CC: Computation Complete Interrupt.
|
||||
* @arg AES_IT_ERR: Error Interrupt.
|
||||
* @retval None
|
||||
*/
|
||||
void AES_ClearITPendingBit(uint32_t AES_IT)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_AES_IT(AES_IT));
|
||||
|
||||
/* Clear the interrupt pending bit */
|
||||
AES->CR |= (uint32_t) (AES_IT >> (uint32_t) 0x00000002);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,679 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32l1xx_aes_util.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.1
|
||||
* @date 05-March-2012
|
||||
* @brief This file provides high level functions to encrypt and decrypt an
|
||||
* input message using AES in ECB/CBC/CTR modes.
|
||||
*
|
||||
* @verbatim
|
||||
|
||||
================================================================================
|
||||
##### How to use this driver #####
|
||||
================================================================================
|
||||
[..]
|
||||
(#) Enable The AES controller clock using
|
||||
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_AES, ENABLE); function.
|
||||
|
||||
(#) Use AES_ECB_Encrypt() function to encrypt an input message in ECB mode.
|
||||
(#) Use AES_ECB_Decrypt() function to decrypt an input message in ECB mode.
|
||||
|
||||
(#) Use AES_CBC_Encrypt() function to encrypt an input message in CBC mode.
|
||||
(#) Use AES_CBC_Decrypt() function to decrypt an input message in CBC mode.
|
||||
|
||||
(#) Use AES_CTR_Encrypt() function to encrypt an input message in CTR mode.
|
||||
(#) Use AES_CTR_Decrypt() function to decrypt an input message in CTR mode.
|
||||
|
||||
* @endverbatim
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32l1xx_aes.h"
|
||||
|
||||
/** @addtogroup STM32L1xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup AES
|
||||
* @brief AES driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
#define AES_CC_TIMEOUT ((uint32_t) 0x00010000)
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup AES_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup AES_Group6 High Level AES functions
|
||||
* @brief High Level AES functions
|
||||
*
|
||||
@verbatim
|
||||
================================================================================
|
||||
##### High Level AES functions #####
|
||||
================================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Encrypt using AES in ECB Mode
|
||||
* @param Key: Key used for AES algorithm.
|
||||
* @param Input: pointer to the Input buffer.
|
||||
* @param Ilength: length of the Input buffer, must be a multiple of 16 bytes.
|
||||
* @param Output: pointer to the returned buffer.
|
||||
* @retval An ErrorStatus enumeration value:
|
||||
* - SUCCESS: Operation done
|
||||
* - ERROR: Operation failed
|
||||
*/
|
||||
ErrorStatus AES_ECB_Encrypt(uint8_t* Key, uint8_t* Input, uint32_t Ilength, uint8_t* Output)
|
||||
{
|
||||
AES_InitTypeDef AES_InitStructure;
|
||||
AES_KeyInitTypeDef AES_KeyInitStructure;
|
||||
ErrorStatus status = SUCCESS;
|
||||
uint32_t keyaddr = (uint32_t)Key;
|
||||
uint32_t inputaddr = (uint32_t)Input;
|
||||
uint32_t outputaddr = (uint32_t)Output;
|
||||
__IO uint32_t counter = 0;
|
||||
uint32_t ccstatus = 0;
|
||||
uint32_t i = 0;
|
||||
|
||||
/* AES Key initialisation */
|
||||
AES_KeyInitStructure.AES_Key3 = __REV(*(uint32_t*)(keyaddr));
|
||||
keyaddr += 4;
|
||||
AES_KeyInitStructure.AES_Key2 = __REV(*(uint32_t*)(keyaddr));
|
||||
keyaddr += 4;
|
||||
AES_KeyInitStructure.AES_Key1 = __REV(*(uint32_t*)(keyaddr));
|
||||
keyaddr += 4;
|
||||
AES_KeyInitStructure.AES_Key0 = __REV(*(uint32_t*)(keyaddr));
|
||||
AES_KeyInit(&AES_KeyInitStructure);
|
||||
|
||||
/* AES configuration */
|
||||
AES_InitStructure.AES_Operation = AES_Operation_Encryp;
|
||||
AES_InitStructure.AES_Chaining = AES_Chaining_ECB;
|
||||
AES_InitStructure.AES_DataType = AES_DataType_8b;
|
||||
AES_Init(&AES_InitStructure);
|
||||
|
||||
/* Enable AES */
|
||||
AES_Cmd(ENABLE);
|
||||
|
||||
for(i = 0; ((i < Ilength) && (status != ERROR)); i += 16)
|
||||
{
|
||||
AES_WriteSubData(*(uint32_t*)(inputaddr));
|
||||
inputaddr += 4;
|
||||
AES_WriteSubData(*(uint32_t*)(inputaddr));
|
||||
inputaddr += 4;
|
||||
AES_WriteSubData(*(uint32_t*)(inputaddr));
|
||||
inputaddr += 4;
|
||||
AES_WriteSubData(*(uint32_t*)(inputaddr));
|
||||
inputaddr += 4;
|
||||
|
||||
/* Wait for CCF flag to be set */
|
||||
counter = 0;
|
||||
do
|
||||
{
|
||||
ccstatus = AES_GetFlagStatus(AES_FLAG_CCF);
|
||||
counter++;
|
||||
}while((counter != AES_CC_TIMEOUT) && (ccstatus == RESET));
|
||||
|
||||
if (ccstatus == RESET)
|
||||
{
|
||||
status = ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Clear CCF flag */
|
||||
AES_ClearFlag(AES_FLAG_CCF);
|
||||
/* Read cipher text */
|
||||
*(uint32_t*)(outputaddr) = AES_ReadSubData();
|
||||
outputaddr += 4;
|
||||
*(uint32_t*)(outputaddr) = AES_ReadSubData();
|
||||
outputaddr += 4;
|
||||
*(uint32_t*)(outputaddr) = AES_ReadSubData();
|
||||
outputaddr += 4;
|
||||
*(uint32_t*)(outputaddr) = AES_ReadSubData();
|
||||
outputaddr += 4;
|
||||
}
|
||||
}
|
||||
|
||||
/* Disable AES before starting new processing */
|
||||
AES_Cmd(DISABLE);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Decrypt using AES in ECB Mode
|
||||
* @param Key: Key used for AES algorithm.
|
||||
* @param Input: pointer to the Input buffer.
|
||||
* @param Ilength: length of the Input buffer, must be a multiple of 16 bytes.
|
||||
* @param Output: pointer to the returned buffer.
|
||||
* @retval An ErrorStatus enumeration value:
|
||||
* - SUCCESS: Operation done
|
||||
* - ERROR: Operation failed
|
||||
*/
|
||||
ErrorStatus AES_ECB_Decrypt(uint8_t* Key, uint8_t* Input, uint32_t Ilength, uint8_t* Output)
|
||||
{
|
||||
AES_InitTypeDef AES_InitStructure;
|
||||
AES_KeyInitTypeDef AES_KeyInitStructure;
|
||||
ErrorStatus status = SUCCESS;
|
||||
uint32_t keyaddr = (uint32_t)Key;
|
||||
uint32_t inputaddr = (uint32_t)Input;
|
||||
uint32_t outputaddr = (uint32_t)Output;
|
||||
__IO uint32_t counter = 0;
|
||||
uint32_t ccstatus = 0;
|
||||
uint32_t i = 0;
|
||||
|
||||
/* AES Key initialisation */
|
||||
AES_KeyInitStructure.AES_Key3 = __REV(*(uint32_t*)(keyaddr));
|
||||
keyaddr += 4;
|
||||
AES_KeyInitStructure.AES_Key2 = __REV(*(uint32_t*)(keyaddr));
|
||||
keyaddr += 4;
|
||||
AES_KeyInitStructure.AES_Key1 = __REV(*(uint32_t*)(keyaddr));
|
||||
keyaddr += 4;
|
||||
AES_KeyInitStructure.AES_Key0 = __REV(*(uint32_t*)(keyaddr));
|
||||
AES_KeyInit(&AES_KeyInitStructure);
|
||||
|
||||
/* AES configuration */
|
||||
AES_InitStructure.AES_Operation = AES_Operation_KeyDerivAndDecryp;
|
||||
AES_InitStructure.AES_Chaining = AES_Chaining_ECB;
|
||||
AES_InitStructure.AES_DataType = AES_DataType_8b;
|
||||
AES_Init(&AES_InitStructure);
|
||||
|
||||
/* Enable AES */
|
||||
AES_Cmd(ENABLE);
|
||||
|
||||
for(i = 0; ((i < Ilength) && (status != ERROR)); i += 16)
|
||||
{
|
||||
AES_WriteSubData(*(uint32_t*)(inputaddr));
|
||||
inputaddr += 4;
|
||||
AES_WriteSubData(*(uint32_t*)(inputaddr));
|
||||
inputaddr += 4;
|
||||
AES_WriteSubData(*(uint32_t*)(inputaddr));
|
||||
inputaddr += 4;
|
||||
AES_WriteSubData(*(uint32_t*)(inputaddr));
|
||||
inputaddr += 4;
|
||||
|
||||
/* Wait for CCF flag to be set */
|
||||
counter = 0;
|
||||
do
|
||||
{
|
||||
ccstatus = AES_GetFlagStatus(AES_FLAG_CCF);
|
||||
counter++;
|
||||
}while((counter != AES_CC_TIMEOUT) && (ccstatus == RESET));
|
||||
|
||||
if (ccstatus == RESET)
|
||||
{
|
||||
status = ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Clear CCF flag */
|
||||
AES_ClearFlag(AES_FLAG_CCF);
|
||||
|
||||
/* Read cipher text */
|
||||
*(uint32_t*)(outputaddr) = AES_ReadSubData();
|
||||
outputaddr += 4;
|
||||
*(uint32_t*)(outputaddr) = AES_ReadSubData();
|
||||
outputaddr += 4;
|
||||
*(uint32_t*)(outputaddr) = AES_ReadSubData();
|
||||
outputaddr += 4;
|
||||
*(uint32_t*)(outputaddr) = AES_ReadSubData();
|
||||
outputaddr += 4;
|
||||
}
|
||||
}
|
||||
|
||||
/* Disable AES before starting new processing */
|
||||
AES_Cmd(DISABLE);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Encrypt using AES in CBC Mode
|
||||
* @param InitVectors: Initialisation Vectors used for AES algorithm.
|
||||
* @param Key: Key used for AES algorithm.
|
||||
* @param Input: pointer to the Input buffer.
|
||||
* @param Ilength: length of the Input buffer, must be a multiple of 16 bytes.
|
||||
* @param Output: pointer to the returned buffer.
|
||||
* @retval An ErrorStatus enumeration value:
|
||||
* - SUCCESS: Operation done
|
||||
* - ERROR: Operation failed
|
||||
*/
|
||||
ErrorStatus AES_CBC_Encrypt(uint8_t* Key, uint8_t InitVectors[16], uint8_t* Input, uint32_t Ilength, uint8_t* Output)
|
||||
{
|
||||
AES_InitTypeDef AES_InitStructure;
|
||||
AES_KeyInitTypeDef AES_KeyInitStructure;
|
||||
AES_IVInitTypeDef AES_IVInitStructure;
|
||||
ErrorStatus status = SUCCESS;
|
||||
uint32_t keyaddr = (uint32_t)Key;
|
||||
uint32_t inputaddr = (uint32_t)Input;
|
||||
uint32_t outputaddr = (uint32_t)Output;
|
||||
uint32_t ivaddr = (uint32_t)InitVectors;
|
||||
__IO uint32_t counter = 0;
|
||||
uint32_t ccstatus = 0;
|
||||
uint32_t i = 0;
|
||||
|
||||
/* AES Key initialisation*/
|
||||
AES_KeyInitStructure.AES_Key3 = __REV(*(uint32_t*)(keyaddr));
|
||||
keyaddr += 4;
|
||||
AES_KeyInitStructure.AES_Key2 = __REV(*(uint32_t*)(keyaddr));
|
||||
keyaddr += 4;
|
||||
AES_KeyInitStructure.AES_Key1 = __REV(*(uint32_t*)(keyaddr));
|
||||
keyaddr += 4;
|
||||
AES_KeyInitStructure.AES_Key0 = __REV(*(uint32_t*)(keyaddr));
|
||||
AES_KeyInit(&AES_KeyInitStructure);
|
||||
|
||||
/* AES Initialization Vectors */
|
||||
AES_IVInitStructure.AES_IV3 = __REV(*(uint32_t*)(ivaddr));
|
||||
ivaddr += 4;
|
||||
AES_IVInitStructure.AES_IV2 = __REV(*(uint32_t*)(ivaddr));
|
||||
ivaddr += 4;
|
||||
AES_IVInitStructure.AES_IV1 = __REV(*(uint32_t*)(ivaddr));
|
||||
ivaddr += 4;
|
||||
AES_IVInitStructure.AES_IV0 = __REV(*(uint32_t*)(ivaddr));
|
||||
AES_IVInit(&AES_IVInitStructure);
|
||||
|
||||
/* AES configuration */
|
||||
AES_InitStructure.AES_Operation = AES_Operation_Encryp;
|
||||
AES_InitStructure.AES_Chaining = AES_Chaining_CBC;
|
||||
AES_InitStructure.AES_DataType = AES_DataType_8b;
|
||||
AES_Init(&AES_InitStructure);
|
||||
|
||||
/* Enable AES */
|
||||
AES_Cmd(ENABLE);
|
||||
|
||||
for(i = 0; ((i < Ilength) && (status != ERROR)); i += 16)
|
||||
{
|
||||
AES_WriteSubData(*(uint32_t*)(inputaddr));
|
||||
inputaddr += 4;
|
||||
AES_WriteSubData(*(uint32_t*)(inputaddr));
|
||||
inputaddr += 4;
|
||||
AES_WriteSubData(*(uint32_t*)(inputaddr));
|
||||
inputaddr += 4;
|
||||
AES_WriteSubData(*(uint32_t*)(inputaddr));
|
||||
inputaddr += 4;
|
||||
|
||||
/* Wait for CCF flag to be set */
|
||||
counter = 0;
|
||||
do
|
||||
{
|
||||
ccstatus = AES_GetFlagStatus(AES_FLAG_CCF);
|
||||
counter++;
|
||||
}while((counter != AES_CC_TIMEOUT) && (ccstatus == RESET));
|
||||
|
||||
if (ccstatus == RESET)
|
||||
{
|
||||
status = ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Clear CCF flag */
|
||||
AES_ClearFlag(AES_FLAG_CCF);
|
||||
|
||||
/* Read cipher text */
|
||||
*(uint32_t*)(outputaddr) = AES_ReadSubData();
|
||||
outputaddr += 4;
|
||||
*(uint32_t*)(outputaddr) = AES_ReadSubData();
|
||||
outputaddr += 4;
|
||||
*(uint32_t*)(outputaddr) = AES_ReadSubData();
|
||||
outputaddr += 4;
|
||||
*(uint32_t*)(outputaddr) = AES_ReadSubData();
|
||||
outputaddr += 4;
|
||||
}
|
||||
}
|
||||
|
||||
/* Disable AES before starting new processing */
|
||||
AES_Cmd(DISABLE);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Decrypt using AES in CBC Mode
|
||||
* @param InitVectors: Initialisation Vectors used for AES algorithm.
|
||||
* @param Key: Key used for AES algorithm.
|
||||
* @param Input: pointer to the Input buffer.
|
||||
* @param Ilength: length of the Input buffer, must be a multiple of 16 bytes.
|
||||
* @param Output: pointer to the returned buffer.
|
||||
* @retval An ErrorStatus enumeration value:
|
||||
* - SUCCESS: Operation done
|
||||
* - ERROR: Operation failed
|
||||
*/
|
||||
ErrorStatus AES_CBC_Decrypt(uint8_t* Key, uint8_t InitVectors[16], uint8_t* Input, uint32_t Ilength, uint8_t* Output)
|
||||
{
|
||||
AES_InitTypeDef AES_InitStructure;
|
||||
AES_KeyInitTypeDef AES_KeyInitStructure;
|
||||
AES_IVInitTypeDef AES_IVInitStructure;
|
||||
ErrorStatus status = SUCCESS;
|
||||
uint32_t keyaddr = (uint32_t)Key;
|
||||
uint32_t inputaddr = (uint32_t)Input;
|
||||
uint32_t outputaddr = (uint32_t)Output;
|
||||
uint32_t ivaddr = (uint32_t)InitVectors;
|
||||
__IO uint32_t counter = 0;
|
||||
uint32_t ccstatus = 0;
|
||||
uint32_t i = 0;
|
||||
|
||||
/* AES Key initialisation*/
|
||||
AES_KeyInitStructure.AES_Key3 = __REV(*(uint32_t*)(keyaddr));
|
||||
keyaddr += 4;
|
||||
AES_KeyInitStructure.AES_Key2 = __REV(*(uint32_t*)(keyaddr));
|
||||
keyaddr += 4;
|
||||
AES_KeyInitStructure.AES_Key1 = __REV(*(uint32_t*)(keyaddr));
|
||||
keyaddr += 4;
|
||||
AES_KeyInitStructure.AES_Key0 = __REV(*(uint32_t*)(keyaddr));
|
||||
AES_KeyInit(&AES_KeyInitStructure);
|
||||
|
||||
/* AES Initialization Vectors */
|
||||
AES_IVInitStructure.AES_IV3 = __REV(*(uint32_t*)(ivaddr));
|
||||
ivaddr += 4;
|
||||
AES_IVInitStructure.AES_IV2 = __REV(*(uint32_t*)(ivaddr));
|
||||
ivaddr += 4;
|
||||
AES_IVInitStructure.AES_IV1 = __REV(*(uint32_t*)(ivaddr));
|
||||
ivaddr += 4;
|
||||
AES_IVInitStructure.AES_IV0 = __REV(*(uint32_t*)(ivaddr));
|
||||
AES_IVInit(&AES_IVInitStructure);
|
||||
|
||||
/* AES configuration */
|
||||
AES_InitStructure.AES_Operation = AES_Operation_KeyDerivAndDecryp;
|
||||
AES_InitStructure.AES_Chaining = AES_Chaining_CBC;
|
||||
AES_InitStructure.AES_DataType = AES_DataType_8b;
|
||||
AES_Init(&AES_InitStructure);
|
||||
|
||||
/* Enable AES */
|
||||
AES_Cmd(ENABLE);
|
||||
|
||||
for(i = 0; ((i < Ilength) && (status != ERROR)); i += 16)
|
||||
{
|
||||
AES_WriteSubData(*(uint32_t*)(inputaddr));
|
||||
inputaddr += 4;
|
||||
AES_WriteSubData(*(uint32_t*)(inputaddr));
|
||||
inputaddr += 4;
|
||||
AES_WriteSubData(*(uint32_t*)(inputaddr));
|
||||
inputaddr += 4;
|
||||
AES_WriteSubData(*(uint32_t*)(inputaddr));
|
||||
inputaddr += 4;
|
||||
|
||||
/* Wait for CCF flag to be set */
|
||||
counter = 0;
|
||||
do
|
||||
{
|
||||
ccstatus = AES_GetFlagStatus(AES_FLAG_CCF);
|
||||
counter++;
|
||||
}while((counter != AES_CC_TIMEOUT) && (ccstatus == RESET));
|
||||
|
||||
if (ccstatus == RESET)
|
||||
{
|
||||
status = ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Clear CCF flag */
|
||||
AES_ClearFlag(AES_FLAG_CCF);
|
||||
|
||||
/* Read cipher text */
|
||||
*(uint32_t*)(outputaddr) = AES_ReadSubData();
|
||||
outputaddr += 4;
|
||||
*(uint32_t*)(outputaddr) = AES_ReadSubData();
|
||||
outputaddr += 4;
|
||||
*(uint32_t*)(outputaddr) = AES_ReadSubData();
|
||||
outputaddr += 4;
|
||||
*(uint32_t*)(outputaddr) = AES_ReadSubData();
|
||||
outputaddr += 4;
|
||||
}
|
||||
}
|
||||
|
||||
/* Disable AES before starting new processing */
|
||||
AES_Cmd(DISABLE);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Encrypt using AES in CTR Mode
|
||||
* @param InitVectors: Initialisation Vectors used for AES algorithm.
|
||||
* @param Key: Key used for AES algorithm.
|
||||
* @param Input: pointer to the Input buffer.
|
||||
* @param Ilength: length of the Input buffer, must be a multiple of 16 bytes.
|
||||
* @param Output: pointer to the returned buffer.
|
||||
* @retval An ErrorStatus enumeration value:
|
||||
* - SUCCESS: Operation done
|
||||
* - ERROR: Operation failed
|
||||
*/
|
||||
ErrorStatus AES_CTR_Encrypt(uint8_t* Key, uint8_t InitVectors[16], uint8_t* Input, uint32_t Ilength, uint8_t* Output)
|
||||
{
|
||||
AES_InitTypeDef AES_InitStructure;
|
||||
AES_KeyInitTypeDef AES_KeyInitStructure;
|
||||
AES_IVInitTypeDef AES_IVInitStructure;
|
||||
|
||||
ErrorStatus status = SUCCESS;
|
||||
uint32_t keyaddr = (uint32_t)Key;
|
||||
uint32_t inputaddr = (uint32_t)Input;
|
||||
uint32_t outputaddr = (uint32_t)Output;
|
||||
uint32_t ivaddr = (uint32_t)InitVectors;
|
||||
__IO uint32_t counter = 0;
|
||||
uint32_t ccstatus = 0;
|
||||
uint32_t i = 0;
|
||||
|
||||
/* AES key initialisation*/
|
||||
AES_KeyInitStructure.AES_Key3 = __REV(*(uint32_t*)(keyaddr));
|
||||
keyaddr += 4;
|
||||
AES_KeyInitStructure.AES_Key2 = __REV(*(uint32_t*)(keyaddr));
|
||||
keyaddr += 4;
|
||||
AES_KeyInitStructure.AES_Key1 = __REV(*(uint32_t*)(keyaddr));
|
||||
keyaddr += 4;
|
||||
AES_KeyInitStructure.AES_Key0 = __REV(*(uint32_t*)(keyaddr));
|
||||
AES_KeyInit(&AES_KeyInitStructure);
|
||||
|
||||
/* AES Initialization Vectors */
|
||||
AES_IVInitStructure.AES_IV3 = __REV(*(uint32_t*)(ivaddr));
|
||||
ivaddr += 4;
|
||||
AES_IVInitStructure.AES_IV2= __REV(*(uint32_t*)(ivaddr));
|
||||
ivaddr += 4;
|
||||
AES_IVInitStructure.AES_IV1 = __REV(*(uint32_t*)(ivaddr));
|
||||
ivaddr += 4;
|
||||
AES_IVInitStructure.AES_IV0= __REV(*(uint32_t*)(ivaddr));
|
||||
AES_IVInit(&AES_IVInitStructure);
|
||||
|
||||
/* AES configuration */
|
||||
AES_InitStructure.AES_Operation = AES_Operation_Encryp;
|
||||
AES_InitStructure.AES_Chaining = AES_Chaining_CTR;
|
||||
AES_InitStructure.AES_DataType = AES_DataType_8b;
|
||||
AES_Init(&AES_InitStructure);
|
||||
|
||||
/* Enable AES */
|
||||
AES_Cmd(ENABLE);
|
||||
|
||||
for(i = 0; ((i < Ilength) && (status != ERROR)); i += 16)
|
||||
{
|
||||
AES_WriteSubData(*(uint32_t*)(inputaddr));
|
||||
inputaddr += 4;
|
||||
AES_WriteSubData(*(uint32_t*)(inputaddr));
|
||||
inputaddr += 4;
|
||||
AES_WriteSubData(*(uint32_t*)(inputaddr));
|
||||
inputaddr += 4;
|
||||
AES_WriteSubData(*(uint32_t*)(inputaddr));
|
||||
inputaddr += 4;
|
||||
|
||||
/* Wait for CCF flag to be set */
|
||||
counter = 0;
|
||||
do
|
||||
{
|
||||
ccstatus = AES_GetFlagStatus(AES_FLAG_CCF);
|
||||
counter++;
|
||||
}while((counter != AES_CC_TIMEOUT) && (ccstatus == RESET));
|
||||
|
||||
if (ccstatus == RESET)
|
||||
{
|
||||
status = ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Clear CCF flag */
|
||||
AES_ClearFlag(AES_FLAG_CCF);
|
||||
|
||||
/* Read cipher text */
|
||||
*(uint32_t*)(outputaddr) = AES_ReadSubData();
|
||||
outputaddr += 4;
|
||||
*(uint32_t*)(outputaddr) = AES_ReadSubData();
|
||||
outputaddr += 4;
|
||||
*(uint32_t*)(outputaddr) = AES_ReadSubData();
|
||||
outputaddr += 4;
|
||||
*(uint32_t*)(outputaddr) = AES_ReadSubData();
|
||||
outputaddr += 4;
|
||||
}
|
||||
}
|
||||
|
||||
/* Disable AES before starting new processing */
|
||||
AES_Cmd(DISABLE);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Decrypt using AES in CTR Mode
|
||||
* @param InitVectors: Initialisation Vectors used for AES algorithm.
|
||||
* @param Key: Key used for AES algorithm.
|
||||
* @param Input: pointer to the Input buffer.
|
||||
* @param Ilength: length of the Input buffer, must be a multiple of 16 bytes.
|
||||
* @param Output: pointer to the returned buffer.
|
||||
* @retval An ErrorStatus enumeration value:
|
||||
* - SUCCESS: Operation done
|
||||
* - ERROR: Operation failed
|
||||
*/
|
||||
ErrorStatus AES_CTR_Decrypt(uint8_t* Key, uint8_t InitVectors[16], uint8_t* Input, uint32_t Ilength, uint8_t* Output)
|
||||
{
|
||||
AES_InitTypeDef AES_InitStructure;
|
||||
AES_KeyInitTypeDef AES_KeyInitStructure;
|
||||
AES_IVInitTypeDef AES_IVInitStructure;
|
||||
|
||||
ErrorStatus status = SUCCESS;
|
||||
uint32_t keyaddr = (uint32_t)Key;
|
||||
uint32_t inputaddr = (uint32_t)Input;
|
||||
uint32_t outputaddr = (uint32_t)Output;
|
||||
uint32_t ivaddr = (uint32_t)InitVectors;
|
||||
__IO uint32_t counter = 0;
|
||||
uint32_t ccstatus = 0;
|
||||
uint32_t i = 0;
|
||||
|
||||
/* AES Key initialisation*/
|
||||
AES_KeyInitStructure.AES_Key3 = __REV(*(uint32_t*)(keyaddr));
|
||||
keyaddr += 4;
|
||||
AES_KeyInitStructure.AES_Key2 = __REV(*(uint32_t*)(keyaddr));
|
||||
keyaddr += 4;
|
||||
AES_KeyInitStructure.AES_Key1 = __REV(*(uint32_t*)(keyaddr));
|
||||
keyaddr += 4;
|
||||
AES_KeyInitStructure.AES_Key0 = __REV(*(uint32_t*)(keyaddr));
|
||||
AES_KeyInit(&AES_KeyInitStructure);
|
||||
|
||||
/* AES Initialization Vectors */
|
||||
AES_IVInitStructure.AES_IV3 = __REV(*(uint32_t*)(ivaddr));
|
||||
ivaddr += 4;
|
||||
AES_IVInitStructure.AES_IV2 = __REV(*(uint32_t*)(ivaddr));
|
||||
ivaddr += 4;
|
||||
AES_IVInitStructure.AES_IV1 = __REV(*(uint32_t*)(ivaddr));
|
||||
ivaddr += 4;
|
||||
AES_IVInitStructure.AES_IV0 = __REV(*(uint32_t*)(ivaddr));
|
||||
AES_IVInit(&AES_IVInitStructure);
|
||||
|
||||
/* AES configuration */
|
||||
AES_InitStructure.AES_Operation = AES_Operation_KeyDerivAndDecryp;
|
||||
AES_InitStructure.AES_Chaining = AES_Chaining_CTR;
|
||||
AES_InitStructure.AES_DataType = AES_DataType_8b;
|
||||
AES_Init(&AES_InitStructure);
|
||||
|
||||
/* Enable AES */
|
||||
AES_Cmd(ENABLE);
|
||||
|
||||
for(i = 0; ((i < Ilength) && (status != ERROR)); i += 16)
|
||||
{
|
||||
AES_WriteSubData(*(uint32_t*)(inputaddr));
|
||||
inputaddr += 4;
|
||||
AES_WriteSubData(*(uint32_t*)(inputaddr));
|
||||
inputaddr += 4;
|
||||
AES_WriteSubData(*(uint32_t*)(inputaddr));
|
||||
inputaddr += 4;
|
||||
AES_WriteSubData(*(uint32_t*)(inputaddr));
|
||||
inputaddr += 4;
|
||||
|
||||
/* Wait for CCF flag to be set */
|
||||
counter = 0;
|
||||
do
|
||||
{
|
||||
ccstatus = AES_GetFlagStatus(AES_FLAG_CCF);
|
||||
counter++;
|
||||
}while((counter != AES_CC_TIMEOUT) && (ccstatus == RESET));
|
||||
|
||||
if (ccstatus == RESET)
|
||||
{
|
||||
status = ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Clear CCF flag */
|
||||
AES_ClearFlag(AES_FLAG_CCF);
|
||||
|
||||
/* Read cipher text */
|
||||
*(uint32_t*)(outputaddr) = AES_ReadSubData();
|
||||
outputaddr += 4;
|
||||
*(uint32_t*)(outputaddr) = AES_ReadSubData();
|
||||
outputaddr += 4;
|
||||
*(uint32_t*)(outputaddr) = AES_ReadSubData();
|
||||
outputaddr += 4;
|
||||
*(uint32_t*)(outputaddr) = AES_ReadSubData();
|
||||
outputaddr += 4;
|
||||
}
|
||||
}
|
||||
|
||||
/* Disable AES before starting new processing */
|
||||
AES_Cmd(DISABLE);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
||||
|
|
@ -0,0 +1,378 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32l1xx_comp.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.1
|
||||
* @date 05-March-2012
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the comparators (COMP1 and COMP2) peripheral:
|
||||
* + Comparators configuration
|
||||
* + Window mode control
|
||||
* + Internal Reference Voltage (VREFINT) output
|
||||
*
|
||||
* @verbatim
|
||||
===============================================================================
|
||||
##### How to use this driver #####
|
||||
===============================================================================
|
||||
[..] The device integrates two analog comparators COMP1 and COMP2:
|
||||
(+) COMP1 is a fixed threshold (VREFINT) that shares the non inverting
|
||||
input with the ADC channels.
|
||||
(+) COMP2 is a rail-to-rail comparator whose the inverting input can be
|
||||
selected among: DAC_OUT1, DAC_OUT2, 1/4 VREFINT, 1/2 VERFINT, 3/4
|
||||
VREFINT, VREFINT, PB3 and whose the output can be redirected to
|
||||
embedded timers: TIM2, TIM3, TIM4, TIM10.
|
||||
|
||||
(+) The two comparators COMP1 and COMP2 can be combined in window mode.
|
||||
|
||||
-@-
|
||||
(#@) Comparator APB clock must be enabled to get write access
|
||||
to comparator register using
|
||||
RCC_APB1PeriphClockCmd(RCC_APB1Periph_COMP, ENABLE).
|
||||
|
||||
(#@) COMP1 comparator and ADC can't be used at the same time since
|
||||
they share the same ADC switch matrix (analog switches).
|
||||
|
||||
(#@) When an I/O is used as comparator input, the corresponding GPIO
|
||||
registers should be configured in analog mode.
|
||||
|
||||
(#@) Comparators outputs (CMP1OUT and CMP2OUT) are not mapped on
|
||||
GPIO pin. They are only internal.
|
||||
To get the comparator output level, use COMP_GetOutputLevel().
|
||||
|
||||
(#@) COMP1 and COMP2 outputs are internally connected to EXTI Line 21
|
||||
and EXTI Line 22 respectively.
|
||||
Interrupts can be used by configuring the EXTI Line using the
|
||||
EXTI peripheral driver.
|
||||
|
||||
(#@) After enabling the comparator (COMP1 or COMP2), user should wait
|
||||
for start-up time (tSTART) to get right output levels.
|
||||
Please refer to product datasheet for more information on tSTART.
|
||||
|
||||
(#@) Comparators cannot be used to exit the device from Sleep or Stop
|
||||
mode when the internal reference voltage is switched off using
|
||||
the PWR_UltraLowPowerCmd() function (ULP bit in the PWR_CR register).
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32l1xx_comp.h"
|
||||
|
||||
/** @addtogroup STM32L1xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup COMP
|
||||
* @brief COMP driver modules.
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup COMP_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_Group1 Initialization and Configuration functions
|
||||
* @brief Initialization and Configuration functions.
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Initialization and Configuration functions #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Deinitializes COMP peripheral registers to their default reset values.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void COMP_DeInit(void)
|
||||
{
|
||||
COMP->CSR = ((uint32_t)0x00000000); /*!< Set COMP->CSR to reset value */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the COMP2 peripheral according to the specified parameters
|
||||
* in the COMP_InitStruct.
|
||||
* @note This function configures only COMP2.
|
||||
* @note COMP2 comparator is enabled as soon as the INSEL[2:0] bits are
|
||||
* different from "000".
|
||||
* @param COMP_InitStruct: pointer to an COMP_InitTypeDef structure that contains
|
||||
* the configuration information for the specified COMP peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
void COMP_Init(COMP_InitTypeDef* COMP_InitStruct)
|
||||
{
|
||||
uint32_t tmpreg = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_COMP_INVERTING_INPUT(COMP_InitStruct->COMP_InvertingInput));
|
||||
assert_param(IS_COMP_OUTPUT(COMP_InitStruct->COMP_OutputSelect));
|
||||
assert_param(IS_COMP_SPEED(COMP_InitStruct->COMP_Speed));
|
||||
|
||||
/*!< Get the COMP CSR value */
|
||||
tmpreg = COMP->CSR;
|
||||
|
||||
/*!< Clear the INSEL[2:0], OUTSEL[1:0] and SPEED bits */
|
||||
tmpreg &= (uint32_t) (~(uint32_t) (COMP_CSR_OUTSEL | COMP_CSR_INSEL | COMP_CSR_SPEED));
|
||||
|
||||
/*!< Configure COMP: speed, inversion input selection and output redirection */
|
||||
/*!< Set SPEED bit according to COMP_InitStruct->COMP_Speed value */
|
||||
/*!< Set INSEL bits according to COMP_InitStruct->COMP_InvertingInput value */
|
||||
/*!< Set OUTSEL bits according to COMP_InitStruct->COMP_OutputSelect value */
|
||||
tmpreg |= (uint32_t)((COMP_InitStruct->COMP_Speed | COMP_InitStruct->COMP_InvertingInput
|
||||
| COMP_InitStruct->COMP_OutputSelect));
|
||||
|
||||
/*!< The COMP2 comparator is enabled as soon as the INSEL[2:0] bits value are
|
||||
different from "000" */
|
||||
/*!< Write to COMP_CSR register */
|
||||
COMP->CSR = tmpreg;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable or disable the COMP1 peripheral.
|
||||
* @note After enabling COMP1, the following functions should be called to
|
||||
* connect the selected GPIO input to COMP1 non inverting input:
|
||||
* @note Enable switch control mode using SYSCFG_RISwitchControlModeCmd()
|
||||
* @note Close VCOMP switch using SYSCFG_RIIOSwitchConfig()
|
||||
* @note Close the I/O switch number n corresponding to the I/O
|
||||
* using SYSCFG_RIIOSwitchConfig()
|
||||
* @param NewState: new state of the COMP1 peripheral.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @note This function enables/disables only the COMP1.
|
||||
* @retval None
|
||||
*/
|
||||
void COMP_Cmd(FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameter */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the COMP1 */
|
||||
COMP->CSR |= (uint32_t) COMP_CSR_CMP1EN;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the COMP1 */
|
||||
COMP->CSR &= (uint32_t)(~COMP_CSR_CMP1EN);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Return the output level (high or low) of the selected comparator.
|
||||
* @note Comparator output is low when the noninverting input is at a lower
|
||||
* voltage than the inverting input.
|
||||
* @note Comparator output is high when the noninverting input is at a higher
|
||||
* voltage than the inverting input.
|
||||
* @note Comparators outputs aren't available on GPIO (outputs levels are
|
||||
* only internal). The COMP1 and COMP2 outputs are connected internally
|
||||
* to the EXTI Line 21 and Line 22 respectively.
|
||||
* @param COMP_Selection: the selected comparator.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg COMP_Selection_COMP1: COMP1 selected
|
||||
* @arg COMP_Selection_COMP2: COMP2 selected
|
||||
* @retval Returns the selected comparator output level.
|
||||
*/
|
||||
uint8_t COMP_GetOutputLevel(uint32_t COMP_Selection)
|
||||
{
|
||||
uint8_t compout = 0x0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_COMP_ALL_PERIPH(COMP_Selection));
|
||||
|
||||
/* Check if Comparator 1 is selected */
|
||||
if(COMP_Selection == COMP_Selection_COMP1)
|
||||
{
|
||||
/* Check if comparator 1 output level is high */
|
||||
if((COMP->CSR & COMP_CSR_CMP1OUT) != (uint8_t) RESET)
|
||||
{
|
||||
/* Get Comparator 1 output level */
|
||||
compout = (uint8_t) COMP_OutputLevel_High;
|
||||
}
|
||||
/* comparator 1 output level is low */
|
||||
else
|
||||
{
|
||||
/* Get Comparator 1 output level */
|
||||
compout = (uint8_t) COMP_OutputLevel_Low;
|
||||
}
|
||||
}
|
||||
/* Comparator 2 is selected */
|
||||
else
|
||||
{
|
||||
/* Check if comparator 2 output level is high */
|
||||
if((COMP->CSR & COMP_CSR_CMP2OUT) != (uint8_t) RESET)
|
||||
{
|
||||
/* Get Comparator output level */
|
||||
compout = (uint8_t) COMP_OutputLevel_High;
|
||||
}
|
||||
/* comparator 2 output level is low */
|
||||
else
|
||||
{
|
||||
/* Get Comparator 2 output level */
|
||||
compout = (uint8_t) COMP_OutputLevel_Low;
|
||||
}
|
||||
}
|
||||
/* Return the comparator output level */
|
||||
return (uint8_t)(compout);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Close or Open the SW1 switch.
|
||||
* @param NewState: new state of the SW1 switch.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @note ENABLE to close the SW1 switch
|
||||
* @note DISABLE to open the SW1 switch
|
||||
* @retval None.
|
||||
*/
|
||||
void COMP_SW1SwitchConfig(FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Close SW1 switch */
|
||||
COMP->CSR |= (uint32_t) COMP_CSR_SW1;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Open SW1 switch */
|
||||
COMP->CSR &= (uint32_t)(~COMP_CSR_SW1);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_Group2 Window mode control function
|
||||
* @brief Window mode control function.
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Window mode control function #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the window mode.
|
||||
* In window mode:
|
||||
* @note COMP1 inverting input is fixed to VREFINT defining the first
|
||||
* threshold.
|
||||
* @note COMP2 inverting input is configurable (DAC_OUT1, DAC_OUT2, VREFINT
|
||||
* sub-multiples, PB3) defining the second threshold.
|
||||
* @note COMP1 and COMP2 non inverting inputs are connected together.
|
||||
* @note In window mode, only the Group 6 (PB4 or PB5) can be used as
|
||||
* noninverting inputs.
|
||||
* @param NewState: new state of the window mode.
|
||||
* This parameter can be ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void COMP_WindowCmd(FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the window mode */
|
||||
COMP->CSR |= (uint32_t) COMP_CSR_WNDWE;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the window mode */
|
||||
COMP->CSR &= (uint32_t)(~COMP_CSR_WNDWE);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup COMP_Group3 Internal Reference Voltage output function
|
||||
* @brief Internal Reference Voltage (VREFINT) output function.
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Internal Reference Voltage (VREFINT) output function #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the output of internal reference voltage (VREFINT).
|
||||
* The VREFINT output can be routed to any I/O in group 3: CH8 (PB0) or
|
||||
* CH9 (PB1).
|
||||
* To correctly use this function, the SYSCFG_RIIOSwitchConfig() function
|
||||
* should be called after.
|
||||
* @param NewState: new state of the Vrefint output.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void COMP_VrefintOutputCmd(FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the output of internal reference voltage */
|
||||
COMP->CSR |= (uint32_t) COMP_CSR_VREFOUTEN;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the output of internal reference voltage */
|
||||
COMP->CSR &= (uint32_t) (~COMP_CSR_VREFOUTEN);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,133 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32l1xx_crc.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.1
|
||||
* @date 05-March-2012
|
||||
* @brief This file provides all the CRC firmware functions.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32l1xx_crc.h"
|
||||
|
||||
/** @addtogroup STM32L1xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup CRC
|
||||
* @brief CRC driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup CRC_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Resets the CRC Data register (DR).
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void CRC_ResetDR(void)
|
||||
{
|
||||
/* Reset CRC generator */
|
||||
CRC->CR = CRC_CR_RESET;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Computes the 32-bit CRC of a given data word(32-bit).
|
||||
* @param Data: data word(32-bit) to compute its CRC.
|
||||
* @retval 32-bit CRC
|
||||
*/
|
||||
uint32_t CRC_CalcCRC(uint32_t Data)
|
||||
{
|
||||
CRC->DR = Data;
|
||||
|
||||
return (CRC->DR);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Computes the 32-bit CRC of a given buffer of data word(32-bit).
|
||||
* @param pBuffer: pointer to the buffer containing the data to be computed.
|
||||
* @param BufferLength: length of the buffer to be computed
|
||||
* @retval 32-bit CRC
|
||||
*/
|
||||
uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength)
|
||||
{
|
||||
uint32_t index = 0;
|
||||
|
||||
for(index = 0; index < BufferLength; index++)
|
||||
{
|
||||
CRC->DR = pBuffer[index];
|
||||
}
|
||||
return (CRC->DR);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the current CRC value.
|
||||
* @param None
|
||||
* @retval 32-bit CRC
|
||||
*/
|
||||
uint32_t CRC_GetCRC(void)
|
||||
{
|
||||
return (CRC->DR);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Stores a 8-bit data in the Independent Data(ID) register.
|
||||
* @param IDValue: 8-bit value to be stored in the ID register
|
||||
* @retval None
|
||||
*/
|
||||
void CRC_SetIDRegister(uint8_t IDValue)
|
||||
{
|
||||
CRC->IDR = IDValue;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the 8-bit data stored in the Independent Data(ID) register.
|
||||
* @param None
|
||||
* @retval 8-bit value of the ID register
|
||||
*/
|
||||
uint8_t CRC_GetIDRegister(void)
|
||||
{
|
||||
return (CRC->IDR);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,687 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32l1xx_dac.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.1
|
||||
* @date 05-March-2012
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the Digital-to-Analog Converter (DAC) peripheral:
|
||||
* + DAC channels configuration: trigger, output buffer, data format
|
||||
* + DMA management
|
||||
* + Interrupts and flags management
|
||||
|
||||
* @verbatim
|
||||
*
|
||||
===============================================================================
|
||||
##### DAC Peripheral features #####
|
||||
===============================================================================
|
||||
[..] The device integrates two 12-bit Digital Analog Converters that can
|
||||
be used independently or simultaneously (dual mode):
|
||||
(#) DAC channel1 with DAC_OUT1 (PA4) as output.
|
||||
(#) DAC channel2 with DAC_OUT2 (PA5) as output.
|
||||
|
||||
[..] Digital to Analog conversion can be non-triggered using DAC_Trigger_None
|
||||
and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register using
|
||||
DAC_SetChannel1Data()/DAC_SetChannel2Data.
|
||||
|
||||
[..] Digital to Analog conversion can be triggered by:
|
||||
(#) External event: EXTI Line 9 (any GPIOx_Pin9) using DAC_Trigger_Ext_IT9.
|
||||
The used pin (GPIOx_Pin9) must be configured in input mode.
|
||||
(#) Timers TRGO: TIM2, TIM4, TIM6, TIM7 and TIM9
|
||||
(DAC_Trigger_T2_TRGO, DAC_Trigger_T4_TRGO...).
|
||||
The timer TRGO event should be selected using TIM_SelectOutputTrigger()
|
||||
(#) Software using DAC_Trigger_Software.
|
||||
|
||||
[..] Each DAC channel integrates an output buffer that can be used to
|
||||
reduce the output impedance, and to drive external loads directly
|
||||
without having to add an external operational amplifier.
|
||||
To enable, the output buffer use
|
||||
DAC_InitStructure.DAC_OutputBuffer = DAC_OutputBuffer_Enable;
|
||||
|
||||
[..] Refer to the device datasheet for more details about output impedance
|
||||
value with and without output buffer.
|
||||
|
||||
[..] Both DAC channels can be used to generate:
|
||||
(#) Noise wave using DAC_WaveGeneration_Noise
|
||||
(#) Triangle wave using DAC_WaveGeneration_Triangle
|
||||
|
||||
[..] Wave generation can be disabled using DAC_WaveGeneration_None.
|
||||
|
||||
[..] The DAC data format can be:
|
||||
(#) 8-bit right alignment using DAC_Align_8b_R
|
||||
(#) 12-bit left alignment using DAC_Align_12b_L
|
||||
(#) 12-bit right alignment using DAC_Align_12b_R
|
||||
|
||||
[..] The analog output voltage on each DAC channel pin is determined
|
||||
by the following equation: DAC_OUTx = VREF+ * DOR / 4095
|
||||
with DOR is the Data Output Register.
|
||||
VEF+ is the input voltage reference (refer to the device datasheet)
|
||||
e.g. To set DAC_OUT1 to 0.7V, use
|
||||
DAC_SetChannel1Data(DAC_Align_12b_R, 868);
|
||||
Assuming that VREF+ = 3.3, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V.
|
||||
|
||||
[..] A DMA1 request can be generated when an external trigger (but not
|
||||
a software trigger) occurs if DMA1 requests are enabled using
|
||||
DAC_DMACmd()
|
||||
[..] DMA1 requests are mapped as following:
|
||||
(#) DAC channel1 is mapped on DMA1 channel3 which must be already
|
||||
configured.
|
||||
(#) DAC channel2 is mapped on DMA1 channel4 which must be already
|
||||
configured.
|
||||
|
||||
##### How to use this driver #####
|
||||
===============================================================================
|
||||
[..]
|
||||
(+) DAC APB clock must be enabled to get write access to DAC registers using
|
||||
RCC_APB1PeriphClockCmd(RCC_APB1Periph_DAC, ENABLE)
|
||||
(+) Configure DAC_OUTx (DAC_OUT1: PA4, DAC_OUT2: PA5) in analog mode.
|
||||
(+) Configure the DAC channel using DAC_Init()
|
||||
(+) Enable the DAC channel using DAC_Cmd()
|
||||
|
||||
@endverbatim
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32l1xx_dac.h"
|
||||
#include "stm32l1xx_rcc.h"
|
||||
|
||||
/** @addtogroup STM32L1xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DAC
|
||||
* @brief DAC driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* CR register Mask */
|
||||
#define CR_CLEAR_MASK ((uint32_t)0x00000FFE)
|
||||
|
||||
/* DAC Dual Channels SWTRIG masks */
|
||||
#define DUAL_SWTRIG_SET ((uint32_t)0x00000003)
|
||||
#define DUAL_SWTRIG_RESET ((uint32_t)0xFFFFFFFC)
|
||||
|
||||
/* DHR registers offsets */
|
||||
#define DHR12R1_OFFSET ((uint32_t)0x00000008)
|
||||
#define DHR12R2_OFFSET ((uint32_t)0x00000014)
|
||||
#define DHR12RD_OFFSET ((uint32_t)0x00000020)
|
||||
|
||||
/* DOR register offset */
|
||||
#define DOR_OFFSET ((uint32_t)0x0000002C)
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DAC_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_Group1 DAC channels configuration
|
||||
* @brief DAC channels configuration: trigger, output buffer, data format.
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### DAC channels configuration: trigger, output buffer, data format #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the DAC peripheral registers to their default reset values.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_DeInit(void)
|
||||
{
|
||||
/* Enable DAC reset state */
|
||||
RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, ENABLE);
|
||||
/* Release DAC from reset state */
|
||||
RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, DISABLE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the DAC peripheral according to the specified
|
||||
* parameters in the DAC_InitStruct.
|
||||
* @param DAC_Channel: the selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Channel_1: DAC Channel1 selected.
|
||||
* @arg DAC_Channel_2: DAC Channel2 selected.
|
||||
* @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure that
|
||||
* contains the configuration information for the specified DAC channel.
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct)
|
||||
{
|
||||
uint32_t tmpreg1 = 0, tmpreg2 = 0;
|
||||
|
||||
/* Check the DAC parameters */
|
||||
assert_param(IS_DAC_CHANNEL(DAC_Channel));
|
||||
assert_param(IS_DAC_TRIGGER(DAC_InitStruct->DAC_Trigger));
|
||||
assert_param(IS_DAC_GENERATE_WAVE(DAC_InitStruct->DAC_WaveGeneration));
|
||||
assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude));
|
||||
assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_InitStruct->DAC_OutputBuffer));
|
||||
|
||||
/*---------------------------- DAC CR Configuration --------------------------*/
|
||||
/* Get the DAC CR value */
|
||||
tmpreg1 = DAC->CR;
|
||||
/* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */
|
||||
tmpreg1 &= ~(CR_CLEAR_MASK << DAC_Channel);
|
||||
/* Configure for the selected DAC channel: buffer output, trigger, wave generation,
|
||||
mask/amplitude for wave generation */
|
||||
/* Set TSELx and TENx bits according to DAC_Trigger value */
|
||||
/* Set WAVEx bits according to DAC_WaveGeneration value */
|
||||
/* Set MAMPx bits according to DAC_LFSRUnmask_TriangleAmplitude value */
|
||||
/* Set BOFFx bit according to DAC_OutputBuffer value */
|
||||
tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration |
|
||||
DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | DAC_InitStruct->DAC_OutputBuffer);
|
||||
/* Calculate CR register value depending on DAC_Channel */
|
||||
tmpreg1 |= tmpreg2 << DAC_Channel;
|
||||
/* Write to DAC CR */
|
||||
DAC->CR = tmpreg1;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Fills each DAC_InitStruct member with its default value.
|
||||
* @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure which will
|
||||
* be initialized.
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct)
|
||||
{
|
||||
/*--------------- Reset DAC init structure parameters values -----------------*/
|
||||
/* Initialize the DAC_Trigger member */
|
||||
DAC_InitStruct->DAC_Trigger = DAC_Trigger_None;
|
||||
/* Initialize the DAC_WaveGeneration member */
|
||||
DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None;
|
||||
/* Initialize the DAC_LFSRUnmask_TriangleAmplitude member */
|
||||
DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0;
|
||||
/* Initialize the DAC_OutputBuffer member */
|
||||
DAC_InitStruct->DAC_OutputBuffer = DAC_OutputBuffer_Enable;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the specified DAC channel.
|
||||
* @param DAC_Channel: The selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Channel_1: DAC Channel1 selected
|
||||
* @arg DAC_Channel_2: DAC Channel2 selected
|
||||
* @param NewState: new state of the DAC channel.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @note When the DAC channel is enabled the trigger source can no more
|
||||
* be modified.
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL(DAC_Channel));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the selected DAC channel */
|
||||
DAC->CR |= (DAC_CR_EN1 << DAC_Channel);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the selected DAC channel */
|
||||
DAC->CR &= (~(DAC_CR_EN1 << DAC_Channel));
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the selected DAC channel software trigger.
|
||||
* @param DAC_Channel: the selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Channel_1: DAC Channel1 selected
|
||||
* @arg DAC_Channel_2: DAC Channel2 selected
|
||||
* @param NewState: new state of the selected DAC channel software trigger.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL(DAC_Channel));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable software trigger for the selected DAC channel */
|
||||
DAC->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable software trigger for the selected DAC channel */
|
||||
DAC->SWTRIGR &= ~((uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4));
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables simultaneously the two DAC channels software
|
||||
* triggers.
|
||||
* @param NewState: new state of the DAC channels software triggers.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_DualSoftwareTriggerCmd(FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable software trigger for both DAC channels */
|
||||
DAC->SWTRIGR |= DUAL_SWTRIG_SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable software trigger for both DAC channels */
|
||||
DAC->SWTRIGR &= DUAL_SWTRIG_RESET;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the selected DAC channel wave generation.
|
||||
* @param DAC_Channel: the selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Channel_1: DAC Channel1 selected
|
||||
* @arg DAC_Channel_2: DAC Channel2 selected
|
||||
* @param DAC_Wave: Specifies the wave type to enable or disable.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Wave_Noise: noise wave generation
|
||||
* @arg DAC_Wave_Triangle: triangle wave generation
|
||||
* @param NewState: new state of the selected DAC channel wave generation.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @note
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL(DAC_Channel));
|
||||
assert_param(IS_DAC_WAVE(DAC_Wave));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the selected wave generation for the selected DAC channel */
|
||||
DAC->CR |= DAC_Wave << DAC_Channel;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the selected wave generation for the selected DAC channel */
|
||||
DAC->CR &= ~(DAC_Wave << DAC_Channel);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the specified data holding register value for DAC channel1.
|
||||
* @param DAC_Align: Specifies the data alignment for DAC channel1.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Align_8b_R: 8bit right data alignment selected
|
||||
* @arg DAC_Align_12b_L: 12bit left data alignment selected
|
||||
* @arg DAC_Align_12b_R: 12bit right data alignment selected
|
||||
* @param Data : Data to be loaded in the selected data holding register.
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data)
|
||||
{
|
||||
__IO uint32_t tmp = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_ALIGN(DAC_Align));
|
||||
assert_param(IS_DAC_DATA(Data));
|
||||
|
||||
tmp = (uint32_t)DAC_BASE;
|
||||
tmp += DHR12R1_OFFSET + DAC_Align;
|
||||
|
||||
/* Set the DAC channel1 selected data holding register */
|
||||
*(__IO uint32_t *) tmp = Data;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the specified data holding register value for DAC channel2.
|
||||
* @param DAC_Align: Specifies the data alignment for DAC channel2.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Align_8b_R: 8bit right data alignment selected
|
||||
* @arg DAC_Align_12b_L: 12bit left data alignment selected
|
||||
* @arg DAC_Align_12b_R: 12bit right data alignment selected
|
||||
* @param Data : Data to be loaded in the selected data holding register.
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data)
|
||||
{
|
||||
__IO uint32_t tmp = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_ALIGN(DAC_Align));
|
||||
assert_param(IS_DAC_DATA(Data));
|
||||
|
||||
tmp = (uint32_t)DAC_BASE;
|
||||
tmp += DHR12R2_OFFSET + DAC_Align;
|
||||
|
||||
/* Set the DAC channel2 selected data holding register */
|
||||
*(__IO uint32_t *)tmp = Data;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the specified data holding register value for dual channel DAC.
|
||||
* @param DAC_Align: Specifies the data alignment for dual channel DAC.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Align_8b_R: 8bit right data alignment selected
|
||||
* @arg DAC_Align_12b_L: 12bit left data alignment selected
|
||||
* @arg DAC_Align_12b_R: 12bit right data alignment selected
|
||||
* @param Data2: Data for DAC Channel2 to be loaded in the selected data
|
||||
* holding register.
|
||||
* @param Data1: Data for DAC Channel1 to be loaded in the selected data
|
||||
* holding register.
|
||||
* @note In dual mode, a unique register access is required to write in both
|
||||
* DAC channels at the same time.
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1)
|
||||
{
|
||||
uint32_t data = 0, tmp = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_ALIGN(DAC_Align));
|
||||
assert_param(IS_DAC_DATA(Data1));
|
||||
assert_param(IS_DAC_DATA(Data2));
|
||||
|
||||
/* Calculate and set dual DAC data holding register value */
|
||||
if (DAC_Align == DAC_Align_8b_R)
|
||||
{
|
||||
data = ((uint32_t)Data2 << 8) | Data1;
|
||||
}
|
||||
else
|
||||
{
|
||||
data = ((uint32_t)Data2 << 16) | Data1;
|
||||
}
|
||||
|
||||
tmp = (uint32_t)DAC_BASE;
|
||||
tmp += DHR12RD_OFFSET + DAC_Align;
|
||||
|
||||
/* Set the dual DAC selected data holding register */
|
||||
*(__IO uint32_t *)tmp = data;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the last data output value of the selected DAC channel.
|
||||
* @param DAC_Channel: the selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Channel_1: DAC Channel1 selected
|
||||
* @arg DAC_Channel_2: DAC Channel2 selected
|
||||
* @retval The selected DAC channel data output value.
|
||||
*/
|
||||
uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel)
|
||||
{
|
||||
__IO uint32_t tmp = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL(DAC_Channel));
|
||||
|
||||
tmp = (uint32_t) DAC_BASE ;
|
||||
tmp += DOR_OFFSET + ((uint32_t)DAC_Channel >> 2);
|
||||
|
||||
/* Returns the DAC channel data output register value */
|
||||
return (uint16_t) (*(__IO uint32_t*) tmp);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_Group2 DMA management functions
|
||||
* @brief DMA management functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### DMA management functions #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the specified DAC channel DMA request.
|
||||
* When enabled DMA1 is generated when an external trigger (EXTI Line9,
|
||||
* TIM2, TIM4, TIM6, TIM7 or TIM9 but not a software trigger) occurs.
|
||||
* @param DAC_Channel: the selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Channel_1: DAC Channel1 selected
|
||||
* @arg DAC_Channel_2: DAC Channel2 selected
|
||||
* @param NewState: new state of the selected DAC channel DMA request.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @note The DAC channel1 (channel2) is mapped on DMA1 channel3 (channel4) which
|
||||
* must be already configured.
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL(DAC_Channel));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the selected DAC channel DMA request */
|
||||
DAC->CR |= (DAC_CR_DMAEN1 << DAC_Channel);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the selected DAC channel DMA request */
|
||||
DAC->CR &= (~(DAC_CR_DMAEN1 << DAC_Channel));
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DAC_Group3 Interrupts and flags management functions
|
||||
* @brief Interrupts and flags management functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Interrupts and flags management functions #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the specified DAC interrupts.
|
||||
* @param DAC_Channel: the selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Channel_1: DAC Channel1 selected
|
||||
* @arg DAC_Channel_2: DAC Channel2 selected
|
||||
* @param DAC_IT: specifies the DAC interrupt sources to be enabled or disabled.
|
||||
* This parameter can be the following value:
|
||||
* @arg DAC_IT_DMAUDR: DMA underrun interrupt mask
|
||||
* @note The DMA underrun occurs when a second external trigger arrives before
|
||||
* the acknowledgement for the first external trigger is received (first request).
|
||||
* @param NewState: new state of the specified DAC interrupts.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL(DAC_Channel));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
assert_param(IS_DAC_IT(DAC_IT));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the selected DAC interrupts */
|
||||
DAC->CR |= (DAC_IT << DAC_Channel);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the selected DAC interrupts */
|
||||
DAC->CR &= (~(uint32_t)(DAC_IT << DAC_Channel));
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified DAC flag is set or not.
|
||||
* @param DAC_Channel: thee selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Channel_1: DAC Channel1 selected
|
||||
* @arg DAC_Channel_2: DAC Channel2 selected
|
||||
* @param DAC_FLAG: specifies the flag to check.
|
||||
* This parameter can be only of the following value:
|
||||
* @arg DAC_FLAG_DMAUDR: DMA underrun flag
|
||||
* @note The DMA underrun occurs when a second external trigger arrives before
|
||||
* the acknowledgement for the first external trigger is received (first request).
|
||||
* @retval The new state of DAC_FLAG (SET or RESET).
|
||||
*/
|
||||
FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG)
|
||||
{
|
||||
FlagStatus bitstatus = RESET;
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL(DAC_Channel));
|
||||
assert_param(IS_DAC_FLAG(DAC_FLAG));
|
||||
|
||||
/* Check the status of the specified DAC flag */
|
||||
if ((DAC->SR & (DAC_FLAG << DAC_Channel)) != (uint8_t)RESET)
|
||||
{
|
||||
/* DAC_FLAG is set */
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* DAC_FLAG is reset */
|
||||
bitstatus = RESET;
|
||||
}
|
||||
/* Return the DAC_FLAG status */
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the DAC channel's pending flags.
|
||||
* @param DAC_Channel: the selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Channel_1: DAC Channel1 selected
|
||||
* @arg DAC_Channel_2: DAC Channel2 selected
|
||||
* @param DAC_FLAG: specifies the flag to clear.
|
||||
* This parameter can be the following value:
|
||||
* @arg DAC_FLAG_DMAUDR: DMA underrun flag
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL(DAC_Channel));
|
||||
assert_param(IS_DAC_FLAG(DAC_FLAG));
|
||||
|
||||
/* Clear the selected DAC flags */
|
||||
DAC->SR = (DAC_FLAG << DAC_Channel);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified DAC interrupt has occurred or not.
|
||||
* @param DAC_Channel: the selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Channel_1: DAC Channel1 selected
|
||||
* @arg DAC_Channel_2: DAC Channel2 selected
|
||||
* @param DAC_IT: specifies the DAC interrupt source to check.
|
||||
* This parameter can be the following values:
|
||||
* @arg DAC_IT_DMAUDR: DMA underrun interrupt mask
|
||||
* @note The DMA underrun occurs when a second external trigger arrives before
|
||||
* the acknowledgement for the first external trigger is received (first request).
|
||||
* @retval The new state of DAC_IT (SET or RESET).
|
||||
*/
|
||||
ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT)
|
||||
{
|
||||
ITStatus bitstatus = RESET;
|
||||
uint32_t enablestatus = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL(DAC_Channel));
|
||||
assert_param(IS_DAC_IT(DAC_IT));
|
||||
|
||||
/* Get the DAC_IT enable bit status */
|
||||
enablestatus = (DAC->CR & (DAC_IT << DAC_Channel)) ;
|
||||
|
||||
/* Check the status of the specified DAC interrupt */
|
||||
if (((DAC->SR & (DAC_IT << DAC_Channel)) != (uint32_t)RESET) && enablestatus)
|
||||
{
|
||||
/* DAC_IT is set */
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* DAC_IT is reset */
|
||||
bitstatus = RESET;
|
||||
}
|
||||
/* Return the DAC_IT status */
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the DAC channel's interrupt pending bits.
|
||||
* @param DAC_Channel: the selected DAC channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DAC_Channel_1: DAC Channel1 selected
|
||||
* @arg DAC_Channel_2: DAC Channel2 selected
|
||||
* @param DAC_IT: specifies the DAC interrupt pending bit to clear.
|
||||
* This parameter can be the following values:
|
||||
* @arg DAC_IT_DMAUDR: DMA underrun interrupt mask
|
||||
* @retval None
|
||||
*/
|
||||
void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DAC_CHANNEL(DAC_Channel));
|
||||
assert_param(IS_DAC_IT(DAC_IT));
|
||||
|
||||
/* Clear the selected DAC interrupt pending bits */
|
||||
DAC->SR = (DAC_IT << DAC_Channel);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,181 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32l1xx_dbgmcu.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.1
|
||||
* @date 05-March-2012
|
||||
* @brief This file provides all the DBGMCU firmware functions.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32l1xx_dbgmcu.h"
|
||||
|
||||
/** @addtogroup STM32L1xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DBGMCU
|
||||
* @brief DBGMCU driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF)
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup DBGMCU_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Returns the device revision identifier.
|
||||
* @param None
|
||||
* @retval Device revision identifier
|
||||
*/
|
||||
uint32_t DBGMCU_GetREVID(void)
|
||||
{
|
||||
return(DBGMCU->IDCODE >> 16);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the device identifier.
|
||||
* @param None
|
||||
* @retval Device identifier
|
||||
*/
|
||||
uint32_t DBGMCU_GetDEVID(void)
|
||||
{
|
||||
return(DBGMCU->IDCODE & IDCODE_DEVID_MASK);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures low power mode behavior when the MCU is in Debug mode.
|
||||
* @param DBGMCU_Periph: specifies the low power mode.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DBGMCU_SLEEP: Keep debugger connection during SLEEP mode
|
||||
* @arg DBGMCU_STOP: Keep debugger connection during STOP mode
|
||||
* @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode
|
||||
* @param NewState: new state of the specified low power mode in Debug mode.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
DBGMCU->CR |= DBGMCU_Periph;
|
||||
}
|
||||
else
|
||||
{
|
||||
DBGMCU->CR &= ~DBGMCU_Periph;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Configures APB1 peripheral behavior when the MCU is in Debug mode.
|
||||
* @param DBGMCU_Periph: specifies the APB1 peripheral.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted
|
||||
* @arg DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted
|
||||
* @arg DBGMCU_TIM4_STOP: TIM4 counter stopped when Core is halted
|
||||
* @arg DBGMCU_TIM5_STOP: TIM5 counter stopped when Core is halted
|
||||
* @arg DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted
|
||||
* @arg DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted
|
||||
* @arg DBGMCU_RTC_STOP:
|
||||
* + On STM32L1xx Medium-density devices: RTC Wakeup counter stopped when
|
||||
* Core is halted.
|
||||
* + On STM32L1xx High-density and Medium-density Plus devices: RTC Calendar
|
||||
* and Wakeup counter stopped when Core is halted.
|
||||
* @arg DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted
|
||||
* @arg DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted
|
||||
* @arg DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when Core is
|
||||
* halted
|
||||
* @arg DBGMCU_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped when Core is
|
||||
* halted
|
||||
* @param NewState: new state of the specified APB1 peripheral in Debug mode.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DBGMCU_APB1PERIPH(DBGMCU_Periph));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
DBGMCU->APB1FZ |= DBGMCU_Periph;
|
||||
}
|
||||
else
|
||||
{
|
||||
DBGMCU->APB1FZ &= ~DBGMCU_Periph;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures APB2 peripheral behavior when the MCU is in Debug mode.
|
||||
* @param DBGMCU_Periph: specifies the APB2 peripheral.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DBGMCU_TIM9_STOP: TIM9 counter stopped when Core is halted
|
||||
* @arg DBGMCU_TIM10_STOP: TIM10 counter stopped when Core is halted
|
||||
* @arg DBGMCU_TIM11_STOP: TIM11 counter stopped when Core is halted
|
||||
* @param NewState: new state of the specified APB2 peripheral in Debug mode.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DBGMCU_APB2PERIPH(DBGMCU_Periph));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
DBGMCU->APB2FZ |= DBGMCU_Periph;
|
||||
}
|
||||
else
|
||||
{
|
||||
DBGMCU->APB2FZ &= ~DBGMCU_Periph;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,866 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32l1xx_dma.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.1
|
||||
* @date 05-March-2012
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the Direct Memory Access controller (DMA):
|
||||
* + Initialization and Configuration
|
||||
* + Data Counter
|
||||
* + Interrupts and flags management
|
||||
*
|
||||
* @verbatim
|
||||
==============================================================================
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
(#) Enable The DMA controller clock using
|
||||
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE) function for DMA1 or
|
||||
using RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA2, ENABLE) function for DMA2.
|
||||
(#) Enable and configure the peripheral to be connected to the DMA channel
|
||||
(except for internal SRAM / FLASH memories: no initialization is
|
||||
necessary).
|
||||
(#) For a given Channel, program the Source and Destination addresses,
|
||||
the transfer Direction, the Buffer Size, the Peripheral and Memory
|
||||
Incrementation mode and Data Size, the Circular or Normal mode,
|
||||
the channel transfer Priority and the Memory-to-Memory transfer
|
||||
mode (if needed) using the DMA_Init() function.
|
||||
(#) Enable the NVIC and the corresponding interrupt(s) using the function
|
||||
DMA_ITConfig() if you need to use DMA interrupts.
|
||||
(#) Enable the DMA channel using the DMA_Cmd() function.
|
||||
(#) Activate the needed channel Request using PPP_DMACmd() function for
|
||||
any PPP peripheral except internal SRAM and FLASH (ie. SPI, USART ...)
|
||||
The function allowing this operation is provided in each PPP peripheral
|
||||
driver (ie. SPI_DMACmd for SPI peripheral).
|
||||
(#) Optionally, you can configure the number of data to be transferred
|
||||
when the channel is disabled (ie. after each Transfer Complete event
|
||||
or when a Transfer Error occurs) using the function DMA_SetCurrDataCounter().
|
||||
And you can get the number of remaining data to be transferred using
|
||||
the function DMA_GetCurrDataCounter() at run time (when the DMA channel is
|
||||
enabled and running).
|
||||
(#) To control DMA events you can use one of the following two methods:
|
||||
(##) Check on DMA channel flags using the function DMA_GetFlagStatus().
|
||||
(##) Use DMA interrupts through the function DMA_ITConfig() at initialization
|
||||
phase and DMA_GetITStatus() function into interrupt routines in
|
||||
communication phase.
|
||||
After checking on a flag you should clear it using DMA_ClearFlag()
|
||||
function. And after checking on an interrupt event you should
|
||||
clear it using DMA_ClearITPendingBit() function.
|
||||
@endverbatim
|
||||
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32l1xx_dma.h"
|
||||
#include "stm32l1xx_rcc.h"
|
||||
|
||||
/** @addtogroup STM32L1xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DMA
|
||||
* @brief DMA driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
|
||||
/* DMA1 Channelx interrupt pending bit masks */
|
||||
#define DMA1_CHANNEL1_IT_MASK ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1))
|
||||
#define DMA1_CHANNEL2_IT_MASK ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2))
|
||||
#define DMA1_CHANNEL3_IT_MASK ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3))
|
||||
#define DMA1_CHANNEL4_IT_MASK ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4))
|
||||
#define DMA1_CHANNEL5_IT_MASK ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5))
|
||||
#define DMA1_CHANNEL6_IT_MASK ((uint32_t)(DMA_ISR_GIF6 | DMA_ISR_TCIF6 | DMA_ISR_HTIF6 | DMA_ISR_TEIF6))
|
||||
#define DMA1_CHANNEL7_IT_MASK ((uint32_t)(DMA_ISR_GIF7 | DMA_ISR_TCIF7 | DMA_ISR_HTIF7 | DMA_ISR_TEIF7))
|
||||
|
||||
/* DMA2 Channelx interrupt pending bit masks */
|
||||
#define DMA2_CHANNEL1_IT_MASK ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1))
|
||||
#define DMA2_CHANNEL2_IT_MASK ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2))
|
||||
#define DMA2_CHANNEL3_IT_MASK ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3))
|
||||
#define DMA2_CHANNEL4_IT_MASK ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4))
|
||||
#define DMA2_CHANNEL5_IT_MASK ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5))
|
||||
|
||||
/* DMA FLAG mask */
|
||||
#define FLAG_MASK ((uint32_t)0x10000000)
|
||||
|
||||
/* DMA registers Masks */
|
||||
#define CCR_CLEAR_MASK ((uint32_t)0xFFFF800F)
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
|
||||
/** @defgroup DMA_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Group1 Initialization and Configuration functions
|
||||
* @brief Initialization and Configuration functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Initialization and Configuration functions #####
|
||||
===============================================================================
|
||||
[..] This subsection provides functions allowing to initialize the DMA channel
|
||||
source and destination addresses, incrementation and data sizes, transfer
|
||||
direction, buffer size, circular/normal mode selection, memory-to-memory
|
||||
mode selection and channel priority value.
|
||||
[..] The DMA_Init() function follows the DMA configuration procedures as described
|
||||
in reference manual (RM0038).
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the DMAy Channelx registers to their default reset
|
||||
* values.
|
||||
* @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and x can be
|
||||
* 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
|
||||
* @retval None
|
||||
*/
|
||||
void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
|
||||
|
||||
/* Disable the selected DMAy Channelx */
|
||||
DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN);
|
||||
|
||||
/* Reset DMAy Channelx control register */
|
||||
DMAy_Channelx->CCR = 0;
|
||||
|
||||
/* Reset DMAy Channelx remaining bytes register */
|
||||
DMAy_Channelx->CNDTR = 0;
|
||||
|
||||
/* Reset DMAy Channelx peripheral address register */
|
||||
DMAy_Channelx->CPAR = 0;
|
||||
|
||||
/* Reset DMAy Channelx memory address register */
|
||||
DMAy_Channelx->CMAR = 0;
|
||||
|
||||
if (DMAy_Channelx == DMA1_Channel1)
|
||||
{
|
||||
/* Reset interrupt pending bits for DMA1 Channel1 */
|
||||
DMA1->IFCR |= DMA1_CHANNEL1_IT_MASK;
|
||||
}
|
||||
else if (DMAy_Channelx == DMA1_Channel2)
|
||||
{
|
||||
/* Reset interrupt pending bits for DMA1 Channel2 */
|
||||
DMA1->IFCR |= DMA1_CHANNEL2_IT_MASK;
|
||||
}
|
||||
else if (DMAy_Channelx == DMA1_Channel3)
|
||||
{
|
||||
/* Reset interrupt pending bits for DMA1 Channel3 */
|
||||
DMA1->IFCR |= DMA1_CHANNEL3_IT_MASK;
|
||||
}
|
||||
else if (DMAy_Channelx == DMA1_Channel4)
|
||||
{
|
||||
/* Reset interrupt pending bits for DMA1 Channel4 */
|
||||
DMA1->IFCR |= DMA1_CHANNEL4_IT_MASK;
|
||||
}
|
||||
else if (DMAy_Channelx == DMA1_Channel5)
|
||||
{
|
||||
/* Reset interrupt pending bits for DMA1 Channel5 */
|
||||
DMA1->IFCR |= DMA1_CHANNEL5_IT_MASK;
|
||||
}
|
||||
else if (DMAy_Channelx == DMA1_Channel6)
|
||||
{
|
||||
/* Reset interrupt pending bits for DMA1 Channel6 */
|
||||
DMA1->IFCR |= DMA1_CHANNEL6_IT_MASK;
|
||||
}
|
||||
else if (DMAy_Channelx == DMA1_Channel7)
|
||||
{
|
||||
/* Reset interrupt pending bits for DMA1 Channel7 */
|
||||
DMA1->IFCR |= DMA1_CHANNEL7_IT_MASK;
|
||||
}
|
||||
else if (DMAy_Channelx == DMA2_Channel1)
|
||||
{
|
||||
/* Reset interrupt pending bits for DMA2 Channel1 */
|
||||
DMA2->IFCR |= DMA2_CHANNEL1_IT_MASK;
|
||||
}
|
||||
else if (DMAy_Channelx == DMA2_Channel2)
|
||||
{
|
||||
/* Reset interrupt pending bits for DMA2 Channel2 */
|
||||
DMA2->IFCR |= DMA2_CHANNEL2_IT_MASK;
|
||||
}
|
||||
else if (DMAy_Channelx == DMA2_Channel3)
|
||||
{
|
||||
/* Reset interrupt pending bits for DMA2 Channel3 */
|
||||
DMA2->IFCR |= DMA2_CHANNEL3_IT_MASK;
|
||||
}
|
||||
else if (DMAy_Channelx == DMA2_Channel4)
|
||||
{
|
||||
/* Reset interrupt pending bits for DMA2 Channel4 */
|
||||
DMA2->IFCR |= DMA2_CHANNEL4_IT_MASK;
|
||||
}
|
||||
else
|
||||
{
|
||||
if (DMAy_Channelx == DMA2_Channel5)
|
||||
{
|
||||
/* Reset interrupt pending bits for DMA2 Channel5 */
|
||||
DMA2->IFCR |= DMA2_CHANNEL5_IT_MASK;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the DMAy Channelx according to the specified
|
||||
* parameters in the DMA_InitStruct.
|
||||
* @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and x can be
|
||||
* 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
|
||||
* @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure that
|
||||
* contains the configuration information for the specified DMA Channel.
|
||||
* @retval None
|
||||
*/
|
||||
void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct)
|
||||
{
|
||||
uint32_t tmpreg = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
|
||||
assert_param(IS_DMA_DIR(DMA_InitStruct->DMA_DIR));
|
||||
assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize));
|
||||
assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc));
|
||||
assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc));
|
||||
assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize));
|
||||
assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize));
|
||||
assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode));
|
||||
assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority));
|
||||
assert_param(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M));
|
||||
|
||||
/*--------------------------- DMAy Channelx CCR Configuration -----------------*/
|
||||
/* Get the DMAy_Channelx CCR value */
|
||||
tmpreg = DMAy_Channelx->CCR;
|
||||
/* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */
|
||||
tmpreg &= CCR_CLEAR_MASK;
|
||||
/* Configure DMAy Channelx: data transfer, data size, priority level and mode */
|
||||
/* Set DIR bit according to DMA_DIR value */
|
||||
/* Set CIRC bit according to DMA_Mode value */
|
||||
/* Set PINC bit according to DMA_PeripheralInc value */
|
||||
/* Set MINC bit according to DMA_MemoryInc value */
|
||||
/* Set PSIZE bits according to DMA_PeripheralDataSize value */
|
||||
/* Set MSIZE bits according to DMA_MemoryDataSize value */
|
||||
/* Set PL bits according to DMA_Priority value */
|
||||
/* Set the MEM2MEM bit according to DMA_M2M value */
|
||||
tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode |
|
||||
DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |
|
||||
DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize |
|
||||
DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M;
|
||||
|
||||
/* Write to DMAy Channelx CCR */
|
||||
DMAy_Channelx->CCR = tmpreg;
|
||||
|
||||
/*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/
|
||||
/* Write to DMAy Channelx CNDTR */
|
||||
DMAy_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize;
|
||||
|
||||
/*--------------------------- DMAy Channelx CPAR Configuration ----------------*/
|
||||
/* Write to DMAy Channelx CPAR */
|
||||
DMAy_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr;
|
||||
|
||||
/*--------------------------- DMAy Channelx CMAR Configuration ----------------*/
|
||||
/* Write to DMAy Channelx CMAR */
|
||||
DMAy_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Fills each DMA_InitStruct member with its default value.
|
||||
* @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure which will
|
||||
* be initialized.
|
||||
* @retval None
|
||||
*/
|
||||
void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct)
|
||||
{
|
||||
/*-------------- Reset DMA init structure parameters values ------------------*/
|
||||
/* Initialize the DMA_PeripheralBaseAddr member */
|
||||
DMA_InitStruct->DMA_PeripheralBaseAddr = 0;
|
||||
/* Initialize the DMA_MemoryBaseAddr member */
|
||||
DMA_InitStruct->DMA_MemoryBaseAddr = 0;
|
||||
/* Initialize the DMA_DIR member */
|
||||
DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC;
|
||||
/* Initialize the DMA_BufferSize member */
|
||||
DMA_InitStruct->DMA_BufferSize = 0;
|
||||
/* Initialize the DMA_PeripheralInc member */
|
||||
DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable;
|
||||
/* Initialize the DMA_MemoryInc member */
|
||||
DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable;
|
||||
/* Initialize the DMA_PeripheralDataSize member */
|
||||
DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
|
||||
/* Initialize the DMA_MemoryDataSize member */
|
||||
DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
|
||||
/* Initialize the DMA_Mode member */
|
||||
DMA_InitStruct->DMA_Mode = DMA_Mode_Normal;
|
||||
/* Initialize the DMA_Priority member */
|
||||
DMA_InitStruct->DMA_Priority = DMA_Priority_Low;
|
||||
/* Initialize the DMA_M2M member */
|
||||
DMA_InitStruct->DMA_M2M = DMA_M2M_Disable;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the specified DMAy Channelx.
|
||||
* @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and x can be
|
||||
* 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
|
||||
* @param NewState: new state of the DMAy Channelx.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the selected DMAy Channelx */
|
||||
DMAy_Channelx->CCR |= DMA_CCR1_EN;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the selected DMAy Channelx */
|
||||
DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR1_EN);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Group2 Data Counter functions
|
||||
* @brief Data Counter functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Data Counter functions #####
|
||||
===============================================================================
|
||||
[..] This subsection provides function allowing to configure and read the buffer
|
||||
size (number of data to be transferred).The DMA data counter can be written
|
||||
only when the DMA channel is disabled (ie. after transfer complete event).
|
||||
[..] The following function can be used to write the Channel data counter value:
|
||||
(+) void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t
|
||||
DataNumber).
|
||||
-@- It is advised to use this function rather than DMA_Init() in situations
|
||||
where only the Data buffer needs to be reloaded.
|
||||
[..] The DMA data counter can be read to indicate the number of remaining transfers
|
||||
for the relative DMA channel. This counter is decremented at the end of each
|
||||
data transfer and when the transfer is complete:
|
||||
(+) If Normal mode is selected: the counter is set to 0.
|
||||
(+) If Circular mode is selected: the counter is reloaded with the initial
|
||||
value(configured before enabling the DMA channel).
|
||||
[..] The following function can be used to read the Channel data counter value:
|
||||
(+) uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx).
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Sets the number of data units in the current DMAy Channelx transfer.
|
||||
* @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and x can be
|
||||
* 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
|
||||
* @param DataNumber: The number of data units in the current DMAy Channelx
|
||||
* transfer.
|
||||
* @note This function can only be used when the DMAy_Channelx is disabled.
|
||||
* @retval None.
|
||||
*/
|
||||
void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
|
||||
|
||||
/*--------------------------- DMAy Channelx CNDTR Configuration ---------------*/
|
||||
/* Write to DMAy Channelx CNDTR */
|
||||
DMAy_Channelx->CNDTR = DataNumber;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the number of remaining data units in the current
|
||||
* DMAy Channelx transfer.
|
||||
* @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and x can be
|
||||
* 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
|
||||
* @retval The number of remaining data units in the current DMAy Channelx
|
||||
* transfer.
|
||||
*/
|
||||
uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
|
||||
/* Return the number of remaining data units for DMAy Channelx */
|
||||
return ((uint16_t)(DMAy_Channelx->CNDTR));
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_Group3 Interrupts and flags management functions
|
||||
* @brief Interrupts and flags management functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Interrupts and flags management functions #####
|
||||
===============================================================================
|
||||
[..] This subsection provides functions allowing to configure the DMA Interrupts
|
||||
sources and check or clear the flags or pending bits status.
|
||||
The user should identify which mode will be used in his application to manage
|
||||
the DMA controller events: Polling mode or Interrupt mode.
|
||||
*** Polling Mode ***
|
||||
====================
|
||||
[..] Each DMA channel can be managed through 4 event Flags:(y : DMA Controller
|
||||
number x : DMA channel number ).
|
||||
(#) DMAy_FLAG_TCx : to indicate that a Transfer Complete event occurred.
|
||||
(#) DMAy_FLAG_HTx : to indicate that a Half-Transfer Complete event occurred.
|
||||
(#) DMAy_FLAG_TEx : to indicate that a Transfer Error occurred.
|
||||
(#) DMAy_FLAG_GLx : to indicate that at least one of the events described
|
||||
above occurred.
|
||||
-@- Clearing DMAy_FLAG_GLx results in clearing all other pending flags of the
|
||||
same channel (DMAy_FLAG_TCx, DMAy_FLAG_HTx and DMAy_FLAG_TEx).
|
||||
[..]In this Mode it is advised to use the following functions:
|
||||
(+) FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG);
|
||||
(+) void DMA_ClearFlag(uint32_t DMA_FLAG);
|
||||
|
||||
*** Interrupt Mode ***
|
||||
======================
|
||||
[..] Each DMA channel can be managed through 4 Interrupts:
|
||||
(+) Interrupt Source
|
||||
(##) DMA_IT_TC: specifies the interrupt source for the Transfer Complete
|
||||
event.
|
||||
(##) DMA_IT_HT : specifies the interrupt source for the Half-transfer Complete
|
||||
event.
|
||||
(##) DMA_IT_TE : specifies the interrupt source for the transfer errors event.
|
||||
(##) DMA_IT_GL : to indicate that at least one of the interrupts described
|
||||
above occurred.
|
||||
-@@- Clearing DMA_IT_GL interrupt results in clearing all other interrupts of
|
||||
the same channel (DMA_IT_TCx, DMA_IT_HT and DMA_IT_TE).
|
||||
[..]In this Mode it is advised to use the following functions:
|
||||
(+) void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT,
|
||||
FunctionalState NewState);
|
||||
(+) ITStatus DMA_GetITStatus(uint32_t DMA_IT);
|
||||
(+) void DMA_ClearITPendingBit(uint32_t DMA_IT);
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the specified DMAy Channelx interrupts.
|
||||
* @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and x can be
|
||||
* 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
|
||||
* @param DMA_IT: specifies the DMA interrupts sources to be enabled
|
||||
* or disabled.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg DMA_IT_TC: Transfer complete interrupt mask
|
||||
* @arg DMA_IT_HT: Half transfer interrupt mask
|
||||
* @arg DMA_IT_TE: Transfer error interrupt mask
|
||||
* @param NewState: new state of the specified DMA interrupts.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
|
||||
assert_param(IS_DMA_CONFIG_IT(DMA_IT));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the selected DMA interrupts */
|
||||
DMAy_Channelx->CCR |= DMA_IT;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the selected DMA interrupts */
|
||||
DMAy_Channelx->CCR &= ~DMA_IT;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified DMAy Channelx flag is set or not.
|
||||
* @param DMAy_FLAG: specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.
|
||||
* @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
|
||||
* @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
|
||||
* @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
|
||||
* @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.
|
||||
* @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
|
||||
* @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
|
||||
* @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
|
||||
* @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.
|
||||
* @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
|
||||
* @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
|
||||
* @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
|
||||
* @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.
|
||||
* @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
|
||||
* @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
|
||||
* @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
|
||||
* @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.
|
||||
* @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
|
||||
* @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
|
||||
* @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
|
||||
* @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag.
|
||||
* @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
|
||||
* @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
|
||||
* @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.
|
||||
* @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag.
|
||||
* @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
|
||||
* @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
|
||||
* @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.
|
||||
* @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag.
|
||||
* @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.
|
||||
* @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.
|
||||
* @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag.
|
||||
* @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag.
|
||||
* @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.
|
||||
* @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.
|
||||
* @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag.
|
||||
* @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag.
|
||||
* @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.
|
||||
* @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.
|
||||
* @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag.
|
||||
* @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag.
|
||||
* @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.
|
||||
* @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.
|
||||
* @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag.
|
||||
* @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag.
|
||||
* @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.
|
||||
* @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.
|
||||
* @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag.
|
||||
*
|
||||
* @note
|
||||
* The Global flag (DMAy_FLAG_GLx) is set whenever any of the other flags
|
||||
* relative to the same channel is set (Transfer Complete, Half-transfer
|
||||
* Complete or Transfer Error flags: DMAy_FLAG_TCx, DMAy_FLAG_HTx or
|
||||
* DMAy_FLAG_TEx).
|
||||
*
|
||||
* @retval The new state of DMAy_FLAG (SET or RESET).
|
||||
*/
|
||||
FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG)
|
||||
{
|
||||
FlagStatus bitstatus = RESET;
|
||||
uint32_t tmpreg = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_GET_FLAG(DMAy_FLAG));
|
||||
|
||||
/* Calculate the used DMAy */
|
||||
if ((DMAy_FLAG & FLAG_MASK) == (uint32_t)RESET)
|
||||
{
|
||||
/* Get DMA1 ISR register value */
|
||||
tmpreg = DMA1->ISR;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Get DMA2 ISR register value */
|
||||
tmpreg = DMA2->ISR;
|
||||
}
|
||||
|
||||
/* Check the status of the specified DMAy flag */
|
||||
if ((tmpreg & DMAy_FLAG) != (uint32_t)RESET)
|
||||
{
|
||||
/* DMAy_FLAG is set */
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* DMAy_FLAG is reset */
|
||||
bitstatus = RESET;
|
||||
}
|
||||
|
||||
/* Return the DMAy_FLAG status */
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the DMAy Channelx's pending flags.
|
||||
* @param DMAy_FLAG: specifies the flag to clear.
|
||||
* This parameter can be any combination (for the same DMA) of the following values:
|
||||
* @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.
|
||||
* @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
|
||||
* @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
|
||||
* @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
|
||||
* @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.
|
||||
* @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
|
||||
* @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
|
||||
* @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
|
||||
* @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.
|
||||
* @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
|
||||
* @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
|
||||
* @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
|
||||
* @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.
|
||||
* @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
|
||||
* @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
|
||||
* @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
|
||||
* @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.
|
||||
* @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
|
||||
* @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
|
||||
* @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
|
||||
* @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag.
|
||||
* @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
|
||||
* @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
|
||||
* @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.
|
||||
* @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag.
|
||||
* @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
|
||||
* @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
|
||||
* @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.
|
||||
* @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag.
|
||||
* @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.
|
||||
* @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.
|
||||
* @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag.
|
||||
* @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag.
|
||||
* @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.
|
||||
* @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.
|
||||
* @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag.
|
||||
* @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag.
|
||||
* @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.
|
||||
* @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.
|
||||
* @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag.
|
||||
* @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag.
|
||||
* @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.
|
||||
* @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.
|
||||
* @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag.
|
||||
* @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag.
|
||||
* @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.
|
||||
* @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.
|
||||
* @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag.
|
||||
*
|
||||
* @note
|
||||
* Clearing the Global flag (DMAy_FLAG_GLx) results in clearing all other flags
|
||||
* relative to the same channel (Transfer Complete, Half-transfer Complete and
|
||||
* Transfer Error flags: DMAy_FLAG_TCx, DMAy_FLAG_HTx and DMAy_FLAG_TEx).
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
void DMA_ClearFlag(uint32_t DMAy_FLAG)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_CLEAR_FLAG(DMAy_FLAG));
|
||||
|
||||
if ((DMAy_FLAG & FLAG_MASK) == (uint32_t)RESET)
|
||||
{
|
||||
/* Clear the selected DMAy flags */
|
||||
DMA1->IFCR = DMAy_FLAG;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Clear the selected DMAy flags */
|
||||
DMA2->IFCR = DMAy_FLAG;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified DMAy Channelx interrupt has occurred or not.
|
||||
* @param DMAy_IT: specifies the DMAy interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.
|
||||
* @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
|
||||
* @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
|
||||
* @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
|
||||
* @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.
|
||||
* @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
|
||||
* @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
|
||||
* @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
|
||||
* @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.
|
||||
* @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
|
||||
* @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
|
||||
* @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
|
||||
* @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.
|
||||
* @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
|
||||
* @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
|
||||
* @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
|
||||
* @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.
|
||||
* @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
|
||||
* @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
|
||||
* @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
|
||||
* @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt.
|
||||
* @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.
|
||||
* @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.
|
||||
* @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.
|
||||
* @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt.
|
||||
* @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.
|
||||
* @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.
|
||||
* @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.
|
||||
* @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt.
|
||||
* @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt.
|
||||
* @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt.
|
||||
* @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt.
|
||||
* @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt.
|
||||
* @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt.
|
||||
* @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt.
|
||||
* @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt.
|
||||
* @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt.
|
||||
* @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt.
|
||||
* @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt.
|
||||
* @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt.
|
||||
* @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt.
|
||||
* @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt.
|
||||
* @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt.
|
||||
* @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt.
|
||||
* @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt.
|
||||
* @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt.
|
||||
* @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt.
|
||||
* @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt.
|
||||
*
|
||||
* @note
|
||||
* The Global interrupt (DMAy_FLAG_GLx) is set whenever any of the other
|
||||
* interrupts relative to the same channel is set (Transfer Complete,
|
||||
* Half-transfer Complete or Transfer Error interrupts: DMAy_IT_TCx,
|
||||
* DMAy_IT_HTx or DMAy_IT_TEx).
|
||||
*
|
||||
* @retval The new state of DMAy_IT (SET or RESET).
|
||||
*/
|
||||
ITStatus DMA_GetITStatus(uint32_t DMAy_IT)
|
||||
{
|
||||
ITStatus bitstatus = RESET;
|
||||
uint32_t tmpreg = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_GET_IT(DMAy_IT));
|
||||
|
||||
/* Calculate the used DMAy */
|
||||
if ((DMAy_IT & FLAG_MASK) == (uint32_t)RESET)
|
||||
{
|
||||
/* Get DMA1 ISR register value */
|
||||
tmpreg = DMA1->ISR;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Get DMA2 ISR register value */
|
||||
tmpreg = DMA2->ISR;
|
||||
}
|
||||
|
||||
/* Check the status of the specified DMAy interrupt */
|
||||
if ((tmpreg & DMAy_IT) != (uint32_t)RESET)
|
||||
{
|
||||
/* DMAy_IT is set */
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* DMAy_IT is reset */
|
||||
bitstatus = RESET;
|
||||
}
|
||||
/* Return the DMAy_IT status */
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the DMAy Channelx's interrupt pending bits.
|
||||
* @param DMAy_IT: specifies the DMAy interrupt pending bit to clear.
|
||||
* This parameter can be any combination (for the same DMA) of the following values:
|
||||
* @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.
|
||||
* @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
|
||||
* @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
|
||||
* @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
|
||||
* @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.
|
||||
* @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
|
||||
* @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
|
||||
* @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
|
||||
* @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.
|
||||
* @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
|
||||
* @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
|
||||
* @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
|
||||
* @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.
|
||||
* @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
|
||||
* @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
|
||||
* @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
|
||||
* @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.
|
||||
* @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
|
||||
* @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
|
||||
* @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
|
||||
* @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt.
|
||||
* @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.
|
||||
* @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.
|
||||
* @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.
|
||||
* @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt.
|
||||
* @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.
|
||||
* @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.
|
||||
* @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.
|
||||
* @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt.
|
||||
* @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt.
|
||||
* @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt.
|
||||
* @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt.
|
||||
* @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt.
|
||||
* @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt.
|
||||
* @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt.
|
||||
* @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt.
|
||||
* @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt.
|
||||
* @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt.
|
||||
* @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt.
|
||||
* @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt.
|
||||
* @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt.
|
||||
* @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt.
|
||||
* @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt.
|
||||
* @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt.
|
||||
* @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt.
|
||||
* @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt.
|
||||
* @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt.
|
||||
* @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt.
|
||||
*
|
||||
* @note
|
||||
* Clearing the Global interrupt (DMAy_IT_GLx) results in clearing all other
|
||||
* interrupts relative to the same channel (Transfer Complete, Half-transfer
|
||||
* Complete and Transfer Error interrupts: DMAy_IT_TCx, DMAy_IT_HTx and
|
||||
* DMAy_IT_TEx).
|
||||
*
|
||||
* @retval None
|
||||
*/
|
||||
void DMA_ClearITPendingBit(uint32_t DMAy_IT)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_DMA_CLEAR_IT(DMAy_IT));
|
||||
|
||||
/* Calculate the used DMAy */
|
||||
if ((DMAy_IT & FLAG_MASK) == (uint32_t)RESET)
|
||||
{
|
||||
/* Clear the selected DMAy interrupt pending bits */
|
||||
DMA1->IFCR = DMAy_IT;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Clear the selected DMAy interrupt pending bits */
|
||||
DMA2->IFCR = DMAy_IT;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,317 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32l1xx_exti.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.1
|
||||
* @date 05-March-2012
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the EXTI peripheral:
|
||||
* + Initialization and Configuration
|
||||
* + Interrupts and flags management
|
||||
*
|
||||
* @verbatim
|
||||
==============================================================================
|
||||
##### EXTI features #####
|
||||
==============================================================================
|
||||
[..] External interrupt/event lines are mapped as following:
|
||||
(#) All available GPIO pins are connected to the 16 external
|
||||
interrupt/event lines from EXTI0 to EXTI15.
|
||||
(#) EXTI line 16 is connected to the PVD output.
|
||||
(#) EXTI line 17 is connected to the RTC Alarm event.
|
||||
(#) EXTI line 18 is connected to the USB Device FS wakeup event.
|
||||
(#) EXTI line 19 is connected to the RTC Tamper and TimeStamp events.
|
||||
(#) EXTI line 20 is connected to the RTC Wakeup event.
|
||||
(#) EXTI line 21 is connected to the Comparator 1 wakeup event.
|
||||
(#) EXTI line 22 is connected to the Comparator 2 wakeup event.
|
||||
(#) EXTI line 23 is connected to the Comparator channel acquisition wakeup event.
|
||||
|
||||
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..] In order to use an I/O pin as an external interrupt source, follow
|
||||
steps below:
|
||||
(#) Configure the I/O in input mode using GPIO_Init()
|
||||
(#) Select the input source pin for the EXTI line using
|
||||
SYSCFG_EXTILineConfig()
|
||||
(#) Select the mode(interrupt, event) and configure the trigger
|
||||
selection (Rising, falling or both) using EXTI_Init()
|
||||
(#) Configure NVIC IRQ channel mapped to the EXTI line using NVIC_Init()
|
||||
[..]
|
||||
(@) SYSCFG APB clock must be enabled to get write access to SYSCFG_EXTICRx
|
||||
registers using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
|
||||
|
||||
* @endverbatim
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32l1xx_exti.h"
|
||||
|
||||
/** @addtogroup STM32L1xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI
|
||||
* @brief EXTI driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
#define EXTI_LINENONE ((uint32_t)0x00000) /* No interrupt selected */
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup EXTI_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_Group1 Initialization and Configuration functions
|
||||
* @brief Initialization and Configuration functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### Initialization and Configuration functions #####
|
||||
==============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the EXTI peripheral registers to their default reset values.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void EXTI_DeInit(void)
|
||||
{
|
||||
EXTI->IMR = 0x00000000;
|
||||
EXTI->EMR = 0x00000000;
|
||||
EXTI->RTSR = 0x00000000;
|
||||
EXTI->FTSR = 0x00000000;
|
||||
EXTI->PR = 0x00FFFFFF;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the EXTI peripheral according to the specified
|
||||
* parameters in the EXTI_InitStruct.
|
||||
* EXTI_Line specifies the EXTI line (EXTI0....EXTI23).
|
||||
* EXTI_Mode specifies which EXTI line is used as interrupt or an event.
|
||||
* EXTI_Trigger selects the trigger. When the trigger occurs, interrupt
|
||||
* pending bit will be set.
|
||||
* EXTI_LineCmd controls (Enable/Disable) the EXTI line.
|
||||
* @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure
|
||||
* that contains the configuration information for the EXTI peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct)
|
||||
{
|
||||
uint32_t tmp = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode));
|
||||
assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger));
|
||||
assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line));
|
||||
assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd));
|
||||
|
||||
tmp = (uint32_t)EXTI_BASE;
|
||||
|
||||
if (EXTI_InitStruct->EXTI_LineCmd != DISABLE)
|
||||
{
|
||||
/* Clear EXTI line configuration */
|
||||
EXTI->IMR &= ~EXTI_InitStruct->EXTI_Line;
|
||||
EXTI->EMR &= ~EXTI_InitStruct->EXTI_Line;
|
||||
|
||||
tmp += EXTI_InitStruct->EXTI_Mode;
|
||||
|
||||
*(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;
|
||||
|
||||
/* Clear Rising Falling edge configuration */
|
||||
EXTI->RTSR &= ~EXTI_InitStruct->EXTI_Line;
|
||||
EXTI->FTSR &= ~EXTI_InitStruct->EXTI_Line;
|
||||
|
||||
/* Select the trigger for the selected external interrupts */
|
||||
if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling)
|
||||
{
|
||||
/* Rising Falling edge */
|
||||
EXTI->RTSR |= EXTI_InitStruct->EXTI_Line;
|
||||
EXTI->FTSR |= EXTI_InitStruct->EXTI_Line;
|
||||
}
|
||||
else
|
||||
{
|
||||
tmp = (uint32_t)EXTI_BASE;
|
||||
tmp += EXTI_InitStruct->EXTI_Trigger;
|
||||
|
||||
*(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
tmp += EXTI_InitStruct->EXTI_Mode;
|
||||
|
||||
/* Disable the selected external lines */
|
||||
*(__IO uint32_t *) tmp &= ~EXTI_InitStruct->EXTI_Line;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Fills each EXTI_InitStruct member with its reset value.
|
||||
* @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will
|
||||
* be initialized.
|
||||
* @retval None
|
||||
*/
|
||||
void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct)
|
||||
{
|
||||
EXTI_InitStruct->EXTI_Line = EXTI_LINENONE;
|
||||
EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt;
|
||||
EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling;
|
||||
EXTI_InitStruct->EXTI_LineCmd = DISABLE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Generates a Software interrupt on selected EXTI line.
|
||||
* @param EXTI_Line: specifies the EXTI line on which the software interrupt
|
||||
* will be generated.
|
||||
* This parameter can be any combination of EXTI_Linex where x can be (0..23).
|
||||
* @retval None
|
||||
*/
|
||||
void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_EXTI_LINE(EXTI_Line));
|
||||
|
||||
EXTI->SWIER |= EXTI_Line;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup EXTI_Group2 Interrupts and flags management functions
|
||||
* @brief Interrupts and flags management functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### Interrupts and flags management functions #####
|
||||
==============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified EXTI line flag is set or not.
|
||||
* @param EXTI_Line: specifies the EXTI line flag to check.
|
||||
* This parameter can be:
|
||||
* EXTI_Linex: External interrupt line x where x(0..23).
|
||||
* @retval The new state of EXTI_Line (SET or RESET).
|
||||
*/
|
||||
FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line)
|
||||
{
|
||||
FlagStatus bitstatus = RESET;
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GET_EXTI_LINE(EXTI_Line));
|
||||
|
||||
if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET)
|
||||
{
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = RESET;
|
||||
}
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the EXTI's line pending flags.
|
||||
* @param EXTI_Line: specifies the EXTI lines flags to clear.
|
||||
* This parameter can be any combination of EXTI_Linex where x can be (0..23).
|
||||
* @retval None
|
||||
*/
|
||||
void EXTI_ClearFlag(uint32_t EXTI_Line)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_EXTI_LINE(EXTI_Line));
|
||||
|
||||
EXTI->PR = EXTI_Line;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified EXTI line is asserted or not.
|
||||
* @param EXTI_Line: specifies the EXTI line to check.
|
||||
* This parameter can be:
|
||||
* EXTI_Linex: External interrupt line x where x(0..23).
|
||||
* @retval The new state of EXTI_Line (SET or RESET).
|
||||
*/
|
||||
ITStatus EXTI_GetITStatus(uint32_t EXTI_Line)
|
||||
{
|
||||
ITStatus bitstatus = RESET;
|
||||
uint32_t enablestatus = 0;
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GET_EXTI_LINE(EXTI_Line));
|
||||
|
||||
enablestatus = EXTI->IMR & EXTI_Line;
|
||||
if (((EXTI->PR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))
|
||||
{
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = RESET;
|
||||
}
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the EXTI's line pending bits.
|
||||
* @param EXTI_Line: specifies the EXTI lines to clear.
|
||||
* This parameter can be any combination of EXTI_Linex where x can be (0..23).
|
||||
* @retval None
|
||||
*/
|
||||
void EXTI_ClearITPendingBit(uint32_t EXTI_Line)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_EXTI_LINE(EXTI_Line));
|
||||
|
||||
EXTI->PR = EXTI_Line;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,553 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32l1xx_flash_ramfunc.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.1
|
||||
* @date 05-March-2012
|
||||
* @brief This file provides all the Flash firmware functions which should be
|
||||
* executed from the internal SRAM. This file should be placed in
|
||||
* internal SRAM.
|
||||
* Other FLASH memory functions that can be used from the FLASH are
|
||||
* defined in the "stm32l1xx_flash.c" file.
|
||||
@verbatim
|
||||
|
||||
*** ARM Compiler ***
|
||||
--------------------
|
||||
[..] RAM functions are defined using the toolchain options.
|
||||
Functions that are be executed in RAM should reside in a separate
|
||||
source module. Using the 'Options for File' dialog you can simply change
|
||||
the 'Code / Const' area of a module to a memory space in physical RAM.
|
||||
Available memory areas are declared in the 'Target' tab of the
|
||||
Options for Target' dialog.
|
||||
|
||||
*** ICCARM Compiler ***
|
||||
-----------------------
|
||||
[..] RAM functions are defined using a specific toolchain keyword "__ramfunc".
|
||||
|
||||
*** GNU Compiler ***
|
||||
--------------------
|
||||
[..] RAM functions are defined using a specific toolchain attribute
|
||||
"__attribute__((section(".data")))".
|
||||
|
||||
*** TASKING Compiler ***
|
||||
------------------------
|
||||
[..] RAM functions are defined using a specific toolchain pragma. This
|
||||
pragma is defined inside this file.
|
||||
|
||||
@endverbatim
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32l1xx_flash.h"
|
||||
|
||||
/** @addtogroup STM32L1xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH
|
||||
* @brief FLASH driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
static __RAM_FUNC GetStatus(void);
|
||||
static __RAM_FUNC WaitForLastOperation(uint32_t Timeout);
|
||||
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup FLASH_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASH_Group1
|
||||
*
|
||||
@verbatim
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
#if defined ( __TASKING__ )
|
||||
#pragma section_code_init on
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief Enable or disable the power down mode during RUN mode.
|
||||
* @note This function can be used only when the user code is running from Internal SRAM.
|
||||
* @param NewState: new state of the power down mode during RUN mode.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
__RAM_FUNC FLASH_RUNPowerDownCmd(FunctionalState NewState)
|
||||
{
|
||||
FLASH_Status status = FLASH_COMPLETE;
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Unlock the RUN_PD bit */
|
||||
FLASH->PDKEYR = FLASH_PDKEY1;
|
||||
FLASH->PDKEYR = FLASH_PDKEY2;
|
||||
|
||||
/* Set the RUN_PD bit in FLASH_ACR register to put Flash in power down mode */
|
||||
FLASH->ACR |= (uint32_t)FLASH_ACR_RUN_PD;
|
||||
|
||||
if((FLASH->ACR & FLASH_ACR_RUN_PD) != FLASH_ACR_RUN_PD)
|
||||
{
|
||||
status = FLASH_ERROR_PROGRAM;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Clear the RUN_PD bit in FLASH_ACR register to put Flash in idle mode */
|
||||
FLASH->ACR &= (uint32_t)(~(uint32_t)FLASH_ACR_RUN_PD);
|
||||
}
|
||||
|
||||
/* Return the Write Status */
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASH_Group2
|
||||
*
|
||||
@verbatim
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Erases a specified 2 page in program memory in parallel.
|
||||
* @note This function can be used only for STM32L1XX_HD density devices.
|
||||
* To correctly run this function, the FLASH_Unlock() function
|
||||
* must be called before.
|
||||
* Call the FLASH_Lock() to disable the flash memory access
|
||||
* (recommended to protect the FLASH memory against possible unwanted operation).
|
||||
* @param Page_Address1: The page address in program memory to be erased in
|
||||
* the first Bank (BANK1). This parameter should be between 0x08000000
|
||||
* and 0x0802FF00.
|
||||
* @param Page_Address2: The page address in program memory to be erased in
|
||||
* the second Bank (BANK2). This parameter should be between 0x08030000
|
||||
* and 0x0805FF00.
|
||||
* @note A Page is erased in the Program memory only if the address to load
|
||||
* is the start address of a page (multiple of 256 bytes).
|
||||
* @retval FLASH Status: The returned value can be:
|
||||
* FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
|
||||
*/
|
||||
FLASH_Status FLASH_EraseParallelPage(uint32_t Page_Address1, uint32_t Page_Address2)
|
||||
{
|
||||
FLASH_Status status = FLASH_COMPLETE;
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
|
||||
|
||||
if(status == FLASH_COMPLETE)
|
||||
{
|
||||
/* If the previous operation is completed, proceed to erase the page */
|
||||
|
||||
/* Set the PARALLBANK bit */
|
||||
FLASH->PECR |= FLASH_PECR_PARALLBANK;
|
||||
|
||||
/* Set the ERASE bit */
|
||||
FLASH->PECR |= FLASH_PECR_ERASE;
|
||||
|
||||
/* Set PROG bit */
|
||||
FLASH->PECR |= FLASH_PECR_PROG;
|
||||
|
||||
/* Write 00000000h to the first word of the first program page to erase */
|
||||
*(__IO uint32_t *)Page_Address1 = 0x00000000;
|
||||
/* Write 00000000h to the first word of the second program page to erase */
|
||||
*(__IO uint32_t *)Page_Address2 = 0x00000000;
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
|
||||
|
||||
/* If the erase operation is completed, disable the ERASE, PROG and PARALLBANK bits */
|
||||
FLASH->PECR &= (uint32_t)(~FLASH_PECR_PROG);
|
||||
FLASH->PECR &= (uint32_t)(~FLASH_PECR_ERASE);
|
||||
FLASH->PECR &= (uint32_t)(~FLASH_PECR_PARALLBANK);
|
||||
}
|
||||
/* Return the Erase Status */
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Programs a half page in program memory.
|
||||
* @param Address: specifies the address to be written.
|
||||
* @param pBuffer: pointer to the buffer containing the data to be written to
|
||||
* the half page.
|
||||
* @note To correctly run this function, the FLASH_Unlock() function
|
||||
* must be called before.
|
||||
* Call the FLASH_Lock() to disable the flash memory access
|
||||
* (recommended to protect the FLASH memory against possible unwanted operation)
|
||||
* @note Half page write is possible only from SRAM.
|
||||
* @note If there are more than 32 words to write, after 32 words another
|
||||
* Half Page programming operation starts and has to be finished.
|
||||
* @note A half page is written to the program memory only if the first
|
||||
* address to load is the start address of a half page (multiple of 128
|
||||
* bytes) and the 31 remaining words to load are in the same half page.
|
||||
* @note During the Program memory half page write all read operations are
|
||||
* forbidden (this includes DMA read operations and debugger read
|
||||
* operations such as breakpoints, periodic updates, etc.).
|
||||
* @note If a PGAERR is set during a Program memory half page write, the
|
||||
* complete write operation is aborted. Software should then reset the
|
||||
* FPRG and PROG/DATA bits and restart the write operation from the
|
||||
* beginning.
|
||||
* @retval FLASH Status: The returned value can be:
|
||||
* FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
|
||||
*/
|
||||
__RAM_FUNC FLASH_ProgramHalfPage(uint32_t Address, uint32_t* pBuffer)
|
||||
{
|
||||
uint32_t count = 0;
|
||||
|
||||
FLASH_Status status = FLASH_COMPLETE;
|
||||
|
||||
/* Set the DISMCYCINT[0] bit in the Auxillary Control Register (0xE000E008)
|
||||
This bit prevents the interruption of multicycle instructions and therefore
|
||||
will increase the interrupt latency. of Cortex-M3. */
|
||||
SCnSCB->ACTLR |= SCnSCB_ACTLR_DISMCYCINT_Msk;
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
|
||||
|
||||
if(status == FLASH_COMPLETE)
|
||||
{
|
||||
/* if the previous operation is completed, proceed to program the new
|
||||
half page */
|
||||
FLASH->PECR |= FLASH_PECR_FPRG;
|
||||
FLASH->PECR |= FLASH_PECR_PROG;
|
||||
|
||||
/* Write one half page directly with 32 different words */
|
||||
while(count < 32)
|
||||
{
|
||||
*(__IO uint32_t*) (Address + (4 * count)) = *(pBuffer++);
|
||||
count ++;
|
||||
}
|
||||
/* Wait for last operation to be completed */
|
||||
status = WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
|
||||
|
||||
/* if the write operation is completed, disable the PROG and FPRG bits */
|
||||
FLASH->PECR &= (uint32_t)(~FLASH_PECR_PROG);
|
||||
FLASH->PECR &= (uint32_t)(~FLASH_PECR_FPRG);
|
||||
}
|
||||
|
||||
SCnSCB->ACTLR &= ~SCnSCB_ACTLR_DISMCYCINT_Msk;
|
||||
|
||||
/* Return the Write Status */
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Programs 2 half page in program memory in parallel.
|
||||
* @param Address1: specifies the first address to be written in the first bank
|
||||
* (BANK1). This parameter should be between 0x08000000 and 0x0802FF80.
|
||||
* @param pBuffer1: pointer to the buffer containing the data to be written
|
||||
* to the first half page in the first bank.
|
||||
* @param Address2: specifies the second address to be written in the second bank
|
||||
* (BANK2). This parameter should be between 0x08030000 and 0x0805FF80.
|
||||
* @param pBuffer2: pointer to the buffer containing the data to be written
|
||||
* to the second half page in the second bank.
|
||||
* @note This function can be used only for STM32L1XX_HD density devices.
|
||||
* @note To correctly run this function, the FLASH_Unlock() function
|
||||
* must be called before.
|
||||
* Call the FLASH_Lock() to disable the flash memory access
|
||||
* (recommended to protect the FLASH memory against possible unwanted operation).
|
||||
* @note Half page write is possible only from SRAM.
|
||||
* @note If there are more than 32 words to write, after 32 words another
|
||||
* Half Page programming operation starts and has to be finished.
|
||||
* @note A half page is written to the program memory only if the first
|
||||
* address to load is the start address of a half page (multiple of 128
|
||||
* bytes) and the 31 remaining words to load are in the same half page.
|
||||
* @note During the Program memory half page write all read operations are
|
||||
* forbidden (this includes DMA read operations and debugger read
|
||||
* operations such as breakpoints, periodic updates, etc.).
|
||||
* @note If a PGAERR is set during a Program memory half page write, the
|
||||
* complete write operation is aborted. Software should then reset the
|
||||
* FPRG and PROG/DATA bits and restart the write operation from the
|
||||
* beginning.
|
||||
* @retval FLASH Status: The returned value can be:
|
||||
* FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
|
||||
*/
|
||||
__RAM_FUNC FLASH_ProgramParallelHalfPage(uint32_t Address1, uint32_t* pBuffer1, uint32_t Address2, uint32_t* pBuffer2)
|
||||
{
|
||||
uint32_t count = 0;
|
||||
|
||||
FLASH_Status status = FLASH_COMPLETE;
|
||||
|
||||
/* Set the DISMCYCINT[0] bit in the Auxillary Control Register (0xE000E008)
|
||||
This bit prevents the interruption of multicycle instructions and therefore
|
||||
will increase the interrupt latency. of Cortex-M3. */
|
||||
SCnSCB->ACTLR |= SCnSCB_ACTLR_DISMCYCINT_Msk;
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
|
||||
|
||||
if(status == FLASH_COMPLETE)
|
||||
{
|
||||
/* If the previous operation is completed, proceed to program the new
|
||||
half page */
|
||||
FLASH->PECR |= FLASH_PECR_PARALLBANK;
|
||||
FLASH->PECR |= FLASH_PECR_FPRG;
|
||||
FLASH->PECR |= FLASH_PECR_PROG;
|
||||
|
||||
/* Write the first half page directly with 32 different words */
|
||||
while(count < 32)
|
||||
{
|
||||
*(__IO uint32_t*) (Address1 + (4 * count)) = *(pBuffer1++);
|
||||
count ++;
|
||||
}
|
||||
count = 0;
|
||||
/* Write the second half page directly with 32 different words */
|
||||
while(count < 32)
|
||||
{
|
||||
*(__IO uint32_t*) (Address2 + (4 * count)) = *(pBuffer2++);
|
||||
count ++;
|
||||
}
|
||||
/* Wait for last operation to be completed */
|
||||
status = WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
|
||||
|
||||
/* if the write operation is completed, disable the PROG, FPRG and PARALLBANK bits */
|
||||
FLASH->PECR &= (uint32_t)(~FLASH_PECR_PROG);
|
||||
FLASH->PECR &= (uint32_t)(~FLASH_PECR_FPRG);
|
||||
FLASH->PECR &= (uint32_t)(~FLASH_PECR_PARALLBANK);
|
||||
}
|
||||
|
||||
SCnSCB->ACTLR &= ~SCnSCB_ACTLR_DISMCYCINT_Msk;
|
||||
|
||||
/* Return the Write Status */
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @addtogroup FLASH_Group3
|
||||
*
|
||||
@verbatim
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Erase a double word in data memory.
|
||||
* @param Address: specifies the address to be erased.
|
||||
* @note To correctly run this function, the DATA_EEPROM_Unlock() function
|
||||
* must be called before.
|
||||
* Call the DATA_EEPROM_Lock() to he data EEPROM access
|
||||
* and Flash program erase control register access(recommended to protect
|
||||
* the DATA_EEPROM against possible unwanted operation).
|
||||
* @note Data memory double word erase is possible only from SRAM.
|
||||
* @note A double word is erased to the data memory only if the first address
|
||||
* to load is the start address of a double word (multiple of 8 bytes).
|
||||
* @note During the Data memory double word erase, all read operations are
|
||||
* forbidden (this includes DMA read operations and debugger read
|
||||
* operations such as breakpoints, periodic updates, etc.).
|
||||
* @retval FLASH Status: The returned value can be:
|
||||
* FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
|
||||
*/
|
||||
|
||||
__RAM_FUNC DATA_EEPROM_EraseDoubleWord(uint32_t Address)
|
||||
{
|
||||
FLASH_Status status = FLASH_COMPLETE;
|
||||
|
||||
/* Set the DISMCYCINT[0] bit in the Auxillary Control Register (0xE000E008)
|
||||
This bit prevents the interruption of multicycle instructions and therefore
|
||||
will increase the interrupt latency. of Cortex-M3. */
|
||||
SCnSCB->ACTLR |= SCnSCB_ACTLR_DISMCYCINT_Msk;
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
|
||||
|
||||
if(status == FLASH_COMPLETE)
|
||||
{
|
||||
/* If the previous operation is completed, proceed to erase the next double word */
|
||||
/* Set the ERASE bit */
|
||||
FLASH->PECR |= FLASH_PECR_ERASE;
|
||||
|
||||
/* Set DATA bit */
|
||||
FLASH->PECR |= FLASH_PECR_DATA;
|
||||
|
||||
/* Write 00000000h to the 2 words to erase */
|
||||
*(__IO uint32_t *)Address = 0x00000000;
|
||||
Address += 4;
|
||||
*(__IO uint32_t *)Address = 0x00000000;
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
|
||||
|
||||
/* If the erase operation is completed, disable the ERASE and DATA bits */
|
||||
FLASH->PECR &= (uint32_t)(~FLASH_PECR_ERASE);
|
||||
FLASH->PECR &= (uint32_t)(~FLASH_PECR_DATA);
|
||||
}
|
||||
|
||||
SCnSCB->ACTLR &= ~SCnSCB_ACTLR_DISMCYCINT_Msk;
|
||||
|
||||
/* Return the erase status */
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Write a double word in data memory without erase.
|
||||
* @param Address: specifies the address to be written.
|
||||
* @param Data: specifies the data to be written.
|
||||
* @note To correctly run this function, the DATA_EEPROM_Unlock() function
|
||||
* must be called before.
|
||||
* Call the DATA_EEPROM_Lock() to he data EEPROM access
|
||||
* and Flash program erase control register access(recommended to protect
|
||||
* the DATA_EEPROM against possible unwanted operation).
|
||||
* @note Data memory double word write is possible only from SRAM.
|
||||
* @note A data memory double word is written to the data memory only if the
|
||||
* first address to load is the start address of a double word (multiple
|
||||
* of double word).
|
||||
* @note During the Data memory double word write, all read operations are
|
||||
* forbidden (this includes DMA read operations and debugger read
|
||||
* operations such as breakpoints, periodic updates, etc.).
|
||||
* @retval FLASH Status: The returned value can be:
|
||||
* FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
|
||||
*/
|
||||
__RAM_FUNC DATA_EEPROM_ProgramDoubleWord(uint32_t Address, uint64_t Data)
|
||||
{
|
||||
FLASH_Status status = FLASH_COMPLETE;
|
||||
|
||||
/* Set the DISMCYCINT[0] bit in the Auxillary Control Register (0xE000E008)
|
||||
This bit prevents the interruption of multicycle instructions and therefore
|
||||
will increase the interrupt latency. of Cortex-M3. */
|
||||
SCnSCB->ACTLR |= SCnSCB_ACTLR_DISMCYCINT_Msk;
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
|
||||
|
||||
if(status == FLASH_COMPLETE)
|
||||
{
|
||||
/* If the previous operation is completed, proceed to program the new data*/
|
||||
FLASH->PECR |= FLASH_PECR_FPRG;
|
||||
FLASH->PECR |= FLASH_PECR_DATA;
|
||||
|
||||
/* Write the 2 words */
|
||||
*(__IO uint32_t *)Address = (uint32_t) Data;
|
||||
Address += 4;
|
||||
*(__IO uint32_t *)Address = (uint32_t) (Data >> 32);
|
||||
|
||||
/* Wait for last operation to be completed */
|
||||
status = WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
|
||||
|
||||
/* If the write operation is completed, disable the FPRG and DATA bits */
|
||||
FLASH->PECR &= (uint32_t)(~FLASH_PECR_FPRG);
|
||||
FLASH->PECR &= (uint32_t)(~FLASH_PECR_DATA);
|
||||
}
|
||||
|
||||
SCnSCB->ACTLR &= ~SCnSCB_ACTLR_DISMCYCINT_Msk;
|
||||
|
||||
/* Return the Write Status */
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Returns the FLASH Status.
|
||||
* @param None
|
||||
* @retval FLASH Status: The returned value can be: FLASH_BUSY,
|
||||
* FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP or FLASH_COMPLETE
|
||||
*/
|
||||
static __RAM_FUNC GetStatus(void)
|
||||
{
|
||||
FLASH_Status FLASHstatus = FLASH_COMPLETE;
|
||||
|
||||
if((FLASH->SR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY)
|
||||
{
|
||||
FLASHstatus = FLASH_BUSY;
|
||||
}
|
||||
else
|
||||
{
|
||||
if((FLASH->SR & (uint32_t)FLASH_FLAG_WRPERR)!= (uint32_t)0x00)
|
||||
{
|
||||
FLASHstatus = FLASH_ERROR_WRP;
|
||||
}
|
||||
else
|
||||
{
|
||||
if((FLASH->SR & (uint32_t)0x1E00) != (uint32_t)0x00)
|
||||
{
|
||||
FLASHstatus = FLASH_ERROR_PROGRAM;
|
||||
}
|
||||
else
|
||||
{
|
||||
FLASHstatus = FLASH_COMPLETE;
|
||||
}
|
||||
}
|
||||
}
|
||||
/* Return the FLASH Status */
|
||||
return FLASHstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Waits for a FLASH operation to complete or a TIMEOUT to occur.
|
||||
* @param Timeout: FLASH programming Timeout
|
||||
* @retval FLASH Status: The returned value can be: FLASH_BUSY,
|
||||
* FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or
|
||||
* FLASH_TIMEOUT.
|
||||
*/
|
||||
static __RAM_FUNC WaitForLastOperation(uint32_t Timeout)
|
||||
{
|
||||
__IO FLASH_Status status = FLASH_COMPLETE;
|
||||
|
||||
/* Check for the FLASH Status */
|
||||
status = GetStatus();
|
||||
|
||||
/* Wait for a FLASH operation to complete or a TIMEOUT to occur */
|
||||
while((status == FLASH_BUSY) && (Timeout != 0x00))
|
||||
{
|
||||
status = GetStatus();
|
||||
Timeout--;
|
||||
}
|
||||
|
||||
if(Timeout == 0x00 )
|
||||
{
|
||||
status = FLASH_TIMEOUT;
|
||||
}
|
||||
/* Return the operation status */
|
||||
return status;
|
||||
}
|
||||
|
||||
#if defined ( __TASKING__ )
|
||||
#pragma section_code_init restore
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,285 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32l1xx_fsmc.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.1
|
||||
* @date 05-March-2012
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the FSMC peripheral:
|
||||
* + Initialization
|
||||
* + Interrupts and flags management
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32l1xx_fsmc.h"
|
||||
#include "stm32l1xx_rcc.h"
|
||||
|
||||
/** @addtogroup STM32L1xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC
|
||||
* @brief FSMC driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup FSMC_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup FSMC_Group1 NOR/SRAM Controller functions
|
||||
* @brief NOR/SRAM Controller functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### NOR-SRAM Controller functions #####
|
||||
==============================================================================
|
||||
[..] The following sequence should be followed to configure the FSMC to
|
||||
interface with SRAM, PSRAM, NOR or OneNAND memory connected to the
|
||||
NOR/SRAM Bank:
|
||||
(#) Enable the clock for the FSMC and associated GPIOs using the following
|
||||
functions:
|
||||
(++)RCC_AHBPeriphClockCmd(RCC_AHBPeriph_FSMC, ENABLE);
|
||||
(++)RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOx, ENABLE);
|
||||
(#) FSMC pins configuration
|
||||
(++) Connect the involved FSMC pins to AF12 using the following function
|
||||
GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FSMC);
|
||||
(++) Configure these FSMC pins in alternate function mode by calling the
|
||||
function GPIO_Init();
|
||||
(#) Declare a FSMC_NORSRAMInitTypeDef structure, for example:
|
||||
FSMC_NORSRAMInitTypeDef FSMC_NORSRAMInitStructure; and fill the
|
||||
FSMC_NORSRAMInitStructure variable with the allowed values of the
|
||||
structure member.
|
||||
(#) Initialize the NOR/SRAM Controller by calling the function
|
||||
FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure);
|
||||
(#) Then enable the NOR/SRAM Bank, for example:
|
||||
FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM2, ENABLE);
|
||||
(#) At this stage you can read/write from/to the memory connected to the
|
||||
NOR/SRAM Bank.
|
||||
|
||||
@endverbatim
|
||||
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the FSMC NOR/SRAM Banks registers to their default
|
||||
* reset values.
|
||||
* @param FSMC_Bank: specifies the FSMC Bank to be used
|
||||
* This parameter can be one of the following values:
|
||||
* @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1
|
||||
* @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2
|
||||
* @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3
|
||||
* @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4
|
||||
* @retval None
|
||||
*/
|
||||
void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank)
|
||||
{
|
||||
/* Check the parameter */
|
||||
assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));
|
||||
|
||||
/* FSMC_Bank1_NORSRAM1 */
|
||||
if(FSMC_Bank == FSMC_Bank1_NORSRAM1)
|
||||
{
|
||||
FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030DB;
|
||||
}
|
||||
/* FSMC_Bank1_NORSRAM2, FSMC_Bank1_NORSRAM3 or FSMC_Bank1_NORSRAM4 */
|
||||
else
|
||||
{
|
||||
FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030D2;
|
||||
}
|
||||
FSMC_Bank1->BTCR[FSMC_Bank + 1] = 0x0FFFFFFF;
|
||||
FSMC_Bank1E->BWTR[FSMC_Bank] = 0x0FFFFFFF;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the FSMC NOR/SRAM Banks according to the specified
|
||||
* parameters in the FSMC_NORSRAMInitStruct.
|
||||
* @param FSMC_NORSRAMInitStruct : pointer to a FSMC_NORSRAMInitTypeDef
|
||||
* structure that contains the configuration information for
|
||||
* the FSMC NOR/SRAM specified Banks.
|
||||
* @retval None
|
||||
*/
|
||||
void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FSMC_NORSRAM_BANK(FSMC_NORSRAMInitStruct->FSMC_Bank));
|
||||
assert_param(IS_FSMC_MUX(FSMC_NORSRAMInitStruct->FSMC_DataAddressMux));
|
||||
assert_param(IS_FSMC_MEMORY(FSMC_NORSRAMInitStruct->FSMC_MemoryType));
|
||||
assert_param(IS_FSMC_MEMORY_WIDTH(FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth));
|
||||
assert_param(IS_FSMC_BURSTMODE(FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode));
|
||||
assert_param(IS_FSMC_ASYNWAIT(FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait));
|
||||
assert_param(IS_FSMC_WAIT_POLARITY(FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity));
|
||||
assert_param(IS_FSMC_WRAP_MODE(FSMC_NORSRAMInitStruct->FSMC_WrapMode));
|
||||
assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive));
|
||||
assert_param(IS_FSMC_WRITE_OPERATION(FSMC_NORSRAMInitStruct->FSMC_WriteOperation));
|
||||
assert_param(IS_FSMC_WAITE_SIGNAL(FSMC_NORSRAMInitStruct->FSMC_WaitSignal));
|
||||
assert_param(IS_FSMC_EXTENDED_MODE(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode));
|
||||
assert_param(IS_FSMC_WRITE_BURST(FSMC_NORSRAMInitStruct->FSMC_WriteBurst));
|
||||
assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime));
|
||||
assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime));
|
||||
assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime));
|
||||
assert_param(IS_FSMC_TURNAROUND_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration));
|
||||
assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision));
|
||||
assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency));
|
||||
assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode));
|
||||
|
||||
/* Bank1 NOR/SRAM control register configuration */
|
||||
FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] =
|
||||
(uint32_t)FSMC_NORSRAMInitStruct->FSMC_DataAddressMux |
|
||||
FSMC_NORSRAMInitStruct->FSMC_MemoryType |
|
||||
FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth |
|
||||
FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode |
|
||||
FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait |
|
||||
FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity |
|
||||
FSMC_NORSRAMInitStruct->FSMC_WrapMode |
|
||||
FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive |
|
||||
FSMC_NORSRAMInitStruct->FSMC_WriteOperation |
|
||||
FSMC_NORSRAMInitStruct->FSMC_WaitSignal |
|
||||
FSMC_NORSRAMInitStruct->FSMC_ExtendedMode |
|
||||
FSMC_NORSRAMInitStruct->FSMC_WriteBurst;
|
||||
|
||||
if(FSMC_NORSRAMInitStruct->FSMC_MemoryType == FSMC_MemoryType_NOR)
|
||||
{
|
||||
FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] |= (uint32_t)FSMC_BCR1_FACCEN;
|
||||
}
|
||||
|
||||
/* Bank1 NOR/SRAM timing register configuration */
|
||||
FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank+1] =
|
||||
(uint32_t)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime |
|
||||
(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime << 4) |
|
||||
(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime << 8) |
|
||||
(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration << 16) |
|
||||
(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision << 20) |
|
||||
(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency << 24) |
|
||||
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode;
|
||||
|
||||
|
||||
/* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */
|
||||
if(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode == FSMC_ExtendedMode_Enable)
|
||||
{
|
||||
assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime));
|
||||
assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime));
|
||||
assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime));
|
||||
assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision));
|
||||
assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency));
|
||||
assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode));
|
||||
FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] =
|
||||
(uint32_t)FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime |
|
||||
(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime << 4 )|
|
||||
(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime << 8) |
|
||||
(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision << 20) |
|
||||
(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency << 24) |
|
||||
FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode;
|
||||
}
|
||||
else
|
||||
{
|
||||
FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 0x0FFFFFFF;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Fills each FSMC_NORSRAMInitStruct member with its default value.
|
||||
* @param FSMC_NORSRAMInitStruct: pointer to a FSMC_NORSRAMInitTypeDef
|
||||
* structure which will be initialized.
|
||||
* @retval None
|
||||
*/
|
||||
void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
|
||||
{
|
||||
/* Reset NOR/SRAM Init structure parameters values */
|
||||
FSMC_NORSRAMInitStruct->FSMC_Bank = FSMC_Bank1_NORSRAM1;
|
||||
FSMC_NORSRAMInitStruct->FSMC_DataAddressMux = FSMC_DataAddressMux_Enable;
|
||||
FSMC_NORSRAMInitStruct->FSMC_MemoryType = FSMC_MemoryType_SRAM;
|
||||
FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
|
||||
FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
|
||||
FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
|
||||
FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
|
||||
FSMC_NORSRAMInitStruct->FSMC_WrapMode = FSMC_WrapMode_Disable;
|
||||
FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
|
||||
FSMC_NORSRAMInitStruct->FSMC_WriteOperation = FSMC_WriteOperation_Enable;
|
||||
FSMC_NORSRAMInitStruct->FSMC_WaitSignal = FSMC_WaitSignal_Enable;
|
||||
FSMC_NORSRAMInitStruct->FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
|
||||
FSMC_NORSRAMInitStruct->FSMC_WriteBurst = FSMC_WriteBurst_Disable;
|
||||
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime = 0xF;
|
||||
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime = 0xF;
|
||||
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime = 0xFF;
|
||||
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;
|
||||
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision = 0xF;
|
||||
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency = 0xF;
|
||||
FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A;
|
||||
FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime = 0xF;
|
||||
FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime = 0xF;
|
||||
FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime = 0xFF;
|
||||
FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;
|
||||
FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision = 0xF;
|
||||
FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency = 0xF;
|
||||
FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the specified NOR/SRAM Memory Bank.
|
||||
* @param FSMC_Bank: specifies the FSMC Bank to be used
|
||||
* This parameter can be one of the following values:
|
||||
* @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1
|
||||
* @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2
|
||||
* @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3
|
||||
* @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4
|
||||
* @param NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState)
|
||||
{
|
||||
assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the selected NOR/SRAM Bank by setting the MBKEN bit in the BCRx register */
|
||||
FSMC_Bank1->BTCR[FSMC_Bank] |= FSMC_BCR1_MBKEN;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the selected NOR/SRAM Bank by clearing the MBKEN bit in the BCRx register */
|
||||
FSMC_Bank1->BTCR[FSMC_Bank] &= (uint32_t)(~FSMC_BCR1_MBKEN);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,557 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32l1xx_gpio.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.1
|
||||
* @date 05-March-2012
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the GPIO peripheral:
|
||||
* + Initialization and Configuration
|
||||
* + GPIO Read and Write
|
||||
* + GPIO Alternate functions configuration
|
||||
*
|
||||
* @verbatim
|
||||
===========================================================================
|
||||
##### How to use this driver #####
|
||||
===========================================================================
|
||||
[..]
|
||||
(#) Enable the GPIO AHB clock using RCC_AHBPeriphClockCmd()
|
||||
(#) Configure the GPIO pin(s) using GPIO_Init()
|
||||
Four possible configuration are available for each pin:
|
||||
(++) Input: Floating, Pull-up, Pull-down.
|
||||
(++) Output: Push-Pull (Pull-up, Pull-down or no Pull)
|
||||
Open Drain (Pull-up, Pull-down or no Pull).
|
||||
In output mode, the speed is configurable: Very Low, Low,
|
||||
Medium or High.
|
||||
(++) Alternate Function: Push-Pull (Pull-up, Pull-down or no Pull)
|
||||
Open Drain (Pull-up, Pull-down or no Pull).
|
||||
(++) Analog: required mode when a pin is to be used as ADC channel,
|
||||
DAC output or comparator input.
|
||||
(#) Peripherals alternate function:
|
||||
(++) For ADC, DAC and comparators, configure the desired pin in
|
||||
analog mode using GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AN
|
||||
(++) For other peripherals (TIM, USART...):
|
||||
(+++) Connect the pin to the desired peripherals' Alternate
|
||||
Function (AF) using GPIO_PinAFConfig() function.
|
||||
(+++) Configure the desired pin in alternate function mode using
|
||||
GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF
|
||||
(+++) Select the type, pull-up/pull-down and output speed via
|
||||
GPIO_PuPd, GPIO_OType and GPIO_Speed members.
|
||||
(+++) Call GPIO_Init() function.
|
||||
(#) To get the level of a pin configured in input mode use GPIO_ReadInputDataBit()
|
||||
(#) To set/reset the level of a pin configured in output mode use
|
||||
GPIO_SetBits()/GPIO_ResetBits()
|
||||
(#) During and just after reset, the alternate functions are not
|
||||
active and the GPIO pins are configured in input floating mode
|
||||
(except JTAG pins).
|
||||
(#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as
|
||||
general-purpose (PC14 and PC15, respectively) when the LSE
|
||||
oscillator is off. The LSE has priority over the GPIO function.
|
||||
(#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as
|
||||
general-purpose PH0 and PH1, respectively, when the HSE
|
||||
oscillator is off. The HSE has priority over the GPIO function.
|
||||
@endverbatim
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32l1xx_gpio.h"
|
||||
#include "stm32l1xx_rcc.h"
|
||||
|
||||
/** @addtogroup STM32L1xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO
|
||||
* @brief GPIO driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup GPIO_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Group1 Initialization and Configuration
|
||||
* @brief Initialization and Configuration
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Initialization and Configuration #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the GPIOx peripheral registers to their default reset
|
||||
* values.
|
||||
* By default, The GPIO pins are configured in input floating mode
|
||||
* (except JTAG pins).
|
||||
* @param GPIOx: where x can be (A..H) to select the GPIO peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_DeInit(GPIO_TypeDef* GPIOx)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
|
||||
if(GPIOx == GPIOA)
|
||||
{
|
||||
RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOA, ENABLE);
|
||||
RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOA, DISABLE);
|
||||
}
|
||||
else if(GPIOx == GPIOB)
|
||||
{
|
||||
RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOB, ENABLE);
|
||||
RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOB, DISABLE);
|
||||
}
|
||||
else if(GPIOx == GPIOC)
|
||||
{
|
||||
RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOC, ENABLE);
|
||||
RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOC, DISABLE);
|
||||
}
|
||||
else if(GPIOx == GPIOD)
|
||||
{
|
||||
RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOD, ENABLE);
|
||||
RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOD, DISABLE);
|
||||
}
|
||||
else if(GPIOx == GPIOE)
|
||||
{
|
||||
RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOE, ENABLE);
|
||||
RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOE, DISABLE);
|
||||
}
|
||||
else if(GPIOx == GPIOF)
|
||||
{
|
||||
RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOF, ENABLE);
|
||||
RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOF, DISABLE);
|
||||
}
|
||||
else if(GPIOx == GPIOG)
|
||||
{
|
||||
RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOG, ENABLE);
|
||||
RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOG, DISABLE);
|
||||
}
|
||||
else
|
||||
{
|
||||
if(GPIOx == GPIOH)
|
||||
{
|
||||
RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOH, ENABLE);
|
||||
RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOH, DISABLE);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the GPIOx peripheral according to the specified
|
||||
* parameters in the GPIO_InitStruct.
|
||||
* @param GPIOx: where x can be (A..H) to select the GPIO peripheral.
|
||||
* @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that
|
||||
* contains the configuration information for the specified GPIO
|
||||
* peripheral.
|
||||
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct)
|
||||
{
|
||||
uint32_t pinpos = 0x00, pos = 0x00 , currentpin = 0x00;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin));
|
||||
assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode));
|
||||
assert_param(IS_GPIO_PUPD(GPIO_InitStruct->GPIO_PuPd));
|
||||
|
||||
/* -------------------------Configure the port pins---------------- */
|
||||
/*-- GPIO Mode Configuration --*/
|
||||
for (pinpos = 0x00; pinpos < 0x10; pinpos++)
|
||||
{
|
||||
pos = ((uint32_t)0x01) << pinpos;
|
||||
|
||||
/* Get the port pins position */
|
||||
currentpin = (GPIO_InitStruct->GPIO_Pin) & pos;
|
||||
|
||||
if (currentpin == pos)
|
||||
{
|
||||
GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (pinpos * 2));
|
||||
|
||||
GPIOx->MODER |= (((uint32_t)GPIO_InitStruct->GPIO_Mode) << (pinpos * 2));
|
||||
|
||||
if ((GPIO_InitStruct->GPIO_Mode == GPIO_Mode_OUT) || (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_AF))
|
||||
{
|
||||
/* Check Speed mode parameters */
|
||||
assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed));
|
||||
|
||||
/* Speed mode configuration */
|
||||
GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (pinpos * 2));
|
||||
GPIOx->OSPEEDR |= ((uint32_t)(GPIO_InitStruct->GPIO_Speed) << (pinpos * 2));
|
||||
|
||||
/*Check Output mode parameters */
|
||||
assert_param(IS_GPIO_OTYPE(GPIO_InitStruct->GPIO_OType));
|
||||
|
||||
/* Output mode configuration */
|
||||
GPIOx->OTYPER &= ~((GPIO_OTYPER_OT_0) << ((uint16_t)pinpos)) ;
|
||||
GPIOx->OTYPER |= (uint16_t)(((uint16_t)GPIO_InitStruct->GPIO_OType) << ((uint16_t)pinpos));
|
||||
}
|
||||
|
||||
/* Pull-up Pull down resistor configuration */
|
||||
GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << ((uint16_t)pinpos * 2));
|
||||
GPIOx->PUPDR |= (((uint32_t)GPIO_InitStruct->GPIO_PuPd) << (pinpos * 2));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Fills each GPIO_InitStruct member with its default value.
|
||||
* @param GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure which will
|
||||
* be initialized.
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct)
|
||||
{
|
||||
/* Reset GPIO init structure parameters values */
|
||||
GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All;
|
||||
GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN;
|
||||
GPIO_InitStruct->GPIO_Speed = GPIO_Speed_400KHz;
|
||||
GPIO_InitStruct->GPIO_OType = GPIO_OType_PP;
|
||||
GPIO_InitStruct->GPIO_PuPd = GPIO_PuPd_NOPULL;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Locks GPIO Pins configuration registers.
|
||||
* The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,
|
||||
* GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
|
||||
* The configuration of the locked GPIO pins can no longer be modified
|
||||
* until the next reset.
|
||||
* @param GPIOx: where x can be (A..H) to select the GPIO peripheral.
|
||||
* @param GPIO_Pin: specifies the port bit to be written.
|
||||
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
|
||||
{
|
||||
__IO uint32_t tmp = 0x00010000;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
||||
|
||||
tmp |= GPIO_Pin;
|
||||
/* Set LCKK bit */
|
||||
GPIOx->LCKR = tmp;
|
||||
/* Reset LCKK bit */
|
||||
GPIOx->LCKR = GPIO_Pin;
|
||||
/* Set LCKK bit */
|
||||
GPIOx->LCKR = tmp;
|
||||
/* Read LCKK bit*/
|
||||
tmp = GPIOx->LCKR;
|
||||
/* Read LCKK bit*/
|
||||
tmp = GPIOx->LCKR;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Group2 GPIO Read and Write
|
||||
* @brief GPIO Read and Write
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### GPIO Read and Write #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Reads the specified input port pin.
|
||||
* @param GPIOx: where x can be (A..H) to select the GPIO peripheral.
|
||||
* @param GPIO_Pin: specifies the port bit to read.
|
||||
* This parameter can be GPIO_Pin_x where x can be (0..15).
|
||||
* @retval The input port pin value.
|
||||
*/
|
||||
uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
|
||||
{
|
||||
uint8_t bitstatus = 0x00;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
|
||||
|
||||
if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)Bit_RESET)
|
||||
{
|
||||
bitstatus = (uint8_t)Bit_SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = (uint8_t)Bit_RESET;
|
||||
}
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reads the specified GPIO input data port.
|
||||
* @param GPIOx: where x can be (A..H) to select the GPIO peripheral.
|
||||
* @retval GPIO input data port value.
|
||||
*/
|
||||
uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
|
||||
return ((uint16_t)GPIOx->IDR);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reads the specified output data port bit.
|
||||
* @param GPIOx: where x can be (A..H) to select the GPIO peripheral.
|
||||
* @param GPIO_Pin: Specifies the port bit to read.
|
||||
* This parameter can be GPIO_Pin_x where x can be (0..15).
|
||||
* @retval The output port pin value.
|
||||
*/
|
||||
uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
|
||||
{
|
||||
uint8_t bitstatus = 0x00;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
|
||||
|
||||
if ((GPIOx->ODR & GPIO_Pin) != (uint32_t)Bit_RESET)
|
||||
{
|
||||
bitstatus = (uint8_t)Bit_SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = (uint8_t)Bit_RESET;
|
||||
}
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reads the specified GPIO output data port.
|
||||
* @param GPIOx: where x can be (A..H) to select the GPIO peripheral.
|
||||
* @retval GPIO output data port value.
|
||||
*/
|
||||
uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
|
||||
return ((uint16_t)GPIOx->ODR);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets the selected data port bits.
|
||||
* @param GPIOx: where x can be (A..H) to select the GPIO peripheral.
|
||||
* @param GPIO_Pin: specifies the port bits to be written.
|
||||
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
|
||||
* @note This functions uses GPIOx_BSRR register to allow atomic read/modify
|
||||
* accesses. In this way, there is no risk of an IRQ occurring between
|
||||
* the read and the modify access.
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
||||
|
||||
GPIOx->BSRRL = GPIO_Pin;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the selected data port bits.
|
||||
* @param GPIOx: where x can be (A..H) to select the GPIO peripheral.
|
||||
* @param GPIO_Pin: specifies the port bits to be written.
|
||||
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
|
||||
* @note This functions uses GPIOx_BSRR register to allow atomic read/modify
|
||||
* accesses. In this way, there is no risk of an IRQ occurring between
|
||||
* the read and the modify access.
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
||||
|
||||
GPIOx->BSRRH = GPIO_Pin;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets or clears the selected data port bit.
|
||||
* @param GPIOx: where x can be (A..H) to select the GPIO peripheral.
|
||||
* @param GPIO_Pin: specifies the port bit to be written.
|
||||
* This parameter can be one of GPIO_Pin_x where x can be (0..15).
|
||||
* @param BitVal: specifies the value to be written to the selected bit.
|
||||
* This parameter can be one of the BitAction enum values:
|
||||
* @arg Bit_RESET: to clear the port pin
|
||||
* @arg Bit_SET: to set the port pin
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
|
||||
assert_param(IS_GPIO_BIT_ACTION(BitVal));
|
||||
|
||||
if (BitVal != Bit_RESET)
|
||||
{
|
||||
GPIOx->BSRRL = GPIO_Pin;
|
||||
}
|
||||
else
|
||||
{
|
||||
GPIOx->BSRRH = GPIO_Pin ;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Writes data to the specified GPIO data port.
|
||||
* @param GPIOx: where x can be (A..H) to select the GPIO peripheral.
|
||||
* @param PortVal: specifies the value to be written to the port output data
|
||||
* register.
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
|
||||
GPIOx->ODR = PortVal;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Toggles the specified GPIO pins..
|
||||
* @param GPIOx: where x can be (A..H) to select the GPIO peripheral.
|
||||
* @param GPIO_Pin: Specifies the pins to be toggled.
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_ToggleBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
|
||||
GPIOx->ODR ^= GPIO_Pin;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup GPIO_Group3 GPIO Alternate functions configuration functions
|
||||
* @brief GPIO Alternate functions configuration functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### GPIO Alternate functions configuration functions #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Changes the mapping of the specified pin.
|
||||
* @param GPIOx: where x can be (A..H) to select the GPIO peripheral.
|
||||
* @param GPIO_PinSource: specifies the pin for the Alternate function.
|
||||
* This parameter can be GPIO_PinSourcex where x can be (0..15).
|
||||
* @param GPIO_AFSelection: selects the pin to used as Alternat function.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg GPIO_AF_RTC_50Hz: RTC 50/60 Hz synchronization
|
||||
* @arg GPIO_AF_MCO: Microcontroller clock output
|
||||
* @arg GPIO_AF_RTC_AF1: Time stamp, Tamper, Alarm A out, Alarm B out,
|
||||
* 512 Hz clock output (with an LSE oscillator of 32.768 kHz)
|
||||
* @arg GPIO_AF_WKUP: wakeup
|
||||
* @arg GPIO_AF_SWJ: SWJ (SW and JTAG)
|
||||
* @arg GPIO_AF_TRACE: Connect TRACE pins to AF0 (default after reset)
|
||||
* @arg GPIO_AF_TIM2c: Connect TIM2 pins to AF1
|
||||
* @arg GPIO_AF_TIM3: Connect TIM3 pins to AF2
|
||||
* @arg GPIO_AF_TIM4: Connect TIM4 pins to AF2
|
||||
* @arg GPIO_AF_TIM5: Connect TIM5 pins to AF2
|
||||
* @arg GPIO_AF_TIM9: Connect TIM9 pins to AF3
|
||||
* @arg GPIO_AF_TIM10: Connect TIM10 pins to AF3
|
||||
* @arg GPIO_AF_TIM11: Connect TIM11 pins to AF3
|
||||
* @arg GPIO_AF_I2C1: Connect I2C1 pins to AF4
|
||||
* @arg GPIO_AF_I2C2: Connect I2C2 pins to AF4
|
||||
* @arg GPIO_AF_SPI1: Connect SPI1 pins to AF5
|
||||
* @arg GPIO_AF_SPI2: Connect SPI2/I2S2 pins to AF5
|
||||
* @arg GPIO_AF_SPI3: Connect SPI3/I2S3 pins to AF6
|
||||
* @arg GPIO_AF_USART1: Connect USART1 pins to AF7
|
||||
* @arg GPIO_AF_USART2: Connect USART2 pins to AF7
|
||||
* @arg GPIO_AF_USART3: Connect USART3 pins to AF7
|
||||
* @arg GPIO_AF_UART4: Connect UART4 pins to AF8
|
||||
* @arg GPIO_AF_UART5: Connect UART5 pins to AF8
|
||||
* @arg GPIO_AF_USB: Connect USB pins to AF10
|
||||
* @arg GPIO_AF_LCD: Connect LCD pins to AF11
|
||||
* @arg GPIO_AF_FSMC: Connect FSMC pins to AF12
|
||||
* @arg GPIO_AF_SDIO: Connect SDIO pins to AF12
|
||||
* @arg GPIO_AF_RI: Connect RI pins to AF14
|
||||
* @arg GPIO_AF_EVENTOUT: Cortex-M3 EVENTOUT signal
|
||||
* @note The pin should already been configured in Alternate Function mode(AF)
|
||||
* using GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF
|
||||
* @note Please refer to the Alternate function mapping table in the device
|
||||
* datasheet for the detailed mapping of the system and peripherals'
|
||||
* alternate function I/O pins.
|
||||
* @note EVENTOUT is not mapped on PH0, PH1 and PH2.
|
||||
* @retval None
|
||||
*/
|
||||
void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF)
|
||||
{
|
||||
uint32_t temp = 0x00;
|
||||
uint32_t temp_2 = 0x00;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
|
||||
assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource));
|
||||
assert_param(IS_GPIO_AF(GPIO_AF));
|
||||
|
||||
temp = ((uint32_t)(GPIO_AF) << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4)) ;
|
||||
GPIOx->AFR[GPIO_PinSource >> 0x03] &= ~((uint32_t)0xF << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4)) ;
|
||||
temp_2 = GPIOx->AFR[GPIO_PinSource >> 0x03] | temp;
|
||||
GPIOx->AFR[GPIO_PinSource >> 0x03] = temp_2;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,266 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32l1xx_iwdg.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.1
|
||||
* @date 05-March-2012
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the Independent watchdog (IWDG) peripheral:
|
||||
* + Prescaler and Counter configuration
|
||||
* + IWDG activation
|
||||
* + Flag management
|
||||
*
|
||||
* @verbatim
|
||||
*
|
||||
==============================================================================
|
||||
##### IWDG features #####
|
||||
==============================================================================
|
||||
[..] The IWDG can be started by either software or hardware (configurable
|
||||
through option byte).
|
||||
|
||||
[..] The IWDG is clocked by its own dedicated low-speed clock (LSI) and
|
||||
thus stays active even if the main clock fails.
|
||||
Once the IWDG is started, the LSI is forced ON and cannot be disabled
|
||||
(LSI cannot be disabled too), and the counter starts counting down from
|
||||
the reset value of 0xFFF. When it reaches the end of count value (0x000)
|
||||
a system reset is generated.
|
||||
The IWDG counter should be reloaded at regular intervals to prevent
|
||||
an MCU reset.
|
||||
|
||||
[..] The IWDG is implemented in the VDD voltage domain that is still functional
|
||||
in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY).
|
||||
|
||||
[..] IWDGRST flag in RCC_CSR register can be used to inform when a IWDG
|
||||
reset occurs.
|
||||
|
||||
[..] Min-max timeout value @37KHz (LSI): ~108us / ~28.3s
|
||||
The IWDG timeout may vary due to LSI frequency dispersion. STM32L1xx
|
||||
devices provide the capability to measure the LSI frequency (LSI clock
|
||||
connected internally to TIM10 CH1 input capture). The measured value
|
||||
can be used to have an IWDG timeout with an acceptable accuracy.
|
||||
For more information, please refer to the STM32L1xx Reference manual.
|
||||
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
(#) Enable write access to IWDG_PR and IWDG_RLR registers using
|
||||
IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable) function.
|
||||
(#) Configure the IWDG prescaler using IWDG_SetPrescaler() function.
|
||||
|
||||
(#) Configure the IWDG counter value using IWDG_SetReload() function.
|
||||
This value will be loaded in the IWDG counter each time the counter
|
||||
is reloaded, then the IWDG will start counting down from this value.
|
||||
|
||||
(#) Start the IWDG using IWDG_Enable() function, when the IWDG is used
|
||||
in software mode (no need to enable the LSI, it will be enabled
|
||||
by hardware).
|
||||
|
||||
(#) Then the application program must reload the IWDG counter at regular
|
||||
intervals during normal operation to prevent an MCU reset, using
|
||||
IWDG_ReloadCounter() function.
|
||||
|
||||
@endverbatim
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32l1xx_iwdg.h"
|
||||
|
||||
/** @addtogroup STM32L1xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG
|
||||
* @brief IWDG driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* ---------------------- IWDG registers bit mask ----------------------------*/
|
||||
/* KR register bit mask */
|
||||
#define KR_KEY_RELOAD ((uint16_t)0xAAAA)
|
||||
#define KR_KEY_ENABLE ((uint16_t)0xCCCC)
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup IWDG_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_Group1 Prescaler and Counter configuration functions
|
||||
* @brief Prescaler and Counter configuration functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### Prescaler and Counter configuration functions #####
|
||||
==============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enables or disables write access to IWDG_PR and IWDG_RLR registers.
|
||||
* @param IWDG_WriteAccess: new state of write access to IWDG_PR and IWDG_RLR registers.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg IWDG_WriteAccess_Enable: Enable write access to IWDG_PR and IWDG_RLR registers
|
||||
* @arg IWDG_WriteAccess_Disable: Disable write access to IWDG_PR and IWDG_RLR registers
|
||||
* @retval None
|
||||
*/
|
||||
void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_IWDG_WRITE_ACCESS(IWDG_WriteAccess));
|
||||
IWDG->KR = IWDG_WriteAccess;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets IWDG Prescaler value.
|
||||
* @param IWDG_Prescaler: specifies the IWDG Prescaler value.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg IWDG_Prescaler_4: IWDG prescaler set to 4
|
||||
* @arg IWDG_Prescaler_8: IWDG prescaler set to 8
|
||||
* @arg IWDG_Prescaler_16: IWDG prescaler set to 16
|
||||
* @arg IWDG_Prescaler_32: IWDG prescaler set to 32
|
||||
* @arg IWDG_Prescaler_64: IWDG prescaler set to 64
|
||||
* @arg IWDG_Prescaler_128: IWDG prescaler set to 128
|
||||
* @arg IWDG_Prescaler_256: IWDG prescaler set to 256
|
||||
* @retval None
|
||||
*/
|
||||
void IWDG_SetPrescaler(uint8_t IWDG_Prescaler)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_IWDG_PRESCALER(IWDG_Prescaler));
|
||||
IWDG->PR = IWDG_Prescaler;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets IWDG Reload value.
|
||||
* @param Reload: specifies the IWDG Reload value.
|
||||
* This parameter must be a number between 0 and 0x0FFF.
|
||||
* @retval None
|
||||
*/
|
||||
void IWDG_SetReload(uint16_t Reload)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_IWDG_RELOAD(Reload));
|
||||
IWDG->RLR = Reload;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Reloads IWDG counter with value defined in the reload register
|
||||
* (write access to IWDG_PR and IWDG_RLR registers disabled).
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void IWDG_ReloadCounter(void)
|
||||
{
|
||||
IWDG->KR = KR_KEY_RELOAD;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_Group2 IWDG activation function
|
||||
* @brief IWDG activation function
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### IWDG activation function #####
|
||||
==============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled).
|
||||
* @param None.
|
||||
* @retval None.
|
||||
*/
|
||||
void IWDG_Enable(void)
|
||||
{
|
||||
IWDG->KR = KR_KEY_ENABLE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup IWDG_Group3 Flag management function
|
||||
* @brief Flag management function
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Flag management function #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified IWDG flag is set or not.
|
||||
* @param IWDG_FLAG: specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg IWDG_FLAG_PVU: Prescaler Value Update on going
|
||||
* @arg IWDG_FLAG_RVU: Reload Value Update on going
|
||||
* @retval The new state of IWDG_FLAG (SET or RESET).
|
||||
*/
|
||||
FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG)
|
||||
{
|
||||
FlagStatus bitstatus = RESET;
|
||||
/* Check the parameters */
|
||||
assert_param(IS_IWDG_FLAG(IWDG_FLAG));
|
||||
if ((IWDG->SR & IWDG_FLAG) != (uint32_t)RESET)
|
||||
{
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = RESET;
|
||||
}
|
||||
/* Return the flag status */
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,640 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32l1xx_lcd.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.1
|
||||
* @date 05-March-2012
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the LCD controller (LCD) peripheral:
|
||||
* + Initialization and configuration
|
||||
* + LCD RAM memory write
|
||||
* + Interrupts and flags management
|
||||
*
|
||||
* @verbatim
|
||||
|
||||
===============================================================================
|
||||
##### LCD Clock #####
|
||||
===============================================================================
|
||||
[..] LCDCLK is the same as RTCCLK.
|
||||
[..] To configure the RTCCLK/LCDCLK, proceed as follows:
|
||||
(+) Enable the Power Controller (PWR) APB1 interface clock using the
|
||||
RCC_APB1PeriphClockCmd() function.
|
||||
(+) Enable access to RTC domain using the PWR_RTCAccessCmd() function.
|
||||
(+) Select the RTC clock source using the RCC_RTCCLKConfig() function.
|
||||
|
||||
[..] The frequency generator allows you to achieve various LCD frame rates
|
||||
starting from an LCD input clock frequency (LCDCLK) which can vary
|
||||
from 32 kHz up to 1 MHz.
|
||||
|
||||
##### LCD and low power modes #####
|
||||
===============================================================================
|
||||
[..] The LCD still active during STOP mode.
|
||||
|
||||
##### How to use this driver #####
|
||||
===============================================================================
|
||||
[..]
|
||||
(#) Enable LCD clock using
|
||||
RCC_APB1PeriphClockCmd(RCC_APB1Periph_LCD, ENABLE) function.
|
||||
(#) Configure the LCD prescaler, divider, duty, bias and voltage source
|
||||
using LCD_Init() function.
|
||||
(#) Optionally you can enable/configure:
|
||||
(++) LCD High Drive using the LCD_HighDriveCmd() function.
|
||||
(++) LCD COM/SEG Mux using the LCD_MuxSegmentCmd() function.
|
||||
(++) LCD Pulse ON Duration using the LCD_PulseOnDurationConfig() function.
|
||||
(++) LCD Dead Time using the LCD_DeadTimeConfig() function
|
||||
(++) The LCD Blink mode and frequency using the LCD_BlinkConfig() function.
|
||||
(++) The LCD Contrast using the LCD_ContrastConfig() function.
|
||||
(#) Call the LCD_WaitForSynchro() function to wait for LCD_FCR register
|
||||
synchronization.
|
||||
(#) Call the LCD_Cmd() to enable the LCD controller.
|
||||
(#) Wait until the LCD Controller status is enabled and the step-up
|
||||
converter is ready using the LCD_GetFlagStatus() and
|
||||
LCD_FLAG_ENS and LCD_FLAG_RDY flags.
|
||||
(#) Write to the LCD RAM memory using the LCD_Write() function.
|
||||
(#) Request an update display using the LCD_UpdateDisplayRequest()
|
||||
function.
|
||||
(#) Wait until the update display is finished by checking the UDD
|
||||
flag status using the LCD_GetFlagStatus(LCD_FLAG_UDD).
|
||||
|
||||
@endverbatim
|
||||
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32l1xx_lcd.h"
|
||||
#include "stm32l1xx_rcc.h"
|
||||
|
||||
/** @addtogroup STM32L1xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup LCD
|
||||
* @brief LCD driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* ------------ LCD registers bit address in the alias region --------------- */
|
||||
#define LCD_OFFSET (LCD_BASE - PERIPH_BASE)
|
||||
|
||||
/* --- CR Register ---*/
|
||||
|
||||
/* Alias word address of LCDEN bit */
|
||||
#define CR_OFFSET (LCD_OFFSET + 0x00)
|
||||
#define LCDEN_BitNumber 0x00
|
||||
#define CR_LCDEN_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (LCDEN_BitNumber * 4))
|
||||
|
||||
/* Alias word address of MUX_SEG bit */
|
||||
#define MUX_SEG_BitNumber 0x07
|
||||
#define CR_MUX_SEG_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (MUX_SEG_BitNumber * 4))
|
||||
|
||||
|
||||
/* --- FCR Register ---*/
|
||||
|
||||
/* Alias word address of HD bit */
|
||||
#define FCR_OFFSET (LCD_OFFSET + 0x04)
|
||||
#define HD_BitNumber 0x00
|
||||
#define FCR_HD_BB (PERIPH_BB_BASE + (FCR_OFFSET * 32) + (HD_BitNumber * 4))
|
||||
|
||||
/* --- SR Register ---*/
|
||||
|
||||
/* Alias word address of UDR bit */
|
||||
#define SR_OFFSET (LCD_OFFSET + 0x08)
|
||||
#define UDR_BitNumber 0x02
|
||||
#define SR_UDR_BB (PERIPH_BB_BASE + (SR_OFFSET * 32) + (UDR_BitNumber * 4))
|
||||
|
||||
#define FCR_MASK ((uint32_t)0xFC03FFFF) /* LCD FCR Mask */
|
||||
#define CR_MASK ((uint32_t)0xFFFFFF81) /* LCD CR Mask */
|
||||
#define PON_MASK ((uint32_t)0xFFFFFF8F) /* LCD PON Mask */
|
||||
#define DEAD_MASK ((uint32_t)0xFFFFFC7F) /* LCD DEAD Mask */
|
||||
#define BLINK_MASK ((uint32_t)0xFFFC1FFF) /* LCD BLINK Mask */
|
||||
#define CONTRAST_MASK ((uint32_t)0xFFFFE3FF) /* LCD CONTRAST Mask */
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup LCD_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup LCD_Group1 Initialization and Configuration functions
|
||||
* @brief Initialization and Configuration functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Initialization and Configuration functions #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the LCD peripheral registers to their default reset
|
||||
* values.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void LCD_DeInit(void)
|
||||
{
|
||||
/* Enable LCD reset state */
|
||||
RCC_APB1PeriphResetCmd(RCC_APB1Periph_LCD, ENABLE);
|
||||
/* Release LCD from reset state */
|
||||
RCC_APB1PeriphResetCmd(RCC_APB1Periph_LCD, DISABLE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the LCD peripheral according to the specified parameters
|
||||
* in the LCD_InitStruct.
|
||||
* @note This function can be used only when the LCD is disabled.
|
||||
* @param LCD_InitStruct: pointer to a LCD_InitTypeDef structure that contains
|
||||
* the configuration information for the specified LCD peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
void LCD_Init(LCD_InitTypeDef* LCD_InitStruct)
|
||||
{
|
||||
/* Check function parameters */
|
||||
assert_param(IS_LCD_PRESCALER(LCD_InitStruct->LCD_Prescaler));
|
||||
assert_param(IS_LCD_DIVIDER(LCD_InitStruct->LCD_Divider));
|
||||
assert_param(IS_LCD_DUTY(LCD_InitStruct->LCD_Duty));
|
||||
assert_param(IS_LCD_BIAS(LCD_InitStruct->LCD_Bias));
|
||||
assert_param(IS_LCD_VOLTAGE_SOURCE(LCD_InitStruct->LCD_VoltageSource));
|
||||
|
||||
LCD->FCR &= (uint32_t)FCR_MASK;
|
||||
LCD->FCR |= (uint32_t)(LCD_InitStruct->LCD_Prescaler | LCD_InitStruct->LCD_Divider);
|
||||
|
||||
LCD_WaitForSynchro();
|
||||
|
||||
LCD->CR &= (uint32_t)CR_MASK;
|
||||
LCD->CR |= (uint32_t)(LCD_InitStruct->LCD_Duty | LCD_InitStruct->LCD_Bias | \
|
||||
LCD_InitStruct->LCD_VoltageSource);
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Fills each LCD_InitStruct member with its default value.
|
||||
* @param LCD_InitStruct: pointer to a LCD_InitTypeDef structure which will
|
||||
* be initialized.
|
||||
* @retval None
|
||||
*/
|
||||
void LCD_StructInit(LCD_InitTypeDef* LCD_InitStruct)
|
||||
{
|
||||
/*--------------- Reset LCD init structure parameters values -----------------*/
|
||||
LCD_InitStruct->LCD_Prescaler = LCD_Prescaler_1; /*!< Initialize the LCD_Prescaler member */
|
||||
|
||||
LCD_InitStruct->LCD_Divider = LCD_Divider_16; /*!< Initialize the LCD_Divider member */
|
||||
|
||||
LCD_InitStruct->LCD_Duty = LCD_Duty_Static; /*!< Initialize the LCD_Duty member */
|
||||
|
||||
LCD_InitStruct->LCD_Bias = LCD_Bias_1_4; /*!< Initialize the LCD_Bias member */
|
||||
|
||||
LCD_InitStruct->LCD_VoltageSource = LCD_VoltageSource_Internal; /*!< Initialize the LCD_VoltageSource member */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the LCD Controller.
|
||||
* @param NewState: new state of the LCD peripheral.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void LCD_Cmd(FunctionalState NewState)
|
||||
{
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
*(__IO uint32_t *) CR_LCDEN_BB = (uint32_t)NewState;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Waits until the LCD FCR register is synchronized in the LCDCLK domain.
|
||||
* This function must be called after any write operation to LCD_FCR register.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void LCD_WaitForSynchro(void)
|
||||
{
|
||||
/* Loop until FCRSF flag is set */
|
||||
while ((LCD->SR & LCD_FLAG_FCRSF) == (uint32_t)RESET)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the low resistance divider. Displays with high
|
||||
* internal resistance may need a longer drive time to achieve
|
||||
* satisfactory contrast. This function is useful in this case if some
|
||||
* additional power consumption can be tolerated.
|
||||
* @note When this mode is enabled, the PulseOn Duration (PON) have to be
|
||||
* programmed to 1/CK_PS (LCD_PulseOnDuration_1).
|
||||
* @param NewState: new state of the low resistance divider.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void LCD_HighDriveCmd(FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
*(__IO uint32_t *) FCR_HD_BB = (uint32_t)NewState;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the Mux Segment.
|
||||
* @note This function can be used only when the LCD is disabled.
|
||||
* @param NewState: new state of the Mux Segment.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void LCD_MuxSegmentCmd(FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
*(__IO uint32_t *) CR_MUX_SEG_BB = (uint32_t)NewState;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures the LCD pulses on duration.
|
||||
* @param LCD_PulseOnDuration: specifies the LCD pulse on duration in terms of
|
||||
* CK_PS (prescaled LCD clock period) pulses.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg LCD_PulseOnDuration_0: 0 pulse
|
||||
* @arg LCD_PulseOnDuration_1: Pulse ON duration = 1/CK_PS
|
||||
* @arg LCD_PulseOnDuration_2: Pulse ON duration = 2/CK_PS
|
||||
* @arg LCD_PulseOnDuration_3: Pulse ON duration = 3/CK_PS
|
||||
* @arg LCD_PulseOnDuration_4: Pulse ON duration = 4/CK_PS
|
||||
* @arg LCD_PulseOnDuration_5: Pulse ON duration = 5/CK_PS
|
||||
* @arg LCD_PulseOnDuration_6: Pulse ON duration = 6/CK_PS
|
||||
* @arg LCD_PulseOnDuration_7: Pulse ON duration = 7/CK_PS
|
||||
* @retval None
|
||||
*/
|
||||
void LCD_PulseOnDurationConfig(uint32_t LCD_PulseOnDuration)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_LCD_PULSE_ON_DURATION(LCD_PulseOnDuration));
|
||||
|
||||
LCD->FCR &= (uint32_t)PON_MASK;
|
||||
LCD->FCR |= (uint32_t)(LCD_PulseOnDuration);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures the LCD dead time.
|
||||
* @param LCD_DeadTime: specifies the LCD dead time.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg LCD_DeadTime_0: No dead Time
|
||||
* @arg LCD_DeadTime_1: One Phase between different couple of Frame
|
||||
* @arg LCD_DeadTime_2: Two Phase between different couple of Frame
|
||||
* @arg LCD_DeadTime_3: Three Phase between different couple of Frame
|
||||
* @arg LCD_DeadTime_4: Four Phase between different couple of Frame
|
||||
* @arg LCD_DeadTime_5: Five Phase between different couple of Frame
|
||||
* @arg LCD_DeadTime_6: Six Phase between different couple of Frame
|
||||
* @arg LCD_DeadTime_7: Seven Phase between different couple of Frame
|
||||
* @retval None
|
||||
*/
|
||||
void LCD_DeadTimeConfig(uint32_t LCD_DeadTime)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_LCD_DEAD_TIME(LCD_DeadTime));
|
||||
|
||||
LCD->FCR &= (uint32_t)DEAD_MASK;
|
||||
LCD->FCR |= (uint32_t)(LCD_DeadTime);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures the LCD Blink mode and Blink frequency.
|
||||
* @param LCD_BlinkMode: specifies the LCD blink mode.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg LCD_BlinkMode_Off: Blink disabled
|
||||
* @arg LCD_BlinkMode_SEG0_COM0: Blink enabled on SEG[0], COM[0] (1 pixel)
|
||||
* @arg LCD_BlinkMode_SEG0_AllCOM: Blink enabled on SEG[0], all COM (up to 8
|
||||
* pixels according to the programmed duty)
|
||||
* @arg LCD_BlinkMode_AllSEG_AllCOM: Blink enabled on all SEG and all COM
|
||||
* (all pixels)
|
||||
* @param LCD_BlinkFrequency: specifies the LCD blink frequency.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg LCD_BlinkFrequency_Div8: The Blink frequency = fLcd/8
|
||||
* @arg LCD_BlinkFrequency_Div16: The Blink frequency = fLcd/16
|
||||
* @arg LCD_BlinkFrequency_Div32: The Blink frequency = fLcd/32
|
||||
* @arg LCD_BlinkFrequency_Div64: The Blink frequency = fLcd/64
|
||||
* @arg LCD_BlinkFrequency_Div128: The Blink frequency = fLcd/128
|
||||
* @arg LCD_BlinkFrequency_Div256: The Blink frequency = fLcd/256
|
||||
* @arg LCD_BlinkFrequency_Div512: The Blink frequency = fLcd/512
|
||||
* @arg LCD_BlinkFrequency_Div1024: The Blink frequency = fLcd/1024
|
||||
* @retval None
|
||||
*/
|
||||
void LCD_BlinkConfig(uint32_t LCD_BlinkMode, uint32_t LCD_BlinkFrequency)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_LCD_BLINK_MODE(LCD_BlinkMode));
|
||||
assert_param(IS_LCD_BLINK_FREQUENCY(LCD_BlinkFrequency));
|
||||
|
||||
LCD->FCR &= (uint32_t)BLINK_MASK;
|
||||
LCD->FCR |= (uint32_t)(LCD_BlinkMode | LCD_BlinkFrequency);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures the LCD Contrast.
|
||||
* @param LCD_Contrast: specifies the LCD Contrast.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg LCD_Contrast_Level_0: Maximum Voltage = 2.60V
|
||||
* @arg LCD_Contrast_Level_1: Maximum Voltage = 2.73V
|
||||
* @arg LCD_Contrast_Level_2: Maximum Voltage = 2.86V
|
||||
* @arg LCD_Contrast_Level_3: Maximum Voltage = 2.99V
|
||||
* @arg LCD_Contrast_Level_4: Maximum Voltage = 3.12V
|
||||
* @arg LCD_Contrast_Level_5: Maximum Voltage = 3.25V
|
||||
* @arg LCD_Contrast_Level_6: Maximum Voltage = 3.38V
|
||||
* @arg LCD_Contrast_Level_7: Maximum Voltage = 3.51V
|
||||
* @retval None
|
||||
*/
|
||||
void LCD_ContrastConfig(uint32_t LCD_Contrast)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_LCD_CONTRAST(LCD_Contrast));
|
||||
|
||||
LCD->FCR &= (uint32_t)CONTRAST_MASK;
|
||||
LCD->FCR |= (uint32_t)(LCD_Contrast);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LCD_Group2 LCD RAM memory write functions
|
||||
* @brief LCD RAM memory write functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### LCD RAM memory write functions #####
|
||||
===============================================================================
|
||||
[..] Using its double buffer memory the LCD controller ensures the coherency
|
||||
of the displayed information without having to use interrupts to control
|
||||
LCD_RAM modification.
|
||||
|
||||
[..] The application software can access the first buffer level (LCD_RAM) through
|
||||
the APB interface. Once it has modified the LCD_RAM, it sets the UDR flag
|
||||
in the LCD_SR register using the LCD_UpdateDisplayRequest() function.
|
||||
|
||||
[..] This UDR flag (update display request) requests the updated information
|
||||
to be moved into the second buffer level (LCD_DISPLAY).
|
||||
|
||||
[..] This operation is done synchronously with the frame (at the beginning of
|
||||
the next frame), until the update is completed, the LCD_RAM is write
|
||||
protected and the UDR flag stays high.
|
||||
|
||||
[..] Once the update is completed another flag (UDD - Update Display Done) is
|
||||
set and generates an interrupt if the UDDIE bit in the LCD_FCR register
|
||||
is set.
|
||||
|
||||
[..] The time it takes to update LCD_DISPLAY is, in the worst case, one odd
|
||||
and one even frame.
|
||||
|
||||
[..] The update will not occur (UDR = 1 and UDD = 0) until the display is
|
||||
enabled (LCDEN = 1).
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Writes a word in the specific LCD RAM.
|
||||
* @param LCD_RAMRegister: specifies the LCD Contrast.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg LCD_RAMRegister_0: LCD RAM Register 0
|
||||
* @arg LCD_RAMRegister_1: LCD RAM Register 1
|
||||
* @arg LCD_RAMRegister_2: LCD RAM Register 2
|
||||
* @arg LCD_RAMRegister_3: LCD RAM Register 3
|
||||
* @arg LCD_RAMRegister_4: LCD RAM Register 4
|
||||
* @arg LCD_RAMRegister_5: LCD RAM Register 5
|
||||
* @arg LCD_RAMRegister_6: LCD RAM Register 6
|
||||
* @arg LCD_RAMRegister_7: LCD RAM Register 7
|
||||
* @arg LCD_RAMRegister_8: LCD RAM Register 8
|
||||
* @arg LCD_RAMRegister_9: LCD RAM Register 9
|
||||
* @arg LCD_RAMRegister_10: LCD RAM Register 10
|
||||
* @arg LCD_RAMRegister_11: LCD RAM Register 11
|
||||
* @arg LCD_RAMRegister_12: LCD RAM Register 12
|
||||
* @arg LCD_RAMRegister_13: LCD RAM Register 13
|
||||
* @arg LCD_RAMRegister_14: LCD RAM Register 14
|
||||
* @arg LCD_RAMRegister_15: LCD RAM Register 15
|
||||
* @param LCD_Data: specifies LCD Data Value to be written.
|
||||
* @retval None
|
||||
*/
|
||||
void LCD_Write(uint32_t LCD_RAMRegister, uint32_t LCD_Data)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_LCD_RAM_REGISTER(LCD_RAMRegister));
|
||||
|
||||
/* Copy data bytes to RAM register */
|
||||
LCD->RAM[LCD_RAMRegister] = (uint32_t)LCD_Data;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables the Update Display Request.
|
||||
* @note Each time software modifies the LCD_RAM it must set the UDR bit to
|
||||
* transfer the updated data to the second level buffer.
|
||||
* The UDR bit stays set until the end of the update and during this
|
||||
* time the LCD_RAM is write protected.
|
||||
* @note When the display is disabled, the update is performed for all
|
||||
* LCD_DISPLAY locations.
|
||||
* When the display is enabled, the update is performed only for locations
|
||||
* for which commons are active (depending on DUTY). For example if
|
||||
* DUTY = 1/2, only the LCD_DISPLAY of COM0 and COM1 will be updated.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void LCD_UpdateDisplayRequest(void)
|
||||
{
|
||||
*(__IO uint32_t *) SR_UDR_BB = (uint32_t)0x01;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup LCD_Group3 Interrupts and flags management functions
|
||||
* @brief Interrupts and flags management functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Interrupts and flags management functions #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the specified LCD interrupts.
|
||||
* @param LCD_IT: specifies the LCD interrupts sources to be enabled or disabled.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg LCD_IT_SOF: Start of Frame Interrupt
|
||||
* @arg LCD_IT_UDD: Update Display Done Interrupt
|
||||
* @param NewState: new state of the specified LCD interrupts.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void LCD_ITConfig(uint32_t LCD_IT, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_LCD_IT(LCD_IT));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
LCD->FCR |= LCD_IT;
|
||||
}
|
||||
else
|
||||
{
|
||||
LCD->FCR &= (uint32_t)~LCD_IT;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified LCD flag is set or not.
|
||||
* @param LCD_FLAG: specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg LCD_FLAG_ENS: LCD Enabled flag. It indicates the LCD controller status.
|
||||
* @note The ENS bit is set immediately when the LCDEN bit in the LCD_CR
|
||||
* goes from 0 to 1. On deactivation it reflects the real status of
|
||||
* LCD so it becomes 0 at the end of the last displayed frame.
|
||||
* @arg LCD_FLAG_SOF: Start of Frame flag. This flag is set by hardware at
|
||||
* the beginning of a new frame, at the same time as the display data is
|
||||
* updated.
|
||||
* @arg LCD_FLAG_UDR: Update Display Request flag.
|
||||
* @arg LCD_FLAG_UDD: Update Display Done flag.
|
||||
* @arg LCD_FLAG_RDY: Step_up converter Ready flag. It indicates the status
|
||||
* of the step-up converter.
|
||||
* @arg LCD_FLAG_FCRSF: LCD Frame Control Register Synchronization Flag.
|
||||
* This flag is set by hardware each time the LCD_FCR register is updated
|
||||
* in the LCDCLK domain.
|
||||
* @retval The new state of LCD_FLAG (SET or RESET).
|
||||
*/
|
||||
FlagStatus LCD_GetFlagStatus(uint32_t LCD_FLAG)
|
||||
{
|
||||
FlagStatus bitstatus = RESET;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_LCD_GET_FLAG(LCD_FLAG));
|
||||
|
||||
if ((LCD->SR & LCD_FLAG) != (uint32_t)RESET)
|
||||
{
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = RESET;
|
||||
}
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the LCD's pending flags.
|
||||
* @param LCD_FLAG: specifies the flag to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg LCD_FLAG_SOF: Start of Frame Interrupt
|
||||
* @arg LCD_FLAG_UDD: Update Display Done Interrupt
|
||||
* @retval None
|
||||
*/
|
||||
void LCD_ClearFlag(uint32_t LCD_FLAG)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_LCD_CLEAR_FLAG(LCD_FLAG));
|
||||
|
||||
/* Clear the corresponding LCD flag */
|
||||
LCD->CLR = (uint32_t)LCD_FLAG;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified RTC interrupt has occurred or not.
|
||||
* @param LCD_IT: specifies the LCD interrupts sources to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg LCD_IT_SOF: Start of Frame Interrupt
|
||||
* @arg LCD_IT_UDD: Update Display Done Interrupt.
|
||||
* @note If the device is in STOP mode (PCLK not provided) UDD will not
|
||||
* generate an interrupt even if UDDIE = 1.
|
||||
* If the display is not enabled the UDD interrupt will never occur.
|
||||
* @retval The new state of the LCD_IT (SET or RESET).
|
||||
*/
|
||||
ITStatus LCD_GetITStatus(uint32_t LCD_IT)
|
||||
{
|
||||
ITStatus bitstatus = RESET;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_LCD_GET_IT(LCD_IT));
|
||||
|
||||
if ((LCD->SR & LCD_IT) != (uint16_t)RESET)
|
||||
{
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = RESET;
|
||||
}
|
||||
|
||||
if (((LCD->FCR & LCD_IT) != (uint16_t)RESET) && (bitstatus != (uint32_t)RESET))
|
||||
{
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = RESET;
|
||||
}
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the LCD's interrupt pending bits.
|
||||
* @param LCD_IT: specifies the interrupt pending bit to clear.
|
||||
* This parameter can be any combination of the following values:
|
||||
* @arg LCD_IT_SOF: Start of Frame Interrupt
|
||||
* @arg LCD_IT_UDD: Update Display Done Interrupt
|
||||
* @retval None
|
||||
*/
|
||||
void LCD_ClearITPendingBit(uint32_t LCD_IT)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_LCD_IT(LCD_IT));
|
||||
|
||||
/* Clear the corresponding LCD pending bit */
|
||||
LCD->CLR = (uint32_t)LCD_IT;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,557 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32l1xx_opamp.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.1
|
||||
* @date 05-March-2012
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the operational amplifiers (opamp) peripheral:
|
||||
* + Initialization and configuration
|
||||
* + Calibration management
|
||||
*
|
||||
* @verbatim
|
||||
==============================================================================
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..] The device integrates three independent rail-to-rail operational amplifiers
|
||||
OPAMP1, OPAMP2 and OPAMP3:
|
||||
(+) Internal connections to the ADC.
|
||||
(+) Internal connections to the DAC.
|
||||
(+) Internal connection to COMP1 (only OPAMP3).
|
||||
(+) Internal connection for unity gain (voltage follower) configuration.
|
||||
(+) Calibration capability.
|
||||
(+) Selectable gain-bandwidth (2MHz in normal mode, 500KHz in low power mode).
|
||||
[..]
|
||||
(#) COMP AHB clock must be enabled to get write access
|
||||
to OPAMP registers using
|
||||
(#) RCC_APB1PeriphClockCmd(RCC_APB1Periph_COMP, ENABLE)
|
||||
|
||||
(#) Configure the corresponding GPIO to OPAMPx INP, OPAMPx_INN (if used)
|
||||
and OPAMPx_OUT in analog mode.
|
||||
|
||||
(#) Configure (close/open) the OPAMP switches using OPAMP_SwitchCmd()
|
||||
|
||||
(#) Enable the OPAMP peripheral using OPAMP_Cmd()
|
||||
|
||||
-@- In order to use OPAMP outputs as ADC inputs, the opamps must be enabled
|
||||
and the ADC must use the OPAMP output channel number:
|
||||
(+@) OPAMP1 output is connected to ADC channel 3.
|
||||
(+@) OPAMP2 output is connected to ADC channel 8.
|
||||
(+@) OPAMP3 output is connected to ADC channel 13 (SW1 switch must be closed).
|
||||
|
||||
* @endverbatim
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32l1xx_opamp.h"
|
||||
|
||||
|
||||
/** @addtogroup STM32L1xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup OPAMP
|
||||
* @brief OPAMP driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup OPAMP_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup OPAMP_Group1 Initialization and configuration
|
||||
* @brief Initialization and configuration
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Initialization and configuration #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Deinitialize the OPAMPs register to its default reset value.
|
||||
* @note At startup, OTR and LPOTR registers are set to factory programmed values.
|
||||
* @param None.
|
||||
* @retval None.
|
||||
*/
|
||||
void OPAMP_DeInit(void)
|
||||
{
|
||||
/*!< Set OPAMP_CSR register to reset value */
|
||||
OPAMP->CSR = 0x00010101;
|
||||
/*!< Set OPAMP_OTR register to reset value */
|
||||
OPAMP->OTR = (uint32_t)(* (uint32_t*)FLASH_R_BASE + 0x00000038);
|
||||
/*!< Set OPAMP_LPOTR register to reset value */
|
||||
OPAMP->LPOTR = (uint32_t)(* (uint32_t*)FLASH_R_BASE + 0x0000003C);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Close or Open the OPAMP switches.
|
||||
* @param OPAMP_OPAMPxSwitchy: selects the OPAMPx switch.
|
||||
* This parameter can be any combinations of the following values:
|
||||
* @arg OPAMP_OPAMP1Switch3: used to connect internally OPAMP1 output to
|
||||
* OPAMP1 negative input (internal follower)
|
||||
* @arg OPAMP_OPAMP1Switch4: used to connect PA2 to OPAMP1 negative input
|
||||
* @arg OPAMP_OPAMP1Switch5: used to connect PA1 to OPAMP1 positive input
|
||||
* @arg OPAMP_OPAMP1Switch6: used to connect DAC_OUT1 to OPAMP1 positive input
|
||||
* @arg OPAMP_OPAMP1SwitchANA: used to meet 1 nA input leakage
|
||||
* @arg OPAMP_OPAMP2Switch3: used to connect internally OPAMP2 output to
|
||||
* OPAMP2 negative input (internal follower)
|
||||
* @arg OPAMP_OPAMP2Switch4: used to connect PA7 to OPAMP2 negative input
|
||||
* @arg OPAMP_OPAMP2Switch5: used to connect PA6 to OPAMP2 positive input
|
||||
* @arg OPAMP_OPAMP2Switch6: used to connect DAC_OUT1 to OPAMP2 positive input
|
||||
* @arg OPAMP_OPAMP2Switch7: used to connect DAC_OUT2 to OPAMP2 positive input
|
||||
* @arg OPAMP_OPAMP2SwitchANA: used to meet 1 nA input leakage
|
||||
* @arg OPAMP_OPAMP3Switch3: used to connect internally OPAMP3 output to
|
||||
* OPAMP3 negative input (internal follower)
|
||||
* @arg OPAMP_OPAMP3Switch4: used to connect PC2 to OPAMP3 negative input
|
||||
* @arg OPAMP_OPAMP3Switch5: used to connect PC1 to OPAMP3 positive input
|
||||
* @arg OPAMP_OPAMP3Switch6: used to connect DAC_OUT1 to OPAMP3 positive input
|
||||
* @arg OPAMP_OPAMP3SwitchANA: used to meet 1 nA input leakage on negative input
|
||||
*
|
||||
* @param NewState: New state of the OPAMP switch.
|
||||
* This parameter can be:
|
||||
* ENABLE to close the OPAMP switch
|
||||
* or DISABLE to open the OPAMP switch
|
||||
* @note OPAMP_OPAMP2Switch6 and OPAMP_OPAMP2Switch7 mustn't be closed together.
|
||||
* @retval None
|
||||
*/
|
||||
void OPAMP_SwitchCmd(uint32_t OPAMP_OPAMPxSwitchy, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameter */
|
||||
assert_param(IS_OPAMP_SWITCH(OPAMP_OPAMPxSwitchy));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Close the selected switches */
|
||||
OPAMP->CSR |= (uint32_t) OPAMP_OPAMPxSwitchy;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Open the selected switches */
|
||||
OPAMP->CSR &= (~(uint32_t)OPAMP_OPAMPxSwitchy);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable or disable the OPAMP peripheral.
|
||||
* @param OPAMP_Selection: the selected OPAMP.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg OPAMP_Selection_OPAMP1: OPAMP1 is selected
|
||||
* @arg OPAMP_Selection_OPAMP2: OPAMP2 is selected
|
||||
* @arg OPAMP_Selection_OPAMP3: OPAMP3 is selected
|
||||
* @param NewState: new state of the selected OPAMP peripheral.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void OPAMP_Cmd(uint32_t OPAMP_Selection, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameter */
|
||||
assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the selected OPAMP */
|
||||
OPAMP->CSR &= (~(uint32_t) OPAMP_Selection);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the selected OPAMP */
|
||||
OPAMP->CSR |= (uint32_t) OPAMP_Selection;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable or disable the low power mode for OPAMP peripheral.
|
||||
* @param OPAMP_Selection: the selected OPAMP.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg OPAMP_Selection_OPAMP1: OPAMP1 selected
|
||||
* @arg OPAMP_Selection_OPAMP2: OPAMP2 selected
|
||||
* @arg OPAMP_Selection_OPAMP3: OPAMP3 selected
|
||||
* @param NewState: new low power state of the selected OPAMP peripheral.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void OPAMP_LowPowerCmd(uint32_t OPAMP_Selection, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameter */
|
||||
assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Set the selected OPAMP in low power mode */
|
||||
OPAMP->CSR |= (uint32_t) (OPAMP_Selection << 7);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the low power mode for the selected OPAMP */
|
||||
OPAMP->CSR &= (~(uint32_t) (OPAMP_Selection << 7));
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Select the OPAMP power range.
|
||||
* @note The OPAMP power range selection must be performed while OPAMPs are powered down.
|
||||
* @param OPAMP_Range: the selected OPAMP power range.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg OPAMP_PowerRange_Low: Low power range is selected (VDDA is lower than 2.4V).
|
||||
* @arg OPAMP_PowerRange_High: High power range is selected (VDDA is higher than 2.4V).
|
||||
* @retval None
|
||||
*/
|
||||
void OPAMP_PowerRangeSelect(uint32_t OPAMP_PowerRange)
|
||||
{
|
||||
/* Check the parameter */
|
||||
assert_param(IS_OPAMP_RANGE(OPAMP_PowerRange));
|
||||
|
||||
/* Reset the OPAMP range bit */
|
||||
OPAMP->CSR &= (~(uint32_t) (OPAMP_CSR_AOP_RANGE));
|
||||
|
||||
/* Select the OPAMP power range */
|
||||
OPAMP->CSR |= OPAMP_PowerRange;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup OPAMP_Group2 Calibration functions
|
||||
* @brief Calibration functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Calibration functions #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Select the trimming mode.
|
||||
* @param OffsetTrimming: the selected offset trimming mode.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg OffsetTrimming_Factory: factory trimming values are used for offset
|
||||
* calibration.
|
||||
* @arg OffsetTrimming_User: user trimming values are used for offset
|
||||
* calibration.
|
||||
* @note When OffsetTrimming_User is selected, use OPAMP_OffsetTrimConfig()
|
||||
* function or OPAMP_OffsetTrimLowPowerConfig() function to adjust
|
||||
* trimming value.
|
||||
* @retval None
|
||||
*/
|
||||
void OPAMP_OffsetTrimmingModeSelect(uint32_t OPAMP_Trimming)
|
||||
{
|
||||
/* Check the parameter */
|
||||
assert_param(IS_OPAMP_TRIMMING(OPAMP_Trimming));
|
||||
|
||||
/* Reset the OPAMP_OTR range bit */
|
||||
OPAMP->CSR &= (~(uint32_t) (OPAMP_OTR_OT_USER));
|
||||
|
||||
/* Select the OPAMP offset trimming */
|
||||
OPAMP->CSR |= OPAMP_Trimming;
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configure the trimming value of OPAMPs in normal mode.
|
||||
* @param OPAMP_Selection: the selected OPAMP.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg OPAMP_Selection_OPAMP1: OPAMP1 is selected to configure the trimming value.
|
||||
* @arg OPAMP_Selection_OPAMP2: OPAMP2 is selected to configure the trimming value.
|
||||
* @arg OPAMP_Selection_OPAMP3: OPAMP3 is selected to configure the trimming value.
|
||||
* @param OPAMP_Input: the selected OPAMP input.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg OPAMP_Input_NMOS: NMOS input is selected to configure the trimming value.
|
||||
* @arg OPAMP_Input_PMOS: PMOS input is selected to configure the trimming value.
|
||||
* @param OPAMP_TrimValue: the trimming value. This parameter can be any value lower
|
||||
* or equal to 0x0000001F.
|
||||
* @retval None
|
||||
*/
|
||||
void OPAMP_OffsetTrimConfig(uint32_t OPAMP_Selection, uint32_t OPAMP_Input, uint32_t OPAMP_TrimValue)
|
||||
{
|
||||
uint32_t tmpreg = 0;
|
||||
|
||||
/* Check the parameter */
|
||||
assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection));
|
||||
assert_param(IS_OPAMP_INPUT(OPAMP_Input));
|
||||
assert_param(IS_OPAMP_TRIMMINGVALUE(OPAMP_TrimValue));
|
||||
|
||||
/* Get the OPAMP_OTR value */
|
||||
tmpreg = OPAMP->OTR;
|
||||
|
||||
if(OPAMP_Selection == OPAMP_Selection_OPAMP1)
|
||||
{
|
||||
/* Reset the OPAMP inputs selection */
|
||||
tmpreg &= (uint32_t)~(OPAMP_CSR_OPA1CAL_L | OPAMP_CSR_OPA1CAL_H);
|
||||
/* Select the OPAMP input */
|
||||
tmpreg |= OPAMP_Input;
|
||||
|
||||
if(OPAMP_Input == OPAMP_Input_PMOS)
|
||||
{
|
||||
/* Reset the trimming value corresponding to OPAMP1 PMOS input */
|
||||
tmpreg &= (0xFFFFFFE0);
|
||||
/* Set the new trimming value corresponding to OPAMP1 PMOS input */
|
||||
tmpreg |= (OPAMP_TrimValue);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Reset the trimming value corresponding to OPAMP1 NMOS input */
|
||||
tmpreg &= (0xFFFFFC1F);
|
||||
/* Set the new trimming value corresponding to OPAMP1 NMOS input */
|
||||
tmpreg |= (OPAMP_TrimValue<<5);
|
||||
}
|
||||
}
|
||||
else if (OPAMP_Selection == OPAMP_Selection_OPAMP2)
|
||||
{
|
||||
/* Reset the OPAMP inputs selection */
|
||||
tmpreg &= (uint32_t)~(OPAMP_CSR_OPA2CAL_L | OPAMP_CSR_OPA2CAL_H);
|
||||
/* Select the OPAMP input */
|
||||
tmpreg |= (uint32_t)(OPAMP_Input<<8);
|
||||
|
||||
if(OPAMP_Input == OPAMP_Input_PMOS)
|
||||
{
|
||||
/* Reset the trimming value corresponding to OPAMP2 PMOS input */
|
||||
tmpreg &= (0xFFFF83FF);
|
||||
/* Set the new trimming value corresponding to OPAMP2 PMOS input */
|
||||
tmpreg |= (OPAMP_TrimValue<<10);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Reset the trimming value corresponding to OPAMP2 NMOS input */
|
||||
tmpreg &= (0xFFF07FFF);
|
||||
/* Set the new trimming value corresponding to OPAMP2 NMOS input */
|
||||
tmpreg |= (OPAMP_TrimValue<<15);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Reset the OPAMP inputs selection */
|
||||
tmpreg &= (uint32_t)~(OPAMP_CSR_OPA3CAL_L | OPAMP_CSR_OPA3CAL_H);
|
||||
/* Select the OPAMP input */
|
||||
tmpreg |= (uint32_t)(OPAMP_Input<<16);
|
||||
|
||||
if(OPAMP_Input == OPAMP_Input_PMOS)
|
||||
{
|
||||
/* Reset the trimming value corresponding to OPAMP3 PMOS input */
|
||||
tmpreg &= (0xFE0FFFFF);
|
||||
/* Set the new trimming value corresponding to OPAMP3 PMOS input */
|
||||
tmpreg |= (OPAMP_TrimValue<<20);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Reset the trimming value corresponding to OPAMP3 NMOS input */
|
||||
tmpreg &= (0xC1FFFFFF);
|
||||
/* Set the new trimming value corresponding to OPAMP3 NMOS input */
|
||||
tmpreg |= (OPAMP_TrimValue<<25);
|
||||
}
|
||||
}
|
||||
|
||||
/* Set the OPAMP_OTR register */
|
||||
OPAMP->OTR = tmpreg;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configure the trimming value of OPAMPs in low power mode.
|
||||
* @param OPAMP_Selection: the selected OPAMP.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg OPAMP_Selection_OPAMP1: OPAMP1 is selected to configure the trimming value.
|
||||
* @arg OPAMP_Selection_OPAMP2: OPAMP2 is selected to configure the trimming value.
|
||||
* @arg OPAMP_Selection_OPAMP3: OPAMP3 is selected to configure the trimming value.
|
||||
* @param OPAMP_Input: the selected OPAMP input.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg OPAMP_Input_NMOS: NMOS input is selected to configure the trimming value.
|
||||
* @arg OPAMP_Input_PMOS: PMOS input is selected to configure the trimming value.
|
||||
* @param OPAMP_TrimValue: the trimming value.
|
||||
* This parameter can be any value lower or equal to 0x0000001F.
|
||||
* @retval None
|
||||
*/
|
||||
void OPAMP_OffsetTrimLowPowerConfig(uint32_t OPAMP_Selection, uint32_t OPAMP_Input, uint32_t OPAMP_TrimValue)
|
||||
{
|
||||
uint32_t tmpreg = 0;
|
||||
|
||||
/* Check the parameter */
|
||||
assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection));
|
||||
assert_param(IS_OPAMP_INPUT(OPAMP_Input));
|
||||
assert_param(IS_OPAMP_TRIMMINGVALUE(OPAMP_TrimValue));
|
||||
|
||||
/* Get the OPAMP_LPOTR value */
|
||||
tmpreg = OPAMP->LPOTR;
|
||||
|
||||
if(OPAMP_Selection == OPAMP_Selection_OPAMP1)
|
||||
{
|
||||
/* Reset the OPAMP inputs selection */
|
||||
tmpreg &= (uint32_t)~(OPAMP_CSR_OPA1CAL_L | OPAMP_CSR_OPA1CAL_H);
|
||||
/* Select the OPAMP input */
|
||||
tmpreg |= OPAMP_Input;
|
||||
|
||||
if(OPAMP_Input == OPAMP_Input_PMOS)
|
||||
{
|
||||
/* Reset the trimming value corresponding to OPAMP1 PMOS input */
|
||||
tmpreg &= (0xFFFFFFE0);
|
||||
/* Set the new trimming value corresponding to OPAMP1 PMOS input */
|
||||
tmpreg |= (OPAMP_TrimValue);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Reset the trimming value corresponding to OPAMP1 NMOS input */
|
||||
tmpreg &= (0xFFFFFC1F);
|
||||
/* Set the new trimming value corresponding to OPAMP1 NMOS input */
|
||||
tmpreg |= (OPAMP_TrimValue<<5);
|
||||
}
|
||||
}
|
||||
else if (OPAMP_Selection == OPAMP_Selection_OPAMP2)
|
||||
{
|
||||
/* Reset the OPAMP inputs selection */
|
||||
tmpreg &= (uint32_t)~(OPAMP_CSR_OPA2CAL_L | OPAMP_CSR_OPA2CAL_H);
|
||||
/* Select the OPAMP input */
|
||||
tmpreg |= (uint32_t)(OPAMP_Input<<8);
|
||||
|
||||
if(OPAMP_Input == OPAMP_Input_PMOS)
|
||||
{
|
||||
/* Reset the trimming value corresponding to OPAMP2 PMOS input */
|
||||
tmpreg &= (0xFFFF83FF);
|
||||
/* Set the new trimming value corresponding to OPAMP2 PMOS input */
|
||||
tmpreg |= (OPAMP_TrimValue<<10);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Reset the trimming value corresponding to OPAMP2 NMOS input */
|
||||
tmpreg &= (0xFFF07FFF);
|
||||
/* Set the new trimming value corresponding to OPAMP2 NMOS input */
|
||||
tmpreg |= (OPAMP_TrimValue<<15);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Reset the OPAMP inputs selection */
|
||||
tmpreg &= (uint32_t)~(OPAMP_CSR_OPA3CAL_L | OPAMP_CSR_OPA3CAL_H);
|
||||
/* Select the OPAMP input */
|
||||
tmpreg |= (uint32_t)(OPAMP_Input<<16);
|
||||
|
||||
if(OPAMP_Input == OPAMP_Input_PMOS)
|
||||
{
|
||||
/* Reset the trimming value corresponding to OPAMP3 PMOS input */
|
||||
tmpreg &= (0xFE0FFFFF);
|
||||
/* Set the new trimming value corresponding to OPAMP3 PMOS input */
|
||||
tmpreg |= (OPAMP_TrimValue<<20);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Reset the trimming value corresponding to OPAMP3 NMOS input */
|
||||
tmpreg &= (0xC1FFFFFF);
|
||||
/* Set the new trimming value corresponding to OPAMP3 NMOS input */
|
||||
tmpreg |= (OPAMP_TrimValue<<25);
|
||||
}
|
||||
}
|
||||
|
||||
/* Set the OPAMP_LPOTR register */
|
||||
OPAMP->LPOTR = tmpreg;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified OPAMP calibration flag is set or not.
|
||||
* @note User should wait until calibration flag change the value when changing
|
||||
* the trimming value.
|
||||
* @param OPAMP_Selection: the selected OPAMP.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg OPAMP_Selection_OPAMP1: OPAMP1 is selected.
|
||||
* @arg OPAMP_Selection_OPAMP2: OPAMP2 is selected.
|
||||
* @arg OPAMP_Selection_OPAMP3: OPAMP3 is selected.
|
||||
* @retval The new state of the OPAMP calibration flag (SET or RESET).
|
||||
*/
|
||||
FlagStatus OPAMP_GetFlagStatus(uint32_t OPAMP_Selection)
|
||||
{
|
||||
FlagStatus bitstatus = RESET;
|
||||
uint32_t tmpreg = 0;
|
||||
|
||||
/* Check the parameter */
|
||||
assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection));
|
||||
|
||||
/* Get the CSR register value */
|
||||
tmpreg = OPAMP->CSR;
|
||||
|
||||
/* Check if OPAMP1 is selected */
|
||||
if(OPAMP_Selection == OPAMP_Selection_OPAMP1)
|
||||
{
|
||||
/* Check OPAMP1 CAL bit status */
|
||||
if ((tmpreg & OPAMP_CSR_OPA1CALOUT) != (uint32_t)RESET)
|
||||
{
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = RESET;
|
||||
}
|
||||
}
|
||||
/* Check if OPAMP2 is selected */
|
||||
else if(OPAMP_Selection == OPAMP_Selection_OPAMP2)
|
||||
{
|
||||
/* Check OPAMP2 CAL bit status */
|
||||
if ((tmpreg & OPAMP_CSR_OPA2CALOUT) != (uint32_t)RESET)
|
||||
{
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = RESET;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Check OPAMP3 CAL bit status */
|
||||
if ((tmpreg & OPAMP_CSR_OPA3CALOUT) != (uint32_t)RESET)
|
||||
{
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = RESET;
|
||||
}
|
||||
}
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,833 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32l1xx_pwr.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.1
|
||||
* @date 05-March-2012
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the Power Controller (PWR) peripheral:
|
||||
* + RTC Domain Access
|
||||
* + PVD configuration
|
||||
* + WakeUp pins configuration
|
||||
* + Ultra Low Power mode configuration
|
||||
* + Voltage Scaling configuration
|
||||
* + Low Power modes configuration
|
||||
* + Flags management
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32l1xx_pwr.h"
|
||||
#include "stm32l1xx_rcc.h"
|
||||
|
||||
/** @addtogroup STM32L1xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PWR
|
||||
* @brief PWR driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/* --------- PWR registers bit address in the alias region ---------- */
|
||||
#define PWR_OFFSET (PWR_BASE - PERIPH_BASE)
|
||||
|
||||
/* --- CR Register ---*/
|
||||
|
||||
/* Alias word address of DBP bit */
|
||||
#define CR_OFFSET (PWR_OFFSET + 0x00)
|
||||
#define DBP_BitNumber 0x08
|
||||
#define CR_DBP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4))
|
||||
|
||||
/* Alias word address of PVDE bit */
|
||||
#define PVDE_BitNumber 0x04
|
||||
#define CR_PVDE_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4))
|
||||
|
||||
/* Alias word address of ULP bit */
|
||||
#define ULP_BitNumber 0x09
|
||||
#define CR_ULP_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (ULP_BitNumber * 4))
|
||||
|
||||
/* Alias word address of FWU bit */
|
||||
#define FWU_BitNumber 0x0A
|
||||
#define CR_FWU_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (FWU_BitNumber * 4))
|
||||
|
||||
/* --- CSR Register ---*/
|
||||
|
||||
/* Alias word address of EWUP bit */
|
||||
#define CSR_OFFSET (PWR_OFFSET + 0x04)
|
||||
#define EWUP_BitNumber 0x08
|
||||
#define CSR_EWUP_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4))
|
||||
|
||||
/* ------------------ PWR registers bit mask ------------------------ */
|
||||
|
||||
/* CR register bit mask */
|
||||
#define CR_DS_MASK ((uint32_t)0xFFFFFFFC)
|
||||
#define CR_PLS_MASK ((uint32_t)0xFFFFFF1F)
|
||||
#define CR_VOS_MASK ((uint32_t)0xFFFFE7FF)
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup PWR_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_Group1 RTC Domain Access function
|
||||
* @brief RTC Domain Access function
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### RTC Domain Access function #####
|
||||
==============================================================================
|
||||
|
||||
[..] After reset, the RTC Registers (RCC CSR Register, RTC registers and RTC backup
|
||||
registers) are protected against possible stray write accesses.
|
||||
[..] To enable access to RTC domain use the PWR_RTCAccessCmd(ENABLE) function.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the PWR peripheral registers to their default reset values.
|
||||
* @note Before calling this function, the VOS[1:0] bits should be configured
|
||||
* to "10" and the system frequency has to be configured accordingly.
|
||||
* To configure the VOS[1:0] bits, use the PWR_VoltageScalingConfig()
|
||||
* function.
|
||||
* @note ULP and FWU bits are not reset by this function.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void PWR_DeInit(void)
|
||||
{
|
||||
RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE);
|
||||
RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables access to the RTC and backup registers.
|
||||
* @note If the HSE divided by 2, 4, 8 or 16 is used as the RTC clock, the
|
||||
* RTC Domain Access should be kept enabled.
|
||||
* @param NewState: new state of the access to the RTC and backup registers.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void PWR_RTCAccessCmd(FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
*(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_Group2 PVD configuration functions
|
||||
* @brief PVD configuration functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### PVD configuration functions #####
|
||||
==============================================================================
|
||||
[..]
|
||||
(+) The PVD is used to monitor the VDD power supply by comparing it to a threshold
|
||||
selected by the PVD Level (PLS[2:0] bits in the PWR_CR).
|
||||
(+) The PVD can use an external input analog voltage (PVD_IN) which is compared
|
||||
internally to VREFINT. The PVD_IN (PB7) has to be configured in Analog mode
|
||||
when PWR_PVDLevel_7 is selected (PLS[2:0] = 111).
|
||||
(+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower than the
|
||||
PVD threshold. This event is internally connected to the EXTI line16
|
||||
and can generate an interrupt if enabled through the EXTI registers.
|
||||
(+) The PVD is stopped in Standby mode.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).
|
||||
* @param PWR_PVDLevel: specifies the PVD detection level.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_PVDLevel_0: PVD detection level set to 1.9V.
|
||||
* @arg PWR_PVDLevel_1: PVD detection level set to 2.1V.
|
||||
* @arg PWR_PVDLevel_2: PVD detection level set to 2.3V.
|
||||
* @arg PWR_PVDLevel_3: PVD detection level set to 2.5V.
|
||||
* @arg PWR_PVDLevel_4: PVD detection level set to 2.7V.
|
||||
* @arg PWR_PVDLevel_5: PVD detection level set to 2.9V.
|
||||
* @arg PWR_PVDLevel_6: PVD detection level set to 3.1V.
|
||||
* @arg PWR_PVDLevel_7: External input analog voltage (Compare internally to VREFINT).
|
||||
* @retval None
|
||||
*/
|
||||
void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)
|
||||
{
|
||||
uint32_t tmpreg = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel));
|
||||
|
||||
tmpreg = PWR->CR;
|
||||
|
||||
/* Clear PLS[7:5] bits */
|
||||
tmpreg &= CR_PLS_MASK;
|
||||
|
||||
/* Set PLS[7:5] bits according to PWR_PVDLevel value */
|
||||
tmpreg |= PWR_PVDLevel;
|
||||
|
||||
/* Store the new value */
|
||||
PWR->CR = tmpreg;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the Power Voltage Detector(PVD).
|
||||
* @param NewState: new state of the PVD.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void PWR_PVDCmd(FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
*(__IO uint32_t *) CR_PVDE_BB = (uint32_t)NewState;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_Group3 WakeUp pins configuration functions
|
||||
* @brief WakeUp pins configuration functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### WakeUp pin configuration functions #####
|
||||
==============================================================================
|
||||
|
||||
(+) WakeUp pins are used to wakeup the system from Standby mode. These pins are
|
||||
forced in input pull down configuration and are active on rising edges.
|
||||
(+) There are three WakeUp pins: WakeUp Pin 1 on PA.00, WakeUp Pin 2 on PC.13 and
|
||||
WakeUp Pin 3 on PE.06.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the WakeUp Pin functionality.
|
||||
* @param PWR_WakeUpPin: specifies the WakeUpPin.
|
||||
* This parameter can be: PWR_WakeUpPin_1, PWR_WakeUpPin_2 or PWR_WakeUpPin_3.
|
||||
* @param NewState: new state of the WakeUp Pin functionality.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void PWR_WakeUpPinCmd(uint32_t PWR_WakeUpPin, FunctionalState NewState)
|
||||
{
|
||||
__IO uint32_t tmp = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_PWR_WAKEUP_PIN(PWR_WakeUpPin));
|
||||
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
tmp = CSR_EWUP_BB + PWR_WakeUpPin;
|
||||
|
||||
*(__IO uint32_t *) (tmp) = (uint32_t)NewState;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_Group4 Ultra Low Power mode configuration functions
|
||||
* @brief Ultra Low Power mode configuration functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### Ultra Low Power mode configuration functions #####
|
||||
==============================================================================
|
||||
[..]
|
||||
(+) The internal voltage reference consumption is not negligible, in particular
|
||||
in Stop and Standby mode. To reduce power consumption, use the PWR_UltraLowPowerCmd()
|
||||
function (ULP bit (Ultra low power) in the PWR_CR register) to disable the
|
||||
internal voltage reference. However, in this case, when exiting from the
|
||||
Stop/Standby mode, the functions managed through the internal voltage reference
|
||||
are not reliable during the internal voltage reference startup time (up to 3 ms).
|
||||
To reduce the wakeup time, the device can exit from Stop/Standby mode without
|
||||
waiting for the internal voltage reference startup time. This is performed
|
||||
by using the PWR_FastWakeUpCmd() function (setting the FWU bit (Fast
|
||||
wakeup) in the PWR_CR register) before entering Stop/Standby mode.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the Fast WakeUp from Ultra Low Power mode.
|
||||
* @param NewState: new state of the Fast WakeUp functionality.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void PWR_FastWakeUpCmd(FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
*(__IO uint32_t *) CR_FWU_BB = (uint32_t)NewState;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the Ultra Low Power mode.
|
||||
* @param NewState: new state of the Ultra Low Power mode.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void PWR_UltraLowPowerCmd(FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
*(__IO uint32_t *) CR_ULP_BB = (uint32_t)NewState;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_Group5 Voltage Scaling configuration functions
|
||||
* @brief Voltage Scaling configuration functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### Voltage Scaling configuration functions #####
|
||||
==============================================================================
|
||||
|
||||
(+) The dynamic voltage scaling is a power management technique which consists in
|
||||
increasing or decreasing the voltage used for the digital peripherals (VCORE),
|
||||
according to the circumstances.
|
||||
|
||||
[..] Depending on the device voltage range, the maximum frequency and FLASH wait
|
||||
state should be adapted accordingly:
|
||||
[..]
|
||||
+------------------------------------------------------------------+
|
||||
| Wait states | HCLK clock frequency (MHz) |
|
||||
| |------------------------------------------------|
|
||||
| (Latency) | voltage range | voltage range |
|
||||
| | 1.65 V - 3.6 V | 2.0 V - 3.6 V |
|
||||
| |----------------|---------------|---------------|
|
||||
| | Range 3 | Range 2 | Range 1 |
|
||||
| | VCORE = 1.2 V | VCORE = 1.5 V | VCORE = 1.8 V |
|
||||
|---------------- |----------------|---------------|---------------|
|
||||
| 0WS(1CPU cycle) |0 < HCLK <= 2 |0 < HCLK <= 8 |0 < HCLK <= 16 |
|
||||
|-----------------|----------------|---------------|---------------|
|
||||
| 1WS(2CPU cycle) |2 < HCLK <= 4 |8 < HCLK <= 16 |16 < HCLK <= 32|
|
||||
|-----------------|----------------|---------------|---------------|
|
||||
| CPU Performance | Low | Medium | High |
|
||||
|-----__----------|----------------|---------------|---------------|
|
||||
|Power Performance| High | Medium | Low |
|
||||
+------------------------------------------------------------------+
|
||||
|
||||
(+) To modify the Product voltage range, user application has to:
|
||||
(++) Check VDD to identify which ranges are allowed (see table above).
|
||||
(++) Check the PWR_FLAG_VOSF (Voltage Scaling update ongoing) using the PWR_GetFlagStatus()
|
||||
function and wait until it is reset.
|
||||
(++) Configure the Voltage range using the PWR_VoltageScalingConfig() function.
|
||||
|
||||
(+) When VCORE range 1 is selected and VDD drops below 2.0 V, the application must
|
||||
reconfigure the system:
|
||||
(++) Detect that VDD drops below 2.0 V using the PVD Level 1.
|
||||
(++) Adapt the clock frequency to the voltage range that will be selected at next step.
|
||||
(++) Select the required voltage range.
|
||||
(++) When VCORE range 2 or range 3 is selected and VDD drops below 2.0 V, no system
|
||||
reconfiguration is required.
|
||||
|
||||
(+) When VDD is above 2.0 V, any of the 3 voltage ranges can be selected.
|
||||
(++) When the voltage range is above the targeted voltage range (e.g. from range
|
||||
1 to 2).
|
||||
(++) Adapt the clock frequency to the lower voltage range that will be selected
|
||||
at next step.
|
||||
(++) Select the required voltage range.
|
||||
(++) When the voltage range is below the targeted voltage range (e.g. from range
|
||||
3 to 1).
|
||||
(++) Select the required voltage range.
|
||||
(++) Tune the clock frequency if needed.
|
||||
|
||||
(+) When VDD is below 2.0 V, only range 2 and 3 can be selected:
|
||||
(++) From range 2 to range 3.
|
||||
(+++) Adapt the clock frequency to voltage range 3.
|
||||
(+++) Select voltage range 3.
|
||||
(++) From range 3 to range 2.
|
||||
(+++) Select the voltage range 2.
|
||||
(+++) Tune the clock frequency if needed.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Configures the voltage scaling range.
|
||||
* @note During voltage scaling configuration, the system clock is stopped
|
||||
* until the regulator is stabilized (VOSF = 0). This must be taken
|
||||
* into account during application developement, in case a critical
|
||||
* reaction time to interrupt is needed, and depending on peripheral
|
||||
* used (timer, communication,...).
|
||||
*
|
||||
* @param PWR_VoltageScaling: specifies the voltage scaling range.
|
||||
* This parameter can be:
|
||||
* @arg PWR_VoltageScaling_Range1: Voltage Scaling Range 1 (VCORE = 1.8V).
|
||||
* @arg PWR_VoltageScaling_Range2: Voltage Scaling Range 2 (VCORE = 1.5V).
|
||||
* @arg PWR_VoltageScaling_Range3: Voltage Scaling Range 3 (VCORE = 1.2V)
|
||||
* @retval None
|
||||
*/
|
||||
void PWR_VoltageScalingConfig(uint32_t PWR_VoltageScaling)
|
||||
{
|
||||
uint32_t tmp = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(PWR_VoltageScaling));
|
||||
|
||||
tmp = PWR->CR;
|
||||
|
||||
tmp &= CR_VOS_MASK;
|
||||
tmp |= PWR_VoltageScaling;
|
||||
|
||||
PWR->CR = tmp & 0xFFFFFFF3;
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_Group6 Low Power modes configuration functions
|
||||
* @brief Low Power modes configuration functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### Low Power modes configuration functions #####
|
||||
==============================================================================
|
||||
|
||||
[..] The devices feature five low-power modes:
|
||||
(+) Low power run mode: regulator in low power mode, limited clock frequency,
|
||||
limited number of peripherals running.
|
||||
(+) Sleep mode: Cortex-M3 core stopped, peripherals kept running.
|
||||
(+) Low power sleep mode: Cortex-M3 core stopped, limited clock frequency,
|
||||
limited number of peripherals running, regulator in low power mode.
|
||||
(+) Stop mode: all clocks are stopped, regulator running, regulator in low power mode.
|
||||
(+) Standby mode: VCORE domain powered off.
|
||||
|
||||
*** Low power run mode (LP run) ***
|
||||
===================================
|
||||
[..]
|
||||
(+) Entry:
|
||||
(++) Decrease the system frequency.
|
||||
(++) The regulator is forced in low power mode using the PWR_EnterLowPowerRunMode()
|
||||
function.
|
||||
(+) Exit:
|
||||
(++) The regulator is forced in Main regulator mode sing the PWR_EnterLowPowerRunMode()
|
||||
function.
|
||||
(++) Increase the system frequency if needed.
|
||||
|
||||
*** Sleep mode ***
|
||||
==================
|
||||
[..]
|
||||
(+) Entry:
|
||||
(++) The Sleep mode is entered by using the PWR_EnterSleepMode(PWR_Regulator_ON,)
|
||||
function with regulator ON.
|
||||
(+) Exit:
|
||||
(++) Any peripheral interrupt acknowledged by the nested vectored interrupt
|
||||
controller (NVIC) can wake up the device from Sleep mode.
|
||||
|
||||
*** Low power sleep mode (LP sleep) ***
|
||||
=======================================
|
||||
[..]
|
||||
(+) Entry:
|
||||
(++) The Flash memory must be switched off by using the FLASH_SLEEPPowerDownCmd()
|
||||
function.
|
||||
(++) Decrease the system frequency.
|
||||
(++) The regulator is forced in low power mode and the WFI or WFE instructions
|
||||
are executed using the PWR_EnterSleepMode(PWR_Regulator_LowPower,) function
|
||||
with regulator in LowPower.
|
||||
(+) Exit:
|
||||
(++) Any peripheral interrupt acknowledged by the nested vectored interrupt
|
||||
controller (NVIC) can wake up the device from Sleep LP mode.
|
||||
|
||||
*** Stop mode ***
|
||||
=================
|
||||
[..] In Stop mode, all clocks in the VCORE domain are stopped, the PLL, the MSI,
|
||||
the HSI and the HSE RC oscillators are disabled. Internal SRAM and register
|
||||
contents are preserved.
|
||||
The voltage regulator can be configured either in normal or low-power mode.
|
||||
To minimize the consumption In Stop mode, VREFINT, the BOR, PVD, and temperature
|
||||
sensor can be switched off before entering the Stop mode. They can be switched
|
||||
on again by software after exiting the Stop mode using the PWR_UltraLowPowerCmd()
|
||||
function.
|
||||
|
||||
(+) Entry:
|
||||
(++) The Stop mode is entered using the PWR_EnterSTOPMode(PWR_Regulator_LowPower,)
|
||||
function with regulator in LowPower or with Regulator ON.
|
||||
(+) Exit:
|
||||
(++) Any EXTI Line (Internal or External) configured in Interrupt/Event mode.
|
||||
|
||||
*** Standby mode ***
|
||||
====================
|
||||
[..] The Standby mode allows to achieve the lowest power consumption. It is based
|
||||
on the Cortex-M3 deepsleep mode, with the voltage regulator disabled.
|
||||
The VCORE domain is consequently powered off. The PLL, the MSI, the HSI
|
||||
oscillator and the HSE oscillator are also switched off. SRAM and register
|
||||
contents are lost except for the RTC registers, RTC backup registers and
|
||||
Standby circuitry.
|
||||
|
||||
[..] The voltage regulator is OFF.
|
||||
|
||||
[..] To minimize the consumption In Standby mode, VREFINT, the BOR, PVD, and temperature
|
||||
sensor can be switched off before entering the Standby mode. They can be switched
|
||||
on again by software after exiting the Standby mode using the PWR_UltraLowPowerCmd()
|
||||
function.
|
||||
|
||||
(+) Entry:
|
||||
(++) The Standby mode is entered using the PWR_EnterSTANDBYMode() function.
|
||||
(+) Exit:
|
||||
(++) WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup,
|
||||
tamper event, time-stamp event, external reset in NRST pin, IWDG reset.
|
||||
|
||||
*** Auto-wakeup (AWU) from low-power mode ***
|
||||
=============================================
|
||||
[..]The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC
|
||||
Wakeup event, a tamper event, a time-stamp event, or a comparator event,
|
||||
without depending on an external interrupt (Auto-wakeup mode).
|
||||
|
||||
(+) RTC auto-wakeup (AWU) from the Stop mode
|
||||
(++) To wake up from the Stop mode with an RTC alarm event, it is necessary to:
|
||||
(+++) Configure the EXTI Line 17 to be sensitive to rising edges (Interrupt
|
||||
or Event modes) using the EXTI_Init() function.
|
||||
(+++) Enable the RTC Alarm Interrupt using the RTC_ITConfig() function
|
||||
(+++) Configure the RTC to generate the RTC alarm using the RTC_SetAlarm()
|
||||
and RTC_AlarmCmd() functions.
|
||||
(++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it
|
||||
is necessary to:
|
||||
(+++) Configure the EXTI Line 19 to be sensitive to rising edges (Interrupt
|
||||
or Event modes) using the EXTI_Init() function.
|
||||
(+++) Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig()
|
||||
function.
|
||||
(+++) Configure the RTC to detect the tamper or time stamp event using the
|
||||
RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd()
|
||||
functions.
|
||||
(++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to:
|
||||
(+++) Configure the EXTI Line 20 to be sensitive to rising edges (Interrupt
|
||||
or Event modes) using the EXTI_Init() function.
|
||||
(+++) Enable the RTC WakeUp Interrupt using the RTC_ITConfig() function.
|
||||
(+++) Configure the RTC to generate the RTC WakeUp event using the RTC_WakeUpClockConfig(),
|
||||
RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions.
|
||||
|
||||
(+) RTC auto-wakeup (AWU) from the Standby mode
|
||||
(++) To wake up from the Standby mode with an RTC alarm event, it is necessary to:
|
||||
(+++) Enable the RTC Alarm Interrupt using the RTC_ITConfig() function.
|
||||
(+++) Configure the RTC to generate the RTC alarm using the RTC_SetAlarm()
|
||||
and RTC_AlarmCmd() functions.
|
||||
(++) To wake up from the Standby mode with an RTC Tamper or time stamp event, it
|
||||
is necessary to:
|
||||
(+++) Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig()
|
||||
function.
|
||||
(+++) Configure the RTC to detect the tamper or time stamp event using the
|
||||
RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd()
|
||||
functions.
|
||||
(++) To wake up from the Standby mode with an RTC WakeUp event, it is necessary to:
|
||||
(+++) Enable the RTC WakeUp Interrupt using the RTC_ITConfig() function
|
||||
(+++) Configure the RTC to generate the RTC WakeUp event using the RTC_WakeUpClockConfig(),
|
||||
RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions.
|
||||
|
||||
(+) Comparator auto-wakeup (AWU) from the Stop mode
|
||||
(++) To wake up from the Stop mode with an comparator 1 or comparator 2 wakeup
|
||||
event, it is necessary to:
|
||||
(+++) Configure the EXTI Line 21 for comparator 1 or EXTI Line 22 for comparator 2
|
||||
to be sensitive to to the selected edges (falling, rising or falling
|
||||
and rising) (Interrupt or Event modes) using the EXTI_Init() function.
|
||||
(+++) Configure the comparator to generate the event.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enters/Exits the Low Power Run mode.
|
||||
* @note Low power run mode can only be entered when VCORE is in range 2.
|
||||
* In addition, the dynamic voltage scaling must not be used when Low
|
||||
* power run mode is selected. Only Stop and Sleep modes with regulator
|
||||
* configured in Low power mode is allowed when Low power run mode is
|
||||
* selected.
|
||||
* @note In Low power run mode, all I/O pins keep the same state as in Run mode.
|
||||
* @param NewState: new state of the Low Power Run mode.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void PWR_EnterLowPowerRunMode(FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
PWR->CR |= PWR_CR_LPSDSR;
|
||||
PWR->CR |= PWR_CR_LPRUN;
|
||||
}
|
||||
else
|
||||
{
|
||||
PWR->CR &= (uint32_t)~((uint32_t)PWR_CR_LPRUN);
|
||||
PWR->CR &= (uint32_t)~((uint32_t)PWR_CR_LPSDSR);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enters Sleep mode.
|
||||
* @note In Sleep mode, all I/O pins keep the same state as in Run mode.
|
||||
* @param PWR_Regulator: specifies the regulator state in Sleep mode.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_Regulator_ON: Sleep mode with regulator ON
|
||||
* @arg PWR_Regulator_LowPower: Sleep mode with regulator in low power mode
|
||||
* @note Low power sleep mode can only be entered when VCORE is in range 2.
|
||||
* @note When the voltage regulator operates in low power mode, an additional
|
||||
* startup delay is incurred when waking up from Low power sleep mode.
|
||||
* @param PWR_SLEEPEntry: specifies if SLEEP mode in entered with WFI or WFE instruction.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_SLEEPEntry_WFI: enter SLEEP mode with WFI instruction
|
||||
* @arg PWR_SLEEPEntry_WFE: enter SLEEP mode with WFE instruction
|
||||
* @retval None
|
||||
*/
|
||||
void PWR_EnterSleepMode(uint32_t PWR_Regulator, uint8_t PWR_SLEEPEntry)
|
||||
{
|
||||
uint32_t tmpreg = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_PWR_REGULATOR(PWR_Regulator));
|
||||
|
||||
assert_param(IS_PWR_SLEEP_ENTRY(PWR_SLEEPEntry));
|
||||
|
||||
/* Select the regulator state in Sleep mode ---------------------------------*/
|
||||
tmpreg = PWR->CR;
|
||||
|
||||
/* Clear PDDS and LPDSR bits */
|
||||
tmpreg &= CR_DS_MASK;
|
||||
|
||||
/* Set LPDSR bit according to PWR_Regulator value */
|
||||
tmpreg |= PWR_Regulator;
|
||||
|
||||
/* Store the new value */
|
||||
PWR->CR = tmpreg;
|
||||
|
||||
/* Clear SLEEPDEEP bit of Cortex System Control Register */
|
||||
SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP);
|
||||
|
||||
/* Select SLEEP mode entry -------------------------------------------------*/
|
||||
if(PWR_SLEEPEntry == PWR_SLEEPEntry_WFI)
|
||||
{
|
||||
/* Request Wait For Interrupt */
|
||||
__WFI();
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Request Wait For Event */
|
||||
__WFE();
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enters STOP mode.
|
||||
* @note In Stop mode, all I/O pins keep the same state as in Run mode.
|
||||
* @note When exiting Stop mode by issuing an interrupt or a wakeup event,
|
||||
* the MSI RC oscillator is selected as system clock.
|
||||
* @note When the voltage regulator operates in low power mode, an additional
|
||||
* startup delay is incurred when waking up from Stop mode.
|
||||
* By keeping the internal regulator ON during Stop mode, the consumption
|
||||
* is higher although the startup time is reduced.
|
||||
* @param PWR_Regulator: specifies the regulator state in STOP mode.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_Regulator_ON: STOP mode with regulator ON.
|
||||
* @arg PWR_Regulator_LowPower: STOP mode with regulator in low power mode.
|
||||
* @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction.
|
||||
* @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction.
|
||||
* @retval None
|
||||
*/
|
||||
void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
|
||||
{
|
||||
uint32_t tmpreg = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_PWR_REGULATOR(PWR_Regulator));
|
||||
assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry));
|
||||
|
||||
/* Select the regulator state in STOP mode ---------------------------------*/
|
||||
tmpreg = PWR->CR;
|
||||
/* Clear PDDS and LPDSR bits */
|
||||
tmpreg &= CR_DS_MASK;
|
||||
|
||||
/* Set LPDSR bit according to PWR_Regulator value */
|
||||
tmpreg |= PWR_Regulator;
|
||||
|
||||
/* Store the new value */
|
||||
PWR->CR = tmpreg;
|
||||
|
||||
/* Set SLEEPDEEP bit of Cortex System Control Register */
|
||||
SCB->SCR |= SCB_SCR_SLEEPDEEP;
|
||||
|
||||
/* Select STOP mode entry --------------------------------------------------*/
|
||||
if(PWR_STOPEntry == PWR_STOPEntry_WFI)
|
||||
{
|
||||
/* Request Wait For Interrupt */
|
||||
__WFI();
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Request Wait For Event */
|
||||
__WFE();
|
||||
}
|
||||
/* Reset SLEEPDEEP bit of Cortex System Control Register */
|
||||
SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enters STANDBY mode.
|
||||
* @note In Standby mode, all I/O pins are high impedance except for:
|
||||
* Reset pad (still available)
|
||||
* RTC_AF1 pin (PC13) if configured for Wakeup pin 2 (WKUP2), tamper,
|
||||
* time-stamp, RTC Alarm out, or RTC clock calibration out.
|
||||
* WKUP pin 1 (PA0) and WKUP pin 3 (PE6), if enabled.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void PWR_EnterSTANDBYMode(void)
|
||||
{
|
||||
/* Clear Wakeup flag */
|
||||
PWR->CR |= PWR_CR_CWUF;
|
||||
|
||||
/* Select STANDBY mode */
|
||||
PWR->CR |= PWR_CR_PDDS;
|
||||
|
||||
/* Set SLEEPDEEP bit of Cortex System Control Register */
|
||||
SCB->SCR |= SCB_SCR_SLEEPDEEP;
|
||||
|
||||
/* This option is used to ensure that store operations are completed */
|
||||
#if defined ( __CC_ARM )
|
||||
__force_stores();
|
||||
#endif
|
||||
/* Request Wait For Interrupt */
|
||||
__WFI();
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup PWR_Group7 Flags management functions
|
||||
* @brief Flags management functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### Flags management functions #####
|
||||
==============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified PWR flag is set or not.
|
||||
* @param PWR_FLAG: specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event
|
||||
* was received from the WKUP pin or from the RTC alarm (Alarm A or Alarm B),
|
||||
* RTC Tamper event, RTC TimeStamp event or RTC Wakeup.
|
||||
* @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was
|
||||
* resumed from StandBy mode.
|
||||
* @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled
|
||||
* by the PWR_PVDCmd() function.
|
||||
* @arg PWR_FLAG_VREFINTRDY: Internal Voltage Reference Ready flag. This
|
||||
* flag indicates the state of the internal voltage reference, VREFINT.
|
||||
* @arg PWR_FLAG_VOS: Voltage Scaling select flag. A delay is required for
|
||||
* the internal regulator to be ready after the voltage range is changed.
|
||||
* The VOSF flag indicates that the regulator has reached the voltage level
|
||||
* defined with bits VOS[1:0] of PWR_CR register.
|
||||
* @arg PWR_FLAG_REGLP: Regulator LP flag. This flag is set by hardware
|
||||
* when the MCU is in Low power run mode.
|
||||
* When the MCU exits from Low power run mode, this flag stays SET until
|
||||
* the regulator is ready in main mode. A polling on this flag is
|
||||
* recommended to wait for the regulator main mode.
|
||||
* This flag is RESET by hardware when the regulator is ready.
|
||||
* @retval The new state of PWR_FLAG (SET or RESET).
|
||||
*/
|
||||
FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG)
|
||||
{
|
||||
FlagStatus bitstatus = RESET;
|
||||
/* Check the parameters */
|
||||
assert_param(IS_PWR_GET_FLAG(PWR_FLAG));
|
||||
|
||||
if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET)
|
||||
{
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = RESET;
|
||||
}
|
||||
/* Return the flag status */
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the PWR's pending flags.
|
||||
* @param PWR_FLAG: specifies the flag to clear.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg PWR_FLAG_WU: Wake Up flag
|
||||
* @arg PWR_FLAG_SB: StandBy flag
|
||||
* @retval None
|
||||
*/
|
||||
void PWR_ClearFlag(uint32_t PWR_FLAG)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG));
|
||||
|
||||
PWR->CR |= PWR_FLAG << 2;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,984 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32l1xx_sdio.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.1
|
||||
* @date 05-March-2012
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the SDIO peripheral:
|
||||
* + Initialization
|
||||
* + Interrupts and flags management
|
||||
*
|
||||
* @verbatim
|
||||
==============================================================================
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
(#) The SDIO clock (SDIOCLK = 48 MHz) is coming from a specific output of PLL
|
||||
(PLLVCO) througth a fixed divider by 2.
|
||||
Before to start working with SDIO peripheral make sure that the PLLVCO is
|
||||
well configured to 96MHz.
|
||||
The SDIO peripheral uses two clock signals:
|
||||
(++) SDIO adapter clock (SDIOCLK = 48 MHz).
|
||||
(++) APB2 bus clock (PCLK2).
|
||||
PCLK2 and SDIO_CK clock frequencies must respect the following
|
||||
condition: Frequenc(PCLK2) >= (3 / 8 x Frequency(SDIO_CK)).
|
||||
(#) Enable peripheral clock using
|
||||
RCC_APB2PeriphClockCmd(RCC_APB2Periph_SDIO, ENABLE).
|
||||
(#) According to the SDIO mode, enable the GPIO clocks using
|
||||
RCC_AHBPeriphClockCmd() function.
|
||||
The I/O can be one of the following configurations:
|
||||
(++) 1-bit data length: SDIO_CMD, SDIO_CK and D0.
|
||||
(++) 4-bit data length: SDIO_CMD, SDIO_CK and D[3:0].
|
||||
(++) 8-bit data length: SDIO_CMD, SDIO_CK and D[7:0].
|
||||
|
||||
(#) Peripheral's alternate function:
|
||||
(++) Connect the pin to the desired peripherals' Alternate
|
||||
Function (AF) using GPIO_PinAFConfig() function.
|
||||
(++) Configure the desired pin in alternate function by:
|
||||
GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF.
|
||||
(++) Select the type, pull-up/pull-down and output speed via
|
||||
GPIO_PuPd, GPIO_OType and GPIO_Speed members.
|
||||
(++) Call GPIO_Init() function.
|
||||
|
||||
(#) Program the Clock Edge, Clock Bypass, Clock Power Save, Bus Wide,
|
||||
hardware, flow control and the Clock Divider using the SDIO_Init()
|
||||
function.
|
||||
(#) Enable the Power ON State using the SDIO_SetPowerState(SDIO_PowerState_ON)
|
||||
function.
|
||||
(#) Enable the clock using the SDIO_ClockCmd() function.
|
||||
(#) Enable the NVIC and the corresponding interrupt using the function
|
||||
SDIO_ITConfig() if you need to use interrupt mode.
|
||||
(#) When using the DMA mode
|
||||
(++) Configure the DMA using DMA_Init() function.
|
||||
(++) Active the needed channel Request using SDIO_DMACmd() function.
|
||||
(#) Enable the DMA using the DMA_Cmd() function, when using DMA mode.
|
||||
(#) To control the CPSM (Command Path State Machine) and send commands to the
|
||||
card use the SDIO_SendCommand(), SDIO_GetCommandResponse() and
|
||||
SDIO_GetResponse() functions. First, user has to fill the command
|
||||
structure (pointer to SDIO_CmdInitTypeDef) according to the selected
|
||||
command to be sent. The parameters that should be filled are:
|
||||
(++) Command Argument.
|
||||
(++) Command Index.
|
||||
(++) Command Response type.
|
||||
(++) Command Wait.
|
||||
(++) CPSM Status (Enable or Disable).
|
||||
To check if the command is well received, read the SDIO_CMDRESP register
|
||||
using the SDIO_GetCommandResponse(). The SDIO responses registers
|
||||
(SDIO_RESP1 to SDIO_RESP2), use the SDIO_GetResponse() function.
|
||||
(#) To control the DPSM (Data Path State Machine) and send/receive
|
||||
data to/from the card use the SDIO_DataConfig(), SDIO_GetDataCounter(),
|
||||
SDIO_ReadData(), SDIO_WriteData() and SDIO_GetFIFOCount() functions.
|
||||
|
||||
*** Read Operations ***
|
||||
-----------------------
|
||||
[..]
|
||||
(#) First, user has to fill the data structure (pointer to
|
||||
SDIO_DataInitTypeDef) according to the selected data type to be received.
|
||||
The parameters that should be filled are:
|
||||
(++) Data TimeOut.
|
||||
(++) Data Length.
|
||||
(++) Data Block size.
|
||||
(++) Data Transfer direction: should be from card (To SDIO).
|
||||
(++) Data Transfer mode.
|
||||
(++) DPSM Status (Enable or Disable).
|
||||
(#) Configure the SDIO resources to receive the data from the card
|
||||
according to selected transfer mode (Refer to Step 8, 9 and 10).
|
||||
(#) Send the selected Read command (refer to step 11).
|
||||
(#) Use the SDIO flags/interrupts to check the transfer status.
|
||||
|
||||
*** Write Operations ***
|
||||
------------------------
|
||||
[..]
|
||||
(#) First, user has to fill the data structure (pointer to
|
||||
SDIO_DataInitTypeDef) according to the selected data type to be received.
|
||||
The parameters that should be filled are:
|
||||
(++) Data TimeOut.
|
||||
(++) Data Length.
|
||||
(++) Data Block size.
|
||||
(++) Data Transfer direction: should be to card (To CARD).
|
||||
(++) Data Transfer mode.
|
||||
(++) DPSM Status (Enable or Disable).
|
||||
(#) Configure the SDIO resources to send the data to the card
|
||||
according to selected transfer mode (Refer to Step 8, 9 and 10).
|
||||
(#) Send the selected Write command (refer to step 11).
|
||||
(#) Use the SDIO flags/interrupts to check the transfer status.
|
||||
|
||||
@endverbatim
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32l1xx_sdio.h"
|
||||
#include "stm32l1xx_rcc.h"
|
||||
|
||||
/** @addtogroup STM32L1xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO
|
||||
* @brief SDIO driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
|
||||
/* ------------ SDIO registers bit address in the alias region ----------- */
|
||||
#define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE)
|
||||
|
||||
/* --- CLKCR Register ---*/
|
||||
|
||||
/* Alias word address of CLKEN bit */
|
||||
#define CLKCR_OFFSET (SDIO_OFFSET + 0x04)
|
||||
#define CLKEN_BitNumber 0x08
|
||||
#define CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BitNumber * 4))
|
||||
|
||||
/* --- CMD Register ---*/
|
||||
|
||||
/* Alias word address of SDIOSUSPEND bit */
|
||||
#define CMD_OFFSET (SDIO_OFFSET + 0x0C)
|
||||
#define SDIOSUSPEND_BitNumber 0x0B
|
||||
#define CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BitNumber * 4))
|
||||
|
||||
/* Alias word address of ENCMDCOMPL bit */
|
||||
#define ENCMDCOMPL_BitNumber 0x0C
|
||||
#define CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BitNumber * 4))
|
||||
|
||||
/* Alias word address of NIEN bit */
|
||||
#define NIEN_BitNumber 0x0D
|
||||
#define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BitNumber * 4))
|
||||
|
||||
/* Alias word address of ATACMD bit */
|
||||
#define ATACMD_BitNumber 0x0E
|
||||
#define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BitNumber * 4))
|
||||
|
||||
/* --- DCTRL Register ---*/
|
||||
|
||||
/* Alias word address of DMAEN bit */
|
||||
#define DCTRL_OFFSET (SDIO_OFFSET + 0x2C)
|
||||
#define DMAEN_BitNumber 0x03
|
||||
#define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BitNumber * 4))
|
||||
|
||||
/* Alias word address of RWSTART bit */
|
||||
#define RWSTART_BitNumber 0x08
|
||||
#define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BitNumber * 4))
|
||||
|
||||
/* Alias word address of RWSTOP bit */
|
||||
#define RWSTOP_BitNumber 0x09
|
||||
#define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BitNumber * 4))
|
||||
|
||||
/* Alias word address of RWMOD bit */
|
||||
#define RWMOD_BitNumber 0x0A
|
||||
#define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BitNumber * 4))
|
||||
|
||||
/* Alias word address of SDIOEN bit */
|
||||
#define SDIOEN_BitNumber 0x0B
|
||||
#define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BitNumber * 4))
|
||||
|
||||
/* ---------------------- SDIO registers bit mask ------------------------ */
|
||||
|
||||
/* --- CLKCR Register ---*/
|
||||
|
||||
/* CLKCR register clear mask */
|
||||
#define CLKCR_CLEAR_MASK ((uint32_t)0xFFFF8100)
|
||||
|
||||
/* --- PWRCTRL Register ---*/
|
||||
|
||||
/* SDIO PWRCTRL Mask */
|
||||
#define PWR_PWRCTRL_MASK ((uint32_t)0xFFFFFFFC)
|
||||
|
||||
/* --- DCTRL Register ---*/
|
||||
|
||||
/* SDIO DCTRL Clear Mask */
|
||||
#define DCTRL_CLEAR_MASK ((uint32_t)0xFFFFFF08)
|
||||
|
||||
/* --- CMD Register ---*/
|
||||
|
||||
/* CMD Register clear mask */
|
||||
#define CMD_CLEAR_MASK ((uint32_t)0xFFFFF800)
|
||||
|
||||
/* SDIO RESP Registers Address */
|
||||
#define SDIO_RESP_ADDR ((uint32_t)(SDIO_BASE + 0x14))
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup SDIO_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO_Group1 Initialization and Configuration functions
|
||||
* @brief Initialization and Configuration functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### Initialization and Configuration functions #####
|
||||
==============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the SDIO peripheral registers to their default reset values.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void SDIO_DeInit(void)
|
||||
{
|
||||
RCC_APB2PeriphResetCmd(RCC_APB2Periph_SDIO, ENABLE);
|
||||
RCC_APB2PeriphResetCmd(RCC_APB2Periph_SDIO, DISABLE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the SDIO peripheral according to the specified
|
||||
* parameters in the SDIO_InitStruct.
|
||||
* @param SDIO_InitStruct : pointer to a SDIO_InitTypeDef structure
|
||||
* that contains the configuration information for the SDIO peripheral.
|
||||
* @retval None
|
||||
*/
|
||||
void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct)
|
||||
{
|
||||
uint32_t tmpreg = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SDIO_CLOCK_EDGE(SDIO_InitStruct->SDIO_ClockEdge));
|
||||
assert_param(IS_SDIO_CLOCK_BYPASS(SDIO_InitStruct->SDIO_ClockBypass));
|
||||
assert_param(IS_SDIO_CLOCK_POWER_SAVE(SDIO_InitStruct->SDIO_ClockPowerSave));
|
||||
assert_param(IS_SDIO_BUS_WIDE(SDIO_InitStruct->SDIO_BusWide));
|
||||
assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(SDIO_InitStruct->SDIO_HardwareFlowControl));
|
||||
|
||||
/*---------------------------- SDIO CLKCR Configuration ------------------------*/
|
||||
/* Get the SDIO CLKCR value */
|
||||
tmpreg = SDIO->CLKCR;
|
||||
|
||||
/* Clear CLKDIV, PWRSAV, BYPASS, WIDBUS, NEGEDGE, HWFC_EN bits */
|
||||
tmpreg &= CLKCR_CLEAR_MASK;
|
||||
|
||||
/* Set CLKDIV bits according to SDIO_ClockDiv value */
|
||||
/* Set PWRSAV bit according to SDIO_ClockPowerSave value */
|
||||
/* Set BYPASS bit according to SDIO_ClockBypass value */
|
||||
/* Set WIDBUS bits according to SDIO_BusWide value */
|
||||
/* Set NEGEDGE bits according to SDIO_ClockEdge value */
|
||||
/* Set HWFC_EN bits according to SDIO_HardwareFlowControl value */
|
||||
tmpreg |= (SDIO_InitStruct->SDIO_ClockDiv | SDIO_InitStruct->SDIO_ClockPowerSave |
|
||||
SDIO_InitStruct->SDIO_ClockBypass | SDIO_InitStruct->SDIO_BusWide |
|
||||
SDIO_InitStruct->SDIO_ClockEdge | SDIO_InitStruct->SDIO_HardwareFlowControl);
|
||||
|
||||
/* Write to SDIO CLKCR */
|
||||
SDIO->CLKCR = tmpreg;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Fills each SDIO_InitStruct member with its default value.
|
||||
* @param SDIO_InitStruct: pointer to an SDIO_InitTypeDef structure which
|
||||
* will be initialized.
|
||||
* @retval None
|
||||
*/
|
||||
void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct)
|
||||
{
|
||||
/* SDIO_InitStruct members default value */
|
||||
SDIO_InitStruct->SDIO_ClockDiv = 0x00;
|
||||
SDIO_InitStruct->SDIO_ClockEdge = SDIO_ClockEdge_Rising;
|
||||
SDIO_InitStruct->SDIO_ClockBypass = SDIO_ClockBypass_Disable;
|
||||
SDIO_InitStruct->SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable;
|
||||
SDIO_InitStruct->SDIO_BusWide = SDIO_BusWide_1b;
|
||||
SDIO_InitStruct->SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the SDIO Clock.
|
||||
* @param NewState: new state of the SDIO Clock. This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void SDIO_ClockCmd(FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
*(__IO uint32_t *) CLKCR_CLKEN_BB = (uint32_t)NewState;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets the power status of the controller.
|
||||
* @param SDIO_PowerState: new state of the Power state.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SDIO_PowerState_OFF: SDIO Power OFF.
|
||||
* @arg SDIO_PowerState_ON: SDIO Power ON.
|
||||
* @retval None
|
||||
*/
|
||||
void SDIO_SetPowerState(uint32_t SDIO_PowerState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SDIO_POWER_STATE(SDIO_PowerState));
|
||||
|
||||
SDIO->POWER = SDIO_PowerState;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Gets the power status of the controller.
|
||||
* @param None
|
||||
* @retval Power status of the controller. The returned value can
|
||||
* be one of the following:
|
||||
* - 0x00: Power OFF
|
||||
* - 0x02: Power UP
|
||||
* - 0x03: Power ON
|
||||
*/
|
||||
uint32_t SDIO_GetPowerState(void)
|
||||
{
|
||||
return (SDIO->POWER & (~PWR_PWRCTRL_MASK));
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO_Group2 DMA transfers management functions
|
||||
* @brief DMA transfers management functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### DMA transfers management functions #####
|
||||
==============================================================================
|
||||
[..] This section provide functions allowing to program SDIO DMA transfer.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the SDIO DMA request.
|
||||
* @param NewState: new state of the selected SDIO DMA request.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void SDIO_DMACmd(FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
*(__IO uint32_t *) DCTRL_DMAEN_BB = (uint32_t)NewState;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO_Group3 Command path state machine (CPSM) management functions
|
||||
* @brief Command path state machine (CPSM) management functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### Command path state machine (CPSM) management functions #####
|
||||
==============================================================================
|
||||
[..] This section provide functions allowing to program and read the Command
|
||||
path state machine (CPSM).
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Initializes the SDIO Command according to the specified
|
||||
* parameters in the SDIO_CmdInitStruct and send the command.
|
||||
* @param SDIO_CmdInitStruct : pointer to a SDIO_CmdInitTypeDef
|
||||
* structure that contains the configuration information for the SDIO command.
|
||||
* @retval None
|
||||
*/
|
||||
void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct)
|
||||
{
|
||||
uint32_t tmpreg = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SDIO_CMD_INDEX(SDIO_CmdInitStruct->SDIO_CmdIndex));
|
||||
assert_param(IS_SDIO_RESPONSE(SDIO_CmdInitStruct->SDIO_Response));
|
||||
assert_param(IS_SDIO_WAIT(SDIO_CmdInitStruct->SDIO_Wait));
|
||||
assert_param(IS_SDIO_CPSM(SDIO_CmdInitStruct->SDIO_CPSM));
|
||||
|
||||
/*---------------------------- SDIO ARG Configuration ------------------------*/
|
||||
/* Set the SDIO Argument value */
|
||||
SDIO->ARG = SDIO_CmdInitStruct->SDIO_Argument;
|
||||
|
||||
/*---------------------------- SDIO CMD Configuration ------------------------*/
|
||||
/* Get the SDIO CMD value */
|
||||
tmpreg = SDIO->CMD;
|
||||
/* Clear CMDINDEX, WAITRESP, WAITINT, WAITPEND, CPSMEN bits */
|
||||
tmpreg &= CMD_CLEAR_MASK;
|
||||
/* Set CMDINDEX bits according to SDIO_CmdIndex value */
|
||||
/* Set WAITRESP bits according to SDIO_Response value */
|
||||
/* Set WAITINT and WAITPEND bits according to SDIO_Wait value */
|
||||
/* Set CPSMEN bits according to SDIO_CPSM value */
|
||||
tmpreg |= (uint32_t)SDIO_CmdInitStruct->SDIO_CmdIndex | SDIO_CmdInitStruct->SDIO_Response
|
||||
| SDIO_CmdInitStruct->SDIO_Wait | SDIO_CmdInitStruct->SDIO_CPSM;
|
||||
|
||||
/* Write to SDIO CMD */
|
||||
SDIO->CMD = tmpreg;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Fills each SDIO_CmdInitStruct member with its default value.
|
||||
* @param SDIO_CmdInitStruct: pointer to an SDIO_CmdInitTypeDef
|
||||
* structure which will be initialized.
|
||||
* @retval None
|
||||
*/
|
||||
void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct)
|
||||
{
|
||||
/* SDIO_CmdInitStruct members default value */
|
||||
SDIO_CmdInitStruct->SDIO_Argument = 0x00;
|
||||
SDIO_CmdInitStruct->SDIO_CmdIndex = 0x00;
|
||||
SDIO_CmdInitStruct->SDIO_Response = SDIO_Response_No;
|
||||
SDIO_CmdInitStruct->SDIO_Wait = SDIO_Wait_No;
|
||||
SDIO_CmdInitStruct->SDIO_CPSM = SDIO_CPSM_Disable;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns command index of last command for which response received.
|
||||
* @param None
|
||||
* @retval Returns the command index of the last command response received.
|
||||
*/
|
||||
uint8_t SDIO_GetCommandResponse(void)
|
||||
{
|
||||
return (uint8_t)(SDIO->RESPCMD);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns response received from the card for the last command.
|
||||
* @param SDIO_RESP: Specifies the SDIO response register.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SDIO_RESP1: Response Register 1.
|
||||
* @arg SDIO_RESP2: Response Register 2.
|
||||
* @arg SDIO_RESP3: Response Register 3.
|
||||
* @arg SDIO_RESP4: Response Register 4.
|
||||
* @retval The Corresponding response register value.
|
||||
*/
|
||||
uint32_t SDIO_GetResponse(uint32_t SDIO_RESP)
|
||||
{
|
||||
__IO uint32_t tmp = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SDIO_RESP(SDIO_RESP));
|
||||
|
||||
tmp = SDIO_RESP_ADDR + SDIO_RESP;
|
||||
|
||||
return (*(__IO uint32_t *) tmp);
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO_Group4 Data path state machine (DPSM) management functions
|
||||
* @brief Data path state machine (DPSM) management functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### Data path state machine (DPSM) management functions #####
|
||||
==============================================================================
|
||||
[..] This section provide functions allowing to program and read the Data path
|
||||
state machine (DPSM).
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Initializes the SDIO data path according to the specified
|
||||
* parameters in the SDIO_DataInitStruct.
|
||||
* @param SDIO_DataInitStruct : pointer to a SDIO_DataInitTypeDef structure that
|
||||
* contains the configuration information for the SDIO command.
|
||||
* @retval None
|
||||
*/
|
||||
void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct)
|
||||
{
|
||||
uint32_t tmpreg = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SDIO_DATA_LENGTH(SDIO_DataInitStruct->SDIO_DataLength));
|
||||
assert_param(IS_SDIO_BLOCK_SIZE(SDIO_DataInitStruct->SDIO_DataBlockSize));
|
||||
assert_param(IS_SDIO_TRANSFER_DIR(SDIO_DataInitStruct->SDIO_TransferDir));
|
||||
assert_param(IS_SDIO_TRANSFER_MODE(SDIO_DataInitStruct->SDIO_TransferMode));
|
||||
assert_param(IS_SDIO_DPSM(SDIO_DataInitStruct->SDIO_DPSM));
|
||||
|
||||
/*---------------------------- SDIO DTIMER Configuration ---------------------*/
|
||||
/* Set the SDIO Data TimeOut value */
|
||||
SDIO->DTIMER = SDIO_DataInitStruct->SDIO_DataTimeOut;
|
||||
|
||||
/*---------------------------- SDIO DLEN Configuration -----------------------*/
|
||||
/* Set the SDIO DataLength value */
|
||||
SDIO->DLEN = SDIO_DataInitStruct->SDIO_DataLength;
|
||||
|
||||
/*---------------------------- SDIO DCTRL Configuration ----------------------*/
|
||||
/* Get the SDIO DCTRL value */
|
||||
tmpreg = SDIO->DCTRL;
|
||||
/* Clear DEN, DTMODE, DTDIR and DBCKSIZE bits */
|
||||
tmpreg &= DCTRL_CLEAR_MASK;
|
||||
/* Set DEN bit according to SDIO_DPSM value */
|
||||
/* Set DTMODE bit according to SDIO_TransferMode value */
|
||||
/* Set DTDIR bit according to SDIO_TransferDir value */
|
||||
/* Set DBCKSIZE bits according to SDIO_DataBlockSize value */
|
||||
tmpreg |= (uint32_t)SDIO_DataInitStruct->SDIO_DataBlockSize | SDIO_DataInitStruct->SDIO_TransferDir
|
||||
| SDIO_DataInitStruct->SDIO_TransferMode | SDIO_DataInitStruct->SDIO_DPSM;
|
||||
|
||||
/* Write to SDIO DCTRL */
|
||||
SDIO->DCTRL = tmpreg;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Fills each SDIO_DataInitStruct member with its default value.
|
||||
* @param SDIO_DataInitStruct: pointer to an SDIO_DataInitTypeDef structure which
|
||||
* will be initialized.
|
||||
* @retval None
|
||||
*/
|
||||
void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct)
|
||||
{
|
||||
/* SDIO_DataInitStruct members default value */
|
||||
SDIO_DataInitStruct->SDIO_DataTimeOut = 0xFFFFFFFF;
|
||||
SDIO_DataInitStruct->SDIO_DataLength = 0x00;
|
||||
SDIO_DataInitStruct->SDIO_DataBlockSize = SDIO_DataBlockSize_1b;
|
||||
SDIO_DataInitStruct->SDIO_TransferDir = SDIO_TransferDir_ToCard;
|
||||
SDIO_DataInitStruct->SDIO_TransferMode = SDIO_TransferMode_Block;
|
||||
SDIO_DataInitStruct->SDIO_DPSM = SDIO_DPSM_Disable;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns number of remaining data bytes to be transferred.
|
||||
* @param None
|
||||
* @retval Number of remaining data bytes to be transferred
|
||||
*/
|
||||
uint32_t SDIO_GetDataCounter(void)
|
||||
{
|
||||
return SDIO->DCOUNT;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Read one data word from Rx FIFO.
|
||||
* @param None
|
||||
* @retval Data received
|
||||
*/
|
||||
uint32_t SDIO_ReadData(void)
|
||||
{
|
||||
return SDIO->FIFO;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Write one data word to Tx FIFO.
|
||||
* @param Data: 32-bit data word to write.
|
||||
* @retval None
|
||||
*/
|
||||
void SDIO_WriteData(uint32_t Data)
|
||||
{
|
||||
SDIO->FIFO = Data;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the number of words left to be written to or read from FIFO.
|
||||
* @param None
|
||||
* @retval Remaining number of words.
|
||||
*/
|
||||
uint32_t SDIO_GetFIFOCount(void)
|
||||
{
|
||||
return SDIO->FIFOCNT;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO_Group5 SDIO IO Cards mode management functions
|
||||
* @brief SDIO IO Cards mode management functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### SDIO IO Cards mode management functions #####
|
||||
==============================================================================
|
||||
[..] This section provide functions allowing to program and read the SDIO IO
|
||||
Cards.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Starts the SD I/O Read Wait operation.
|
||||
* @param NewState: new state of the Start SDIO Read Wait operation.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void SDIO_StartSDIOReadWait(FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
*(__IO uint32_t *) DCTRL_RWSTART_BB = (uint32_t) NewState;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Stops the SD I/O Read Wait operation.
|
||||
* @param NewState: new state of the Stop SDIO Read Wait operation.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void SDIO_StopSDIOReadWait(FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
*(__IO uint32_t *) DCTRL_RWSTOP_BB = (uint32_t) NewState;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets one of the two options of inserting read wait interval.
|
||||
* @param SDIO_ReadWaitMode: SD I/O Read Wait operation mode.
|
||||
* This parametre can be:
|
||||
* @arg SDIO_ReadWaitMode_CLK: Read Wait control by stopping SDIOCLK.
|
||||
* @arg SDIO_ReadWaitMode_DATA2: Read Wait control using SDIO_DATA2.
|
||||
* @retval None
|
||||
*/
|
||||
void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SDIO_READWAIT_MODE(SDIO_ReadWaitMode));
|
||||
|
||||
*(__IO uint32_t *) DCTRL_RWMOD_BB = SDIO_ReadWaitMode;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the SD I/O Mode Operation.
|
||||
* @param NewState: new state of SDIO specific operation.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void SDIO_SetSDIOOperation(FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
*(__IO uint32_t *) DCTRL_SDIOEN_BB = (uint32_t)NewState;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the SD I/O Mode suspend command sending.
|
||||
* @param NewState: new state of the SD I/O Mode suspend command.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void SDIO_SendSDIOSuspendCmd(FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = (uint32_t)NewState;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO_Group6 CE-ATA mode management functions
|
||||
* @brief CE-ATA mode management functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### CE-ATA mode management functions #####
|
||||
==============================================================================
|
||||
[..] This section provide functions allowing to program and read the CE-ATA
|
||||
card.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the command completion signal.
|
||||
* @param NewState: new state of command completion signal.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void SDIO_CommandCompletionCmd(FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = (uint32_t)NewState;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the CE-ATA interrupt.
|
||||
* @param NewState: new state of CE-ATA interrupt. This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void SDIO_CEATAITCmd(FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)((~((uint32_t)NewState)) & ((uint32_t)0x1));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sends CE-ATA command (CMD61).
|
||||
* @param NewState: new state of CE-ATA command. This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void SDIO_SendCEATACmd(FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
*(__IO uint32_t *) CMD_ATACMD_BB = (uint32_t)NewState;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SDIO_Group7 Interrupts and flags management functions
|
||||
* @brief Interrupts and flags management functions
|
||||
|
||||
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### Interrupts and flags management functions #####
|
||||
==============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enables or disables the SDIO interrupts.
|
||||
* @param SDIO_IT: specifies the SDIO interrupt sources to be enabled or disabled.
|
||||
* This parameter can be one or a combination of the following values:
|
||||
* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt.
|
||||
* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt.
|
||||
* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt.
|
||||
* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt.
|
||||
* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt.
|
||||
* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt.
|
||||
* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt.
|
||||
* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt.
|
||||
* @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt.
|
||||
* @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
|
||||
* bus mode interrupt.
|
||||
* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt.
|
||||
* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt.
|
||||
* @arg SDIO_IT_TXACT: Data transmit in progress interrupt.
|
||||
* @arg SDIO_IT_RXACT: Data receive in progress interrupt.
|
||||
* @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt.
|
||||
* @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt.
|
||||
* @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt.
|
||||
* @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt.
|
||||
* @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt.
|
||||
* @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt.
|
||||
* @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt.
|
||||
* @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt.
|
||||
* @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt.
|
||||
* @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt.
|
||||
* @param NewState: new state of the specified SDIO interrupts.
|
||||
* This parameter can be: ENABLE or DISABLE.
|
||||
* @retval None
|
||||
*/
|
||||
void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SDIO_IT(SDIO_IT));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the SDIO interrupts */
|
||||
SDIO->MASK |= SDIO_IT;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the SDIO interrupts */
|
||||
SDIO->MASK &= ~SDIO_IT;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified SDIO flag is set or not.
|
||||
* @param SDIO_FLAG: specifies the flag to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed).
|
||||
* @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed).
|
||||
* @arg SDIO_FLAG_CTIMEOUT: Command response timeout.
|
||||
* @arg SDIO_FLAG_DTIMEOUT: Data timeout.
|
||||
* @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error.
|
||||
* @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error.
|
||||
* @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed).
|
||||
* @arg SDIO_FLAG_CMDSENT: Command sent (no response required).
|
||||
* @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero).
|
||||
* @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide
|
||||
* bus mode.
|
||||
* @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed).
|
||||
* @arg SDIO_FLAG_CMDACT: Command transfer in progress.
|
||||
* @arg SDIO_FLAG_TXACT: Data transmit in progress.
|
||||
* @arg SDIO_FLAG_RXACT: Data receive in progress.
|
||||
* @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty.
|
||||
* @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full.
|
||||
* @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full.
|
||||
* @arg SDIO_FLAG_RXFIFOF: Receive FIFO full.
|
||||
* @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty.
|
||||
* @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty.
|
||||
* @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO.
|
||||
* @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO.
|
||||
* @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received.
|
||||
* @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61.
|
||||
* @retval The new state of SDIO_FLAG (SET or RESET).
|
||||
*/
|
||||
FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG)
|
||||
{
|
||||
FlagStatus bitstatus = RESET;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SDIO_FLAG(SDIO_FLAG));
|
||||
|
||||
if ((SDIO->STA & SDIO_FLAG) != (uint32_t)RESET)
|
||||
{
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = RESET;
|
||||
}
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the SDIO's pending flags.
|
||||
* @param SDIO_FLAG: specifies the flag to clear.
|
||||
* This parameter can be one or a combination of the following values:
|
||||
* @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed).
|
||||
* @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed).
|
||||
* @arg SDIO_FLAG_CTIMEOUT: Command response timeout.
|
||||
* @arg SDIO_FLAG_DTIMEOUT: Data timeout.
|
||||
* @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error.
|
||||
* @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error.
|
||||
* @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed).
|
||||
* @arg SDIO_FLAG_CMDSENT: Command sent (no response required).
|
||||
* @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero).
|
||||
* @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide
|
||||
* bus mode.
|
||||
* @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed).
|
||||
* @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received.
|
||||
* @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61.
|
||||
* @retval None
|
||||
*/
|
||||
void SDIO_ClearFlag(uint32_t SDIO_FLAG)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SDIO_CLEAR_FLAG(SDIO_FLAG));
|
||||
|
||||
SDIO->ICR = SDIO_FLAG;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Checks whether the specified SDIO interrupt has occurred or not.
|
||||
* @param SDIO_IT: specifies the SDIO interrupt source to check.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt.
|
||||
* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt.
|
||||
* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt.
|
||||
* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt.
|
||||
* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt.
|
||||
* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt.
|
||||
* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt.
|
||||
* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt.
|
||||
* @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt.
|
||||
* @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
|
||||
* bus mode interrupt.
|
||||
* @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt.
|
||||
* @arg SDIO_IT_CMDACT: Command transfer in progress interrupt.
|
||||
* @arg SDIO_IT_TXACT: Data transmit in progress interrupt.
|
||||
* @arg SDIO_IT_RXACT: Data receive in progress interrupt.
|
||||
* @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt.
|
||||
* @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt.
|
||||
* @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt.
|
||||
* @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt.
|
||||
* @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt.
|
||||
* @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt.
|
||||
* @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt.
|
||||
* @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt.
|
||||
* @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt.
|
||||
* @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt.
|
||||
* @retval The new state of SDIO_IT (SET or RESET).
|
||||
*/
|
||||
ITStatus SDIO_GetITStatus(uint32_t SDIO_IT)
|
||||
{
|
||||
ITStatus bitstatus = RESET;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SDIO_GET_IT(SDIO_IT));
|
||||
if ((SDIO->STA & SDIO_IT) != (uint32_t)RESET)
|
||||
{
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = RESET;
|
||||
}
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears the SDIO's interrupt pending bits.
|
||||
* @param SDIO_IT: specifies the interrupt pending bit to clear.
|
||||
* This parameter can be one or a combination of the following values:
|
||||
* @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt.
|
||||
* @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt.
|
||||
* @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt.
|
||||
* @arg SDIO_IT_DTIMEOUT: Data timeout interrupt.
|
||||
* @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt.
|
||||
* @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt.
|
||||
* @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt.
|
||||
* @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt.
|
||||
* @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt.
|
||||
* @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
|
||||
* bus mode interrupt.
|
||||
* @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt.
|
||||
* @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61.
|
||||
* @retval None
|
||||
*/
|
||||
void SDIO_ClearITPendingBit(uint32_t SDIO_IT)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SDIO_CLEAR_IT(SDIO_IT));
|
||||
|
||||
SDIO->ICR = SDIO_IT;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,652 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32l1xx_syscfg.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.1
|
||||
* @date 05-March-2012
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the SYSCFG and RI peripherals:
|
||||
* + SYSCFG Initialization and Configuration
|
||||
* + RI Initialization and Configuration
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### How to use this driver #####
|
||||
===============================================================================
|
||||
[..] This driver provides functions for:
|
||||
(#) Remapping the memory accessible in the code area using
|
||||
SYSCFG_MemoryRemapConfig().
|
||||
(#) Manage the EXTI lines connection to the GPIOs using
|
||||
SYSCFG_EXTILineConfig().
|
||||
(#) Routing of I/Os toward the input captures of timers (TIM2, TIM3 and TIM4).
|
||||
(#) Input routing of COMP1 and COMP2.
|
||||
(#) Routing of internal reference voltage VREFINT to PB0 and PB1.
|
||||
(#) The RI registers can be accessed only when the comparator
|
||||
APB interface clock is enabled.
|
||||
To enable comparator clock use:
|
||||
RCC_APB1PeriphClockCmd(RCC_APB1Periph_COMP, ENABLE).
|
||||
Following functions uses RI registers:
|
||||
(++) SYSCFG_RIDeInit()
|
||||
(++) SYSCFG_RITIMSelect()
|
||||
(++) SYSCFG_RITIMInputCaptureConfig()
|
||||
(++) SYSCFG_RIResistorConfig()
|
||||
(++) SYSCFG_RIChannelSpeedConfig()
|
||||
(++) SYSCFG_RIIOSwitchConfig()
|
||||
(++) SYSCFG_RISwitchControlModeCmd()
|
||||
(++) SYSCFG_RIHysteresisConfig()
|
||||
(#) The SYSCFG registers can be accessed only when the SYSCFG
|
||||
interface APB clock is enabled.
|
||||
To enable SYSCFG APB clock use:
|
||||
RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
|
||||
Following functions uses SYSCFG registers:
|
||||
(++) SYSCFG_DeInit()
|
||||
(++) SYSCFG_MemoryRemapConfig()
|
||||
(++) SYSCFG_GetBootMode()
|
||||
(++) SYSCFG_USBPuCmd()
|
||||
(++) SYSCFG_EXTILineConfig()
|
||||
@endverbatim
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32l1xx_syscfg.h"
|
||||
#include "stm32l1xx_rcc.h"
|
||||
|
||||
/** @addtogroup STM32L1xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup SYSCFG
|
||||
* @brief SYSCFG driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
#define TIM_SELECT_MASK ((uint32_t)0xFFFCFFFF) /*!< TIM select mask */
|
||||
#define IC_ROUTING_MASK ((uint32_t)0x0000000F) /*!< Input Capture routing mask */
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup SYSCFG_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup SYSCFG_Group1 SYSCFG Initialization and Configuration functions
|
||||
* @brief SYSCFG Initialization and Configuration functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### SYSCFG Initialization and Configuration functions #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the SYSCFG registers to their default reset values.
|
||||
* @param None.
|
||||
* @retval None.
|
||||
* @Note: MEMRMP bits are not reset by APB2 reset.
|
||||
*/
|
||||
void SYSCFG_DeInit(void)
|
||||
{
|
||||
RCC_APB2PeriphResetCmd(RCC_APB2Periph_SYSCFG, ENABLE);
|
||||
RCC_APB2PeriphResetCmd(RCC_APB2Periph_SYSCFG, DISABLE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the RI registers to their default reset values.
|
||||
* @param None.
|
||||
* @retval None.
|
||||
*/
|
||||
void SYSCFG_RIDeInit(void)
|
||||
{
|
||||
RI->ICR = ((uint32_t)0x00000000); /*!< Set RI->ICR to reset value */
|
||||
RI->ASCR1 = ((uint32_t)0x00000000); /*!< Set RI->ASCR1 to reset value */
|
||||
RI->ASCR2 = ((uint32_t)0x00000000); /*!< Set RI->ASCR2 to reset value */
|
||||
RI->HYSCR1 = ((uint32_t)0x00000000); /*!< Set RI->HYSCR1 to reset value */
|
||||
RI->HYSCR2 = ((uint32_t)0x00000000); /*!< Set RI->HYSCR2 to reset value */
|
||||
RI->HYSCR3 = ((uint32_t)0x00000000); /*!< Set RI->HYSCR3 to reset value */
|
||||
RI->HYSCR4 = ((uint32_t)0x00000000); /*!< Set RI->HYSCR4 to reset value */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Changes the mapping of the specified memory.
|
||||
* @param SYSCFG_Memory: selects the memory remapping.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg SYSCFG_MemoryRemap_Flash: Main Flash memory mapped at 0x00000000
|
||||
* @arg SYSCFG_MemoryRemap_SystemFlash: System Flash memory mapped at 0x00000000
|
||||
* @arg SYSCFG_MemoryRemap_FSMC: FSMC memory mapped at 0x00000000
|
||||
* @arg SYSCFG_MemoryRemap_SRAM: Embedded SRAM mapped at 0x00000000
|
||||
* @retval None
|
||||
*/
|
||||
void SYSCFG_MemoryRemapConfig(uint8_t SYSCFG_MemoryRemap)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_SYSCFG_MEMORY_REMAP_CONFING(SYSCFG_MemoryRemap));
|
||||
SYSCFG->MEMRMP = SYSCFG_MemoryRemap;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Returns the boot mode as configured by user.
|
||||
* @param None.
|
||||
* @retval The boot mode as configured by user. The returned value can be one
|
||||
* of the following values:
|
||||
* - 0x00000000: Boot is configured in Main Flash memory
|
||||
* - 0x00000100: Boot is configured in System Flash memory
|
||||
* - 0x00000200: Boot is configured in FSMC memory
|
||||
* - 0x00000300: Boot is configured in Embedded SRAM memory
|
||||
*/
|
||||
uint32_t SYSCFG_GetBootMode(void)
|
||||
{
|
||||
return (SYSCFG->MEMRMP & SYSCFG_MEMRMP_BOOT_MODE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Control the internal pull-up on USB DP line.
|
||||
* @param NewState: New state of the internal pull-up on USB DP line.
|
||||
* This parameter can be ENABLE: Connect internal pull-up on USB DP line.
|
||||
* or DISABLE: Disconnect internal pull-up on USB DP line.
|
||||
* @retval None
|
||||
*/
|
||||
void SYSCFG_USBPuCmd(FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Connect internal pull-up on USB DP line */
|
||||
SYSCFG->PMC |= (uint32_t) SYSCFG_PMC_USB_PU;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disconnect internal pull-up on USB DP line */
|
||||
SYSCFG->PMC &= (uint32_t)(~SYSCFG_PMC_USB_PU);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Selects the GPIO pin used as EXTI Line.
|
||||
* @param EXTI_PortSourceGPIOx : selects the GPIO port to be used as source
|
||||
* for EXTI lines where x can be (A, B, C, D, E, F, G or H).
|
||||
* @param EXTI_PinSourcex: specifies the EXTI line to be configured.
|
||||
* This parameter can be EXTI_PinSourcex where x can be (0..15).
|
||||
* @retval None
|
||||
*/
|
||||
void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex)
|
||||
{
|
||||
uint32_t tmp = 0x00;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_EXTI_PORT_SOURCE(EXTI_PortSourceGPIOx));
|
||||
assert_param(IS_EXTI_PIN_SOURCE(EXTI_PinSourcex));
|
||||
|
||||
tmp = ((uint32_t)0x0F) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03));
|
||||
SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] &= ~tmp;
|
||||
SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] |= (((uint32_t)EXTI_PortSourceGPIOx) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03)));
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SYSCFG_Group2 RI Initialization and Configuration functions
|
||||
* @brief RI Initialization and Configuration functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### RI Initialization and Configuration functions #####
|
||||
===============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Configures the routing interface to select which Timer to be routed.
|
||||
* @note Routing capability can be applied only on one of the three timers
|
||||
* (TIM2, TIM3 or TIM4) at a time.
|
||||
* @param TIM_Select: Timer select.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg TIM_Select_None: No timer selected and default Timer mapping is enabled.
|
||||
* @arg TIM_Select_TIM2: Timer 2 Input Captures to be routed.
|
||||
* @arg TIM_Select_TIM3: Timer 3 Input Captures to be routed.
|
||||
* @arg TIM_Select_TIM4: Timer 4 Input Captures to be routed.
|
||||
* @retval None.
|
||||
*/
|
||||
void SYSCFG_RITIMSelect(uint32_t TIM_Select)
|
||||
{
|
||||
uint32_t tmpreg = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_RI_TIM(TIM_Select));
|
||||
|
||||
/* Get the old register value */
|
||||
tmpreg = RI->ICR;
|
||||
|
||||
/* Clear the TIMx select bits */
|
||||
tmpreg &= TIM_SELECT_MASK;
|
||||
|
||||
/* Select the Timer */
|
||||
tmpreg |= (TIM_Select);
|
||||
|
||||
/* Write to RI->ICR register */
|
||||
RI->ICR = tmpreg;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures the routing interface to map Input Capture 1, 2, 3 or 4
|
||||
* to a selected I/O pin.
|
||||
* @param RI_InputCapture selects which input capture to be routed.
|
||||
* This parameter can be one (or combination) of the following parameters:
|
||||
* @arg RI_InputCapture_IC1: Input capture 1 is selected.
|
||||
* @arg RI_InputCapture_IC2: Input capture 2 is selected.
|
||||
* @arg RI_InputCapture_IC3: Input capture 3 is selected.
|
||||
* @arg RI_InputCapture_IC4: Input capture 4 is selected.
|
||||
* @param RI_InputCaptureRouting: selects which pin to be routed to Input Capture.
|
||||
* This parameter can be one of the following values:
|
||||
* @param RI_InputCaptureRouting_0 to RI_InputCaptureRouting_15
|
||||
* e.g.
|
||||
* SYSCFG_RITIMSelect(TIM_Select_TIM2)
|
||||
* SYSCFG_RITIMInputCaptureConfig(RI_InputCapture_IC1, RI_InputCaptureRouting_1)
|
||||
* allows routing of Input capture IC1 of TIM2 to PA4.
|
||||
* For details about correspondence between RI_InputCaptureRouting_x
|
||||
* and I/O pins refer to the parameters' description in the header file
|
||||
* or refer to the product reference manual.
|
||||
* @note Input capture selection bits are not reset by this function.
|
||||
* To reset input capture selection bits, use SYSCFG_RIDeInit() function.
|
||||
* @note The I/O should be configured in alternate function mode (AF14) using
|
||||
* GPIO_PinAFConfig() function.
|
||||
* @retval None.
|
||||
*/
|
||||
void SYSCFG_RITIMInputCaptureConfig(uint32_t RI_InputCapture, uint32_t RI_InputCaptureRouting)
|
||||
{
|
||||
uint32_t tmpreg = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_RI_INPUTCAPTURE(RI_InputCapture));
|
||||
assert_param(IS_RI_INPUTCAPTURE_ROUTING(RI_InputCaptureRouting));
|
||||
|
||||
/* Get the old register value */
|
||||
tmpreg = RI->ICR;
|
||||
|
||||
/* Select input captures to be routed */
|
||||
tmpreg |= (RI_InputCapture);
|
||||
|
||||
if((RI_InputCapture & RI_InputCapture_IC1) == RI_InputCapture_IC1)
|
||||
{
|
||||
/* Clear the input capture select bits */
|
||||
tmpreg &= (uint32_t)(~IC_ROUTING_MASK);
|
||||
|
||||
/* Set RI_InputCaptureRouting bits */
|
||||
tmpreg |= (uint32_t)( RI_InputCaptureRouting);
|
||||
}
|
||||
|
||||
if((RI_InputCapture & RI_InputCapture_IC2) == RI_InputCapture_IC2)
|
||||
{
|
||||
/* Clear the input capture select bits */
|
||||
tmpreg &= (uint32_t)(~(IC_ROUTING_MASK << 4));
|
||||
|
||||
/* Set RI_InputCaptureRouting bits */
|
||||
tmpreg |= (uint32_t)( (RI_InputCaptureRouting << 4));
|
||||
}
|
||||
|
||||
if((RI_InputCapture & RI_InputCapture_IC3) == RI_InputCapture_IC3)
|
||||
{
|
||||
/* Clear the input capture select bits */
|
||||
tmpreg &= (uint32_t)(~(IC_ROUTING_MASK << 8));
|
||||
|
||||
/* Set RI_InputCaptureRouting bits */
|
||||
tmpreg |= (uint32_t)( (RI_InputCaptureRouting << 8));
|
||||
}
|
||||
|
||||
if((RI_InputCapture & RI_InputCapture_IC4) == RI_InputCapture_IC4)
|
||||
{
|
||||
/* Clear the input capture select bits */
|
||||
tmpreg &= (uint32_t)(~(IC_ROUTING_MASK << 12));
|
||||
|
||||
/* Set RI_InputCaptureRouting bits */
|
||||
tmpreg |= (uint32_t)( (RI_InputCaptureRouting << 12));
|
||||
}
|
||||
|
||||
/* Write to RI->ICR register */
|
||||
RI->ICR = tmpreg;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures the Pull-up and Pull-down Resistors
|
||||
* @param RI_Resistor selects the resistor to connect.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg RI_Resistor_10KPU: 10K pull-up resistor.
|
||||
* @arg RI_Resistor_400KPU: 400K pull-up resistor.
|
||||
* @arg RI_Resistor_10KPD: 10K pull-down resistor.
|
||||
* @arg RI_Resistor_400KPD: 400K pull-down resistor.
|
||||
* @param NewState: New state of the analog switch associated to the selected
|
||||
* resistor.
|
||||
* This parameter can be:
|
||||
* ENABLE so the selected resistor is connected
|
||||
* or DISABLE so the selected resistor is disconnected.
|
||||
* @note To avoid extra power consumption, only one resistor should be enabled
|
||||
* at a time.
|
||||
* @retval None
|
||||
*/
|
||||
void SYSCFG_RIResistorConfig(uint32_t RI_Resistor, FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_RI_RESISTOR(RI_Resistor));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the resistor */
|
||||
COMP->CSR |= (uint32_t) RI_Resistor;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the Resistor */
|
||||
COMP->CSR &= (uint32_t) (~RI_Resistor);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configures the ADC channels speed.
|
||||
* @param RI_Channel selects the channel.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg RI_Channel_3: Channel 3 is selected.
|
||||
* @arg RI_Channel_8: Channel 8 is selected.
|
||||
* @arg RI_Channel_13: Channel 13 is selected.
|
||||
* @param RI_ChannelSpeed: The speed of the selected ADC channel
|
||||
* This parameter can be:
|
||||
* RI_ChannelSpeed_Fast: The selected channel is a fast ADC channel
|
||||
* or RI_ChannelSpeed_Slow: The selected channel is a slow ADC channel.
|
||||
* @retval None
|
||||
*/
|
||||
void SYSCFG_RIChannelSpeedConfig(uint32_t RI_Channel, uint32_t RI_ChannelSpeed)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_RI_CHANNEL(RI_Channel));
|
||||
assert_param(IS_RI_CHANNELSPEED(RI_ChannelSpeed));
|
||||
|
||||
if(RI_ChannelSpeed != RI_ChannelSpeed_Fast)
|
||||
{
|
||||
/* Set the selected channel as a slow ADC channel */
|
||||
COMP->CSR &= (uint32_t) (~RI_Channel);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Set the selected channel as a fast ADC channel */
|
||||
COMP->CSR |= (uint32_t) (RI_Channel);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Close or Open the routing interface Input Output switches.
|
||||
* @param RI_IOSwitch: selects the I/O analog switch number.
|
||||
* This parameter can be one of the following values:
|
||||
* @param RI_IOSwitch_CH0 --> RI_IOSwitch_CH15.
|
||||
* @param RI_IOSwitch_CH18 --> RI_IOSwitch_CH25.
|
||||
* @param RI_IOSwitch_GR10_1 --> RI_IOSwitch_GR10_4.
|
||||
* @param RI_IOSwitch_GR6_1 --> RI_IOSwitch_GR6_2.
|
||||
* @param RI_IOSwitch_GR5_1 --> RI_IOSwitch_GR5_3.
|
||||
* @param RI_IOSwitch_GR4_1 --> RI_IOSwitch_GR4_3.
|
||||
* @param RI_IOSwitch_VCOMP
|
||||
* RI_IOSwitch_CH27
|
||||
* @param RI_IOSwitch_CH28 --> RI_IOSwitch_CH30
|
||||
* @param RI_IOSwitch_GR10_1 --> RI_IOSwitch_GR10_4
|
||||
* @param RI_IOSwitch_GR6_1
|
||||
* @param RI_IOSwitch_GR6_2
|
||||
* @param RI_IOSwitch_GR5_1 --> RI_IOSwitch_GR5_3
|
||||
* @param RI_IOSwitch_GR4_1 --> RI_IOSwitch_GR4_4
|
||||
* @param RI_IOSwitch_CH0b --> RI_IOSwitch_CH3b
|
||||
* @param RI_IOSwitch_CH6b --> RI_IOSwitch_CH12b
|
||||
* @param RI_IOSwitch_GR6_3
|
||||
* @param RI_IOSwitch_GR6_4
|
||||
* @param RI_IOSwitch_GR5_4
|
||||
|
||||
* @param NewState: New state of the analog switch.
|
||||
* This parameter can be
|
||||
* ENABLE so the Input Output switch is closed
|
||||
* or DISABLE so the Input Output switch is open.
|
||||
* @retval None
|
||||
*/
|
||||
void SYSCFG_RIIOSwitchConfig(uint32_t RI_IOSwitch, FunctionalState NewState)
|
||||
{
|
||||
uint32_t ioswitchmask = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_RI_IOSWITCH(RI_IOSwitch));
|
||||
|
||||
/* Read Analog switch register index */
|
||||
ioswitchmask = RI_IOSwitch >> 31;
|
||||
|
||||
/* Get Bits[30:0] of the IO switch */
|
||||
RI_IOSwitch &= 0x7FFFFFFF;
|
||||
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
if (ioswitchmask != 0)
|
||||
{
|
||||
/* Close the analog switches */
|
||||
RI->ASCR1 |= RI_IOSwitch;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Open the analog switches */
|
||||
RI->ASCR2 |= RI_IOSwitch;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
if (ioswitchmask != 0)
|
||||
{
|
||||
/* Close the analog switches */
|
||||
RI->ASCR1 &= (~ (uint32_t)RI_IOSwitch);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Open the analog switches */
|
||||
RI->ASCR2 &= (~ (uint32_t)RI_IOSwitch);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable or disable the switch control mode.
|
||||
* @param NewState: New state of the switch control mode. This parameter can
|
||||
* be ENABLE: ADC analog switches closed if the corresponding
|
||||
* I/O switch is also closed.
|
||||
* When using COMP1, switch control mode must be enabled.
|
||||
* or DISABLE: ADC analog switches open or controlled by the ADC interface.
|
||||
* When using the ADC for acquisition, switch control mode
|
||||
* must be disabled.
|
||||
* @note COMP1 comparator and ADC cannot be used at the same time since
|
||||
* they share the ADC switch matrix.
|
||||
* @retval None
|
||||
*/
|
||||
void SYSCFG_RISwitchControlModeCmd(FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Enable the Switch control mode */
|
||||
RI->ASCR1 |= (uint32_t) RI_ASCR1_SCM;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable the Switch control mode */
|
||||
RI->ASCR1 &= (uint32_t)(~RI_ASCR1_SCM);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable or disable Hysteresis of the input schmitt triger of Ports A..E
|
||||
* When the I/Os are programmed in input mode by standard I/O port
|
||||
* registers, the Schmitt trigger and the hysteresis are enabled by default.
|
||||
* When hysteresis is disabled, it is possible to read the
|
||||
* corresponding port with a trigger level of VDDIO/2.
|
||||
* @param RI_Port: selects the GPIO Port.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg RI_PortA: Port A is selected
|
||||
* @arg RI_PortB: Port B is selected
|
||||
* @arg RI_PortC: Port C is selected
|
||||
* @arg RI_PortD: Port D is selected
|
||||
* @arg RI_PortE: Port E is selected
|
||||
* @arg RI_PortF: Port F is selected
|
||||
* @arg RI_PortG: Port G is selected
|
||||
* @param RI_Pin : Selects the pin(s) on which to enable or disable hysteresis.
|
||||
* This parameter can any value from RI_Pin_x where x can be (0..15) or RI_Pin_All.
|
||||
* @param NewState new state of the Hysteresis.
|
||||
* This parameter can be:
|
||||
* ENABLE so the Hysteresis is on
|
||||
* or DISABLE so the Hysteresis is off
|
||||
* @retval None
|
||||
*/
|
||||
void SYSCFG_RIHysteresisConfig(uint8_t RI_Port, uint16_t RI_Pin,
|
||||
FunctionalState NewState)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_RI_PORT(RI_Port));
|
||||
assert_param(IS_RI_PIN(RI_Pin));
|
||||
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
||||
|
||||
if(RI_Port == RI_PortA)
|
||||
{
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Hysteresis on */
|
||||
RI->HYSCR1 &= (uint32_t)~((uint32_t)RI_Pin);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Hysteresis off */
|
||||
RI->HYSCR1 |= (uint32_t) RI_Pin;
|
||||
}
|
||||
}
|
||||
|
||||
else if(RI_Port == RI_PortB)
|
||||
{
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Hysteresis on */
|
||||
RI->HYSCR1 &= (uint32_t) (~((uint32_t)RI_Pin) << 16);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Hysteresis off */
|
||||
RI->HYSCR1 |= (uint32_t) ((uint32_t)(RI_Pin) << 16);
|
||||
}
|
||||
}
|
||||
|
||||
else if(RI_Port == RI_PortC)
|
||||
{
|
||||
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Hysteresis on */
|
||||
RI->HYSCR2 &= (uint32_t) (~((uint32_t)RI_Pin));
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Hysteresis off */
|
||||
RI->HYSCR2 |= (uint32_t) (RI_Pin );
|
||||
}
|
||||
}
|
||||
else if(RI_Port == RI_PortD)
|
||||
{
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Hysteresis on */
|
||||
RI->HYSCR2 &= (uint32_t) (~((uint32_t)RI_Pin) << 16);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Hysteresis off */
|
||||
RI->HYSCR2 |= (uint32_t) ((uint32_t)(RI_Pin) << 16);
|
||||
|
||||
}
|
||||
}
|
||||
else if(RI_Port == RI_PortE)
|
||||
{
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Hysteresis on */
|
||||
RI->HYSCR3 &= (uint32_t) (~((uint32_t)RI_Pin));
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Hysteresis off */
|
||||
RI->HYSCR3 |= (uint32_t) (RI_Pin );
|
||||
}
|
||||
}
|
||||
else if(RI_Port == RI_PortF)
|
||||
{
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Hysteresis on */
|
||||
RI->HYSCR3 &= (uint32_t) (~((uint32_t)RI_Pin) << 16);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Hysteresis off */
|
||||
RI->HYSCR3 |= (uint32_t) ((uint32_t)(RI_Pin) << 16);
|
||||
}
|
||||
}
|
||||
else /* RI_Port == RI_PortG */
|
||||
{
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
/* Hysteresis on */
|
||||
RI->HYSCR4 &= (uint32_t) (~((uint32_t)RI_Pin));
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Hysteresis off */
|
||||
RI->HYSCR4 |= (uint32_t) (RI_Pin);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load diff
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,313 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file stm32l1xx_wwdg.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.1.1
|
||||
* @date 05-March-2012
|
||||
* @brief This file provides firmware functions to manage the following
|
||||
* functionalities of the Window watchdog (WWDG) peripheral:
|
||||
* + Prescaler, Refresh window and Counter configuration
|
||||
* + WWDG activation
|
||||
* + Interrupts and flags management
|
||||
*
|
||||
* @verbatim
|
||||
*
|
||||
==============================================================================
|
||||
##### WWDG features #####
|
||||
==============================================================================
|
||||
[..] Once enabled the WWDG generates a system reset on expiry of a programmed
|
||||
time period, unless the program refreshes the counter (downcounter)
|
||||
before to reach 0x3F value (i.e. a reset is generated when the counter
|
||||
value rolls over from 0x40 to 0x3F).
|
||||
[..] An MCU reset is also generated if the counter value is refreshed
|
||||
before the counter has reached the refresh window value. This
|
||||
implies that the counter must be refreshed in a limited window.
|
||||
|
||||
[..] Once enabled the WWDG cannot be disabled except by a system reset.
|
||||
|
||||
[..] WWDGRST flag in RCC_CSR register can be used to inform when a WWDG
|
||||
reset occurs.
|
||||
|
||||
[..] The WWDG counter input clock is derived from the APB clock divided
|
||||
by a programmable prescaler.
|
||||
|
||||
[..] WWDG counter clock = PCLK1 / Prescaler.
|
||||
[..] WWDG timeout = (WWDG counter clock) * (counter value).
|
||||
|
||||
[..] Min-max timeout value @32MHz (PCLK1): ~128us / ~65.6ms.
|
||||
|
||||
##### How to use this driver #####
|
||||
==============================================================================
|
||||
[..]
|
||||
(#) Enable WWDG clock using RCC_APB1PeriphClockCmd(RCC_APB1Periph_WWDG, ENABLE)
|
||||
function.
|
||||
|
||||
(#) Configure the WWDG prescaler using WWDG_SetPrescaler() function.
|
||||
|
||||
(#) Configure the WWDG refresh window using WWDG_SetWindowValue() function.
|
||||
|
||||
(#) Set the WWDG counter value and start it using WWDG_Enable() function.
|
||||
When the WWDG is enabled the counter value should be configured to
|
||||
a value greater than 0x40 to prevent generating an immediate reset.
|
||||
|
||||
(#) Optionally you can enable the Early wakeup interrupt which is
|
||||
generated when the counter reach 0x40.
|
||||
Once enabled this interrupt cannot be disabled except by a system reset.
|
||||
|
||||
(#) Then the application program must refresh the WWDG counter at regular
|
||||
intervals during normal operation to prevent an MCU reset, using
|
||||
WWDG_SetCounter() function. This operation must occur only when
|
||||
the counter value is lower than the refresh window value,
|
||||
programmed using WWDG_SetWindowValue().
|
||||
|
||||
* @endverbatim
|
||||
*
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32l1xx_wwdg.h"
|
||||
#include "stm32l1xx_rcc.h"
|
||||
|
||||
/** @addtogroup STM32L1xx_StdPeriph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup WWDG
|
||||
* @brief WWDG driver modules
|
||||
* @{
|
||||
*/
|
||||
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
|
||||
/* ----------- WWDG registers bit address in the alias region ----------- */
|
||||
#define WWDG_OFFSET (WWDG_BASE - PERIPH_BASE)
|
||||
|
||||
/* Alias word address of EWI bit */
|
||||
#define CFR_OFFSET (WWDG_OFFSET + 0x04)
|
||||
#define EWI_BitNumber 0x09
|
||||
#define CFR_EWI_BB (PERIPH_BB_BASE + (CFR_OFFSET * 32) + (EWI_BitNumber * 4))
|
||||
|
||||
/* --------------------- WWDG registers bit mask ------------------------ */
|
||||
|
||||
/* CFR register bit mask */
|
||||
#define CFR_WDGTB_MASK ((uint32_t)0xFFFFFE7F)
|
||||
#define CFR_W_MASK ((uint32_t)0xFFFFFF80)
|
||||
#define BIT_MASK ((uint8_t)0x7F)
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
/* Private functions ---------------------------------------------------------*/
|
||||
|
||||
/** @defgroup WWDG_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup WWDG_Group1 Prescaler, Refresh window and Counter configuration functions
|
||||
* @brief Prescaler, Refresh window and Counter configuration functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### Prescaler, Refresh window and Counter configuration functions #####
|
||||
==============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Deinitializes the WWDG peripheral registers to their default reset values.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void WWDG_DeInit(void)
|
||||
{
|
||||
RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE);
|
||||
RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets the WWDG Prescaler.
|
||||
* @param WWDG_Prescaler: specifies the WWDG Prescaler.
|
||||
* This parameter can be one of the following values:
|
||||
* @arg WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1
|
||||
* @arg WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2
|
||||
* @arg WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4
|
||||
* @arg WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8
|
||||
* @retval None
|
||||
*/
|
||||
void WWDG_SetPrescaler(uint32_t WWDG_Prescaler)
|
||||
{
|
||||
uint32_t tmpreg = 0;
|
||||
/* Check the parameters */
|
||||
assert_param(IS_WWDG_PRESCALER(WWDG_Prescaler));
|
||||
/* Clear WDGTB[1:0] bits */
|
||||
tmpreg = WWDG->CFR & CFR_WDGTB_MASK;
|
||||
/* Set WDGTB[1:0] bits according to WWDG_Prescaler value */
|
||||
tmpreg |= WWDG_Prescaler;
|
||||
/* Store the new value */
|
||||
WWDG->CFR = tmpreg;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets the WWDG window value.
|
||||
* @param WindowValue: specifies the window value to be compared to the downcounter.
|
||||
* This parameter value must be lower than 0x80.
|
||||
* @retval None
|
||||
*/
|
||||
void WWDG_SetWindowValue(uint8_t WindowValue)
|
||||
{
|
||||
__IO uint32_t tmpreg = 0;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_WWDG_WINDOW_VALUE(WindowValue));
|
||||
/* Clear W[6:0] bits */
|
||||
|
||||
tmpreg = WWDG->CFR & CFR_W_MASK;
|
||||
|
||||
/* Set W[6:0] bits according to WindowValue value */
|
||||
tmpreg |= WindowValue & (uint32_t) BIT_MASK;
|
||||
|
||||
/* Store the new value */
|
||||
WWDG->CFR = tmpreg;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables the WWDG Early Wakeup interrupt(EWI).
|
||||
* @note Once enabled this interrupt cannot be disabled except by a system reset.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void WWDG_EnableIT(void)
|
||||
{
|
||||
*(__IO uint32_t *) CFR_EWI_BB = (uint32_t)ENABLE;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Sets the WWDG counter value.
|
||||
* @param Counter: specifies the watchdog counter value.
|
||||
* This parameter must be a number between 0x40 and 0x7F (to prevent generating
|
||||
* an immediate reset).
|
||||
* @retval None
|
||||
*/
|
||||
void WWDG_SetCounter(uint8_t Counter)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_WWDG_COUNTER(Counter));
|
||||
/* Write to T[6:0] bits to configure the counter value, no need to do
|
||||
a read-modify-write; writing a 0 to WDGA bit does nothing */
|
||||
WWDG->CR = Counter & BIT_MASK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup WWDG_Group2 WWDG activation functions
|
||||
* @brief WWDG activation functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### WWDG activation function #####
|
||||
==============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enables WWDG and load the counter value.
|
||||
* @param Counter: specifies the watchdog counter value.
|
||||
* This parameter must be a number between 0x40 and 0x7F (to prevent generating
|
||||
* an immediate reset).
|
||||
* @retval None
|
||||
*/
|
||||
void WWDG_Enable(uint8_t Counter)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_WWDG_COUNTER(Counter));
|
||||
WWDG->CR = WWDG_CR_WDGA | Counter;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup WWDG_Group3 Interrupts and flags management functions
|
||||
* @brief Interrupts and flags management functions
|
||||
*
|
||||
@verbatim
|
||||
==============================================================================
|
||||
##### Interrupts and flags management functions #####
|
||||
==============================================================================
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Checks whether the Early Wakeup interrupt flag is set or not.
|
||||
* @param None
|
||||
* @retval The new state of the Early Wakeup interrupt flag (SET or RESET).
|
||||
*/
|
||||
FlagStatus WWDG_GetFlagStatus(void)
|
||||
{
|
||||
FlagStatus bitstatus = RESET;
|
||||
|
||||
if ((WWDG->SR) != (uint32_t)RESET)
|
||||
{
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = RESET;
|
||||
}
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clears Early Wakeup interrupt flag.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void WWDG_ClearFlag(void)
|
||||
{
|
||||
WWDG->SR = (uint32_t)RESET;
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,686 @@
|
|||
<html>
|
||||
<head>
|
||||
<style>
|
||||
<!--
|
||||
/* Style Definitions */
|
||||
p.MsoNormal, li.MsoNormal, div.MsoNormal
|
||||
{margin-top:0cm;margin-right:0cm;margin-bottom:8pt;margin-left:0cm;line-height:normal;font-size:10.0pt;font-family:Verdana,sans-serif;}
|
||||
p.MsoListParagraph, li.MsoListParagraph, div.MsoListParagraph
|
||||
{margin-top:0cm;margin-right:0cm;margin-bottom:2pt;margin-left:0cm;line-height:normal;font-size:10.0pt;font-family:Verdana,sans-serif;}
|
||||
-->
|
||||
</style>
|
||||
<title>
|
||||
STMTouch Driver Release Notes
|
||||
</title>
|
||||
</head>
|
||||
<body lang=EN-US>
|
||||
<p class=MsoNormal align=center style='text-align:center;line-height:normal'><b><span style='font-size:18.0pt;color: rgb(51, 102, 255)'>
|
||||
Release Notes for
|
||||
</span></b></p>
|
||||
<p class=MsoNormal align=center style='text-align:center;line-height:normal'><b><span style='font-size:18.0pt;color: rgb(51, 102, 255)'>
|
||||
STMTouch Driver
|
||||
</span></b></p>
|
||||
<p class=MsoNormal style='line-height:normal'><span style='font-size:10.0pt'> </span></p>
|
||||
<p class=MsoNormal align=center style='line-height:center;line-height:normal'><span style='font-size:10.0pt'>
|
||||
Copyright © 2013 STMicroelectronics
|
||||
</span></p>
|
||||
<p class=MsoNormal align=center style='line-height:center;line-height:normal'><span style='font-size:10.0pt'>
|
||||
Microcontrollers Division - Application Team
|
||||
</span></p>
|
||||
<p class=MsoNormal align=center> <img id=_rnc_img0 src=../../_htmresc/st_logo.png border=0> </span></p>
|
||||
<p class=MsoNormal align=center> <img id=_rnc_img1 src=../../_htmresc/stmtouch.bmp border=0> </span></p>
|
||||
<p class=MsoNormal style='line-height:normal'><span style='font-size:10.0pt'> </span></p>
|
||||
<table class=MsoNormal border=0 cellspacing=0 cellpadding=0 width=100%
|
||||
style='margin-left:4cm;margin-right:4cm;width:80%;background:rgb(51, 102, 255)'>
|
||||
<td style='padding:0cm 5.4pt 0cm 5.4pt'>
|
||||
<p class=MsoNormal style='margin-left:0cm;margin-bottom:0cm;line-height:normal'><b><span style='font-size:12.0pt;color:white'>
|
||||
Update History</span></b></p></td></tr></table>
|
||||
<p class=MsoNormal style='line-height:normal'><span style='font-size:10.0pt'> </span></p>
|
||||
<table class=MsoNormal border=0 cellspacing=0 cellpadding=0 width=100%
|
||||
style='margin-left:4cm;width:23%;background:rgb(51, 102, 255)'>
|
||||
<td align=left style='padding:0cm 5.4pt 0cm 5.4pt'>
|
||||
<p class=MsoNormal style='margin-bottom:0cm;line-height:normal'><b><span style='font-size:10.0pt;color:white'>
|
||||
V1.3.2 / 22-January-2013</span></b></p></td></tr></table>
|
||||
<p class=MsoNormal style='line-height:normal'><span style='font-size:10.0pt'> </span></p>
|
||||
<p class=MsoNormal style='margin-left:4cm;line-height:normal'><b><u><span style='font-size:10.0pt'>
|
||||
Main Changes
|
||||
</span></u></b></p>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Change in STM32L1xx acquisition:
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
GPIOs speed configured to "Very Low" (400 kHz).
|
||||
</span></p>
|
||||
<p class=MsoNormal style='line-height:normal'><span style='font-size:10.0pt'> </span></p>
|
||||
<p class=MsoNormal style='margin-left:4cm;line-height:normal'><b><u><span style='font-size:10.0pt'>
|
||||
Content
|
||||
</span></u></b></p>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Support of STM8TL5xx devices (OFFICIAL).
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Support of STM32F0xx devices (OFFICIAL).
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Support of STM32F3xx devices (ALPHA).
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Support of STM32L1xx High-density devices using hardware and software acquisition modes (OFFICIAL).
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Support of STM32L1xx Medium-density Plus devices using hardware and software acquisition modes (OFFICIAL).
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Support of STM32L1xx Medium-density devices using sofware acquisition mode (OFFICIAL).
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Support of proximity, touchkey and linear/rotary touch sensors.
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Debounce mechanism for all states.
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Environment Change System (ECS).
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Detection Exclusion System (DXS).
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Detection Time Out (DTO).
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Noise filtering capability on measurement and delta.
|
||||
</span></p>
|
||||
<p class=MsoNormal style='line-height:normal'><span style='font-size:10.0pt'> </span></p>
|
||||
<p class=MsoNormal style='margin-left:4cm;line-height:normal'><b><u><span style='font-size:10.0pt'>
|
||||
Development Toolchains and Compilers
|
||||
</span></u></b></p>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
STM8 devices:
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
ST Visual Develop (STVD).
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
IAR Embedded Workbench for STM8.
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Cosmic STM8 C Compiler.
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Raisonance Ride7/RKit-STM8.
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
STM32 devices:
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
IAR Embedded Workbench for ARM.
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Keil MDK-ARM.
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Altium Tasking.
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Atollic TrueSTUDIO.
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Raisonance Ride7/RKit-Arm.
|
||||
</span></p>
|
||||
<p class=MsoNormal style='line-height:normal'><span style='font-size:10.0pt'> </span></p>
|
||||
<p class=MsoNormal style='margin-left:4cm;line-height:normal'><b><u><span style='font-size:10.0pt'>
|
||||
Known Limitations
|
||||
</span></u></b></p>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
None.
|
||||
</span></p>
|
||||
<p class=MsoNormal style='line-height:normal'><span style='font-size:10.0pt'> </span></p>
|
||||
<table class=MsoNormal border=0 cellspacing=0 cellpadding=0 width=100%
|
||||
style='margin-left:4cm;width:23%;background:rgb(51, 102, 255)'>
|
||||
<td align=left style='padding:0cm 5.4pt 0cm 5.4pt'>
|
||||
<p class=MsoNormal style='margin-bottom:0cm;line-height:normal'><b><span style='font-size:10.0pt;color:white'>
|
||||
V1.3.1 / 15-January-2013</span></b></p></td></tr></table>
|
||||
<p class=MsoNormal style='line-height:normal'><span style='font-size:10.0pt'> </span></p>
|
||||
<p class=MsoNormal style='margin-left:4cm;line-height:normal'><b><u><span style='font-size:10.0pt'>
|
||||
Main Changes
|
||||
</span></u></b></p>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Improvement of STM32L1xx acquisition.
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Typo corrections.
|
||||
</span></p>
|
||||
<p class=MsoNormal style='line-height:normal'><span style='font-size:10.0pt'> </span></p>
|
||||
<p class=MsoNormal style='margin-left:4cm;line-height:normal'><b><u><span style='font-size:10.0pt'>
|
||||
Content
|
||||
</span></u></b></p>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Support of STM8TL5xx devices (OFFICIAL).
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Support of STM32F0xx devices (OFFICIAL).
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Support of STM32F3xx devices (ALPHA).
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Support of STM32L1xx High-density devices using hardware and software acquisition modes (OFFICIAL).
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Support of STM32L1xx Medium-density Plus devices using hardware and software acquisition modes (OFFICIAL).
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Support of STM32L1xx Medium-density devices using sofware acquisition mode (OFFICIAL).
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Support of proximity, touchkey and linear/rotary touch sensors.
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Debounce mechanism for all states.
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Environment Change System (ECS).
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Detection Exclusion System (DXS).
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Detection Time Out (DTO).
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Noise filtering capability on measurement and delta.
|
||||
</span></p>
|
||||
<p class=MsoNormal style='line-height:normal'><span style='font-size:10.0pt'> </span></p>
|
||||
<p class=MsoNormal style='margin-left:4cm;line-height:normal'><b><u><span style='font-size:10.0pt'>
|
||||
Development Toolchains and Compilers
|
||||
</span></u></b></p>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
STM8 devices:
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
ST Visual Develop (STVD).
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
IAR Embedded Workbench for STM8.
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Cosmic STM8 C Compiler.
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Raisonance Ride7/RKit-STM8.
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
STM32 devices:
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
IAR Embedded Workbench for ARM.
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Keil MDK-ARM.
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Altium Tasking.
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Atollic TrueSTUDIO.
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Raisonance Ride7/RKit-Arm.
|
||||
</span></p>
|
||||
<p class=MsoNormal style='line-height:normal'><span style='font-size:10.0pt'> </span></p>
|
||||
<p class=MsoNormal style='margin-left:4cm;line-height:normal'><b><u><span style='font-size:10.0pt'>
|
||||
Known Limitations
|
||||
</span></u></b></p>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
None.
|
||||
</span></p>
|
||||
<p class=MsoNormal style='line-height:normal'><span style='font-size:10.0pt'> </span></p>
|
||||
<table class=MsoNormal border=0 cellspacing=0 cellpadding=0 width=100%
|
||||
style='margin-left:4cm;width:23%;background:rgb(51, 102, 255)'>
|
||||
<td align=left style='padding:0cm 5.4pt 0cm 5.4pt'>
|
||||
<p class=MsoNormal style='margin-bottom:0cm;line-height:normal'><b><span style='font-size:10.0pt;color:white'>
|
||||
V1.3.0 / 10-December-2012</span></b></p></td></tr></table>
|
||||
<p class=MsoNormal style='line-height:normal'><span style='font-size:10.0pt'> </span></p>
|
||||
<p class=MsoNormal style='margin-left:4cm;line-height:normal'><b><u><span style='font-size:10.0pt'>
|
||||
Main Changes
|
||||
</span></u></b></p>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Add support of STM32F30x and STM32F37x devices.
|
||||
</span></p>
|
||||
<p class=MsoNormal style='line-height:normal'><span style='font-size:10.0pt'> </span></p>
|
||||
<p class=MsoNormal style='margin-left:4cm;line-height:normal'><b><u><span style='font-size:10.0pt'>
|
||||
Content
|
||||
</span></u></b></p>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Support of STM8TL5xx devices (OFFICIAL).
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Support of STM32F0xx devices (OFFICIAL).
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Support of STM32F3xx devices (ALPHA).
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Support of STM32L1xx High-density devices using hardware and software acquisition modes (BETA).
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Support of STM32L1xx Medium-density Plus devices using hardware and software acquisition modes (BETA).
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Support of STM32L1xx Medium-density devices using sofware acquisition mode (BETA).
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Support of proximity, touchkey and linear/rotary touch sensors.
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Debounce mechanism for all states.
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Environment Change System (ECS).
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Detection Exclusion System (DXS).
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Detection Time Out (DTO).
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Noise filtering capability on measurement and delta.
|
||||
</span></p>
|
||||
<p class=MsoNormal style='line-height:normal'><span style='font-size:10.0pt'> </span></p>
|
||||
<p class=MsoNormal style='margin-left:4cm;line-height:normal'><b><u><span style='font-size:10.0pt'>
|
||||
Development Toolchains and Compilers
|
||||
</span></u></b></p>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
STM8 devices:
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
ST Visual Develop (STVD).
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
IAR Embedded Workbench for STM8.
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Cosmic STM8 C Compiler.
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Raisonance Ride7/RKit-STM8.
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
STM32 devices:
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
IAR Embedded Workbench for ARM.
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Keil MDK-ARM.
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Altium Tasking.
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Atollic TrueSTUDIO.
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Raisonance Ride7/RKit-Arm.
|
||||
</span></p>
|
||||
<p class=MsoNormal style='line-height:normal'><span style='font-size:10.0pt'> </span></p>
|
||||
<p class=MsoNormal style='margin-left:4cm;line-height:normal'><b><u><span style='font-size:10.0pt'>
|
||||
Known Limitations
|
||||
</span></u></b></p>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
None.
|
||||
</span></p>
|
||||
<p class=MsoNormal style='line-height:normal'><span style='font-size:10.0pt'> </span></p>
|
||||
<table class=MsoNormal border=0 cellspacing=0 cellpadding=0 width=100%
|
||||
style='margin-left:4cm;width:23%;background:rgb(51, 102, 255)'>
|
||||
<td align=left style='padding:0cm 5.4pt 0cm 5.4pt'>
|
||||
<p class=MsoNormal style='margin-bottom:0cm;line-height:normal'><b><span style='font-size:10.0pt;color:white'>
|
||||
V1.2.0 / 30-November-2012</span></b></p></td></tr></table>
|
||||
<p class=MsoNormal style='line-height:normal'><span style='font-size:10.0pt'> </span></p>
|
||||
<p class=MsoNormal style='margin-left:4cm;line-height:normal'><b><u><span style='font-size:10.0pt'>
|
||||
Main Changes
|
||||
</span></u></b></p>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Common.
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Change LinRot sensors position offset tables names (Mono, Half-ended, Dual).
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Add more LinRot sensors position offset tables with conditional compilation.
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
STM8TL5x acquisition.
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Increase TSLPRM_KEY_TARGET_REFERENCE max value to 2000.
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
STM32F0xx acquisition.
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Improvement of capacitors discharge processing.
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Add automatic GPIO configuration.
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
STM32L1xx acquisition.
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Add support of Medium-density Plus devices.
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Rename files ("hw/sw" put after "stm32l1xx").
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Software acquisition is now done if TSLPRM_STM32L1XX_SW_ACQ is defined (was previously TSLPRM_STM32L1XX_HD_SW or TSLPRM_STM32L1XX_MDP_SW).
|
||||
</span></p>
|
||||
<p class=MsoNormal style='line-height:normal'><span style='font-size:10.0pt'> </span></p>
|
||||
<p class=MsoNormal style='margin-left:4cm;line-height:normal'><b><u><span style='font-size:10.0pt'>
|
||||
Content
|
||||
</span></u></b></p>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Support of STM8TL5xx devices (OFFICIAL).
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Support of STM32F0xx devices (BETA).
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Support of STM32L1xx High-density devices using hardware and software acquisition modes (BETA).
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Support of STM32L1xx Medium-density Plus devices using hardware and software acquisition modes (BETA).
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Support of STM32L1xx Medium-density devices using sofware acquisition mode (BETA).
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Support of proximity, touchkey and linear/rotary touch sensors (1, 3, 5 and 6 channels).
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Debounce mechanism for all states.
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Environment Change System (ECS).
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Detection Exclusion System (DXS).
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Detection Time Out (DTO).
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Noise filtering capability on measurement and delta.
|
||||
</span></p>
|
||||
<p class=MsoNormal style='line-height:normal'><span style='font-size:10.0pt'> </span></p>
|
||||
<p class=MsoNormal style='margin-left:4cm;line-height:normal'><b><u><span style='font-size:10.0pt'>
|
||||
Development Toolchains and Compilers
|
||||
</span></u></b></p>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
STM8 devices:
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
ST Visual Develop (STVD).
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
IAR Embedded Workbench for STM8.
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Cosmic STM8 C Compiler.
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Raisonance Ride7/RKit-STM8.
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
STM32 devices:
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
IAR Embedded Workbench for ARM.
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Keil MDK-ARM.
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Altium Tasking.
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Atollic TrueSTUDIO.
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Raisonance Ride7/RKit-Arm.
|
||||
</span></p>
|
||||
<p class=MsoNormal style='line-height:normal'><span style='font-size:10.0pt'> </span></p>
|
||||
<p class=MsoNormal style='margin-left:4cm;line-height:normal'><b><u><span style='font-size:10.0pt'>
|
||||
Known Limitations
|
||||
</span></u></b></p>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
None.
|
||||
</span></p>
|
||||
<p class=MsoNormal style='line-height:normal'><span style='font-size:10.0pt'> </span></p>
|
||||
<table class=MsoNormal border=0 cellspacing=0 cellpadding=0 width=100%
|
||||
style='margin-left:4cm;width:23%;background:rgb(51, 102, 255)'>
|
||||
<td align=left style='padding:0cm 5.4pt 0cm 5.4pt'>
|
||||
<p class=MsoNormal style='margin-bottom:0cm;line-height:normal'><b><span style='font-size:10.0pt;color:white'>
|
||||
V1.1.0 / 08-August-2012</span></b></p></td></tr></table>
|
||||
<p class=MsoNormal style='line-height:normal'><span style='font-size:10.0pt'> </span></p>
|
||||
<p class=MsoNormal style='margin-left:4cm;line-height:normal'><b><u><span style='font-size:10.0pt'>
|
||||
Main Changes
|
||||
</span></u></b></p>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Improvement of hardware acquisition mode of STM32L1xx High-density devices:
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Disable hysteresis on sampling capacitor IOs to reduce acquisition noise level.
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Use of the timer TSUSP mode.
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Add support of Medium-density devices.
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Add sofware acquisition mode on STM32L1xx High and Medium density devices.
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Add TSLPRM_LINROT_USE_NORMDELTA parameter.
|
||||
</span></p>
|
||||
<p class=MsoNormal style='line-height:normal'><span style='font-size:10.0pt'> </span></p>
|
||||
<p class=MsoNormal style='margin-left:4cm;line-height:normal'><b><u><span style='font-size:10.0pt'>
|
||||
Content
|
||||
</span></u></b></p>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Support of STM8TL5xx devices (OFFICIAL).
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Support of STM32F0xx devices (BETA).
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Support of STM32L1xx High-density devices using hardware and software acquisition modes (BETA).
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Support of STM32L1xx Medium-density devices using sofware acquisition mode (BETA).
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Support of proximity, touchkey and linear/rotary touch sensors (1, 3, 5 and 6 channels).
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Debounce mechanism for all states.
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Environment Change System (ECS).
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Detection Exclusion System (DXS).
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Detection Time Out (DTO).
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Noise filtering capability on measurement and delta.
|
||||
</span></p>
|
||||
<p class=MsoNormal style='line-height:normal'><span style='font-size:10.0pt'> </span></p>
|
||||
<p class=MsoNormal style='margin-left:4cm;line-height:normal'><b><u><span style='font-size:10.0pt'>
|
||||
Development Toolchains and Compilers
|
||||
</span></u></b></p>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
STM8 devices:
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
ST Visual Develop (STVD).
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
IAR Embedded Workbench for STM8.
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Cosmic STM8 C Compiler.
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Raisonance Ride7/RKit-STM8.
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
STM32 devices:
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
IAR Embedded Workbench for ARM.
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Keil MDK-ARM.
|
||||
</span></p>
|
||||
<p class=MsoNormal style='line-height:normal'><span style='font-size:10.0pt'> </span></p>
|
||||
<p class=MsoNormal style='margin-left:4cm;line-height:normal'><b><u><span style='font-size:10.0pt'>
|
||||
Known Limitations
|
||||
</span></u></b></p>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
None.
|
||||
</span></p>
|
||||
<p class=MsoNormal style='line-height:normal'><span style='font-size:10.0pt'> </span></p>
|
||||
<table class=MsoNormal border=0 cellspacing=0 cellpadding=0 width=100%
|
||||
style='margin-left:4cm;width:23%;background:rgb(51, 102, 255)'>
|
||||
<td align=left style='padding:0cm 5.4pt 0cm 5.4pt'>
|
||||
<p class=MsoNormal style='margin-bottom:0cm;line-height:normal'><b><span style='font-size:10.0pt;color:white'>
|
||||
V1.0.0 / 25-June-2012</span></b></p></td></tr></table>
|
||||
<p class=MsoNormal style='line-height:normal'><span style='font-size:10.0pt'> </span></p>
|
||||
<p class=MsoNormal style='margin-left:4cm;line-height:normal'><b><u><span style='font-size:10.0pt'>
|
||||
Main Changes
|
||||
</span></u></b></p>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
First official release.
|
||||
</span></p>
|
||||
<p class=MsoNormal style='line-height:normal'><span style='font-size:10.0pt'> </span></p>
|
||||
<p class=MsoNormal style='margin-left:4cm;line-height:normal'><b><u><span style='font-size:10.0pt'>
|
||||
Content
|
||||
</span></u></b></p>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Support of STM8TL5xx devices (OFFICIAL).
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Support of STM32F0xx devices (BETA).
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Support of STM32L1xx High-density devices using hardware acquisition mode (BETA).
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Support of proximity, touchkey and linear/rotary touch sensors (1, 3, 5 and 6 channels).
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Debounce mechanism for all states.
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Environment Change System (ECS).
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Detection Exclusion System (DXS).
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Detection Time Out (DTO).
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Noise filtering capability on measurement and delta.
|
||||
</span></p>
|
||||
<p class=MsoNormal style='line-height:normal'><span style='font-size:10.0pt'> </span></p>
|
||||
<p class=MsoNormal style='margin-left:4cm;line-height:normal'><b><u><span style='font-size:10.0pt'>
|
||||
Development Toolchains and Compilers
|
||||
</span></u></b></p>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
STM8 devices:
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
ST Visual Develop (STVD).
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
IAR Embedded Workbench for STM8.
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Cosmic STM8 C Compiler.
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Raisonance Ride7/RKit-STM8.
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
STM32 devices:
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
IAR Embedded Workbench for ARM.
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Keil MDK-ARM.
|
||||
</span></p>
|
||||
<p class=MsoNormal style='line-height:normal'><span style='font-size:10.0pt'> </span></p>
|
||||
<p class=MsoNormal style='margin-left:4cm;line-height:normal'><b><u><span style='font-size:10.0pt'>
|
||||
Known Limitations
|
||||
</span></u></b></p>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:10.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>•<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
Use of Linear/Rotary sensors with STM32L1xx High-density devices:
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
The hardware acquisition is too noisy to properly support Linear/Rotary sensors.
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
This noise induces an important jitter of the reported position.
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
As a workaround, the position resolution must be configured to 4 bits maximum.
|
||||
</span>
|
||||
<p class=MsoListParagraph style='margin-left:4cm;margin-right:4cm;text-indent:30.0pt;line-height:normal'><spanstyle='font-size:10.0pt;font-family:Symbol'>–<span style='font:7.0pt'> </span><span style='font-size:10.0pt'>
|
||||
The Touchkey sensors are not impacted by this issue.
|
||||
</span></p>
|
||||
<p class=MsoNormal style='line-height:normal'><span style='font-size:10.0pt'> </span></p>
|
||||
<table class=MsoNormal border=0 cellspacing=0 cellpadding=0 width=100%
|
||||
style='margin-left:4cm;margin-right:4cm;width:80%;background:rgb(51, 102, 255)'>
|
||||
<td style='padding:0cm 5.4pt 0cm 5.4pt'>
|
||||
<p class=MsoNormal style='margin-left:0cm;margin-bottom:0cm;line-height:normal'><b><span style='font-size:12.0pt;color:white'>
|
||||
License</span></b></p></td></tr></table>
|
||||
<p class=MsoNormal style='line-height:normal'><span style='font-size:10.0pt'> </span></p>
|
||||
<p class=MsoNormal style='margin-left:4cm;margin-right:4cm;line-height:normal'><span style='font-size:10.0pt;color:black'>Licensed under MCD-ST Liberty SW License Agreement V2, (the "License").
|
||||
You may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at:
|
||||
|
||||
|
||||
</span></p>
|
||||
<p class=MsoNormal style='text-align:center;line-height:normal'><span style='font-size:10.0pt'>
|
||||
<a href=http://www.st.com/software_license_agreement_liberty_v2> http://www.st.com/software_license_agreement_liberty_v2</a></span></p>
|
||||
<p class=MsoNormal style='margin-left:4cm;margin-right:4cm;line-height:normal'><span style='font-size:10.0pt;color:black'>Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
See the License for the specific language governing permissions and
|
||||
limitations under the License.
|
||||
</a></span></p>
|
||||
<p class=MsoNormal style='line-height:normal'><b><span style='font-size:10.0pt'> </span></b></p>
|
||||
<table class=MsoNormal border=0 cellspacing=0 cellpadding=0 width=100%
|
||||
style='margin-left:4cm;margin-right:4cm;width:80%;background:rgb(51, 102, 255)'>
|
||||
<td style='padding:0cm 5.4pt 0cm 5.4pt'>
|
||||
<p class=MsoNormal style='margin-left:0cm;margin-bottom:0cm;line-height:4pt'><b><span style='font-size:10.0pt;color:rgb(51, 102, 255)'>
|
||||
---</span></b></p></td></tr></table>
|
||||
<p class=MsoNormal style='line-height:normal'><b><span style='font-size:10.0pt'> </span></b></p>
|
||||
<p class=MsoNormal style='text-align:center;line-height:normal'><span style='font-size:10.0pt'>
|
||||
For complete documentation on <b>STMTouch</b> microcontrollers please visit <a href=http://www.st.com/stmtouch> http://www.st.com/stmtouch</a></span></p>
|
||||
<p class=MsoNormal style='line-height:normal'><b><span style='font-size:10.0pt'> </span></b></p>
|
||||
<p class=MsoNormal align=right style='margin-right:1cm;line-height:normal'><span style='font-size:8.0pt'>Generated by RNcreator v2.3
|
||||
</span></p>
|
||||
<!-- Generated by RNcreator v2.3 on 22-Jan-13 12:40:56 -->
|
||||
</div>
|
||||
</body>
|
||||
</html>
|
||||
|
|
@ -0,0 +1,607 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file tsl_conf_stm32f0xx.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.3.2
|
||||
* @date 22-January-2013
|
||||
* @brief Acquisition parameters for STM32F0xx products.
|
||||
* @note This file must be copied in the application project and values
|
||||
* changed for the application.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __TSL_CONF_STM32F0XX_H
|
||||
#define __TSL_CONF_STM32F0XX_H
|
||||
|
||||
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
//+++++++++++++++++++++++++++ COMMON PARAMETERS ++++++++++++++++++++++++++++++++
|
||||
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
|
||||
/** @defgroup Common_Parameters Common Parameters
|
||||
* @{ */
|
||||
|
||||
//==============================================================================
|
||||
// Number of elements
|
||||
//==============================================================================
|
||||
|
||||
/** @defgroup Common_Parameters_Number_Of_Elements 01 - Number of elements
|
||||
* @{ */
|
||||
|
||||
/** Total number of channels in application (range=1..255)
|
||||
*/
|
||||
#define TSLPRM_TOTAL_CHANNELS (1)
|
||||
|
||||
/** Total number of banks in application (range=1..255)
|
||||
*/
|
||||
#define TSLPRM_TOTAL_BANKS (1)
|
||||
|
||||
/** Total number of "Extended" TouchKeys in application (range=0..255)
|
||||
*/
|
||||
#define TSLPRM_TOTAL_TOUCHKEYS (1)
|
||||
|
||||
/** Total number of "Basic" TouchKeys in application (range=0..255)
|
||||
*/
|
||||
#define TSLPRM_TOTAL_TOUCHKEYS_B (1)
|
||||
|
||||
/** Total number of "Extended" Linear and Rotary sensors in application (range=0..255)
|
||||
- Count also the 1-channel linear sensor used as TouchKey
|
||||
*/
|
||||
#define TSLPRM_TOTAL_LINROTS (1)
|
||||
|
||||
/** Total number of "Basic" Linear and Rotary sensors in application (range=0..255)
|
||||
- Count also the 1-channel linear sensor used as TouchKey
|
||||
*/
|
||||
#define TSLPRM_TOTAL_LINROTS_B (1)
|
||||
|
||||
/** Total number of sensors/objects in application (range=1..255)
|
||||
- Count all TouchKeys, Linear and Rotary sensors
|
||||
*/
|
||||
#define TSLPRM_TOTAL_OBJECTS (1)
|
||||
|
||||
/** @} Common_Parameters_Number_Of_Elements */
|
||||
|
||||
//==============================================================================
|
||||
// Optional features
|
||||
//==============================================================================
|
||||
|
||||
/** @defgroup Common_Parameters_Options 02 - Optional features
|
||||
* @{ */
|
||||
|
||||
/** Record the last measure (0=No, 1=Yes)
|
||||
- If No the measure is recalculated using the Reference and Delta
|
||||
*/
|
||||
#define TSLPRM_USE_MEAS (1)
|
||||
|
||||
/** Zone management usage (0=No, 1=Yes)
|
||||
*/
|
||||
#define TSLPRM_USE_ZONE (1)
|
||||
|
||||
/** Proximity detection usage (0=No, 1=Yes)
|
||||
*/
|
||||
#define TSLPRM_USE_PROX (1)
|
||||
|
||||
/** Use the Timer tick callback (0=No, 1=Yes)
|
||||
- When equal to 1, the function TSL_CallBack_TimerTick must be defined in
|
||||
the application code. It is called for each timer interruption.
|
||||
*/
|
||||
#define TSLPRM_USE_TIMER_CALLBACK (1)
|
||||
|
||||
/** Acquisition interrupt mode (0=No, 1=Yes)
|
||||
- If No the TS interrupt is not used.
|
||||
- If Yes the TS interrupt is used.
|
||||
*/
|
||||
#define TSLPRM_USE_ACQ_INTERRUPT (1)
|
||||
|
||||
/** @} Common_Parameters_Options */
|
||||
|
||||
//==============================================================================
|
||||
// Acquisition limits
|
||||
//==============================================================================
|
||||
|
||||
/** @defgroup Common_Parameters_Acquisition_Limits 03 - Acquisition limits
|
||||
* @{ */
|
||||
|
||||
/** Minimum acquisition measurement (range=0..65535)
|
||||
- This is the minimum acceptable value for the acquisition measure.
|
||||
- The acquisition will be in error if the measure is below this value.
|
||||
*/
|
||||
#define TSLPRM_ACQ_MIN (10)
|
||||
|
||||
/** Maximum acquisition measurement (range=255, 511, 1023, 2047, 8191, 16383)
|
||||
- This is the maximum acceptable value for the acquisition measure.
|
||||
- The acquisition will be in error if the measure is above this value.
|
||||
*/
|
||||
#define TSLPRM_ACQ_MAX (8191)
|
||||
|
||||
/** @} Common_Parameters_Acquisition_Limits */
|
||||
|
||||
//==============================================================================
|
||||
// Calibration
|
||||
//==============================================================================
|
||||
|
||||
/** @defgroup Common_Parameters_Calibration 04 - Calibration
|
||||
* @{ */
|
||||
|
||||
/** Number of calibration samples (range=4, 8, 16)
|
||||
- Low value = faster calibration but less precision.
|
||||
- High value = slower calibration but more precision.
|
||||
*/
|
||||
#define TSLPRM_CALIB_SAMPLES (8)
|
||||
|
||||
/** Delay in measurement samples before starting the calibration (range=0..40)
|
||||
- This is usefull if a noise filter is used.
|
||||
- Write 0 to disable the delay.
|
||||
*/
|
||||
#define TSLPRM_CALIB_DELAY (10)
|
||||
|
||||
/** @} Common_Parameters_Calibration */
|
||||
|
||||
//==============================================================================
|
||||
// Thresholds for TouchKey sensors
|
||||
//==============================================================================
|
||||
|
||||
/** @defgroup Common_Parameters_TouchKey_Thresholds 05 - Thresholds for TouchKey sensors
|
||||
* @{ */
|
||||
|
||||
/** TouchKeys Proximity state input threshold (range=0..255)
|
||||
- Enter Proximity state if delta is above
|
||||
*/
|
||||
#define TSLPRM_TKEY_PROX_IN_TH (10)
|
||||
|
||||
/** TouchKeys Proximity state output threshold (range=0..255)
|
||||
- Exit Proximity state if delta is below
|
||||
*/
|
||||
#define TSLPRM_TKEY_PROX_OUT_TH (5)
|
||||
|
||||
/** TouchKeys Detect state input threshold (range=0..255)
|
||||
- Enter Detect state if delta is above
|
||||
*/
|
||||
#define TSLPRM_TKEY_DETECT_IN_TH (20)
|
||||
|
||||
/** TouchKeys Detect state output threshold (range=0..255)
|
||||
- Exit Detect state if delta is below
|
||||
*/
|
||||
#define TSLPRM_TKEY_DETECT_OUT_TH (15)
|
||||
|
||||
/** TouchKeys re-Calibration threshold (range=0..255)
|
||||
- @warning The value is inverted in the sensor state machine
|
||||
- Enter Calibration state if delta is below
|
||||
*/
|
||||
#define TSLPRM_TKEY_CALIB_TH (20)
|
||||
|
||||
/** TouchKey, Linear and Rotary sensors thresholds coefficient (range=0..4)
|
||||
This multiplier coefficient is applied on Detect thresholds only.
|
||||
- 0: feature disabled
|
||||
- 1: thresholds x 2
|
||||
- 2: thresholds x 4
|
||||
- 3: thresholds x 8
|
||||
- 4: thresholds x 16
|
||||
*/
|
||||
#define TSLPRM_COEFF_TH (1)
|
||||
|
||||
/** @} Common_Parameters_TouchKey_Thresholds */
|
||||
|
||||
//==============================================================================
|
||||
// Thresholds for Linear and Rotary sensors
|
||||
//==============================================================================
|
||||
|
||||
/** @defgroup Common_Parameters_LinRot_Thresholds 06 - Thresholds for Linear and Rotary sensors
|
||||
* @{ */
|
||||
|
||||
/** Linear/Rotary Proximity state input threshold (range=0..255)
|
||||
- Enter Proximity state if delta is above
|
||||
*/
|
||||
#define TSLPRM_LINROT_PROX_IN_TH (10)
|
||||
|
||||
/** Linear/Rotary Proximity state output threshold (range=0..255)
|
||||
- Exit Proximity state if delta is below
|
||||
*/
|
||||
#define TSLPRM_LINROT_PROX_OUT_TH (5)
|
||||
|
||||
/** Linear/Rotary Detect state input threshold (range=0..255)
|
||||
- Enter Detect state if delta is above
|
||||
*/
|
||||
#define TSLPRM_LINROT_DETECT_IN_TH (20)
|
||||
|
||||
/** Linear/Rotary Detect state output threshold (range=0..255)
|
||||
- Exit Detect state if delta is below
|
||||
*/
|
||||
#define TSLPRM_LINROT_DETECT_OUT_TH (15)
|
||||
|
||||
/** Linear/Rotary re-Calibration threshold (range=0..255)
|
||||
- @warning The value is inverted in the sensor state machine
|
||||
- Enter Calibration state if delta is below
|
||||
- A low absolute value will result in a higher sensitivity and thus some spurious
|
||||
recalibration may be issued.
|
||||
*/
|
||||
#define TSLPRM_LINROT_CALIB_TH (20)
|
||||
|
||||
/** Linear/Rotary Delta normalization (0=No, 1=Yes)
|
||||
- When this parameter is set, a coefficient is applied on all Delta of all sensors
|
||||
in order to normalize them and to improve the position calculation.
|
||||
- These coefficients must be defined in a constant table in the application (see Library examples).
|
||||
- The MSB is the coefficient integer part, the LSB is the coefficient real part.
|
||||
- Examples:
|
||||
- To apply a factor 1.10:
|
||||
0x01 to the MSB
|
||||
0x1A to the LSB (0.10 x 256 = 25.6 -> rounded to 26 = 0x1A)
|
||||
- To apply a factor 0.90:
|
||||
0x00 to the MSB
|
||||
0xE6 to the LSB (0.90 x 256 = 230.4 -> rounded to 230 = 0xE6)
|
||||
- To apply no factor:
|
||||
0x01 to the MSB
|
||||
0x00 to the LSB
|
||||
*/
|
||||
#define TSLPRM_LINROT_USE_NORMDELTA (1)
|
||||
|
||||
/** @} Common_Parameters_LinRot_Thresholds */
|
||||
|
||||
//==============================================================================
|
||||
// Linear/Rotary sensors used
|
||||
//==============================================================================
|
||||
|
||||
/** @defgroup Common_Parameters_LinRot_Used 07 - Linear/Rotary sensors used
|
||||
* @{ */
|
||||
|
||||
/** Select which Linear and Rotary sensors you use in your application.
|
||||
- 0 = Not Used
|
||||
- 1 = Used
|
||||
|
||||
LIN = Linear sensor
|
||||
ROT = Rotary sensor
|
||||
M1 = Mono electrodes design with 0/255 position at extremities of the sensor
|
||||
M2 = Mono electrodes design
|
||||
H = Half-ended electrodes design
|
||||
D = Dual electrodes design
|
||||
*/
|
||||
#define TSLPRM_USE_3CH_LIN_M1 (1)
|
||||
#define TSLPRM_USE_3CH_LIN_M2 (1)
|
||||
#define TSLPRM_USE_3CH_LIN_H (1)
|
||||
#define TSLPRM_USE_3CH_ROT_M (1)
|
||||
|
||||
#define TSLPRM_USE_4CH_LIN_M1 (1)
|
||||
#define TSLPRM_USE_4CH_LIN_M2 (1)
|
||||
#define TSLPRM_USE_4CH_LIN_H (1)
|
||||
#define TSLPRM_USE_4CH_ROT_M (1)
|
||||
|
||||
#define TSLPRM_USE_5CH_LIN_M1 (1)
|
||||
#define TSLPRM_USE_5CH_LIN_M2 (1)
|
||||
#define TSLPRM_USE_5CH_LIN_H (1)
|
||||
#define TSLPRM_USE_5CH_ROT_M (1)
|
||||
#define TSLPRM_USE_5CH_ROT_D (1)
|
||||
|
||||
#define TSLPRM_USE_6CH_LIN_M1 (1)
|
||||
#define TSLPRM_USE_6CH_LIN_M2 (1)
|
||||
#define TSLPRM_USE_6CH_LIN_H (1)
|
||||
#define TSLPRM_USE_6CH_ROT_M (1)
|
||||
|
||||
/** @} Common_Parameters_LinRot_used */
|
||||
|
||||
//==============================================================================
|
||||
// Linear/Rotary sensors position
|
||||
//==============================================================================
|
||||
|
||||
/** @defgroup Common_Parameters_LinRot_Position 08 - Linear/Rotary sensors position
|
||||
* @{ */
|
||||
|
||||
/** Position resolution in number of bits (range=1..8)
|
||||
- A Low value will result in a low resolution and will be less subject to noise.
|
||||
- A High value will result in a high resolution and will be more subject to noise.
|
||||
*/
|
||||
#define TSLPRM_LINROT_RESOLUTION (7)
|
||||
|
||||
/** Direction change threshold in position unit (range=0..255)
|
||||
- Defines the default threshold used during the change direction process.
|
||||
- A Low value will result in a faster direction change.
|
||||
- A High value will result in a slower direction change.
|
||||
*/
|
||||
#define TSLPRM_LINROT_DIR_CHG_POS (10)
|
||||
|
||||
/** Direction change debounce (range=0..63)
|
||||
- Defines the default integrator counter used during the change direction process.
|
||||
- This counter is decremented when the same change in the position is detected and the direction will
|
||||
change after this counter reaches zero.
|
||||
- A Low value will result in a faster direction change.
|
||||
- A High value will result in a slower direction change.
|
||||
*/
|
||||
#define TSLPRM_LINROT_DIR_CHG_DEB (1)
|
||||
|
||||
/** @} Common_Parameters_LinRot_Position */
|
||||
|
||||
//==============================================================================
|
||||
// Debounce counters
|
||||
//==============================================================================
|
||||
|
||||
/** @defgroup Common_Parameters_Debounce 09 - Debounce counters
|
||||
* @{ */
|
||||
|
||||
/** Proximity state debounce in samples unit (range=0..63)
|
||||
- A Low value will result in a higher sensitivity during the Proximity detection but with less noise filtering.
|
||||
- A High value will result in improving the system noise immunity but will increase the system response time.
|
||||
*/
|
||||
#define TSLPRM_DEBOUNCE_PROX (3)
|
||||
|
||||
/** Detect state debounce in samples unit (range=0..63)
|
||||
- A Low value will result in a higher sensitivity during the detection but with less noise filtering.
|
||||
- A High value will result in improving the system noise immunity but will increase the system response time.
|
||||
*/
|
||||
#define TSLPRM_DEBOUNCE_DETECT (3)
|
||||
|
||||
/** Release state debounce in samples unit (range=0..63)
|
||||
- A Low value will result in a higher sensitivity during the end-detection but with less noise filtering.
|
||||
- A High value will result in a lower sensitivity during the end-detection but with more noise filtering.
|
||||
*/
|
||||
#define TSLPRM_DEBOUNCE_RELEASE (3)
|
||||
|
||||
/** Re-calibration state debounce in samples unit (range=0..63)
|
||||
- A Low value will result in a higher sensitivity during the recalibration but with less noise filtering.
|
||||
- A High value will result in a lower sensitivity during the recalibration but with more noise filtering.
|
||||
*/
|
||||
#define TSLPRM_DEBOUNCE_CALIB (3)
|
||||
|
||||
/** Error state debounce in samples unit (range=0..63)
|
||||
- A Low value will result in a higher sensitivity to enter in error state.
|
||||
- A High value will result in a lower sensitivity to enter in error state.
|
||||
*/
|
||||
#define TSLPRM_DEBOUNCE_ERROR (3)
|
||||
|
||||
/** @} Common_Parameters_Debounce */
|
||||
|
||||
//==============================================================================
|
||||
// Environment Change System (ECS)
|
||||
//==============================================================================
|
||||
|
||||
/** @defgroup Common_Parameters_ECS 10 - ECS
|
||||
* @{ */
|
||||
|
||||
/** Environment Change System Slow K factor (range=0..255)
|
||||
- The higher value is K, the faster is the response time.
|
||||
*/
|
||||
#define TSLPRM_ECS_K_SLOW (10)
|
||||
|
||||
/** Environment Change System Fast K factor (range=0..255)
|
||||
- The higher value is K, the faster is the response time.
|
||||
*/
|
||||
#define TSLPRM_ECS_K_FAST (20)
|
||||
|
||||
/** Environment Change System delay in msec (range=0..5000)
|
||||
- The ECS will be started after this delay and when all sensors are in Release state.
|
||||
*/
|
||||
#define TSLPRM_ECS_DELAY (500)
|
||||
|
||||
/** @} Common_Parameters_ECS */
|
||||
|
||||
//==============================================================================
|
||||
// Detection Time Out (DTO)
|
||||
//==============================================================================
|
||||
|
||||
/** @defgroup Common_Parameters_DTO 11 - DTO
|
||||
* @{ */
|
||||
|
||||
/** Detection Time Out delay in seconds (range=0..63)
|
||||
- Value 0: DTO processing not compiled in the code (to gain size if not used).
|
||||
- Value 1: Default time out infinite.
|
||||
- Value between 2 and 63: Default time out between value n-1 and n.
|
||||
- Examples:
|
||||
- With a DTO equal to 2, the time out is between 1s and 2s.
|
||||
- With a DTO equal to 63, the time out is between 62s and 63s.
|
||||
|
||||
@note The DTO can be changed in run-time by the application only if the
|
||||
default value is between 1 and 63.
|
||||
*/
|
||||
#define TSLPRM_DTO (5)
|
||||
|
||||
/** @} Common_Parameters_DTO */
|
||||
|
||||
//==============================================================================
|
||||
// Detection Exclusion System (DXS)
|
||||
//==============================================================================
|
||||
|
||||
/** @defgroup Common_Parameters_DXS 12 - DXS
|
||||
* @{ */
|
||||
|
||||
/** Detection Exclusion System (0=No, 1=Yes)
|
||||
*/
|
||||
#define TSLPRM_USE_DXS (1)
|
||||
|
||||
/** @} Common_Parameters_DXS */
|
||||
|
||||
//==============================================================================
|
||||
// Miscellaneous parameters
|
||||
//==============================================================================
|
||||
|
||||
/** @defgroup Common_Parameters_Misc 13 - Miscellaneous
|
||||
* @{ */
|
||||
|
||||
/** Timing tick frequency in Hz (range=125, 250, 500, 1000, 2000)
|
||||
- Result to a timing interrupt respectively every 8ms, 4ms, 2ms, 1ms, 0.5ms
|
||||
*/
|
||||
#define TSLPRM_TICK_FREQ (1000)
|
||||
|
||||
/** @} Common_Parameters_Misc */
|
||||
|
||||
/** @} Common_Parameters */
|
||||
|
||||
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
//++++++++++++++++++++++++++++++ MCU PARAMETERS ++++++++++++++++++++++++++++++++
|
||||
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
|
||||
/** @defgroup STM32F0xx_Parameters STM32F0xx Parameters
|
||||
* @{ */
|
||||
|
||||
//==============================================================================
|
||||
// GPIO configuration
|
||||
//==============================================================================
|
||||
|
||||
/** @defgroup STM32F0xx_Parameters_GPIO_Config 01 - TSC GPIOs Configuration
|
||||
* @{ */
|
||||
|
||||
/** TSC GPIOs Configuration selection (range=0..1)
|
||||
- 0: Manual. The TSC GPIOs configuration must be done by the application code.
|
||||
- 1: Automatic. The TSLPRM_TSC_GROUPx_IOy parameters below must be filled up.
|
||||
The TSC GPIOs configuration is automatically done by the STMTouch driver.
|
||||
*/
|
||||
#define TSLPRM_TSC_GPIO_CONFIG (1)
|
||||
|
||||
//+++ DO NOT CHANGE THESE VALUES +++++++++++++++++++++++++++++++++
|
||||
// These defines must be applied to the TSLPRM_TSC_GROUPx_IOy parameters below.
|
||||
#define NU (0) // Not Used IO
|
||||
#define CHANNEL (1) // Channel IO
|
||||
#define SHIELD (2) // Shield IO (= Channel IO but not acquired)
|
||||
#define SAMPCAP (3) // Sampling Capacitor IO
|
||||
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
|
||||
// If TSLPRM_TSC_GPIO_CONFIG=1 assign each TSLPRM_TSC_GROUPx_IOy parameters below.
|
||||
// If TSLPRM_TSC_GPIO_CONFIG=0 these parameters are ignored.
|
||||
|
||||
#define TSLPRM_TSC_GROUP1_IO1 NU // PA0
|
||||
#define TSLPRM_TSC_GROUP1_IO2 NU // PA1
|
||||
#define TSLPRM_TSC_GROUP1_IO3 NU // PA2
|
||||
#define TSLPRM_TSC_GROUP1_IO4 NU // PA3
|
||||
|
||||
#define TSLPRM_TSC_GROUP2_IO1 NU // PA4
|
||||
#define TSLPRM_TSC_GROUP2_IO2 NU // PA5
|
||||
#define TSLPRM_TSC_GROUP2_IO3 NU // PA6
|
||||
#define TSLPRM_TSC_GROUP2_IO4 NU // PA7
|
||||
|
||||
#define TSLPRM_TSC_GROUP3_IO1 NU // PC5
|
||||
#define TSLPRM_TSC_GROUP3_IO2 NU // PB0
|
||||
#define TSLPRM_TSC_GROUP3_IO3 NU // PB1
|
||||
#define TSLPRM_TSC_GROUP3_IO4 NU // PB2
|
||||
|
||||
#define TSLPRM_TSC_GROUP4_IO1 NU // PA9
|
||||
#define TSLPRM_TSC_GROUP4_IO2 NU // PA10
|
||||
#define TSLPRM_TSC_GROUP4_IO3 NU // PA11
|
||||
#define TSLPRM_TSC_GROUP4_IO4 NU // PA12
|
||||
|
||||
#define TSLPRM_TSC_GROUP5_IO1 NU // PB3
|
||||
#define TSLPRM_TSC_GROUP5_IO2 NU // PB4
|
||||
#define TSLPRM_TSC_GROUP5_IO3 NU // PB6
|
||||
#define TSLPRM_TSC_GROUP5_IO4 NU // PB7
|
||||
|
||||
#define TSLPRM_TSC_GROUP6_IO1 NU // PB11
|
||||
#define TSLPRM_TSC_GROUP6_IO2 NU // PB12
|
||||
#define TSLPRM_TSC_GROUP6_IO3 NU // PB13
|
||||
#define TSLPRM_TSC_GROUP6_IO4 NU // PB14
|
||||
|
||||
/** @} STM32F0xx_Parameters_GPIO_Config */
|
||||
|
||||
//==============================================================================
|
||||
// Charge Transfer Pulses
|
||||
//==============================================================================
|
||||
|
||||
/** @defgroup STM32F0xx_Parameters_CT_Pulses 02 - Charge Transfer Pulses
|
||||
* @{ */
|
||||
|
||||
/** Charge Transfer Pulse High (range=0..15)
|
||||
- 0: 1 x tPGCLK
|
||||
- 1: 2 x tPGCLK
|
||||
- ...
|
||||
- 15: 16 x tPGCLK
|
||||
*/
|
||||
#define TSLPRM_TSC_CTPH (1)
|
||||
|
||||
/** Charge Transfer Pulse Low (range=0..15)
|
||||
- 0: 1 x tPGCLK
|
||||
- 1: 2 x tPGCLK
|
||||
- ...
|
||||
- 15: 16 x tPGCLK
|
||||
*/
|
||||
#define TSLPRM_TSC_CTPL (1)
|
||||
|
||||
/** Pulse Generator Prescaler (range=0..7)
|
||||
- 0: fPGCLK = fHCLK
|
||||
- 1: fPGCLK = fHCLK/2
|
||||
- ...
|
||||
- 7: fPGCLK = fHCLK/128
|
||||
*/
|
||||
#define TSLPRM_TSC_PGPSC (5)
|
||||
|
||||
/** @} STM32F0xx_Parameters_CT_Pulses */
|
||||
|
||||
//==============================================================================
|
||||
// IOs
|
||||
//==============================================================================
|
||||
|
||||
/** @defgroup STM32F0xx_Parameters_IOs 03 - I/Os
|
||||
* @{ */
|
||||
|
||||
/** TSC IOs default mode when no on-going acquisition (range=0..1)
|
||||
- 0: Output push-pull low
|
||||
- 1: Input floating
|
||||
*/
|
||||
#define TSLPRM_TSC_IODEF (0)
|
||||
|
||||
/** Acquisition Mode (range=0..1)
|
||||
- 0: Normal acquisition mode
|
||||
- 1: Synchronized acquisition mode
|
||||
*/
|
||||
#define TSLPRM_TSC_AM (0)
|
||||
|
||||
/** Synchronization Pin (range=0..1)
|
||||
- 0: PB08
|
||||
- 1: PB10
|
||||
*/
|
||||
#define TSLPRM_TSC_SYNC_PIN (0)
|
||||
|
||||
/** Synchronization Polarity (range=0..1)
|
||||
- 0: Falling edge only
|
||||
- 1: Rising edge and high level
|
||||
*/
|
||||
#define TSLPRM_TSC_SYNC_POL (0)
|
||||
|
||||
/** @} STM32F0xx_Parameters_Misc */
|
||||
|
||||
//==============================================================================
|
||||
// Spread Spectrum
|
||||
//==============================================================================
|
||||
|
||||
/** @defgroup STM32F0xx_Parameters_SpreadSpectrum 04 - Spread Spectrum
|
||||
* @{ */
|
||||
|
||||
/** Use Spread Spectrum (0=No, 1=Yes)
|
||||
*/
|
||||
#define TSLPRM_TSC_USE_SS (0)
|
||||
|
||||
/** Spread Spectrum Deviation (range=0..127)
|
||||
- 0: 1 x tSSCLK
|
||||
- 1: 2 x tSSCLK
|
||||
- ...
|
||||
- 127: 128 x tSSCLK
|
||||
*/
|
||||
#define TSLPRM_TSC_SSD (0)
|
||||
|
||||
/** Spread Spectrum Prescaler (range=0..1)
|
||||
- 0: fSSCLK = fHCLK
|
||||
- 1: fSSCLK = fHCLK/2
|
||||
*/
|
||||
#define TSLPRM_TSC_SSPSC (0)
|
||||
|
||||
/** @} STM32F0xx_Parameters_SpreadSpectrum */
|
||||
|
||||
/** @} STM32F0xx_Parameters */
|
||||
|
||||
// DO NOT REMOVE !!!
|
||||
#include "tsl_check_config.h"
|
||||
|
||||
#endif /* __TSL_CONF_STM32F0XX_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,617 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file tsl_conf_stm32f3xx.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.3.2
|
||||
* @date 22-January-2013
|
||||
* @brief Acquisition parameters for STM32F3xx products.
|
||||
* @note This file must be copied in the application project and values
|
||||
* changed for the application.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __TSL_CONF_STM32F3XX_H
|
||||
#define __TSL_CONF_STM32F3XX_H
|
||||
|
||||
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
//+++++++++++++++++++++++++++ COMMON PARAMETERS ++++++++++++++++++++++++++++++++
|
||||
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
|
||||
/** @defgroup Common_Parameters Common Parameters
|
||||
* @{ */
|
||||
|
||||
//==============================================================================
|
||||
// Number of elements
|
||||
//==============================================================================
|
||||
|
||||
/** @defgroup Common_Parameters_Number_Of_Elements 01 - Number of elements
|
||||
* @{ */
|
||||
|
||||
/** Total number of channels in application (range=1..255)
|
||||
*/
|
||||
#define TSLPRM_TOTAL_CHANNELS (1)
|
||||
|
||||
/** Total number of banks in application (range=1..255)
|
||||
*/
|
||||
#define TSLPRM_TOTAL_BANKS (1)
|
||||
|
||||
/** Total number of "Extended" TouchKeys in application (range=0..255)
|
||||
*/
|
||||
#define TSLPRM_TOTAL_TOUCHKEYS (1)
|
||||
|
||||
/** Total number of "Basic" TouchKeys in application (range=0..255)
|
||||
*/
|
||||
#define TSLPRM_TOTAL_TOUCHKEYS_B (1)
|
||||
|
||||
/** Total number of "Extended" Linear and Rotary sensors in application (range=0..255)
|
||||
- Count also the 1-channel linear sensor used as TouchKey
|
||||
*/
|
||||
#define TSLPRM_TOTAL_LINROTS (1)
|
||||
|
||||
/** Total number of "Basic" Linear and Rotary sensors in application (range=0..255)
|
||||
- Count also the 1-channel linear sensor used as TouchKey
|
||||
*/
|
||||
#define TSLPRM_TOTAL_LINROTS_B (1)
|
||||
|
||||
/** Total number of sensors/objects in application (range=1..255)
|
||||
- Count all TouchKeys, Linear and Rotary sensors
|
||||
*/
|
||||
#define TSLPRM_TOTAL_OBJECTS (1)
|
||||
|
||||
/** @} Common_Parameters_Number_Of_Elements */
|
||||
|
||||
//==============================================================================
|
||||
// Optional features
|
||||
//==============================================================================
|
||||
|
||||
/** @defgroup Common_Parameters_Options 02 - Optional features
|
||||
* @{ */
|
||||
|
||||
/** Record the last measure (0=No, 1=Yes)
|
||||
- If No the measure is recalculated using the Reference and Delta
|
||||
*/
|
||||
#define TSLPRM_USE_MEAS (1)
|
||||
|
||||
/** Zone management usage (0=No, 1=Yes)
|
||||
*/
|
||||
#define TSLPRM_USE_ZONE (1)
|
||||
|
||||
/** Proximity detection usage (0=No, 1=Yes)
|
||||
*/
|
||||
#define TSLPRM_USE_PROX (1)
|
||||
|
||||
/** Use the Timer tick callback (0=No, 1=Yes)
|
||||
- When equal to 1, the function TSL_CallBack_TimerTick must be defined in
|
||||
the application code. It is called for each timer interruption.
|
||||
*/
|
||||
#define TSLPRM_USE_TIMER_CALLBACK (1)
|
||||
|
||||
/** Acquisition interrupt mode (0=No, 1=Yes)
|
||||
- If No the TS interrupt is not used.
|
||||
- If Yes the TS interrupt is used.
|
||||
*/
|
||||
#define TSLPRM_USE_ACQ_INTERRUPT (1)
|
||||
|
||||
/** @} Common_Parameters_Options */
|
||||
|
||||
//==============================================================================
|
||||
// Acquisition limits
|
||||
//==============================================================================
|
||||
|
||||
/** @defgroup Common_Parameters_Acquisition_Limits 03 - Acquisition limits
|
||||
* @{ */
|
||||
|
||||
/** Minimum acquisition measurement (range=0..65535)
|
||||
- This is the minimum acceptable value for the acquisition measure.
|
||||
- The acquisition will be in error if the measure is below this value.
|
||||
*/
|
||||
#define TSLPRM_ACQ_MIN (10)
|
||||
|
||||
/** Maximum acquisition measurement (range=255, 511, 1023, 2047, 8191, 16383)
|
||||
- This is the maximum acceptable value for the acquisition measure.
|
||||
- The acquisition will be in error if the measure is above this value.
|
||||
*/
|
||||
#define TSLPRM_ACQ_MAX (8191)
|
||||
|
||||
/** @} Common_Parameters_Acquisition_Limits */
|
||||
|
||||
//==============================================================================
|
||||
// Calibration
|
||||
//==============================================================================
|
||||
|
||||
/** @defgroup Common_Parameters_Calibration 04 - Calibration
|
||||
* @{ */
|
||||
|
||||
/** Number of calibration samples (range=4, 8, 16)
|
||||
- Low value = faster calibration but less precision.
|
||||
- High value = slower calibration but more precision.
|
||||
*/
|
||||
#define TSLPRM_CALIB_SAMPLES (8)
|
||||
|
||||
/** Delay in measurement samples before starting the calibration (range=0..40)
|
||||
- This is usefull if a noise filter is used.
|
||||
- Write 0 to disable the delay.
|
||||
*/
|
||||
#define TSLPRM_CALIB_DELAY (10)
|
||||
|
||||
/** @} Common_Parameters_Calibration */
|
||||
|
||||
//==============================================================================
|
||||
// Thresholds for TouchKey sensors
|
||||
//==============================================================================
|
||||
|
||||
/** @defgroup Common_Parameters_TouchKey_Thresholds 05 - Thresholds for TouchKey sensors
|
||||
* @{ */
|
||||
|
||||
/** TouchKeys Proximity state input threshold (range=0..255)
|
||||
- Enter Proximity state if delta is above
|
||||
*/
|
||||
#define TSLPRM_TKEY_PROX_IN_TH (10)
|
||||
|
||||
/** TouchKeys Proximity state output threshold (range=0..255)
|
||||
- Exit Proximity state if delta is below
|
||||
*/
|
||||
#define TSLPRM_TKEY_PROX_OUT_TH (5)
|
||||
|
||||
/** TouchKeys Detect state input threshold (range=0..255)
|
||||
- Enter Detect state if delta is above
|
||||
*/
|
||||
#define TSLPRM_TKEY_DETECT_IN_TH (20)
|
||||
|
||||
/** TouchKeys Detect state output threshold (range=0..255)
|
||||
- Exit Detect state if delta is below
|
||||
*/
|
||||
#define TSLPRM_TKEY_DETECT_OUT_TH (15)
|
||||
|
||||
/** TouchKeys re-Calibration threshold (range=0..255)
|
||||
- @warning The value is inverted in the sensor state machine
|
||||
- Enter Calibration state if delta is below
|
||||
*/
|
||||
#define TSLPRM_TKEY_CALIB_TH (20)
|
||||
|
||||
/** TouchKey, Linear and Rotary sensors thresholds coefficient (range=0..4)
|
||||
This multiplier coefficient is applied on Detect thresholds only.
|
||||
- 0: feature disabled
|
||||
- 1: thresholds x 2
|
||||
- 2: thresholds x 4
|
||||
- 3: thresholds x 8
|
||||
- 4: thresholds x 16
|
||||
*/
|
||||
#define TSLPRM_COEFF_TH (1)
|
||||
|
||||
/** @} Common_Parameters_TouchKey_Thresholds */
|
||||
|
||||
//==============================================================================
|
||||
// Thresholds for Linear and Rotary sensors
|
||||
//==============================================================================
|
||||
|
||||
/** @defgroup Common_Parameters_LinRot_Thresholds 06 - Thresholds for Linear and Rotary sensors
|
||||
* @{ */
|
||||
|
||||
/** Linear/Rotary Proximity state input threshold (range=0..255)
|
||||
- Enter Proximity state if delta is above
|
||||
*/
|
||||
#define TSLPRM_LINROT_PROX_IN_TH (10)
|
||||
|
||||
/** Linear/Rotary Proximity state output threshold (range=0..255)
|
||||
- Exit Proximity state if delta is below
|
||||
*/
|
||||
#define TSLPRM_LINROT_PROX_OUT_TH (5)
|
||||
|
||||
/** Linear/Rotary Detect state input threshold (range=0..255)
|
||||
- Enter Detect state if delta is above
|
||||
*/
|
||||
#define TSLPRM_LINROT_DETECT_IN_TH (20)
|
||||
|
||||
/** Linear/Rotary Detect state output threshold (range=0..255)
|
||||
- Exit Detect state if delta is below
|
||||
*/
|
||||
#define TSLPRM_LINROT_DETECT_OUT_TH (15)
|
||||
|
||||
/** Linear/Rotary re-Calibration threshold (range=0..255)
|
||||
- @warning The value is inverted in the sensor state machine
|
||||
- Enter Calibration state if delta is below
|
||||
- A low absolute value will result in a higher sensitivity and thus some spurious
|
||||
recalibration may be issued.
|
||||
*/
|
||||
#define TSLPRM_LINROT_CALIB_TH (20)
|
||||
|
||||
/** Linear/Rotary Delta normalization (0=No, 1=Yes)
|
||||
- When this parameter is set, a coefficient is applied on all Delta of all sensors
|
||||
in order to normalize them and to improve the position calculation.
|
||||
- These coefficients must be defined in a constant table in the application (see Library examples).
|
||||
- The MSB is the coefficient integer part, the LSB is the coefficient real part.
|
||||
- Examples:
|
||||
- To apply a factor 1.10:
|
||||
0x01 to the MSB
|
||||
0x1A to the LSB (0.10 x 256 = 25.6 -> rounded to 26 = 0x1A)
|
||||
- To apply a factor 0.90:
|
||||
0x00 to the MSB
|
||||
0xE6 to the LSB (0.90 x 256 = 230.4 -> rounded to 230 = 0xE6)
|
||||
- To apply no factor:
|
||||
0x01 to the MSB
|
||||
0x00 to the LSB
|
||||
*/
|
||||
#define TSLPRM_LINROT_USE_NORMDELTA (1)
|
||||
|
||||
/** @} Common_Parameters_LinRot_Thresholds */
|
||||
|
||||
//==============================================================================
|
||||
// Linear/Rotary sensors used
|
||||
//==============================================================================
|
||||
|
||||
/** @defgroup Common_Parameters_LinRot_Used 07 - Linear/Rotary sensors used
|
||||
* @{ */
|
||||
|
||||
/** Select which Linear and Rotary sensors you use in your application.
|
||||
- 0 = Not Used
|
||||
- 1 = Used
|
||||
|
||||
LIN = Linear sensor
|
||||
ROT = Rotary sensor
|
||||
M1 = Mono electrodes design with 0/255 position at extremities of the sensor
|
||||
M2 = Mono electrodes design
|
||||
H = Half-ended electrodes design
|
||||
D = Dual electrodes design
|
||||
*/
|
||||
#define TSLPRM_USE_3CH_LIN_M1 (1)
|
||||
#define TSLPRM_USE_3CH_LIN_M2 (1)
|
||||
#define TSLPRM_USE_3CH_LIN_H (1)
|
||||
#define TSLPRM_USE_3CH_ROT_M (1)
|
||||
|
||||
#define TSLPRM_USE_4CH_LIN_M1 (1)
|
||||
#define TSLPRM_USE_4CH_LIN_M2 (1)
|
||||
#define TSLPRM_USE_4CH_LIN_H (1)
|
||||
#define TSLPRM_USE_4CH_ROT_M (1)
|
||||
|
||||
#define TSLPRM_USE_5CH_LIN_M1 (1)
|
||||
#define TSLPRM_USE_5CH_LIN_M2 (1)
|
||||
#define TSLPRM_USE_5CH_LIN_H (1)
|
||||
#define TSLPRM_USE_5CH_ROT_M (1)
|
||||
#define TSLPRM_USE_5CH_ROT_D (1)
|
||||
|
||||
#define TSLPRM_USE_6CH_LIN_M1 (1)
|
||||
#define TSLPRM_USE_6CH_LIN_M2 (1)
|
||||
#define TSLPRM_USE_6CH_LIN_H (1)
|
||||
#define TSLPRM_USE_6CH_ROT_M (1)
|
||||
|
||||
/** @} Common_Parameters_LinRot_used */
|
||||
|
||||
//==============================================================================
|
||||
// Linear/Rotary sensors position
|
||||
//==============================================================================
|
||||
|
||||
/** @defgroup Common_Parameters_LinRot_Position 08 - Linear/Rotary sensors position
|
||||
* @{ */
|
||||
|
||||
/** Position resolution in number of bits (range=1..8)
|
||||
- A Low value will result in a low resolution and will be less subject to noise.
|
||||
- A High value will result in a high resolution and will be more subject to noise.
|
||||
*/
|
||||
#define TSLPRM_LINROT_RESOLUTION (7)
|
||||
|
||||
/** Direction change threshold in position unit (range=0..255)
|
||||
- Defines the default threshold used during the change direction process.
|
||||
- A Low value will result in a faster direction change.
|
||||
- A High value will result in a slower direction change.
|
||||
*/
|
||||
#define TSLPRM_LINROT_DIR_CHG_POS (10)
|
||||
|
||||
/** Direction change debounce (range=0..63)
|
||||
- Defines the default integrator counter used during the change direction process.
|
||||
- This counter is decremented when the same change in the position is detected and the direction will
|
||||
change after this counter reaches zero.
|
||||
- A Low value will result in a faster direction change.
|
||||
- A High value will result in a slower direction change.
|
||||
*/
|
||||
#define TSLPRM_LINROT_DIR_CHG_DEB (1)
|
||||
|
||||
/** @} Common_Parameters_LinRot_Position */
|
||||
|
||||
//==============================================================================
|
||||
// Debounce counters
|
||||
//==============================================================================
|
||||
|
||||
/** @defgroup Common_Parameters_Debounce 09 - Debounce counters
|
||||
* @{ */
|
||||
|
||||
/** Proximity state debounce in samples unit (range=0..63)
|
||||
- A Low value will result in a higher sensitivity during the Proximity detection but with less noise filtering.
|
||||
- A High value will result in improving the system noise immunity but will increase the system response time.
|
||||
*/
|
||||
#define TSLPRM_DEBOUNCE_PROX (3)
|
||||
|
||||
/** Detect state debounce in samples unit (range=0..63)
|
||||
- A Low value will result in a higher sensitivity during the detection but with less noise filtering.
|
||||
- A High value will result in improving the system noise immunity but will increase the system response time.
|
||||
*/
|
||||
#define TSLPRM_DEBOUNCE_DETECT (3)
|
||||
|
||||
/** Release state debounce in samples unit (range=0..63)
|
||||
- A Low value will result in a higher sensitivity during the end-detection but with less noise filtering.
|
||||
- A High value will result in a lower sensitivity during the end-detection but with more noise filtering.
|
||||
*/
|
||||
#define TSLPRM_DEBOUNCE_RELEASE (3)
|
||||
|
||||
/** Re-calibration state debounce in samples unit (range=0..63)
|
||||
- A Low value will result in a higher sensitivity during the recalibration but with less noise filtering.
|
||||
- A High value will result in a lower sensitivity during the recalibration but with more noise filtering.
|
||||
*/
|
||||
#define TSLPRM_DEBOUNCE_CALIB (3)
|
||||
|
||||
/** Error state debounce in samples unit (range=0..63)
|
||||
- A Low value will result in a higher sensitivity to enter in error state.
|
||||
- A High value will result in a lower sensitivity to enter in error state.
|
||||
*/
|
||||
#define TSLPRM_DEBOUNCE_ERROR (3)
|
||||
|
||||
/** @} Common_Parameters_Debounce */
|
||||
|
||||
//==============================================================================
|
||||
// Environment Change System (ECS)
|
||||
//==============================================================================
|
||||
|
||||
/** @defgroup Common_Parameters_ECS 10 - ECS
|
||||
* @{ */
|
||||
|
||||
/** Environment Change System Slow K factor (range=0..255)
|
||||
- The higher value is K, the faster is the response time.
|
||||
*/
|
||||
#define TSLPRM_ECS_K_SLOW (10)
|
||||
|
||||
/** Environment Change System Fast K factor (range=0..255)
|
||||
- The higher value is K, the faster is the response time.
|
||||
*/
|
||||
#define TSLPRM_ECS_K_FAST (20)
|
||||
|
||||
/** Environment Change System delay in msec (range=0..5000)
|
||||
- The ECS will be started after this delay and when all sensors are in Release state.
|
||||
*/
|
||||
#define TSLPRM_ECS_DELAY (500)
|
||||
|
||||
/** @} Common_Parameters_ECS */
|
||||
|
||||
//==============================================================================
|
||||
// Detection Time Out (DTO)
|
||||
//==============================================================================
|
||||
|
||||
/** @defgroup Common_Parameters_DTO 11 - DTO
|
||||
* @{ */
|
||||
|
||||
/** Detection Time Out delay in seconds (range=0..63)
|
||||
- Value 0: DTO processing not compiled in the code (to gain size if not used).
|
||||
- Value 1: Default time out infinite.
|
||||
- Value between 2 and 63: Default time out between value n-1 and n.
|
||||
- Examples:
|
||||
- With a DTO equal to 2, the time out is between 1s and 2s.
|
||||
- With a DTO equal to 63, the time out is between 62s and 63s.
|
||||
|
||||
@note The DTO can be changed in run-time by the application only if the
|
||||
default value is between 1 and 63.
|
||||
*/
|
||||
#define TSLPRM_DTO (5)
|
||||
|
||||
/** @} Common_Parameters_DTO */
|
||||
|
||||
//==============================================================================
|
||||
// Detection Exclusion System (DXS)
|
||||
//==============================================================================
|
||||
|
||||
/** @defgroup Common_Parameters_DXS 12 - DXS
|
||||
* @{ */
|
||||
|
||||
/** Detection Exclusion System (0=No, 1=Yes)
|
||||
*/
|
||||
#define TSLPRM_USE_DXS (1)
|
||||
|
||||
/** @} Common_Parameters_DXS */
|
||||
|
||||
//==============================================================================
|
||||
// Miscellaneous parameters
|
||||
//==============================================================================
|
||||
|
||||
/** @defgroup Common_Parameters_Misc 13 - Miscellaneous
|
||||
* @{ */
|
||||
|
||||
/** Timing tick frequency in Hz (range=125, 250, 500, 1000, 2000)
|
||||
- Result to a timing interrupt respectively every 8ms, 4ms, 2ms, 1ms, 0.5ms
|
||||
*/
|
||||
#define TSLPRM_TICK_FREQ (1000)
|
||||
|
||||
/** @} Common_Parameters_Misc */
|
||||
|
||||
/** @} Common_Parameters */
|
||||
|
||||
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
//++++++++++++++++++++++++++++++ MCU PARAMETERS ++++++++++++++++++++++++++++++++
|
||||
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
|
||||
/** @defgroup STM32F3xx_Parameters STM32F3xx Parameters
|
||||
* @{ */
|
||||
|
||||
//==============================================================================
|
||||
// GPIO configuration
|
||||
//==============================================================================
|
||||
|
||||
/** @defgroup STM32F3xx_Parameters_GPIO_Config 01 - TSC GPIOs Configuration
|
||||
* @{ */
|
||||
|
||||
/** TSC GPIOs Configuration selection (range=0..1)
|
||||
- 0: Manual. The TSC GPIOs configuration must be done by the application code.
|
||||
- 1: Automatic. The TSLPRM_TSC_GROUPx_IOy parameters below must be filled up.
|
||||
The TSC GPIOs configuration is automatically done by the STMTouch driver.
|
||||
*/
|
||||
#define TSLPRM_TSC_GPIO_CONFIG (1)
|
||||
|
||||
//+++ DO NOT CHANGE THESE VALUES +++++++++++++++++++++++++++++++++
|
||||
// These defines must be applied to the TSLPRM_TSC_GROUPx_IOy parameters below.
|
||||
#define NU (0) // Not Used IO
|
||||
#define CHANNEL (1) // Channel IO
|
||||
#define SHIELD (2) // Shield IO (= Channel IO but not acquired)
|
||||
#define SAMPCAP (3) // Sampling Capacitor IO
|
||||
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
|
||||
// If TSLPRM_TSC_GPIO_CONFIG=1 assign each TSLPRM_TSC_GROUPx_IOy parameters below.
|
||||
// If TSLPRM_TSC_GPIO_CONFIG=0 these parameters are ignored.
|
||||
// STM32F30X STM32F37X
|
||||
#define TSLPRM_TSC_GROUP1_IO1 NU // PA0 PA0
|
||||
#define TSLPRM_TSC_GROUP1_IO2 NU // PA1 PA1
|
||||
#define TSLPRM_TSC_GROUP1_IO3 NU // PA2 PA2
|
||||
#define TSLPRM_TSC_GROUP1_IO4 NU // PA3 PA3
|
||||
|
||||
#define TSLPRM_TSC_GROUP2_IO1 NU // PA4 PA4
|
||||
#define TSLPRM_TSC_GROUP2_IO2 NU // PA5 PA5
|
||||
#define TSLPRM_TSC_GROUP2_IO3 NU // PA6 PA6
|
||||
#define TSLPRM_TSC_GROUP2_IO4 NU // PA7 PA7
|
||||
|
||||
#define TSLPRM_TSC_GROUP3_IO1 NU // PC5 PC4 << diff
|
||||
#define TSLPRM_TSC_GROUP3_IO2 NU // PB0 PC5 << diff
|
||||
#define TSLPRM_TSC_GROUP3_IO3 NU // PB1 PB0 << diff
|
||||
#define TSLPRM_TSC_GROUP3_IO4 NU // PB2 PB1 << diff
|
||||
|
||||
#define TSLPRM_TSC_GROUP4_IO1 NU // PA9 PA9
|
||||
#define TSLPRM_TSC_GROUP4_IO2 NU // PA10 PA10
|
||||
#define TSLPRM_TSC_GROUP4_IO3 NU // PA13 PA13
|
||||
#define TSLPRM_TSC_GROUP4_IO4 NU // PA14 PA14
|
||||
|
||||
#define TSLPRM_TSC_GROUP5_IO1 NU // PB3 PB3
|
||||
#define TSLPRM_TSC_GROUP5_IO2 NU // PB4 PB4
|
||||
#define TSLPRM_TSC_GROUP5_IO3 NU // PB6 PB6
|
||||
#define TSLPRM_TSC_GROUP5_IO4 NU // PB7 PB7
|
||||
|
||||
#define TSLPRM_TSC_GROUP6_IO1 NU // PB11 PB14 << diff
|
||||
#define TSLPRM_TSC_GROUP6_IO2 NU // PB12 PB15 << diff
|
||||
#define TSLPRM_TSC_GROUP6_IO3 NU // PB13 PD8 << diff
|
||||
#define TSLPRM_TSC_GROUP6_IO4 NU // PB14 PD9 << diff
|
||||
|
||||
#define TSLPRM_TSC_GROUP7_IO1 NU // PE2 PE2
|
||||
#define TSLPRM_TSC_GROUP7_IO2 NU // PE3 PE3
|
||||
#define TSLPRM_TSC_GROUP7_IO3 NU // PE4 PE4
|
||||
#define TSLPRM_TSC_GROUP7_IO4 NU // PE5 PE5
|
||||
|
||||
#define TSLPRM_TSC_GROUP8_IO1 NU // PD12 PD12
|
||||
#define TSLPRM_TSC_GROUP8_IO2 NU // PD13 PD13
|
||||
#define TSLPRM_TSC_GROUP8_IO3 NU // PD14 PD14
|
||||
#define TSLPRM_TSC_GROUP8_IO4 NU // PD15 PD15
|
||||
|
||||
/** @} STM32F3xx_Parameters_GPIO_Config */
|
||||
|
||||
//==============================================================================
|
||||
// Charge Transfer Pulses
|
||||
//==============================================================================
|
||||
|
||||
/** @defgroup STM32F3xx_Parameters_CT_Pulses 02 - Charge Transfer Pulses
|
||||
* @{ */
|
||||
|
||||
/** Charge Transfer Pulse High (range=0..15)
|
||||
- 0: 1 x tPGCLK
|
||||
- 1: 2 x tPGCLK
|
||||
- ...
|
||||
- 15: 16 x tPGCLK
|
||||
*/
|
||||
#define TSLPRM_TSC_CTPH (1)
|
||||
|
||||
/** Charge Transfer Pulse Low (range=0..15)
|
||||
- 0: 1 x tPGCLK
|
||||
- 1: 2 x tPGCLK
|
||||
- ...
|
||||
- 15: 16 x tPGCLK
|
||||
*/
|
||||
#define TSLPRM_TSC_CTPL (1)
|
||||
|
||||
/** Pulse Generator Prescaler (range=0..7)
|
||||
- 0: fPGCLK = fHCLK
|
||||
- 1: fPGCLK = fHCLK/2
|
||||
- ...
|
||||
- 7: fPGCLK = fHCLK/128
|
||||
*/
|
||||
#define TSLPRM_TSC_PGPSC (5)
|
||||
|
||||
/** @} STM32F3xx_Parameters_CT_Pulses */
|
||||
|
||||
//==============================================================================
|
||||
// IOs
|
||||
//==============================================================================
|
||||
|
||||
/** @defgroup STM32F3xx_Parameters_IOs 03 - I/Os
|
||||
* @{ */
|
||||
|
||||
/** TSC IOs default mode when no on-going acquisition (range=0..1)
|
||||
- 0: Output push-pull low
|
||||
- 1: Input floating
|
||||
*/
|
||||
#define TSLPRM_TSC_IODEF (0)
|
||||
|
||||
/** Acquisition Mode (range=0..1)
|
||||
- 0: Normal acquisition mode
|
||||
- 1: Synchronized acquisition mode
|
||||
*/
|
||||
#define TSLPRM_TSC_AM (0)
|
||||
|
||||
/** Synchronization Pin (range=0..1)
|
||||
- 0: PB08
|
||||
- 1: PB10
|
||||
*/
|
||||
#define TSLPRM_TSC_SYNC_PIN (0)
|
||||
|
||||
/** Synchronization Polarity (range=0..1)
|
||||
- 0: Falling edge only
|
||||
- 1: Rising edge and high level
|
||||
*/
|
||||
#define TSLPRM_TSC_SYNC_POL (0)
|
||||
|
||||
/** @} STM32F3xx_Parameters_Misc */
|
||||
|
||||
//==============================================================================
|
||||
// Spread Spectrum
|
||||
//==============================================================================
|
||||
|
||||
/** @defgroup STM32F3xx_Parameters_SpreadSpectrum 04 - Spread Spectrum
|
||||
* @{ */
|
||||
|
||||
/** Use Spread Spectrum (0=No, 1=Yes)
|
||||
*/
|
||||
#define TSLPRM_TSC_USE_SS (0)
|
||||
|
||||
/** Spread Spectrum Deviation (range=0..127)
|
||||
- 0: 1 x tSSCLK
|
||||
- 1: 2 x tSSCLK
|
||||
- ...
|
||||
- 127: 128 x tSSCLK
|
||||
*/
|
||||
#define TSLPRM_TSC_SSD (0)
|
||||
|
||||
/** Spread Spectrum Prescaler (range=0..1)
|
||||
- 0: fSSCLK = fHCLK
|
||||
- 1: fSSCLK = fHCLK/2
|
||||
*/
|
||||
#define TSLPRM_TSC_SSPSC (0)
|
||||
|
||||
/** @} STM32F3xx_Parameters_SpreadSpectrum */
|
||||
|
||||
/** @} STM32F3xx_Parameters */
|
||||
|
||||
// DO NOT REMOVE !!!
|
||||
#include "tsl_check_config.h"
|
||||
|
||||
#endif /* __TSL_CONF_STM32F3XX_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,498 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file tsl_conf_stm32l1xx.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.3.2
|
||||
* @date 22-January-2013
|
||||
* @brief Acquisition parameters for STM32L1xx products.
|
||||
* @note This file must be copied in the application project and values
|
||||
* changed for the application.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __TSL_CONF_STM32L1xx_H
|
||||
#define __TSL_CONF_STM32L1xx_H
|
||||
|
||||
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
//+++++++++++++++++++++++++++ COMMON PARAMETERS ++++++++++++++++++++++++++++++++
|
||||
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
|
||||
/** @defgroup Common_Parameters Common Parameters
|
||||
* @{ */
|
||||
|
||||
//==============================================================================
|
||||
// Number of elements
|
||||
//==============================================================================
|
||||
|
||||
/** @defgroup Common_Parameters_Number_Of_Elements 01 - Number of elements
|
||||
* @{ */
|
||||
|
||||
/** Total number of channels in application (range=1..255)
|
||||
*/
|
||||
#define TSLPRM_TOTAL_CHANNELS (1)
|
||||
|
||||
/** Total number of banks in application (range=1..255)
|
||||
*/
|
||||
#define TSLPRM_TOTAL_BANKS (1)
|
||||
|
||||
/** Total number of "Extended" TouchKeys in application (range=0..255)
|
||||
*/
|
||||
#define TSLPRM_TOTAL_TOUCHKEYS (1)
|
||||
|
||||
/** Total number of "Basic" TouchKeys in application (range=0..255)
|
||||
*/
|
||||
#define TSLPRM_TOTAL_TOUCHKEYS_B (1)
|
||||
|
||||
/** Total number of "Extended" Linear and Rotary sensors in application (range=0..255)
|
||||
- Count also the 1-channel linear sensor used as TouchKey
|
||||
*/
|
||||
#define TSLPRM_TOTAL_LINROTS (1)
|
||||
|
||||
/** Total number of "Basic" Linear and Rotary sensors in application (range=0..255)
|
||||
- Count also the 1-channel linear sensor used as TouchKey
|
||||
*/
|
||||
#define TSLPRM_TOTAL_LINROTS_B (1)
|
||||
|
||||
/** Total number of sensors/objects in application (range=1..255)
|
||||
- Count all TouchKeys, Linear and Rotary sensors
|
||||
*/
|
||||
#define TSLPRM_TOTAL_OBJECTS (1)
|
||||
|
||||
/** @} Common_Parameters_Number_Of_Elements */
|
||||
|
||||
//==============================================================================
|
||||
// Optional features
|
||||
//==============================================================================
|
||||
|
||||
/** @defgroup Common_Parameters_Options 02 - Optional features
|
||||
* @{ */
|
||||
|
||||
/** Record the last measure (0=No, 1=Yes)
|
||||
- If No the measure is recalculated using the Reference and Delta
|
||||
*/
|
||||
#define TSLPRM_USE_MEAS (1)
|
||||
|
||||
/** Zone management usage (0=No, 1=Yes)
|
||||
*/
|
||||
#define TSLPRM_USE_ZONE (1)
|
||||
|
||||
/** Proximity detection usage (0=No, 1=Yes)
|
||||
*/
|
||||
#define TSLPRM_USE_PROX (1)
|
||||
|
||||
/** Use the Timer tick callback (0=No, 1=Yes)
|
||||
- When equal to 1, the function TSL_CallBack_TimerTick must be defined in
|
||||
the application code. It is called for each timer interruption.
|
||||
*/
|
||||
#define TSLPRM_USE_TIMER_CALLBACK (1)
|
||||
|
||||
/** Acquisition interrupt mode (0=No, 1=Yes)
|
||||
- If No the TS interrupt is not used.
|
||||
- If Yes the TS interrupt is used.
|
||||
*/
|
||||
#define TSLPRM_USE_ACQ_INTERRUPT (1)
|
||||
|
||||
/** @} Common_Parameters_Options */
|
||||
|
||||
//==============================================================================
|
||||
// Acquisition limits
|
||||
//==============================================================================
|
||||
|
||||
/** @defgroup Common_Parameters_Acquisition_Limits 03 - Acquisition limits
|
||||
* @{ */
|
||||
|
||||
/** Minimum acquisition measurement (range=0..65535)
|
||||
- This is the minimum acceptable value for the acquisition measure.
|
||||
- The acquisition will be in error if the measure is below this value.
|
||||
*/
|
||||
#define TSLPRM_ACQ_MIN (10)
|
||||
|
||||
/** Maximum acquisition measurement (range=0..65535)
|
||||
- This is the maximum acceptable value for the acquisition measure.
|
||||
- The acquisition will be in error if the measure is above this value.
|
||||
*/
|
||||
#define TSLPRM_ACQ_MAX (4000)
|
||||
|
||||
/** @} Common_Parameters_Acquisition_Limits */
|
||||
|
||||
//==============================================================================
|
||||
// Calibration
|
||||
//==============================================================================
|
||||
|
||||
/** @defgroup Common_Parameters_Calibration 04 - Calibration
|
||||
* @{ */
|
||||
|
||||
/** Number of calibration samples (range=4, 8, 16)
|
||||
- Low value = faster calibration but less precision.
|
||||
- High value = slower calibration but more precision.
|
||||
*/
|
||||
#define TSLPRM_CALIB_SAMPLES (8)
|
||||
|
||||
/** Delay in measurement samples before starting the calibration (range=0..40)
|
||||
- This is usefull if a noise filter is used.
|
||||
- Write 0 to disable the delay.
|
||||
*/
|
||||
#define TSLPRM_CALIB_DELAY (10)
|
||||
|
||||
/** @} Common_Parameters_Calibration */
|
||||
|
||||
//==============================================================================
|
||||
// Thresholds for TouchKey sensors
|
||||
//==============================================================================
|
||||
|
||||
/** @defgroup Common_Parameters_TouchKey_Thresholds 05 - Thresholds for TouchKey sensors
|
||||
* @{ */
|
||||
|
||||
/** TouchKeys Proximity state input threshold (range=0..255)
|
||||
- Enter Proximity state if delta is above
|
||||
*/
|
||||
#define TSLPRM_TKEY_PROX_IN_TH (10)
|
||||
|
||||
/** TouchKeys Proximity state output threshold (range=0..255)
|
||||
- Exit Proximity state if delta is below
|
||||
*/
|
||||
#define TSLPRM_TKEY_PROX_OUT_TH (5)
|
||||
|
||||
/** TouchKeys Detect state input threshold (range=0..255)
|
||||
- Enter Detect state if delta is above
|
||||
*/
|
||||
#define TSLPRM_TKEY_DETECT_IN_TH (20)
|
||||
|
||||
/** TouchKeys Detect state output threshold (range=0..255)
|
||||
- Exit Detect state if delta is below
|
||||
*/
|
||||
#define TSLPRM_TKEY_DETECT_OUT_TH (15)
|
||||
|
||||
/** TouchKeys re-Calibration threshold (range=0..255)
|
||||
- @warning The value is inverted in the sensor state machine
|
||||
- Enter Calibration state if delta is below
|
||||
*/
|
||||
#define TSLPRM_TKEY_CALIB_TH (20)
|
||||
|
||||
/** TouchKey, Linear and Rotary sensors thresholds coefficient (range=0..4)
|
||||
This multiplier coefficient is applied on Detect thresholds only.
|
||||
- 0: feature disabled
|
||||
- 1: thresholds x 2
|
||||
- 2: thresholds x 4
|
||||
- 3: thresholds x 8
|
||||
- 4: thresholds x 16
|
||||
*/
|
||||
#define TSLPRM_COEFF_TH (1)
|
||||
|
||||
/** @} Common_Parameters_TouchKey_Thresholds */
|
||||
|
||||
//==============================================================================
|
||||
// Thresholds for Linear and Rotary sensors
|
||||
//==============================================================================
|
||||
|
||||
/** @defgroup Common_Parameters_LinRot_Thresholds 06 - Thresholds for Linear and Rotary sensors
|
||||
* @{ */
|
||||
|
||||
/** Linear/Rotary Proximity state input threshold (range=0..255)
|
||||
- Enter Proximity state if delta is above
|
||||
*/
|
||||
#define TSLPRM_LINROT_PROX_IN_TH (10)
|
||||
|
||||
/** Linear/Rotary Proximity state output threshold (range=0..255)
|
||||
- Exit Proximity state if delta is below
|
||||
*/
|
||||
#define TSLPRM_LINROT_PROX_OUT_TH (5)
|
||||
|
||||
/** Linear/Rotary Detect state input threshold (range=0..255)
|
||||
- Enter Detect state if delta is above
|
||||
*/
|
||||
#define TSLPRM_LINROT_DETECT_IN_TH (20)
|
||||
|
||||
/** Linear/Rotary Detect state output threshold (range=0..255)
|
||||
- Exit Detect state if delta is below
|
||||
*/
|
||||
#define TSLPRM_LINROT_DETECT_OUT_TH (15)
|
||||
|
||||
/** Linear/Rotary re-Calibration threshold (range=0..255)
|
||||
- @warning The value is inverted in the sensor state machine
|
||||
- Enter Calibration state if delta is below
|
||||
- A low absolute value will result in a higher sensitivity and thus some spurious
|
||||
recalibration may be issued.
|
||||
*/
|
||||
#define TSLPRM_LINROT_CALIB_TH (20)
|
||||
|
||||
/** Linear/Rotary Delta normalization (0=No, 1=Yes)
|
||||
- When this parameter is set, a coefficient is applied on all Delta of all sensors
|
||||
in order to normalize them and to improve the position calculation.
|
||||
- These coefficients must be defined in a constant table in the application (see Library examples).
|
||||
- The MSB is the coefficient integer part, the LSB is the coefficient real part.
|
||||
- Examples:
|
||||
- To apply a factor 1.10:
|
||||
0x01 to the MSB
|
||||
0x1A to the LSB (0.10 x 256 = 25.6 -> rounded to 26 = 0x1A)
|
||||
- To apply a factor 0.90:
|
||||
0x00 to the MSB
|
||||
0xE6 to the LSB (0.90 x 256 = 230.4 -> rounded to 230 = 0xE6)
|
||||
- To apply no factor:
|
||||
0x01 to the MSB
|
||||
0x00 to the LSB
|
||||
*/
|
||||
#define TSLPRM_LINROT_USE_NORMDELTA (1)
|
||||
|
||||
/** @} Common_Parameters_LinRot_Thresholds */
|
||||
|
||||
//==============================================================================
|
||||
// Linear/Rotary sensors used
|
||||
//==============================================================================
|
||||
|
||||
/** @defgroup Common_Parameters_LinRot_Used 07 - Linear/Rotary sensors used
|
||||
* @{ */
|
||||
|
||||
/** Select which Linear and Rotary sensors you use in your application.
|
||||
- 0 = Not Used
|
||||
- 1 = Used
|
||||
|
||||
LIN = Linear sensor
|
||||
ROT = Rotary sensor
|
||||
M1 = Mono electrodes design with 0/255 position at extremities of the sensor
|
||||
M2 = Mono electrodes design
|
||||
H = Half-ended electrodes design
|
||||
D = Dual electrodes design
|
||||
*/
|
||||
#define TSLPRM_USE_3CH_LIN_M1 (1)
|
||||
#define TSLPRM_USE_3CH_LIN_M2 (1)
|
||||
#define TSLPRM_USE_3CH_LIN_H (1)
|
||||
#define TSLPRM_USE_3CH_ROT_M (1)
|
||||
|
||||
#define TSLPRM_USE_4CH_LIN_M1 (1)
|
||||
#define TSLPRM_USE_4CH_LIN_M2 (1)
|
||||
#define TSLPRM_USE_4CH_LIN_H (1)
|
||||
#define TSLPRM_USE_4CH_ROT_M (1)
|
||||
|
||||
#define TSLPRM_USE_5CH_LIN_M1 (1)
|
||||
#define TSLPRM_USE_5CH_LIN_M2 (1)
|
||||
#define TSLPRM_USE_5CH_LIN_H (1)
|
||||
#define TSLPRM_USE_5CH_ROT_M (1)
|
||||
#define TSLPRM_USE_5CH_ROT_D (1)
|
||||
|
||||
#define TSLPRM_USE_6CH_LIN_M1 (1)
|
||||
#define TSLPRM_USE_6CH_LIN_M2 (1)
|
||||
#define TSLPRM_USE_6CH_LIN_H (1)
|
||||
#define TSLPRM_USE_6CH_ROT_M (1)
|
||||
|
||||
/** @} Common_Parameters_LinRot_used */
|
||||
|
||||
//==============================================================================
|
||||
// Linear/Rotary sensors position
|
||||
//==============================================================================
|
||||
|
||||
/** @defgroup Common_Parameters_LinRot_Position 08 - Linear/Rotary sensors position
|
||||
* @{ */
|
||||
|
||||
/** Position resolution in number of bits (range=1..8)
|
||||
- A Low value will result in a low resolution and will be less subject to noise.
|
||||
- A High value will result in a high resolution and will be more subject to noise.
|
||||
*/
|
||||
#define TSLPRM_LINROT_RESOLUTION (7)
|
||||
|
||||
/** Direction change threshold in position unit (range=0..255)
|
||||
- Defines the default threshold used during the change direction process.
|
||||
- A Low value will result in a faster direction change.
|
||||
- A High value will result in a slower direction change.
|
||||
*/
|
||||
#define TSLPRM_LINROT_DIR_CHG_POS (10)
|
||||
|
||||
/** Direction change debounce (range=0..63)
|
||||
- Defines the default integrator counter used during the change direction process.
|
||||
- This counter is decremented when the same change in the position is detected and the direction will
|
||||
change after this counter reaches zero.
|
||||
- A Low value will result in a faster direction change.
|
||||
- A High value will result in a slower direction change.
|
||||
*/
|
||||
#define TSLPRM_LINROT_DIR_CHG_DEB (1)
|
||||
|
||||
/** @} Common_Parameters_LinRot_Position */
|
||||
|
||||
//==============================================================================
|
||||
// Debounce counters
|
||||
//==============================================================================
|
||||
|
||||
/** @defgroup Common_Parameters_Debounce 09 - Debounce counters
|
||||
* @{ */
|
||||
|
||||
/** Proximity state debounce in samples unit (range=0..63)
|
||||
- A Low value will result in a higher sensitivity during the Proximity detection but with less noise filtering.
|
||||
- A High value will result in improving the system noise immunity but will increase the system response time.
|
||||
*/
|
||||
#define TSLPRM_DEBOUNCE_PROX (3)
|
||||
|
||||
/** Detect state debounce in samples unit (range=0..63)
|
||||
- A Low value will result in a higher sensitivity during the detection but with less noise filtering.
|
||||
- A High value will result in improving the system noise immunity but will increase the system response time.
|
||||
*/
|
||||
#define TSLPRM_DEBOUNCE_DETECT (3)
|
||||
|
||||
/** Release state debounce in samples unit (range=0..63)
|
||||
- A Low value will result in a higher sensitivity during the end-detection but with less noise filtering.
|
||||
- A High value will result in a lower sensitivity during the end-detection but with more noise filtering.
|
||||
*/
|
||||
#define TSLPRM_DEBOUNCE_RELEASE (3)
|
||||
|
||||
/** Re-calibration state debounce in samples unit (range=0..63)
|
||||
- A Low value will result in a higher sensitivity during the recalibration but with less noise filtering.
|
||||
- A High value will result in a lower sensitivity during the recalibration but with more noise filtering.
|
||||
*/
|
||||
#define TSLPRM_DEBOUNCE_CALIB (3)
|
||||
|
||||
/** Error state debounce in samples unit (range=0..63)
|
||||
- A Low value will result in a higher sensitivity to enter in error state.
|
||||
- A High value will result in a lower sensitivity to enter in error state.
|
||||
*/
|
||||
#define TSLPRM_DEBOUNCE_ERROR (3)
|
||||
|
||||
/** @} Common_Parameters_Debounce */
|
||||
|
||||
//==============================================================================
|
||||
// Environment Change System (ECS)
|
||||
//==============================================================================
|
||||
|
||||
/** @defgroup Common_Parameters_ECS 10 - ECS
|
||||
* @{ */
|
||||
|
||||
/** Environment Change System Slow K factor (range=0..255)
|
||||
- The higher value is K, the faster is the response time.
|
||||
*/
|
||||
#define TSLPRM_ECS_K_SLOW (10)
|
||||
|
||||
/** Environment Change System Fast K factor (range=0..255)
|
||||
- The higher value is K, the faster is the response time.
|
||||
*/
|
||||
#define TSLPRM_ECS_K_FAST (20)
|
||||
|
||||
/** Environment Change System delay in msec (range=0..5000)
|
||||
- The ECS will be started after this delay and when all sensors are in Release state.
|
||||
*/
|
||||
#define TSLPRM_ECS_DELAY (500)
|
||||
|
||||
/** @} Common_Parameters_ECS */
|
||||
|
||||
//==============================================================================
|
||||
// Detection Time Out (DTO)
|
||||
//==============================================================================
|
||||
|
||||
/** @defgroup Common_Parameters_DTO 11 - DTO
|
||||
* @{ */
|
||||
|
||||
/** Detection Time Out delay in seconds (range=0..63)
|
||||
- Value 0: DTO processing not compiled in the code (to gain size if not used).
|
||||
- Value 1: Default time out infinite.
|
||||
- Value between 2 and 63: Default time out between value n-1 and n.
|
||||
- Examples:
|
||||
- With a DTO equal to 2, the time out is between 1s and 2s.
|
||||
- With a DTO equal to 63, the time out is between 62s and 63s.
|
||||
|
||||
@note The DTO can be changed in run-time by the application only if the
|
||||
default value is between 1 and 63.
|
||||
*/
|
||||
#define TSLPRM_DTO (5)
|
||||
|
||||
/** @} Common_Parameters_DTO */
|
||||
|
||||
//==============================================================================
|
||||
// Detection Exclusion System (DXS)
|
||||
//==============================================================================
|
||||
|
||||
/** @defgroup Common_Parameters_DXS 12 - DXS
|
||||
* @{ */
|
||||
|
||||
/** Detection Exclusion System (0=No, 1=Yes)
|
||||
*/
|
||||
#define TSLPRM_USE_DXS (1)
|
||||
|
||||
/** @} Common_Parameters_DXS */
|
||||
|
||||
//==============================================================================
|
||||
// Miscellaneous parameters
|
||||
//==============================================================================
|
||||
|
||||
/** @defgroup Common_Parameters_Misc 13 - Miscellaneous
|
||||
* @{ */
|
||||
|
||||
/** Timing tick frequency in Hz (range=125, 250, 500, 1000, 2000)
|
||||
- Result to a timing interrupt respectively every 8ms, 4ms, 2ms, 1ms, 0.5ms
|
||||
*/
|
||||
#define TSLPRM_TICK_FREQ (1000)
|
||||
|
||||
/** @} Common_Parameters_Misc */
|
||||
|
||||
/** @} Common_Parameters */
|
||||
|
||||
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
//++++++++++++++++++++++++++++++ MCU PARAMETERS ++++++++++++++++++++++++++++++++
|
||||
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
|
||||
/** @defgroup STM32L1xx_Parameters STM32L1xx Parameters
|
||||
* @{ */
|
||||
|
||||
/** @defgroup STM32L1xx_Parameters_Misc 01 - Miscellaneous
|
||||
* @{ */
|
||||
|
||||
/** Shield with a channel (0=No, 1=Yes)
|
||||
*/
|
||||
#define TSLPRM_USE_SHIELD (1)
|
||||
|
||||
/** IOs default mode when no on-going acquisition (range=0..1)
|
||||
- 0: Output push-pull low
|
||||
- 1: Input floating
|
||||
*/
|
||||
#define TSLPRM_IODEF (1)
|
||||
|
||||
/** Master timer prescaler for HW acquisition only (range=0..65535)
|
||||
- Divide the timer input clock by this value plus one
|
||||
*/
|
||||
#define TSLPRM_TIM_PRESCALER (0)
|
||||
|
||||
/** Master timer reload value for HW acquisition only (range=4..65534, even number)
|
||||
- Set the auto-reload value for the center aligned counter
|
||||
*/
|
||||
#define TSLPRM_TIM_RELOAD (64)
|
||||
|
||||
/** IT disabling for IO protection for SW acquisition only (range=0..1)
|
||||
- 0: IO not protected
|
||||
- 1: IO protected
|
||||
*/
|
||||
#define TSLPRM_PROTECT_IO_ACCESS (0)
|
||||
|
||||
/** Which GPIO will be used for SW acquisition only (range=0..1)
|
||||
- 0: Not used
|
||||
- 1: Used
|
||||
*/
|
||||
#define TSLPRM_USE_GPIOA (1)
|
||||
#define TSLPRM_USE_GPIOB (1)
|
||||
#define TSLPRM_USE_GPIOC (1)
|
||||
#define TSLPRM_USE_GPIOF (0)
|
||||
#define TSLPRM_USE_GPIOG (0)
|
||||
|
||||
/** @} STM32L1xx_Parameters_Misc */
|
||||
|
||||
/** @} STM32L1xx_Parameters */
|
||||
|
||||
// DO NOT REMOVE !!!
|
||||
#include "tsl_check_config.h"
|
||||
|
||||
#endif /* __TSL_CONF_STM32L1xx_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,594 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file tsl_conf_stm8tl5x.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.3.2
|
||||
* @date 22-January-2013
|
||||
* @brief Acquisition parameters for STM8TL5x products.
|
||||
* @note This file must be copied in the application project and values
|
||||
* changed for the application.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __TSL_CONF_STM8TL5X_H
|
||||
#define __TSL_CONF_STM8TL5X_H
|
||||
|
||||
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
//+++++++++++++++++++++++++++ COMMON PARAMETERS ++++++++++++++++++++++++++++++++
|
||||
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
|
||||
/** @defgroup Common_Parameters Common Parameters
|
||||
* @{ */
|
||||
|
||||
//==============================================================================
|
||||
// Number of elements
|
||||
//==============================================================================
|
||||
|
||||
/** @defgroup Common_Parameters_Number_Of_Elements 01 - Number of elements
|
||||
* @{ */
|
||||
|
||||
/** Total number of channels in application (range=1..255)
|
||||
*/
|
||||
#define TSLPRM_TOTAL_CHANNELS (1)
|
||||
|
||||
/** Total number of banks in application (range=1..255)
|
||||
*/
|
||||
#define TSLPRM_TOTAL_BANKS (1)
|
||||
|
||||
/** Total number of "Extended" TouchKeys in application (range=0..255)
|
||||
*/
|
||||
#define TSLPRM_TOTAL_TOUCHKEYS (1)
|
||||
|
||||
/** Total number of "Basic" TouchKeys in application (range=0..255)
|
||||
*/
|
||||
#define TSLPRM_TOTAL_TOUCHKEYS_B (1)
|
||||
|
||||
/** Total number of "Extended" Linear and Rotary sensors in application (range=0..255)
|
||||
- Count also the 1-channel linear sensor used as TouchKey
|
||||
*/
|
||||
#define TSLPRM_TOTAL_LINROTS (1)
|
||||
|
||||
/** Total number of "Basic" Linear and Rotary sensors in application (range=0..255)
|
||||
- Count also the 1-channel linear sensor used as TouchKey
|
||||
*/
|
||||
#define TSLPRM_TOTAL_LINROTS_B (1)
|
||||
|
||||
/** Total number of sensors/objects in application (range=1..255)
|
||||
- Count all TouchKeys, Linear and Rotary sensors
|
||||
*/
|
||||
#define TSLPRM_TOTAL_OBJECTS (1)
|
||||
|
||||
/** @} Common_Parameters_Number_Of_Elements */
|
||||
|
||||
//==============================================================================
|
||||
// Optional features
|
||||
//==============================================================================
|
||||
|
||||
/** @defgroup Common_Parameters_Options 02 - Optional features
|
||||
* @{ */
|
||||
|
||||
/** Record the last measure (0=No, 1=Yes)
|
||||
- If No the measure is recalculated using the Reference and Delta
|
||||
*/
|
||||
#define TSLPRM_USE_MEAS (1)
|
||||
|
||||
/** Zone management usage (0=No, 1=Yes)
|
||||
*/
|
||||
#define TSLPRM_USE_ZONE (1)
|
||||
|
||||
/** Proximity detection usage (0=No, 1=Yes)
|
||||
*/
|
||||
#define TSLPRM_USE_PROX (1)
|
||||
|
||||
/** Use the Timer tick callback (0=No, 1=Yes)
|
||||
- When equal to 1, the function TSL_CallBack_TimerTick must be defined in
|
||||
the application code. It is called for each timer interruption.
|
||||
*/
|
||||
#define TSLPRM_USE_TIMER_CALLBACK (1)
|
||||
|
||||
/** Acquisition interrupt mode (0=No, 1=Yes)
|
||||
- If No the acquisition is managed in the main routine using polling mode.
|
||||
- If Yes the acquisition is managed in the interrupt routines.
|
||||
*/
|
||||
#define TSLPRM_USE_ACQ_INTERRUPT (1)
|
||||
|
||||
/** @} Common_Parameters_Options */
|
||||
|
||||
//==============================================================================
|
||||
// Acquisition limits
|
||||
//==============================================================================
|
||||
|
||||
/** @defgroup Common_Parameters_Acquisition_Limits 03 - Acquisition limits
|
||||
* @{ */
|
||||
|
||||
/** Minimum acquisition measurement (range=0..65535)
|
||||
- This is the minimum acceptable value for the acquisition measure.
|
||||
- The acquisition will be in error if the measure is below this value.
|
||||
*/
|
||||
#define TSLPRM_ACQ_MIN (50)
|
||||
|
||||
/** Maximum acquisition measurement (range=0..65535)
|
||||
- This is the maximum acceptable value for the acquisition measure.
|
||||
- The acquisition will be in error if the measure is above this value.
|
||||
*/
|
||||
#define TSLPRM_ACQ_MAX (4000)
|
||||
|
||||
/** @} Common_Parameters_Acquisition_Limits */
|
||||
|
||||
//==============================================================================
|
||||
// Calibration
|
||||
//==============================================================================
|
||||
|
||||
/** @defgroup Common_Parameters_Calibration 04 - Calibration
|
||||
* @{ */
|
||||
|
||||
/** Number of calibration samples (range=4, 8, 16)
|
||||
- Low value = faster calibration but less precision.
|
||||
- High value = slower calibration but more precision.
|
||||
*/
|
||||
#define TSLPRM_CALIB_SAMPLES (8)
|
||||
|
||||
/** Delay in measurement samples before starting the calibration (range=0..40)
|
||||
- This is usefull if a noise filter is used.
|
||||
- Write 0 to disable the delay.
|
||||
*/
|
||||
#define TSLPRM_CALIB_DELAY (10)
|
||||
|
||||
/** @} Common_Parameters_Calibration */
|
||||
|
||||
//==============================================================================
|
||||
// Thresholds for TouchKey sensors
|
||||
//==============================================================================
|
||||
|
||||
/** @defgroup Common_Parameters_TouchKey_Thresholds 05 - Thresholds for TouchKey sensors
|
||||
* @{ */
|
||||
|
||||
/** TouchKeys Proximity state input threshold (range=0..255)
|
||||
- Enter Proximity state if delta is above
|
||||
*/
|
||||
#define TSLPRM_TKEY_PROX_IN_TH (15)
|
||||
|
||||
/** TouchKeys Proximity state output threshold (range=0..255)
|
||||
- Exit Proximity state if delta is below
|
||||
*/
|
||||
#define TSLPRM_TKEY_PROX_OUT_TH (5)
|
||||
|
||||
/** TouchKeys Detect state input threshold (range=0..255)
|
||||
- Enter Detect state if delta is above
|
||||
*/
|
||||
#define TSLPRM_TKEY_DETECT_IN_TH (50)
|
||||
|
||||
/** TouchKeys Detect state output threshold (range=0..255)
|
||||
- Exit Detect state if delta is below
|
||||
*/
|
||||
#define TSLPRM_TKEY_DETECT_OUT_TH (40)
|
||||
|
||||
/** TouchKeys re-Calibration threshold (range=0..255)
|
||||
- @warning The value is inverted in the sensor state machine
|
||||
- Enter Calibration state if delta is below
|
||||
*/
|
||||
#define TSLPRM_TKEY_CALIB_TH (20)
|
||||
|
||||
/** TouchKey, Linear and Rotary sensors thresholds coefficient (range=0..4)
|
||||
This multiplier coefficient is applied on Detect thresholds only.
|
||||
- 0: feature disabled
|
||||
- 1: thresholds x 2
|
||||
- 2: thresholds x 4
|
||||
- 3: thresholds x 8
|
||||
- 4: thresholds x 16
|
||||
*/
|
||||
#define TSLPRM_COEFF_TH (1)
|
||||
|
||||
/** @} Common_Parameters_TouchKey_Thresholds */
|
||||
|
||||
//==============================================================================
|
||||
// Thresholds for Linear and Rotary sensors
|
||||
//==============================================================================
|
||||
|
||||
/** @defgroup Common_Parameters_LinRot_Thresholds 06 - Thresholds for Linear and Rotary sensors
|
||||
* @{ */
|
||||
|
||||
/** Linear/Rotary Proximity state input threshold (range=0..255)
|
||||
- Enter Proximity state if delta is above
|
||||
*/
|
||||
#define TSLPRM_LINROT_PROX_IN_TH (15)
|
||||
|
||||
/** Linear/Rotary Proximity state output threshold (range=0..255)
|
||||
- Exit Proximity state if delta is below
|
||||
*/
|
||||
#define TSLPRM_LINROT_PROX_OUT_TH (5)
|
||||
|
||||
/** Linear/Rotary Detect state input threshold (range=0..255)
|
||||
- Enter Detect state if delta is above
|
||||
*/
|
||||
#define TSLPRM_LINROT_DETECT_IN_TH (50)
|
||||
|
||||
/** Linear/Rotary Detect state output threshold (range=0..255)
|
||||
- Exit Detect state if delta is below
|
||||
*/
|
||||
#define TSLPRM_LINROT_DETECT_OUT_TH (30)
|
||||
|
||||
/** Linear/Rotary re-Calibration threshold (range=0..255)
|
||||
- @warning The value is inverted in the sensor state machine
|
||||
- Enter Calibration state if delta is below
|
||||
- A low absolute value will result in a higher sensitivity and thus some spurious
|
||||
recalibration may be issued.
|
||||
*/
|
||||
#define TSLPRM_LINROT_CALIB_TH (20)
|
||||
|
||||
/** Linear/Rotary Delta normalization (0=No, 1=Yes)
|
||||
- When this parameter is set, a coefficient is applied on all Delta of all sensors
|
||||
in order to normalize them and to improve the position calculation.
|
||||
- These coefficients must be defined in a constant table in the application (see Library examples).
|
||||
- The MSB is the coefficient integer part, the LSB is the coefficient real part.
|
||||
- Examples:
|
||||
- To apply a factor 1.10:
|
||||
0x01 to the MSB
|
||||
0x1A to the LSB (0.10 x 256 = 25.6 -> rounded to 26 = 0x1A)
|
||||
- To apply a factor 0.90:
|
||||
0x00 to the MSB
|
||||
0xE6 to the LSB (0.90 x 256 = 230.4 -> rounded to 230 = 0xE6)
|
||||
- To apply no factor:
|
||||
0x01 to the MSB
|
||||
0x00 to the LSB
|
||||
*/
|
||||
#define TSLPRM_LINROT_USE_NORMDELTA (1)
|
||||
|
||||
/** @} Common_Parameters_LinRot_Thresholds */
|
||||
|
||||
//==============================================================================
|
||||
// Linear/Rotary sensors used
|
||||
//==============================================================================
|
||||
|
||||
/** @defgroup Common_Parameters_LinRot_Used 07 - Linear/Rotary sensors used
|
||||
* @{ */
|
||||
|
||||
/** Select which Linear and Rotary sensors you use in your application.
|
||||
- 0 = Not Used
|
||||
- 1 = Used
|
||||
|
||||
LIN = Linear sensor
|
||||
ROT = Rotary sensor
|
||||
M1 = Mono electrodes design with 0/255 position at extremities of the sensor
|
||||
M2 = Mono electrodes design
|
||||
H = Half-ended electrodes design
|
||||
D = Dual electrodes design
|
||||
*/
|
||||
#define TSLPRM_USE_3CH_LIN_M1 (1)
|
||||
#define TSLPRM_USE_3CH_LIN_M2 (1)
|
||||
#define TSLPRM_USE_3CH_LIN_H (1)
|
||||
#define TSLPRM_USE_3CH_ROT_M (1)
|
||||
|
||||
#define TSLPRM_USE_4CH_LIN_M1 (1)
|
||||
#define TSLPRM_USE_4CH_LIN_M2 (1)
|
||||
#define TSLPRM_USE_4CH_LIN_H (1)
|
||||
#define TSLPRM_USE_4CH_ROT_M (1)
|
||||
|
||||
#define TSLPRM_USE_5CH_LIN_M1 (1)
|
||||
#define TSLPRM_USE_5CH_LIN_M2 (1)
|
||||
#define TSLPRM_USE_5CH_LIN_H (1)
|
||||
#define TSLPRM_USE_5CH_ROT_M (1)
|
||||
#define TSLPRM_USE_5CH_ROT_D (1)
|
||||
|
||||
#define TSLPRM_USE_6CH_LIN_M1 (1)
|
||||
#define TSLPRM_USE_6CH_LIN_M2 (1)
|
||||
#define TSLPRM_USE_6CH_LIN_H (1)
|
||||
#define TSLPRM_USE_6CH_ROT_M (1)
|
||||
|
||||
/** @} Common_Parameters_LinRot_used */
|
||||
|
||||
//==============================================================================
|
||||
// Linear/Rotary sensors position
|
||||
//==============================================================================
|
||||
|
||||
/** @defgroup Common_Parameters_LinRot_Position 08 - Linear/Rotary sensors position
|
||||
* @{ */
|
||||
|
||||
/** Position resolution in number of bits (range=1..8)
|
||||
- A Low value will result in a low resolution and will be less subject to noise.
|
||||
- A High value will result in a high resolution and will be more subject to noise.
|
||||
*/
|
||||
#define TSLPRM_LINROT_RESOLUTION (7)
|
||||
|
||||
/** Direction change threshold in position unit (range=0..255)
|
||||
- Defines the default threshold used during the change direction process.
|
||||
- A Low value will result in a faster direction change.
|
||||
- A High value will result in a slower direction change.
|
||||
*/
|
||||
#define TSLPRM_LINROT_DIR_CHG_POS (10)
|
||||
|
||||
/** Direction change debounce (range=0..63)
|
||||
- Defines the default integrator counter used during the change direction process.
|
||||
- This counter is decremented when the same change in the position is detected and the direction will
|
||||
change after this counter reaches zero.
|
||||
- A Low value will result in a faster direction change.
|
||||
- A High value will result in a slower direction change.
|
||||
*/
|
||||
#define TSLPRM_LINROT_DIR_CHG_DEB (1)
|
||||
|
||||
/** @} Common_Parameters_LinRot_Position */
|
||||
|
||||
//==============================================================================
|
||||
// Debounce counters
|
||||
//==============================================================================
|
||||
|
||||
/** @defgroup Common_Parameters_Debounce 09 - Debounce counters
|
||||
* @{ */
|
||||
|
||||
/** Proximity state debounce in samples unit (range=0..63)
|
||||
- A Low value will result in a higher sensitivity during the Proximity detection but with less noise filtering.
|
||||
- A High value will result in improving the system noise immunity but will increase the system response time.
|
||||
*/
|
||||
#define TSLPRM_DEBOUNCE_PROX (3)
|
||||
|
||||
/** Detect state debounce in samples unit (range=0..63)
|
||||
- A Low value will result in a higher sensitivity during the detection but with less noise filtering.
|
||||
- A High value will result in improving the system noise immunity but will increase the system response time.
|
||||
*/
|
||||
#define TSLPRM_DEBOUNCE_DETECT (3)
|
||||
|
||||
/** Release state debounce in samples unit (range=0..63)
|
||||
- A Low value will result in a higher sensitivity during the end-detection but with less noise filtering.
|
||||
- A High value will result in a lower sensitivity during the end-detection but with more noise filtering.
|
||||
*/
|
||||
#define TSLPRM_DEBOUNCE_RELEASE (3)
|
||||
|
||||
/** Re-calibration state debounce in samples unit (range=0..63)
|
||||
- A Low value will result in a higher sensitivity during the recalibration but with less noise filtering.
|
||||
- A High value will result in a lower sensitivity during the recalibration but with more noise filtering.
|
||||
*/
|
||||
#define TSLPRM_DEBOUNCE_CALIB (3)
|
||||
|
||||
/** Error state debounce in samples unit (range=0..63)
|
||||
- A Low value will result in a higher sensitivity to enter in error state.
|
||||
- A High value will result in a lower sensitivity to enter in error state.
|
||||
*/
|
||||
#define TSLPRM_DEBOUNCE_ERROR (3)
|
||||
|
||||
/** @} Common_Parameters_Debounce */
|
||||
|
||||
//==============================================================================
|
||||
// Environment Change System (ECS)
|
||||
//==============================================================================
|
||||
|
||||
/** @defgroup Common_Parameters_ECS 10 - ECS
|
||||
* @{ */
|
||||
|
||||
/** Environment Change System Slow K factor (range=0..255)
|
||||
- The higher value is K, the faster is the response time.
|
||||
*/
|
||||
#define TSLPRM_ECS_K_SLOW (5)
|
||||
|
||||
/** Environment Change System Fast K factor (range=0..255)
|
||||
- The higher value is K, the faster is the response time.
|
||||
*/
|
||||
#define TSLPRM_ECS_K_FAST (40)
|
||||
|
||||
/** Environment Change System delay in msec (range=0..5000)
|
||||
- The ECS will be started after this delay and when all sensors are in Release state.
|
||||
*/
|
||||
#define TSLPRM_ECS_DELAY (500)
|
||||
|
||||
/** @} Common_Parameters_ECS */
|
||||
|
||||
//==============================================================================
|
||||
// Detection Time Out (DTO)
|
||||
//==============================================================================
|
||||
|
||||
/** @defgroup Common_Parameters_DTO 11 - DTO
|
||||
* @{ */
|
||||
|
||||
/** Detection Time Out delay in seconds (range=0..63)
|
||||
- Value 0: DTO processing not compiled in the code (to gain size if not used).
|
||||
- Value 1: Default time out infinite.
|
||||
- Value between 2 and 63: Default time out between value n-1 and n.
|
||||
- Examples:
|
||||
- With a DTO equal to 2, the time out is between 1s and 2s.
|
||||
- With a DTO equal to 63, the time out is between 62s and 63s.
|
||||
|
||||
@note The DTO can be changed in run-time by the application only if the
|
||||
default value is between 1 and 63.
|
||||
*/
|
||||
#define TSLPRM_DTO (5)
|
||||
|
||||
/** @} Common_Parameters_DTO */
|
||||
|
||||
//==============================================================================
|
||||
// Detection Exclusion System (DXS)
|
||||
//==============================================================================
|
||||
|
||||
/** @defgroup Common_Parameters_DXS 12 - DXS
|
||||
* @{ */
|
||||
|
||||
/** Detection Exclusion System (0=No, 1=Yes)
|
||||
*/
|
||||
#define TSLPRM_USE_DXS (1)
|
||||
|
||||
/** @} Common_Parameters_DXS */
|
||||
|
||||
//==============================================================================
|
||||
// Miscellaneous parameters
|
||||
//==============================================================================
|
||||
|
||||
/** @defgroup Common_Parameters_Misc 13 - Miscellaneous
|
||||
* @{ */
|
||||
|
||||
/** Timing tick frequency in Hz (range=125, 250, 500, 1000, 2000)
|
||||
- Result to a timing interrupt respectively every 8ms, 4ms, 2ms, 1ms, 0.5ms
|
||||
*/
|
||||
#define TSLPRM_TICK_FREQ (1000)
|
||||
|
||||
/** @} Common_Parameters_Misc */
|
||||
|
||||
/** @} Common_Parameters */
|
||||
|
||||
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
//++++++++++++++++++++++++++++++ MCU PARAMETERS ++++++++++++++++++++++++++++++++
|
||||
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
|
||||
// DO NOT MODIFY THE LINES BELOW!!!
|
||||
#define STM8TL53C4 (0)
|
||||
#define STM8TL53G4 (1)
|
||||
#define STM8TL53F4 (2)
|
||||
#define STM8TL52G4 (3)
|
||||
#define STM8TL52F4 (4)
|
||||
|
||||
/** @defgroup STM8TL5x_Parameters STM8TL5x Parameters
|
||||
* @{ */
|
||||
|
||||
//==============================================================================
|
||||
// Device selection
|
||||
//==============================================================================
|
||||
|
||||
/** @defgroup STM8TL5x_Parameters_Device_Selection 01 - Device Selection
|
||||
* @{ */
|
||||
|
||||
/** STM8TL5x device selection (range=0..4)
|
||||
- Select a MCU in the above list
|
||||
*/
|
||||
#define TSLPRM_MCU STM8TL53C4
|
||||
|
||||
/** @} STM8TL5x_Parameters_Device_Selection */
|
||||
|
||||
//==============================================================================
|
||||
// Reference adjustment
|
||||
//==============================================================================
|
||||
|
||||
/** @defgroup STM8TL5x_Parameters_Reference_Adjustment 02 - Reference adjustment
|
||||
* @{ */
|
||||
|
||||
/** Used to calibrate the EPCC to get the Reference closed to this value (range=100..2000)
|
||||
- The range values are recommended values.
|
||||
- The higher the Reference, the higher the sensitivity
|
||||
*/
|
||||
#define TSLPRM_KEY_TARGET_REFERENCE (500)
|
||||
|
||||
/** Used to calibrate the EPCC (range=1..TSLPRM_KEY_TARGET_REFERENCE)
|
||||
*/
|
||||
#define TSLPRM_KEY_TARGET_REFERENCE_ERROR (25)
|
||||
|
||||
/** Number of iteration after the dichotomy to fine tune the EPCC value (range=3..5)
|
||||
*/
|
||||
#define TSLPRM_PXS_EPCC_FINE_TUNING_ITERATION (3)
|
||||
|
||||
/** Used to calibrate the CS (range=1,2,4,8)
|
||||
*/
|
||||
#define TSLPRM_KEY_TARGET_ATTENUATION (4)
|
||||
|
||||
/** Below (TSLPRM_KEY_TARGET_REFERENCE - TSLPRM_TOUCHKEY_REFERENCE_RANGE) the EPCC is updated for the TKeys (range=1..TSLPRM_KEY_TARGET_REFERENCE)
|
||||
*/
|
||||
#define TSLPRM_TOUCHKEY_REFERENCE_RANGE (75)
|
||||
|
||||
/** Below (TSLPRM_KEY_TARGET_REFERENCE - TSLPRM_LINROT_REFERENCE_RANGE) the EPCC is updated for the Linear/Rotary (range=1..TSLPRM_KEY_TARGET_REFERENCE)
|
||||
*/
|
||||
#define TSLPRM_LINROT_REFERENCE_RANGE (75)
|
||||
|
||||
/** @} STM8TL5x_Parameters_Reference_Adjustment */
|
||||
|
||||
//==============================================================================
|
||||
// PXS Clock
|
||||
//==============================================================================
|
||||
|
||||
/** @defgroup STM8TL5x_Parameters_PXS_Clock 03 - PXS Clock
|
||||
- These parameters define the acquisition clock settings.
|
||||
* @{ */
|
||||
|
||||
/** Acquisition frequency (values are 16000, 8000, 4000, 2000, 1000, 500, 250 or 125)
|
||||
*/
|
||||
#define TSLPRM_PXS_HSI (16000)
|
||||
|
||||
/** Up phase length (range=1..7)
|
||||
*/
|
||||
#define TSLPRM_PXS_UP_LENGTH (1)
|
||||
|
||||
/** Pass phase length (range=1..7)
|
||||
*/
|
||||
#define TSLPRM_PXS_PASS_LENGTH (1)
|
||||
|
||||
/** @} STM8TL5x_Parameters_PXS_Clock */
|
||||
|
||||
//==============================================================================
|
||||
// PXS Synchro
|
||||
//==============================================================================
|
||||
|
||||
/** @defgroup STM8TL5x_Parameters_PXS_Synchro 04 - PXS Synchro
|
||||
* @{ */
|
||||
|
||||
/** Acquisition synchronized with SYNCHRO pin (0=No, 1=Yes)
|
||||
*/
|
||||
#define TSLPRM_PXS_SYNCHRONIZE (1)
|
||||
|
||||
/** Synchronization edge (0=Fall, 1=Rise)
|
||||
*/
|
||||
#define TSLPRM_PXS_SYNCHRO_EDGE (1)
|
||||
|
||||
/** @} STM8TL5x_Parameters_PXS_Synchro */
|
||||
|
||||
//==============================================================================
|
||||
// PXS Miscellaneous
|
||||
//==============================================================================
|
||||
|
||||
/** @defgroup STM8TL5x_Parameters_PXS_Miscellaneous 05 - PXS Miscellaneous
|
||||
* @{ */
|
||||
|
||||
/** Low power mode between acquisition (0=No, 1=Yes)
|
||||
*/
|
||||
#define TSLPRM_PXS_LOW_POWER_MODE (1)
|
||||
|
||||
/** RF detection (0=No, 1=Yes)
|
||||
*/
|
||||
#define TSLPRM_PXS_RF_DETECTION (1)
|
||||
|
||||
/** Transmitter inactive state (0=Grounded, 1=Floating)
|
||||
*/
|
||||
#define TSLPRM_PXS_INACTIVE_TX (1)
|
||||
|
||||
/** Receiver inactive state (0=Grounded, 1=Floating)
|
||||
*/
|
||||
#define TSLPRM_PXS_INACTIVE_RX (1)
|
||||
|
||||
/** Charge/Discharge cycle behaviour after VTHR is reached (0=stop, 1=continue)
|
||||
*/
|
||||
#define TSLPRM_PXS_RX_COUPLING (1)
|
||||
|
||||
/** Stabilization time (values are LONG_STAB, MEDIUM_STAB, SHORT_STAB)
|
||||
*/
|
||||
#define TSLPRM_PXS_STAB LONG_STAB
|
||||
|
||||
/** Bias (values are HIGH_BIAS, MEDIUM_BIAS, LOW_BIAS, VERY_LOW_BIAS)
|
||||
*/
|
||||
#define TSLPRM_PXS_BIAS HIGH_BIAS
|
||||
|
||||
/** Index maximum of Rx channels ("N" of RxN)
|
||||
- This value must not exceed 9 with STM8TL53C4 and 7 with STM8TL53G4
|
||||
*/
|
||||
#define TSLPRM_HIGH_CHANNEL_NB (9)
|
||||
|
||||
/** @} STM8TL5x_Parameters_PXS_Miscellaneous */
|
||||
|
||||
/** @} STM8TL5x_Parameters */
|
||||
|
||||
// DO NOT REMOVE !!!
|
||||
#include "tsl_check_config.h"
|
||||
|
||||
#endif /* __TSL_CONF_STM8TL5X_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,52 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file tsl.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.3.2
|
||||
* @date 22-January-2013
|
||||
* @brief This file contains external declarations of the tsl.c file.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __TSL_H
|
||||
#define __TSL_H
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "tsl_acq.h"
|
||||
#include "tsl_time.h"
|
||||
#include "tsl_touchkey.h"
|
||||
#include "tsl_linrot.h"
|
||||
#include "tsl_object.h"
|
||||
#include "tsl_dxs.h"
|
||||
#include "tsl_ecs.h"
|
||||
#include "tsl_filter.h"
|
||||
#include "tsl_globals.h"
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
/* Exported variables --------------------------------------------------------*/
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
TSL_Status_enum_T TSL_Init(CONST TSL_Bank_T *bank);
|
||||
|
||||
#endif /* __TSL_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,112 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file tsl_acq.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.3.2
|
||||
* @date 22-January-2013
|
||||
* @brief This file contains external declarations of the tsl_acq.c file.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __TSL_ACQ_H
|
||||
#define __TSL_ACQ_H
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
|
||||
// Check the device selection.
|
||||
// It must be defined in the toolchain compiler preprocessor.
|
||||
// The same name as in the Standard Peripheral Library is used.
|
||||
#if !defined(STM8TL5X) &&\
|
||||
!defined(STM32F0XX) &&\
|
||||
!defined(STM32F30X) &&\
|
||||
!defined(STM32F37X) &&\
|
||||
!defined(STM32L1XX_HD) &&\
|
||||
!defined(STM32L1XX_MD) &&\
|
||||
!defined(STM32L1XX_MDP)
|
||||
#error "Device family not declared in the toolchain compiler preprocessor."
|
||||
#endif
|
||||
|
||||
#if defined(STM8TL5X)
|
||||
#include "tsl_acq_stm8tl5x.h"
|
||||
#endif
|
||||
|
||||
#if defined(STM32F0XX)
|
||||
#include "tsl_acq_stm32f0xx.h"
|
||||
#endif
|
||||
|
||||
#if defined(STM32F30X) || defined(STM32F37X)
|
||||
#include "tsl_acq_stm32f3xx.h"
|
||||
#endif
|
||||
|
||||
#if defined(STM32L1XX_HD)
|
||||
#if defined(TSLPRM_STM32L1XX_SW_ACQ)
|
||||
#include "tsl_acq_stm32l1xx_sw.h" // Software acquisition
|
||||
#else
|
||||
#include "tsl_acq_stm32l1xx_hw.h" // Hardware acquisition with Timers (default)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if defined(STM32L1XX_MD)
|
||||
#include "tsl_acq_stm32l1xx_sw.h" // Software acquisition only
|
||||
#endif
|
||||
|
||||
#if defined(STM32L1XX_MDP)
|
||||
#if defined(TSLPRM_STM32L1XX_SW_ACQ)
|
||||
#include "tsl_acq_stm32l1xx_sw.h" // Software acquisition
|
||||
#else
|
||||
#include "tsl_acq_stm32l1xx_hw.h" // Hardware acquisition with Timers (default)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* Defines -------------------------------------------------------------------*/
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
// Filter functions
|
||||
typedef TSL_tMeas_T(* TSL_pFuncMeasFilter_T)(TSL_tMeas_T, TSL_tMeas_T); /**< Pointer to the Measure filter function */
|
||||
typedef TSL_tDelta_T(* TSL_pFuncDeltaFilter_T)(TSL_tDelta_T); /**< Pointer to the Delta filter function */
|
||||
|
||||
/** Structure containing all data of a Zone.
|
||||
* A Zone is a set of Banks.
|
||||
* Variables of this structure type can be placed in RAM or ROM.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
// Common to all acquisitions
|
||||
TSL_tIndex_T *BankIndex; /**< Pointer to an array of bank indexes */
|
||||
TSL_pFuncDeltaFilter_T *dFilter; /**< Pointer to a Delta filter function */
|
||||
TSL_tNb_T NbBanks; /**< Number of banks in the zone */
|
||||
}
|
||||
TSL_Zone_T;
|
||||
|
||||
/* Exported variables --------------------------------------------------------*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
TSL_Status_enum_T TSL_acq_ZoneConfig(CONST TSL_Zone_T *zone, TSL_tIndex_T idx_bk);
|
||||
TSL_Status_enum_T TSL_acq_BankGetResult(TSL_tIndex_T idx_bk, TSL_pFuncMeasFilter_T mfilter, TSL_pFuncDeltaFilter_T dfilter);
|
||||
TSL_Status_enum_T TSL_acq_BankCalibrate(TSL_tIndex_T bank);
|
||||
void TSL_acq_BankClearData(TSL_tIndex_T bank);
|
||||
|
||||
#endif /* __TSL_ACQ_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,189 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file tsl_acq_stm32f0xx.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.3.2
|
||||
* @date 22-January-2013
|
||||
* @brief This file contains all functions prototypes that manage the TSC
|
||||
* acquisition on STM32F0x products.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __TSL_ACQ_STM32F0XX_H
|
||||
#define __TSL_ACQ_STM32F0XX_H
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx.h"
|
||||
#include "tsl_conf_stm32f0xx.h"
|
||||
#include "tsl_types.h"
|
||||
|
||||
/* Defines -------------------------------------------------------------------*/
|
||||
|
||||
#ifndef CONST
|
||||
#define CONST const
|
||||
#endif
|
||||
|
||||
// SysTick enable/disable interrupt macros
|
||||
#define enableInterrupts() {SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk;}
|
||||
#define disableInterrupts() {SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;}
|
||||
|
||||
#define TSL_NB_GROUPS (6) // Only 6 groups on STM32F0xx
|
||||
|
||||
#define TSL_GROUP1 (0x01)
|
||||
#define TSL_GROUP2 (0x02)
|
||||
#define TSL_GROUP3 (0x04)
|
||||
#define TSL_GROUP4 (0x08)
|
||||
#define TSL_GROUP5 (0x10)
|
||||
#define TSL_GROUP6 (0x20)
|
||||
|
||||
// GxIOy masks
|
||||
#define TSL_GROUP1_IO1 (0x00000001)
|
||||
#define TSL_GROUP1_IO2 (0x00000002)
|
||||
#define TSL_GROUP1_IO3 (0x00000004)
|
||||
#define TSL_GROUP1_IO4 (0x00000008)
|
||||
#define TSL_GROUP2_IO1 (0x00000010)
|
||||
#define TSL_GROUP2_IO2 (0x00000020)
|
||||
#define TSL_GROUP2_IO3 (0x00000040)
|
||||
#define TSL_GROUP2_IO4 (0x00000080)
|
||||
#define TSL_GROUP3_IO1 (0x00000100)
|
||||
#define TSL_GROUP3_IO2 (0x00000200)
|
||||
#define TSL_GROUP3_IO3 (0x00000400)
|
||||
#define TSL_GROUP3_IO4 (0x00000800)
|
||||
#define TSL_GROUP4_IO1 (0x00001000)
|
||||
#define TSL_GROUP4_IO2 (0x00002000)
|
||||
#define TSL_GROUP4_IO3 (0x00004000)
|
||||
#define TSL_GROUP4_IO4 (0x00008000)
|
||||
#define TSL_GROUP5_IO1 (0x00010000)
|
||||
#define TSL_GROUP5_IO2 (0x00020000)
|
||||
#define TSL_GROUP5_IO3 (0x00040000)
|
||||
#define TSL_GROUP5_IO4 (0x00080000)
|
||||
#define TSL_GROUP6_IO1 (0x00100000)
|
||||
#define TSL_GROUP6_IO2 (0x00200000)
|
||||
#define TSL_GROUP6_IO3 (0x00400000)
|
||||
#define TSL_GROUP6_IO4 (0x00800000)
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
// For all devices/acquisitions
|
||||
|
||||
typedef uint16_t TSL_tMeas_T; /**< Measurement */
|
||||
typedef uint16_t TSL_tRef_T; /**< Reference */
|
||||
typedef int16_t TSL_tDelta_T; /**< Delta */
|
||||
|
||||
typedef uint8_t TSL_tIndexSrc_T; /**< Channel source index */
|
||||
typedef uint16_t TSL_tIndexDest_T; /**< Channel destination index */
|
||||
|
||||
typedef uint8_t TSL_tRefRest_T; /**< Reference Rest (ECS) */
|
||||
typedef uint16_t TSL_tKCoeff_T; /**< K coefficient (ECS) */
|
||||
|
||||
typedef uint8_t TSL_tIndex_T; /**< Generic index */
|
||||
typedef uint16_t TSL_tNb_T; /**< Generic number */
|
||||
typedef uint8_t TSL_tCounter_T; /**< Generic counter used for debounce */
|
||||
|
||||
typedef uint8_t TSL_tThreshold_T; /**< Delta threshold */
|
||||
|
||||
typedef int16_t TSL_tsignPosition_T; /**< Linear and Rotary sensors position */
|
||||
typedef uint8_t TSL_tPosition_T; /**< Linear and Rotary sensors position */
|
||||
|
||||
typedef uint16_t TSL_tTick_ms_T; /**< Time in ms */
|
||||
typedef uint8_t TSL_tTick_sec_T; /**< Time in sec */
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
// Channel
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
/** Channel destination index
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
TSL_tIndexDest_T IdxDest; /**< Index in the Channel data array */
|
||||
} TSL_ChannelDest_T;
|
||||
|
||||
/** Channel Source and Configuration
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
TSL_tIndexSrc_T IdxSrc; /**< Index of TSC->IOGXCR[] registers */
|
||||
// For stm32f0x TSC acquisition only
|
||||
uint32_t msk_IOCCR_channel; /**< Mask of the Channel IO (electrodes ONLY) */
|
||||
uint32_t msk_IOGCSR_group; /**< Mask of the Group used (electrodes ONLY) */
|
||||
} TSL_ChannelSrc_T;
|
||||
|
||||
/** Channel flags
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
unsigned int DataReady : 1; /**< To identify a new measurement (TSL_DataReady_enum_T) */
|
||||
unsigned int AcqStatus : 2; /**< Acquisition status (TSL_AcqStatus_enum_T) */
|
||||
unsigned int ObjStatus : 2; /**< Object status (TSL_ObjStatus_enum_T) */
|
||||
} TSL_ChannelFlags_T;
|
||||
|
||||
/** Channel Data
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
TSL_ChannelFlags_T Flags; /**< Flags */
|
||||
TSL_tRef_T Ref; /**< Reference */
|
||||
TSL_tRefRest_T RefRest; /**< Reference rest for ECS */
|
||||
TSL_tDelta_T Delta; /**< Delta */
|
||||
#if TSLPRM_USE_MEAS > 0
|
||||
TSL_tMeas_T Meas; /**< Hold the last acquisition measure */
|
||||
#endif
|
||||
} TSL_ChannelData_T;
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
// Bank
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
/** Bank
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
// Common to all acquisitions
|
||||
CONST TSL_ChannelSrc_T *p_chSrc; /**< Pointer to the Channel Source and Configuration */
|
||||
CONST TSL_ChannelDest_T *p_chDest; /**< Pointer to the Channel Destination */
|
||||
TSL_ChannelData_T *p_chData; /**< Pointer to the Channel Data */
|
||||
TSL_tNb_T NbChannels; /**< Number of channels in the bank */
|
||||
// For STM32F0x TSC acquisition only
|
||||
uint32_t msk_IOCCR_channels; /**< Mask of all channel IOs (electrodes AND shields) */
|
||||
uint32_t msk_IOGCSR_groups; /**< Mask of all groups used (electrodes ONLY) */
|
||||
} TSL_Bank_T;
|
||||
|
||||
/* Exported variables --------------------------------------------------------*/
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
|
||||
TSL_Status_enum_T TSL_acq_Init(void);
|
||||
void TSL_acq_InitGPIOs(void);
|
||||
TSL_Status_enum_T TSL_acq_BankConfig(TSL_tIndex_T idx_bk);
|
||||
TSL_Bool_enum_T TSL_acq_UseFilter(TSL_ChannelData_T *pCh);
|
||||
TSL_Bool_enum_T TSL_acq_TestReferenceOutOfRange(TSL_ChannelData_T *pCh);
|
||||
TSL_Bool_enum_T TSL_acq_TestFirstReferenceIsValid(TSL_ChannelData_T *pCh, TSL_tMeas_T new_meas);
|
||||
void TSL_acq_BankStartAcq(void);
|
||||
TSL_Status_enum_T TSL_acq_BankWaitEOC(void);
|
||||
TSL_AcqStatus_enum_T TSL_acq_CheckNoise(void);
|
||||
TSL_tMeas_T TSL_acq_GetMeas(TSL_tIndexSrc_T index);
|
||||
TSL_tDelta_T TSL_acq_ComputeDelta(TSL_tRef_T ref, TSL_tMeas_T meas);
|
||||
TSL_tMeas_T TSL_acq_ComputeMeas(TSL_tRef_T ref, TSL_tDelta_T delta);
|
||||
|
||||
#endif /* __TSL_ACQ_STM32F0XX_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,204 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file tsl_acq_stm32f3xx.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.3.2
|
||||
* @date 22-January-2013
|
||||
* @brief This file contains all functions prototypes that manage the TSC
|
||||
* acquisition on STM32F3xx products.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __TSL_ACQ_STM32F3XX_H
|
||||
#define __TSL_ACQ_STM32F3XX_H
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#if defined(STM32F30X)
|
||||
#include "stm32f30x.h"
|
||||
#endif
|
||||
#if defined(STM32F37X)
|
||||
#include "stm32f37x.h"
|
||||
#endif
|
||||
#include "tsl_conf_stm32f3xx.h"
|
||||
#include "tsl_types.h"
|
||||
|
||||
/* Defines -------------------------------------------------------------------*/
|
||||
|
||||
#ifndef CONST
|
||||
#define CONST const
|
||||
#endif
|
||||
|
||||
// SysTick enable/disable interrupt macros
|
||||
#define enableInterrupts() {SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk;}
|
||||
#define disableInterrupts() {SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;}
|
||||
|
||||
#define TSL_NB_GROUPS (8) // Number of groups available on STM32F3xx devices
|
||||
|
||||
#define TSL_GROUP1 (0x01)
|
||||
#define TSL_GROUP2 (0x02)
|
||||
#define TSL_GROUP3 (0x04)
|
||||
#define TSL_GROUP4 (0x08)
|
||||
#define TSL_GROUP5 (0x10)
|
||||
#define TSL_GROUP6 (0x20)
|
||||
#define TSL_GROUP7 (0x40)
|
||||
#define TSL_GROUP8 (0x80)
|
||||
|
||||
// GxIOy masks
|
||||
#define TSL_GROUP1_IO1 (0x00000001)
|
||||
#define TSL_GROUP1_IO2 (0x00000002)
|
||||
#define TSL_GROUP1_IO3 (0x00000004)
|
||||
#define TSL_GROUP1_IO4 (0x00000008)
|
||||
#define TSL_GROUP2_IO1 (0x00000010)
|
||||
#define TSL_GROUP2_IO2 (0x00000020)
|
||||
#define TSL_GROUP2_IO3 (0x00000040)
|
||||
#define TSL_GROUP2_IO4 (0x00000080)
|
||||
#define TSL_GROUP3_IO1 (0x00000100)
|
||||
#define TSL_GROUP3_IO2 (0x00000200)
|
||||
#define TSL_GROUP3_IO3 (0x00000400)
|
||||
#define TSL_GROUP3_IO4 (0x00000800)
|
||||
#define TSL_GROUP4_IO1 (0x00001000)
|
||||
#define TSL_GROUP4_IO2 (0x00002000)
|
||||
#define TSL_GROUP4_IO3 (0x00004000)
|
||||
#define TSL_GROUP4_IO4 (0x00008000)
|
||||
#define TSL_GROUP5_IO1 (0x00010000)
|
||||
#define TSL_GROUP5_IO2 (0x00020000)
|
||||
#define TSL_GROUP5_IO3 (0x00040000)
|
||||
#define TSL_GROUP5_IO4 (0x00080000)
|
||||
#define TSL_GROUP6_IO1 (0x00100000)
|
||||
#define TSL_GROUP6_IO2 (0x00200000)
|
||||
#define TSL_GROUP6_IO3 (0x00400000)
|
||||
#define TSL_GROUP6_IO4 (0x00800000)
|
||||
#define TSL_GROUP7_IO1 (0x01000000)
|
||||
#define TSL_GROUP7_IO2 (0x02000000)
|
||||
#define TSL_GROUP7_IO3 (0x04000000)
|
||||
#define TSL_GROUP7_IO4 (0x08000000)
|
||||
#define TSL_GROUP8_IO1 (0x10000000)
|
||||
#define TSL_GROUP8_IO2 (0x20000000)
|
||||
#define TSL_GROUP8_IO3 (0x40000000)
|
||||
#define TSL_GROUP8_IO4 (0x80000000)
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
// For all devices/acquisitions
|
||||
|
||||
typedef uint16_t TSL_tMeas_T; /**< Measurement */
|
||||
typedef uint16_t TSL_tRef_T; /**< Reference */
|
||||
typedef int16_t TSL_tDelta_T; /**< Delta */
|
||||
|
||||
typedef uint8_t TSL_tIndexSrc_T; /**< Channel source index */
|
||||
typedef uint16_t TSL_tIndexDest_T; /**< Channel destination index */
|
||||
|
||||
typedef uint8_t TSL_tRefRest_T; /**< Reference Rest (ECS) */
|
||||
typedef uint16_t TSL_tKCoeff_T; /**< K coefficient (ECS) */
|
||||
|
||||
typedef uint8_t TSL_tIndex_T; /**< Generic index */
|
||||
typedef uint16_t TSL_tNb_T; /**< Generic number */
|
||||
typedef uint8_t TSL_tCounter_T; /**< Generic counter used for debounce */
|
||||
|
||||
typedef uint8_t TSL_tThreshold_T; /**< Delta threshold */
|
||||
|
||||
typedef int16_t TSL_tsignPosition_T; /**< Linear and Rotary sensors position */
|
||||
typedef uint8_t TSL_tPosition_T; /**< Linear and Rotary sensors position */
|
||||
|
||||
typedef uint16_t TSL_tTick_ms_T; /**< Time in ms */
|
||||
typedef uint8_t TSL_tTick_sec_T; /**< Time in sec */
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
// Channel
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
/** Channel destination index
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
TSL_tIndexDest_T IdxDest; /**< Index in the Channel data array */
|
||||
} TSL_ChannelDest_T;
|
||||
|
||||
/** Channel Source and Configuration
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
TSL_tIndexSrc_T IdxSrc; /**< Index of TSC->IOGXCR[] registers */
|
||||
// For STM32F3xx TSC acquisition only
|
||||
uint32_t msk_IOCCR_channel; /**< Mask of the Channel IO (electrodes ONLY) */
|
||||
uint32_t msk_IOGCSR_group; /**< Mask of the Group used (electrodes ONLY) */
|
||||
} TSL_ChannelSrc_T;
|
||||
|
||||
/** Channel flags
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
unsigned int DataReady : 1; /**< To identify a new measurement (TSL_DataReady_enum_T) */
|
||||
unsigned int AcqStatus : 2; /**< Acquisition status (TSL_AcqStatus_enum_T) */
|
||||
unsigned int ObjStatus : 2; /**< Object status (TSL_ObjStatus_enum_T) */
|
||||
} TSL_ChannelFlags_T;
|
||||
|
||||
/** Channel Data
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
TSL_ChannelFlags_T Flags; /**< Flags */
|
||||
TSL_tRef_T Ref; /**< Reference */
|
||||
TSL_tRefRest_T RefRest; /**< Reference rest for ECS */
|
||||
TSL_tDelta_T Delta; /**< Delta */
|
||||
#if TSLPRM_USE_MEAS > 0
|
||||
TSL_tMeas_T Meas; /**< Hold the last acquisition measure */
|
||||
#endif
|
||||
} TSL_ChannelData_T;
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
// Bank
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
/** Bank
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
// Common to all acquisitions
|
||||
CONST TSL_ChannelSrc_T *p_chSrc; /**< Pointer to the Channel Source and Configuration */
|
||||
CONST TSL_ChannelDest_T *p_chDest; /**< Pointer to the Channel Destination */
|
||||
TSL_ChannelData_T *p_chData; /**< Pointer to the Channel Data */
|
||||
TSL_tNb_T NbChannels; /**< Number of channels in the bank */
|
||||
// For STM32F3xx TSC acquisition only
|
||||
uint32_t msk_IOCCR_channels; /**< Mask of all channel IOs (electrodes AND shields) */
|
||||
uint32_t msk_IOGCSR_groups; /**< Mask of all groups used (electrodes ONLY) */
|
||||
} TSL_Bank_T;
|
||||
|
||||
/* Exported variables --------------------------------------------------------*/
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
|
||||
TSL_Status_enum_T TSL_acq_Init(void);
|
||||
void TSL_acq_InitGPIOs(void);
|
||||
TSL_Status_enum_T TSL_acq_BankConfig(TSL_tIndex_T idx_bk);
|
||||
TSL_Bool_enum_T TSL_acq_UseFilter(TSL_ChannelData_T *pCh);
|
||||
TSL_Bool_enum_T TSL_acq_TestReferenceOutOfRange(TSL_ChannelData_T *pCh);
|
||||
TSL_Bool_enum_T TSL_acq_TestFirstReferenceIsValid(TSL_ChannelData_T *pCh, TSL_tMeas_T new_meas);
|
||||
void TSL_acq_BankStartAcq(void);
|
||||
TSL_Status_enum_T TSL_acq_BankWaitEOC(void);
|
||||
TSL_AcqStatus_enum_T TSL_acq_CheckNoise(void);
|
||||
TSL_tMeas_T TSL_acq_GetMeas(TSL_tIndexSrc_T index);
|
||||
TSL_tDelta_T TSL_acq_ComputeDelta(TSL_tRef_T ref, TSL_tMeas_T meas);
|
||||
TSL_tMeas_T TSL_acq_ComputeMeas(TSL_tRef_T ref, TSL_tDelta_T delta);
|
||||
|
||||
#endif /* __TSL_ACQ_STM32F3XX_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,317 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file tsl_acq_stm32l1xx_hw.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.3.2
|
||||
* @date 22-January-2013
|
||||
* @brief This file contains external declarations of the tsl_acq_stm32l1xx_hw.c file.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __TSL_ACQ_STM32L1XX_HW_H
|
||||
#define __TSL_ACQ_STM32L1XX_HW_H
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32l1xx.h"
|
||||
#include "tsl_conf_stm32l1xx.h"
|
||||
#include "tsl_types.h"
|
||||
|
||||
/* Defines -------------------------------------------------------------------*/
|
||||
|
||||
#ifndef CONST
|
||||
#define CONST const
|
||||
#endif
|
||||
|
||||
// SysTick enable/disable interrupt macros
|
||||
#define enableInterrupts() {SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk;}
|
||||
#define disableInterrupts() {SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;}
|
||||
|
||||
/** Groups list
|
||||
*/
|
||||
enum
|
||||
{
|
||||
GR1,
|
||||
GR2,
|
||||
GR3,
|
||||
GR4,
|
||||
GR5,
|
||||
GR6,
|
||||
GR7,
|
||||
GR8,
|
||||
GR9,
|
||||
GR10,
|
||||
GR11
|
||||
};
|
||||
|
||||
/** GPIOs list
|
||||
High significant nibble for the IO port (GPIOA:0,...,GPIOG:6)
|
||||
Low significant nibble for the IO number (pin0:0,...,pin15:F)
|
||||
*/
|
||||
enum
|
||||
{
|
||||
PA0 = 0x00, /**< TSL_GROUP1_IO1 */
|
||||
PA1 = 0x01,
|
||||
PA2 = 0x02,
|
||||
PA3 = 0x03,
|
||||
PA6 = 0x06, /**< TSL_GROUP2_IO1 */
|
||||
PA7 = 0x07,
|
||||
PA8 = 0x08,
|
||||
PA9 = 0x09,
|
||||
PA10 = 0x0A,
|
||||
PA13 = 0x0D, /**< TSL_GROUP5_IO1 */
|
||||
PA14 = 0x0E,
|
||||
PA15 = 0x0F,
|
||||
PB0 = 0x10, /**< TSL_GROUP3_IO1 */
|
||||
PB1 = 0x11,
|
||||
PB2 = 0x12,
|
||||
PB4 = 0x14, /**< TSL_GROUP6_IO1 */
|
||||
PB5 = 0x15,
|
||||
PB6 = 0x16,
|
||||
PB7 = 0x17,
|
||||
PB12 = 0x1C, /**< TSL_GROUP7_IO1 */
|
||||
PB13 = 0x1D,
|
||||
PB14 = 0x1E,
|
||||
PB15 = 0x1F,
|
||||
PC0 = 0x20, /**< TSL_GROUP8_IO1 */
|
||||
PC1 = 0x21,
|
||||
PC2 = 0x22,
|
||||
PC3 = 0x23,
|
||||
PC4 = 0x24,
|
||||
PC5 = 0x25,
|
||||
PC6 = 0x26,
|
||||
PC7 = 0x27,
|
||||
PC8 = 0x28,
|
||||
PC9 = 0x29,
|
||||
PF6 = 0x56, /**< TSL_GROUP11_IO1 */
|
||||
PF7 = 0x57,
|
||||
PF8 = 0x58,
|
||||
PF9 = 0x59,
|
||||
PF10 = 0x5A,
|
||||
PF11 = 0x5B,
|
||||
PF12 = 0x5C,
|
||||
PF13 = 0x5D,
|
||||
PF14 = 0x5E,
|
||||
PF15 = 0x5F,
|
||||
PG0 = 0x60, /**< TSL_GROUP2_IO4 */
|
||||
PG1 = 0x61,
|
||||
PG2 = 0x62,
|
||||
PG3 = 0x63,
|
||||
PG4 = 0x64
|
||||
};
|
||||
|
||||
/** GPIOs list:
|
||||
High significant nibble for the IO port (GPIOA:0,...,GPIOG:6)
|
||||
Low significant nibble for the IO number (pin0:0,...,pin15:F)
|
||||
*/
|
||||
enum
|
||||
{
|
||||
TSL_GROUP1_IO1 = 0x00, /**< PA0 */
|
||||
TSL_GROUP1_IO2 = 0x01,
|
||||
TSL_GROUP1_IO3 = 0x02,
|
||||
TSL_GROUP1_IO4 = 0x03,
|
||||
TSL_GROUP2_IO1 = 0x06, /**< PA6 */
|
||||
TSL_GROUP2_IO2 = 0x07,
|
||||
TSL_GROUP4_IO1 = 0x08,
|
||||
TSL_GROUP4_IO2 = 0x09,
|
||||
TSL_GROUP4_IO3 = 0x0A,
|
||||
TSL_GROUP5_IO1 = 0x0D, /**< PA13 */
|
||||
TSL_GROUP5_IO2 = 0x0E,
|
||||
TSL_GROUP5_IO3 = 0x0F,
|
||||
TSL_GROUP3_IO1 = 0x10, /**< PB0 */
|
||||
TSL_GROUP3_IO2 = 0x11,
|
||||
TSL_GROUP3_IO3 = 0x12,
|
||||
TSL_GROUP6_IO1 = 0x14, /**< PB4 */
|
||||
TSL_GROUP6_IO2 = 0x15,
|
||||
TSL_GROUP6_IO3 = 0x16,
|
||||
TSL_GROUP6_IO4 = 0x17,
|
||||
TSL_GROUP7_IO1 = 0x1C, /**< PB12 */
|
||||
TSL_GROUP7_IO2 = 0x1D,
|
||||
TSL_GROUP7_IO3 = 0x1E,
|
||||
TSL_GROUP7_IO4 = 0x1F,
|
||||
TSL_GROUP8_IO1 = 0x20, /**< PC0 */
|
||||
TSL_GROUP8_IO2 = 0x21,
|
||||
TSL_GROUP8_IO3 = 0x22,
|
||||
TSL_GROUP8_IO4 = 0x23,
|
||||
TSL_GROUP9_IO1 = 0x24,
|
||||
TSL_GROUP9_IO2 = 0x25,
|
||||
TSL_GROUP10_IO1 = 0x26,
|
||||
TSL_GROUP10_IO2 = 0x27,
|
||||
TSL_GROUP10_IO3 = 0x28,
|
||||
TSL_GROUP10_IO4 = 0x29,
|
||||
TSL_GROUP11_IO1 = 0x56, /**< PF6 */
|
||||
TSL_GROUP11_IO2 = 0x57,
|
||||
TSL_GROUP11_IO3 = 0x58,
|
||||
TSL_GROUP11_IO4 = 0x59,
|
||||
TSL_GROUP11_IO5 = 0x5A,
|
||||
TSL_GROUP3_IO4 = 0x5B,
|
||||
TSL_GROUP3_IO5 = 0x5C,
|
||||
TSL_GROUP9_IO3 = 0x5D,
|
||||
TSL_GROUP9_IO4 = 0x5E,
|
||||
TSL_GROUP2_IO3 = 0x5F,
|
||||
TSL_GROUP2_IO4 = 0x60, /**< PG0 */
|
||||
TSL_GROUP2_IO5 = 0x61,
|
||||
TSL_GROUP7_IO5 = 0x62,
|
||||
TSL_GROUP7_IO6 = 0x63,
|
||||
TSL_GROUP7_IO7 = 0x64
|
||||
};
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
// RI
|
||||
__IO uint32_t ICR;
|
||||
__IO uint32_t ASCR1;
|
||||
__IO uint32_t ASCR2;
|
||||
__IO uint32_t HYSCR1;
|
||||
__IO uint32_t HYSCR2;
|
||||
__IO uint32_t HYSCR3;
|
||||
__IO uint32_t HYSCR4;
|
||||
// CP
|
||||
__IO uint32_t ASMR1;
|
||||
__IO uint32_t CMR1;
|
||||
__IO uint32_t CICR1;
|
||||
__IO uint32_t ASMR2;
|
||||
__IO uint32_t CMR2;
|
||||
__IO uint32_t CICR2;
|
||||
__IO uint32_t ASMR3;
|
||||
__IO uint32_t CMR3;
|
||||
__IO uint32_t CICR3;
|
||||
__IO uint32_t ASMR4;
|
||||
__IO uint32_t CMR4;
|
||||
__IO uint32_t CICR4;
|
||||
__IO uint32_t ASMR5;
|
||||
__IO uint32_t CMR5;
|
||||
__IO uint32_t CICR5;
|
||||
} CPRI_TypeDef;
|
||||
|
||||
// For all devices/acquisitions
|
||||
|
||||
typedef uint16_t TSL_tMeas_T; /**< Measurement */
|
||||
typedef uint16_t TSL_tRef_T; /**< Reference */
|
||||
typedef int16_t TSL_tDelta_T; /**< Delta */
|
||||
|
||||
typedef uint8_t TSL_tIndexSrc_T; /**< Channel source index */
|
||||
typedef uint16_t TSL_tIndexDest_T; /**< Channel destination index */
|
||||
|
||||
typedef uint8_t TSL_tRefRest_T; /**< Reference Rest (ECS) */
|
||||
typedef uint16_t TSL_tKCoeff_T; /**< K coefficient (ECS) */
|
||||
|
||||
typedef uint8_t TSL_tIndex_T; /**< Generic index */
|
||||
typedef uint16_t TSL_tNb_T; /**< Generic number */
|
||||
typedef uint8_t TSL_tCounter_T; /**< Generic counter used for debounce */
|
||||
|
||||
typedef uint8_t TSL_tThreshold_T; /**< Delta threshold */
|
||||
|
||||
typedef int16_t TSL_tsignPosition_T; /**< Linear and Rotary sensors position */
|
||||
typedef uint8_t TSL_tPosition_T; /**< Linear and Rotary sensors position */
|
||||
|
||||
typedef uint16_t TSL_tTick_ms_T; /**< Time in ms */
|
||||
typedef uint8_t TSL_tTick_sec_T; /**< Time in sec */
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
// Channel
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
typedef uint8_t TSL_Conf_t;
|
||||
|
||||
/** Channel destination index
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
TSL_tIndex_T IdxDest; /**< Index in the Channel data array */
|
||||
} TSL_ChannelDest_T;
|
||||
|
||||
/** Channel Source and Configuration
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
TSL_tIndex_T IdxSrc; /**< Index of source value */
|
||||
// For stm32l1x acquisition only
|
||||
TSL_Conf_t t_sample; /**< Indicates which GPIO.n is used for the sample */
|
||||
TSL_Conf_t t_channel; /**< Indicates which GPIO.n is used for the channel */
|
||||
} TSL_ChannelSrc_T;
|
||||
|
||||
/** Channel flags
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
unsigned int DataReady : 1; /**< To identify a new measurement (TSL_DataReady_enum_T) */
|
||||
unsigned int AcqStatus : 2; /**< Acquisition status (TSL_AcqStatus_enum_T) */
|
||||
unsigned int ObjStatus : 2; /**< Object status (TSL_ObjStatus_enum_T) */
|
||||
} TSL_ChannelFlags_T;
|
||||
|
||||
/** Channel Data
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
TSL_ChannelFlags_T Flags; /**< Flags */
|
||||
TSL_tRef_T Ref; /**< Reference */
|
||||
TSL_tRefRest_T RefRest; /**< Reference rest for ECS */
|
||||
TSL_tDelta_T Delta; /**< Delta */
|
||||
#if TSLPRM_USE_MEAS > 0
|
||||
TSL_tMeas_T Meas; /**< Hold the last acquisition measure */
|
||||
#endif
|
||||
} TSL_ChannelData_T;
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
// Bank
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
/** Bank
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
// Common to all acquisitions
|
||||
CONST TSL_ChannelSrc_T *p_chSrc; /**< Pointer to the Channel Source and Configuration */
|
||||
CONST TSL_ChannelDest_T *p_chDest; /**< Pointer to the Channel Destination */
|
||||
TSL_ChannelData_T *p_chData; /**< Pointer to the Channel Data */
|
||||
TSL_tNb_T NbChannels; /**< Number of channels in the bank */
|
||||
// For stm32l1x acquisition only
|
||||
TSL_Conf_t shield_sample; /**< Indicates which GPIO.n is used for the shield sample */
|
||||
TSL_Conf_t shield_channel; /**< Indicates which GPIO.n is used for the shield channel */
|
||||
} TSL_Bank_T;
|
||||
|
||||
/* Exported variables --------------------------------------------------------*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
|
||||
#define CPRI_BASE (APB1PERIPH_BASE + 0x7C04)
|
||||
#define CPRI ((CPRI_TypeDef *) CPRI_BASE)
|
||||
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
|
||||
TSL_Status_enum_T TSL_acq_Init(void);
|
||||
TSL_Status_enum_T TSL_acq_BankConfig(TSL_tIndex_T idx_bk);
|
||||
void TSL_acq_BankStartAcq(void);
|
||||
TSL_Status_enum_T TSL_acq_BankWaitEOC(void);
|
||||
void TSL_acq_ProcessIT(void);
|
||||
TSL_tMeas_T TSL_acq_GetMeas(TSL_tIndex_T index);
|
||||
TSL_AcqStatus_enum_T TSL_acq_CheckNoise(void);
|
||||
TSL_Bool_enum_T TSL_acq_UseFilter(TSL_ChannelData_T *pCh);
|
||||
TSL_tDelta_T TSL_acq_ComputeDelta(TSL_tRef_T ref, TSL_tMeas_T meas);
|
||||
TSL_tMeas_T TSL_acq_ComputeMeas(TSL_tRef_T ref, TSL_tDelta_T delta);
|
||||
TSL_Bool_enum_T TSL_acq_TestReferenceOutOfRange(TSL_ChannelData_T *pCh);
|
||||
TSL_Bool_enum_T TSL_acq_TestFirstReferenceIsValid(TSL_ChannelData_T *pCh, TSL_tMeas_T new_meas);
|
||||
|
||||
#endif // __TSL_ACQ_STM32L1XX_HW_H
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,293 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file tsl_acq_stm32l1xx_sw.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.3.2
|
||||
* @date 22-January-2013
|
||||
* @brief This file contains external declarations of the tsl_acq_stm32l1xx_sw.c file.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __TSL_ACQ_STM32L1XX_SW_H
|
||||
#define __TSL_ACQ_STM32L1XX_SW_H
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32l1xx.h"
|
||||
#include "tsl_conf_stm32l1xx.h"
|
||||
#include "tsl_types.h"
|
||||
|
||||
/* Defines -------------------------------------------------------------------*/
|
||||
|
||||
#ifndef CONST
|
||||
#define CONST const
|
||||
#endif
|
||||
|
||||
// SysTick enable/disable interrupt macros
|
||||
#define enableInterrupts() {SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk;}
|
||||
#define disableInterrupts() {SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk;}
|
||||
|
||||
enum
|
||||
{
|
||||
GR1,
|
||||
GR2,
|
||||
GR3,
|
||||
GR4,
|
||||
GR5,
|
||||
GR6,
|
||||
GR7,
|
||||
GR8,
|
||||
GR9,
|
||||
GR10,
|
||||
GR11
|
||||
};
|
||||
|
||||
enum
|
||||
{
|
||||
TSL_BANK_GPIOA = 0,
|
||||
TSL_BANK_GPIOB,
|
||||
TSL_BANK_GPIOC,
|
||||
TSL_BANK_GPIOE,
|
||||
TSL_BANK_GPIOF,
|
||||
TSL_BANK_GPIOG
|
||||
};
|
||||
|
||||
/** GPIOs list
|
||||
High significant nibble for the IO port (GPIOA:0,...,GPIOG:6)
|
||||
Low significant nibble for the IO number (pin0:0,...,pin15:F)
|
||||
*/
|
||||
enum
|
||||
{
|
||||
PA0 = 0x00, /**< TSL_GROUP1_IO1 */
|
||||
PA1 = 0x01,
|
||||
PA2 = 0x02,
|
||||
PA3 = 0x03,
|
||||
PA6 = 0x06, /**< TSL_GROUP2_IO1 */
|
||||
PA7 = 0x07,
|
||||
PA8 = 0x08,
|
||||
PA9 = 0x09,
|
||||
PA10 = 0x0A,
|
||||
PA13 = 0x0D, /**< TSL_GROUP5_IO1 */
|
||||
PA14 = 0x0E,
|
||||
PA15 = 0x0F,
|
||||
PB0 = 0x10, /**< TSL_GROUP3_IO1 */
|
||||
PB1 = 0x11,
|
||||
PB2 = 0x12,
|
||||
PB4 = 0x14, /**< TSL_GROUP6_IO1 */
|
||||
PB5 = 0x15,
|
||||
PB6 = 0x16,
|
||||
PB7 = 0x17,
|
||||
PB12 = 0x1C, /**< TSL_GROUP7_IO1 */
|
||||
PB13 = 0x1D,
|
||||
PB14 = 0x1E,
|
||||
PB15 = 0x1F,
|
||||
PC0 = 0x20, /**< TSL_GROUP8_IO1 */
|
||||
PC1 = 0x21,
|
||||
PC2 = 0x22,
|
||||
PC3 = 0x23,
|
||||
PC4 = 0x24,
|
||||
PC5 = 0x25,
|
||||
PC6 = 0x26,
|
||||
PC7 = 0x27,
|
||||
PC8 = 0x28,
|
||||
PC9 = 0x29,
|
||||
PF6 = 0x56, /**< TSL_GROUP11_IO1 */
|
||||
PF7 = 0x57,
|
||||
PF8 = 0x58,
|
||||
PF9 = 0x59,
|
||||
PF10 = 0x5A,
|
||||
PF11 = 0x5B,
|
||||
PF12 = 0x5C,
|
||||
PF13 = 0x5D,
|
||||
PF14 = 0x5E,
|
||||
PF15 = 0x5F,
|
||||
PG0 = 0x60, /**< TSL_GROUP2_IO4 */
|
||||
PG1 = 0x61,
|
||||
PG2 = 0x62,
|
||||
PG3 = 0x63,
|
||||
PG4 = 0x64
|
||||
};
|
||||
|
||||
/** GPIOs list:
|
||||
- High significant nibble for the IO port (GPIOA:0,...,GPIOG:6)
|
||||
- Low significant nibble for the IO number (pin0:0,...,pin15:F)
|
||||
*/
|
||||
enum
|
||||
{
|
||||
TSL_GROUP1_IO1 = 0x00, /**< PA0 */
|
||||
TSL_GROUP1_IO2 = 0x01,
|
||||
TSL_GROUP1_IO3 = 0x02,
|
||||
TSL_GROUP1_IO4 = 0x03,
|
||||
TSL_GROUP2_IO1 = 0x06, /**< PA6 */
|
||||
TSL_GROUP2_IO2 = 0x07,
|
||||
TSL_GROUP4_IO1 = 0x08,
|
||||
TSL_GROUP4_IO2 = 0x09,
|
||||
TSL_GROUP4_IO3 = 0x0A,
|
||||
TSL_GROUP5_IO1 = 0x0D, /**< PA13 */
|
||||
TSL_GROUP5_IO2 = 0x0E,
|
||||
TSL_GROUP5_IO3 = 0x0F,
|
||||
TSL_GROUP3_IO1 = 0x10, /**< PB0 */
|
||||
TSL_GROUP3_IO2 = 0x11,
|
||||
TSL_GROUP3_IO3 = 0x12,
|
||||
TSL_GROUP6_IO1 = 0x14, /**< PB4 */
|
||||
TSL_GROUP6_IO2 = 0x15,
|
||||
TSL_GROUP6_IO3 = 0x16,
|
||||
TSL_GROUP6_IO4 = 0x17,
|
||||
TSL_GROUP7_IO1 = 0x1C, /**< PB12 */
|
||||
TSL_GROUP7_IO2 = 0x1D,
|
||||
TSL_GROUP7_IO3 = 0x1E,
|
||||
TSL_GROUP7_IO4 = 0x1F,
|
||||
TSL_GROUP8_IO1 = 0x20, /**< PC0 */
|
||||
TSL_GROUP8_IO2 = 0x21,
|
||||
TSL_GROUP8_IO3 = 0x22,
|
||||
TSL_GROUP8_IO4 = 0x23,
|
||||
TSL_GROUP9_IO1 = 0x24,
|
||||
TSL_GROUP9_IO2 = 0x25,
|
||||
TSL_GROUP10_IO1 = 0x26,
|
||||
TSL_GROUP10_IO2 = 0x27,
|
||||
TSL_GROUP10_IO3 = 0x28,
|
||||
TSL_GROUP10_IO4 = 0x29,
|
||||
TSL_GROUP11_IO1 = 0x56, /**< PF6 */
|
||||
TSL_GROUP11_IO2 = 0x57,
|
||||
TSL_GROUP11_IO3 = 0x58,
|
||||
TSL_GROUP11_IO4 = 0x59,
|
||||
TSL_GROUP11_IO5 = 0x5A,
|
||||
TSL_GROUP3_IO4 = 0x5B,
|
||||
TSL_GROUP3_IO5 = 0x5C,
|
||||
TSL_GROUP9_IO3 = 0x5D,
|
||||
TSL_GROUP9_IO4 = 0x5E,
|
||||
TSL_GROUP2_IO3 = 0x5F,
|
||||
TSL_GROUP2_IO4 = 0x60, /**< PG0 */
|
||||
TSL_GROUP2_IO5 = 0x61,
|
||||
TSL_GROUP7_IO5 = 0x62,
|
||||
TSL_GROUP7_IO6 = 0x63,
|
||||
TSL_GROUP7_IO7 = 0x64
|
||||
};
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
// For all devices/acquisitions
|
||||
|
||||
typedef uint16_t TSL_tMeas_T; /**< Measurement */
|
||||
typedef uint16_t TSL_tRef_T; /**< Reference */
|
||||
typedef int16_t TSL_tDelta_T; /**< Delta */
|
||||
|
||||
typedef uint8_t TSL_tIndexSrc_T; /**< Channel source index */
|
||||
typedef uint16_t TSL_tIndexDest_T; /**< Channel destination index */
|
||||
|
||||
typedef uint8_t TSL_tRefRest_T; /**< Reference Rest (ECS) */
|
||||
typedef uint16_t TSL_tKCoeff_T; /**< K coefficient (ECS) */
|
||||
|
||||
typedef uint8_t TSL_tIndex_T; /**< Generic index */
|
||||
typedef uint16_t TSL_tNb_T; /**< Generic number */
|
||||
typedef uint8_t TSL_tCounter_T; /**< Generic counter used for debounce */
|
||||
|
||||
typedef uint8_t TSL_tThreshold_T; /**< Delta threshold */
|
||||
|
||||
typedef int16_t TSL_tsignPosition_T; /**< Linear and Rotary sensors position */
|
||||
typedef uint8_t TSL_tPosition_T; /**< Linear and Rotary sensors position */
|
||||
|
||||
typedef uint16_t TSL_tTick_ms_T; /**< Time in ms */
|
||||
typedef uint8_t TSL_tTick_sec_T; /**< Time in sec */
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
// Channel
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
typedef uint8_t TSL_Conf_t;
|
||||
|
||||
/** Channel destination index
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
TSL_tIndex_T IdxDest; /**< Index in the Channel data array */
|
||||
} TSL_ChannelDest_T;
|
||||
|
||||
/** Channel Source and Configuration
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
TSL_tIndex_T IdxSrc; /**< Index of source value */
|
||||
// For stm32l1x acquisition only
|
||||
TSL_Conf_t t_sample; /**< Indicates which GPIO.n is used for the sample */
|
||||
TSL_Conf_t t_channel; /**< Indicates which GPIO.n is used for the channel */
|
||||
} TSL_ChannelSrc_T;
|
||||
|
||||
/** Channel flags
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
unsigned int DataReady : 1; /**< To identify a new measurement (TSL_DataReady_enum_T) */
|
||||
unsigned int AcqStatus : 2; /**< Acquisition status (TSL_AcqStatus_enum_T) */
|
||||
unsigned int ObjStatus : 2; /**< Object status (TSL_ObjStatus_enum_T) */
|
||||
} TSL_ChannelFlags_T;
|
||||
|
||||
/** Channel Data
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
TSL_ChannelFlags_T Flags; /**< Flags */
|
||||
TSL_tRef_T Ref; /**< Reference */
|
||||
TSL_tRefRest_T RefRest; /**< Reference rest for ECS */
|
||||
TSL_tDelta_T Delta; /**< Delta */
|
||||
#if TSLPRM_USE_MEAS > 0
|
||||
TSL_tMeas_T Meas; /**< Hold the last acquisition measure */
|
||||
#endif
|
||||
} TSL_ChannelData_T;
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
// Bank
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
/** Bank
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
// Common to all acquisitions
|
||||
CONST TSL_ChannelSrc_T *p_chSrc; /**< Pointer to the Channel Source and Configuration */
|
||||
CONST TSL_ChannelDest_T *p_chDest; /**< Pointer to the Channel Destination */
|
||||
TSL_ChannelData_T *p_chData; /**< Pointer to the Channel Data */
|
||||
TSL_tNb_T NbChannels; /**< Number of channels in the bank */
|
||||
// For stm32l1x acquisition only
|
||||
TSL_Conf_t shield_sample; /**< Indicates which GPIO.n is used for the shield sample */
|
||||
TSL_Conf_t shield_channel; /**< Indicates which GPIO.n is used for the shield channel */
|
||||
} TSL_Bank_T;
|
||||
|
||||
/* Exported variables --------------------------------------------------------*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
TSL_Status_enum_T TSL_acq_Init(void);
|
||||
TSL_Status_enum_T TSL_acq_BankConfig(TSL_tIndex_T idx_bk);
|
||||
void TSL_acq_BankStartAcq(void);
|
||||
TSL_Status_enum_T TSL_acq_BankWaitEOC(void);
|
||||
void TSL_acq_ProcessIT(void);
|
||||
TSL_tMeas_T TSL_acq_GetMeas(TSL_tIndex_T index);
|
||||
TSL_AcqStatus_enum_T TSL_acq_CheckNoise(void);
|
||||
|
||||
TSL_Bool_enum_T TSL_acq_UseFilter(TSL_ChannelData_T *pCh);
|
||||
TSL_tDelta_T TSL_acq_ComputeDelta(TSL_tRef_T ref, TSL_tMeas_T meas);
|
||||
TSL_tMeas_T TSL_acq_ComputeMeas(TSL_tRef_T ref, TSL_tDelta_T delta);
|
||||
TSL_Bool_enum_T TSL_acq_TestReferenceOutOfRange(TSL_ChannelData_T *pCh);
|
||||
TSL_Bool_enum_T TSL_acq_TestFirstReferenceIsValid(TSL_ChannelData_T *pCh, TSL_tMeas_T new_meas);
|
||||
|
||||
#endif /* __TSL_ACQ_STM32L1XX_SW_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,270 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file tsl_acq_stm8tl5x.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.3.2
|
||||
* @date 22-January-2013
|
||||
* @brief This file contains all functions prototypes that manage the TSC
|
||||
* acquisition on STM8TL5x products.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __TSL_ACQ_STM8TL5X_H
|
||||
#define __TSL_ACQ_STM8TL5X_H
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm8tl5x.h"
|
||||
#include "tsl_conf_stm8tl5x.h"
|
||||
#include "tsl_types.h"
|
||||
|
||||
/*==============================================================================
|
||||
|
||||
*** RECEIVERS AND TRANSMITTERS DESCRIPTION ***
|
||||
|
||||
ProxSense receiver and transmitter description for STM8TL5x
|
||||
For more details please refer to the Proxsense
|
||||
section in the reference manual
|
||||
|
||||
|
||||
Txi
|
||||
Group Ai Rx0a __/____ |
|
||||
Rx1a __/____ |
|
||||
Rx2a __/____ |
|
||||
Rx3a __/____ |
|
||||
Rx4a __/____ |
|
||||
Rx5a __/____ |
|
||||
Rx6a __/____ |
|
||||
Rx7a __/____ |
|
||||
Rx8a __/____ |
|
||||
Rx9a __/____ |
|
||||
|
||||
Group Bi Rx0b __/____ |
|
||||
Rx1b __/____ |
|
||||
Rx2b __/____ |
|
||||
Rx3b __/____ |
|
||||
Rx4b __/____ |
|
||||
Rx5b __/____ |
|
||||
Rx6b __/____ |
|
||||
Rx7b __/____ |
|
||||
Rx8b __/____ |
|
||||
Rx9b __/____ |
|
||||
|
||||
==============================================================================*/
|
||||
|
||||
/* Defines -------------------------------------------------------------------*/
|
||||
|
||||
// Receivers
|
||||
#define RX0 (0+0x8000)
|
||||
#define RX1 (1+0x8000)
|
||||
#define RX2 (2+0x8000)
|
||||
#define RX3 (3+0x8000)
|
||||
#define RX4 (4+0x8000)
|
||||
#define RX5 (5+0x8000)
|
||||
#define RX6 (6+0x8000)
|
||||
#define RX7 (7+0x8000)
|
||||
#define RX8 (8+0x8000)
|
||||
#define RX9 (9+0x8000)
|
||||
|
||||
// Transmitters
|
||||
#define TX0 (0)
|
||||
#define TX1 (1)
|
||||
#define TX2 (2)
|
||||
#define TX3 (3)
|
||||
#define TX4 (4)
|
||||
#define TX5 (5)
|
||||
#define TX6 (6)
|
||||
#define TX7 (7)
|
||||
#define TX8 (8)
|
||||
#define TX9 (9)
|
||||
#define TX10 (10)
|
||||
#define TX11 (11)
|
||||
#define TX12 (12)
|
||||
#define TX13 (13)
|
||||
#define TX14 (14)
|
||||
|
||||
#define BIT_MASK_RX(N) ((uint16_t)1<<(uint8_t)(N & 0xFF))
|
||||
#define BIT_MASK_TX(N) ((uint16_t)1<< N)
|
||||
|
||||
// Acquisition Bank
|
||||
#define BANK01 1
|
||||
#define BANK02 2
|
||||
#define BANK03 3
|
||||
#define BANK04 4
|
||||
#define BANK05 5
|
||||
#define BANK06 6
|
||||
#define BANK07 7
|
||||
#define BANK08 8
|
||||
#define BANK09 9
|
||||
#define BANK10 10
|
||||
#define BANK11 11
|
||||
#define BANK12 12
|
||||
#define BANK13 13
|
||||
#define BANK14 14
|
||||
#define BANK15 15
|
||||
#define BANK16 16
|
||||
#define BANK17 17
|
||||
#define BANK18 18
|
||||
#define BANK19 19
|
||||
#define BANK20 20
|
||||
#define BANK21 21
|
||||
#define BANK22 22
|
||||
#define BANK23 23
|
||||
#define BANK24 24
|
||||
#define BANK25 25
|
||||
#define BANK26 26
|
||||
#define BANK27 27
|
||||
#define BANK28 28
|
||||
#define BANK29 29
|
||||
#define BANK30 30
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
// For all devices/acquisitions
|
||||
|
||||
typedef uint16_t TSL_tMeas_T; /**< Measurement */
|
||||
typedef uint16_t TSL_tRef_T; /**< Reference */
|
||||
typedef int16_t TSL_tDelta_T; /**< Delta */
|
||||
|
||||
typedef uint8_t TSL_tIndexSrc_T; /**< Channel source index */
|
||||
typedef uint16_t TSL_tIndexDest_T; /**< Channel destination index */
|
||||
|
||||
typedef uint8_t TSL_tRefRest_T; /**< Reference Rest (ECS) */
|
||||
typedef uint16_t TSL_tKCoeff_T; /**< K coefficient (ECS) */
|
||||
|
||||
typedef uint8_t TSL_tIndex_T; /**< Generic index */
|
||||
typedef uint16_t TSL_tNb_T; /**< Generic number */
|
||||
typedef uint8_t TSL_tCounter_T; /**< Generic counter used for debounce */
|
||||
|
||||
typedef uint8_t TSL_tThreshold_T; /**< Delta threshold */
|
||||
|
||||
typedef int16_t TSL_tsignPosition_T; /**< Linear and Rotary sensors position */
|
||||
typedef uint8_t TSL_tPosition_T; /**< Linear and Rotary sensors position */
|
||||
|
||||
typedef uint16_t TSL_tTick_ms_T; /**< Time in ms */
|
||||
typedef uint8_t TSL_tTick_sec_T; /**< Time in sec */
|
||||
|
||||
// For STM8TL5X only
|
||||
|
||||
typedef uint16_t TSL_tMaskRX; /**< Receiver mask */
|
||||
typedef uint16_t TSL_tMaskTX; /**< Transmitter mask */
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
// Channel
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
/** Channel destination index
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
TSL_tIndexDest_T IdxDest; /**< Index in the Channel data array */
|
||||
} TSL_ChannelDest_T;
|
||||
|
||||
/** Channel Source and Configuration
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
TSL_tIndexSrc_T IdxSrc; /**< Index of the receivers (between 0 and 9) */
|
||||
} TSL_ChannelSrc_T;
|
||||
|
||||
#define TSL_EPCC_CHANGE_MASK (0x04) /**< EPCC change mask */
|
||||
|
||||
/** EPCC status
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TSL_EPCC_STATUS_UNLOCKED = 0, /**< EPCC is unlocked */
|
||||
TSL_EPCC_STATUS_LOCKED = 1, /**< EPCC is locked */
|
||||
TSL_EPCC_STATUS_DECREASE = 4, /**< EPCC must decreased */
|
||||
TSL_EPCC_STATUS_INCREASE = 6 /**< EPCC must be increased */
|
||||
} TSL_EPCCStatus_enum_T;
|
||||
|
||||
/** Channel flags
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
unsigned int DataReady : 1; /**< To identify a new measurement (TSL_DataReady_enum_T) */
|
||||
unsigned int AcqStatus : 2; /**< Acquisition status (TSL_AcqStatus_enum_T) */
|
||||
unsigned int EPCCStatus : 3; /**< Acquisition status (TSL_EPCCStatus_enum_T) */
|
||||
unsigned int ObjStatus : 2; /**< Object status (TSL_ObjStatus_enum_T) */
|
||||
} TSL_ChannelFlags_T;
|
||||
|
||||
/** Channel Data
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
TSL_ChannelFlags_T Flags; /**< Flags */
|
||||
TSL_tRef_T Ref; /**< Reference */
|
||||
TSL_tRefRest_T RefRest; /**< Reference rest for ECS */
|
||||
TSL_tDelta_T Delta; /**< Delta */
|
||||
#if TSLPRM_USE_MEAS > 0
|
||||
TSL_tMeas_T Meas; /**< Hold the last acquisition measure */
|
||||
#endif
|
||||
} TSL_ChannelData_T;
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
// Bank
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
/** Bank
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
// Common to all acquisitions
|
||||
CONST TSL_ChannelSrc_T *p_chSrc; /**< Pointer to the Channel Source and Configuration */
|
||||
CONST TSL_ChannelDest_T *p_chDest; /**< Pointer to the Channel Destination */
|
||||
TSL_ChannelData_T *p_chData; /**< Pointer to the Channel Data */
|
||||
TSL_tNb_T NbChannels; /**< Number of channels in the bank */
|
||||
// For stm8tl5x PXS acquisition only
|
||||
TSL_tMaskRX msk_channels; /**< Mask of all receivers */
|
||||
TSL_tMaskTX msk_TX; /**< Mask of Tx */
|
||||
uint8_t msk_group; /**< Mask of group used (RX_GROUPA or RX_GROUPB) */
|
||||
TSL_tMaskRX msk_RXEN; /**< Mask of all RX (receivers and transmitters) */
|
||||
} TSL_Bank_T;
|
||||
|
||||
/** Bank Configuration
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t CSSEL[TSLPRM_HIGH_CHANNEL_NB+1]; /**< Array of CS values */
|
||||
uint8_t EPCCSEL[TSLPRM_HIGH_CHANNEL_NB+1]; /**< Array of EPCC values */
|
||||
} TSL_BankConfig_T;
|
||||
|
||||
/* Exported variables --------------------------------------------------------*/
|
||||
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
#define TSL_acq_ComputeDelta(Reference,Measure) (TSL_tDelta_T)(Measure - Reference) /**< Calculate the Delta */
|
||||
#define TSL_acq_ComputeMeas(Reference,Delta) (TSL_tMeas_T)(Delta + Reference) /**< Calculate the Measure */
|
||||
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
TSL_Status_enum_T TSL_acq_Init(void);
|
||||
TSL_Status_enum_T TSL_acq_BankConfig(TSL_tIndex_T idx_bk);
|
||||
TSL_Bool_enum_T TSL_acq_UseFilter(TSL_ChannelData_T *pCh);
|
||||
TSL_Bool_enum_T TSL_acq_TestFirstReferenceIsValid(TSL_ChannelData_T *pCh, TSL_tMeas_T new_meas);
|
||||
TSL_Bool_enum_T TSL_acq_TestReferenceOutOfRange(TSL_ChannelData_T *pCh);
|
||||
void TSL_acq_BankStartAcq(void);
|
||||
TSL_Status_enum_T TSL_acq_BankWaitEOC(void);
|
||||
TSL_AcqStatus_enum_T TSL_acq_CheckNoise(void);
|
||||
TSL_tMeas_T TSL_acq_GetMeas(TSL_tIndexSrc_T index);
|
||||
void TSL_acq_UpdateCS(uint8_t *pCSSEL, TSL_EPCCStatus_enum_T change);
|
||||
|
||||
#endif /* __TSL_ACQ_STM8TL5X_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,445 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file tsl_check_config.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.3.2
|
||||
* @date 22-January-2013
|
||||
* @brief This file contains the check of all parameters defined in the
|
||||
* common configuration file.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __TSL_CHECK_CONFIG_H
|
||||
#define __TSL_CHECK_CONFIG_H
|
||||
|
||||
//==============================================================================
|
||||
// Common parameters check
|
||||
//==============================================================================
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#ifndef TSLPRM_TOTAL_CHANNELS
|
||||
#error "TSLPRM_TOTAL_CHANNELS is not defined."
|
||||
#endif
|
||||
|
||||
#ifndef TSLPRM_TOTAL_BANKS
|
||||
#error "TSLPRM_TOTAL_BANKS is not defined."
|
||||
#endif
|
||||
|
||||
#ifndef TSLPRM_TOTAL_TOUCHKEYS
|
||||
#error "TSLPRM_TOTAL_TOUCHKEYS is not defined."
|
||||
#endif
|
||||
|
||||
#ifndef TSLPRM_TOTAL_TOUCHKEYS_B
|
||||
#error "TSLPRM_TOTAL_TOUCHKEYS_B is not defined."
|
||||
#endif
|
||||
|
||||
#ifndef TSLPRM_TOTAL_LINROTS
|
||||
#error "TSLPRM_TOTAL_LINROTS is not defined."
|
||||
#endif
|
||||
|
||||
#ifndef TSLPRM_TOTAL_LINROTS_B
|
||||
#error "TSLPRM_TOTAL_LINROTS_B is not defined."
|
||||
#endif
|
||||
|
||||
#ifndef TSLPRM_TOTAL_OBJECTS
|
||||
#error "TSLPRM_TOTAL_OBJECTS is not defined."
|
||||
#endif
|
||||
|
||||
#define TSLPRM_TOTAL_TKEYS (TSLPRM_TOTAL_TOUCHKEYS + TSLPRM_TOTAL_TOUCHKEYS_B)
|
||||
#define TSLPRM_TOTAL_LNRTS (TSLPRM_TOTAL_LINROTS + TSLPRM_TOTAL_LINROTS_B)
|
||||
|
||||
#if ((TSLPRM_TOTAL_TKEYS == 0) && (TSLPRM_TOTAL_LNRTS == 0))
|
||||
#error "No TouchKey and No Linear/Rotary sensors are defined."
|
||||
#endif
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#ifndef TSLPRM_CALIB_SAMPLES
|
||||
#error "TSLPRM_CALIB_SAMPLES is not defined."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_CALIB_SAMPLES != 4) && (TSLPRM_CALIB_SAMPLES != 8) && (TSLPRM_CALIB_SAMPLES != 16))
|
||||
#error "TSLPRM_CALIB_SAMPLES is out of range (4, 8, 16)."
|
||||
#endif
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#ifndef TSLPRM_CALIB_DELAY
|
||||
#error "TSLPRM_CALIB_DELAY is not defined."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_CALIB_DELAY < 0) || (TSLPRM_CALIB_DELAY > 40))
|
||||
#error "TSLPRM_CALIB_DELAY is out of range (0..40)."
|
||||
#endif
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#ifndef TSLPRM_ACQ_MIN
|
||||
#error "TSLPRM_ACQ_MIN is not defined."
|
||||
#endif
|
||||
|
||||
#ifndef TSLPRM_ACQ_MAX
|
||||
#error "TSLPRM_ACQ_MAX is not defined."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_ACQ_MIN < 1) || (TSLPRM_ACQ_MIN > (TSLPRM_ACQ_MAX-1)))
|
||||
#error "TSLPRM_ACQ_MIN is out of range (1 .. ACQ_MAX-1)."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_ACQ_MAX < (TSLPRM_ACQ_MIN+1)) || (TSLPRM_ACQ_MAX > 50000))
|
||||
#error "TSLPRM_ACQ_MAX is out of range (ACQ_MIN+1 .. 50000)."
|
||||
#endif
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#ifndef TSLPRM_TKEY_PROX_IN_TH
|
||||
#error "TSLPRM_TKEY_PROX_IN_TH is not defined."
|
||||
#endif
|
||||
|
||||
#ifndef TSLPRM_TKEY_PROX_OUT_TH
|
||||
#error "TSLPRM_TKEY_PROX_OUT_TH is not defined."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_TKEY_PROX_OUT_TH < 0) || (TSLPRM_TKEY_PROX_OUT_TH > (TSLPRM_TKEY_PROX_IN_TH-1)))
|
||||
#error "TSLPRM_TKEY_PROX_OUT_TH is out of range (0 .. TSLPRM_TKEY_PROX_IN_TH-1)."
|
||||
#endif
|
||||
|
||||
#if TSLPRM_COEFF_TH == 0
|
||||
#if ((TSLPRM_TKEY_PROX_IN_TH < (TSLPRM_TKEY_PROX_OUT_TH+1)) || (TSLPRM_TKEY_PROX_IN_TH > (TSLPRM_TKEY_DETECT_OUT_TH-1)))
|
||||
#error "TSLPRM_TKEY_PROX_IN_TH is out of range (TSLPRM_TKEY_PROX_OUT_TH+1 .. TSLPRM_TKEY_DETECT_OUT_TH-1)."
|
||||
#endif
|
||||
#endif
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#ifndef TSLPRM_LINROT_PROX_IN_TH
|
||||
#error "TSLPRM_LINROT_PROX_IN_TH is not defined."
|
||||
#endif
|
||||
|
||||
#ifndef TSLPRM_LINROT_PROX_OUT_TH
|
||||
#error "TSLPRM_LINROT_PROX_OUT_TH is not defined."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_LINROT_PROX_OUT_TH < 0) || (TSLPRM_LINROT_PROX_OUT_TH > (TSLPRM_LINROT_PROX_IN_TH-1)))
|
||||
#error "TSLPRM_LINROT_PROX_OUT_TH is out of range (0 .. TSLPRM_LINROT_PROX_IN_TH-1)."
|
||||
#endif
|
||||
|
||||
#if TSLPRM_COEFF_TH == 0
|
||||
#if ((TSLPRM_LINROT_PROX_IN_TH < (TSLPRM_LINROT_PROX_OUT_TH+1)) || (TSLPRM_LINROT_PROX_IN_TH > (TSLPRM_LINROT_DETECT_OUT_TH-1)))
|
||||
#error "TSLPRM_LINROT_PROX_IN_TH is out of range (TSLPRM_LINROT_PROX_OUT_TH+1 .. TSLPRM_LINROT_DETECT_OUT_TH-1)."
|
||||
#endif
|
||||
#endif
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#ifndef TSLPRM_TKEY_DETECT_IN_TH
|
||||
#error "TSLPRM_TKEY_DETECT_IN_TH is not defined."
|
||||
#endif
|
||||
|
||||
#ifndef TSLPRM_TKEY_DETECT_OUT_TH
|
||||
#error "TSLPRM_TKEY_DETECT_OUT_TH is not defined."
|
||||
#endif
|
||||
|
||||
#if TSLPRM_COEFF_TH == 0
|
||||
#if ((TSLPRM_TKEY_DETECT_OUT_TH < (TSLPRM_TKEY_PROX_IN_TH+1)) || (TSLPRM_TKEY_DETECT_OUT_TH > (TSLPRM_TKEY_DETECT_IN_TH-1)))
|
||||
#error "TSLPRM_TKEY_DETECT_OUT_TH is out of range (TSLPRM_TKEY_PROX_IN_TH+1 .. TSLPRM_TKEY_DETECT_IN_TH-1)."
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_TKEY_DETECT_IN_TH < (TSLPRM_TKEY_DETECT_OUT_TH+1)) || (TSLPRM_TKEY_DETECT_IN_TH > 255))
|
||||
#error "TSLPRM_TKEY_DETECT_IN_TH is out of range (TSLPRM_TKEY_DETECT_OUT_TH+1 .. 255)."
|
||||
#endif
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#ifndef TSLPRM_LINROT_DETECT_IN_TH
|
||||
#error "TSLPRM_LINROT_DETECT_IN_TH is not defined."
|
||||
#endif
|
||||
|
||||
#ifndef TSLPRM_LINROT_DETECT_OUT_TH
|
||||
#error "TSLPRM_LINROT_DETECT_OUT_TH is not defined."
|
||||
#endif
|
||||
|
||||
#if TSLPRM_COEFF_TH == 0
|
||||
#if ((TSLPRM_LINROT_DETECT_OUT_TH < (TSLPRM_LINROT_PROX_IN_TH+1)) || (TSLPRM_LINROT_DETECT_OUT_TH > (TSLPRM_LINROT_DETECT_IN_TH-1)))
|
||||
#error "TSLPRM_LINROT_DETECT_OUT_TH is out of range (TSLPRM_LINROT_PROX_IN_TH+1 .. TSLPRM_LINROT_DETECT_IN_TH-1)."
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_LINROT_DETECT_IN_TH < (TSLPRM_LINROT_DETECT_OUT_TH+1)) || (TSLPRM_LINROT_DETECT_IN_TH > 255))
|
||||
#error "TSLPRM_LINROT_DETECT_IN_TH is out of range (TSLPRM_LINROT_DETECT_OUT_TH+1 .. 255)."
|
||||
#endif
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#ifndef TSLPRM_TKEY_CALIB_TH
|
||||
#error "TSLPRM_TKEY_CALIB_TH is not defined."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_TKEY_CALIB_TH < 0) || (TSLPRM_TKEY_CALIB_TH > 255))
|
||||
#error "TSLPRM_TKEY_CALIB_TH is out of range (0 .. 255)."
|
||||
#endif
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#ifndef TSLPRM_LINROT_CALIB_TH
|
||||
#error "TSLPRM_LINROT_CALIB_TH is not defined."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_LINROT_CALIB_TH < 0) || (TSLPRM_LINROT_CALIB_TH > 255))
|
||||
#error "TSLPRM_LINROT_CALIB_TH is out of range (0 .. 255)."
|
||||
#endif
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#ifndef TSLPRM_LINROT_USE_NORMDELTA
|
||||
#error "TSLPRM_LINROT_USE_NORMDELTA is not defined."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_LINROT_USE_NORMDELTA < 0) || (TSLPRM_LINROT_USE_NORMDELTA > 1))
|
||||
#error "TSLPRM_LINROT_USE_NORMDELTA is out of range (0 .. 1)."
|
||||
#endif
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#ifndef TSLPRM_COEFF_TH
|
||||
#error "TSLPRM_COEFF_TH is not defined."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_COEFF_TH < 0) || (TSLPRM_COEFF_TH > 4))
|
||||
#error "TSLPRM_COEFF_TH is out of range (0 .. 4)."
|
||||
#endif
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#ifndef TSLPRM_LINROT_DIR_CHG_POS
|
||||
#error "TSLPRM_LINROT_DIR_CHG_POS is not defined."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_LINROT_DIR_CHG_POS < 0) || (TSLPRM_LINROT_DIR_CHG_POS > 255))
|
||||
#error "TSLPRM_LINROT_DIR_CHG_POS is out of range (0 .. 255)."
|
||||
#endif
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#ifndef TSLPRM_LINROT_RESOLUTION
|
||||
#error "TSLPRM_LINROT_RESOLUTION is not defined."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_LINROT_RESOLUTION < 1) || (TSLPRM_LINROT_RESOLUTION > 8))
|
||||
#error "TSLPRM_LINROT_RESOLUTION is out of range (1 .. 8)."
|
||||
#endif
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#ifndef TSLPRM_DEBOUNCE_PROX
|
||||
#error "TSLPRM_DEBOUNCE_PROX is not defined."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_DEBOUNCE_PROX < 0) || (TSLPRM_DEBOUNCE_PROX > 63))
|
||||
#error "TSLPRM_DEBOUNCE_PROX is out of range (0 .. 63)."
|
||||
#endif
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#ifndef TSLPRM_DEBOUNCE_DETECT
|
||||
#error "TSLPRM_DEBOUNCE_DETECT is not defined."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_DEBOUNCE_DETECT < 0) || (TSLPRM_DEBOUNCE_DETECT > 63))
|
||||
#error "TSLPRM_DEBOUNCE_DETECT is out of range (0 .. 63)."
|
||||
#endif
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#ifndef TSLPRM_DEBOUNCE_RELEASE
|
||||
#error "TSLPRM_DEBOUNCE_RELEASE is not defined."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_DEBOUNCE_RELEASE < 0) || (TSLPRM_DEBOUNCE_RELEASE > 63))
|
||||
#error "TSLPRM_DEBOUNCE_RELEASE is out of range (0 .. 63)."
|
||||
#endif
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#ifndef TSLPRM_DEBOUNCE_CALIB
|
||||
#error "TSLPRM_DEBOUNCE_CALIB is not defined."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_DEBOUNCE_CALIB < 0) || (TSLPRM_DEBOUNCE_CALIB > 63))
|
||||
#error "TSLPRM_DEBOUNCE_CALIB is out of range (0 .. 63)."
|
||||
#endif
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#ifndef TSLPRM_DEBOUNCE_ERROR
|
||||
#error "TSLPRM_DEBOUNCE_ERROR is not defined."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_DEBOUNCE_ERROR < 0) || (TSLPRM_DEBOUNCE_ERROR > 63))
|
||||
#error "TSLPRM_DEBOUNCE_ERROR is out of range (0 .. 63)."
|
||||
#endif
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#ifndef TSLPRM_LINROT_DIR_CHG_DEB
|
||||
#error "TSLPRM_LINROT_DIR_CHG_DEB is not defined."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_LINROT_DIR_CHG_DEB < 0) || (TSLPRM_LINROT_DIR_CHG_DEB > 63))
|
||||
#error "TSLPRM_LINROT_DIR_CHG_DEB is out of range (0 .. 63)."
|
||||
#endif
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#ifndef TSLPRM_ECS_K_SLOW
|
||||
#error "TSLPRM_ECS_K_SLOW is not defined."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_ECS_K_SLOW < 0) || (TSLPRM_ECS_K_SLOW > 255))
|
||||
#error "TSLPRM_ECS_K_SLOW is out of range (0 .. 255)."
|
||||
#endif
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#ifndef TSLPRM_ECS_K_FAST
|
||||
#error "TSLPRM_ECS_K_FAST is not defined."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_ECS_K_FAST < 0) || (TSLPRM_ECS_K_FAST > 255))
|
||||
#error "TSLPRM_ECS_K_FAST is out of range (0 .. 255)."
|
||||
#endif
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#ifndef TSLPRM_ECS_DELAY
|
||||
#error "TSLPRM_ECS_DELAY is not defined."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_ECS_DELAY < 0) || (TSLPRM_ECS_DELAY > 5000))
|
||||
#error "TSLPRM_ECS_DELAY is out of range (0 .. 5000)."
|
||||
#endif
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#ifndef TSLPRM_USE_MEAS
|
||||
#error "TSLPRM_USE_MEAS is not defined."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_USE_MEAS != 0) && (TSLPRM_USE_MEAS != 1))
|
||||
#error "TSLPRM_USE_MEAS is out of range (0 .. 1)."
|
||||
#endif
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#ifndef TSLPRM_USE_PROX
|
||||
#error "TSLPRM_USE_PROX is not defined."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_USE_PROX != 0) && (TSLPRM_USE_PROX != 1))
|
||||
#error "TSLPRM_USE_PROX is out of range (0 .. 1)."
|
||||
#endif
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#ifndef TSLPRM_USE_ZONE
|
||||
#error "TSLPRM_USE_ZONE is not defined."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_USE_ZONE != 0) && (TSLPRM_USE_ZONE != 1))
|
||||
#error "TSLPRM_USE_ZONE is out of range (0 .. 1)."
|
||||
#endif
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#ifndef TSLPRM_USE_ACQ_INTERRUPT
|
||||
#error "TSLPRM_USE_ACQ_INTERRUPT is not defined."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_USE_ACQ_INTERRUPT != 0) && (TSLPRM_USE_ACQ_INTERRUPT != 1))
|
||||
#error "TSLPRM_USE_ACQ_INTERRUPT is out of range (0 .. 1)."
|
||||
#endif
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#ifndef TSLPRM_DTO
|
||||
#error "TSLPRM_DTO is not defined."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_DTO < 0) || (TSLPRM_DTO > 63))
|
||||
#error "TSLPRM_DTO is out of range (0 .. 63)."
|
||||
#endif
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#ifndef TSLPRM_TICK_FREQ
|
||||
#error "TSLPRM_TICK_FREQ is not defined."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_TICK_FREQ != 125) && (TSLPRM_TICK_FREQ != 250) && (TSLPRM_TICK_FREQ != 500) &&\
|
||||
(TSLPRM_TICK_FREQ != 1000) && (TSLPRM_TICK_FREQ != 2000))
|
||||
#error "TSLPRM_TICK_FREQ is out of range (125, 250, 500, 1000, 2000)."
|
||||
#endif
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#ifndef TSLPRM_USE_DXS
|
||||
#error "TSLPRM_USE_DXS is not defined."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_USE_DXS < 0) || (TSLPRM_USE_DXS > 1))
|
||||
#error "TSLPRM_USE_DXS is out of range (0 .. 1)."
|
||||
#endif
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#ifndef TSLPRM_USE_TIMER_CALLBACK
|
||||
#error "TSLPRM_USE_TIMER_CALLBACK is not defined."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_USE_TIMER_CALLBACK != 0) && (TSLPRM_USE_TIMER_CALLBACK != 1))
|
||||
#error "TSLPRM_USE_TIMER_CALLBACK is out of range (0 .. 1)."
|
||||
#endif
|
||||
|
||||
//==============================================================================
|
||||
// Specific parameters check
|
||||
//==============================================================================
|
||||
|
||||
#if defined(STM8TL5X)
|
||||
#include "tsl_check_config_stm8tl5x.h"
|
||||
#endif
|
||||
|
||||
#if defined(STM32F0XX)
|
||||
#include "tsl_check_config_stm32f0xx.h"
|
||||
#endif
|
||||
|
||||
#if defined(STM32F30X) || defined(STM32F37X)
|
||||
#include "tsl_check_config_stm32f3xx.h"
|
||||
#endif
|
||||
|
||||
#if defined(STM32L1XX_MD) || defined(STM32L1XX_HD) || defined(STM32L1XX_MDP)
|
||||
#include "tsl_check_config_stm32l1xx.h"
|
||||
#endif
|
||||
|
||||
#endif /* __TSL_CHECK_CONFIG_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,217 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file tsl_check_config_stm32f0xx.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.3.2
|
||||
* @date 22-January-2013
|
||||
* @brief This file contains the check of all parameters defined in the
|
||||
* STM32F0XX configuration file.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __TSL_CHECK_CONFIG_STM32F0XX_H
|
||||
#define __TSL_CHECK_CONFIG_STM32F0XX_H
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#if ((TSLPRM_TOTAL_CHANNELS < 1) || (TSLPRM_TOTAL_CHANNELS > 24))
|
||||
#error "TSLPRM_TOTAL_CHANNELS is out of range (1 .. 24)."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_TOTAL_BANKS < 1) || (TSLPRM_TOTAL_BANKS > 8))
|
||||
#error "TSLPRM_TOTAL_BANKS is out of range (1 .. 8)."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_TOTAL_TOUCHKEYS < 0) || (TSLPRM_TOTAL_TOUCHKEYS > 24))
|
||||
#error "TSLPRM_TOTAL_TOUCHKEYS is out of range (0 .. 24)."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_TOTAL_TOUCHKEYS_B < 0) || (TSLPRM_TOTAL_TOUCHKEYS_B > 24))
|
||||
#error "TSLPRM_TOTAL_TOUCHKEYS_B is out of range (0 .. 24)."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_TOTAL_LINROTS < 0) || (TSLPRM_TOTAL_LINROTS > 24))
|
||||
#error "TSLPRM_TOTAL_LINROTS is out of range (0 .. 24)."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_TOTAL_LINROTS_B < 0) || (TSLPRM_TOTAL_LINROTS_B > 24))
|
||||
#error "TSLPRM_TOTAL_LINROTS_B is out of range (0 .. 24)."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_TOTAL_OBJECTS < 1) || (TSLPRM_TOTAL_OBJECTS > 24))
|
||||
#error "TSLPRM_TOTAL_OBJECTS is out of range (1 .. 24)."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_TOTAL_TKEYS + TSLPRM_TOTAL_LNRTS) > 24)
|
||||
#error "The Sum of TouchKeys and Linear/Rotary sensors exceeds 24."
|
||||
#endif
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#ifndef TSLPRM_TSC_GPIO_CONFIG
|
||||
#error "TSLPRM_TSC_GPIO_CONFIG is not defined."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_TSC_GPIO_CONFIG < 0) || (TSLPRM_TSC_GPIO_CONFIG > 1))
|
||||
#error "TSLPRM_TSC_GPIO_CONFIG is out of range (0 .. 1)."
|
||||
#endif
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#ifndef TSLPRM_TSC_CTPH
|
||||
#error "TSLPRM_TSC_CTPH is not defined."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_TSC_CTPH < 0) || (TSLPRM_TSC_CTPH > 15))
|
||||
#error "TSLPRM_TSC_CTPH is out of range (0 .. 15)."
|
||||
#endif
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#ifndef TSLPRM_TSC_CTPL
|
||||
#error "TSLPRM_TSC_CTPL is not defined."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_TSC_CTPL < 0) || (TSLPRM_TSC_CTPL > 15))
|
||||
#error "TSLPRM_TSC_CTPL is out of range (0 .. 15)."
|
||||
#endif
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#ifndef TSLPRM_TSC_PGPSC
|
||||
#error "TSLPRM_TSC_PGPSC is not defined."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_TSC_PGPSC < 0) || (TSLPRM_TSC_PGPSC > 7))
|
||||
#error "TSLPRM_TSC_PGPSC is out of range (0 .. 7)."
|
||||
#endif
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#if (TSLPRM_ACQ_MAX > 0) && (TSLPRM_ACQ_MAX < 256)
|
||||
#define TSLPRM_TSC_MCV 0 // 255
|
||||
#endif
|
||||
|
||||
#if (TSLPRM_ACQ_MAX > 255) && (TSLPRM_ACQ_MAX < 512)
|
||||
#define TSLPRM_TSC_MCV 1 // 511
|
||||
#endif
|
||||
|
||||
#if (TSLPRM_ACQ_MAX > 511) && (TSLPRM_ACQ_MAX < 1024)
|
||||
#define TSLPRM_TSC_MCV 2 // 1023
|
||||
#endif
|
||||
|
||||
#if (TSLPRM_ACQ_MAX > 1023) && (TSLPRM_ACQ_MAX < 2048)
|
||||
#define TSLPRM_TSC_MCV 3 // 2047
|
||||
#endif
|
||||
|
||||
#if (TSLPRM_ACQ_MAX > 2047) && (TSLPRM_ACQ_MAX < 4096)
|
||||
#define TSLPRM_TSC_MCV 4 // 4095
|
||||
#endif
|
||||
|
||||
#if (TSLPRM_ACQ_MAX > 4095) && (TSLPRM_ACQ_MAX < 8192)
|
||||
#define TSLPRM_TSC_MCV 5 // 8191
|
||||
#endif
|
||||
|
||||
#if (TSLPRM_ACQ_MAX > 8191)
|
||||
#define TSLPRM_TSC_MCV 6 // 16383
|
||||
#endif
|
||||
|
||||
#ifndef TSLPRM_TSC_MCV
|
||||
#error "TSLPRM_TSC_MCV is not defined."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_TSC_MCV < 0) || (TSLPRM_TSC_MCV > 6))
|
||||
#error "TSLPRM_TSC_MCV is out of range (0 .. 6)."
|
||||
#endif
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#ifndef TSLPRM_TSC_IODEF
|
||||
#error "TSLPRM_TSC_IODEF is not defined."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_TSC_IODEF < 0) || (TSLPRM_TSC_IODEF > 1))
|
||||
#error "TSLPRM_TSC_IODEF is out of range (0 .. 1)."
|
||||
#endif
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#ifndef TSLPRM_TSC_AM
|
||||
#error "TSLPRM_TSC_AM is not defined."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_TSC_AM < 0) || (TSLPRM_TSC_AM > 1))
|
||||
#error "TSLPRM_TSC_AM is out of range (0 .. 1)."
|
||||
#endif
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#ifndef TSLPRM_TSC_SYNC_PIN
|
||||
#error "TSLPRM_TSC_SYNC_PIN is not defined."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_TSC_SYNC_PIN < 0) || (TSLPRM_TSC_SYNC_PIN > 1))
|
||||
#error "TSLPRM_TSC_SYNC_PIN is out of range (0 .. 1)."
|
||||
#endif
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#ifndef TSLPRM_TSC_SYNC_POL
|
||||
#error "TSLPRM_TSC_SYNC_POL is not defined."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_TSC_SYNC_POL < 0) || (TSLPRM_TSC_SYNC_POL > 1))
|
||||
#error "TSLPRM_TSC_SYNC_POL is out of range (0 .. 1)."
|
||||
#endif
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#ifndef TSLPRM_TSC_USE_SS
|
||||
#error "TSLPRM_TSC_USE_SS is not defined."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_TSC_USE_SS < 0) || (TSLPRM_TSC_USE_SS > 1))
|
||||
#error "TSLPRM_TSC_USE_SS is out of range (0 .. 1)."
|
||||
#endif
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#ifndef TSLPRM_TSC_SSD
|
||||
#error "TSLPRM_TSC_SSD is not defined."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_TSC_SSD < 0) || (TSLPRM_TSC_SSD > 127))
|
||||
#error "TSLPRM_TSC_SSD is out of range (0 .. 127)."
|
||||
#endif
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#ifndef TSLPRM_TSC_SSPSC
|
||||
#error "TSLPRM_TSC_SSPSC is not defined."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_TSC_SSPSC < 0) || (TSLPRM_TSC_SSPSC > 1))
|
||||
#error "TSLPRM_TSC_SSPSC is out of range (0 .. 1)."
|
||||
#endif
|
||||
|
||||
#endif /* __TSL_CHECK_CONFIG_STM32F0XX_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,217 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file tsl_check_config_stm32f3xx.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.3.2
|
||||
* @date 22-January-2013
|
||||
* @brief This file contains the check of all parameters defined in the
|
||||
* STM32F3XX configuration file.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __TSL_CHECK_CONFIG_STM32F3XX_H
|
||||
#define __TSL_CHECK_CONFIG_STM32F3XX_H
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#if ((TSLPRM_TOTAL_CHANNELS < 1) || (TSLPRM_TOTAL_CHANNELS > 24))
|
||||
#error "TSLPRM_TOTAL_CHANNELS is out of range (1 .. 24)."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_TOTAL_BANKS < 1) || (TSLPRM_TOTAL_BANKS > 8))
|
||||
#error "TSLPRM_TOTAL_BANKS is out of range (1 .. 8)."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_TOTAL_TOUCHKEYS < 0) || (TSLPRM_TOTAL_TOUCHKEYS > 24))
|
||||
#error "TSLPRM_TOTAL_TOUCHKEYS is out of range (0 .. 24)."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_TOTAL_TOUCHKEYS_B < 0) || (TSLPRM_TOTAL_TOUCHKEYS_B > 24))
|
||||
#error "TSLPRM_TOTAL_TOUCHKEYS_B is out of range (0 .. 24)."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_TOTAL_LINROTS < 0) || (TSLPRM_TOTAL_LINROTS > 24))
|
||||
#error "TSLPRM_TOTAL_LINROTS is out of range (0 .. 24)."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_TOTAL_LINROTS_B < 0) || (TSLPRM_TOTAL_LINROTS_B > 24))
|
||||
#error "TSLPRM_TOTAL_LINROTS_B is out of range (0 .. 24)."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_TOTAL_OBJECTS < 1) || (TSLPRM_TOTAL_OBJECTS > 24))
|
||||
#error "TSLPRM_TOTAL_OBJECTS is out of range (1 .. 24)."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_TOTAL_TKEYS + TSLPRM_TOTAL_LNRTS) > 24)
|
||||
#error "The Sum of TouchKeys and Linear/Rotary sensors exceeds 24."
|
||||
#endif
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#ifndef TSLPRM_TSC_GPIO_CONFIG
|
||||
#error "TSLPRM_TSC_GPIO_CONFIG is not defined."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_TSC_GPIO_CONFIG < 0) || (TSLPRM_TSC_GPIO_CONFIG > 1))
|
||||
#error "TSLPRM_TSC_GPIO_CONFIG is out of range (0 .. 1)."
|
||||
#endif
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#ifndef TSLPRM_TSC_CTPH
|
||||
#error "TSLPRM_TSC_CTPH is not defined."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_TSC_CTPH < 0) || (TSLPRM_TSC_CTPH > 15))
|
||||
#error "TSLPRM_TSC_CTPH is out of range (0 .. 15)."
|
||||
#endif
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#ifndef TSLPRM_TSC_CTPL
|
||||
#error "TSLPRM_TSC_CTPL is not defined."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_TSC_CTPL < 0) || (TSLPRM_TSC_CTPL > 15))
|
||||
#error "TSLPRM_TSC_CTPL is out of range (0 .. 15)."
|
||||
#endif
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#ifndef TSLPRM_TSC_PGPSC
|
||||
#error "TSLPRM_TSC_PGPSC is not defined."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_TSC_PGPSC < 0) || (TSLPRM_TSC_PGPSC > 7))
|
||||
#error "TSLPRM_TSC_PGPSC is out of range (0 .. 7)."
|
||||
#endif
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#if (TSLPRM_ACQ_MAX > 0) && (TSLPRM_ACQ_MAX < 256)
|
||||
#define TSLPRM_TSC_MCV 0 // 255
|
||||
#endif
|
||||
|
||||
#if (TSLPRM_ACQ_MAX > 255) && (TSLPRM_ACQ_MAX < 512)
|
||||
#define TSLPRM_TSC_MCV 1 // 511
|
||||
#endif
|
||||
|
||||
#if (TSLPRM_ACQ_MAX > 511) && (TSLPRM_ACQ_MAX < 1024)
|
||||
#define TSLPRM_TSC_MCV 2 // 1023
|
||||
#endif
|
||||
|
||||
#if (TSLPRM_ACQ_MAX > 1023) && (TSLPRM_ACQ_MAX < 2048)
|
||||
#define TSLPRM_TSC_MCV 3 // 2047
|
||||
#endif
|
||||
|
||||
#if (TSLPRM_ACQ_MAX > 2047) && (TSLPRM_ACQ_MAX < 4096)
|
||||
#define TSLPRM_TSC_MCV 4 // 4095
|
||||
#endif
|
||||
|
||||
#if (TSLPRM_ACQ_MAX > 4095) && (TSLPRM_ACQ_MAX < 8192)
|
||||
#define TSLPRM_TSC_MCV 5 // 8191
|
||||
#endif
|
||||
|
||||
#if (TSLPRM_ACQ_MAX > 8191)
|
||||
#define TSLPRM_TSC_MCV 6 // 16383
|
||||
#endif
|
||||
|
||||
#ifndef TSLPRM_TSC_MCV
|
||||
#error "TSLPRM_TSC_MCV is not defined."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_TSC_MCV < 0) || (TSLPRM_TSC_MCV > 6))
|
||||
#error "TSLPRM_TSC_MCV is out of range (0 .. 6)."
|
||||
#endif
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#ifndef TSLPRM_TSC_IODEF
|
||||
#error "TSLPRM_TSC_IODEF is not defined."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_TSC_IODEF < 0) || (TSLPRM_TSC_IODEF > 1))
|
||||
#error "TSLPRM_TSC_IODEF is out of range (0 .. 1)."
|
||||
#endif
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#ifndef TSLPRM_TSC_AM
|
||||
#error "TSLPRM_TSC_AM is not defined."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_TSC_AM < 0) || (TSLPRM_TSC_AM > 1))
|
||||
#error "TSLPRM_TSC_AM is out of range (0 .. 1)."
|
||||
#endif
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#ifndef TSLPRM_TSC_SYNC_PIN
|
||||
#error "TSLPRM_TSC_SYNC_PIN is not defined."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_TSC_SYNC_PIN < 0) || (TSLPRM_TSC_SYNC_PIN > 1))
|
||||
#error "TSLPRM_TSC_SYNC_PIN is out of range (0 .. 1)."
|
||||
#endif
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#ifndef TSLPRM_TSC_SYNC_POL
|
||||
#error "TSLPRM_TSC_SYNC_POL is not defined."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_TSC_SYNC_POL < 0) || (TSLPRM_TSC_SYNC_POL > 1))
|
||||
#error "TSLPRM_TSC_SYNC_POL is out of range (0 .. 1)."
|
||||
#endif
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#ifndef TSLPRM_TSC_USE_SS
|
||||
#error "TSLPRM_TSC_USE_SS is not defined."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_TSC_USE_SS < 0) || (TSLPRM_TSC_USE_SS > 1))
|
||||
#error "TSLPRM_TSC_USE_SS is out of range (0 .. 1)."
|
||||
#endif
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#ifndef TSLPRM_TSC_SSD
|
||||
#error "TSLPRM_TSC_SSD is not defined."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_TSC_SSD < 0) || (TSLPRM_TSC_SSD > 127))
|
||||
#error "TSLPRM_TSC_SSD is out of range (0 .. 127)."
|
||||
#endif
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#ifndef TSLPRM_TSC_SSPSC
|
||||
#error "TSLPRM_TSC_SSPSC is not defined."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_TSC_SSPSC < 0) || (TSLPRM_TSC_SSPSC > 1))
|
||||
#error "TSLPRM_TSC_SSPSC is out of range (0 .. 1)."
|
||||
#endif
|
||||
|
||||
#endif /* __TSL_CHECK_CONFIG_STM32F3XX_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,333 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file tsl_check_config_stm32l1xx.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.3.2
|
||||
* @date 22-January-2013
|
||||
* @brief This file contains the check of all parameters defined in the
|
||||
* STM32L1XX configuration file.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __TSL_CHECK_CONFIG_STM32L1XX_H
|
||||
#define __TSL_CHECK_CONFIG_STM32L1XX_H
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#if ((TSLPRM_TOTAL_CHANNELS < 1) || (TSLPRM_TOTAL_CHANNELS > 24))
|
||||
#error "TSLPRM_TOTAL_CHANNELS is out of range (1 .. 24)."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_TOTAL_BANKS < 1) || (TSLPRM_TOTAL_BANKS > 8))
|
||||
#error "TSLPRM_TOTAL_BANKS is out of range (1 .. 8)."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_TOTAL_TOUCHKEYS < 0) || (TSLPRM_TOTAL_TOUCHKEYS > 24))
|
||||
#error "TSLPRM_TOTAL_TOUCHKEYS is out of range (0 .. 24)."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_TOTAL_TOUCHKEYS_B < 0) || (TSLPRM_TOTAL_TOUCHKEYS_B > 24))
|
||||
#error "TSLPRM_TOTAL_TOUCHKEYS_B is out of range (0 .. 24)."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_TOTAL_LINROTS < 0) || (TSLPRM_TOTAL_LINROTS > 24))
|
||||
#error "TSLPRM_TOTAL_LINROTS is out of range (0 .. 24)."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_TOTAL_LINROTS_B < 0) || (TSLPRM_TOTAL_LINROTS_B > 24))
|
||||
#error "TSLPRM_TOTAL_LINROTS_B is out of range (0 .. 24)."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_TOTAL_OBJECTS < 1) || (TSLPRM_TOTAL_OBJECTS > 24))
|
||||
#error "TSLPRM_TOTAL_OBJECTS is out of range (1 .. 24)."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_TOTAL_TKEYS + TSLPRM_TOTAL_LNRTS) > 24)
|
||||
#error "The Sum of TouchKeys and Linear/Rotary sensors exceeds 24."
|
||||
#endif
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#ifndef TSLPRM_USE_SHIELD
|
||||
#error "TSLPRM_USE_SHIELD is not defined."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_USE_SHIELD < 0) || (TSLPRM_USE_SHIELD > 1))
|
||||
#error "TSLPRM_USE_SHIELD is out of range (0 .. 1)."
|
||||
#endif
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#ifndef TSLPRM_IODEF
|
||||
#error "TSLPRM_IODEF is not defined."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_IODEF < 0) || (TSLPRM_IODEF > 1))
|
||||
#error "TSLPRM_IODEF is out of range (0 .. 1)."
|
||||
#endif
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#if defined(STM32L1XX_HD) && !defined(TSLPRM_STM32L1XX_HD_SW)
|
||||
|
||||
#ifndef TSLPRM_TIM_PRESCALER
|
||||
#error "TSLPRM_TIM_PRESCALER is not defined."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_TIM_PRESCALER < 0) || (TSLPRM_TIM_PRESCALER > 65535))
|
||||
#error "TSLPRM_TIM_PRESCALER is out of range (0 .. 65535)."
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#if defined(STM32L1XX_HD) && !defined(TSLPRM_STM32L1XX_HD_SW)
|
||||
|
||||
#ifndef TSLPRM_TIM_RELOAD
|
||||
#error "TSLPRM_TIM_RELOAD is not defined."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_TIM_RELOAD < 4) || (TSLPRM_TIM_RELOAD > 65534))
|
||||
#error "TSLPRM_TIM_RELOAD is out of range (4 .. 65534)."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_TIM_RELOAD % 2) != (0))
|
||||
#error "TSLPRM_TIM_RELOAD is odd and must be even."
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#if defined(STM32L1XX_HD) && defined(TSLPRM_STM32L1XX_HD_SW)
|
||||
|
||||
#ifndef TSLPRM_PROTECT_IO_ACCESS
|
||||
#error "TSLPRM_PROTECT_IO_ACCESS is not defined."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_PROTECT_IO_ACCESS < 0) || (TSLPRM_PROTECT_IO_ACCESS > 1))
|
||||
#error "TSLPRM_PROTECT_IO_ACCESS is out of range (0 .. 1)."
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#if defined(STM32L1XX_HD) && defined(TSLPRM_STM32L1XX_HD_SW)
|
||||
|
||||
#ifndef TSLPRM_USE_GPIOA
|
||||
#error "TSLPRM_USE_GPIOA is not defined."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_USE_GPIOA < 0) || (TSLPRM_USE_GPIOA > 1))
|
||||
#error "TSLPRM_USE_GPIOA is out of range (0 .. 1)."
|
||||
#endif
|
||||
|
||||
#ifndef TSLPRM_USE_GPIOB
|
||||
#error "TSLPRM_USE_GPIOB is not defined."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_USE_GPIOB < 0) || (TSLPRM_USE_GPIOB > 1))
|
||||
#error "TSLPRM_USE_GPIOB is out of range (0 .. 1)."
|
||||
#endif
|
||||
|
||||
#ifndef TSLPRM_USE_GPIOC
|
||||
#error "TSLPRM_USE_GPIOC is not defined."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_USE_GPIOC < 0) || (TSLPRM_USE_GPIOC > 1))
|
||||
#error "TSLPRM_USE_GPIOC is out of range (0 .. 1)."
|
||||
#endif
|
||||
|
||||
#ifndef TSLPRM_USE_GPIOF
|
||||
#error "TSLPRM_USE_GPIOA is not defined."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_USE_GPIOF < 0) || (TSLPRM_USE_GPIOF > 1))
|
||||
#error "TSLPRM_USE_GPIOF is out of range (0 .. 1)."
|
||||
#endif
|
||||
|
||||
#ifndef TSLPRM_USE_GPIOG
|
||||
#error "TSLPRM_USE_GPIOG is not defined."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_USE_GPIOG < 0) || (TSLPRM_USE_GPIOG > 1))
|
||||
#error "TSLPRM_USE_GPIOG is out of range (0 .. 1)."
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#if defined(STM32L1XX_MD)
|
||||
|
||||
#ifndef TSLPRM_PROTECT_IO_ACCESS
|
||||
#error "TSLPRM_PROTECT_IO_ACCESS is not defined."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_PROTECT_IO_ACCESS < 0) || (TSLPRM_PROTECT_IO_ACCESS > 1))
|
||||
#error "TSLPRM_PROTECT_IO_ACCESS is out of range (0 .. 1)."
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#if defined(STM32L1XX_MD)
|
||||
|
||||
#ifndef TSLPRM_USE_GPIOA
|
||||
#error "TSLPRM_USE_GPIOA is not defined."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_USE_GPIOA < 0) || (TSLPRM_USE_GPIOA > 1))
|
||||
#error "TSLPRM_USE_GPIOA is out of range (0 .. 1)."
|
||||
#endif
|
||||
|
||||
#ifndef TSLPRM_USE_GPIOB
|
||||
#error "TSLPRM_USE_GPIOB is not defined."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_USE_GPIOB < 0) || (TSLPRM_USE_GPIOB > 1))
|
||||
#error "TSLPRM_USE_GPIOB is out of range (0 .. 1)."
|
||||
#endif
|
||||
|
||||
#ifndef TSLPRM_USE_GPIOC
|
||||
#error "TSLPRM_USE_GPIOC is not defined."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_USE_GPIOC < 0) || (TSLPRM_USE_GPIOC > 1))
|
||||
#error "TSLPRM_USE_GPIOC is out of range (0 .. 1)."
|
||||
#endif
|
||||
|
||||
#ifndef TSLPRM_USE_GPIOF
|
||||
#error "TSLPRM_USE_GPIOA is not defined."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_USE_GPIOF < 0) || (TSLPRM_USE_GPIOF > 1))
|
||||
#error "TSLPRM_USE_GPIOF is out of range (0 .. 1)."
|
||||
#endif
|
||||
|
||||
#ifndef TSLPRM_USE_GPIOG
|
||||
#error "TSLPRM_USE_GPIOG is not defined."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_USE_GPIOG < 0) || (TSLPRM_USE_GPIOG > 1))
|
||||
#error "TSLPRM_USE_GPIOG is out of range (0 .. 1)."
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#if defined(STM32L1XX_MDP) && !defined(TSLPRM_STM32L1XX_MDP_SW)
|
||||
|
||||
#ifndef TSLPRM_TIM_PRESCALER
|
||||
#error "TSLPRM_TIM_PRESCALER is not defined."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_TIM_PRESCALER < 0) || (TSLPRM_TIM_PRESCALER > 65535))
|
||||
#error "TSLPRM_TIM_PRESCALER is out of range (0 .. 65535)."
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#if defined(STM32L1XX_MDP) && !defined(TSLPRM_STM32L1XX_MDP_SW)
|
||||
|
||||
#ifndef TSLPRM_TIM_RELOAD
|
||||
#error "TSLPRM_TIM_RELOAD is not defined."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_TIM_RELOAD < 4) || (TSLPRM_TIM_RELOAD > 65534))
|
||||
#error "TSLPRM_TIM_RELOAD is out of range (4 .. 65534)."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_TIM_RELOAD % 2) != (0))
|
||||
#error "TSLPRM_TIM_RELOAD is odd and must be even."
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#if defined(STM32L1XX_MDP) && defined(TSLPRM_STM32L1XX_MDP_SW)
|
||||
|
||||
#ifndef TSLPRM_PROTECT_IO_ACCESS
|
||||
#error "TSLPRM_PROTECT_IO_ACCESS is not defined."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_PROTECT_IO_ACCESS < 0) || (TSLPRM_PROTECT_IO_ACCESS > 1))
|
||||
#error "TSLPRM_PROTECT_IO_ACCESS is out of range (0 .. 1)."
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#if defined(STM32L1XX_MDP) && defined(TSLPRM_STM32L1XX_MDP_SW)
|
||||
|
||||
#ifndef TSLPRM_USE_GPIOA
|
||||
#error "TSLPRM_USE_GPIOA is not defined."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_USE_GPIOA < 0) || (TSLPRM_USE_GPIOA > 1))
|
||||
#error "TSLPRM_USE_GPIOA is out of range (0 .. 1)."
|
||||
#endif
|
||||
|
||||
#ifndef TSLPRM_USE_GPIOB
|
||||
#error "TSLPRM_USE_GPIOB is not defined."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_USE_GPIOB < 0) || (TSLPRM_USE_GPIOB > 1))
|
||||
#error "TSLPRM_USE_GPIOB is out of range (0 .. 1)."
|
||||
#endif
|
||||
|
||||
#ifndef TSLPRM_USE_GPIOC
|
||||
#error "TSLPRM_USE_GPIOC is not defined."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_USE_GPIOC < 0) || (TSLPRM_USE_GPIOC > 1))
|
||||
#error "TSLPRM_USE_GPIOC is out of range (0 .. 1)."
|
||||
#endif
|
||||
|
||||
#ifndef TSLPRM_USE_GPIOF
|
||||
#error "TSLPRM_USE_GPIOA is not defined."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_USE_GPIOF < 0) || (TSLPRM_USE_GPIOF > 1))
|
||||
#error "TSLPRM_USE_GPIOF is out of range (0 .. 1)."
|
||||
#endif
|
||||
|
||||
#ifndef TSLPRM_USE_GPIOG
|
||||
#error "TSLPRM_USE_GPIOG is not defined."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_USE_GPIOG < 0) || (TSLPRM_USE_GPIOG > 1))
|
||||
#error "TSLPRM_USE_GPIOG is out of range (0 .. 1)."
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
#endif /* __TSL_CHECK_CONFIG_STM32L1XX_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,270 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file tsl_check_config_stm8tl5x.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.3.2
|
||||
* @date 22-January-2013
|
||||
* @brief This file contains the check of all parameters defined in the
|
||||
* STM8TL5X configuration file.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __TSL_CHECK_CONFIG_STM8TL5X_H
|
||||
#define __TSL_CHECK_CONFIG_STM8TL5X_H
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#if ((TSLPRM_MCU < 0) && (TSLPRM_MCU > 4))
|
||||
#error "The MCU selected is not in the STM8TL5x MCU list !"
|
||||
#endif
|
||||
|
||||
#if (TSLPRM_MCU > 0)
|
||||
#define __MAX_RX 7
|
||||
#else
|
||||
#define __MAX_RX 9
|
||||
#endif
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#if ((TSLPRM_TOTAL_CHANNELS < 1) || (TSLPRM_TOTAL_CHANNELS > 300))
|
||||
#error "TSLPRM_TOTAL_CHANNELS is out of range (1 .. 300)."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_TOTAL_BANKS < 1) || (TSLPRM_TOTAL_BANKS > 15))
|
||||
#error "TSLPRM_TOTAL_BANKS is out of range (1 .. 15)."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_TOTAL_TOUCHKEYS < 0) || (TSLPRM_TOTAL_TOUCHKEYS > 256))
|
||||
#error "TSLPRM_TOTAL_TOUCHKEYS is out of range (0 .. 256)."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_TOTAL_TOUCHKEYS_B < 0) || (TSLPRM_TOTAL_TOUCHKEYS_B > 256))
|
||||
#error "TSLPRM_TOTAL_TOUCHKEYS_B is out of range (0 .. 256)."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_TOTAL_LINROTS < 0) || (TSLPRM_TOTAL_LINROTS > 256))
|
||||
#error "TSLPRM_TOTAL_LINROTS is out of range (0 .. 256)."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_TOTAL_LINROTS_B < 0) || (TSLPRM_TOTAL_LINROTS_B > 256))
|
||||
#error "TSLPRM_TOTAL_LINROTS_B is out of range (0 .. 256)."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_TOTAL_OBJECTS < 1) || (TSLPRM_TOTAL_OBJECTS > 256))
|
||||
#error "TSLPRM_TOTAL_OBJECTS is out of range (1 .. 256)."
|
||||
#endif
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#ifndef TSLPRM_KEY_TARGET_REFERENCE
|
||||
#error "TSLPRM_KEY_TARGET_REFERENCE is not defined."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_KEY_TARGET_REFERENCE < 100) || (TSLPRM_KEY_TARGET_REFERENCE > 2000))
|
||||
#error "TSLPRM_KEY_TARGET_REFERENCE is out of range (100 .. 2000)."
|
||||
#endif
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#ifndef TSLPRM_KEY_TARGET_REFERENCE_ERROR
|
||||
#error "TSLPRM_KEY_TARGET_REFERENCE_ERROR is not defined."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_KEY_TARGET_REFERENCE_ERROR < 1) || (TSLPRM_KEY_TARGET_REFERENCE_ERROR > TSLPRM_KEY_TARGET_REFERENCE))
|
||||
#error "TSLPRM_KEY_TARGET_REFERENCE_ERROR is out of range (1 .. TSLPRM_KEY_TARGET_REFERENCE)."
|
||||
#endif
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#ifndef TSLPRM_PXS_EPCC_FINE_TUNING_ITERATION
|
||||
#error "TSLPRM_PXS_EPCC_FINE_TUNING_ITERATION is not defined."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_PXS_EPCC_FINE_TUNING_ITERATION < 3) || (TSLPRM_PXS_EPCC_FINE_TUNING_ITERATION > 5))
|
||||
#error "TSLPRM_PXS_EPCC_FINE_TUNING_ITERATION is out of range (3 .. 5)."
|
||||
#endif
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#ifndef TSLPRM_KEY_TARGET_ATTENUATION
|
||||
#error "TSLPRM_KEY_TARGET_ATTENUATION is not defined."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_KEY_TARGET_ATTENUATION != 1) && (TSLPRM_KEY_TARGET_ATTENUATION != 2) &&\
|
||||
(TSLPRM_KEY_TARGET_ATTENUATION != 4) && (TSLPRM_KEY_TARGET_ATTENUATION != 8))
|
||||
#error "TSLPRM_KEY_TARGET_ATTENUATION is out of range (1,2,4,8)."
|
||||
#endif
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#ifndef TSLPRM_TOUCHKEY_REFERENCE_RANGE
|
||||
#error "TSLPRM_TOUCHKEY_REFERENCE_RANGE is not defined."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_TOUCHKEY_REFERENCE_RANGE < 1) || (TSLPRM_TOUCHKEY_REFERENCE_RANGE > TSLPRM_KEY_TARGET_REFERENCE))
|
||||
#error "TSLPRM_TOUCHKEY_REFERENCE_RANGE is out of range (1 .. TSLPRM_KEY_TARGET_REFERENCE)."
|
||||
#endif
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#ifndef TSLPRM_LINROT_REFERENCE_RANGE
|
||||
#error "TSLPRM_LINROT_REFERENCE_RANGE is not defined."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_LINROT_REFERENCE_RANGE < 1) || (TSLPRM_LINROT_REFERENCE_RANGE > TSLPRM_KEY_TARGET_REFERENCE))
|
||||
#error "TSLPRM_LINROT_REFERENCE_RANGE is out of range (1 .. TSLPRM_KEY_TARGET_REFERENCE)."
|
||||
#endif
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#ifndef TSLPRM_PXS_HSI
|
||||
#error "TSLPRM_PXS_HSI is not defined."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_PXS_HSI != 16000) && (TSLPRM_PXS_HSI != 8000) && (TSLPRM_PXS_HSI != 4000) && \
|
||||
(TSLPRM_PXS_HSI != 2000) && (TSLPRM_PXS_HSI != 1000) && (TSLPRM_PXS_HSI != 500) && \
|
||||
(TSLPRM_PXS_HSI != 250) && (TSLPRM_PXS_HSI != 125))
|
||||
#error "TSLPRM_PXS_HSI is out of range (16000, 8000, 4000, 2000, 1000, 500, 250, 125)."
|
||||
#endif
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#ifndef TSLPRM_PXS_UP_LENGTH
|
||||
#error "TSLPRM_PXS_UP_LENGTH is not defined."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_PXS_UP_LENGTH < 1) || (TSLPRM_PXS_UP_LENGTH > 7))
|
||||
#error "TSLPRM_PXS_UP_LENGTH is out of range (1 .. 7)."
|
||||
#endif
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#ifndef TSLPRM_PXS_PASS_LENGTH
|
||||
#error "TSLPRM_PXS_PASS_LENGTH is not defined."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_PXS_PASS_LENGTH < 1) || (TSLPRM_PXS_PASS_LENGTH > 7))
|
||||
#error "TSLPRM_PXS_PASS_LENGTH is out of range (1 .. 7)."
|
||||
#endif
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#ifndef TSLPRM_PXS_LOW_POWER_MODE
|
||||
#error "TSLPRM_PXS_LOW_POWER_MODE is not defined."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_PXS_LOW_POWER_MODE != 0) && (TSLPRM_PXS_LOW_POWER_MODE != 1))
|
||||
#error "TSLPRM_PXS_LOW_POWER_MODE is out of range (0 .. 1)."
|
||||
#endif
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#ifndef TSLPRM_PXS_RF_DETECTION
|
||||
#error "TSLPRM_PXS_RF_DETECTION is not defined."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_PXS_RF_DETECTION != 0) && (TSLPRM_PXS_RF_DETECTION != 1))
|
||||
#error "TSLPRM_PXS_RF_DETECTION is out of range (0 .. 1)."
|
||||
#endif
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#ifndef TSLPRM_PXS_SYNCHRONIZE
|
||||
#error "TSLPRM_PXS_SYNCHRONIZE is not defined."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_PXS_SYNCHRONIZE != 0) && (TSLPRM_PXS_SYNCHRONIZE != 1))
|
||||
#error "TSLPRM_PXS_SYNCHRONIZE is out of range (0 .. 1)."
|
||||
#endif
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#ifndef TSLPRM_PXS_SYNCHRO_EDGE
|
||||
#error "TSLPRM_PXS_SYNCHRO_EDGE is not defined."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_PXS_SYNCHRO_EDGE != 0) && (TSLPRM_PXS_SYNCHRO_EDGE != 1))
|
||||
#error "TSLPRM_PXS_SYNCHRO_EDGE is out of range (0 .. 1)."
|
||||
#endif
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#ifndef TSLPRM_PXS_INACTIVE_TX
|
||||
#error "TSLPRM_PXS_INACTIVE_TX is not defined."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_PXS_INACTIVE_TX != 0) && (TSLPRM_PXS_INACTIVE_TX != 1))
|
||||
#error "TSLPRM_PXS_INACTIVE_TX is out of range (0 .. 1)."
|
||||
#endif
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#ifndef TSLPRM_PXS_INACTIVE_RX
|
||||
#error "TSLPRM_PXS_INACTIVE_RX is not defined."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_PXS_INACTIVE_RX != 0) && (TSLPRM_PXS_INACTIVE_RX != 1))
|
||||
#error "TSLPRM_PXS_INACTIVE_RX is out of range (0 .. 1)."
|
||||
#endif
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#ifndef TSLPRM_PXS_RX_COUPLING
|
||||
#error "TSLPRM_PXS_RX_COUPLING is not defined."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_PXS_RX_COUPLING != 0) && (TSLPRM_PXS_RX_COUPLING != 1))
|
||||
#error "TSLPRM_PXS_RX_COUPLING is out of range (0 .. 1)."
|
||||
#endif
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#ifndef TSLPRM_PXS_STAB
|
||||
#error "TSLPRM_PXS_STAB is not defined."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_PXS_STAB != LONG_STAB) && (TSLPRM_PXS_STAB != MEDIUM_STAB) && (TSLPRM_PXS_STAB != SHORT_STAB))
|
||||
#error "TSLPRM_PXS_STAB is out of range (LONG_STAB, MEDIUM_STAB, SHORT_STAB)."
|
||||
#endif
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#ifndef TSLPRM_PXS_BIAS
|
||||
#error "TSLPRM_PXS_BIAS is not defined."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_PXS_BIAS != HIGH_BIAS) && (TSLPRM_PXS_BIAS != MEDIUM_BIAS) && (TSLPRM_PXS_BIAS != LOW_BIAS) && (TSLPRM_PXS_BIAS != VERY_LOW_BIAS))
|
||||
#error "TSLPRM_PXS_BIAS is out of range (HIGH_BIAS, MEDIUM_BIAS, LOW_BIAS, VERY_LOW_BIAS)."
|
||||
#endif
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
|
||||
#ifndef TSLPRM_HIGH_CHANNEL_NB
|
||||
#error "TSLPRM_HIGH_CHANNEL_NB is not defined."
|
||||
#endif
|
||||
|
||||
#if ((TSLPRM_HIGH_CHANNEL_NB < 0) || (TSLPRM_HIGH_CHANNEL_NB > __MAX_RX))
|
||||
#error "TSLPRM_HIGH_CHANNEL_NB is out of range (0..9 for STM8TL53C4, 0..7 for STM8TL53G4)."
|
||||
#endif
|
||||
|
||||
#endif /* __TSL_CHECK_CONFIG_STM8TL5X_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,43 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file tsl_dxs.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.3.2
|
||||
* @date 22-January-2013
|
||||
* @brief This file contains external declarations of the tsl_dxs.c file.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __TSL_DXS_H
|
||||
#define __TSL_DXS_H
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "tsl_object.h"
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
void TSL_dxs_FirstObj(CONST TSL_ObjectGroup_T *objgrp);
|
||||
|
||||
#endif /* __TSL_DXS_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,45 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file tsl_ecs.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.3.2
|
||||
* @date 22-January-2013
|
||||
* @brief This file contains external declarations of the tsl_ecs.c file.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __TSL_ECS_H
|
||||
#define __TSL_ECS_H
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "tsl_object.h"
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
TSL_tKCoeff_T TSL_ecs_CalcK(CONST TSL_ObjectGroup_T *objgrp, TSL_tKCoeff_T k_slow, TSL_tKCoeff_T k_fast);
|
||||
void TSL_ecs_ProcessK(CONST TSL_ObjectGroup_T *objgrp, TSL_tKCoeff_T Kcoeff);
|
||||
TSL_Status_enum_T TSL_ecs_Process(CONST TSL_ObjectGroup_T *objgrp);
|
||||
|
||||
#endif /* __TSL_ECS_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,41 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file tsl_filter.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.3.2
|
||||
* @date 22-January-2013
|
||||
* @brief This file contains external declarations of the tsl_filter.c file.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __TSL_FILTER_H
|
||||
#define __TSL_FILTER_H
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "tsl_acq.h"
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
TSL_tMeas_T TSL_filt_MeasFilter(TSL_tMeas_T measn1, TSL_tMeas_T measn);
|
||||
TSL_tDelta_T TSL_filt_DeltaFilter(TSL_tDelta_T delta);
|
||||
|
||||
#endif /* __TSL_FILTER_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,87 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file tsl_globals.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.3.2
|
||||
* @date 22-January-2013
|
||||
* @brief This file contains external declarations of the tsl_globals.c file.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __TSL_GLOBALS_H
|
||||
#define __TSL_GLOBALS_H
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "tsl_acq.h"
|
||||
#include "tsl_object.h"
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/** Store all global variables shared between the STMTouch Driver and the Application.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
TSL_tTick_ms_T Tick_ms; /**< Incremented each 0.5ms by timing interrupt routine */
|
||||
TSL_tTick_sec_T Tick_sec; /**< Incremented each second by timing interrupt routine */
|
||||
CONST TSL_Bank_T *Bank_Array; /**< Pointer to the array containing all Banks */
|
||||
TSL_tIndex_T This_Bank; /**< Pointer to the current Bank */
|
||||
CONST TSL_Object_T *This_Obj; /**< Pointer to the current Object */
|
||||
#if TSLPRM_USE_ZONE > 0
|
||||
CONST TSL_Zone_T *This_Zone; /**< Pointer to the current Zone */
|
||||
TSL_tIndex_T Index_In_This_Zone; /**< Index in the current Zone */
|
||||
#endif
|
||||
#if TSLPRM_TOTAL_TKEYS > 0
|
||||
CONST TSL_TouchKey_T *This_TKey; /**< Pointer to the current TKey */
|
||||
#endif
|
||||
#if TSLPRM_TOTAL_LNRTS > 0
|
||||
CONST TSL_LinRot_T *This_LinRot; /**< Pointer to the current Linear or Rotary sensor */
|
||||
#endif
|
||||
}
|
||||
TSL_Globals_T;
|
||||
|
||||
/** Store all global parametersshared between the STMTouch Driver and the Application .
|
||||
@warning Only one variable of this structure type must be created and be placed
|
||||
in RAM only.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
TSL_tMeas_T AcqMin; /**< Acquisition minimum limit */
|
||||
TSL_tMeas_T AcqMax; /**< Acquisition maximum limit */
|
||||
TSL_tNb_T NbCalibSamples; /**< Number of Calibration samples */
|
||||
TSL_tTick_sec_T DTO; /**< Detection Time Out */
|
||||
#if TSLPRM_TOTAL_TKEYS > 0
|
||||
CONST TSL_State_T *p_TKeySM; /**< Default state machine for TouchKey sensors */
|
||||
CONST TSL_TouchKeyMethods_T *p_TKeyMT; /**< Default methods for TouchKey sensors */
|
||||
#endif
|
||||
#if TSLPRM_TOTAL_LNRTS > 0
|
||||
CONST TSL_State_T *p_LinRotSM; /**< Default state machine for Linear/Rotary sensors */
|
||||
CONST TSL_LinRotMethods_T *p_LinRotMT; /**< Default methods for Linear/Rotary sensors */
|
||||
#endif
|
||||
}
|
||||
TSL_Params_T;
|
||||
|
||||
/* Exported variables --------------------------------------------------------*/
|
||||
extern TSL_Globals_T TSL_Globals;
|
||||
extern TSL_Params_T TSL_Params;
|
||||
|
||||
#endif /* __TSL_GLOBALS_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,225 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file tsl_linrot.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.3.2
|
||||
* @date 22-January-2013
|
||||
* @brief This file contains external declarations of the tsl_linrot.c file.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __TSL_LINROT_H
|
||||
#define __TSL_LINROT_H
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "tsl_acq.h"
|
||||
#include "tsl_time.h"
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/** Contains all data related to Linear and Rotary sensor.
|
||||
* Variables of this structure type must be placed in RAM only.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
TSL_StateId_enum_T StateId; /**< Current state identifier */
|
||||
TSL_tPosition_T RawPosition; /**< Raw position */
|
||||
TSL_tPosition_T Position; /**< Scaled position */
|
||||
unsigned int Counter : 6; /**< Generic counter for state debounce, calibration & DTO (TSL_tCounter_T) */
|
||||
unsigned int Change : 1; /**< The State is different from the previous one (TSL_StateChange_enum_T) */
|
||||
unsigned int PosChange : 1; /**< The RawPosition/Position is different from the previous one (TSL_StateChange_enum_T) */
|
||||
unsigned int Counter2 : 6; /**< Generic counter for direction debounce (TSL_tCounter_T) */
|
||||
unsigned int DxSLock : 1; /**< The State is locked by the DxS (TSL_Bool_enum_T) */
|
||||
unsigned int Direction : 1; /**< Movement direction (TSL_Bool_enum_T) */
|
||||
}
|
||||
TSL_LinRotData_T;
|
||||
|
||||
/** Contains all parameters related to Linear and Rotary sensor.
|
||||
* Variables of this structure type can be placed in RAM or ROM.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
// Thresholds
|
||||
#if TSLPRM_USE_PROX > 0
|
||||
TSL_tThreshold_T ProxInTh; /**< Proximity state in threshold */
|
||||
TSL_tThreshold_T ProxOutTh; /**< Proximity state out threshold */
|
||||
#endif
|
||||
TSL_tThreshold_T DetectInTh; /**< Detection state in threshold */
|
||||
TSL_tThreshold_T DetectOutTh; /**< Detection state out threshold */
|
||||
TSL_tThreshold_T CalibTh; /**< Calibration state threshold */
|
||||
// Debounce counters
|
||||
TSL_tCounter_T CounterDebCalib; /**< Debounce counter to enter in Calibration state */
|
||||
#if TSLPRM_USE_PROX > 0
|
||||
TSL_tCounter_T CounterDebProx; /**< Debounce counter to enter in Proximity state */
|
||||
#endif
|
||||
TSL_tCounter_T CounterDebDetect; /**< Debounce counter to enter in Detect state */
|
||||
TSL_tCounter_T CounterDebRelease; /**< Debounce counter to enter in Release state */
|
||||
TSL_tCounter_T CounterDebError; /**< Debounce counter to enter in Error state */
|
||||
TSL_tCounter_T CounterDebDirection; /**< Debounce counter for the direction change */
|
||||
// Other parameters
|
||||
TSL_tCounter_T Resolution; /**< Position resolution */
|
||||
TSL_tPosition_T DirChangePos; /**< Direction change position threshold */
|
||||
}
|
||||
TSL_LinRotParam_T;
|
||||
|
||||
/** Contains definition of a Linear and Rotary sensor.
|
||||
* Variables of this structure type can be placed in RAM or ROM.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
TSL_LinRotData_T *p_Data; /**< Data (state id, counter, flags, ...) */
|
||||
TSL_LinRotParam_T *p_Param; /**< Parameters (thresholds, debounce, ...) */
|
||||
TSL_ChannelData_T *p_ChD; /**< First Channel Data (Meas, Ref, Delta, ...) */
|
||||
TSL_tNb_T NbChannels; /**< Number of channels */
|
||||
CONST uint16_t *p_DeltaCoeff; /**< Coefficient to apply on Delta */
|
||||
CONST TSL_tsignPosition_T *p_PosOff; /**< Position offset table */
|
||||
TSL_tIndex_T SctComp; /**< Sector Computation */
|
||||
TSL_tIndex_T PosCorr; /**< Position Correction */
|
||||
CONST TSL_State_T *p_SM; /**< State Machine */
|
||||
CONST TSL_LinRotMethods_T *p_Methods; /**< Methods */
|
||||
}
|
||||
TSL_LinRot_T;
|
||||
|
||||
/** Contains definition of a Basic Linear and Rotary sensor.
|
||||
* Variables of this structure type can be placed in RAM or ROM.
|
||||
* Basic sensor does not contain its own state machine and methods. It used
|
||||
* default ones instead to gain memory space.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
TSL_LinRotData_T *p_Data; /**< Data (state id, counter, flags, ...) */
|
||||
TSL_LinRotParam_T *p_Param; /**< Parameters (thresholds, debounce, ...) */
|
||||
TSL_ChannelData_T *p_ChD; /**< First Channel Data (Meas, Ref, Delta, ...) */
|
||||
TSL_tNb_T NbChannels; /**< Number of channels */
|
||||
CONST uint16_t *p_DeltaCoeff; /**< Coefficient to apply on Delta */
|
||||
CONST TSL_tsignPosition_T *p_PosOff; /**< Position offset table */
|
||||
TSL_tIndex_T SctComp; /**< Sector Computation */
|
||||
TSL_tIndex_T PosCorr; /**< Position Correction */
|
||||
}
|
||||
TSL_LinRotB_T;
|
||||
|
||||
/* Exported variables --------------------------------------------------------*/
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
// "Object methods" functions
|
||||
void TSL_linrot_Init(void);
|
||||
void TSL_linrot_Process(void);
|
||||
TSL_Status_enum_T TSL_linrot_CalcPos(void);
|
||||
|
||||
// Utility functions
|
||||
void TSL_linrot_SetStateCalibration(TSL_tCounter_T delay);
|
||||
void TSL_linrot_SetStateOff(void);
|
||||
#if !defined(TSLPRM_STM8TL5X) && !defined(STM8TL5X)
|
||||
void TSL_linrot_SetStateBurstOnly(void);
|
||||
#endif
|
||||
TSL_StateId_enum_T TSL_linrot_GetStateId(void);
|
||||
TSL_StateMask_enum_T TSL_linrot_GetStateMask(void);
|
||||
TSL_tNb_T TSL_linrot_IsChanged(void);
|
||||
|
||||
// State machine functions
|
||||
void TSL_linrot_CalibrationStateProcess(void);
|
||||
void TSL_linrot_DebCalibrationStateProcess(void);
|
||||
void TSL_linrot_ReleaseStateProcess(void);
|
||||
void TSL_linrot_DebReleaseProxStateProcess(void);
|
||||
void TSL_linrot_DebReleaseDetectStateProcess(void);
|
||||
void TSL_linrot_DebReleaseTouchStateProcess(void);
|
||||
void TSL_linrot_ProxStateProcess(void);
|
||||
void TSL_linrot_DebProxStateProcess(void);
|
||||
void TSL_linrot_DebProxDetectStateProcess(void);
|
||||
void TSL_linrot_DebProxTouchStateProcess(void);
|
||||
void TSL_linrot_DetectStateProcess(void);
|
||||
void TSL_linrot_DebDetectStateProcess(void);
|
||||
void TSL_linrot_TouchStateProcess(void);
|
||||
void TSL_linrot_DebTouchStateProcess(void);
|
||||
void TSL_linrot_ErrorStateProcess(void);
|
||||
void TSL_linrot_DebErrorStateProcess(void);
|
||||
void TSL_linrot_OffStateProcess(void);
|
||||
|
||||
// Position offset constant tables and corrections
|
||||
|
||||
extern CONST TSL_tsignPosition_T TSL_POSOFF_3CH_LIN_M1[3][3];
|
||||
extern CONST TSL_tsignPosition_T TSL_POSOFF_3CH_LIN_M2[3][3];
|
||||
extern CONST TSL_tsignPosition_T TSL_POSOFF_3CH_LIN_H[3][3];
|
||||
extern CONST TSL_tsignPosition_T TSL_POSOFF_3CH_ROT_M[3][3];
|
||||
|
||||
extern CONST TSL_tsignPosition_T TSL_POSOFF_4CH_LIN_M1[4][4];
|
||||
extern CONST TSL_tsignPosition_T TSL_POSOFF_4CH_LIN_M2[4][4];
|
||||
extern CONST TSL_tsignPosition_T TSL_POSOFF_4CH_LIN_H[4][4];
|
||||
extern CONST TSL_tsignPosition_T TSL_POSOFF_4CH_ROT_M[4][4];
|
||||
|
||||
extern CONST TSL_tsignPosition_T TSL_POSOFF_5CH_LIN_M1[5][5];
|
||||
extern CONST TSL_tsignPosition_T TSL_POSOFF_5CH_LIN_M2[5][5];
|
||||
extern CONST TSL_tsignPosition_T TSL_POSOFF_5CH_LIN_H[5][5];
|
||||
extern CONST TSL_tsignPosition_T TSL_POSOFF_5CH_ROT_M[5][5];
|
||||
extern CONST TSL_tsignPosition_T TSL_POSOFF_5CH_ROT_D[5][5];
|
||||
|
||||
extern CONST TSL_tsignPosition_T TSL_POSOFF_6CH_LIN_M1[6][6];
|
||||
extern CONST TSL_tsignPosition_T TSL_POSOFF_6CH_LIN_M2[6][6];
|
||||
extern CONST TSL_tsignPosition_T TSL_POSOFF_6CH_LIN_H[6][6];
|
||||
extern CONST TSL_tsignPosition_T TSL_POSOFF_6CH_ROT_M[6][6];
|
||||
|
||||
#define TSL_SCTCOMP_3CH_LIN_M1 (128)
|
||||
#define TSL_POSCORR_3CH_LIN_M1 (64)
|
||||
#define TSL_SCTCOMP_3CH_LIN_M2 (256)
|
||||
#define TSL_POSCORR_3CH_LIN_M2 (256)
|
||||
|
||||
#define TSL_SCTCOMP_3CH_LIN_H (128)
|
||||
#define TSL_POSCORR_3CH_LIN_H (128)
|
||||
|
||||
#define TSL_SCTCOMP_3CH_ROT_M (85)
|
||||
|
||||
#define TSL_SCTCOMP_4CH_LIN_M1 (85)
|
||||
#define TSL_POSCORR_4CH_LIN_M1 (43)
|
||||
#define TSL_SCTCOMP_4CH_LIN_M2 (128)
|
||||
#define TSL_POSCORR_4CH_LIN_M2 (128)
|
||||
|
||||
#define TSL_SCTCOMP_4CH_LIN_H (85)
|
||||
#define TSL_POSCORR_4CH_LIN_H (85)
|
||||
|
||||
#define TSL_SCTCOMP_4CH_ROT_M (64)
|
||||
|
||||
#define TSL_SCTCOMP_5CH_LIN_M1 (64)
|
||||
#define TSL_POSCORR_5CH_LIN_M1 (32)
|
||||
#define TSL_SCTCOMP_5CH_LIN_M2 (85)
|
||||
#define TSL_POSCORR_5CH_LIN_M2 (85)
|
||||
|
||||
#define TSL_SCTCOMP_5CH_LIN_H (64)
|
||||
#define TSL_POSCORR_5CH_LIN_H (64)
|
||||
|
||||
#define TSL_SCTCOMP_5CH_ROT_M (51)
|
||||
|
||||
#define TSL_SCTCOMP_5CH_ROT_D (26)
|
||||
|
||||
#define TSL_SCTCOMP_6CH_LIN_M1 (51)
|
||||
#define TSL_POSCORR_6CH_LIN_M1 (25)
|
||||
#define TSL_SCTCOMP_6CH_LIN_M2 (64)
|
||||
#define TSL_POSCORR_6CH_LIN_M2 (64)
|
||||
|
||||
#define TSL_SCTCOMP_6CH_LIN_H (51)
|
||||
#define TSL_POSCORR_6CH_LIN_H (51)
|
||||
|
||||
#define TSL_SCTCOMP_6CH_ROT_M (43)
|
||||
|
||||
#endif /* __TSL_LINROT_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,87 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file tsl_object.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.3.2
|
||||
* @date 22-January-2013
|
||||
* @brief This file contains external declarations of the tsl_object.c file.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __TSL_OBJECT_H
|
||||
#define __TSL_OBJECT_H
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "tsl_touchkey.h"
|
||||
#include "tsl_linrot.h"
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
#define TSL_OBJ_TYPE_TKEY_MASK (0x10) /**< TouchKey object mask */
|
||||
#define TSL_OBJ_TYPE_LINROT_MASK (0x20) /**< Linear and Rotary objects mask */
|
||||
#define TSL_OBJ_TYPE_TRACKNAV_MASK (0x40) /**< TrackPad and NaviPad objects mask */
|
||||
|
||||
/** Contains all different kinds of sensors.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TSL_OBJ_TOUCHKEY = (TSL_OBJ_TYPE_TKEY_MASK + 0), /**< Normal TouchKey */
|
||||
TSL_OBJ_TOUCHKEYB = (TSL_OBJ_TYPE_TKEY_MASK + 1), /**< Basic TouchKey */
|
||||
TSL_OBJ_LINEAR = (TSL_OBJ_TYPE_LINROT_MASK + 0), /**< Normal Linear sensor */
|
||||
TSL_OBJ_LINEARB = (TSL_OBJ_TYPE_LINROT_MASK + 1), /**< Basic Linear sensor */
|
||||
TSL_OBJ_ROTARY = (TSL_OBJ_TYPE_LINROT_MASK + 2), /**< Normal Rotary sensor */
|
||||
TSL_OBJ_ROTARYB = (TSL_OBJ_TYPE_LINROT_MASK + 3), /**< Basic Rotary sensor */
|
||||
TSL_OBJ_TRACKPAD = (TSL_OBJ_TYPE_TRACKNAV_MASK + 0), /**< TrackPad sensor */
|
||||
TSL_OBJ_NAVIPAD = (TSL_OBJ_TYPE_TRACKNAV_MASK + 1) /**< NaviPad sensor */
|
||||
}
|
||||
TSL_ObjectType_enum_T;
|
||||
|
||||
/** Contains the definition of an Object.
|
||||
* Variables of this structure type can be placed in RAM or ROM.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
TSL_ObjectType_enum_T Type; /**< Object type */
|
||||
void *Elmt; /**< Pointer to the object */
|
||||
}
|
||||
TSL_Object_T;
|
||||
|
||||
/** Contains the definition of a Group of Objects.
|
||||
* Variables of this structure type must be placed in RAM only.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
CONST TSL_Object_T *p_Obj; /**< Pointer to the first object */
|
||||
TSL_tNb_T NbObjects; /**< Number of objects in the group */
|
||||
TSL_tNb_T StateMask; /**< "OR" of all objects state mask */
|
||||
TSL_StateChange_enum_T Change; /**< The State is different from the previous one */
|
||||
}
|
||||
TSL_ObjectGroup_T;
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
void TSL_obj_GroupInit(TSL_ObjectGroup_T *objgrp);
|
||||
void TSL_obj_GroupProcess(TSL_ObjectGroup_T *objgrp);
|
||||
void TSL_obj_SetGlobalObj(CONST TSL_Object_T *pobj);
|
||||
|
||||
#endif /* __TSL_OBJECT_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,81 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file tsl_time.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.3.2
|
||||
* @date 22-January-2013
|
||||
* @brief This file contains external declarations of the tsl_time.c file.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __TSL_TIME_H
|
||||
#define __TSL_TIME_H
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
|
||||
#if defined(STM8TL5X)
|
||||
#include "tsl_acq_stm8tl5x.h"
|
||||
#include "tsl_time_stm8tl5x.h"
|
||||
#endif
|
||||
|
||||
#if defined(STM32F0XX)
|
||||
#include "tsl_acq_stm32f0xx.h"
|
||||
#include "tsl_time_stm32f0xx.h"
|
||||
#endif
|
||||
|
||||
#if defined(STM32F30X) || defined(STM32F37X)
|
||||
#include "tsl_acq_stm32f3xx.h"
|
||||
#include "tsl_time_stm32f3xx.h"
|
||||
#endif
|
||||
|
||||
#if defined(STM32L1XX_HD)
|
||||
#if defined(TSLPRM_STM32L1XX_SW_ACQ)
|
||||
#include "tsl_acq_stm32l1xx_sw.h" // Software acquisition
|
||||
#else
|
||||
#include "tsl_acq_stm32l1xx_hw.h" // Hardware acquisition with Timers (default)
|
||||
#endif
|
||||
#include "tsl_time_stm32l1xx.h"
|
||||
#endif
|
||||
|
||||
#if defined(STM32L1XX_MD)
|
||||
#include "tsl_acq_stm32l1xx_sw.h" // Software acquisition only
|
||||
#include "tsl_time_stm32l1xx.h"
|
||||
#endif
|
||||
|
||||
#if defined(STM32L1XX_MDP)
|
||||
#if defined(TSLPRM_STM32L1XX_SW_ACQ)
|
||||
#include "tsl_acq_stm32l1xx_sw.h" // Software acquisition
|
||||
#else
|
||||
#include "tsl_acq_stm32l1xx_hw.h" // Hardware acquisition with Timers (default)
|
||||
#endif
|
||||
#include "tsl_time_stm32l1xx.h"
|
||||
#endif
|
||||
|
||||
/* Exported functions ------------------------------------------------------- */
|
||||
|
||||
void TSL_tim_ProcessIT(void);
|
||||
TSL_Status_enum_T TSL_tim_CheckDelay_ms(TSL_tTick_ms_T delay_ms, __IO TSL_tTick_ms_T *last_tick);
|
||||
TSL_Status_enum_T TSL_tim_CheckDelay_sec(TSL_tTick_sec_T delay_sec, __IO TSL_tTick_sec_T *last_tick);
|
||||
void TSL_CallBack_TimerTick(void);
|
||||
|
||||
#endif /* __TSL_TIME_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,43 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file tsl_time_stm32f0xx.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.3.2
|
||||
* @date 22-January-2013
|
||||
* @brief This file contains external declarations of the tsl_time_stm32f0xx.c file.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __TSL_TIME_STM32F0XX_H
|
||||
#define __TSL_TIME_STM32F0XX_H
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32f0xx.h"
|
||||
#include "tsl_conf_stm32f0xx.h"
|
||||
#include "tsl_types.h"
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
TSL_Status_enum_T TSL_tim_Init(void);
|
||||
|
||||
#endif /* __TSL_TIME_STM32F0XX_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,48 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file tsl_time_stm32f3xx.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.3.2
|
||||
* @date 22-January-2013
|
||||
* @brief This file contains external declarations of the tsl_time_stm32f3xx.c file.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __TSL_TIME_STM32F3XX_H
|
||||
#define __TSL_TIME_STM32F3XX_H
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#if defined(STM32F30X)
|
||||
#include "stm32f30x.h"
|
||||
#endif
|
||||
#if defined(STM32F37X)
|
||||
#include "stm32f37x.h"
|
||||
#endif
|
||||
#include "tsl_conf_stm32f3xx.h"
|
||||
#include "tsl_types.h"
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
TSL_Status_enum_T TSL_tim_Init(void);
|
||||
|
||||
#endif /* __TSL_TIME_STM32F3XX_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,43 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file tsl_time_stm32l1xx.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.3.2
|
||||
* @date 22-January-2013
|
||||
* @brief This file contains external declarations of the tsl_time_stm32l1xx.c file.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __TSL_TIME_STM32L1XX_H
|
||||
#define __TSL_TIME_STM32L1XX_H
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm32l1xx.h"
|
||||
#include "tsl_conf_stm32l1xx.h"
|
||||
#include "tsl_types.h"
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
TSL_Status_enum_T TSL_tim_Init(void);
|
||||
|
||||
#endif /* __TSL_TIME_STM32L1XX_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,43 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file tsl_time_stm8tl5x.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.3.2
|
||||
* @date 22-January-2013
|
||||
* @brief This file contains external declarations of the tsl_time_stm8tl5x.c file.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __TSL_TIME_STM8TL5X_H
|
||||
#define __TSL_TIME_STM8TL5X_H
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "stm8tl5x.h"
|
||||
#include "tsl_conf_stm8tl5x.h"
|
||||
#include "tsl_types.h"
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
TSL_Status_enum_T TSL_tim_Init(void);
|
||||
|
||||
#endif /* __TSL_TIME_STM8TL5X_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,138 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file tsl_touchkey.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.3.2
|
||||
* @date 22-January-2013
|
||||
* @brief This file contains external declarations of the tsl_touchkey.c file.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __TSL_TOUCHKEY_H
|
||||
#define __TSL_TOUCHKEY_H
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "tsl_acq.h"
|
||||
#include "tsl_time.h"
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/** Contains all data related to TouchKey sensor.
|
||||
* Variables of this structure type must be placed in RAM only.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
TSL_StateId_enum_T StateId; /**< Current state identifier */
|
||||
unsigned int Counter : 6; /**< Generic counter for debounce, calibration & DTO */
|
||||
unsigned int Change : 1; /**< The State is different from the previous one (TSL_StateChange_enum_T) */
|
||||
unsigned int DxSLock : 1; /**< The State is locked by the DxS (TSL_Bool_enum_T) */
|
||||
}
|
||||
TSL_TouchKeyData_T;
|
||||
|
||||
/** Contains all parameters related to TouchKey sensor.
|
||||
* Variables of this structure type can be placed in RAM or ROM.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
#if TSLPRM_USE_PROX > 0
|
||||
TSL_tThreshold_T ProxInTh; /**< Proximity in threshold */
|
||||
TSL_tThreshold_T ProxOutTh; /**< Proximity out threshold */
|
||||
#endif
|
||||
TSL_tThreshold_T DetectInTh; /**< Detection in threshold */
|
||||
TSL_tThreshold_T DetectOutTh; /**< Detection out threshold */
|
||||
TSL_tThreshold_T CalibTh; /**< Calibration threshold */
|
||||
TSL_tCounter_T CounterDebCalib; /**< Debounce counter to enter in Calibration state */
|
||||
#if TSLPRM_USE_PROX > 0
|
||||
TSL_tCounter_T CounterDebProx; /**< Debounce counter to enter in Proximity state */
|
||||
#endif
|
||||
TSL_tCounter_T CounterDebDetect; /**< Debounce counter to enter in Detect state */
|
||||
TSL_tCounter_T CounterDebRelease; /**< Debounce counter to enter in Release state */
|
||||
TSL_tCounter_T CounterDebError; /**< Debounce counter to enter in Error state */
|
||||
}
|
||||
TSL_TouchKeyParam_T;
|
||||
|
||||
/** Contains definition of a TouchKey sensor.
|
||||
* Variables of this structure type can be placed in RAM or ROM.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
TSL_TouchKeyData_T *p_Data; /**< Data (state id, counter, flags, ...) */
|
||||
TSL_TouchKeyParam_T *p_Param; /**< Parameters (thresholds, debounce, ...) */
|
||||
TSL_ChannelData_T *p_ChD; /**< Channel Data (Meas, Ref, Delta, ...) */
|
||||
CONST TSL_State_T *p_SM; /**< State Machine */
|
||||
CONST TSL_TouchKeyMethods_T *p_Methods; /**< Methods */
|
||||
}
|
||||
TSL_TouchKey_T;
|
||||
|
||||
/** Contains definition of a Basic TouchKey sensor.
|
||||
* Variables of this structure type can be placed in RAM or ROM.
|
||||
* Basic sensor does not contain its own state machine and methods. It used
|
||||
* default ones instead to gain memory space.
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
TSL_TouchKeyData_T *p_Data; /**< Data (state id, counter, flags, ...) */
|
||||
TSL_TouchKeyParam_T *p_Param; /**< Parameters (thresholds, debounce, ...) */
|
||||
TSL_ChannelData_T *p_ChD; /**< Channel Data (Meas, Ref, Delta, ...) */
|
||||
}
|
||||
TSL_TouchKeyB_T;
|
||||
|
||||
/* Exported variables --------------------------------------------------------*/
|
||||
/* Exported macros -----------------------------------------------------------*/
|
||||
|
||||
/* Exported functions --------------------------------------------------------*/
|
||||
|
||||
// "Object methods" functions
|
||||
void TSL_tkey_Init(void);
|
||||
void TSL_tkey_Process(void);
|
||||
|
||||
// Utility functions
|
||||
void TSL_tkey_SetStateCalibration(TSL_tCounter_T delay);
|
||||
void TSL_tkey_SetStateOff(void);
|
||||
#if !defined(TSLPRM_STM8TL5X) && !defined(STM8TL5X)
|
||||
void TSL_tkey_SetStateBurstOnly(void);
|
||||
#endif
|
||||
TSL_StateId_enum_T TSL_tkey_GetStateId(void);
|
||||
TSL_StateMask_enum_T TSL_tkey_GetStateMask(void);
|
||||
TSL_tNb_T TSL_tkey_IsChanged(void);
|
||||
|
||||
// State machine functions
|
||||
void TSL_tkey_CalibrationStateProcess(void);
|
||||
void TSL_tkey_DebCalibrationStateProcess(void);
|
||||
void TSL_tkey_ReleaseStateProcess(void);
|
||||
void TSL_tkey_DebReleaseProxStateProcess(void);
|
||||
void TSL_tkey_DebReleaseDetectStateProcess(void);
|
||||
void TSL_tkey_DebReleaseTouchStateProcess(void);
|
||||
void TSL_tkey_ProxStateProcess(void);
|
||||
void TSL_tkey_DebProxStateProcess(void);
|
||||
void TSL_tkey_DebProxDetectStateProcess(void);
|
||||
void TSL_tkey_DebProxTouchStateProcess(void);
|
||||
void TSL_tkey_DetectStateProcess(void);
|
||||
void TSL_tkey_DebDetectStateProcess(void);
|
||||
void TSL_tkey_TouchStateProcess(void);
|
||||
void TSL_tkey_DebTouchStateProcess(void);
|
||||
void TSL_tkey_ErrorStateProcess(void);
|
||||
void TSL_tkey_DebErrorStateProcess(void);
|
||||
void TSL_tkey_OffStateProcess(void);
|
||||
|
||||
#endif /* __TSL_TOUCHKEY_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,217 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file tsl_types.h
|
||||
* @author MCD Application Team
|
||||
* @version V1.3.2
|
||||
* @date 22-January-2013
|
||||
* @brief This file contains all general structures definition.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Define to prevent recursive inclusion -------------------------------------*/
|
||||
#ifndef __TSL_TYPES_H
|
||||
#define __TSL_TYPES_H
|
||||
|
||||
/* Exported types ------------------------------------------------------------*/
|
||||
|
||||
/** Generic Boolean status
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TSL_FALSE = 0, /**< A False value */
|
||||
TSL_TRUE = 1 /**< A True value */
|
||||
}
|
||||
TSL_Bool_enum_T;
|
||||
|
||||
/** Generic status returned by functions
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TSL_STATUS_OK = 0, /**< The function has been executed correctly */
|
||||
TSL_STATUS_BUSY = 1, /**< The function is in a Busy state */
|
||||
TSL_STATUS_ERROR = 2 /**< The function has been executed not correctly */
|
||||
} TSL_Status_enum_T;
|
||||
|
||||
/** DataReady status : 1 bit
|
||||
- Used by acquisition to indicate if a new measurement is ready or not.
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TSL_DATA_NOT_READY = 0, /**< No new measurement or measurement treated */
|
||||
TSL_DATA_READY = 1 /**< A new measurement is ready */
|
||||
} TSL_DataReady_enum_T;
|
||||
|
||||
/** State change status
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TSL_STATE_NOT_CHANGED = 0, /**< The object has the same state */
|
||||
TSL_STATE_CHANGED = 1 /**< The object has changed of state */
|
||||
} TSL_StateChange_enum_T;
|
||||
|
||||
#define TSL_ACQ_STATUS_ERROR_MASK (0x02) /**< Associated to TSL_AcqStatus_enum_T */
|
||||
|
||||
/** Acquisition status
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TSL_ACQ_STATUS_OK = 0, /**< The acquisition is correct */
|
||||
TSL_ACQ_STATUS_NOISE = 1, /**< Noise detected during the acquisition */
|
||||
TSL_ACQ_STATUS_ERROR_MIN = TSL_ACQ_STATUS_ERROR_MASK, /**< The measure is below the minimum threshold */
|
||||
TSL_ACQ_STATUS_ERROR_MAX = (TSL_ACQ_STATUS_ERROR_MASK | 0x01) /**< The measure is above the maximum threshold */
|
||||
} TSL_AcqStatus_enum_T;
|
||||
|
||||
/** Bank status
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TSL_BANK_STATUS_DISABLED = 0, /**< The bank is disabled */
|
||||
TSL_BANK_STATUS_ENABLED = 1 /**< The bank is enabled */
|
||||
} TSL_BankStatus_enum_T;
|
||||
|
||||
/** Zone status
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TSL_ZONE_STATUS_DISABLED = 0, /**< The zone is disabled */
|
||||
TSL_ZONE_STATUS_ENABLED = 1 /**< The zone is enabled */
|
||||
}TSL_ZoneStatus_enum_T;
|
||||
|
||||
#define TSL_OBJ_STATUS_ACQ_MASK (0x01) /**< Associated to TSL_ObjStatus_enum_T */
|
||||
#define TSL_OBJ_STATUS_BURST_MASK (0x02) /**< Associated to TSL_ObjStatus_enum_T */
|
||||
|
||||
/** Object status
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
TSL_OBJ_STATUS_OFF = 0, /**< No burst and no acquisition */
|
||||
TSL_OBJ_STATUS_BURST_ONLY = TSL_OBJ_STATUS_BURST_MASK, /**< Burst only */
|
||||
TSL_OBJ_STATUS_ON = (TSL_OBJ_STATUS_BURST_MASK | TSL_OBJ_STATUS_ACQ_MASK) /**< Burst and acquisition */
|
||||
} TSL_ObjStatus_enum_T;
|
||||
|
||||
#define TSL_STATE_ERROR_BIT_MASK (0x80) /**< Associated to TSL_StateMask_enum_T */
|
||||
#define TSL_STATE_OFF_BIT_MASK (0x40) /**< Associated to TSL_StateMask_enum_T */
|
||||
#define TSL_STATE_DEBOUNCE_BIT_MASK (0x20) /**< Associated to TSL_StateMask_enum_T */
|
||||
#define TSL_STATE_CALIB_BIT_MASK (0x10) /**< Associated to TSL_StateMask_enum_T */
|
||||
#define TSL_STATE_TOUCH_BIT_MASK (0x08) /**< Associated to TSL_StateMask_enum_T */
|
||||
#define TSL_STATE_DETECT_BIT_MASK (0x04) /**< Associated to TSL_StateMask_enum_T */
|
||||
#define TSL_STATE_PROX_BIT_MASK (0x02) /**< Associated to TSL_StateMask_enum_T */
|
||||
#define TSL_STATE_RELEASE_BIT_MASK (0x01) /**< Associated to TSL_StateMask_enum_T */
|
||||
|
||||
/** Object state masks
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
// Calibration states
|
||||
TSL_STATEMASK_CALIB = TSL_STATE_CALIB_BIT_MASK, /**< 0x10 */
|
||||
TSL_STATEMASK_DEB_CALIB = (TSL_STATE_DEBOUNCE_BIT_MASK | TSL_STATE_CALIB_BIT_MASK), /**< 0x30 */
|
||||
// Release states
|
||||
TSL_STATEMASK_RELEASE = TSL_STATE_RELEASE_BIT_MASK, /**< 0x01 */
|
||||
TSL_STATEMASK_DEB_RELEASE_PROX = (TSL_STATE_DEBOUNCE_BIT_MASK | TSL_STATE_RELEASE_BIT_MASK | TSL_STATE_PROX_BIT_MASK), /**< 0x23 */
|
||||
TSL_STATEMASK_DEB_RELEASE_DETECT = (TSL_STATE_DEBOUNCE_BIT_MASK | TSL_STATE_RELEASE_BIT_MASK | TSL_STATE_DETECT_BIT_MASK), /**< 0x25 */
|
||||
TSL_STATEMASK_DEB_RELEASE_TOUCH = (TSL_STATE_DEBOUNCE_BIT_MASK | TSL_STATE_RELEASE_BIT_MASK | TSL_STATE_TOUCH_BIT_MASK), /**< 0x29 */
|
||||
// Proximity states
|
||||
TSL_STATEMASK_PROX = TSL_STATE_PROX_BIT_MASK, /**< 0x02 */
|
||||
TSL_STATEMASK_DEB_PROX = (TSL_STATE_DEBOUNCE_BIT_MASK | TSL_STATE_PROX_BIT_MASK), /**< 0x22 */
|
||||
TSL_STATEMASK_DEB_PROX_DETECT = (TSL_STATE_DEBOUNCE_BIT_MASK | TSL_STATE_PROX_BIT_MASK | TSL_STATE_DETECT_BIT_MASK), /**< 0x26 */
|
||||
TSL_STATEMASK_DEB_PROX_TOUCH = (TSL_STATE_DEBOUNCE_BIT_MASK | TSL_STATE_PROX_BIT_MASK | TSL_STATE_TOUCH_BIT_MASK), /**< 0x2A */
|
||||
// Detect states
|
||||
TSL_STATEMASK_DETECT = TSL_STATE_DETECT_BIT_MASK, /**< 0x04 */
|
||||
TSL_STATEMASK_DEB_DETECT = (TSL_STATE_DEBOUNCE_BIT_MASK | TSL_STATE_DETECT_BIT_MASK), /**< 0x24 */
|
||||
// Touch state
|
||||
TSL_STATEMASK_TOUCH = TSL_STATE_TOUCH_BIT_MASK, /**< 0x08 */
|
||||
// Error states
|
||||
TSL_STATEMASK_ERROR = TSL_STATE_ERROR_BIT_MASK, /**< 0x80 */
|
||||
TSL_STATEMASK_DEB_ERROR_CALIB = (TSL_STATE_DEBOUNCE_BIT_MASK | TSL_STATE_ERROR_BIT_MASK | TSL_STATE_CALIB_BIT_MASK), /**< 0xB0 */
|
||||
TSL_STATEMASK_DEB_ERROR_RELEASE = (TSL_STATE_DEBOUNCE_BIT_MASK | TSL_STATE_ERROR_BIT_MASK | TSL_STATE_RELEASE_BIT_MASK), /**< 0xA1 */
|
||||
TSL_STATEMASK_DEB_ERROR_PROX = (TSL_STATE_DEBOUNCE_BIT_MASK | TSL_STATE_ERROR_BIT_MASK | TSL_STATE_PROX_BIT_MASK), /**< 0xA2 */
|
||||
TSL_STATEMASK_DEB_ERROR_DETECT = (TSL_STATE_DEBOUNCE_BIT_MASK | TSL_STATE_ERROR_BIT_MASK | TSL_STATE_DETECT_BIT_MASK), /**< 0xA4 */
|
||||
TSL_STATEMASK_DEB_ERROR_TOUCH = (TSL_STATE_DEBOUNCE_BIT_MASK | TSL_STATE_ERROR_BIT_MASK | TSL_STATE_TOUCH_BIT_MASK), /**< 0xA8 */
|
||||
// OFF state
|
||||
TSL_STATEMASK_OFF = TSL_STATE_OFF_BIT_MASK, /**< 0x40 */
|
||||
// Other states not associated to a state id
|
||||
TSL_STATEMASK_ACTIVE = (TSL_STATE_PROX_BIT_MASK | TSL_STATE_DETECT_BIT_MASK | TSL_STATE_TOUCH_BIT_MASK | TSL_STATE_CALIB_BIT_MASK | TSL_STATE_DEBOUNCE_BIT_MASK), /**< 0x3E */
|
||||
TSL_STATEMASK_UNKNOWN = 0 /**< 0x00 */
|
||||
} TSL_StateMask_enum_T;
|
||||
|
||||
/** Object state identifiers
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
// Calibration states
|
||||
TSL_STATEID_CALIB = 0, /**< 0 - Object is in Calibration */
|
||||
TSL_STATEID_DEB_CALIB = 1, /**< 1 - Object is in Debounce Calibration */
|
||||
// Release states
|
||||
TSL_STATEID_RELEASE = 2, /**< 2 - Object is released */
|
||||
TSL_STATEID_DEB_RELEASE_PROX = 3, /**< 3 - Object is in Debounce Release from Proximity state */
|
||||
TSL_STATEID_DEB_RELEASE_DETECT = 4, /**< 4 - Object is in Debounce Release from Detect state */
|
||||
TSL_STATEID_DEB_RELEASE_TOUCH = 5, /**< 5 - Object is in Debounce Release from Touch state */
|
||||
// Proximity states
|
||||
TSL_STATEID_PROX = 6, /**< 6 - Object is in Proximity */
|
||||
TSL_STATEID_DEB_PROX = 7, /**< 7 - Object is in Debounce Proximity from Release state */
|
||||
TSL_STATEID_DEB_PROX_DETECT = 8, /**< 8 - Object is in Debounce Proximity from Detect state */
|
||||
TSL_STATEID_DEB_PROX_TOUCH = 9, /**< 9 - Object is in Debounce Proximity from Detect state */
|
||||
// Detect states
|
||||
TSL_STATEID_DETECT = 10, /**< 10 - Object is in Detect */
|
||||
TSL_STATEID_DEB_DETECT = 11, /**< 11 - Object is in Debounce Detect */
|
||||
// Touch state
|
||||
TSL_STATEID_TOUCH = 12, /**< 12 - Object is in Touch */
|
||||
// Error states
|
||||
TSL_STATEID_ERROR = 13, /**< 13 - Object is in Error */
|
||||
TSL_STATEID_DEB_ERROR_CALIB = 14, /**< 14 - Object is in Debounce Error from Calibration */
|
||||
TSL_STATEID_DEB_ERROR_RELEASE = 15, /**< 15 - Object is in Debounce Error from Release */
|
||||
TSL_STATEID_DEB_ERROR_PROX = 16, /**< 16 - Object is in Debounce Error from Proximity */
|
||||
TSL_STATEID_DEB_ERROR_DETECT = 17, /**< 17 - Object is in Debounce Error from Detect */
|
||||
TSL_STATEID_DEB_ERROR_TOUCH = 18, /**< 18 - Object is in Debounce Error from Touch */
|
||||
// Other states
|
||||
TSL_STATEID_OFF = 19 /**< 19 - Object is OFF (no burst, no acquisition) */
|
||||
} TSL_StateId_enum_T;
|
||||
|
||||
/** Object state
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
TSL_StateMask_enum_T StateMask; /**< Current state mask */
|
||||
void(* StateFunc)(void); /**< Function executed in the state */
|
||||
}
|
||||
TSL_State_T;
|
||||
|
||||
/** Touchkey methods
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
void(* Init)(void); /**< Used to initialize the TouchKey sensor */
|
||||
void(* Process)(void); /**< Used to execute the TouchKey sensor state machine */
|
||||
}
|
||||
TSL_TouchKeyMethods_T;
|
||||
|
||||
/** Linear/Rotary methods
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
void(* Init)(void); /**< Used to initialize the Linear/Rotary sensor */
|
||||
void(* Process)(void); /**< Used to execute the Linear/Rotary sensor state machine */
|
||||
TSL_Status_enum_T(* CalcPosition)(void); /**< Used to calculate the Linear/Rotary sensor position */
|
||||
}
|
||||
TSL_LinRotMethods_T;
|
||||
|
||||
#endif /* __TSL_TYPES_H */
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,61 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file tsl.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.3.2
|
||||
* @date 22-January-2013
|
||||
* @brief This file contains the STMTouch Driver main functions.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "tsl.h"
|
||||
|
||||
/* Private typedefs ----------------------------------------------------------*/
|
||||
/* Private defines -----------------------------------------------------------*/
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private functions prototype -----------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief Initializes the TS interface.
|
||||
* @param bank Array holding all the banks
|
||||
* @retval Status
|
||||
*/
|
||||
TSL_Status_enum_T TSL_Init(CONST TSL_Bank_T *bank)
|
||||
{
|
||||
TSL_Status_enum_T retval;
|
||||
|
||||
// Get banks array
|
||||
TSL_Globals.Bank_Array = bank;
|
||||
|
||||
// Initialization of the timing module
|
||||
retval = TSL_tim_Init();
|
||||
|
||||
if (retval == TSL_STATUS_OK)
|
||||
{
|
||||
// Initialization of the acquisition module
|
||||
retval = TSL_acq_Init();
|
||||
}
|
||||
|
||||
return retval;
|
||||
}
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,372 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file tsl_acq.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.3.2
|
||||
* @date 22-January-2013
|
||||
* @brief This file contains all functions to manage the acquisition in general.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "tsl_acq.h"
|
||||
#include "tsl_globals.h"
|
||||
|
||||
/* Private typedefs ----------------------------------------------------------*/
|
||||
/* Private defines -----------------------------------------------------------*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
#define IS_BANK_INDEX_OK(INDEX) (((INDEX) == 0) || (((INDEX) > 0) && ((INDEX) < TSLPRM_TOTAL_BANKS)))
|
||||
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private functions prototype -----------------------------------------------*/
|
||||
|
||||
/**
|
||||
* @brief Read all channels measurement of a Bank, calculate Delta
|
||||
* @param[in] idx_bk Index of the Bank to access
|
||||
* @param[in] mfilter Pointer to the Measure filter function
|
||||
* @param[in] dfilter Pointer to the Delta filter function
|
||||
* @retval Status
|
||||
*/
|
||||
TSL_Status_enum_T TSL_acq_BankGetResult(TSL_tIndex_T idx_bk, TSL_pFuncMeasFilter_T mfilter, TSL_pFuncDeltaFilter_T dfilter)
|
||||
{
|
||||
TSL_Status_enum_T retval = TSL_STATUS_OK;
|
||||
TSL_tIndex_T idx_ch;
|
||||
TSL_tIndexDest_T idx_dest;
|
||||
TSL_tMeas_T old_meas, new_meas;
|
||||
TSL_tDelta_T new_delta;
|
||||
CONST TSL_Bank_T *bank = &(TSL_Globals.Bank_Array[idx_bk]);
|
||||
CONST TSL_ChannelDest_T *pchDest = bank->p_chDest;
|
||||
CONST TSL_ChannelSrc_T *pchSrc = bank->p_chSrc;
|
||||
|
||||
// Check parameters (if USE_FULL_ASSERT is defined)
|
||||
assert_param(IS_BANK_INDEX_OK(idx_bk));
|
||||
|
||||
// For all channels in the bank copy the measure + calculate delta and store them.
|
||||
for (idx_ch = 0; idx_ch < bank->NbChannels; idx_ch++)
|
||||
{
|
||||
|
||||
// Get the Destination Index of the current channel
|
||||
idx_dest = pchDest->IdxDest;
|
||||
|
||||
if (bank->p_chData[idx_dest].Flags.ObjStatus == TSL_OBJ_STATUS_ON)
|
||||
{
|
||||
|
||||
// Initialize flag to inform the Object of that a new data is ready
|
||||
bank->p_chData[idx_dest].Flags.DataReady = TSL_DATA_READY;
|
||||
|
||||
// Get the new measure (the access is different between acquisitions)
|
||||
new_meas = TSL_acq_GetMeas(pchSrc->IdxSrc);
|
||||
|
||||
// Store last measure for the filter below
|
||||
#if TSLPRM_USE_MEAS > 0
|
||||
old_meas = bank->p_chData[idx_dest].Meas;
|
||||
#else
|
||||
old_meas = new_meas;
|
||||
#endif
|
||||
|
||||
// Store the new measure
|
||||
#if TSLPRM_USE_MEAS > 0
|
||||
bank->p_chData[idx_dest].Meas = new_meas;
|
||||
#endif
|
||||
|
||||
// Check acquisition value min/max and set acquisition status flag
|
||||
if (new_meas < TSL_Params.AcqMin)
|
||||
{
|
||||
bank->p_chData[idx_dest].Flags.AcqStatus = TSL_ACQ_STATUS_ERROR_MIN;
|
||||
bank->p_chData[idx_dest].Delta = 0;
|
||||
retval = TSL_STATUS_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
if (new_meas > TSL_Params.AcqMax)
|
||||
{
|
||||
bank->p_chData[idx_dest].Flags.AcqStatus = TSL_ACQ_STATUS_ERROR_MAX;
|
||||
bank->p_chData[idx_dest].Delta = 0;
|
||||
retval = TSL_STATUS_ERROR;
|
||||
}
|
||||
else // The measure is OK
|
||||
{
|
||||
if (TSL_acq_UseFilter(&bank->p_chData[idx_dest]))
|
||||
{
|
||||
// Apply Measure filter if it exists
|
||||
if (mfilter)
|
||||
{
|
||||
new_meas = mfilter(old_meas, new_meas);
|
||||
// Store the measure (optional - used for debug purpose)
|
||||
#if TSLPRM_USE_MEAS > 0
|
||||
bank->p_chData[idx_dest].Meas = new_meas;
|
||||
#endif
|
||||
}
|
||||
|
||||
// Calculate the new Delta
|
||||
new_delta = TSL_acq_ComputeDelta(bank->p_chData[idx_dest].Ref, new_meas);
|
||||
|
||||
// Check Noise (TSL_ACQ_STATUS_OK if no Noise or if Noise detection is not supported)
|
||||
bank->p_chData[idx_dest].Flags.AcqStatus = TSL_acq_CheckNoise();
|
||||
|
||||
// Apply Delta filter if it exists
|
||||
if (dfilter)
|
||||
{
|
||||
bank->p_chData[idx_dest].Delta = dfilter(new_delta);
|
||||
}
|
||||
else
|
||||
{
|
||||
bank->p_chData[idx_dest].Delta = new_delta;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
// Calculate the new Delta
|
||||
bank->p_chData[idx_dest].Delta = TSL_acq_ComputeDelta(bank->p_chData[idx_dest].Ref, new_meas);
|
||||
|
||||
// Check Noise (TSL_ACQ_STATUS_OK if no Noise or if Noise detection is not supported)
|
||||
bank->p_chData[idx_dest].Flags.AcqStatus = TSL_acq_CheckNoise();
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// Next channel
|
||||
pchDest++;
|
||||
pchSrc++;
|
||||
|
||||
}
|
||||
|
||||
return retval;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Calibrate a Bank
|
||||
* @param[in] idx_bk Index of the Bank to access
|
||||
* @retval Status
|
||||
*/
|
||||
TSL_Status_enum_T TSL_acq_BankCalibrate(TSL_tIndex_T idx_bk)
|
||||
{
|
||||
TSL_Status_enum_T retval;
|
||||
TSL_Status_enum_T acq_status;
|
||||
TSL_tIndex_T idx_ch;
|
||||
TSL_tIndexDest_T idx_dest;
|
||||
TSL_tMeas_T new_meas;
|
||||
static TSL_tIndex_T calibration_ongoing = 0;
|
||||
static TSL_tNb_T calibration_done = 0;
|
||||
static TSL_tNb_T div;
|
||||
CONST TSL_Bank_T *bank;
|
||||
CONST TSL_ChannelDest_T *pchDest; // Pointer to the current channel
|
||||
CONST TSL_ChannelSrc_T *pchSrc; // Pointer to the current channel
|
||||
|
||||
// Check parameters (if USE_FULL_ASSERT is defined)
|
||||
assert_param(IS_BANK_INDEX_OK(idx_bk));
|
||||
|
||||
bank = &(TSL_Globals.Bank_Array[idx_bk]);
|
||||
|
||||
if (calibration_ongoing == 0)
|
||||
{
|
||||
switch (TSL_Params.NbCalibSamples)
|
||||
{
|
||||
case 4:
|
||||
div = 2;
|
||||
break;
|
||||
case 16:
|
||||
div = 4;
|
||||
break;
|
||||
default:
|
||||
TSL_Params.NbCalibSamples = 8;
|
||||
div = 3;
|
||||
break;
|
||||
}
|
||||
// Clear data for all channels of the bank
|
||||
TSL_acq_BankClearData(idx_bk);
|
||||
// Configure bank
|
||||
if (TSL_acq_BankConfig(idx_bk) == TSL_STATUS_OK)
|
||||
{
|
||||
// Start acquisition
|
||||
TSL_acq_BankStartAcq();
|
||||
calibration_ongoing = 1; // Calibration started
|
||||
calibration_done = TSL_Params.NbCalibSamples;
|
||||
retval = TSL_STATUS_BUSY;
|
||||
}
|
||||
else
|
||||
{
|
||||
// Stop calibration
|
||||
// Clear data for all channels of the bank
|
||||
TSL_acq_BankClearData(idx_bk);
|
||||
calibration_ongoing = 0;
|
||||
retval = TSL_STATUS_ERROR;
|
||||
}
|
||||
|
||||
}
|
||||
else // Calibration is on-going
|
||||
{
|
||||
// Check End of Acquisition
|
||||
acq_status = TSL_acq_BankWaitEOC();
|
||||
if (acq_status == TSL_STATUS_OK)
|
||||
{
|
||||
|
||||
// Get the first channel of the bank
|
||||
pchDest = bank->p_chDest;
|
||||
pchSrc = bank->p_chSrc;
|
||||
|
||||
// Get new measurement for all channels of the bank
|
||||
for (idx_ch = 0; idx_ch < bank->NbChannels; idx_ch++)
|
||||
{
|
||||
|
||||
// Get index of the current channel
|
||||
idx_dest = pchDest->IdxDest;
|
||||
|
||||
// Get the new measure (the access is different between acquisitions)
|
||||
new_meas = TSL_acq_GetMeas(pchSrc->IdxSrc);
|
||||
|
||||
// Check min/max and set status flag
|
||||
if ((new_meas < TSL_Params.AcqMin) || (new_meas > TSL_Params.AcqMax))
|
||||
{
|
||||
// Stop calibration
|
||||
// Clear data for all channels of the bank
|
||||
TSL_acq_BankClearData(idx_bk);
|
||||
calibration_ongoing = 0;
|
||||
return TSL_STATUS_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
// Add the measure
|
||||
bank->p_chData[idx_dest].Ref += new_meas;
|
||||
}
|
||||
|
||||
// Next channel
|
||||
pchDest++;
|
||||
pchSrc++;
|
||||
}
|
||||
|
||||
// Check that we have all the needed measurements
|
||||
calibration_done--;
|
||||
if (calibration_done == 0)
|
||||
{
|
||||
|
||||
// Get the first channel of the bank
|
||||
pchDest = bank->p_chDest;
|
||||
|
||||
// Calculate the Reference for all channels of the bank
|
||||
for (idx_ch = 0; idx_ch < bank->NbChannels; idx_ch++)
|
||||
{
|
||||
// Get index of the current channel
|
||||
idx_dest = pchDest->IdxDest;
|
||||
// Divide the Reference by the number of samples
|
||||
bank->p_chData[idx_dest].Ref >>= div;
|
||||
// Next channel
|
||||
pchDest++;
|
||||
}
|
||||
|
||||
// End
|
||||
calibration_ongoing = 0;
|
||||
retval = TSL_STATUS_OK;
|
||||
}
|
||||
else // Restart a new measurement on the bank
|
||||
{
|
||||
TSL_acq_BankStartAcq();
|
||||
retval = TSL_STATUS_BUSY;
|
||||
}
|
||||
}
|
||||
else
|
||||
if (acq_status == TSL_STATUS_ERROR)
|
||||
{
|
||||
// Stop calibration
|
||||
// Clear data for all channels of the bank
|
||||
TSL_acq_BankClearData(idx_bk);
|
||||
calibration_ongoing = 0;
|
||||
retval = TSL_STATUS_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
retval = TSL_STATUS_BUSY;
|
||||
}
|
||||
}
|
||||
|
||||
return retval;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Clear Reference and Delta on all channels of a Bank
|
||||
* @param[in] idx_bk Index of the Bank to access
|
||||
* @retval None
|
||||
*/
|
||||
void TSL_acq_BankClearData(TSL_tIndex_T idx_bk)
|
||||
{
|
||||
TSL_tIndex_T idx_ch;
|
||||
TSL_tIndexDest_T idx_Dest;
|
||||
CONST TSL_Bank_T *bank = &(TSL_Globals.Bank_Array[idx_bk]);
|
||||
CONST TSL_ChannelDest_T *pchDest = bank->p_chDest;
|
||||
|
||||
// Check parameters (if USE_FULL_ASSERT is defined)
|
||||
assert_param(IS_BANK_INDEX_OK(idx_bk));
|
||||
|
||||
// For all channels of the bank
|
||||
for (idx_ch = 0; idx_ch < bank->NbChannels; idx_ch++)
|
||||
{
|
||||
idx_Dest = pchDest->IdxDest;
|
||||
bank->p_chData[idx_Dest].Ref = 0;
|
||||
bank->p_chData[idx_Dest].Delta = 0;
|
||||
pchDest++; // Next channel
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
#if TSLPRM_USE_ZONE > 0
|
||||
|
||||
/**
|
||||
* @brief Configures a Zone.
|
||||
* @param[in] zone Zone to configure
|
||||
* @param[in] idx_bk Bank index in the zone to configure
|
||||
* @retval Status
|
||||
*/
|
||||
TSL_Status_enum_T TSL_acq_ZoneConfig(CONST TSL_Zone_T *zone, TSL_tIndex_T idx_bk)
|
||||
{
|
||||
TSL_Status_enum_T retval;
|
||||
|
||||
// Check parameters (if USE_FULL_ASSERT is defined)
|
||||
assert_param(IS_BANK_INDEX_OK(idx_bk));
|
||||
|
||||
TSL_Globals.This_Zone = zone;
|
||||
|
||||
do
|
||||
{
|
||||
retval = TSL_acq_BankConfig(zone->BankIndex[idx_bk]);
|
||||
TSL_Globals.This_Bank = zone->BankIndex[idx_bk];
|
||||
idx_bk++;
|
||||
}
|
||||
while ((idx_bk < zone->NbBanks) && (retval == TSL_STATUS_ERROR));
|
||||
|
||||
TSL_Globals.Index_In_This_Zone = idx_bk;
|
||||
|
||||
#if TSLPRM_PXS_LOW_POWER_MODE > 0
|
||||
if (idx_bk < zone->NbBanks)
|
||||
{
|
||||
resetPXSLowPower();
|
||||
}
|
||||
#endif
|
||||
|
||||
return(retval);
|
||||
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,817 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file tsl_acq_stm32f0xx.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.3.2
|
||||
* @date 22-January-2013
|
||||
* @brief This file contains all functions to manage the TSC acquisition
|
||||
* on STM32F0xx products.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "tsl_acq_stm32f0xx.h"
|
||||
#include "tsl_globals.h"
|
||||
#include "stm32f0xx_it.h"
|
||||
|
||||
/* Private typedefs ----------------------------------------------------------*/
|
||||
/* Private defines -----------------------------------------------------------*/
|
||||
#define TSL_DELAY_DISCHARGE (1000)
|
||||
|
||||
#define NU (0) // Not Used IO
|
||||
#define CHANNEL (1) // Channel IO
|
||||
#define SHIELD (2) // Shield IO (= Channel IO but not acquired)
|
||||
#define SAMPCAP (3) // Sampling Capacitor IO
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
#define IS_BANK_INDEX_OK(INDEX) (((INDEX) == 0) || (((INDEX) > 0) && ((INDEX) < TSLPRM_TOTAL_BANKS)))
|
||||
#define IS_SOURCE_INDEX_OK(INDEX) (((INDEX) == 0) || (((INDEX) > 0) && ((INDEX) < TSLPRM_TOTAL_CHANNELS)))
|
||||
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
|
||||
/* Private functions prototype -----------------------------------------------*/
|
||||
void SoftDelay(uint32_t val);
|
||||
|
||||
/**
|
||||
* @brief Initializes the TouchSensing GPIOs.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void TSL_acq_InitGPIOs(void)
|
||||
{
|
||||
|
||||
GPIO_InitTypeDef GPIO_InitStructure;
|
||||
uint32_t tmp_value_0;
|
||||
uint32_t tmp_value_1;
|
||||
|
||||
//====================
|
||||
// GPIOs configuration
|
||||
//====================
|
||||
|
||||
// Enable GPIOs clocks
|
||||
RCC->AHBENR |= (RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN | RCC_AHBENR_GPIOCEN);
|
||||
|
||||
// Alternate function Output Open-Drain for Sampling Capacitor IOs
|
||||
//----------------------------------------------------------------
|
||||
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
|
||||
GPIO_InitStructure.GPIO_OType = GPIO_OType_OD;
|
||||
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz;
|
||||
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
|
||||
|
||||
// GPIOA
|
||||
GPIO_InitStructure.GPIO_Pin = 0;
|
||||
#if TSLPRM_TSC_GROUP1_IO1 == SAMPCAP
|
||||
GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_0;
|
||||
#endif
|
||||
#if TSLPRM_TSC_GROUP1_IO2 == SAMPCAP
|
||||
GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_1;
|
||||
#endif
|
||||
#if TSLPRM_TSC_GROUP1_IO3 == SAMPCAP
|
||||
GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_2;
|
||||
#endif
|
||||
#if TSLPRM_TSC_GROUP1_IO4 == SAMPCAP
|
||||
GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_3;
|
||||
#endif
|
||||
#if TSLPRM_TSC_GROUP2_IO1 == SAMPCAP
|
||||
GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_4;
|
||||
#endif
|
||||
#if TSLPRM_TSC_GROUP2_IO2 == SAMPCAP
|
||||
GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_5;
|
||||
#endif
|
||||
#if TSLPRM_TSC_GROUP2_IO3 == SAMPCAP
|
||||
GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_6;
|
||||
#endif
|
||||
#if TSLPRM_TSC_GROUP2_IO4 == SAMPCAP
|
||||
GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_7;
|
||||
#endif
|
||||
#if TSLPRM_TSC_GROUP4_IO1 == SAMPCAP
|
||||
GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_9;
|
||||
#endif
|
||||
#if TSLPRM_TSC_GROUP4_IO2 == SAMPCAP
|
||||
GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_10;
|
||||
#endif
|
||||
#if TSLPRM_TSC_GROUP4_IO3 == SAMPCAP
|
||||
GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_11;
|
||||
#endif
|
||||
#if TSLPRM_TSC_GROUP4_IO4 == SAMPCAP
|
||||
GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_12;
|
||||
#endif
|
||||
if (GPIO_InitStructure.GPIO_Pin != 0)
|
||||
{
|
||||
GPIO_Init(GPIOA, &GPIO_InitStructure);
|
||||
}
|
||||
|
||||
// GPIOB
|
||||
GPIO_InitStructure.GPIO_Pin = 0;
|
||||
#if TSLPRM_TSC_GROUP3_IO2 == SAMPCAP
|
||||
GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_0;
|
||||
#endif
|
||||
#if TSLPRM_TSC_GROUP3_IO3 == SAMPCAP
|
||||
GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_1;
|
||||
#endif
|
||||
#if TSLPRM_TSC_GROUP3_IO4 == SAMPCAP
|
||||
GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_2;
|
||||
#endif
|
||||
#if TSLPRM_TSC_GROUP5_IO1 == SAMPCAP
|
||||
GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_3;
|
||||
#endif
|
||||
#if TSLPRM_TSC_GROUP5_IO2 == SAMPCAP
|
||||
GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_4;
|
||||
#endif
|
||||
#if TSLPRM_TSC_GROUP5_IO3 == SAMPCAP
|
||||
GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_6;
|
||||
#endif
|
||||
#if TSLPRM_TSC_GROUP5_IO4 == SAMPCAP
|
||||
GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_7;
|
||||
#endif
|
||||
#if TSLPRM_TSC_GROUP6_IO1 == SAMPCAP
|
||||
GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_11;
|
||||
#endif
|
||||
#if TSLPRM_TSC_GROUP6_IO2 == SAMPCAP
|
||||
GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_12;
|
||||
#endif
|
||||
#if TSLPRM_TSC_GROUP6_IO3 == SAMPCAP
|
||||
GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_13;
|
||||
#endif
|
||||
#if TSLPRM_TSC_GROUP6_IO4 == SAMPCAP
|
||||
GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_14;
|
||||
#endif
|
||||
if (GPIO_InitStructure.GPIO_Pin != 0)
|
||||
{
|
||||
GPIO_Init(GPIOB, &GPIO_InitStructure);
|
||||
}
|
||||
|
||||
// GPIOC
|
||||
#if TSLPRM_TSC_GROUP3_IO1 == SAMPCAP
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5;
|
||||
GPIO_Init(GPIOC, &GPIO_InitStructure);
|
||||
#endif
|
||||
|
||||
// Alternate function Output Push-Pull for Channel and Shield IOs
|
||||
//---------------------------------------------------------------
|
||||
|
||||
GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
|
||||
|
||||
// GPIOA
|
||||
GPIO_InitStructure.GPIO_Pin = 0;
|
||||
#if (TSLPRM_TSC_GROUP1_IO1 == CHANNEL) || (TSLPRM_TSC_GROUP1_IO1 == SHIELD)
|
||||
GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_0;
|
||||
#endif
|
||||
#if (TSLPRM_TSC_GROUP1_IO2 == CHANNEL) || (TSLPRM_TSC_GROUP1_IO2 == SHIELD)
|
||||
GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_1;
|
||||
#endif
|
||||
#if (TSLPRM_TSC_GROUP1_IO3 == CHANNEL) || (TSLPRM_TSC_GROUP1_IO3 == SHIELD)
|
||||
GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_2;
|
||||
#endif
|
||||
#if (TSLPRM_TSC_GROUP1_IO4 == CHANNEL) || (TSLPRM_TSC_GROUP1_IO4 == SHIELD)
|
||||
GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_3;
|
||||
#endif
|
||||
#if (TSLPRM_TSC_GROUP2_IO1 == CHANNEL) || (TSLPRM_TSC_GROUP2_IO1 == SHIELD)
|
||||
GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_4;
|
||||
#endif
|
||||
#if (TSLPRM_TSC_GROUP2_IO2 == CHANNEL) || (TSLPRM_TSC_GROUP2_IO2 == SHIELD)
|
||||
GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_5;
|
||||
#endif
|
||||
#if (TSLPRM_TSC_GROUP2_IO3 == CHANNEL) || (TSLPRM_TSC_GROUP2_IO3 == SHIELD)
|
||||
GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_6;
|
||||
#endif
|
||||
#if (TSLPRM_TSC_GROUP2_IO4 == CHANNEL) || (TSLPRM_TSC_GROUP2_IO4 == SHIELD)
|
||||
GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_7;
|
||||
#endif
|
||||
#if (TSLPRM_TSC_GROUP4_IO1 == CHANNEL) || (TSLPRM_TSC_GROUP4_IO1 == SHIELD)
|
||||
GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_9;
|
||||
#endif
|
||||
#if (TSLPRM_TSC_GROUP4_IO2 == CHANNEL) || (TSLPRM_TSC_GROUP4_IO2 == SHIELD)
|
||||
GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_10;
|
||||
#endif
|
||||
#if (TSLPRM_TSC_GROUP4_IO3 == CHANNEL) || (TSLPRM_TSC_GROUP4_IO3 == SHIELD)
|
||||
GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_11;
|
||||
#endif
|
||||
#if (TSLPRM_TSC_GROUP4_IO4 == CHANNEL) || (TSLPRM_TSC_GROUP4_IO4 == SHIELD)
|
||||
GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_12;
|
||||
#endif
|
||||
if (GPIO_InitStructure.GPIO_Pin != 0)
|
||||
{
|
||||
GPIO_Init(GPIOA, &GPIO_InitStructure);
|
||||
}
|
||||
|
||||
// GPIOB
|
||||
GPIO_InitStructure.GPIO_Pin = 0;
|
||||
#if (TSLPRM_TSC_GROUP3_IO2 == CHANNEL) || (TSLPRM_TSC_GROUP3_IO2 == SHIELD)
|
||||
GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_0;
|
||||
#endif
|
||||
#if (TSLPRM_TSC_GROUP3_IO3 == CHANNEL) || (TSLPRM_TSC_GROUP3_IO3 == SHIELD)
|
||||
GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_1;
|
||||
#endif
|
||||
#if (TSLPRM_TSC_GROUP3_IO4 == CHANNEL) || (TSLPRM_TSC_GROUP3_IO4 == SHIELD)
|
||||
GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_2;
|
||||
#endif
|
||||
#if (TSLPRM_TSC_GROUP5_IO1 == CHANNEL) || (TSLPRM_TSC_GROUP5_IO1 == SHIELD)
|
||||
GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_3;
|
||||
#endif
|
||||
#if (TSLPRM_TSC_GROUP5_IO2 == CHANNEL) || (TSLPRM_TSC_GROUP5_IO2 == SHIELD)
|
||||
GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_4;
|
||||
#endif
|
||||
#if (TSLPRM_TSC_GROUP5_IO3 == CHANNEL) || (TSLPRM_TSC_GROUP5_IO3 == SHIELD)
|
||||
GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_6;
|
||||
#endif
|
||||
#if (TSLPRM_TSC_GROUP5_IO4 == CHANNEL) || (TSLPRM_TSC_GROUP5_IO4 == SHIELD)
|
||||
GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_7;
|
||||
#endif
|
||||
#if (TSLPRM_TSC_GROUP6_IO1 == CHANNEL) || (TSLPRM_TSC_GROUP6_IO1 == SHIELD)
|
||||
GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_11;
|
||||
#endif
|
||||
#if (TSLPRM_TSC_GROUP6_IO2 == CHANNEL) || (TSLPRM_TSC_GROUP6_IO2 == SHIELD)
|
||||
GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_12;
|
||||
#endif
|
||||
#if (TSLPRM_TSC_GROUP6_IO3 == CHANNEL) || (TSLPRM_TSC_GROUP6_IO3 == SHIELD)
|
||||
GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_13;
|
||||
#endif
|
||||
#if (TSLPRM_TSC_GROUP6_IO4 == CHANNEL) || (TSLPRM_TSC_GROUP6_IO4 == SHIELD)
|
||||
GPIO_InitStructure.GPIO_Pin |= GPIO_Pin_14;
|
||||
#endif
|
||||
if (GPIO_InitStructure.GPIO_Pin != 0)
|
||||
{
|
||||
GPIO_Init(GPIOB, &GPIO_InitStructure);
|
||||
}
|
||||
|
||||
// GPIOC
|
||||
#if (TSLPRM_TSC_GROUP3_IO1 == CHANNEL) || (TSLPRM_TSC_GROUP3_IO1 == SHIELD)
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5;
|
||||
GPIO_Init(GPIOC, &GPIO_InitStructure);
|
||||
#endif
|
||||
|
||||
// Set Alternate-Function AF3 for GPIOA and GPIOB
|
||||
//-----------------------------------------------
|
||||
|
||||
// GPIOA
|
||||
tmp_value_0 = 0;
|
||||
tmp_value_1 = 0;
|
||||
#if TSLPRM_TSC_GROUP1_IO1 != NU
|
||||
tmp_value_0 |= (uint32_t)((uint32_t)3 << (0 * 4));
|
||||
#endif
|
||||
#if TSLPRM_TSC_GROUP1_IO2 != NU
|
||||
tmp_value_0 |= (uint32_t)((uint32_t)3 << (1 * 4));
|
||||
#endif
|
||||
#if TSLPRM_TSC_GROUP1_IO3 != NU
|
||||
tmp_value_0 |= (uint32_t)((uint32_t)3 << (2 * 4));
|
||||
#endif
|
||||
#if TSLPRM_TSC_GROUP1_IO4 != NU
|
||||
tmp_value_0 |= (uint32_t)((uint32_t)3 << (3 * 4));
|
||||
#endif
|
||||
#if TSLPRM_TSC_GROUP2_IO1 != NU
|
||||
tmp_value_0 |= (uint32_t)((uint32_t)3 << (4 * 4));
|
||||
#endif
|
||||
#if TSLPRM_TSC_GROUP2_IO2 != NU
|
||||
tmp_value_0 |= (uint32_t)((uint32_t)3 << (5 * 4));
|
||||
#endif
|
||||
#if TSLPRM_TSC_GROUP2_IO3 != NU
|
||||
tmp_value_0 |= (uint32_t)((uint32_t)3 << (6 * 4));
|
||||
#endif
|
||||
#if TSLPRM_TSC_GROUP2_IO4 != NU
|
||||
tmp_value_0 |= (uint32_t)((uint32_t)3 << (7 * 4));
|
||||
#endif
|
||||
#if TSLPRM_TSC_GROUP4_IO1 != NU
|
||||
tmp_value_1 |= (uint32_t)((uint32_t)3 << (1 * 4));
|
||||
#endif
|
||||
#if TSLPRM_TSC_GROUP4_IO2 != NU
|
||||
tmp_value_1 |= (uint32_t)((uint32_t)3 << (2 * 4));
|
||||
#endif
|
||||
#if TSLPRM_TSC_GROUP4_IO3 != NU
|
||||
tmp_value_1 |= (uint32_t)((uint32_t)3 << (3 * 4));
|
||||
#endif
|
||||
#if TSLPRM_TSC_GROUP4_IO4 != NU
|
||||
tmp_value_1 |= (uint32_t)((uint32_t)3 << (4 * 4));
|
||||
#endif
|
||||
if (tmp_value_0 != 0) {GPIOA->AFR[0] |= tmp_value_0;}
|
||||
if (tmp_value_1 != 0) {GPIOA->AFR[1] |= tmp_value_1;}
|
||||
|
||||
// GPIOB
|
||||
tmp_value_0 = 0;
|
||||
tmp_value_1 = 0;
|
||||
#if TSLPRM_TSC_GROUP3_IO2 != NU
|
||||
tmp_value_0 |= (uint32_t)((uint32_t)3 << (0 * 4));
|
||||
#endif
|
||||
#if TSLPRM_TSC_GROUP3_IO3 != NU
|
||||
tmp_value_0 |= (uint32_t)((uint32_t)3 << (1 * 4));
|
||||
#endif
|
||||
#if TSLPRM_TSC_GROUP3_IO4 != NU
|
||||
tmp_value_0 |= (uint32_t)((uint32_t)3 << (2 * 4));
|
||||
#endif
|
||||
#if TSLPRM_TSC_GROUP5_IO1 != NU
|
||||
tmp_value_0 |= (uint32_t)((uint32_t)3 << (3 * 4));
|
||||
#endif
|
||||
#if TSLPRM_TSC_GROUP5_IO2 != NU
|
||||
tmp_value_0 |= (uint32_t)((uint32_t)3 << (4 * 4));
|
||||
#endif
|
||||
#if TSLPRM_TSC_GROUP5_IO3 != NU
|
||||
tmp_value_0 |= (uint32_t)((uint32_t)3 << (6 * 4));
|
||||
#endif
|
||||
#if TSLPRM_TSC_GROUP5_IO4 != NU
|
||||
tmp_value_0 |= (uint32_t)((uint32_t)3 << (7 * 4));
|
||||
#endif
|
||||
#if TSLPRM_TSC_GROUP6_IO1 != NU
|
||||
tmp_value_1 |= (uint32_t)((uint32_t)3 << (3 * 4));
|
||||
#endif
|
||||
#if TSLPRM_TSC_GROUP6_IO2 != NU
|
||||
tmp_value_1 |= (uint32_t)((uint32_t)3 << (4 * 4));
|
||||
#endif
|
||||
#if TSLPRM_TSC_GROUP6_IO3 != NU
|
||||
tmp_value_1 |= (uint32_t)((uint32_t)3 << (5 * 4));
|
||||
#endif
|
||||
#if TSLPRM_TSC_GROUP6_IO4 != NU
|
||||
tmp_value_1 |= (uint32_t)((uint32_t)3 << (6 * 4));
|
||||
#endif
|
||||
if (tmp_value_0 != 0) {GPIOB->AFR[0] |= tmp_value_0;}
|
||||
if (tmp_value_1 != 0) {GPIOB->AFR[1] |= tmp_value_1;}
|
||||
|
||||
//==================
|
||||
// TSC configuration
|
||||
//==================
|
||||
|
||||
// Enable TSC clock
|
||||
RCC->AHBENR |= RCC_AHBENR_TSEN;
|
||||
|
||||
// Disable Schmitt trigger hysteresis on all used TS IOs (Channel, Shield and Sampling IOs)
|
||||
//-----------------------------------------------------------------------------------------
|
||||
|
||||
tmp_value_0 = 0xFFFFFFFF;
|
||||
#if TSLPRM_TSC_GROUP1_IO1 != NU
|
||||
tmp_value_0 &= (uint32_t)~((uint32_t)1 << 0);
|
||||
#endif
|
||||
#if TSLPRM_TSC_GROUP1_IO2 != NU
|
||||
tmp_value_0 &= (uint32_t)~((uint32_t)1 << 1);
|
||||
#endif
|
||||
#if TSLPRM_TSC_GROUP1_IO3 != NU
|
||||
tmp_value_0 &= (uint32_t)~((uint32_t)1 << 2);
|
||||
#endif
|
||||
#if TSLPRM_TSC_GROUP1_IO4 != NU
|
||||
tmp_value_0 &= (uint32_t)~((uint32_t)1 << 3);
|
||||
#endif
|
||||
#if TSLPRM_TSC_GROUP2_IO1 != NU
|
||||
tmp_value_0 &= (uint32_t)~((uint32_t)1 << 4);
|
||||
#endif
|
||||
#if TSLPRM_TSC_GROUP2_IO2 != NU
|
||||
tmp_value_0 &= (uint32_t)~((uint32_t)1 << 5);
|
||||
#endif
|
||||
#if TSLPRM_TSC_GROUP2_IO3 != NU
|
||||
tmp_value_0 &= (uint32_t)~((uint32_t)1 << 6);
|
||||
#endif
|
||||
#if TSLPRM_TSC_GROUP2_IO4 != NU
|
||||
tmp_value_0 &= (uint32_t)~((uint32_t)1 << 7);
|
||||
#endif
|
||||
#if TSLPRM_TSC_GROUP3_IO1 != NU
|
||||
tmp_value_0 &= (uint32_t)~((uint32_t)1 << 8);
|
||||
#endif
|
||||
#if TSLPRM_TSC_GROUP3_IO2 != NU
|
||||
tmp_value_0 &= (uint32_t)~((uint32_t)1 << 9);
|
||||
#endif
|
||||
#if TSLPRM_TSC_GROUP3_IO3 != NU
|
||||
tmp_value_0 &= (uint32_t)~((uint32_t)1 << 10);
|
||||
#endif
|
||||
#if TSLPRM_TSC_GROUP3_IO4 != NU
|
||||
tmp_value_0 &= (uint32_t)~((uint32_t)1 << 11);
|
||||
#endif
|
||||
#if TSLPRM_TSC_GROUP4_IO1 != NU
|
||||
tmp_value_0 &= (uint32_t)~((uint32_t)1 << 12);
|
||||
#endif
|
||||
#if TSLPRM_TSC_GROUP4_IO2 != NU
|
||||
tmp_value_0 &= (uint32_t)~((uint32_t)1 << 13);
|
||||
#endif
|
||||
#if TSLPRM_TSC_GROUP4_IO3 != NU
|
||||
tmp_value_0 &= (uint32_t)~((uint32_t)1 << 14);
|
||||
#endif
|
||||
#if TSLPRM_TSC_GROUP4_IO4 != NU
|
||||
tmp_value_0 &= (uint32_t)~((uint32_t)1 << 15);
|
||||
#endif
|
||||
#if TSLPRM_TSC_GROUP5_IO1 != NU
|
||||
tmp_value_0 &= (uint32_t)~((uint32_t)1 << 16);
|
||||
#endif
|
||||
#if TSLPRM_TSC_GROUP5_IO2 != NU
|
||||
tmp_value_0 &= (uint32_t)~((uint32_t)1 << 17);
|
||||
#endif
|
||||
#if TSLPRM_TSC_GROUP5_IO3 != NU
|
||||
tmp_value_0 &= (uint32_t)~((uint32_t)1 << 18);
|
||||
#endif
|
||||
#if TSLPRM_TSC_GROUP5_IO4 != NU
|
||||
tmp_value_0 &= (uint32_t)~((uint32_t)1 << 19);
|
||||
#endif
|
||||
#if TSLPRM_TSC_GROUP6_IO1 != NU
|
||||
tmp_value_0 &= (uint32_t)~((uint32_t)1 << 20);
|
||||
#endif
|
||||
#if TSLPRM_TSC_GROUP6_IO2 != NU
|
||||
tmp_value_0 &= (uint32_t)~((uint32_t)1 << 21);
|
||||
#endif
|
||||
#if TSLPRM_TSC_GROUP6_IO3 != NU
|
||||
tmp_value_0 &= (uint32_t)~((uint32_t)1 << 22);
|
||||
#endif
|
||||
#if TSLPRM_TSC_GROUP6_IO4 != NU
|
||||
tmp_value_0 &= (uint32_t)~((uint32_t)1 << 23);
|
||||
#endif
|
||||
if (tmp_value_0 != 0xFFFFFFFF) {TSC->IOHCR &= tmp_value_0;}
|
||||
|
||||
// Set Sampling Capacitor IOs
|
||||
//---------------------------
|
||||
|
||||
tmp_value_0 = 0;
|
||||
#if TSLPRM_TSC_GROUP1_IO1 == SAMPCAP
|
||||
tmp_value_0 |= (uint32_t)((uint32_t)1 << 0);
|
||||
#endif
|
||||
#if TSLPRM_TSC_GROUP1_IO2 == SAMPCAP
|
||||
tmp_value_0 |= (uint32_t)((uint32_t)1 << 1);
|
||||
#endif
|
||||
#if TSLPRM_TSC_GROUP1_IO3 == SAMPCAP
|
||||
tmp_value_0 |= (uint32_t)((uint32_t)1 << 2);
|
||||
#endif
|
||||
#if TSLPRM_TSC_GROUP1_IO4 == SAMPCAP
|
||||
tmp_value_0 |= (uint32_t)((uint32_t)1 << 3);
|
||||
#endif
|
||||
#if TSLPRM_TSC_GROUP2_IO1 == SAMPCAP
|
||||
tmp_value_0 |= (uint32_t)((uint32_t)1 << 4);
|
||||
#endif
|
||||
#if TSLPRM_TSC_GROUP2_IO2 == SAMPCAP
|
||||
tmp_value_0 |= (uint32_t)((uint32_t)1 << 5);
|
||||
#endif
|
||||
#if TSLPRM_TSC_GROUP2_IO3 == SAMPCAP
|
||||
tmp_value_0 |= (uint32_t)((uint32_t)1 << 6);
|
||||
#endif
|
||||
#if TSLPRM_TSC_GROUP2_IO4 == SAMPCAP
|
||||
tmp_value_0 |= (uint32_t)((uint32_t)1 << 7);
|
||||
#endif
|
||||
#if TSLPRM_TSC_GROUP3_IO1 == SAMPCAP
|
||||
tmp_value_0 |= (uint32_t)((uint32_t)1 << 8);
|
||||
#endif
|
||||
#if TSLPRM_TSC_GROUP3_IO2 == SAMPCAP
|
||||
tmp_value_0 |= (uint32_t)((uint32_t)1 << 9);
|
||||
#endif
|
||||
#if TSLPRM_TSC_GROUP3_IO3 == SAMPCAP
|
||||
tmp_value_0 |= (uint32_t)((uint32_t)1 << 10);
|
||||
#endif
|
||||
#if TSLPRM_TSC_GROUP3_IO4 == SAMPCAP
|
||||
tmp_value_0 |= (uint32_t)((uint32_t)1 << 11);
|
||||
#endif
|
||||
#if TSLPRM_TSC_GROUP4_IO1 == SAMPCAP
|
||||
tmp_value_0 |= (uint32_t)((uint32_t)1 << 12);
|
||||
#endif
|
||||
#if TSLPRM_TSC_GROUP4_IO2 == SAMPCAP
|
||||
tmp_value_0 |= (uint32_t)((uint32_t)1 << 13);
|
||||
#endif
|
||||
#if TSLPRM_TSC_GROUP4_IO3 == SAMPCAP
|
||||
tmp_value_0 |= (uint32_t)((uint32_t)1 << 14);
|
||||
#endif
|
||||
#if TSLPRM_TSC_GROUP4_IO4 == SAMPCAP
|
||||
tmp_value_0 |= (uint32_t)((uint32_t)1 << 15);
|
||||
#endif
|
||||
#if TSLPRM_TSC_GROUP5_IO1 == SAMPCAP
|
||||
tmp_value_0 |= (uint32_t)((uint32_t)1 << 16);
|
||||
#endif
|
||||
#if TSLPRM_TSC_GROUP5_IO2 == SAMPCAP
|
||||
tmp_value_0 |= (uint32_t)((uint32_t)1 << 17);
|
||||
#endif
|
||||
#if TSLPRM_TSC_GROUP5_IO3 == SAMPCAP
|
||||
tmp_value_0 |= (uint32_t)((uint32_t)1 << 18);
|
||||
#endif
|
||||
#if TSLPRM_TSC_GROUP5_IO4 == SAMPCAP
|
||||
tmp_value_0 |= (uint32_t)((uint32_t)1 << 19);
|
||||
#endif
|
||||
#if TSLPRM_TSC_GROUP6_IO1 == SAMPCAP
|
||||
tmp_value_0 |= (uint32_t)((uint32_t)1 << 20);
|
||||
#endif
|
||||
#if TSLPRM_TSC_GROUP6_IO2 == SAMPCAP
|
||||
tmp_value_0 |= (uint32_t)((uint32_t)1 << 21);
|
||||
#endif
|
||||
#if TSLPRM_TSC_GROUP6_IO3 == SAMPCAP
|
||||
tmp_value_0 |= (uint32_t)((uint32_t)1 << 22);
|
||||
#endif
|
||||
#if TSLPRM_TSC_GROUP6_IO4 == SAMPCAP
|
||||
tmp_value_0 |= (uint32_t)((uint32_t)1 << 23);
|
||||
#endif
|
||||
if (tmp_value_0 != 0) {TSC->IOSCR |= tmp_value_0;}
|
||||
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Initializes the acquisition module.
|
||||
* @param None
|
||||
* @retval Status
|
||||
*/
|
||||
TSL_Status_enum_T TSL_acq_Init(void)
|
||||
{
|
||||
|
||||
#if TSLPRM_TSC_GPIO_CONFIG > 0
|
||||
TSL_acq_InitGPIOs();
|
||||
#endif
|
||||
|
||||
// Enable TSC clock
|
||||
RCC->AHBENR |= RCC_AHBENR_TSEN;
|
||||
|
||||
// TSC enabled
|
||||
TSC->CR = 0x01;
|
||||
|
||||
// Set CTPH
|
||||
TSC->CR |= (uint32_t)((uint32_t)TSLPRM_TSC_CTPH << 28) & 0xF0000000;
|
||||
|
||||
// Set CTPL
|
||||
TSC->CR |= (uint32_t)((uint32_t)TSLPRM_TSC_CTPL << 24) & 0x0F000000;
|
||||
|
||||
// Set SpreadSpectrum
|
||||
TSC->CR |= (uint32_t)((uint32_t)TSLPRM_TSC_USE_SS << 16) & 0x00010000;
|
||||
TSC->CR |= (uint32_t)((uint32_t)TSLPRM_TSC_SSD << 17) & 0x00FE0000;
|
||||
TSC->CR |= (uint32_t)((uint32_t)TSLPRM_TSC_SSPSC << 15) & 0x00008000;
|
||||
|
||||
// Set Prescaler
|
||||
TSC->CR |= (uint32_t)((uint32_t)TSLPRM_TSC_PGPSC << 12) & 0x00007000;
|
||||
|
||||
// Set Max Count
|
||||
TSC->CR |= (uint32_t)((uint32_t)TSLPRM_TSC_MCV << 5) & 0x000000E0;
|
||||
|
||||
// Set IO default in Output PP Low to discharge all capacitors
|
||||
TSC->CR &= (uint32_t)(~(1 << 4));
|
||||
|
||||
// Set Synchronization Mode
|
||||
#if TSLPRM_TSC_AM > 0
|
||||
|
||||
// Set Synchronization Pin in Alternate-Function mode
|
||||
RCC->AHBENR |= RCC_AHBENR_GPIOBEN; // Set GPIOB clock
|
||||
|
||||
#if TSLPRM_TSC_SYNC_PIN == 0 // PB08
|
||||
GPIOB->MODER &= 0xFFFCFFFF;
|
||||
GPIOB->MODER |= 0x00020000;
|
||||
GPIOB->AFR[1] |= 0x00000003;
|
||||
#else // PB10
|
||||
GPIOB->MODER &= 0xFFCFFFFF;
|
||||
GPIOB->MODER |= 0x00200000;
|
||||
GPIOB->AFR[1] |= 0x00000300;
|
||||
#endif
|
||||
|
||||
// Set Synchronization Polarity
|
||||
TSC->CR |= (uint32_t)((uint32_t)TSLPRM_TSC_SYNC_POL << 3) & 0x00000008;
|
||||
|
||||
#endif
|
||||
|
||||
// Set acquisition mode
|
||||
TSC->CR |= (uint32_t)((uint32_t)TSLPRM_TSC_AM << 2) & 0x00000004;
|
||||
|
||||
#if TSLPRM_USE_ACQ_INTERRUPT > 0
|
||||
|
||||
// Set both EOA and MCE interrupts
|
||||
TSC->IER |= 0x03;
|
||||
|
||||
// Configure NVIC
|
||||
NVIC_SetPriority(TS_IRQn, 0);
|
||||
NVIC_EnableIRQ(TS_IRQn);
|
||||
|
||||
#endif
|
||||
|
||||
return TSL_STATUS_OK;
|
||||
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Configures a Bank.
|
||||
* @param[in] idx_bk Index of the Bank to configure
|
||||
* @retval Status
|
||||
*/
|
||||
TSL_Status_enum_T TSL_acq_BankConfig(TSL_tIndex_T idx_bk)
|
||||
{
|
||||
TSL_tIndex_T idx_ch;
|
||||
uint32_t objs; /* bit field of TSL_ObjStatus_enum_T type */
|
||||
uint32_t gx;
|
||||
uint32_t ioy;
|
||||
CONST TSL_Bank_T *bank = &(TSL_Globals.Bank_Array[idx_bk]);
|
||||
CONST TSL_ChannelSrc_T *pchSrc = bank->p_chSrc;
|
||||
CONST TSL_ChannelDest_T *pchDest = bank->p_chDest;
|
||||
|
||||
// Check parameters (if USE_FULL_ASSERT is defined)
|
||||
assert_param(IS_BANK_INDEX_OK(idx_bk));
|
||||
|
||||
// Mark the current bank processed
|
||||
TSL_Globals.This_Bank = idx_bk;
|
||||
|
||||
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
// Enable the Gx_IOy used as channels (channels + shield)
|
||||
TSC->IOCCR = bank->msk_IOCCR_channels;
|
||||
// Enable acquisition on selected Groups
|
||||
TSC->IOGCSR = bank->msk_IOGCSR_groups;
|
||||
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
|
||||
// For all channels of the bank check if they are OFF or BURST_ONLY
|
||||
// and set acquisition status flag
|
||||
for (idx_ch = 0; idx_ch < bank->NbChannels; idx_ch++)
|
||||
{
|
||||
|
||||
// Check Object status flag
|
||||
objs = bank->p_chData[pchDest->IdxDest].Flags.ObjStatus;
|
||||
|
||||
if (objs != TSL_OBJ_STATUS_ON)
|
||||
{
|
||||
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
// Get the Channel Group mask
|
||||
gx = pchSrc->msk_IOGCSR_group;
|
||||
// Stop acquisition of the Group
|
||||
TSC->IOGCSR &= (uint32_t)~gx;
|
||||
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
|
||||
if (objs == TSL_OBJ_STATUS_OFF)
|
||||
{
|
||||
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
// Get the Channel IO mask
|
||||
ioy = pchSrc->msk_IOCCR_channel;
|
||||
// Stop Burst of the Channel
|
||||
TSC->IOCCR &= (uint32_t)~ioy;
|
||||
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
}
|
||||
}
|
||||
|
||||
// Next channel
|
||||
pchSrc++;
|
||||
pchDest++;
|
||||
}
|
||||
|
||||
return TSL_STATUS_OK;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Start acquisition on a previously configured bank
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void TSL_acq_BankStartAcq(void)
|
||||
{
|
||||
// Clear both EOAIC and MCEIC flags
|
||||
TSC->ICR |= 0x03;
|
||||
|
||||
// Wait capacitors discharge
|
||||
SoftDelay(TSL_DELAY_DISCHARGE);
|
||||
|
||||
#if TSLPRM_TSC_IODEF > 0 // Default = Input Floating
|
||||
// Set IO default in Input Floating
|
||||
TSC->CR |= (1 << 4);
|
||||
#endif
|
||||
|
||||
// Start acquisition
|
||||
TSC->CR |= 0x02;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Wait end of acquisition
|
||||
* @param None
|
||||
* @retval Status
|
||||
*/
|
||||
TSL_Status_enum_T TSL_acq_BankWaitEOC(void)
|
||||
{
|
||||
TSL_Status_enum_T retval = TSL_STATUS_BUSY;
|
||||
|
||||
// Check EOAF flag
|
||||
if (TSC->ISR & 0x01)
|
||||
{
|
||||
|
||||
#if TSLPRM_TSC_IODEF > 0 // Default = Input Floating
|
||||
// Set IO default in Output PP Low to discharge all capacitors
|
||||
TSC->CR &= (uint32_t)(~(1 << 4));
|
||||
#endif
|
||||
|
||||
// Check MCEF flag
|
||||
if (TSC->ISR & 0x02)
|
||||
{
|
||||
retval = TSL_STATUS_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
retval = TSL_STATUS_OK;
|
||||
}
|
||||
}
|
||||
|
||||
return retval;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Return the current measure
|
||||
* @param[in] index Index of the measure source
|
||||
* @retval Measure
|
||||
*/
|
||||
TSL_tMeas_T TSL_acq_GetMeas(TSL_tIndex_T index)
|
||||
{
|
||||
return(TSC->IOGXCR[index]);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Compute the Delta value
|
||||
* @param[in] ref Reference value
|
||||
* @param[in] meas Last Measurement value
|
||||
* @retval Delta value
|
||||
*/
|
||||
TSL_tDelta_T TSL_acq_ComputeDelta(TSL_tRef_T ref, TSL_tMeas_T meas)
|
||||
{
|
||||
return((TSL_tDelta_T)(ref - meas));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Compute the Measurement value
|
||||
* @param[in] ref Reference value
|
||||
* @param[in] delta Delta value
|
||||
* @retval Measurement value
|
||||
*/
|
||||
TSL_tMeas_T TSL_acq_ComputeMeas(TSL_tRef_T ref, TSL_tDelta_T delta)
|
||||
{
|
||||
return((TSL_tMeas_T)(ref - delta));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Check noise (not used)
|
||||
* @param None
|
||||
* @retval Status
|
||||
*/
|
||||
TSL_AcqStatus_enum_T TSL_acq_CheckNoise(void)
|
||||
{
|
||||
return TSL_ACQ_STATUS_OK;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Check if a filter must be used on the current channel (not used)
|
||||
* @param[in] pCh Pointer on the channel data information
|
||||
* @retval Result TRUE if a filter can be applied
|
||||
*/
|
||||
TSL_Bool_enum_T TSL_acq_UseFilter(TSL_ChannelData_T *pCh)
|
||||
{
|
||||
return TSL_TRUE;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Test if the Reference is incorrect (not used)
|
||||
* @param[in] pCh Pointer on the channel data information
|
||||
* @retval Result TRUE if the Reference is out of range
|
||||
*/
|
||||
TSL_Bool_enum_T TSL_acq_TestReferenceOutOfRange(TSL_ChannelData_T *pCh)
|
||||
{
|
||||
return TSL_FALSE;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Test if the measure has crossed the reference target (not used)
|
||||
* @param[in] pCh Pointer on the channel data information
|
||||
* @param[in] new_meas Measure of the last acquisition on this channel
|
||||
* @retval Result TRUE if the Reference is valid
|
||||
*/
|
||||
TSL_Bool_enum_T TSL_acq_TestFirstReferenceIsValid(TSL_ChannelData_T *pCh, TSL_tMeas_T new_meas)
|
||||
{
|
||||
return TSL_TRUE;
|
||||
}
|
||||
|
||||
|
||||
#if defined(__IAR_SYSTEMS_ICC__) // IAR/EWARM
|
||||
#pragma optimize=low
|
||||
#elif defined(__CC_ARM) // Keil/MDK-ARM
|
||||
#pragma O1
|
||||
#pragma Ospace
|
||||
#elif defined(__TASKING__) // Altium/Tasking
|
||||
#pragma optimize O0
|
||||
#elif defined(__GNUC__) // Atollic/True Studio + Raisonance/RKit
|
||||
#pragma GCC push_options
|
||||
#pragma GCC optimize ("O0")
|
||||
#endif
|
||||
/**
|
||||
* @brief Software delay (private routine)
|
||||
* @param val Wait delay
|
||||
* @retval None
|
||||
*/
|
||||
void SoftDelay(uint32_t val)
|
||||
{
|
||||
__IO uint32_t i;
|
||||
for (i = val; i > 0; i--)
|
||||
{}
|
||||
}
|
||||
#if defined(__TASKING__)
|
||||
#pragma endoptimize
|
||||
#endif
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
File diff suppressed because it is too large
Load diff
|
|
@ -0,0 +1,834 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file tsl_acq_stm32l1xx_hw.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.3.2
|
||||
* @date 22-January-2013
|
||||
* @brief This file contains all functions to manage the acquisition
|
||||
* on STM32l1xx products using the Hardware mode (with Timers).
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "tsl_acq_stm32l1xx_hw.h"
|
||||
#include "tsl_globals.h"
|
||||
|
||||
/* Private typedefs ----------------------------------------------------------*/
|
||||
|
||||
// Register configuration
|
||||
typedef struct
|
||||
{
|
||||
unsigned int RI_ASCR : 3;
|
||||
unsigned int RI_ASCR_bit : 5;
|
||||
} TSL_RIConf_t;
|
||||
|
||||
/* Private defines -----------------------------------------------------------*/
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
|
||||
#define IS_BANK_INDEX_OK(INDEX) (((INDEX) == 0) || (((INDEX) > 0) && ((INDEX) < TSLPRM_TOTAL_BANKS)))
|
||||
|
||||
#define TSL_CHANNEL_PORT(channel) (channel >> 4)
|
||||
#define TSL_CHANNEL_IO(channel) (channel & 0x0F)
|
||||
|
||||
#define TSL_GPIO_AFR(channel) ((TSL_CHANNEL_IO(channel) < 8) ? 0 : 1)
|
||||
#define TSL_GPIO_AFR_Shift(channel) ((TSL_CHANNEL_IO(channel) < 8) ? (4 * TSL_CHANNEL_IO(channel)) : (4 * (TSL_CHANNEL_IO(channel) - 8)))
|
||||
|
||||
#define TSL_CPRI_HYSCR_MASK(channel) (1 << TSL_CHANNEL_IO(channel))
|
||||
#define TSL_CPRI_ASMR_MASK(channel) (1 << TSL_CHANNEL_IO(channel))
|
||||
#define TSL_CPRI_CMR_MASK(channel) (1 << TSL_CHANNEL_IO(channel))
|
||||
#define TSL_CPRI_CICR_MASK(channel) (1 << TSL_CHANNEL_IO(channel))
|
||||
|
||||
#define TSL_RCC_AHBENR_Config(channel) (RCC->AHBENR |= TSL_GPIO_Clock_LookUpTable[TSL_CHANNEL_PORT(channel)])
|
||||
|
||||
#define TSL_CPRI_ASCR_Config(channel) (*TSL_CPRI_ASCR_LookUpTable[TSL_RI_Conf_LookUpTable[channel].RI_ASCR] |= (1 << (TSL_RI_Conf_LookUpTable[channel].RI_ASCR_bit)))
|
||||
#define TSL_CPRI_HYSCR_Config(channel) (*TSL_CPRI_HYSCR_LookUpTable[TSL_CHANNEL_PORT(channel)] |= TSL_CPRI_HYSCR_MASK(channel))
|
||||
#define TSL_CPRI_ASMR_Config(channel) (*TSL_CPRI_ASMR_LookUpTable[TSL_CHANNEL_PORT(channel)] |= TSL_CPRI_ASMR_MASK(channel))
|
||||
#define TSL_CPRI_ASMR_Config_Clear(channel) (*TSL_CPRI_ASMR_LookUpTable[TSL_CHANNEL_PORT(channel)] &= (uint32_t)(~TSL_CPRI_ASMR_MASK(channel)))
|
||||
#define TSL_CPRI_CMR_Config(channel) (*TSL_CPRI_CMR_LookUpTable[TSL_CHANNEL_PORT(channel)] |= TSL_CPRI_CMR_MASK(channel))
|
||||
#define TSL_CPRI_CMR_Config_Clear(channel) (*TSL_CPRI_CMR_LookUpTable[TSL_CHANNEL_PORT(channel)] &= (uint32_t)(~TSL_CPRI_CMR_MASK(channel)))
|
||||
#define TSL_CPRI_CICR_Config(channel) (*TSL_CPRI_CICR_LookUpTable[TSL_CHANNEL_PORT(channel)] |= TSL_CPRI_CICR_MASK(channel))
|
||||
#define TSL_CPRI_CICR_Config_Clear(channel) (*TSL_CPRI_CICR_LookUpTable[TSL_CHANNEL_PORT(channel)] &= (uint32_t)(~TSL_CPRI_CICR_MASK(channel)))
|
||||
|
||||
#define TSL_GPIO_MODER_IN_Config(channel) (TSL_GPIO_LookUpTable[TSL_CHANNEL_PORT(channel)]->MODER &= (uint32_t)(~(3 << (2 * TSL_CHANNEL_IO(channel)))))
|
||||
#define TSL_GPIO_MODER_AF_Config(channel) (TSL_GPIO_LookUpTable[TSL_CHANNEL_PORT(channel)]->MODER = (TSL_GPIO_LookUpTable[TSL_CHANNEL_PORT(channel)]->MODER & (uint32_t)(~(3 << (2 * TSL_CHANNEL_IO(channel))))) | (2 << (2 * TSL_CHANNEL_IO(channel))))
|
||||
#define TSL_GPIO_MODER_OUT_Config(channel) (TSL_GPIO_LookUpTable[TSL_CHANNEL_PORT(channel)]->MODER = (TSL_GPIO_LookUpTable[TSL_CHANNEL_PORT(channel)]->MODER & (uint32_t)(~(3 << (2 * TSL_CHANNEL_IO(channel))))) | (1 << (2 * TSL_CHANNEL_IO(channel))))
|
||||
#define TSL_GPIO_PUPDR_NO_PUPD_Config(channel) (TSL_GPIO_LookUpTable[TSL_CHANNEL_PORT(channel)]->PUPDR &= (uint32_t)(~(3 << (2 * TSL_CHANNEL_IO(channel)))))
|
||||
#define TSL_GPIO_OTYPER_PP_Config(channel) (TSL_GPIO_LookUpTable[TSL_CHANNEL_PORT(channel)]->OTYPER &= (uint32_t)(~(1 << TSL_CHANNEL_IO(channel))))
|
||||
#define TSL_GPIO_OSPEEDR_VL_Config(channel) (TSL_GPIO_LookUpTable[TSL_CHANNEL_PORT(channel)]->OSPEEDR &= (uint32_t)~(3 << (2 * TSL_CHANNEL_IO(channel))))
|
||||
#define TSL_GPIO_AFR_Config(channel) (TSL_GPIO_LookUpTable[TSL_CHANNEL_PORT(channel)]->AFR[TSL_GPIO_AFR(channel)] |= (0x0E << (TSL_GPIO_AFR_Shift(channel))))
|
||||
#define TSL_GPIO_BS_Config(channel) (TSL_GPIO_LookUpTable[TSL_CHANNEL_PORT(channel)]->BSRRL = (uint16_t)(1 << (TSL_CHANNEL_IO(channel))))
|
||||
#define TSL_GPIO_BR_Config(channel) (TSL_GPIO_LookUpTable[TSL_CHANNEL_PORT(channel)]->BSRRH = (uint16_t)(1 << (TSL_CHANNEL_IO(channel))))
|
||||
|
||||
#define TSL_GPIO_AFR_NOAF_Config(channel) (TSL_GPIO_LookUpTable[TSL_CHANNEL_PORT(channel)]->AFR[TSL_GPIO_AFR(channel)] &= (uint32_t)(~(0x0F << (TSL_GPIO_AFR_Shift(channel)))))
|
||||
|
||||
#define TSL_GPIO_IDR_XOR_CPRI_CMR(channel) ((TSL_GPIO_LookUpTable[TSL_CHANNEL_PORT(channel)]->IDR)^(*TSL_CPRI_CMR_LookUpTable[TSL_CHANNEL_PORT(channel)]))
|
||||
#define TSL_GPIO_IDR_AND_CPRI_CMR(channel) ((TSL_GPIO_LookUpTable[TSL_CHANNEL_PORT(channel)]->IDR)&(*TSL_CPRI_CMR_LookUpTable[TSL_CHANNEL_PORT(channel)]))
|
||||
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
CONST TSL_Bank_T *bank;
|
||||
TSL_tIndex_T NumberOfChannelOn = 0;
|
||||
TSL_tNb_T NumberOfChannels = 0;
|
||||
uint32_t tab_MeasurementCounter[11];
|
||||
TSL_Status_enum_T TSL_Acq_Status = TSL_STATUS_BUSY;
|
||||
static uint16_t GroupToCheck = 0;
|
||||
static TSL_tIndex_T NumberOfChannelChecked = 0;
|
||||
|
||||
uint32_t TSL_GPIO_Clock_LookUpTable[] = {RCC_AHBPeriph_GPIOA, RCC_AHBPeriph_GPIOB, RCC_AHBPeriph_GPIOC, RCC_AHBPeriph_GPIOD, RCC_AHBPeriph_GPIOE, RCC_AHBPeriph_GPIOF, RCC_AHBPeriph_GPIOG, RCC_AHBPeriph_GPIOH};
|
||||
GPIO_TypeDef *TSL_GPIO_LookUpTable[] = {GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH};
|
||||
|
||||
uint32_t *TSL_CPRI_ASCR_LookUpTable[] = {(uint32_t *)&CPRI->ASCR1, (uint32_t *)&CPRI->ASCR2};
|
||||
|
||||
uint16_t *TSL_CPRI_HYSCR_LookUpTable[] =
|
||||
{
|
||||
(uint16_t *)&CPRI->HYSCR1, (uint16_t *)&CPRI->HYSCR1 + 1,
|
||||
(uint16_t *)&CPRI->HYSCR2, (uint16_t *)&CPRI->HYSCR2 + 1,
|
||||
(uint16_t *)&CPRI->HYSCR3, (uint16_t *)&CPRI->HYSCR3 + 1,
|
||||
(uint16_t *)&CPRI->HYSCR4, (uint16_t *)&CPRI->HYSCR4 + 1
|
||||
};
|
||||
|
||||
uint32_t *TSL_CPRI_ASMR_LookUpTable[] = {(uint32_t *)&CPRI->ASMR1, (uint32_t *)&CPRI->ASMR2, (uint32_t *)&CPRI->ASMR3, 0, 0, (uint32_t *)&CPRI->ASMR4, (uint32_t *)&CPRI->ASMR5};
|
||||
uint32_t *TSL_CPRI_CMR_LookUpTable[] = {(uint32_t *)&CPRI->CMR1, (uint32_t *)&CPRI->CMR2, (uint32_t *)&CPRI->CMR3, 0, 0, (uint32_t *)&CPRI->CMR4, (uint32_t *)&CPRI->CMR5};
|
||||
uint32_t *TSL_CPRI_CICR_LookUpTable[] = {(uint32_t *)&CPRI->CICR1, (uint32_t *)&CPRI->CICR2, (uint32_t *)&CPRI->CICR3, 0, 0, (uint32_t *)&CPRI->CICR4, (uint32_t *)&CPRI->CICR5};
|
||||
|
||||
CONST TSL_RIConf_t TSL_RI_Conf_LookUpTable[101] =
|
||||
{
|
||||
{0, 0},
|
||||
{0, 1},
|
||||
{0, 2},
|
||||
{0, 3},
|
||||
{0, 0},//padding
|
||||
{0, 0},//padding
|
||||
{0, 6},
|
||||
{0, 7},
|
||||
{1, 9},
|
||||
{1, 10},
|
||||
{1, 11},
|
||||
{1, 15},
|
||||
{0, 0},//padding
|
||||
{1, 6},
|
||||
{1, 7},
|
||||
{1, 8},
|
||||
|
||||
{0, 8},
|
||||
{0, 9},
|
||||
{1, 16},
|
||||
{0, 0},//padding
|
||||
{1, 4},
|
||||
{1, 5},
|
||||
{1, 27},
|
||||
{1, 28},
|
||||
{0, 0},//padding
|
||||
{0, 0},//padding
|
||||
{0, 0},//padding
|
||||
{0, 0},//padding
|
||||
{0, 18},
|
||||
{0, 19},
|
||||
{0, 20},
|
||||
{0, 21},
|
||||
|
||||
{0, 10},
|
||||
{0, 11},
|
||||
{0, 12},
|
||||
{0, 13},
|
||||
{0, 14},
|
||||
{0, 15},
|
||||
{1, 0},
|
||||
{1, 1},
|
||||
{1, 2},
|
||||
{1, 3},
|
||||
{1, 29},
|
||||
{0, 0},//padding
|
||||
{0, 0},//padding
|
||||
{0, 0},//padding
|
||||
{0, 0},//padding
|
||||
{0, 0},//padding
|
||||
|
||||
{0, 0},//padding
|
||||
{0, 0},//padding
|
||||
{0, 0},//padding
|
||||
{0, 0},//padding
|
||||
{0, 0},//padding
|
||||
{0, 0},//padding
|
||||
{0, 0},//padding
|
||||
{0, 0},//padding
|
||||
{0, 0},//padding
|
||||
{0, 0},//padding
|
||||
{0, 0},//padding
|
||||
{0, 0},//padding
|
||||
{0, 0},//padding
|
||||
{0, 0},//padding
|
||||
{0, 0},//padding
|
||||
{0, 0},//padding
|
||||
|
||||
{0, 0},//padding
|
||||
{0, 0},//padding
|
||||
{0, 0},//padding
|
||||
{0, 0},//padding
|
||||
{0, 0},//padding
|
||||
{0, 0},//padding
|
||||
{0, 0},//padding
|
||||
{0, 0},//padding
|
||||
{0, 0},//padding
|
||||
{0, 0},//padding
|
||||
{0, 0},//padding
|
||||
{0, 0},//padding
|
||||
{0, 0},//padding
|
||||
{0, 0},//padding
|
||||
{0, 0},//padding
|
||||
{0, 0},//padding
|
||||
|
||||
{0, 0},//padding
|
||||
{0, 0},//padding
|
||||
{0, 0},//padding
|
||||
{0, 0},//padding
|
||||
{0, 0},//padding
|
||||
{0, 0},//padding
|
||||
{0, 27},
|
||||
{0, 28},
|
||||
{0, 29},
|
||||
{0, 30},
|
||||
{0, 16},
|
||||
{1, 17},
|
||||
{1, 18},
|
||||
{1, 19},
|
||||
{1, 20},
|
||||
{1, 21},
|
||||
|
||||
{1, 22},
|
||||
{1, 23},
|
||||
{1, 24},
|
||||
{1, 25},
|
||||
{1, 26}
|
||||
};
|
||||
|
||||
/* Private functions prototype -----------------------------------------------*/
|
||||
void TSL_Init_GPIOs(void);
|
||||
void TSL_Init_TIMs(void);
|
||||
void TSL_Init_RI(void);
|
||||
uint8_t TSL_Check_GPIO_IDR(uint8_t sample);
|
||||
void SoftDelay(uint16_t val);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Initializes the TouchSensing GPIOs.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void TSL_Init_GPIOs(void)
|
||||
{
|
||||
CONST TSL_Bank_T *LocalBank = &(TSL_Globals.Bank_Array[0]);
|
||||
TSL_tNb_T NumberOfBanks = TSLPRM_TOTAL_BANKS;
|
||||
TSL_tNb_T LocalNumberOfChannels = 0;
|
||||
TSL_tIndex_T idx_bk;
|
||||
TSL_tIndex_T idx_ch;
|
||||
CONST TSL_ChannelSrc_T *p_chSrc = LocalBank->p_chSrc; // Pointer to the current channel
|
||||
|
||||
for (idx_bk = 0; idx_bk < NumberOfBanks; idx_bk++)
|
||||
{
|
||||
LocalBank = &(TSL_Globals.Bank_Array[idx_bk]);
|
||||
p_chSrc = LocalBank->p_chSrc;
|
||||
|
||||
#if (TSLPRM_USE_SHIELD > 0)
|
||||
// Enables GPIOs clock
|
||||
TSL_RCC_AHBENR_Config(LocalBank->shield_sample);
|
||||
|
||||
// Bank shield configuration
|
||||
TSL_GPIO_OTYPER_PP_Config(LocalBank->shield_channel);
|
||||
TSL_GPIO_OSPEEDR_VL_Config(LocalBank->shield_channel);
|
||||
TSL_GPIO_PUPDR_NO_PUPD_Config(LocalBank->shield_channel);
|
||||
TSL_GPIO_AFR_Config(LocalBank->shield_channel);
|
||||
|
||||
TSL_GPIO_OSPEEDR_VL_Config(LocalBank->shield_sample);
|
||||
TSL_GPIO_BR_Config(LocalBank->shield_sample);
|
||||
TSL_GPIO_OTYPER_PP_Config(LocalBank->shield_sample);
|
||||
TSL_GPIO_PUPDR_NO_PUPD_Config(LocalBank->shield_sample);
|
||||
|
||||
TSL_GPIO_MODER_OUT_Config(LocalBank->shield_sample);
|
||||
TSL_GPIO_MODER_OUT_Config(LocalBank->shield_channel);
|
||||
#endif
|
||||
|
||||
LocalNumberOfChannels = LocalBank->NbChannels;
|
||||
|
||||
for (idx_ch = 0;
|
||||
idx_ch < LocalNumberOfChannels;
|
||||
idx_ch++)
|
||||
{
|
||||
TSL_RCC_AHBENR_Config(p_chSrc->t_sample);
|
||||
TSL_RCC_AHBENR_Config(p_chSrc->t_channel);
|
||||
|
||||
TSL_GPIO_OTYPER_PP_Config(p_chSrc->t_channel);
|
||||
TSL_GPIO_OSPEEDR_VL_Config(p_chSrc->t_channel);
|
||||
TSL_GPIO_PUPDR_NO_PUPD_Config(p_chSrc->t_channel);
|
||||
TSL_GPIO_AFR_Config(p_chSrc->t_channel);
|
||||
|
||||
TSL_GPIO_OSPEEDR_VL_Config(p_chSrc->t_sample);
|
||||
TSL_GPIO_BR_Config(p_chSrc->t_sample);
|
||||
TSL_GPIO_OTYPER_PP_Config(p_chSrc->t_sample);
|
||||
TSL_GPIO_PUPDR_NO_PUPD_Config(p_chSrc->t_sample);
|
||||
|
||||
TSL_GPIO_MODER_OUT_Config(p_chSrc->t_sample);
|
||||
TSL_GPIO_MODER_OUT_Config(p_chSrc->t_channel);
|
||||
|
||||
p_chSrc++;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes the TouchSensing timers.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void TSL_Init_TIMs(void)
|
||||
{
|
||||
// Enable Timers clocks
|
||||
RCC->APB2ENR |= ((1 << 4) | (1 << 2)); // TIM11, TIM9
|
||||
|
||||
//==============================
|
||||
// TIMER 9 configuration: Master
|
||||
//==============================
|
||||
// Set the option register to redirect cpri_tim9_itr_O to TIM9_itr
|
||||
TIM9->OR |= 4;
|
||||
// Set the Autoreload value (signal frequency)
|
||||
//TIM9->ARR = 64; // freq = (64*2)*31.25ns = 1us
|
||||
TIM9->ARR = TSLPRM_TIM_RELOAD; // freq = (64*2)*31.25ns = 1us
|
||||
// Set the Prescaler value
|
||||
//TIM9->PSC = 0; // fCK_CNT = 32MHz/(0+1) = 32MHz --> T=31.25ns
|
||||
TIM9->PSC = TSLPRM_TIM_PRESCALER; // fCK_CNT = 32MHz/(1+1) = 32MHz --> T=31.25ns
|
||||
// Set UP counter, Center-Aligned mode 1
|
||||
TIM9->CR1 = 0x20;
|
||||
// OC1REF used as TRGO
|
||||
TIM9->CR2 |= 0x40; // MMS=100
|
||||
// Select Master mode
|
||||
TIM9->SMCR = 0x95;
|
||||
// Set Update generation
|
||||
TIM9->EGR |= 0x01;
|
||||
|
||||
// Channel 1 PWM configuration
|
||||
// Set the Output Compare Mode, PWM2
|
||||
TIM9->CCMR1 |= 0x0070;
|
||||
// Set the Pulse value
|
||||
//TIM9->CCR1 = 34; // duty cycle
|
||||
TIM9->CCR1 = (TSLPRM_TIM_RELOAD >> 1) + 1; // duty cycle
|
||||
// Compare output enable, active high
|
||||
TIM9->CCER |= 0x01;
|
||||
|
||||
// Channel 2 PWM configuration
|
||||
// Set the Output Compare Mode, PWM2
|
||||
TIM9->CCMR1 |= 0x6000;
|
||||
// Set the Pulse value
|
||||
//TIM9->CCR2 = 30;
|
||||
TIM9->CCR2 = (TSLPRM_TIM_RELOAD >> 1) - 1;
|
||||
// Compare output enable, active high
|
||||
TIM9->CCER |= 0x10;
|
||||
|
||||
//==============================
|
||||
// TIMER 11 configuration: slave
|
||||
//==============================
|
||||
// Set the option register to redirect TIM11_ic_o to TIM11_ti
|
||||
TIM11->OR |= 8;
|
||||
// Set the option register to redirect TIM9_tgo_cktim to TIM11_etri
|
||||
TIM11->OR |= 4;
|
||||
// Set the Prescaler value
|
||||
TIM11->PSC = 0;
|
||||
// Set UP counter, edge-aligned mode
|
||||
TIM11->CR1 = 0;
|
||||
// Select Slave mode, Internal Trigger 2 (ITR2 = TIM9), External clock mode 1
|
||||
TIM11->SMCR = 0x4000; // ECE bit
|
||||
// Channel 1 configured in Input capture mode
|
||||
TIM11->CCMR1 = 0x01; // No prescaler, no filter
|
||||
// Channel 1 capture enable (CCE1 = 1)
|
||||
TIM11->CCER = 0x01;
|
||||
// Interrupt Enable, active high
|
||||
TIM11->DIER |= 0x02;
|
||||
// Start slave timer
|
||||
TIM11->CR1 |= 0x01;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Init TS routing interface.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void TSL_Init_RI(void)
|
||||
{
|
||||
CONST TSL_Bank_T *LocalBank;
|
||||
TSL_tNb_T NumberOfBanks = TSLPRM_TOTAL_BANKS;
|
||||
TSL_tNb_T LocalNumberOfChannels = 0;
|
||||
TSL_tIndex_T idx_bk;
|
||||
TSL_tIndex_T idx_ch;
|
||||
CONST TSL_ChannelSrc_T *p_chSrc; // Pointer to the current channel
|
||||
|
||||
RCC->APB1ENR |= (uint32_t)((uint32_t)1 << 31); // COMP enable
|
||||
|
||||
for (idx_bk = 0; idx_bk < NumberOfBanks; idx_bk++)
|
||||
{
|
||||
LocalBank = &(TSL_Globals.Bank_Array[idx_bk]);
|
||||
|
||||
#if (TSLPRM_USE_SHIELD > 0)
|
||||
TSL_CPRI_HYSCR_Config(LocalBank->shield_sample);
|
||||
TSL_CPRI_CICR_Config(LocalBank->shield_sample);
|
||||
TSL_CPRI_CICR_Config_Clear(LocalBank->shield_channel);
|
||||
|
||||
TSL_CPRI_ASCR_Config(LocalBank->shield_sample);
|
||||
#endif
|
||||
|
||||
LocalNumberOfChannels = LocalBank->NbChannels;
|
||||
|
||||
p_chSrc = LocalBank->p_chSrc;
|
||||
for (idx_ch = 0; idx_ch < LocalNumberOfChannels; idx_ch++)
|
||||
{
|
||||
TSL_CPRI_HYSCR_Config(p_chSrc->t_sample);
|
||||
TSL_CPRI_CICR_Config(p_chSrc->t_sample);
|
||||
TSL_CPRI_CICR_Config_Clear(p_chSrc->t_channel);
|
||||
TSL_CPRI_ASCR_Config(p_chSrc->t_sample);
|
||||
p_chSrc++;
|
||||
}
|
||||
}
|
||||
|
||||
// Reset TSUSP bit, TIM9 ITR enabled to suspend OC TIM9 generation
|
||||
COMP->CSR &= (uint32_t)(~0x80000000);
|
||||
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Initializes the acquisition module.
|
||||
* @param None
|
||||
* @retval retval
|
||||
*/
|
||||
TSL_Status_enum_T TSL_acq_Init(void)
|
||||
{
|
||||
NVIC_InitTypeDef NVIC_InitStructure;
|
||||
|
||||
NVIC_InitStructure.NVIC_IRQChannel = TIM11_IRQn;
|
||||
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;
|
||||
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 1;
|
||||
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
|
||||
NVIC_Init(&NVIC_InitStructure);
|
||||
|
||||
TSL_Init_GPIOs();
|
||||
TSL_Init_TIMs();
|
||||
TSL_Init_RI();
|
||||
|
||||
return TSL_STATUS_OK;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Configures a Bank.
|
||||
* @param[in] idx_bk Index of the Bank to configure
|
||||
* @retval Status
|
||||
*/
|
||||
TSL_Status_enum_T TSL_acq_BankConfig(TSL_tIndex_T idx_bk)
|
||||
{
|
||||
TSL_tIndex_T idx_dest;
|
||||
TSL_tIndex_T idx_ch;
|
||||
CONST TSL_ChannelDest_T *p_chDest; // Pointer to the current channel
|
||||
CONST TSL_ChannelSrc_T *p_chSrc; // Pointer to the current channel
|
||||
|
||||
// Check parameters (if USE_FULL_ASSERT is defined)
|
||||
assert_param(IS_BANK_INDEX_OK(idx_bk));
|
||||
|
||||
bank = &(TSL_Globals.Bank_Array[idx_bk]);
|
||||
|
||||
NumberOfChannels = bank->NbChannels;
|
||||
|
||||
GroupToCheck = 0;//init group to check
|
||||
NumberOfChannelOn = 0;//init number of channel on
|
||||
|
||||
// init CPRI ASMR
|
||||
CPRI->ASMR1 = 0;
|
||||
CPRI->ASMR2 = 0;
|
||||
CPRI->ASMR3 = 0;
|
||||
CPRI->ASMR4 = 0;
|
||||
CPRI->ASMR5 = 0;
|
||||
|
||||
p_chDest = bank->p_chDest;
|
||||
p_chSrc = bank->p_chSrc;
|
||||
for (idx_ch = 0; idx_ch < NumberOfChannels; idx_ch++)
|
||||
{
|
||||
// Get index in the result array associated to the current channel
|
||||
idx_dest = p_chDest->IdxDest;
|
||||
if (bank->p_chData[idx_dest].Flags.ObjStatus != TSL_OBJ_STATUS_OFF)
|
||||
{
|
||||
TSL_CPRI_CMR_Config(p_chSrc->t_sample);
|
||||
TSL_CPRI_ASMR_Config(p_chSrc->t_channel);
|
||||
GroupToCheck |= (1 << (p_chSrc->IdxSrc));
|
||||
NumberOfChannelOn++;
|
||||
}
|
||||
p_chDest++;
|
||||
p_chSrc++;
|
||||
}
|
||||
|
||||
return TSL_STATUS_OK;
|
||||
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Start acquisition on a previously configured bank
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void TSL_acq_BankStartAcq(void)
|
||||
{
|
||||
#if (TSLPRM_IODEF > 0)
|
||||
CONST TSL_Bank_T *LocalBank = &(TSL_Globals.Bank_Array[0]);
|
||||
TSL_tNb_T NumberOfBanks = TSLPRM_TOTAL_BANKS;
|
||||
TSL_tNb_T LocalNumberOfChannels = 0;
|
||||
TSL_tIndex_T BankIndex;
|
||||
#endif
|
||||
CONST TSL_ChannelSrc_T *p_chSrc;
|
||||
CONST TSL_ChannelDest_T *p_chDest;
|
||||
TSL_tIndex_T idx_dest;
|
||||
TSL_tIndex_T idx_ch;
|
||||
|
||||
if (NumberOfChannelOn)
|
||||
{
|
||||
#if (TSLPRM_IODEF > 0)
|
||||
//============================
|
||||
// All GPIOs in Input floating
|
||||
//============================
|
||||
for (BankIndex = 0; BankIndex < NumberOfBanks; BankIndex++)
|
||||
{
|
||||
LocalBank = &(TSL_Globals.Bank_Array[BankIndex]);
|
||||
p_chSrc = LocalBank->p_chSrc;
|
||||
|
||||
#if (TSLPRM_USE_SHIELD > 0)
|
||||
TSL_GPIO_MODER_IN_Config(LocalBank->shield_sample);
|
||||
TSL_GPIO_MODER_IN_Config(LocalBank->shield_channel);
|
||||
#endif
|
||||
|
||||
LocalNumberOfChannels = LocalBank->NbChannels;
|
||||
|
||||
for (idx_ch = 0;
|
||||
idx_ch < LocalNumberOfChannels;
|
||||
idx_ch++)
|
||||
{
|
||||
TSL_GPIO_MODER_IN_Config(p_chSrc->t_sample);
|
||||
TSL_GPIO_MODER_IN_Config(p_chSrc->t_channel);
|
||||
|
||||
p_chSrc++;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
// Reset count
|
||||
TIM11->CNT = 0;
|
||||
|
||||
// Discharge sample capacitors
|
||||
p_chDest = bank->p_chDest;
|
||||
p_chSrc = bank->p_chSrc;
|
||||
for (idx_ch = 0; idx_ch < NumberOfChannels; idx_ch++)
|
||||
{
|
||||
// Get index in the result array associated to the current channel
|
||||
idx_dest = p_chDest->IdxDest;
|
||||
if (bank->p_chData[idx_dest].Flags.ObjStatus != TSL_OBJ_STATUS_OFF)
|
||||
{
|
||||
TSL_GPIO_MODER_OUT_Config(p_chSrc->t_sample);
|
||||
}
|
||||
p_chDest++;
|
||||
p_chSrc++;
|
||||
}
|
||||
|
||||
#if (TSLPRM_USE_SHIELD > 0)
|
||||
// Discharge shield sample capacitor
|
||||
TSL_GPIO_MODER_OUT_Config(bank->shield_sample);
|
||||
#endif
|
||||
|
||||
// Wait for capa discharge
|
||||
SoftDelay(0x80);
|
||||
|
||||
#if (TSLPRM_USE_SHIELD > 0)
|
||||
// Init sample shield in floating input
|
||||
TSL_GPIO_MODER_IN_Config(bank->shield_sample);
|
||||
TSL_GPIO_MODER_AF_Config(bank->shield_channel);
|
||||
|
||||
TSL_CPRI_ASMR_Config(bank->shield_channel);
|
||||
#endif
|
||||
|
||||
// Init samples in floating input and channels in alternate
|
||||
p_chDest = bank->p_chDest;
|
||||
p_chSrc = bank->p_chSrc;
|
||||
for (idx_ch = 0; idx_ch < NumberOfChannels; idx_ch++)
|
||||
{
|
||||
// Get index in the result array associated to the current channel
|
||||
idx_dest = p_chDest->IdxDest;
|
||||
|
||||
if (bank->p_chData[idx_dest].Flags.ObjStatus != TSL_OBJ_STATUS_OFF)
|
||||
{
|
||||
TSL_GPIO_MODER_IN_Config(p_chSrc->t_sample);
|
||||
TSL_GPIO_MODER_AF_Config(p_chSrc->t_channel);
|
||||
}
|
||||
|
||||
p_chDest++;
|
||||
p_chSrc++;
|
||||
}
|
||||
|
||||
/* Start acquisition */
|
||||
TSL_Acq_Status = TSL_STATUS_BUSY;
|
||||
TIM9 ->CR1 |= 0x01; // Master
|
||||
}
|
||||
else
|
||||
{
|
||||
TSL_Acq_Status = TSL_STATUS_OK;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Wait end of acquisition
|
||||
* @param None
|
||||
* @retval status
|
||||
*/
|
||||
TSL_Status_enum_T TSL_acq_BankWaitEOC(void)
|
||||
{
|
||||
return TSL_Acq_Status;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Return the current measure
|
||||
* @param[in] index Index of the measure source
|
||||
* @retval Measure
|
||||
*/
|
||||
TSL_tMeas_T TSL_acq_GetMeas(TSL_tIndex_T index)
|
||||
{
|
||||
return(tab_MeasurementCounter[index]);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Check noise (not used)
|
||||
* @param None
|
||||
* @retval Status
|
||||
*/
|
||||
TSL_AcqStatus_enum_T TSL_acq_CheckNoise(void)
|
||||
{
|
||||
return TSL_ACQ_STATUS_OK;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Check GPIO IDR for the sample
|
||||
* @param[in] sample
|
||||
* @retval Status
|
||||
*/
|
||||
uint8_t TSL_Check_GPIO_IDR(uint8_t sample)
|
||||
{
|
||||
GPIO_TypeDef *GPIO;
|
||||
uint32_t GPIO_IDR_Mask = 0;
|
||||
|
||||
GPIO = TSL_GPIO_LookUpTable[TSL_CHANNEL_PORT(sample)];
|
||||
|
||||
GPIO_IDR_Mask = (1 << (sample & 0x0F));
|
||||
|
||||
if (((GPIO->IDR) & GPIO_IDR_Mask) == GPIO_IDR_Mask)
|
||||
{
|
||||
return 1;
|
||||
}
|
||||
else
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Process the TS Interrupt routine
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void TSL_acq_ProcessIT(void)
|
||||
{
|
||||
CONST TSL_Bank_T *LocalBank = &(TSL_Globals.Bank_Array[0]);
|
||||
TSL_tNb_T NumberOfBanks = TSLPRM_TOTAL_BANKS;
|
||||
TSL_tNb_T LocalNumberOfChannels = 0;
|
||||
TSL_tIndex_T BankIndex;
|
||||
|
||||
CONST TSL_ChannelSrc_T *p_chSrc;
|
||||
CONST TSL_ChannelDest_T *p_chDest;
|
||||
TSL_tIndex_T idx_dest;
|
||||
TSL_tIndex_T idx_ch;
|
||||
|
||||
// Reset flags
|
||||
TIM11->SR = 0;
|
||||
idx_ch = 0;
|
||||
|
||||
p_chDest = bank->p_chDest;
|
||||
p_chSrc = bank->p_chSrc;
|
||||
do
|
||||
{
|
||||
// Get index in the result array associated to the current channel
|
||||
idx_dest = p_chDest->IdxDest;
|
||||
|
||||
if (bank->p_chData[idx_dest].Flags.ObjStatus != TSL_OBJ_STATUS_OFF)
|
||||
{
|
||||
if ((TSL_Check_GPIO_IDR(p_chSrc->t_sample)) &&
|
||||
((GroupToCheck & (1 << (p_chSrc->IdxSrc))) == (1 << (p_chSrc->IdxSrc))))
|
||||
{
|
||||
tab_MeasurementCounter[p_chSrc->IdxSrc] = TIM11->CCR1;
|
||||
NumberOfChannelChecked++;
|
||||
GroupToCheck &= (uint32_t)(~(1 << (p_chSrc->IdxSrc)));
|
||||
|
||||
// Reset CMR register to restart the timer
|
||||
TSL_CPRI_CMR_Config_Clear(p_chSrc->t_sample);
|
||||
}
|
||||
}
|
||||
p_chDest++;
|
||||
p_chSrc++;
|
||||
idx_ch++;
|
||||
}
|
||||
while (idx_ch < NumberOfChannels);
|
||||
|
||||
if (NumberOfChannelChecked >= NumberOfChannelOn)
|
||||
{
|
||||
NumberOfChannelOn = 0;
|
||||
NumberOfChannelChecked = 0;
|
||||
|
||||
// Disable master counter
|
||||
TIM9->CR1 &= (uint16_t)(~0x01);
|
||||
|
||||
//====================
|
||||
// All GPIOs in PP Low
|
||||
//====================
|
||||
for (BankIndex = 0; BankIndex < NumberOfBanks; BankIndex++)
|
||||
{
|
||||
LocalBank = &(TSL_Globals.Bank_Array[BankIndex]);
|
||||
p_chSrc = LocalBank->p_chSrc;
|
||||
|
||||
#if (TSLPRM_USE_SHIELD > 0)
|
||||
TSL_GPIO_BR_Config(LocalBank->shield_sample);
|
||||
TSL_GPIO_BR_Config(LocalBank->shield_channel);
|
||||
TSL_GPIO_MODER_OUT_Config(LocalBank->shield_sample);
|
||||
TSL_GPIO_MODER_OUT_Config(LocalBank->shield_channel);
|
||||
#endif
|
||||
|
||||
LocalNumberOfChannels = LocalBank->NbChannels;
|
||||
|
||||
for (idx_ch = 0;
|
||||
idx_ch < LocalNumberOfChannels;
|
||||
idx_ch++)
|
||||
{
|
||||
TSL_GPIO_BR_Config(p_chSrc->t_sample);
|
||||
TSL_GPIO_BR_Config(p_chSrc->t_channel);
|
||||
TSL_GPIO_MODER_OUT_Config(p_chSrc->t_sample);
|
||||
TSL_GPIO_MODER_OUT_Config(p_chSrc->t_channel);
|
||||
|
||||
p_chSrc++;
|
||||
}
|
||||
}
|
||||
TSL_Acq_Status = TSL_STATUS_OK;
|
||||
}
|
||||
|
||||
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Check if a filter must be used on the current channel (not used)
|
||||
* @param[in] pCh Pointer on the channel data information
|
||||
* @retval Result TRUE if a filter can be applied
|
||||
*/
|
||||
TSL_Bool_enum_T TSL_acq_UseFilter(TSL_ChannelData_T *pCh)
|
||||
{
|
||||
return TSL_TRUE;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Compute the Delta value
|
||||
* @param[in] ref Reference value
|
||||
* @param[in] meas Last Measurement value
|
||||
* @retval Delta value
|
||||
*/
|
||||
TSL_tDelta_T TSL_acq_ComputeDelta(TSL_tRef_T ref, TSL_tMeas_T meas)
|
||||
{
|
||||
return((TSL_tDelta_T)(ref - meas));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Compute the Measurement value
|
||||
* @param[in] ref Reference value
|
||||
* @param[in] delta Delta value
|
||||
* @retval Measurement value
|
||||
*/
|
||||
TSL_tMeas_T TSL_acq_ComputeMeas(TSL_tRef_T ref, TSL_tDelta_T delta)
|
||||
{
|
||||
return((TSL_tMeas_T)(ref - delta));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Test if the Reference is incorrect (not used)
|
||||
* @param[in] pCh Pointer on the channel data information
|
||||
* @retval Result TRUE if the Reference is out of range
|
||||
*/
|
||||
TSL_Bool_enum_T TSL_acq_TestReferenceOutOfRange(TSL_ChannelData_T *pCh)
|
||||
{
|
||||
return TSL_FALSE;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Test if the measure has crossed the reference target (not used)
|
||||
* @param[in] pCh Pointer on the channel data information
|
||||
* @param[in] new_meas Measure of the last acquisition on this channel
|
||||
* @retval Result TRUE if the Reference is valid
|
||||
*/
|
||||
TSL_Bool_enum_T TSL_acq_TestFirstReferenceIsValid(TSL_ChannelData_T *pCh, TSL_tMeas_T new_meas)
|
||||
{
|
||||
return TSL_TRUE;
|
||||
}
|
||||
|
||||
|
||||
#if defined(__IAR_SYSTEMS_ICC__) // IAR/EWARM
|
||||
#pragma optimize=medium
|
||||
#elif defined(__CC_ARM) // Keil/MDK-ARM
|
||||
#pragma O1
|
||||
#pragma Ospace
|
||||
#elif defined(__TASKING__) // Altium/Tasking
|
||||
#pragma optimize O0
|
||||
#elif defined(__GNUC__) // Atollic/True Studio + Raisonance/RKit
|
||||
#pragma GCC push_options
|
||||
#pragma GCC optimize ("O0")
|
||||
#endif
|
||||
/**
|
||||
* @brief Software delay (private routine)
|
||||
* @param val Wait delay
|
||||
* With fHCLK = 32MHz: 1 = ~1µs, 50 = ~14µs, 100 = ~25µs, 200 = ~50µs
|
||||
* @retval None
|
||||
*/
|
||||
void SoftDelay(uint16_t val)
|
||||
{
|
||||
__IO uint16_t i;
|
||||
for (i = val; i > 0; i--)
|
||||
{}
|
||||
}
|
||||
#if defined(__TASKING__)
|
||||
#pragma endoptimize
|
||||
#endif
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
|
|
@ -0,0 +1,942 @@
|
|||
/**
|
||||
******************************************************************************
|
||||
* @file tsl_acq_stm32l1xx_sw.c
|
||||
* @author MCD Application Team
|
||||
* @version V1.3.2
|
||||
* @date 22-January-2013
|
||||
* @brief This file contains all functions to manage the acquisition
|
||||
* on STM32l1xx products using the software mode.
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>
|
||||
*
|
||||
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
|
||||
* You may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at:
|
||||
*
|
||||
* http://www.st.com/software_license_agreement_liberty_v2
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
/* Includes ------------------------------------------------------------------*/
|
||||
#include "tsl_acq_stm32l1xx_sw.h"
|
||||
#include "tsl_globals.h"
|
||||
|
||||
/* Private typedefs ----------------------------------------------------------*/
|
||||
|
||||
// Register configuration
|
||||
typedef struct
|
||||
{
|
||||
unsigned int RI_ASCR : 3;
|
||||
unsigned int RI_ASCR_bit : 5;
|
||||
} TSL_RIConf_t;
|
||||
|
||||
/* Private defines -----------------------------------------------------------*/
|
||||
#define SIZEOFBANKCONF (17) //2 mask RIRs + 5 ports x 3 mask registers(MODER input, output, ODR) => 17 registers
|
||||
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
#define IS_BANK_INDEX_OK(INDEX) (((INDEX) == 0) || (((INDEX) > 0) && ((INDEX) < TSLPRM_TOTAL_BANKS)))
|
||||
|
||||
#define TSL_CHANNEL_PORT(channel) (channel >> 4)
|
||||
#define TSL_CHANNEL_IO(channel) (channel & 0x0F)
|
||||
|
||||
|
||||
#define TSL_RI_HYSCR_MASK(channel) (1 << TSL_CHANNEL_IO(channel))
|
||||
|
||||
#define TSL_RCC_AHBENR_Config(channel) (RCC->AHBENR |= TSL_GPIO_Clock_LookUpTable[TSL_CHANNEL_PORT(channel)])
|
||||
|
||||
#define TSL_RI_HYSCR_Config(channel) (*TSL_RI_HYSCR_LookUpTable[TSL_CHANNEL_PORT(channel)] |= TSL_RI_HYSCR_MASK(channel))
|
||||
|
||||
#define TSL_GPIO_MODER_IN_Config(channel) (TSL_GPIO_LookUpTable[TSL_CHANNEL_PORT(channel)]->MODER &= (uint32_t)(~(3 << (2 * TSL_CHANNEL_IO(channel)))))
|
||||
#define TSL_GPIO_MODER_OUT_Config(channel) (TSL_GPIO_LookUpTable[TSL_CHANNEL_PORT(channel)]->MODER = (TSL_GPIO_LookUpTable[TSL_CHANNEL_PORT(channel)]->MODER & (uint32_t)(~(3 << (2 * TSL_CHANNEL_IO(channel))))) | (1 << (2 * TSL_CHANNEL_IO(channel))))
|
||||
#define TSL_GPIO_PUPDR_NO_PUPD_Config(channel) (TSL_GPIO_LookUpTable[TSL_CHANNEL_PORT(channel)]->PUPDR &= (uint32_t)(~(3 << (2 * TSL_CHANNEL_IO(channel)))))
|
||||
#define TSL_GPIO_OTYPER_PP_Config(channel) (TSL_GPIO_LookUpTable[TSL_CHANNEL_PORT(channel)]->OTYPER &= (uint32_t)(~(1 << TSL_CHANNEL_IO(channel))))
|
||||
#define TSL_GPIO_OSPEEDR_VL_Config(channel) (TSL_GPIO_LookUpTable[TSL_CHANNEL_PORT(channel)]->OSPEEDR &= (uint32_t)~(3 << (2 * TSL_CHANNEL_IO(channel))))
|
||||
#define TSL_GPIO_BS_Config(channel) (TSL_GPIO_LookUpTable[TSL_CHANNEL_PORT(channel)]->BSRRL = (uint16_t)(1 << (TSL_CHANNEL_IO(channel))))
|
||||
#define TSL_GPIO_BR_Config(channel) (TSL_GPIO_LookUpTable[TSL_CHANNEL_PORT(channel)]->BSRRH = (uint16_t)(1 << (TSL_CHANNEL_IO(channel))))
|
||||
|
||||
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
uint32_t TSL_BankSampleConf[SIZEOFBANKCONF];
|
||||
uint32_t TSL_BankChannelConf[SIZEOFBANKCONF];
|
||||
uint32_t tab_MeasurementCounter[11];
|
||||
extern TSL_Params_T TSL_Params;
|
||||
|
||||
CONST TSL_Bank_T *bank;
|
||||
TSL_tIndex_T NumberOfChannelOn = 0;
|
||||
TSL_tNb_T NumberOfChannels = 0;
|
||||
TSL_Status_enum_T TSL_Acq_Status = TSL_STATUS_BUSY;
|
||||
uint16_t GroupToCheck = 0;
|
||||
|
||||
uint32_t TSL_GPIO_Clock_LookUpTable[] = {RCC_AHBPeriph_GPIOA, RCC_AHBPeriph_GPIOB, RCC_AHBPeriph_GPIOC, RCC_AHBPeriph_GPIOD, RCC_AHBPeriph_GPIOE, RCC_AHBPeriph_GPIOF, RCC_AHBPeriph_GPIOG, RCC_AHBPeriph_GPIOH};
|
||||
GPIO_TypeDef *TSL_GPIO_LookUpTable[] = {GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH};
|
||||
|
||||
uint16_t *TSL_RI_HYSCR_LookUpTable[] =
|
||||
{
|
||||
(uint16_t *)&RI->HYSCR1, (uint16_t *)&RI->HYSCR1 + 1,
|
||||
(uint16_t *)&RI->HYSCR2, (uint16_t *)&RI->HYSCR2 + 1,
|
||||
(uint16_t *)&RI->HYSCR3, (uint16_t *)&RI->HYSCR3 + 1,
|
||||
(uint16_t *)&RI->HYSCR4, (uint16_t *)&RI->HYSCR4 + 1
|
||||
};
|
||||
|
||||
CONST TSL_RIConf_t TSL_RI_Conf_LookUpTable[101] =
|
||||
{
|
||||
{0, 0},
|
||||
{0, 1},
|
||||
{0, 2},
|
||||
{0, 3},
|
||||
{0, 0},//padding
|
||||
{0, 0},//padding
|
||||
{0, 6},
|
||||
{0, 7},
|
||||
{1, 9},
|
||||
{1, 10},
|
||||
{1, 11},
|
||||
{1, 15},
|
||||
{0, 0},//padding
|
||||
{1, 6},
|
||||
{1, 7},
|
||||
{1, 8},
|
||||
|
||||
{0, 8},
|
||||
{0, 9},
|
||||
{1, 16},
|
||||
{0, 0},//padding
|
||||
{1, 4},
|
||||
{1, 5},
|
||||
{1, 27},
|
||||
{1, 28},
|
||||
{0, 0},//padding
|
||||
{0, 0},//padding
|
||||
{0, 0},//padding
|
||||
{0, 0},//padding
|
||||
{0, 18},
|
||||
{0, 19},
|
||||
{0, 20},
|
||||
{0, 21},
|
||||
|
||||
{0, 10},
|
||||
{0, 11},
|
||||
{0, 12},
|
||||
{0, 13},
|
||||
{0, 14},
|
||||
{0, 15},
|
||||
{1, 0},
|
||||
{1, 1},
|
||||
{1, 2},
|
||||
{1, 3},
|
||||
{1, 29},
|
||||
{0, 0},//padding
|
||||
{0, 0},//padding
|
||||
{0, 0},//padding
|
||||
{0, 0},//padding
|
||||
{0, 0},//padding
|
||||
|
||||
{0, 0},//padding
|
||||
{0, 0},//padding
|
||||
{0, 0},//padding
|
||||
{0, 0},//padding
|
||||
{0, 0},//padding
|
||||
{0, 0},//padding
|
||||
{0, 0},//padding
|
||||
{0, 0},//padding
|
||||
{0, 0},//padding
|
||||
{0, 0},//padding
|
||||
{0, 0},//padding
|
||||
{0, 0},//padding
|
||||
{0, 0},//padding
|
||||
{0, 0},//padding
|
||||
{0, 0},//padding
|
||||
{0, 0},//padding
|
||||
|
||||
{0, 0},//padding
|
||||
{0, 0},//padding
|
||||
{0, 0},//padding
|
||||
{0, 0},//padding
|
||||
{0, 0},//padding
|
||||
{0, 0},//padding
|
||||
{0, 0},//padding
|
||||
{0, 0},//padding
|
||||
{0, 0},//padding
|
||||
{0, 0},//padding
|
||||
{0, 0},//padding
|
||||
{0, 0},//padding
|
||||
{0, 0},//padding
|
||||
{0, 0},//padding
|
||||
{0, 0},//padding
|
||||
{0, 0},//padding
|
||||
|
||||
{0, 0},//padding
|
||||
{0, 0},//padding
|
||||
{0, 0},//padding
|
||||
{0, 0},//padding
|
||||
{0, 0},//padding
|
||||
{0, 0},//padding
|
||||
{0, 27},
|
||||
{0, 28},
|
||||
{0, 29},
|
||||
{0, 30},
|
||||
{0, 16},
|
||||
{1, 17},
|
||||
{1, 18},
|
||||
{1, 19},
|
||||
{1, 20},
|
||||
{1, 21},
|
||||
|
||||
{1, 22},
|
||||
{1, 23},
|
||||
{1, 24},
|
||||
{1, 25},
|
||||
{1, 26}
|
||||
};
|
||||
|
||||
#if (TSLPRM_USE_GPIOA)
|
||||
uint32_t GPIOA_IDR_Mask = 0;
|
||||
#endif
|
||||
#if (TSLPRM_USE_GPIOB)
|
||||
uint32_t GPIOB_IDR_Mask = 0;
|
||||
#endif
|
||||
#if (TSLPRM_USE_GPIOC)
|
||||
uint32_t GPIOC_IDR_Mask = 0;
|
||||
#endif
|
||||
#if (TSLPRM_USE_GPIOF)
|
||||
uint32_t GPIOF_IDR_Mask = 0;
|
||||
#endif
|
||||
#if (TSLPRM_USE_GPIOG)
|
||||
uint32_t GPIOG_IDR_Mask = 0;
|
||||
#endif
|
||||
|
||||
/* Private functions prototype -----------------------------------------------*/
|
||||
void SoftDelay(uint16_t val);
|
||||
void TSL_BankConf(uint32_t * BankConf, TSL_Conf_t Conf);
|
||||
void TSL_acq_GroupDone(uint16_t EndedGroup);
|
||||
|
||||
/**
|
||||
* @brief Configures the acquisition module.
|
||||
* @param[in] BankConf Pointer to the bank to configure
|
||||
* @param[in] Conf Configuration
|
||||
* @retval None
|
||||
*/
|
||||
void TSL_BankConf(uint32_t *BankConf, TSL_Conf_t Conf)
|
||||
{
|
||||
BankConf[TSL_RI_Conf_LookUpTable[Conf].RI_ASCR] |= (1 << (TSL_RI_Conf_LookUpTable[Conf].RI_ASCR_bit));
|
||||
|
||||
switch (TSL_CHANNEL_PORT(Conf))
|
||||
{
|
||||
case TSL_BANK_GPIOA: BankConf[2] |= (3 << (2 * (TSL_CHANNEL_IO(Conf)))); //MODER input
|
||||
BankConf[3] |= (1 << (2 * (TSL_CHANNEL_IO(Conf)))); //MODER output
|
||||
BankConf[4] |= (1 << (TSL_CHANNEL_IO(Conf))); //ODR
|
||||
break;
|
||||
case TSL_BANK_GPIOB: BankConf[5] |= (3 << (2 * (TSL_CHANNEL_IO(Conf)))); //MODER input
|
||||
BankConf[6] |= (1 << (2 * (TSL_CHANNEL_IO(Conf)))); //MODER output
|
||||
BankConf[7] |= (1 << (TSL_CHANNEL_IO(Conf))); //ODR
|
||||
break;
|
||||
case TSL_BANK_GPIOC: BankConf[8] |= (3 << (2 * (TSL_CHANNEL_IO(Conf)))); //MODER input
|
||||
BankConf[9] |= (1 << (2 * (TSL_CHANNEL_IO(Conf)))); //MODER output
|
||||
BankConf[10] |= (1 << (TSL_CHANNEL_IO(Conf))); //ODR
|
||||
break;
|
||||
case TSL_BANK_GPIOF: BankConf[11] |= (3 << (2 * (TSL_CHANNEL_IO(Conf)))); //MODER input
|
||||
BankConf[12] |= (1 << (2 * (TSL_CHANNEL_IO(Conf)))); //MODER output
|
||||
BankConf[13] |= (1 << (TSL_CHANNEL_IO(Conf))); //ODR
|
||||
break;
|
||||
case TSL_BANK_GPIOG: BankConf[14] |= (3 << (2 * (TSL_CHANNEL_IO(Conf)))); //MODER input
|
||||
BankConf[15] |= (1 << (2 * (TSL_CHANNEL_IO(Conf)))); //MODER output
|
||||
BankConf[16] |= (1 << (TSL_CHANNEL_IO(Conf))); //ODR
|
||||
break;
|
||||
default: break;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Initializes the acquisition module.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
TSL_Status_enum_T TSL_acq_Init(void)
|
||||
{
|
||||
CONST TSL_Bank_T *LocalBank = &(TSL_Globals.Bank_Array[0]);
|
||||
TSL_tNb_T NumberOfBanks = TSLPRM_TOTAL_BANKS;
|
||||
TSL_tNb_T LocalNumberOfChannels = 0;
|
||||
TSL_tIndex_T idx_bk;
|
||||
TSL_tIndex_T idx_ch;
|
||||
CONST TSL_ChannelSrc_T *p_chSrc = LocalBank->p_chSrc; // Pointer to the current channel
|
||||
|
||||
/* Enables the comparator interface clock */
|
||||
RCC->APB1ENR |= RCC_APB1Periph_COMP;
|
||||
|
||||
//====================
|
||||
// GPIOs configuration
|
||||
//====================
|
||||
for (idx_bk = 0; idx_bk < NumberOfBanks; idx_bk++)
|
||||
{
|
||||
LocalBank = &(TSL_Globals.Bank_Array[idx_bk]);
|
||||
p_chSrc = LocalBank->p_chSrc;
|
||||
|
||||
#if (TSLPRM_USE_SHIELD > 0)
|
||||
// Enables GPIOs clock
|
||||
TSL_RCC_AHBENR_Config(LocalBank->shield_sample);
|
||||
|
||||
// Bank shield configuration
|
||||
/* Disables Hysteresis Register */
|
||||
TSL_RI_HYSCR_Config(LocalBank->shield_sample);
|
||||
|
||||
/* Output PP config */
|
||||
TSL_GPIO_OTYPER_PP_Config(p_chSrc->t_sample);
|
||||
TSL_GPIO_OTYPER_PP_Config(p_chSrc->t_channel);
|
||||
/* 400kHz config */
|
||||
TSL_GPIO_OSPEEDR_VL_Config(p_chSrc->t_sample);
|
||||
TSL_GPIO_OSPEEDR_VL_Config(p_chSrc->t_channel);
|
||||
/* No pull up/pull down config */
|
||||
TSL_GPIO_PUPDR_NO_PUPD_Config(LocalBank->shield_sample);
|
||||
TSL_GPIO_PUPDR_NO_PUPD_Config(LocalBank->shield_channel);
|
||||
/* Set ODR */
|
||||
TSL_GPIO_BR_Config(LocalBank->shield_sample);
|
||||
TSL_GPIO_BR_Config(LocalBank->shield_channel);
|
||||
/* Output mode */
|
||||
TSL_GPIO_MODER_OUT_Config(LocalBank->shield_sample);
|
||||
TSL_GPIO_MODER_OUT_Config(LocalBank->shield_channel);
|
||||
#endif
|
||||
|
||||
LocalNumberOfChannels = LocalBank->NbChannels;
|
||||
|
||||
for (idx_ch = 0;
|
||||
idx_ch < LocalNumberOfChannels;
|
||||
idx_ch++)
|
||||
{
|
||||
/* Enables GPIOs clock */
|
||||
TSL_RCC_AHBENR_Config(p_chSrc->t_sample);
|
||||
TSL_RCC_AHBENR_Config(p_chSrc->t_channel);
|
||||
|
||||
// Bank/channel configuration
|
||||
/* Disables Hysteresis Register */
|
||||
TSL_RI_HYSCR_Config(p_chSrc->t_sample);
|
||||
/* Output PP config */
|
||||
TSL_GPIO_OTYPER_PP_Config(p_chSrc->t_sample);
|
||||
TSL_GPIO_OTYPER_PP_Config(p_chSrc->t_channel);
|
||||
/* 400kHz config */
|
||||
TSL_GPIO_OSPEEDR_VL_Config(p_chSrc->t_sample);
|
||||
TSL_GPIO_OSPEEDR_VL_Config(p_chSrc->t_channel);
|
||||
/* No pull up/pull down config */
|
||||
TSL_GPIO_PUPDR_NO_PUPD_Config(p_chSrc->t_sample);
|
||||
TSL_GPIO_PUPDR_NO_PUPD_Config(p_chSrc->t_channel);
|
||||
/* Set ODR */
|
||||
TSL_GPIO_BR_Config(p_chSrc->t_sample);
|
||||
TSL_GPIO_BR_Config(p_chSrc->t_channel);
|
||||
/* Output mode */
|
||||
TSL_GPIO_MODER_OUT_Config(p_chSrc->t_sample);
|
||||
TSL_GPIO_MODER_OUT_Config(p_chSrc->t_channel);
|
||||
|
||||
p_chSrc++;
|
||||
}
|
||||
}
|
||||
|
||||
/* Enable RI Switch */
|
||||
RI->ASCR1 &= (uint32_t)(~0x80000000); // ADC analog switches open !!!
|
||||
|
||||
return TSL_STATUS_OK;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Configures a Bank.
|
||||
* @param[in] idx_bk Index of the Bank to configure
|
||||
* @retval Status
|
||||
*/
|
||||
TSL_Status_enum_T TSL_acq_BankConfig(TSL_tIndex_T idx_bk)
|
||||
{
|
||||
TSL_tIndex_T index;
|
||||
TSL_tIndex_T idx_dest;
|
||||
TSL_tIndex_T idx_ch;
|
||||
CONST TSL_ChannelDest_T *p_chDest; // Pointer to the current channel
|
||||
CONST TSL_ChannelSrc_T *p_chSrc; // Pointer to the current channel
|
||||
|
||||
// Check parameters (if USE_FULL_ASSERT is defined)
|
||||
assert_param(IS_BANK_INDEX_OK(idx_bk));
|
||||
|
||||
bank = &(TSL_Globals.Bank_Array[idx_bk]);
|
||||
|
||||
for (index = 0;index < SIZEOFBANKCONF;index++)
|
||||
{
|
||||
TSL_BankSampleConf[index] = 0x00000000;
|
||||
TSL_BankChannelConf[index] = 0x00000000;
|
||||
}
|
||||
|
||||
NumberOfChannels = bank->NbChannels;
|
||||
NumberOfChannelOn = 0;
|
||||
GroupToCheck = 0;//init group to check
|
||||
|
||||
p_chDest = bank->p_chDest;
|
||||
p_chSrc = bank->p_chSrc;
|
||||
for (idx_ch = 0; idx_ch < NumberOfChannels; idx_ch++)
|
||||
{
|
||||
// Get index in the result array associated to the current channel
|
||||
idx_dest = p_chDest->IdxDest;
|
||||
|
||||
if (bank->p_chData[idx_dest].Flags.ObjStatus != TSL_OBJ_STATUS_OFF)
|
||||
{
|
||||
TSL_BankConf(TSL_BankSampleConf, p_chSrc->t_sample);
|
||||
TSL_BankConf(TSL_BankChannelConf, p_chSrc->t_channel);
|
||||
GroupToCheck |= (1 << (p_chSrc->IdxSrc));
|
||||
NumberOfChannelOn++;
|
||||
}
|
||||
|
||||
p_chSrc++;
|
||||
p_chDest++;
|
||||
}
|
||||
|
||||
#if (TSLPRM_USE_GPIOA)
|
||||
GPIOA_IDR_Mask = TSL_BankSampleConf[4];
|
||||
#endif
|
||||
|
||||
#if (TSLPRM_USE_GPIOB)
|
||||
GPIOB_IDR_Mask = TSL_BankSampleConf[7];
|
||||
#endif
|
||||
|
||||
#if (TSLPRM_USE_GPIOC)
|
||||
GPIOC_IDR_Mask = TSL_BankSampleConf[10];
|
||||
#endif
|
||||
|
||||
#if (TSLPRM_USE_GPIOF)
|
||||
GPIOF_IDR_Mask = TSL_BankSampleConf[13];
|
||||
#endif
|
||||
|
||||
#if (TSLPRM_USE_GPIOG)
|
||||
GPIOG_IDR_Mask = TSL_BankSampleConf[16];
|
||||
#endif
|
||||
|
||||
|
||||
#if (TSLPRM_USE_SHIELD > 0)
|
||||
if (NumberOfChannelOn != 0)
|
||||
{
|
||||
TSL_BankConf(TSL_BankSampleConf, bank->shield_sample);
|
||||
TSL_BankConf(TSL_BankChannelConf, bank->shield_channel);
|
||||
}
|
||||
#endif
|
||||
|
||||
return TSL_STATUS_OK;
|
||||
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Check which group is not over
|
||||
* @param[in] EndedGroup
|
||||
* @retval None
|
||||
*/
|
||||
void TSL_acq_GroupDone(uint16_t EndedGroup)
|
||||
{
|
||||
uint16_t i;
|
||||
|
||||
for (i = 0;i < 11;i++)
|
||||
{
|
||||
if ((EndedGroup & (1 << i)) != (1 << i))
|
||||
{
|
||||
tab_MeasurementCounter[i] = TSL_Params.AcqMax + 1;
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Start acquisition on a previously configured bank
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void TSL_acq_BankStartAcq(void)
|
||||
{
|
||||
CONST TSL_Bank_T *LocalBank = &(TSL_Globals.Bank_Array[0]);
|
||||
TSL_tNb_T NumberOfBanks = TSLPRM_TOTAL_BANKS;
|
||||
TSL_tNb_T LocalNumberOfChannels = 0;
|
||||
TSL_tIndex_T BankIndex;
|
||||
|
||||
uint16_t MeasurementCounter = 0;
|
||||
CONST TSL_ChannelSrc_T *p_chSrc;
|
||||
TSL_tIndex_T idx_ch;
|
||||
uint16_t GroupToCheckMask = 0;
|
||||
uint32_t GPIO_IDR_Mask = 0;
|
||||
uint8_t Check_Input = 0;
|
||||
|
||||
#if (TSLPRM_USE_GPIOA)
|
||||
uint16_t TSL_GPIOA_IDR = 0;
|
||||
#endif
|
||||
#if (TSLPRM_USE_GPIOB)
|
||||
uint16_t TSL_GPIOB_IDR = 0;
|
||||
#endif
|
||||
#if (TSLPRM_USE_GPIOC)
|
||||
uint16_t TSL_GPIOC_IDR = 0;
|
||||
#endif
|
||||
#if (TSLPRM_USE_GPIOF)
|
||||
uint16_t TSL_GPIOF_IDR = 0;
|
||||
#endif
|
||||
#if (TSLPRM_USE_GPIOG)
|
||||
uint16_t TSL_GPIOG_IDR = 0;
|
||||
#endif
|
||||
uint16_t GPIO_IDR = 0;
|
||||
|
||||
#if (TSLPRM_PROTECT_IO_ACCESS > 0)
|
||||
__disable_irq();
|
||||
#endif
|
||||
#if (TSLPRM_IODEF > 0)
|
||||
//============================
|
||||
// All GPIOs in Input floating
|
||||
//============================
|
||||
for (BankIndex = 0; BankIndex < NumberOfBanks; BankIndex++)
|
||||
{
|
||||
LocalBank = &(TSL_Globals.Bank_Array[BankIndex]);
|
||||
p_chSrc = LocalBank->p_chSrc;
|
||||
|
||||
#if (TSLPRM_USE_SHIELD > 0)
|
||||
TSL_GPIO_MODER_IN_Config(LocalBank->shield_sample);
|
||||
TSL_GPIO_MODER_IN_Config(LocalBank->shield_channel);
|
||||
#endif
|
||||
|
||||
LocalNumberOfChannels = LocalBank->NbChannels;
|
||||
|
||||
for (idx_ch = 0;
|
||||
idx_ch < LocalNumberOfChannels;
|
||||
idx_ch++)
|
||||
{
|
||||
TSL_GPIO_MODER_IN_Config(p_chSrc->t_sample);
|
||||
TSL_GPIO_MODER_IN_Config(p_chSrc->t_channel);
|
||||
|
||||
p_chSrc++;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
#if (TSLPRM_PROTECT_IO_ACCESS > 0)
|
||||
__enable_irq();
|
||||
#endif
|
||||
|
||||
/* Open the analog switches */
|
||||
RI->ASCR1 &= (uint32_t)(~(TSL_BankSampleConf[0] | TSL_BankChannelConf[0]));
|
||||
RI->ASCR2 &= (uint32_t)(~(TSL_BankSampleConf[1] | TSL_BankChannelConf[1]));
|
||||
|
||||
/* All IO to pushpull LOW for discharging all capacitors (Ctouch and Csense) */
|
||||
#if (TSLPRM_PROTECT_IO_ACCESS > 0)
|
||||
__disable_irq();
|
||||
#endif
|
||||
/* Discharging sampling capacitor and CTouch */
|
||||
#if (TSLPRM_USE_GPIOA)
|
||||
GPIOA->ODR &= (uint32_t)(~(TSL_BankSampleConf[4] | TSL_BankChannelConf[4]));
|
||||
GPIOA->MODER = (GPIOA->MODER & (uint32_t)(~(TSL_BankSampleConf[2] | TSL_BankChannelConf[2]))) | (TSL_BankSampleConf[3] | TSL_BankChannelConf[3]);
|
||||
#endif
|
||||
#if (TSLPRM_USE_GPIOB)
|
||||
GPIOB->ODR &= (uint32_t)(~(TSL_BankSampleConf[7] | TSL_BankChannelConf[7]));
|
||||
GPIOB->MODER = (GPIOB->MODER & (uint32_t)(~(TSL_BankSampleConf[5] | TSL_BankChannelConf[5]))) | (TSL_BankSampleConf[6] | TSL_BankChannelConf[6]);
|
||||
#endif
|
||||
#if (TSLPRM_USE_GPIOC)
|
||||
GPIOC->ODR &= (uint32_t)(~(TSL_BankSampleConf[10] | TSL_BankChannelConf[10]));
|
||||
GPIOC->MODER = (GPIOC->MODER & (uint32_t)(~(TSL_BankSampleConf[8] | TSL_BankChannelConf[8]))) | (TSL_BankSampleConf[9] | TSL_BankChannelConf[9]);
|
||||
#endif
|
||||
#if (TSLPRM_USE_GPIOF)
|
||||
GPIOF->ODR &= (uint32_t)(~(TSL_BankSampleConf[13] | TSL_BankChannelConf[13]));
|
||||
GPIOF->MODER = (GPIOF->MODER & (uint32_t)(~(TSL_BankSampleConf[11] | TSL_BankChannelConf[11]))) | (TSL_BankSampleConf[12] | TSL_BankChannelConf[12]);
|
||||
#endif
|
||||
#if (TSLPRM_USE_GPIOG)
|
||||
GPIOG->ODR &= (uint32_t)(~(TSL_BankSampleConf[16] | TSL_BankChannelConf[16]));
|
||||
GPIOG->MODER = (GPIOG->MODER & (uint32_t)(~(TSL_BankSampleConf[14] | TSL_BankChannelConf[14]))) | (TSL_BankSampleConf[15] | TSL_BankChannelConf[15]);
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
#if (TSLPRM_PROTECT_IO_ACCESS > 0)
|
||||
__enable_irq();
|
||||
#endif
|
||||
|
||||
/* Wait a while for a good discharging of all capacitors */
|
||||
SoftDelay(50); // ~14µs with fHCLK = 32MHz
|
||||
//this time depends of the size of the sampling capacitor
|
||||
|
||||
#if (TSLPRM_PROTECT_IO_ACCESS > 0)
|
||||
__disable_irq();
|
||||
#endif
|
||||
/* All IO in input floating */
|
||||
#if (TSLPRM_USE_GPIOA)
|
||||
GPIOA->MODER &= (uint32_t)(~(TSL_BankSampleConf[2] | TSL_BankChannelConf[2]));
|
||||
#endif
|
||||
#if (TSLPRM_USE_GPIOB)
|
||||
GPIOB->MODER &= (uint32_t)(~(TSL_BankSampleConf[5] | TSL_BankChannelConf[5]));
|
||||
#endif
|
||||
#if (TSLPRM_USE_GPIOC)
|
||||
GPIOC->MODER &= (uint32_t)(~(TSL_BankSampleConf[8] | TSL_BankChannelConf[8]));
|
||||
#endif
|
||||
#if (TSLPRM_USE_GPIOF)
|
||||
GPIOF->MODER &= (uint32_t)(~(TSL_BankSampleConf[11] | TSL_BankChannelConf[11]));
|
||||
#endif
|
||||
#if (TSLPRM_USE_GPIOG)
|
||||
GPIOG->MODER &= (uint32_t)(~(TSL_BankSampleConf[14] | TSL_BankChannelConf[14]));
|
||||
#endif
|
||||
|
||||
/* set the IO to Vdd (io in push-pull HIGH when in output mode) */
|
||||
#if (TSLPRM_USE_GPIOA)
|
||||
GPIOA->ODR |= (TSL_BankSampleConf[4] | TSL_BankChannelConf[4]); /* HIGH level */
|
||||
#endif
|
||||
#if (TSLPRM_USE_GPIOB)
|
||||
GPIOB->ODR |= (TSL_BankSampleConf[7] | TSL_BankChannelConf[7]); /* HIGH level */
|
||||
#endif
|
||||
#if (TSLPRM_USE_GPIOC)
|
||||
GPIOC->ODR |= (TSL_BankSampleConf[10] | TSL_BankChannelConf[10]); /* HIGH level */
|
||||
#endif
|
||||
#if (TSLPRM_USE_GPIOF)
|
||||
GPIOF->ODR |= (TSL_BankSampleConf[13] | TSL_BankChannelConf[13]); /* HIGH level */
|
||||
#endif
|
||||
#if (TSLPRM_USE_GPIOG)
|
||||
GPIOG->ODR |= (TSL_BankSampleConf[16] | TSL_BankChannelConf[16]); /* HIGH level */
|
||||
#endif
|
||||
|
||||
#if (TSLPRM_PROTECT_IO_ACCESS > 0)
|
||||
__enable_irq();
|
||||
#endif
|
||||
|
||||
/* Close the sampling capacitor analog switch */
|
||||
RI->ASCR1 |= (TSL_BankSampleConf[0]);
|
||||
RI->ASCR2 |= (TSL_BankSampleConf[1]);
|
||||
|
||||
|
||||
/* Loop while all the 1st channel of each group have not reach the VIH level */
|
||||
do
|
||||
{
|
||||
|
||||
#if (TSLPRM_PROTECT_IO_ACCESS > 0)
|
||||
__disable_irq();
|
||||
#endif
|
||||
/* Charging Ctouch by connecting the IO to Vdd (io in push-pull HIGH) */
|
||||
#if (TSLPRM_USE_GPIOA)
|
||||
GPIOA->MODER |= (TSL_BankChannelConf[3]); /* Output push pull config */
|
||||
#endif
|
||||
#if (TSLPRM_USE_GPIOB)
|
||||
GPIOB->MODER |= (TSL_BankChannelConf[6]); /* Output push pull config */
|
||||
#endif
|
||||
#if (TSLPRM_USE_GPIOC)
|
||||
GPIOC->MODER |= (TSL_BankChannelConf[9]); /* Output push pull config */
|
||||
#endif
|
||||
#if (TSLPRM_USE_GPIOF)
|
||||
GPIOF->MODER |= (TSL_BankChannelConf[12]); /* Output push pull config */
|
||||
#endif
|
||||
#if (TSLPRM_USE_GPIOG)
|
||||
GPIOG->MODER |= (TSL_BankChannelConf[15]); /* Output push pull config */
|
||||
#endif
|
||||
#if (TSLPRM_PROTECT_IO_ACCESS > 0)
|
||||
__enable_irq();
|
||||
#endif
|
||||
|
||||
/* Wait a while for a good charging (programmable delay) */
|
||||
SoftDelay(1);
|
||||
|
||||
/* test GPIOx->IDR bit + group configuration for each channel */
|
||||
|
||||
#if (TSLPRM_USE_GPIOA)
|
||||
TSL_GPIOA_IDR = GPIOA->IDR;
|
||||
if ((TSL_GPIOA_IDR & GPIOA_IDR_Mask) != 0)
|
||||
{
|
||||
Check_Input = 1;
|
||||
GPIOA_IDR_Mask &= (uint32_t)(~TSL_GPIOA_IDR);
|
||||
}
|
||||
#endif
|
||||
|
||||
#if (TSLPRM_USE_GPIOB)
|
||||
TSL_GPIOB_IDR = GPIOB->IDR;
|
||||
if ((TSL_GPIOB_IDR & GPIOB_IDR_Mask) != 0)
|
||||
{
|
||||
Check_Input = (1 << 1);
|
||||
GPIOB_IDR_Mask &= (uint32_t)(~TSL_GPIOB_IDR);
|
||||
}
|
||||
#endif
|
||||
|
||||
#if (TSLPRM_USE_GPIOC)
|
||||
TSL_GPIOC_IDR = GPIOC->IDR;
|
||||
if ((TSL_GPIOC_IDR & GPIOC_IDR_Mask) != 0)
|
||||
{
|
||||
Check_Input = (1 << 2);
|
||||
GPIOC_IDR_Mask &= (uint32_t)(~TSL_GPIOC_IDR);
|
||||
}
|
||||
#endif
|
||||
|
||||
#if (TSLPRM_USE_GPIOF)
|
||||
TSL_GPIOF_IDR = GPIOF->IDR;
|
||||
if ((TSL_GPIOF_IDR & GPIOF_IDR_Mask) != 0)
|
||||
{
|
||||
Check_Input = (1 << 5);
|
||||
GPIOF_IDR_Mask &= (uint32_t)(~TSL_GPIOF_IDR);
|
||||
}
|
||||
#endif
|
||||
|
||||
#if (TSLPRM_USE_GPIOG)
|
||||
TSL_GPIOG_IDR = GPIOG->IDR;
|
||||
if ((TSL_GPIOG_IDR & GPIOG_IDR_Mask) != 0)
|
||||
{
|
||||
Check_Input = (1 << 6);
|
||||
GPIOG_IDR_Mask &= (uint32_t)(~TSL_GPIOG_IDR);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
if (Check_Input)
|
||||
{
|
||||
p_chSrc = bank->p_chSrc;
|
||||
for (idx_ch = 0; idx_ch < NumberOfChannels; idx_ch++)
|
||||
{
|
||||
GroupToCheckMask = (1 << (p_chSrc->IdxSrc));
|
||||
if ((GroupToCheck & GroupToCheckMask) == (GroupToCheckMask))
|
||||
{
|
||||
GPIO_IDR_Mask = (1 << TSL_CHANNEL_IO(p_chSrc->t_sample));
|
||||
|
||||
switch (TSL_CHANNEL_PORT(p_chSrc->t_sample))
|
||||
{
|
||||
#if (TSLPRM_USE_GPIOA)
|
||||
case 0: GPIO_IDR = TSL_GPIOA_IDR; break;
|
||||
#endif
|
||||
#if (TSLPRM_USE_GPIOB)
|
||||
case 1: GPIO_IDR = TSL_GPIOB_IDR; break;
|
||||
#endif
|
||||
#if (TSLPRM_USE_GPIOC)
|
||||
case 2: GPIO_IDR = TSL_GPIOC_IDR; break;
|
||||
#endif
|
||||
#if (TSLPRM_USE_GPIOF)
|
||||
case 5: GPIO_IDR = TSL_GPIOF_IDR; break;
|
||||
#endif
|
||||
#if (TSLPRM_USE_GPIOG)
|
||||
case 6: GPIO_IDR = TSL_GPIOG_IDR; break;
|
||||
#endif
|
||||
default: break;
|
||||
}
|
||||
|
||||
if ((GPIO_IDR & GPIO_IDR_Mask) == GPIO_IDR_Mask)
|
||||
{
|
||||
tab_MeasurementCounter[p_chSrc->IdxSrc] = MeasurementCounter;
|
||||
GroupToCheck &= (uint32_t)(~(1 << (p_chSrc->IdxSrc)));
|
||||
Check_Input &= (uint32_t)(~(1 << TSL_CHANNEL_PORT(p_chSrc->t_sample)));
|
||||
}
|
||||
}
|
||||
p_chSrc++;
|
||||
}
|
||||
}
|
||||
|
||||
MeasurementCounter++;
|
||||
|
||||
#if (TSLPRM_PROTECT_IO_ACCESS > 0)
|
||||
__disable_irq();
|
||||
#endif
|
||||
/* Configure All channels in input floating */
|
||||
#if (TSLPRM_USE_GPIOA)
|
||||
GPIOA->MODER &= (uint32_t)(~(TSL_BankChannelConf[2]));
|
||||
#endif
|
||||
#if (TSLPRM_USE_GPIOB)
|
||||
GPIOB->MODER &= (uint32_t)(~(TSL_BankChannelConf[5]));
|
||||
#endif
|
||||
#if (TSLPRM_USE_GPIOC)
|
||||
GPIOC->MODER &= (uint32_t)(~(TSL_BankChannelConf[8]));
|
||||
#endif
|
||||
#if (TSLPRM_USE_GPIOF)
|
||||
GPIOF->MODER &= (uint32_t)(~(TSL_BankChannelConf[11]));
|
||||
#endif
|
||||
#if (TSLPRM_USE_GPIOG)
|
||||
GPIOG->MODER &= (uint32_t)(~(TSL_BankChannelConf[14]));
|
||||
#endif
|
||||
|
||||
#if (TSLPRM_PROTECT_IO_ACCESS > 0)
|
||||
__enable_irq();
|
||||
#endif
|
||||
|
||||
/* Charging the Csense cap with connecting it to Ctouch by closing the analog switch */
|
||||
RI->ASCR1 |= (TSL_BankChannelConf[0]);
|
||||
RI->ASCR2 |= (TSL_BankChannelConf[1]);
|
||||
|
||||
/* Wait a while for a good charge transfering (programmable delay) */
|
||||
SoftDelay(1);
|
||||
|
||||
RI->ASCR1 &= (uint32_t)(~(TSL_BankChannelConf[0]));
|
||||
RI->ASCR2 &= (uint32_t)(~(TSL_BankChannelConf[1]));
|
||||
|
||||
/*it's better to implement this like that because it's much more faster than to put this test in the "while test" below */
|
||||
if (MeasurementCounter > TSL_Params.AcqMax)
|
||||
{
|
||||
TSL_acq_GroupDone(GroupToCheck);
|
||||
__NOP();
|
||||
break;
|
||||
}
|
||||
|
||||
}
|
||||
while (GroupToCheck != 0);
|
||||
|
||||
|
||||
#if (TSLPRM_PROTECT_IO_ACCESS > 0)
|
||||
__disable_irq();
|
||||
#endif
|
||||
//====================
|
||||
// All GPIOs in PP Low
|
||||
//====================
|
||||
for (BankIndex = 0; BankIndex < NumberOfBanks; BankIndex++)
|
||||
{
|
||||
LocalBank = &(TSL_Globals.Bank_Array[BankIndex]);
|
||||
p_chSrc = LocalBank->p_chSrc;
|
||||
|
||||
#if (TSLPRM_USE_SHIELD > 0)
|
||||
TSL_GPIO_BR_Config(LocalBank->shield_sample);
|
||||
TSL_GPIO_BR_Config(LocalBank->shield_channel);
|
||||
TSL_GPIO_MODER_OUT_Config(LocalBank->shield_sample);
|
||||
TSL_GPIO_MODER_OUT_Config(LocalBank->shield_channel);
|
||||
#endif
|
||||
|
||||
LocalNumberOfChannels = LocalBank->NbChannels;
|
||||
|
||||
for (idx_ch = 0;
|
||||
idx_ch < LocalNumberOfChannels;
|
||||
idx_ch++)
|
||||
{
|
||||
TSL_GPIO_BR_Config(p_chSrc->t_sample);
|
||||
TSL_GPIO_BR_Config(p_chSrc->t_channel);
|
||||
TSL_GPIO_MODER_OUT_Config(p_chSrc->t_sample);
|
||||
TSL_GPIO_MODER_OUT_Config(p_chSrc->t_channel);
|
||||
|
||||
p_chSrc++;
|
||||
}
|
||||
}
|
||||
#if (TSLPRM_PROTECT_IO_ACCESS > 0)
|
||||
__enable_irq();
|
||||
#endif
|
||||
|
||||
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Wait end of acquisition
|
||||
* @param None
|
||||
* @retval status
|
||||
*/
|
||||
TSL_Status_enum_T TSL_acq_BankWaitEOC(void)
|
||||
{
|
||||
TSL_Status_enum_T retval = TSL_STATUS_BUSY;
|
||||
retval = TSL_STATUS_OK;
|
||||
return retval;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Return the current measure
|
||||
* @param[in] index Index of the measure source
|
||||
* @retval Measure
|
||||
*/
|
||||
TSL_tMeas_T TSL_acq_GetMeas(TSL_tIndex_T index)
|
||||
{
|
||||
return(tab_MeasurementCounter[index]);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Check noise (not used)
|
||||
* @param None
|
||||
* @retval Status
|
||||
*/
|
||||
TSL_AcqStatus_enum_T TSL_acq_CheckNoise(void)
|
||||
{
|
||||
return TSL_ACQ_STATUS_OK;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Process the TS Interrupt routine
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void TSL_acq_ProcessIT(void)
|
||||
{
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if a filter must be used on the current channel (not used)
|
||||
* @param[in] pCh Pointer on the channel data information
|
||||
* @retval Result TRUE if a filter can be applied
|
||||
*/
|
||||
TSL_Bool_enum_T TSL_acq_UseFilter(TSL_ChannelData_T *pCh)
|
||||
{
|
||||
return TSL_TRUE;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Compute the Delta value
|
||||
* @param[in] ref Reference value
|
||||
* @param[in] meas Last Measurement value
|
||||
* @retval Delta value
|
||||
*/
|
||||
TSL_tDelta_T TSL_acq_ComputeDelta(TSL_tRef_T ref, TSL_tMeas_T meas)
|
||||
{
|
||||
return((TSL_tDelta_T)(ref - meas));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Compute the Measurement value
|
||||
* @param[in] ref Reference value
|
||||
* @param[in] delta Delta value
|
||||
* @retval Measurement value
|
||||
*/
|
||||
TSL_tMeas_T TSL_acq_ComputeMeas(TSL_tRef_T ref, TSL_tDelta_T delta)
|
||||
{
|
||||
return((TSL_tMeas_T)(ref - delta));
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Test if the Reference is incorrect (not used)
|
||||
* @param[in] pCh Pointer on the channel data information
|
||||
* @retval Result TRUE if the Reference is out of range
|
||||
*/
|
||||
TSL_Bool_enum_T TSL_acq_TestReferenceOutOfRange(TSL_ChannelData_T *pCh)
|
||||
{
|
||||
return TSL_FALSE;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Test if the measure has crossed the reference target (not used)
|
||||
* @param[in] pCh Pointer on the channel data information
|
||||
* @param[in] new_meas Measure of the last acquisition on this channel
|
||||
* @retval Result TRUE if the Reference is valid
|
||||
*/
|
||||
TSL_Bool_enum_T TSL_acq_TestFirstReferenceIsValid(TSL_ChannelData_T *pCh, TSL_tMeas_T new_meas)
|
||||
{
|
||||
return TSL_TRUE;
|
||||
}
|
||||
|
||||
|
||||
#if defined(__IAR_SYSTEMS_ICC__) // IAR/EWARM
|
||||
#pragma optimize=medium
|
||||
#elif defined(__CC_ARM) // Keil/MDK-ARM
|
||||
#pragma O1
|
||||
#pragma Ospace
|
||||
#elif defined(__TASKING__) // Altium/Tasking
|
||||
#pragma optimize O0
|
||||
#elif defined(__GNUC__) // Atollic/True Studio + Raisonance/RKit
|
||||
#pragma GCC push_options
|
||||
#pragma GCC optimize ("O0")
|
||||
#endif
|
||||
/**
|
||||
* @brief Software delay (private routine)
|
||||
* @param val Wait delay
|
||||
* With fHCLK = 32MHz: 1 = ~1µs, 50 = ~14µs, 100 = ~25µs, 200 = ~50µs
|
||||
* @retval None
|
||||
*/
|
||||
void SoftDelay(uint16_t val)
|
||||
{
|
||||
__IO uint16_t i;
|
||||
for (i = val; i > 0; i--)
|
||||
{}
|
||||
}
|
||||
#if defined(__TASKING__)
|
||||
#pragma endoptimize
|
||||
#endif
|
||||
|
||||
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
|
||||
Some files were not shown because too many files have changed in this diff Show more
Loading…
Reference in a new issue