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https://github.com/FreeRTOS/FreeRTOS-Kernel.git
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Latest TriCore port files - these still contain some debug code, and are not yet fully documented.
This commit is contained in:
Richard Barry
parent
93c4c48f78
commit
b89f1a729a
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@ -75,11 +75,11 @@
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/*-----------------------------------------------------------*/
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/* System register Definitions. */
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#define portSYSTEM_PROGRAM_STATUS_WORD ( (unsigned portBASE_TYPE) 0x000008FF ) /* Supervisor Mode, MPU Register Set 0 and Call Depth Counting disabled. */
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#define portINITIAL_PRIVILEGED_PROGRAM_STATUS_WORD ( (unsigned portBASE_TYPE) 0x000014FF ) /* IO Level 1, MPU Register Set 1 and Call Depth Counting disabled. */
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#define portINITIAL_UNPRIVILEGED_PROGRAM_STATUS_WORD ( (unsigned portBASE_TYPE) 0x000010FF ) /* IO Level 0, MPU Register Set 1 and Call Depth Counting disabled. */
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#define portINITIAL_PCXI_UPPER_CONTEXT_WORD ( (unsigned portBASE_TYPE) 0x00C00000 ) /* The lower 20 bits identify the CSA address. */
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#define portINITIAL_SYSCON ( (unsigned portBASE_TYPE) 0x00000000 ) /* MPU Disable. */
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#define portSYSTEM_PROGRAM_STATUS_WORD ( 0x000008FFUL ) /* Supervisor Mode, MPU Register Set 0 and Call Depth Counting disabled. */
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#define portINITIAL_PRIVILEGED_PROGRAM_STATUS_WORD ( 0x000014FFUL ) /* IO Level 1, MPU Register Set 1 and Call Depth Counting disabled. */
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#define portINITIAL_UNPRIVILEGED_PROGRAM_STATUS_WORD ( 0x000010FFUL ) /* IO Level 0, MPU Register Set 1 and Call Depth Counting disabled. */
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#define portINITIAL_PCXI_UPPER_CONTEXT_WORD ( 0x00C00000UL ) /* The lower 20 bits identify the CSA address. */
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#define portINITIAL_SYSCON ( 0x00000000UL ) /* MPU Disable. */
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/* CSA manipulation macros. */
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#define portCSA_FCX_MASK ( 0x000FFFFFUL )
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@ -90,6 +90,9 @@
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/* Each CSA contains 16 words of data. */
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#define portNUM_WORDS_IN_CSA ( 16 )
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/* The interrupt enable bit in the PCP_SRC register. */
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#define portENABLE_CPU_INTERRUPT ( 1U << 12U )
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/*-----------------------------------------------------------*/
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/*
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@ -101,7 +104,13 @@ static void prvSetupTimerInterrupt( void );
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/*
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* Trap handler for yields.
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*/
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static void prvPortYield( int iTrapIdentification );
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static void prvTrapYield( int iTrapIdentification );
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/*
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* Priority 1 interrupt handler for yields pended from an interrupt.
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*/
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static void prvInterruptYield( int iTrapIdentification );
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/*-----------------------------------------------------------*/
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/* This reference is required by the save/restore context macros. */
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@ -153,10 +162,11 @@ unsigned long *pulLowerCSA = NULL;
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if( ( NULL != pulLowerCSA ) && ( NULL != pulUpperCSA ) )
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{
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/* Remove the two consumed CSAs from the free CSA list. */
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_disable();
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_dsync();
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_mtcr( $FCX, pulUpperCSA[ 0 ] );
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/* ISync to commit the change to the FCX. */
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_isync();
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_enable();
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}
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else
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{
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@ -167,14 +177,14 @@ unsigned long *pulLowerCSA = NULL;
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portEXIT_CRITICAL();
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/* Clear the upper CSA. */
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memset( pulUpperCSA, 0, portNUM_WORDS_IN_CSA * sizeof( unsigned portBASE_TYPE ) );
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memset( pulUpperCSA, 0, portNUM_WORDS_IN_CSA * sizeof( unsigned long ) );
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/* Upper Context. */
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pulUpperCSA[ 2 ] = ( unsigned long )pxTopOfStack; /* A10; Stack Return aka Stack Pointer */
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pulUpperCSA[ 1 ] = portSYSTEM_PROGRAM_STATUS_WORD; /* PSW */
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/* Clear the lower CSA. */
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memset( pulLowerCSA, 0, portNUM_WORDS_IN_CSA * sizeof( unsigned portBASE_TYPE ) );
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memset( pulLowerCSA, 0, portNUM_WORDS_IN_CSA * sizeof( unsigned long ) );
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/* Lower Context. */
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pulLowerCSA[ 8 ] = ( unsigned long ) pvParameters; /* A4; Address Type Parameter Register */
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@ -193,29 +203,43 @@ unsigned long *pulLowerCSA = NULL;
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}
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/*-----------------------------------------------------------*/
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portBASE_TYPE xPortStartScheduler( void )
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long xPortStartScheduler( void )
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{
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extern void vTrapInstallHandlers( void );
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unsigned long ulMFCR = 0UL;
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unsigned long *pulUpperCSA = NULL;
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unsigned long *pulLowerCSA = NULL;
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/* Interrupts at or below configMAX_SYSCALL_INTERRUPT_PRIORITY are disable
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when this function is called. */
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/* Set-up the timer interrupt. */
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prvSetupTimerInterrupt();
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/* Install the Trap Handlers. */
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vTrapInstallHandlers();
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/* Install the Syscall Handler. */
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if( 0 == _install_trap_handler( portSYSCALL_TRAP, prvPortYield ) )
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/* Install the Syscall Handler for yield calls. */
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if( 0 == _install_trap_handler( portSYSCALL_TRAP, prvTrapYield ) )
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{
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/* Failed to install the yield handler, force an assert. */
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configASSERT( ( ( volatile void * ) NULL ) );
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}
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/* Enable then install the priority 1 interrupt for pending context
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switches from an ISR. See mod_SRC in the TriCore manual. */
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CPU_SRC0.reg = ( portENABLE_CPU_INTERRUPT ) | ( configKERNEL_YIELD_PRIORITY );
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if( 0 == _install_int_handler( configKERNEL_YIELD_PRIORITY, prvInterruptYield, 0 ) )
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{
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/* Failed to install the yield handler, force an assert. */
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configASSERT( ( ( volatile void * ) NULL ) );
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}
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_disable();
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/* Load the initial SYSCON. */
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_dsync();
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_mtcr( $SYSCON, portINITIAL_SYSCON );
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_isync();
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/* ENDINIT has already been applied in the 'cstart.c' code. */
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@ -223,14 +247,16 @@ unsigned long *pulLowerCSA = NULL;
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exception because this code is not genuinely in an exception. */
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ulMFCR = _mfcr( $PSW );
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ulMFCR &= portRESTORE_PSW_MASK;
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_dsync();
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_mtcr( $PSW, ulMFCR );
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_isync();
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/* Finally, perform the equivalent of a portRESTORE_CONTEXT() */
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pulLowerCSA = portCSA_TO_ADDRESS( ( *pxCurrentTCB ) );
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pulUpperCSA = portCSA_TO_ADDRESS( pulLowerCSA[0] );
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_mtcr( $PCXI, *pxCurrentTCB );
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_dsync();
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_mtcr( $PCXI, *pxCurrentTCB );
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_isync();
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_nop();
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_rslcx();
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_nop();
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@ -285,6 +311,11 @@ static void prvSetupTimerInterrupt( void )
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static void prvSystemTickHandler( int iArg )
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{
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unsigned long ulSavedInterruptMask;
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unsigned long *pxUpperCSA = NULL;
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unsigned long xUpperCSA = 0UL;
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extern volatile unsigned long *pxCurrentTCB;
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COUNT_NEST();
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/* Just to avoid compiler warnings about unused parameters. */
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( void ) iArg;
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@ -321,8 +352,36 @@ unsigned long ulSavedInterruptMask;
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#if configUSE_PREEMPTION == 1
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{
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portYIELD_FROM_ISR( pdTRUE );
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/* Save the context of a task.
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The upper context is automatically saved when entering a trap or interrupt.
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Need to save the lower context as well and copy the PCXI CSA ID into
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pxCurrentTCB->pxTopOfStack. Only Lower Context CSA IDs may be saved to the
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TCB of a task.
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Call vTaskSwitchContext to select the next task, note that this changes the
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value of pxCurrentTCB so that it needs to be reloaded.
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Call vPortSetMPURegisterSetOne to change the MPU mapping for the task
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that has just been switched in.
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Load the context of the task.
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Need to restore the lower context by loading the CSA from
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pxCurrentTCB->pxTopOfStack into PCXI (effectively changing the call stack).
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In the Interrupt handler post-amble, RSLCX will restore the lower context
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of the task. RFE will restore the upper context of the task, jump to the
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return address and restore the previous state of interrupts being
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enabled/disabled. */
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_disable();
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_dsync();
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xUpperCSA = _mfcr( $PCXI );
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pxUpperCSA = portCSA_TO_ADDRESS( xUpperCSA );
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*pxCurrentTCB = pxUpperCSA[ 0 ];
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vTaskSwitchContext();
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pxUpperCSA[ 0 ] = *pxCurrentTCB;
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CPU_SRC0.bits.SETR = 0;
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_isync();
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}
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ulNest--;
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#endif
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}
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/*-----------------------------------------------------------*/
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@ -345,10 +404,10 @@ unsigned long ulSavedInterruptMask;
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* than they can be freed assuming that tasks are being spawned and
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* deleted frequently.
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*/
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void vPortReclaimCSA( unsigned portBASE_TYPE *pxTCB )
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void vPortReclaimCSA( unsigned long *pxTCB )
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{
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unsigned portBASE_TYPE pxHeadCSA, pxTailCSA, pxFreeCSA;
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unsigned portBASE_TYPE *pulNextCSA;
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unsigned long pxHeadCSA, pxTailCSA, pxFreeCSA;
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unsigned long *pulNextCSA;
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/* A pointer to the first CSA in the list of CSAs consumed by the task is
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stored in the first element of the tasks TCB structure (where the stack
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@ -382,7 +441,7 @@ unsigned portBASE_TYPE *pulNextCSA;
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pulNextCSA = portCSA_TO_ADDRESS( pxTailCSA );
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}
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taskENTER_CRITICAL();
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_disable();
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{
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/* Look up the current free CSA head. */
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_dsync();
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@ -394,11 +453,9 @@ unsigned portBASE_TYPE *pulNextCSA;
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/* Move the head of the reclaimed into the Free. */
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_dsync();
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_mtcr( $FCX, pxHeadCSA );
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/* ISync to commit the change to the FCX. */
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_isync();
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}
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taskEXIT_CRITICAL();
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_enable();
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}
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/*-----------------------------------------------------------*/
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@ -408,13 +465,43 @@ void vPortEndScheduler( void )
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}
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/*-----------------------------------------------------------*/
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static void prvPortYield( int iTrapIdentification )
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static void prvTrapYield( int iTrapIdentification )
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{
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unsigned long *pxUpperCSA = NULL;
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unsigned long xUpperCSA = 0UL;
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extern volatile unsigned long *pxCurrentTCB;
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switch( iTrapIdentification )
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{
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case portSYSCALL_TASK_YIELD:
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/* Select another task to run. */
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portYIELD_FROM_ISR( pdTRUE );
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/* Save the context of a task.
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The upper context is automatically saved when entering a trap or interrupt.
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Need to save the lower context as well and copy the PCXI CSA ID into
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pxCurrentTCB->pxTopOfStack. Only Lower Context CSA IDs may be saved to the
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TCB of a task.
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Call vTaskSwitchContext to select the next task, note that this changes the
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value of pxCurrentTCB so that it needs to be reloaded.
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Call vPortSetMPURegisterSetOne to change the MPU mapping for the task
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that has just been switched in.
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Load the context of the task.
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Need to restore the lower context by loading the CSA from
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pxCurrentTCB->pxTopOfStack into PCXI (effectively changing the call stack).
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In the Interrupt handler post-amble, RSLCX will restore the lower context
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of the task. RFE will restore the upper context of the task, jump to the
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return address and restore the previous state of interrupts being
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enabled/disabled. */
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_disable();
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_dsync();
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xUpperCSA = _mfcr( $PCXI );
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pxUpperCSA = portCSA_TO_ADDRESS( xUpperCSA );
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*pxCurrentTCB = pxUpperCSA[ 0 ];
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vTaskSwitchContext();
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pxUpperCSA[ 0 ] = *pxCurrentTCB;
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CPU_SRC0.bits.SETR = 0;
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_isync();
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break;
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default:
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@ -425,20 +512,60 @@ static void prvPortYield( int iTrapIdentification )
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}
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/*-----------------------------------------------------------*/
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unsigned portBASE_TYPE uxPortSetInterruptMaskFromISR( void )
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static void prvInterruptYield( int iId )
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{
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unsigned portBASE_TYPE uxReturn = 0UL;
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unsigned long *pxUpperCSA = NULL;
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unsigned long xUpperCSA = 0UL;
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extern volatile unsigned long *pxCurrentTCB;
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COUNT_NEST();
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/* Just to remove compiler warnings. */
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( void ) iId;
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/* Save the context of a task.
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The upper context is automatically saved when entering a trap or interrupt.
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Need to save the lower context as well and copy the PCXI CSA ID into
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pxCurrentTCB->pxTopOfStack. Only Lower Context CSA IDs may be saved to the
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TCB of a task.
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Call vTaskSwitchContext to select the next task, note that this changes the
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value of pxCurrentTCB so that it needs to be reloaded.
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Call vPortSetMPURegisterSetOne to change the MPU mapping for the task
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that has just been switched in.
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Load the context of the task.
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Need to restore the lower context by loading the CSA from
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pxCurrentTCB->pxTopOfStack into PCXI (effectively changing the call stack).
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In the Interrupt handler post-amble, RSLCX will restore the lower context
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of the task. RFE will restore the upper context of the task, jump to the
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return address and restore the previous state of interrupts being
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enabled/disabled. */
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_disable();
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_dsync();
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xUpperCSA = _mfcr( $PCXI );
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pxUpperCSA = portCSA_TO_ADDRESS( xUpperCSA );
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*pxCurrentTCB = pxUpperCSA[ 0 ];
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vTaskSwitchContext();
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pxUpperCSA[ 0 ] = *pxCurrentTCB;
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CPU_SRC0.bits.SETR = 0;
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_isync();
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ulNest--;
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}
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/*-----------------------------------------------------------*/
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unsigned long uxPortSetInterruptMaskFromISR( void )
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{
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unsigned long uxReturn = 0UL;
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_disable();
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uxReturn = _mfcr( $ICR );
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_mtcr( $ICR, ( ( uxReturn & ~portCCPN_MASK ) | configMAX_SYSCALL_INTERRUPT_PRIORITY ) );
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_isync();
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_enable();
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/* Return just the interrupt mask bits. */
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return ( uxReturn & portCCPN_MASK );
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}
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/*-----------------------------------------------------------*/
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void vPortClearInterruptMaskFromISR( unsigned portBASE_TYPE uxSavedStatusValue )
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{
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_mtcr( $ICR, ( uxSavedStatusValue & portCCPN_MASK ) );
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}
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/*-----------------------------------------------------------*/
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@ -114,16 +114,12 @@ extern void vTaskExitCritical( void );
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#define portEXIT_CRITICAL() vTaskExitCritical()
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/*---------------------------------------------------------------------------*/
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/* Task utilities. */
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extern void vPortReclaimCSA( unsigned portBASE_TYPE *pxTCB );
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/* CSA Manipulation. */
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#define portCSA_TO_ADDRESS( pCSA ) ( ( unsigned portBASE_TYPE * )( ( ( ( pCSA ) & 0x000F0000 ) << 12 ) | ( ( ( pCSA ) & 0x0000FFFF ) << 6 ) ) )
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#define portADDRESS_TO_CSA( pAddress ) ( ( unsigned portBASE_TYPE )( ( ( ( (unsigned portBASE_TYPE)( pAddress ) ) & 0xF0000000 ) >> 12 ) | ( ( (unsigned portBASE_TYPE)( pAddress ) & 0x003FFFC0 ) >> 6 ) ) )
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#define portCSA_TO_ADDRESS( pCSA ) ( ( unsigned long * )( ( ( ( pCSA ) & 0x000F0000 ) << 12 ) | ( ( ( pCSA ) & 0x0000FFFF ) << 6 ) ) )
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#define portADDRESS_TO_CSA( pAddress ) ( ( unsigned long )( ( ( ( (unsigned long)( pAddress ) ) & 0xF0000000 ) >> 12 ) | ( ( ( unsigned long )( pAddress ) & 0x003FFFC0 ) >> 6 ) ) )
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/*---------------------------------------------------------------------------*/
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#define portYIELD() _syscall(0)
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#define portYIELD() _syscall( 0 )
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/* Port Restore is implicit in the platform when the function is returned from the original PSW is automatically replaced. */
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#define portSYSCALL_TASK_YIELD 0
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#define portSYSCALL_RAISE_PRIORITY 1
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@ -131,68 +127,53 @@ extern void vPortReclaimCSA( unsigned portBASE_TYPE *pxTCB );
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/* Critical section management. */
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/* Clear the ICR.IE bit. */
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#define portDISABLE_INTERRUPTS() _mtcr( $ICR, ( ( _mfcr( $ICR ) & ~portCCPN_MASK ) | configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
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/* Set ICR.CCPN to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
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#define portDISABLE_INTERRUPTS() { \
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unsigned long ulICR; \
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_disable(); \
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ulICR = _mfcr( $ICR ); /* Get current ICR value. */ \
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ulICR &= ~portCCPN_MASK; /* Clear down mask bits. */ \
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ulICR |= configMAX_SYSCALL_INTERRUPT_PRIORITY; /* Set mask bits to required priority mask. */ \
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_mtcr( $ICR, ulICR ); /* Write back updated ICR. */ \
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_isync(); \
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_enable(); \
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}
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/* Set the ICR.IE bit. */
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#define portENABLE_INTERRUPTS() { unsigned long ulCurrentICR = _mfcr( $ICR ); _mtcr( $ICR, ( ulCurrentICR & ~portCCPN_MASK ) ) }
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/* Clear ICR.CCPN to allow all interrupt priorities. */
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#define portENABLE_INTERRUPTS() { \
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unsigned long ulICR; \
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_disable(); \
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ulICR = _mfcr( $ICR ); /* Get current ICR value. */ \
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ulICR &= ~portCCPN_MASK; /* Clear down mask bits. */ \
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_mtcr( $ICR, ulICR ); /* Write back updated ICR. */ \
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_isync(); \
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_enable(); \
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}
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/* Set ICR.CCPN to uxSavedMaskValue. */
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#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedMaskValue ) { \
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unsigned long ulICR; \
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_disable(); \
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ulICR = _mfcr( $ICR ); /* Get current ICR value. */ \
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ulICR &= ~portCCPN_MASK; /* Clear down mask bits. */ \
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ulICR |= uxSavedMaskValue; /* Set mask bits to previously saved mask value. */ \
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_mtcr( $ICR, ulICR ); /* Write back updated ICR. */ \
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_isync(); \
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_enable(); \
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}
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extern unsigned portBASE_TYPE uxPortSetInterruptMaskFromISR( void );
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extern void vPortClearInterruptMaskFromISR( unsigned portBASE_TYPE uxSavedStatusValue );
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/* Set ICR.CCPN to configMAX_SYSCALL_INTERRUPT_PRIORITY */
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extern unsigned long uxPortSetInterruptMaskFromISR( void );
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#define portSET_INTERRUPT_MASK_FROM_ISR() uxPortSetInterruptMaskFromISR()
|
||||
|
||||
/* Set ICR.CCPN to uxSavedInterruptStatus */
|
||||
#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusValue ) vPortClearInterruptMaskFromISR( uxSavedStatusValue )
|
||||
|
||||
/* As this port holds a CSA address in pxTopOfStack, the assert that checks the
|
||||
pxTopOfStack alignment is removed. */
|
||||
#define portALIGNMENT_ASSERT_pxCurrentTCB ( void )
|
||||
|
||||
/*---------------------------------------------------------------------------*/
|
||||
/* Pend a priority 1 interrupt, which will take care of the context switch. */
|
||||
#define portYIELD_FROM_ISR( xHigherPriorityTaskWoken ) if( xHigherPriorityTaskWoken != pdFALSE ) { CPU_SRC0.bits.SETR = 1; _isync(); }
|
||||
|
||||
/*
|
||||
* Save the context of a task.
|
||||
* The upper context is automatically saved when entering a trap or interrupt.
|
||||
* Need to save the lower context as well and copy the PCXI CSA ID into
|
||||
* pxCurrentTCB->pxTopOfStack. Only Lower Context CSA IDs may be saved to the
|
||||
* TCB of a task.
|
||||
*
|
||||
* Call vTaskSwitchContext to select the next task, note that this changes the
|
||||
* value of pxCurrentTCB so that it needs to be reloaded.
|
||||
*
|
||||
* Call vPortSetMPURegisterSetOne to change the MPU mapping for the task
|
||||
* that has just been switched in.
|
||||
*
|
||||
* Load the context of the task.
|
||||
* Need to restore the lower context by loading the CSA from
|
||||
* pxCurrentTCB->pxTopOfStack into PCXI (effectively changing the call stack).
|
||||
* In the Interrupt handler post-amble, RSLCX will restore the lower context
|
||||
* of the task. RFE will restore the upper context of the task, jump to the
|
||||
* return address and restore the previous state of interrupts being
|
||||
* enabled/disabled.
|
||||
*/
|
||||
#define portYIELD_FROM_ISR( xHigherPriorityTaskWoken ) \
|
||||
{ \
|
||||
unsigned portBASE_TYPE *pxUpperCSA = NULL; \
|
||||
unsigned portBASE_TYPE xUpperCSA = 0UL; \
|
||||
extern volatile unsigned long *pxCurrentTCB; \
|
||||
if ( pdTRUE == xHigherPriorityTaskWoken ) \
|
||||
{ \
|
||||
_disable(); \
|
||||
_isync(); \
|
||||
xUpperCSA = _mfcr( $PCXI ); \
|
||||
pxUpperCSA = portCSA_TO_ADDRESS( xUpperCSA ); \
|
||||
*pxCurrentTCB = pxUpperCSA[0]; \
|
||||
vTaskSwitchContext(); \
|
||||
pxUpperCSA[0] = *pxCurrentTCB; \
|
||||
_dsync(); \
|
||||
_isync(); \
|
||||
_nop(); \
|
||||
_nop(); \
|
||||
} \
|
||||
}
|
||||
/*---------------------------------------------------------------------------*/
|
||||
|
||||
/* Task function macros as described on the FreeRTOS.org WEB site. */
|
||||
|
|
@ -204,8 +185,8 @@ extern volatile unsigned long *pxCurrentTCB; \
|
|||
* Port specific clean up macro required to free the CSAs that were consumed by
|
||||
* a task that has since been deleted.
|
||||
*/
|
||||
void vPortReclaimCSA( unsigned portBASE_TYPE *pxTCB );
|
||||
#define portCLEAN_UP_TCB( pxTCB ) vPortReclaimCSA( ( unsigned portBASE_TYPE *) ( pxTCB ) )
|
||||
void vPortReclaimCSA( unsigned long *pxTCB );
|
||||
#define portCLEAN_UP_TCB( pxTCB ) vPortReclaimCSA( ( unsigned long * ) ( pxTCB ) )
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in a new issue