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First version under SVN is V4.0.1

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Richard Barry 2006-05-02 09:39:15 +00:00
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Demo/ARM7_AT91FR40008_GCC/AT91R40008.h Normal file
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// ----------------------------------------------------------------------------
// ATMEL Microcontroller Software Support - ROUSSET -
// ----------------------------------------------------------------------------
// The software is delivered "AS IS" without warranty or condition of any
// kind, either express, implied or statutory. This includes without
// limitation any warranty or condition with respect to merchantability or
// fitness for any particular purpose, or against the infringements of
// intellectual property rights of others.
// ----------------------------------------------------------------------------
// File Name : AT91R40008.h
// Object : AT91R40008 definitions
// Generated : AT91 SW Application Group 02/19/2003 (11:13:31)
//
// CVS Reference : /AT91R40008.pl/1.3/Tue Nov 12 16:01:52 2002//
// CVS Reference : /AIC_1246F.pl/1.4/Mon Nov 04 17:51:00 2002//
// CVS Reference : /WD_1241B.pl/1.1/Mon Nov 04 17:51:00 2002//
// CVS Reference : /PS_x40.pl/1.2/Tue Nov 12 16:01:52 2002//
// CVS Reference : /PIO_1321C.pl/1.5/Tue Oct 29 15:50:24 2002//
// CVS Reference : /TC_1243B.pl/1.4/Tue Nov 05 12:43:10 2002//
// CVS Reference : /PDC_1363D.pl/1.3/Wed Oct 23 14:49:48 2002//
// CVS Reference : /US_1242E.pl/1.5/Thu Nov 21 13:37:56 2002//
// CVS Reference : /SF_x40.pl/1.1/Tue Nov 12 13:27:20 2002//
// CVS Reference : /EBI_x40.pl/1.5/Wed Feb 19 09:25:22 2003//
// ----------------------------------------------------------------------------
#ifndef AT91R40008_H
#define AT91R40008_H
/* AT91 Register type */
typedef volatile unsigned int AT91_REG; // Hardware register definition
typedef volatile unsigned int at91_reg;
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Advanced Interrupt Controller
// *****************************************************************************
typedef struct _AT91S_AIC {
AT91_REG AIC_SMR[32]; // Source Mode egister
AT91_REG AIC_SVR[32]; // Source Vector egister
AT91_REG AIC_IVR; // IRQ Vector Register
AT91_REG AIC_FVR; // FIQ Vector Register
AT91_REG AIC_ISR; // Interrupt Status Register
AT91_REG AIC_IPR; // Interrupt Pending Register
AT91_REG AIC_IMR; // Interrupt Mask Register
AT91_REG AIC_CISR; // Core Interrupt Status Register
AT91_REG Reserved0[2]; //
AT91_REG AIC_IECR; // Interrupt Enable Command Register
AT91_REG AIC_IDCR; // Interrupt Disable Command egister
AT91_REG AIC_ICCR; // Interrupt Clear Command Register
AT91_REG AIC_ISCR; // Interrupt Set Command Register
AT91_REG AIC_EOICR; // End of Interrupt Command Register
AT91_REG AIC_SPU; // Spurious Vector Register
} AT91S_AIC, *AT91PS_AIC;
// -------- AIC_SMR : (AIC Offset: 0x0) Control Register --------
#define AT91C_AIC_PRIOR ((unsigned int) 0x7 << 0) // (AIC) Priority Level
#define AT91C_AIC_PRIOR_LOWEST ((unsigned int) 0x0) // (AIC) Lowest priority level
#define AT91C_AIC_PRIOR_HIGHEST ((unsigned int) 0x7) // (AIC) Highest priority level
#define AT91C_AIC_SRCTYPE ((unsigned int) 0x3 << 5) // (AIC) Interrupt Source Type
#define AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE ((unsigned int) 0x0 << 5) // (AIC) Internal Sources Code Label Level Sensitive
#define AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED ((unsigned int) 0x1 << 5) // (AIC) Internal Sources Code Label Edge triggered
#define AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL ((unsigned int) 0x2 << 5) // (AIC) External Sources Code Label High-level Sensitive
#define AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE ((unsigned int) 0x3 << 5) // (AIC) External Sources Code Label Positive Edge triggered
// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register --------
#define AT91C_AIC_NFIQ ((unsigned int) 0x1 << 0) // (AIC) NFIQ Status
#define AT91C_AIC_NIRQ ((unsigned int) 0x1 << 1) // (AIC) NIRQ Status
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Watchdog Timer Interface
// *****************************************************************************
typedef struct _AT91S_WD {
AT91_REG WD_OMR; // Overflow Mode Register
AT91_REG WD_CMR; // Clock Mode Register
AT91_REG WD_CR; // Control Register
AT91_REG WD_SR; // Status Register
} AT91S_WD, *AT91PS_WD;
// -------- WD_OMR : (WD Offset: 0x0) Overflow Mode Register --------
#define AT91C_WD_WDEN ((unsigned int) 0x1 << 0) // (WD) Watchdog Enable
#define AT91C_WD_RSTEN ((unsigned int) 0x1 << 1) // (WD) Reset Enable
#define AT91C_WD_IRQEN ((unsigned int) 0x1 << 2) // (WD) Interrupt Enable
#define AT91C_WD_EXTEN ((unsigned int) 0x1 << 3) // (WD) External Signal Enable
#define AT91C_WD_OKEY ((unsigned int) 0xFFF << 4) // (WD) Watchdog Enable
// -------- WD_CMR : (WD Offset: 0x4) Clock Mode Register --------
#define AT91C_WD_WDCLKS ((unsigned int) 0x3 << 0) // (WD) Clock Selection
#define AT91C_WD_WDCLKS_MCK32 ((unsigned int) 0x0) // (WD) Master Clock divided by 32
#define AT91C_WD_WDCLKS_MCK128 ((unsigned int) 0x1) // (WD) Master Clock divided by 128
#define AT91C_WD_WDCLKS_MCK1024 ((unsigned int) 0x2) // (WD) Master Clock divided by 1024
#define AT91C_WD_WDCLKS_MCK4096 ((unsigned int) 0x3) // (WD) Master Clock divided by 4096
#define AT91C_WD_HPCV ((unsigned int) 0xF << 2) // (WD) High Pre-load Counter Value
#define AT91C_WD_CKEY ((unsigned int) 0x1FF << 7) // (WD) Clock Access Key
// -------- WD_CR : (WD Offset: 0x8) Control Register --------
#define AT91C_WD_RSTKEY ((unsigned int) 0xFFFF << 0) // (WD) Restart Key
// -------- WD_SR : (WD Offset: 0xc) Status Register --------
#define AT91C_WD_WDOVF ((unsigned int) 0x1 << 0) // (WD) Watchdog Overflow
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Power Saving Controler
// *****************************************************************************
typedef struct _AT91S_PS {
AT91_REG PS_CR; // Control Register
AT91_REG PS_PCER; // Peripheral Clock Enable Register
AT91_REG PS_PCDR; // Peripheral Clock Disable Register
AT91_REG PS_PCSR; // Peripheral Clock Status Register
} AT91S_PS, *AT91PS_PS;
// -------- PS_PCER : (PS Offset: 0x4) Peripheral Clock Enable Register --------
#define AT91C_PS_US0 ((unsigned int) 0x1 << 2) // (PS) Usart 0 Clock
#define AT91C_PS_US1 ((unsigned int) 0x1 << 3) // (PS) Usart 1 Clock
#define AT91C_PS_TC0 ((unsigned int) 0x1 << 4) // (PS) Timer Counter 0 Clock
#define AT91C_PS_TC1 ((unsigned int) 0x1 << 5) // (PS) Timer Counter 1 Clock
#define AT91C_PS_TC2 ((unsigned int) 0x1 << 6) // (PS) Timer Counter 2 Clock
#define AT91C_PS_PIO ((unsigned int) 0x1 << 8) // (PS) PIO Clock
// -------- PS_PCDR : (PS Offset: 0x8) Peripheral Clock Disable Register --------
// -------- PS_PCSR : (PS Offset: 0xc) Peripheral Clock Satus Register --------
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Parallel Input Output Controler
// *****************************************************************************
typedef struct _AT91S_PIO {
AT91_REG PIO_PER; // PIO Enable Register
AT91_REG PIO_PDR; // PIO Disable Register
AT91_REG PIO_PSR; // PIO Status Register
AT91_REG Reserved0[1]; //
AT91_REG PIO_OER; // Output Enable Register
AT91_REG PIO_ODR; // Output Disable Registerr
AT91_REG PIO_OSR; // Output Status Register
AT91_REG Reserved1[1]; //
AT91_REG PIO_IFER; // Input Filter Enable Register
AT91_REG PIO_IFDR; // Input Filter Disable Register
AT91_REG PIO_IFSR; // Input Filter Status Register
AT91_REG Reserved2[1]; //
AT91_REG PIO_SODR; // Set Output Data Register
AT91_REG PIO_CODR; // Clear Output Data Register
AT91_REG PIO_ODSR; // Output Data Status Register
AT91_REG PIO_PDSR; // Pin Data Status Register
AT91_REG PIO_IER; // Interrupt Enable Register
AT91_REG PIO_IDR; // Interrupt Disable Register
AT91_REG PIO_IMR; // Interrupt Mask Register
AT91_REG PIO_ISR; // Interrupt Status Register
AT91_REG PIO_MDER; // Multi-driver Enable Register
AT91_REG PIO_MDDR; // Multi-driver Disable Register
AT91_REG PIO_MDSR; // Multi-driver Status Register
} AT91S_PIO, *AT91PS_PIO;
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Timer Counter Channel Interface
// *****************************************************************************
typedef struct _AT91S_TC {
AT91_REG TC_CCR; // Channel Control Register
AT91_REG TC_CMR; // Channel Mode Register
AT91_REG Reserved0[2]; //
AT91_REG TC_CV; // Counter Value
AT91_REG TC_RA; // Register A
AT91_REG TC_RB; // Register B
AT91_REG TC_RC; // Register C
AT91_REG TC_SR; // Status Register
AT91_REG TC_IER; // Interrupt Enable Register
AT91_REG TC_IDR; // Interrupt Disable Register
AT91_REG TC_IMR; // Interrupt Mask Register
} AT91S_TC, *AT91PS_TC;
// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register --------
#define AT91C_TC_CLKEN ((unsigned int) 0x1 << 0) // (TC) Counter Clock Enable Command
#define AT91C_TC_CLKDIS ((unsigned int) 0x1 << 1) // (TC) Counter Clock Disable Command
#define AT91C_TC_SWTRG ((unsigned int) 0x1 << 2) // (TC) Software Trigger Command
// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode --------
#define AT91C_TC_CPCSTOP ((unsigned int) 0x1 << 6) // (TC) Counter Clock Stopped with RC Compare
#define AT91C_TC_CPCDIS ((unsigned int) 0x1 << 7) // (TC) Counter Clock Disable with RC Compare
#define AT91C_TC_EEVTEDG ((unsigned int) 0x3 << 8) // (TC) External Event Edge Selection
#define AT91C_TC_EEVTEDG_NONE ((unsigned int) 0x0 << 8) // (TC) Edge: None
#define AT91C_TC_EEVTEDG_RISING ((unsigned int) 0x1 << 8) // (TC) Edge: rising edge
#define AT91C_TC_EEVTEDG_FALLING ((unsigned int) 0x2 << 8) // (TC) Edge: falling edge
#define AT91C_TC_EEVTEDG_BOTH ((unsigned int) 0x3 << 8) // (TC) Edge: each edge
#define AT91C_TC_EEVT ((unsigned int) 0x3 << 10) // (TC) External Event Selection
#define AT91C_TC_EEVT_NONE ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
#define AT91C_TC_EEVT_RISING ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
#define AT91C_TC_EEVT_FALLING ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
#define AT91C_TC_EEVT_BOTH ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
#define AT91C_TC_ENETRG ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable
#define AT91C_TC_WAVESEL ((unsigned int) 0x3 << 13) // (TC) Waveform Selection
#define AT91C_TC_WAVESEL_UP ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare
#define AT91C_TC_WAVESEL_UP_AUTO ((unsigned int) 0x1 << 13) // (TC) UP mode with automatic trigger on RC Compare
#define AT91C_TC_WAVESEL_UPDOWN ((unsigned int) 0x2 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare
#define AT91C_TC_WAVESEL_UPDOWN_AUTO ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare
#define AT91C_TC_CPCTRG ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable
#define AT91C_TC_WAVE ((unsigned int) 0x1 << 15) // (TC)
#define AT91C_TC_ACPA ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA
#define AT91C_TC_ACPA_NONE ((unsigned int) 0x0 << 16) // (TC) Effect: none
#define AT91C_TC_ACPA_SET ((unsigned int) 0x1 << 16) // (TC) Effect: set
#define AT91C_TC_ACPA_CLEAR ((unsigned int) 0x2 << 16) // (TC) Effect: clear
#define AT91C_TC_ACPA_TOGGLE ((unsigned int) 0x3 << 16) // (TC) Effect: toggle
#define AT91C_TC_ACPC ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA
#define AT91C_TC_ACPC_NONE ((unsigned int) 0x0 << 18) // (TC) Effect: none
#define AT91C_TC_ACPC_SET ((unsigned int) 0x1 << 18) // (TC) Effect: set
#define AT91C_TC_ACPC_CLEAR ((unsigned int) 0x2 << 18) // (TC) Effect: clear
#define AT91C_TC_ACPC_TOGGLE ((unsigned int) 0x3 << 18) // (TC) Effect: toggle
#define AT91C_TC_AEEVT ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA
#define AT91C_TC_AEEVT_NONE ((unsigned int) 0x0 << 20) // (TC) Effect: none
#define AT91C_TC_AEEVT_SET ((unsigned int) 0x1 << 20) // (TC) Effect: set
#define AT91C_TC_AEEVT_CLEAR ((unsigned int) 0x2 << 20) // (TC) Effect: clear
#define AT91C_TC_AEEVT_TOGGLE ((unsigned int) 0x3 << 20) // (TC) Effect: toggle
#define AT91C_TC_ASWTRG ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA
#define AT91C_TC_ASWTRG_NONE ((unsigned int) 0x0 << 22) // (TC) Effect: none
#define AT91C_TC_ASWTRG_SET ((unsigned int) 0x1 << 22) // (TC) Effect: set
#define AT91C_TC_ASWTRG_CLEAR ((unsigned int) 0x2 << 22) // (TC) Effect: clear
#define AT91C_TC_ASWTRG_TOGGLE ((unsigned int) 0x3 << 22) // (TC) Effect: toggle
#define AT91C_TC_BCPB ((unsigned int) 0x3 << 24) // (TC) RB Compare Effect on TIOB
#define AT91C_TC_BCPB_NONE ((unsigned int) 0x0 << 24) // (TC) Effect: none
#define AT91C_TC_BCPB_SET ((unsigned int) 0x1 << 24) // (TC) Effect: set
#define AT91C_TC_BCPB_CLEAR ((unsigned int) 0x2 << 24) // (TC) Effect: clear
#define AT91C_TC_BCPB_TOGGLE ((unsigned int) 0x3 << 24) // (TC) Effect: toggle
#define AT91C_TC_BCPC ((unsigned int) 0x3 << 26) // (TC) RC Compare Effect on TIOB
#define AT91C_TC_BCPC_NONE ((unsigned int) 0x0 << 26) // (TC) Effect: none
#define AT91C_TC_BCPC_SET ((unsigned int) 0x1 << 26) // (TC) Effect: set
#define AT91C_TC_BCPC_CLEAR ((unsigned int) 0x2 << 26) // (TC) Effect: clear
#define AT91C_TC_BCPC_TOGGLE ((unsigned int) 0x3 << 26) // (TC) Effect: toggle
#define AT91C_TC_BEEVT ((unsigned int) 0x3 << 28) // (TC) External Event Effect on TIOB
#define AT91C_TC_BEEVT_NONE ((unsigned int) 0x0 << 28) // (TC) Effect: none
#define AT91C_TC_BEEVT_SET ((unsigned int) 0x1 << 28) // (TC) Effect: set
#define AT91C_TC_BEEVT_CLEAR ((unsigned int) 0x2 << 28) // (TC) Effect: clear
#define AT91C_TC_BEEVT_TOGGLE ((unsigned int) 0x3 << 28) // (TC) Effect: toggle
#define AT91C_TC_BSWTRG ((unsigned int) 0x3 << 30) // (TC) Software Trigger Effect on TIOB
#define AT91C_TC_BSWTRG_NONE ((unsigned int) 0x0 << 30) // (TC) Effect: none
#define AT91C_TC_BSWTRG_SET ((unsigned int) 0x1 << 30) // (TC) Effect: set
#define AT91C_TC_BSWTRG_CLEAR ((unsigned int) 0x2 << 30) // (TC) Effect: clear
#define AT91C_TC_BSWTRG_TOGGLE ((unsigned int) 0x3 << 30) // (TC) Effect: toggle
// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register --------
#define AT91C_TC_COVFS ((unsigned int) 0x1 << 0) // (TC) Counter Overflow
#define AT91C_TC_LOVRS ((unsigned int) 0x1 << 1) // (TC) Load Overrun
#define AT91C_TC_CPAS ((unsigned int) 0x1 << 2) // (TC) RA Compare
#define AT91C_TC_CPBS ((unsigned int) 0x1 << 3) // (TC) RB Compare
#define AT91C_TC_CPCS ((unsigned int) 0x1 << 4) // (TC) RC Compare
#define AT91C_TC_LDRAS ((unsigned int) 0x1 << 5) // (TC) RA Loading
#define AT91C_TC_LDRBS ((unsigned int) 0x1 << 6) // (TC) RB Loading
#define AT91C_TC_ETRCS ((unsigned int) 0x1 << 7) // (TC) External Trigger
#define AT91C_TC_ETRGS ((unsigned int) 0x1 << 16) // (TC) Clock Enabling
#define AT91C_TC_MTIOA ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror
#define AT91C_TC_MTIOB ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror
// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register --------
// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register --------
// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register --------
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Timer Counter Interface
// *****************************************************************************
typedef struct _AT91S_TCB {
AT91S_TC TCB_TC0; // TC Channel 0
AT91_REG Reserved0[4]; //
AT91S_TC TCB_TC1; // TC Channel 1
AT91_REG Reserved1[4]; //
AT91S_TC TCB_TC2; // TC Channel 2
AT91_REG Reserved2[4]; //
AT91_REG TCB_BCR; // TC Block Control Register
AT91_REG TCB_BMR; // TC Block Mode Register
} AT91S_TCB, *AT91PS_TCB;
// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register --------
#define AT91C_TCB_SYNC ((unsigned int) 0x1 << 0) // (TCB) Synchro Command
// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register --------
#define AT91C_TCB_TC0XC0S ((unsigned int) 0x1 << 0) // (TCB) External Clock Signal 0 Selection
#define AT91C_TCB_TC0XC0S_TCLK0 ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0
#define AT91C_TCB_TC0XC0S_NONE ((unsigned int) 0x1) // (TCB) None signal connected to XC0
#define AT91C_TCB_TC0XC0S_TIOA1 ((unsigned int) 0x2) // (TCB) TIOA1 connected to XC0
#define AT91C_TCB_TC0XC0S_TIOA2 ((unsigned int) 0x3) // (TCB) TIOA2 connected to XC0
#define AT91C_TCB_TC1XC1S ((unsigned int) 0x1 << 2) // (TCB) External Clock Signal 1 Selection
#define AT91C_TCB_TC1XC1S_TCLK1 ((unsigned int) 0x0 << 2) // (TCB) TCLK1 connected to XC1
#define AT91C_TCB_TC1XC1S_NONE ((unsigned int) 0x1 << 2) // (TCB) None signal connected to XC1
#define AT91C_TCB_TC1XC1S_TIOA0 ((unsigned int) 0x2 << 2) // (TCB) TIOA0 connected to XC1
#define AT91C_TCB_TC1XC1S_TIOA2 ((unsigned int) 0x3 << 2) // (TCB) TIOA2 connected to XC1
#define AT91C_TCB_TC2XC2S ((unsigned int) 0x1 << 4) // (TCB) External Clock Signal 2 Selection
#define AT91C_TCB_TC2XC2S_TCLK2 ((unsigned int) 0x0 << 4) // (TCB) TCLK2 connected to XC2
#define AT91C_TCB_TC2XC2S_NONE ((unsigned int) 0x1 << 4) // (TCB) None signal connected to XC2
#define AT91C_TCB_TC2XC2S_TIOA0 ((unsigned int) 0x2 << 4) // (TCB) TIOA0 connected to XC2
#define AT91C_TCB_TC2XC2S_TIOA2 ((unsigned int) 0x3 << 4) // (TCB) TIOA2 connected to XC2
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Peripheral Data Controller
// *****************************************************************************
typedef struct _AT91S_PDC {
AT91_REG PDC_RPR; // Receive Pointer Register
AT91_REG PDC_RCR; // Receive Counter Register
AT91_REG PDC_TPR; // Transmit Pointer Register
AT91_REG PDC_TCR; // Transmit Counter Register
} AT91S_PDC, *AT91PS_PDC;
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Usart
// *****************************************************************************
typedef struct _AT91S_USART {
AT91_REG US_CR; // Control Register
AT91_REG US_MR; // Mode Register
AT91_REG US_IER; // Interrupt Enable Register
AT91_REG US_IDR; // Interrupt Disable Register
AT91_REG US_IMR; // Interrupt Mask Register
AT91_REG US_CSR; // Channel Status Register
AT91_REG US_RHR; // Receiver Holding Register
AT91_REG US_THR; // Transmitter Holding Register
AT91_REG US_BRGR; // Baud Rate Generator Register
AT91_REG US_RTOR; // Receiver Time-out Register
AT91_REG US_TTGR; // Transmitter Time-guard Register
AT91_REG Reserved0[1]; //
AT91_REG US_RPR; // Receive Pointer Register
AT91_REG US_RCR; // Receive Counter Register
AT91_REG US_TPR; // Transmit Pointer Register
AT91_REG US_TCR; // Transmit Counter Register
} AT91S_USART, *AT91PS_USART;
// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register --------
#define AT91C_US_RSTRX ((unsigned int) 0x1 << 2) // (USART) Reset Receiver
#define AT91C_US_RSTTX ((unsigned int) 0x1 << 3) // (USART) Reset Transmitter
#define AT91C_US_RXEN ((unsigned int) 0x1 << 4) // (USART) Receiver Enable
#define AT91C_US_RXDIS ((unsigned int) 0x1 << 5) // (USART) Receiver Disable
#define AT91C_US_TXEN ((unsigned int) 0x1 << 6) // (USART) Transmitter Enable
#define AT91C_US_TXDIS ((unsigned int) 0x1 << 7) // (USART) Transmitter Disable
#define AT91C_US_RSTSTA ((unsigned int) 0x1 << 8) // (USART) Reset Status Bits
#define AT91C_US_STTBRK ((unsigned int) 0x1 << 9) // (USART) Start Break
#define AT91C_US_STPBRK ((unsigned int) 0x1 << 10) // (USART) Stop Break
#define AT91C_US_STTTO ((unsigned int) 0x1 << 11) // (USART) Start Time-out
#define AT91C_US_SENDA ((unsigned int) 0x1 << 12) // (USART) Send Address
// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register --------
#define AT91C_US_CLKS ((unsigned int) 0x3 << 4) // (USART) Clock Selection (Baud Rate generator Input Clock
#define AT91C_US_CLKS_CLOCK ((unsigned int) 0x0 << 4) // (USART) Clock
#define AT91C_US_CLKS_FDIV1 ((unsigned int) 0x1 << 4) // (USART) fdiv1
#define AT91C_US_CLKS_SLOW ((unsigned int) 0x2 << 4) // (USART) slow_clock (ARM)
#define AT91C_US_CLKS_EXT ((unsigned int) 0x3 << 4) // (USART) External (SCK)
#define AT91C_US_CHRL ((unsigned int) 0x3 << 6) // (USART) Clock Selection (Baud Rate generator Input Clock
#define AT91C_US_CHRL_5_BITS ((unsigned int) 0x0 << 6) // (USART) Character Length: 5 bits
#define AT91C_US_CHRL_6_BITS ((unsigned int) 0x1 << 6) // (USART) Character Length: 6 bits
#define AT91C_US_CHRL_7_BITS ((unsigned int) 0x2 << 6) // (USART) Character Length: 7 bits
#define AT91C_US_CHRL_8_BITS ((unsigned int) 0x3 << 6) // (USART) Character Length: 8 bits
#define AT91C_US_SYNC ((unsigned int) 0x1 << 8) // (USART) Synchronous Mode Select
#define AT91C_US_PAR ((unsigned int) 0x7 << 9) // (USART) Parity type
#define AT91C_US_PAR_EVEN ((unsigned int) 0x0 << 9) // (USART) Even Parity
#define AT91C_US_PAR_ODD ((unsigned int) 0x1 << 9) // (USART) Odd Parity
#define AT91C_US_PAR_SPACE ((unsigned int) 0x2 << 9) // (USART) Parity forced to 0 (Space)
#define AT91C_US_PAR_MARK ((unsigned int) 0x3 << 9) // (USART) Parity forced to 1 (Mark)
#define AT91C_US_PAR_NONE ((unsigned int) 0x4 << 9) // (USART) No Parity
#define AT91C_US_PAR_MULTI_DROP ((unsigned int) 0x6 << 9) // (USART) Multi-drop mode
#define AT91C_US_NBSTOP ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits
#define AT91C_US_NBSTOP_1_BIT ((unsigned int) 0x0 << 12) // (USART) 1 stop bit
#define AT91C_US_NBSTOP_15_BIT ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
#define AT91C_US_NBSTOP_2_BIT ((unsigned int) 0x2 << 12) // (USART) 2 stop bits
#define AT91C_US_CHMODE ((unsigned int) 0x3 << 14) // (USART) Channel Mode
#define AT91C_US_CHMODE_NORMAL ((unsigned int) 0x0 << 14) // (USART) Normal Mode: The USART channel operates as an RX/TX USART.
#define AT91C_US_CHMODE_AUTO ((unsigned int) 0x1 << 14) // (USART) Automatic Echo: Receiver Data Input is connected to the TXD pin.
#define AT91C_US_CHMODE_LOCAL ((unsigned int) 0x2 << 14) // (USART) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
#define AT91C_US_CHMODE_REMOTE ((unsigned int) 0x3 << 14) // (USART) Remote Loopback: RXD pin is internally connected to TXD pin.
#define AT91C_US_MODE9 ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length
#define AT91C_US_CKLO ((unsigned int) 0x1 << 18) // (USART) Clock Output Select
// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register --------
#define AT91C_US_RXRDY ((unsigned int) 0x1 << 0) // (USART) RXRDY Interrupt
#define AT91C_US_TXRDY ((unsigned int) 0x1 << 1) // (USART) TXRDY Interrupt
#define AT91C_US_RXBRK ((unsigned int) 0x1 << 2) // (USART) Break Received/End of Break
#define AT91C_US_ENDRX ((unsigned int) 0x1 << 3) // (USART) End of Receive Transfer Interrupt
#define AT91C_US_ENDTX ((unsigned int) 0x1 << 4) // (USART) End of Transmit Interrupt
#define AT91C_US_OVRE ((unsigned int) 0x1 << 5) // (USART) Overrun Interrupt
#define AT91C_US_FRAME ((unsigned int) 0x1 << 6) // (USART) Framing Error Interrupt
#define AT91C_US_PARE ((unsigned int) 0x1 << 7) // (USART) Parity Error Interrupt
#define AT91C_US_TIMEOUT ((unsigned int) 0x1 << 8) // (USART) Receiver Time-out
#define AT91C_US_TXEMPTY ((unsigned int) 0x1 << 9) // (USART) TXEMPTY Interrupt
// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register --------
// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register --------
// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register --------
// *****************************************************************************
// SOFTWARE API DEFINITION FOR Special Function Interface
// *****************************************************************************
typedef struct _AT91S_SF {
AT91_REG SF_CIDR; // Chip ID Register
AT91_REG SF_EXID; // Chip ID Extension Register
AT91_REG SF_RSR; // Reset Status Register
AT91_REG SF_MMR; // Memory Mode Register
AT91_REG Reserved0[2]; //
AT91_REG SF_PMR; // Protect Mode Register
} AT91S_SF, *AT91PS_SF;
// -------- SF_CIDR : (SF Offset: 0x0) Chip ID Register --------
#define AT91C_SF_VERSION ((unsigned int) 0x1F << 0) // (SF) Version of the chip
#define AT91C_SF_BIT5 ((unsigned int) 0x1 << 5) // (SF) Hardwired at 0
#define AT91C_SF_BIT6 ((unsigned int) 0x1 << 6) // (SF) Hardwired at 1
#define AT91C_SF_BIT7 ((unsigned int) 0x1 << 7) // (SF) Hardwired at 0
#define AT91C_SF_NVPSIZ ((unsigned int) 0xF << 8) // (SF) Nonvolatile Program Memory Size
#define AT91C_SF_NVPSIZ_NONE ((unsigned int) 0x0 << 8) // (SF) None
#define AT91C_SF_NVPSIZ_32K ((unsigned int) 0x3 << 8) // (SF) 32K Bytes
#define AT91C_SF_NVPSIZ_64K ((unsigned int) 0x5 << 8) // (SF) 64K Bytes
#define AT91C_SF_NVPSIZ_128K ((unsigned int) 0x7 << 8) // (SF) 128K Bytes
#define AT91C_SF_NVPSIZ_256K ((unsigned int) 0x11 << 8) // (SF) 256K Bytes
#define AT91C_SF_NVDSIZ ((unsigned int) 0xF << 12) // (SF) Nonvolatile Data Memory Size
#define AT91C_SF_NVDSIZ_NONE ((unsigned int) 0x0 << 12) // (SF) None
#define AT91C_SF_VDSIZ ((unsigned int) 0xF << 16) // (SF) Volatile Data Memory Size
#define AT91C_SF_VDSIZ_NONE ((unsigned int) 0x0 << 16) // (SF) None
#define AT91C_SF_VDSIZ_1K ((unsigned int) 0x3 << 16) // (SF) 1K Bytes
#define AT91C_SF_VDSIZ_2K ((unsigned int) 0x5 << 16) // (SF) 2K Bytes
#define AT91C_SF_VDSIZ_4K ((unsigned int) 0x7 << 16) // (SF) 4K Bytes
#define AT91C_SF_VDSIZ_8K ((unsigned int) 0x11 << 16) // (SF) 8K Bytes
#define AT91C_SF_ARCH ((unsigned int) 0xFF << 20) // (SF) Chip Architecture
#define AT91C_SF_ARCH_AT91x40 ((unsigned int) 0x28 << 20) // (SF) AT91x40yyy
#define AT91C_SF_ARCH_AT91x55 ((unsigned int) 0x37 << 20) // (SF) AT91x55yyy
#define AT91C_SF_ARCH_AT91x63 ((unsigned int) 0x3F << 20) // (SF) AT91x63yyy
#define AT91C_SF_NVPTYP ((unsigned int) 0x7 << 28) // (SF) Nonvolatile Program Memory Type
#define AT91C_SF_NVPTYP_NVPTYP_M ((unsigned int) 0x1 << 28) // (SF) 'M' Series or 'F' Series
#define AT91C_SF_NVPTYP_NVPTYP_R ((unsigned int) 0x4 << 28) // (SF) 'R' Series
#define AT91C_SF_EXT ((unsigned int) 0x1 << 31) // (SF) Extension Flag
// -------- SF_RSR : (SF Offset: 0x8) Reset Status Information --------
#define AT91C_SF_RESET ((unsigned int) 0xFF << 0) // (SF) Cause of Reset
#define AT91C_SF_RESET_WD ((unsigned int) 0x35) // (SF) Internal Watchdog
#define AT91C_SF_RESET_EXT ((unsigned int) 0x6C) // (SF) External Pin
// -------- SF_MMR : (SF Offset: 0xc) Memory Mode Register --------
#define AT91C_SF_RAMWU ((unsigned int) 0x1 << 0) // (SF) Internal Extended RAM Write Detection
// -------- SF_PMR : (SF Offset: 0x18) Protection Mode Register --------
#define AT91C_SF_AIC ((unsigned int) 0x1 << 5) // (SF) AIC Protect Mode Enable
#define AT91C_SF_PMRKEY ((unsigned int) 0xFFFF << 16) // (SF) Protect Mode Register Key
// *****************************************************************************
// SOFTWARE API DEFINITION FOR External Bus Interface
// *****************************************************************************
typedef struct _AT91S_EBI {
AT91_REG EBI_CSR[8]; // Chip-select Register
AT91_REG EBI_RCR; // Remap Control Register
AT91_REG EBI_MCR; // Memory Control Register
} AT91S_EBI, *AT91PS_EBI;
// -------- EBI_CSR : (EBI Offset: 0x0) Chip Select Register --------
#define AT91C_EBI_DBW ((unsigned int) 0x3 << 0) // (EBI) Data Bus Width
#define AT91C_EBI_DBW_16 ((unsigned int) 0x1) // (EBI) 16-bit data bus width
#define AT91C_EBI_DBW_8 ((unsigned int) 0x2) // (EBI) 8-bit data bus width
#define AT91C_EBI_NWS ((unsigned int) 0x7 << 2) // (EBI) Number of wait states
#define AT91C_EBI_NWS_1 ((unsigned int) 0x0 << 2) // (EBI) 1 wait state
#define AT91C_EBI_NWS_2 ((unsigned int) 0x1 << 2) // (EBI) 2 wait state
#define AT91C_EBI_NWS_3 ((unsigned int) 0x2 << 2) // (EBI) 3 wait state
#define AT91C_EBI_NWS_4 ((unsigned int) 0x3 << 2) // (EBI) 4 wait state
#define AT91C_EBI_NWS_5 ((unsigned int) 0x4 << 2) // (EBI) 5 wait state
#define AT91C_EBI_NWS_6 ((unsigned int) 0x5 << 2) // (EBI) 6 wait state
#define AT91C_EBI_NWS_7 ((unsigned int) 0x6 << 2) // (EBI) 7 wait state
#define AT91C_EBI_NWS_8 ((unsigned int) 0x7 << 2) // (EBI) 8 wait state
#define AT91C_EBI_WSE ((unsigned int) 0x1 << 5) // (EBI) Wait State Enable
#define AT91C_EBI_PAGES ((unsigned int) 0x3 << 7) // (EBI) Pages Size
#define AT91C_EBI_PAGES_1M ((unsigned int) 0x0 << 7) // (EBI) 1M Byte
#define AT91C_EBI_PAGES_4M ((unsigned int) 0x1 << 7) // (EBI) 4M Byte
#define AT91C_EBI_PAGES_16M ((unsigned int) 0x2 << 7) // (EBI) 16M Byte
#define AT91C_EBI_PAGES_64M ((unsigned int) 0x3 << 7) // (EBI) 64M Byte
#define AT91C_EBI_TDF ((unsigned int) 0x7 << 9) // (EBI) Data Float Output Time
#define AT91C_EBI_TDF_0 ((unsigned int) 0x0 << 9) // (EBI) 1 TDF
#define AT91C_EBI_TDF_1 ((unsigned int) 0x1 << 9) // (EBI) 2 TDF
#define AT91C_EBI_TDF_2 ((unsigned int) 0x2 << 9) // (EBI) 3 TDF
#define AT91C_EBI_TDF_3 ((unsigned int) 0x3 << 9) // (EBI) 4 TDF
#define AT91C_EBI_TDF_4 ((unsigned int) 0x4 << 9) // (EBI) 5 TDF
#define AT91C_EBI_TDF_5 ((unsigned int) 0x5 << 9) // (EBI) 6 TDF
#define AT91C_EBI_TDF_6 ((unsigned int) 0x6 << 9) // (EBI) 7 TDF
#define AT91C_EBI_TDF_7 ((unsigned int) 0x7 << 9) // (EBI) 8 TDF
#define AT91C_EBI_BAT ((unsigned int) 0x1 << 12) // (EBI) Byte Access Type
#define AT91C_EBI_CSEN ((unsigned int) 0x1 << 13) // (EBI) Chip Select Enable
#define AT91C_EBI_BA ((unsigned int) 0xFFF << 20) // (EBI) Base Address
// -------- EBI_RCR : (EBI Offset: 0x20) Remap Control Register --------
#define AT91C_EBI_RCB ((unsigned int) 0x1 << 0) // (EBI) 0 = No effect. 1 = Cancels the remapping (performed at reset) of the page zero memory devices.
// -------- EBI_MCR : (EBI Offset: 0x24) Memory Control Register --------
#define AT91C_EBI_ALE ((unsigned int) 0x7 << 0) // (EBI) Address Line Enable
#define AT91C_EBI_ALE_16M ((unsigned int) 0x0) // (EBI) Valid Address Bits = A20, A21, A22, A23 Max Addressable Space = 16M Bytes Valid Chip Select=None
#define AT91C_EBI_ALE_8M ((unsigned int) 0x4) // (EBI) Valid Address Bits = A20, A21, A22 Max Addressable Space = 8M Bytes Valid Chip Select = CS4
#define AT91C_EBI_ALE_4M ((unsigned int) 0x5) // (EBI) Valid Address Bits = A20, A21 Max Addressable Space = 4M Bytes Valid Chip Select = CS4, CS5
#define AT91C_EBI_ALE_2M ((unsigned int) 0x6) // (EBI) Valid Address Bits = A20 Max Addressable Space = 2M Bytes Valid Chip Select = CS4, CS5, CS6
#define AT91C_EBI_ALE_1M ((unsigned int) 0x7) // (EBI) Valid Address Bits = None Max Addressable Space = 1M Byte Valid Chip Select = CS4, CS5, CS6, CS7
#define AT91C_EBI_DRP ((unsigned int) 0x1 << 4) // (EBI)
// *****************************************************************************
// REGISTER ADDRESS DEFINITION FOR AT91R40008
// *****************************************************************************
// ========== Register definition for AIC peripheral ==========
#define AT91C_AIC_EOICR ((AT91_REG *) 0xFFFFF130) // (AIC) End of Interrupt Command Register
#define AT91C_AIC_ICCR ((AT91_REG *) 0xFFFFF128) // (AIC) Interrupt Clear Command Register
#define AT91C_AIC_IECR ((AT91_REG *) 0xFFFFF120) // (AIC) Interrupt Enable Command Register
#define AT91C_AIC_SVR ((AT91_REG *) 0xFFFFF080) // (AIC) Source Vector egister
#define AT91C_AIC_SMR ((AT91_REG *) 0xFFFFF000) // (AIC) Source Mode egister
#define AT91C_AIC_SPU ((AT91_REG *) 0xFFFFF134) // (AIC) Spurious Vector Register
#define AT91C_AIC_FVR ((AT91_REG *) 0xFFFFF104) // (AIC) FIQ Vector Register
#define AT91C_AIC_IVR ((AT91_REG *) 0xFFFFF100) // (AIC) IRQ Vector Register
#define AT91C_AIC_ISR ((AT91_REG *) 0xFFFFF108) // (AIC) Interrupt Status Register
#define AT91C_AIC_IMR ((AT91_REG *) 0xFFFFF110) // (AIC) Interrupt Mask Register
#define AT91C_AIC_ISCR ((AT91_REG *) 0xFFFFF12C) // (AIC) Interrupt Set Command Register
#define AT91C_AIC_IPR ((AT91_REG *) 0xFFFFF10C) // (AIC) Interrupt Pending Register
#define AT91C_AIC_CISR ((AT91_REG *) 0xFFFFF114) // (AIC) Core Interrupt Status Register
#define AT91C_AIC_IDCR ((AT91_REG *) 0xFFFFF124) // (AIC) Interrupt Disable Command egister
// ========== Register definition for WD peripheral ==========
#define AT91C_WD_SR ((AT91_REG *) 0xFFFF800C) // (WD) Status Register
#define AT91C_WD_CMR ((AT91_REG *) 0xFFFF8004) // (WD) Clock Mode Register
#define AT91C_WD_CR ((AT91_REG *) 0xFFFF8008) // (WD) Control Register
#define AT91C_WD_OMR ((AT91_REG *) 0xFFFF8000) // (WD) Overflow Mode Register
// ========== Register definition for PS peripheral ==========
#define AT91C_PS_PCDR ((AT91_REG *) 0xFFFF4008) // (PS) Peripheral Clock Disable Register
#define AT91C_PS_CR ((AT91_REG *) 0xFFFF4000) // (PS) Control Register
#define AT91C_PS_PCSR ((AT91_REG *) 0xFFFF400C) // (PS) Peripheral Clock Status Register
#define AT91C_PS_PCER ((AT91_REG *) 0xFFFF4004) // (PS) Peripheral Clock Enable Register
// ========== Register definition for PIO peripheral ==========
#define AT91C_PIO_MDSR ((AT91_REG *) 0xFFFF0058) // (PIO) Multi-driver Status Register
#define AT91C_PIO_IFSR ((AT91_REG *) 0xFFFF0028) // (PIO) Input Filter Status Register
#define AT91C_PIO_IFER ((AT91_REG *) 0xFFFF0020) // (PIO) Input Filter Enable Register
#define AT91C_PIO_OSR ((AT91_REG *) 0xFFFF0018) // (PIO) Output Status Register
#define AT91C_PIO_OER ((AT91_REG *) 0xFFFF0010) // (PIO) Output Enable Register
#define AT91C_PIO_PSR ((AT91_REG *) 0xFFFF0008) // (PIO) PIO Status Register
#define AT91C_PIO_PDSR ((AT91_REG *) 0xFFFF003C) // (PIO) Pin Data Status Register
#define AT91C_PIO_CODR ((AT91_REG *) 0xFFFF0034) // (PIO) Clear Output Data Register
#define AT91C_PIO_IFDR ((AT91_REG *) 0xFFFF0024) // (PIO) Input Filter Disable Register
#define AT91C_PIO_MDER ((AT91_REG *) 0xFFFF0050) // (PIO) Multi-driver Enable Register
#define AT91C_PIO_IMR ((AT91_REG *) 0xFFFF0048) // (PIO) Interrupt Mask Register
#define AT91C_PIO_IER ((AT91_REG *) 0xFFFF0040) // (PIO) Interrupt Enable Register
#define AT91C_PIO_ODSR ((AT91_REG *) 0xFFFF0038) // (PIO) Output Data Status Register
#define AT91C_PIO_SODR ((AT91_REG *) 0xFFFF0030) // (PIO) Set Output Data Register
#define AT91C_PIO_PER ((AT91_REG *) 0xFFFF0000) // (PIO) PIO Enable Register
#define AT91C_PIO_MDDR ((AT91_REG *) 0xFFFF0054) // (PIO) Multi-driver Disable Register
#define AT91C_PIO_ISR ((AT91_REG *) 0xFFFF004C) // (PIO) Interrupt Status Register
#define AT91C_PIO_IDR ((AT91_REG *) 0xFFFF0044) // (PIO) Interrupt Disable Register
#define AT91C_PIO_PDR ((AT91_REG *) 0xFFFF0004) // (PIO) PIO Disable Register
#define AT91C_PIO_ODR ((AT91_REG *) 0xFFFF0014) // (PIO) Output Disable Registerr
// ========== Register definition for TC2 peripheral ==========
#define AT91C_TC2_IDR ((AT91_REG *) 0xFFFE00A8) // (TC2) Interrupt Disable Register
#define AT91C_TC2_SR ((AT91_REG *) 0xFFFE00A0) // (TC2) Status Register
#define AT91C_TC2_RB ((AT91_REG *) 0xFFFE0098) // (TC2) Register B
#define AT91C_TC2_CV ((AT91_REG *) 0xFFFE0090) // (TC2) Counter Value
#define AT91C_TC2_CCR ((AT91_REG *) 0xFFFE0080) // (TC2) Channel Control Register
#define AT91C_TC2_IMR ((AT91_REG *) 0xFFFE00AC) // (TC2) Interrupt Mask Register
#define AT91C_TC2_IER ((AT91_REG *) 0xFFFE00A4) // (TC2) Interrupt Enable Register
#define AT91C_TC2_RC ((AT91_REG *) 0xFFFE009C) // (TC2) Register C
#define AT91C_TC2_RA ((AT91_REG *) 0xFFFE0094) // (TC2) Register A
#define AT91C_TC2_CMR ((AT91_REG *) 0xFFFE0084) // (TC2) Channel Mode Register
// ========== Register definition for TC1 peripheral ==========
#define AT91C_TC1_IDR ((AT91_REG *) 0xFFFE0068) // (TC1) Interrupt Disable Register
#define AT91C_TC1_SR ((AT91_REG *) 0xFFFE0060) // (TC1) Status Register
#define AT91C_TC1_RB ((AT91_REG *) 0xFFFE0058) // (TC1) Register B
#define AT91C_TC1_CV ((AT91_REG *) 0xFFFE0050) // (TC1) Counter Value
#define AT91C_TC1_CCR ((AT91_REG *) 0xFFFE0040) // (TC1) Channel Control Register
#define AT91C_TC1_IMR ((AT91_REG *) 0xFFFE006C) // (TC1) Interrupt Mask Register
#define AT91C_TC1_IER ((AT91_REG *) 0xFFFE0064) // (TC1) Interrupt Enable Register
#define AT91C_TC1_RC ((AT91_REG *) 0xFFFE005C) // (TC1) Register C
#define AT91C_TC1_RA ((AT91_REG *) 0xFFFE0054) // (TC1) Register A
#define AT91C_TC1_CMR ((AT91_REG *) 0xFFFE0044) // (TC1) Channel Mode Register
// ========== Register definition for TC0 peripheral ==========
#define AT91C_TC0_IDR ((AT91_REG *) 0xFFFE0028) // (TC0) Interrupt Disable Register
#define AT91C_TC0_SR ((AT91_REG *) 0xFFFE0020) // (TC0) Status Register
#define AT91C_TC0_RB ((AT91_REG *) 0xFFFE0018) // (TC0) Register B
#define AT91C_TC0_CV ((AT91_REG *) 0xFFFE0010) // (TC0) Counter Value
#define AT91C_TC0_CCR ((AT91_REG *) 0xFFFE0000) // (TC0) Channel Control Register
#define AT91C_TC0_IMR ((AT91_REG *) 0xFFFE002C) // (TC0) Interrupt Mask Register
#define AT91C_TC0_IER ((AT91_REG *) 0xFFFE0024) // (TC0) Interrupt Enable Register
#define AT91C_TC0_RC ((AT91_REG *) 0xFFFE001C) // (TC0) Register C
#define AT91C_TC0_RA ((AT91_REG *) 0xFFFE0014) // (TC0) Register A
#define AT91C_TC0_CMR ((AT91_REG *) 0xFFFE0004) // (TC0) Channel Mode Register
// ========== Register definition for TCB0 peripheral ==========
#define AT91C_TCB0_BCR ((AT91_REG *) 0xFFFE00C0) // (TCB0) TC Block Control Register
#define AT91C_TCB0_BMR ((AT91_REG *) 0xFFFE00C4) // (TCB0) TC Block Mode Register
// ========== Register definition for PDC_US1 peripheral ==========
#define AT91C_US1_TPR ((AT91_REG *) 0xFFFC4038) // (PDC_US1) Transmit Pointer Register
#define AT91C_US1_RPR ((AT91_REG *) 0xFFFC4030) // (PDC_US1) Receive Pointer Register
#define AT91C_US1_TCR ((AT91_REG *) 0xFFFC403C) // (PDC_US1) Transmit Counter Register
#define AT91C_US1_RCR ((AT91_REG *) 0xFFFC4034) // (PDC_US1) Receive Counter Register
// ========== Register definition for US1 peripheral ==========
#define AT91C_US1_RTOR ((AT91_REG *) 0xFFFCC024) // (US1) Receiver Time-out Register
#define AT91C_US1_THR ((AT91_REG *) 0xFFFCC01C) // (US1) Transmitter Holding Register
#define AT91C_US1_CSR ((AT91_REG *) 0xFFFCC014) // (US1) Channel Status Register
#define AT91C_US1_IDR ((AT91_REG *) 0xFFFCC00C) // (US1) Interrupt Disable Register
#define AT91C_US1_MR ((AT91_REG *) 0xFFFCC004) // (US1) Mode Register
#define AT91C_US1_TTGR ((AT91_REG *) 0xFFFCC028) // (US1) Transmitter Time-guard Register
#define AT91C_US1_BRGR ((AT91_REG *) 0xFFFCC020) // (US1) Baud Rate Generator Register
#define AT91C_US1_RHR ((AT91_REG *) 0xFFFCC018) // (US1) Receiver Holding Register
#define AT91C_US1_IMR ((AT91_REG *) 0xFFFCC010) // (US1) Interrupt Mask Register
#define AT91C_US1_IER ((AT91_REG *) 0xFFFCC008) // (US1) Interrupt Enable Register
#define AT91C_US1_CR ((AT91_REG *) 0xFFFCC000) // (US1) Control Register
// ========== Register definition for PDC_US0 peripheral ==========
#define AT91C_US0_TPR ((AT91_REG *) 0xFFFC0038) // (PDC_US0) Transmit Pointer Register
#define AT91C_US0_RPR ((AT91_REG *) 0xFFFC0030) // (PDC_US0) Receive Pointer Register
#define AT91C_US0_TCR ((AT91_REG *) 0xFFFC003C) // (PDC_US0) Transmit Counter Register
#define AT91C_US0_RCR ((AT91_REG *) 0xFFFC0034) // (PDC_US0) Receive Counter Register
// ========== Register definition for US0 peripheral ==========
#define AT91C_US0_RTOR ((AT91_REG *) 0xFFFD0024) // (US0) Receiver Time-out Register
#define AT91C_US0_THR ((AT91_REG *) 0xFFFD001C) // (US0) Transmitter Holding Register
#define AT91C_US0_CSR ((AT91_REG *) 0xFFFD0014) // (US0) Channel Status Register
#define AT91C_US0_IDR ((AT91_REG *) 0xFFFD000C) // (US0) Interrupt Disable Register
#define AT91C_US0_MR ((AT91_REG *) 0xFFFD0004) // (US0) Mode Register
#define AT91C_US0_TTGR ((AT91_REG *) 0xFFFD0028) // (US0) Transmitter Time-guard Register
#define AT91C_US0_BRGR ((AT91_REG *) 0xFFFD0020) // (US0) Baud Rate Generator Register
#define AT91C_US0_RHR ((AT91_REG *) 0xFFFD0018) // (US0) Receiver Holding Register
#define AT91C_US0_IMR ((AT91_REG *) 0xFFFD0010) // (US0) Interrupt Mask Register
#define AT91C_US0_IER ((AT91_REG *) 0xFFFD0008) // (US0) Interrupt Enable Register
#define AT91C_US0_CR ((AT91_REG *) 0xFFFD0000) // (US0) Control Register
// ========== Register definition for SF peripheral ==========
#define AT91C_SF_PMR ((AT91_REG *) 0xFFF00018) // (SF) Protect Mode Register
#define AT91C_SF_RSR ((AT91_REG *) 0xFFF00008) // (SF) Reset Status Register
#define AT91C_SF_CIDR ((AT91_REG *) 0xFFF00000) // (SF) Chip ID Register
#define AT91C_SF_MMR ((AT91_REG *) 0xFFF0000C) // (SF) Memory Mode Register
#define AT91C_SF_EXID ((AT91_REG *) 0xFFF00004) // (SF) Chip ID Extension Register
// ========== Register definition for EBI peripheral ==========
#define AT91C_EBI_RCR ((AT91_REG *) 0xFFE00020) // (EBI) Remap Control Register
#define AT91C_EBI_CSR ((AT91_REG *) 0xFFE00000) // (EBI) Chip-select Register
#define AT91C_EBI_MCR ((AT91_REG *) 0xFFE00024) // (EBI) Memory Control Register
// *****************************************************************************
// PIO DEFINITIONS FOR AT91R40008
// *****************************************************************************
#define AT91C_PIO_P0 ((unsigned int) 1 << 0) // Pin Controlled by P0
#define AT91C_P0_TCLK0 ((unsigned int) AT91C_PIO_P0) // Timer 0 Clock signal
#define AT91C_PIO_P1 ((unsigned int) 1 << 1) // Pin Controlled by P1
#define AT91C_P1_TIOA0 ((unsigned int) AT91C_PIO_P1) // Timer 0 Signal A
#define AT91C_PIO_P10 ((unsigned int) 1 << 10) // Pin Controlled by P10
#define AT91C_P10_IRQ1 ((unsigned int) AT91C_PIO_P10) // External Interrupt 1
#define AT91C_PIO_P11 ((unsigned int) 1 << 11) // Pin Controlled by P11
#define AT91C_P11_IRQ2 ((unsigned int) AT91C_PIO_P11) // External Interrupt 2
#define AT91C_PIO_P12 ((unsigned int) 1 << 12) // Pin Controlled by P12
#define AT91C_P12_FIQ ((unsigned int) AT91C_PIO_P12) // Fast External Interrupt
#define AT91C_PIO_P13 ((unsigned int) 1 << 13) // Pin Controlled by P13
#define AT91C_P13_SCK0 ((unsigned int) AT91C_PIO_P13) // USART 0 Serial Clock
#define AT91C_PIO_P14 ((unsigned int) 1 << 14) // Pin Controlled by P14
#define AT91C_P14_TXD0 ((unsigned int) AT91C_PIO_P14) // USART 0 Transmit Data
#define AT91C_PIO_P15 ((unsigned int) 1 << 15) // Pin Controlled by P15
#define AT91C_P15_RXD0 ((unsigned int) AT91C_PIO_P15) // USART 0 Receive Data
#define AT91C_PIO_P16 ((unsigned int) 1 << 16) // Pin Controlled by P16
#define AT91C_PIO_P17 ((unsigned int) 1 << 17) // Pin Controlled by P17
#define AT91C_PIO_P18 ((unsigned int) 1 << 18) // Pin Controlled by P18
#define AT91C_PIO_P19 ((unsigned int) 1 << 19) // Pin Controlled by P19
#define AT91C_PIO_P2 ((unsigned int) 1 << 2) // Pin Controlled by P2
#define AT91C_P2_TIOB0 ((unsigned int) AT91C_PIO_P2) // Timer 0 Signal B
#define AT91C_PIO_P20 ((unsigned int) 1 << 20) // Pin Controlled by P20
#define AT91C_P20_SCK1 ((unsigned int) AT91C_PIO_P20) // USART 1 Serial Clock
#define AT91C_PIO_P21 ((unsigned int) 1 << 21) // Pin Controlled by P21
#define AT91C_P21_TXD1 ((unsigned int) AT91C_PIO_P21) // USART 1 Transmit Data
#define AT91C_P21_NTRI ((unsigned int) AT91C_PIO_P21) // Tri-state Mode
#define AT91C_PIO_P22 ((unsigned int) 1 << 22) // Pin Controlled by P22
#define AT91C_P22_RXD1 ((unsigned int) AT91C_PIO_P22) // USART 1 Receive Data
#define AT91C_PIO_P23 ((unsigned int) 1 << 23) // Pin Controlled by P23
#define AT91C_PIO_P24 ((unsigned int) 1 << 24) // Pin Controlled by P24
#define AT91C_P24_BMS ((unsigned int) AT91C_PIO_P24) // Boot Mode Select
#define AT91C_PIO_P25 ((unsigned int) 1 << 25) // Pin Controlled by P25
#define AT91C_P25_MCKO ((unsigned int) AT91C_PIO_P25) // Master Clock Out
#define AT91C_PIO_P26 ((unsigned int) 1 << 26) // Pin Controlled by P26
#define AT91C_P26_NCS2 ((unsigned int) AT91C_PIO_P26) // Chip Select 2
#define AT91C_PIO_P27 ((unsigned int) 1 << 27) // Pin Controlled by P27
#define AT91C_P27_NCS3 ((unsigned int) AT91C_PIO_P27) // Chip Select 3
#define AT91C_PIO_P28 ((unsigned int) 1 << 28) // Pin Controlled by P28
#define AT91C_P28_A20 ((unsigned int) AT91C_PIO_P28) // Address line A20
#define AT91C_P28_NCS7 ((unsigned int) AT91C_PIO_P28) // Chip Select 7
#define AT91C_PIO_P29 ((unsigned int) 1 << 29) // Pin Controlled by P29
#define AT91C_P29_A21 ((unsigned int) AT91C_PIO_P29) // Address line A21
#define AT91C_P29_NCS6 ((unsigned int) AT91C_PIO_P29) // Chip Select 6
#define AT91C_PIO_P3 ((unsigned int) 1 << 3) // Pin Controlled by P3
#define AT91C_P3_TCLK1 ((unsigned int) AT91C_PIO_P3) // Timer 1 Clock signal
#define AT91C_PIO_P30 ((unsigned int) 1 << 30) // Pin Controlled by P30
#define AT91C_P30_A22 ((unsigned int) AT91C_PIO_P30) // Address line A22
#define AT91C_P30_NCS5 ((unsigned int) AT91C_PIO_P30) // Chip Select 5
#define AT91C_PIO_P31 ((unsigned int) 1 << 31) // Pin Controlled by P31
#define AT91C_P31_A23 ((unsigned int) AT91C_PIO_P31) // Address line A23
#define AT91C_P31_NCS4 ((unsigned int) AT91C_PIO_P31) // Chip Select 4
#define AT91C_PIO_P4 ((unsigned int) 1 << 4) // Pin Controlled by P4
#define AT91C_P4_TIOA1 ((unsigned int) AT91C_PIO_P4) // Timer 1 Signal A
#define AT91C_PIO_P5 ((unsigned int) 1 << 5) // Pin Controlled by P5
#define AT91C_P5_TIOB1 ((unsigned int) AT91C_PIO_P5) // Timer 1 Signal B
#define AT91C_PIO_P6 ((unsigned int) 1 << 6) // Pin Controlled by P6
#define AT91C_P6_TCLK2 ((unsigned int) AT91C_PIO_P6) // Timer 2 Clock signal
#define AT91C_PIO_P7 ((unsigned int) 1 << 7) // Pin Controlled by P7
#define AT91C_P7_TIOA2 ((unsigned int) AT91C_PIO_P7) // Timer 2 Signal A
#define AT91C_PIO_P8 ((unsigned int) 1 << 8) // Pin Controlled by P8
#define AT91C_P8_TIOB2 ((unsigned int) AT91C_PIO_P8) // Timer 2 Signal B
#define AT91C_PIO_P9 ((unsigned int) 1 << 9) // Pin Controlled by P9
#define AT91C_P9_IRQ0 ((unsigned int) AT91C_PIO_P9) // External Interrupt 0
// *****************************************************************************
// PERIPHERAL ID DEFINITIONS FOR AT91R40008
// *****************************************************************************
#define AT91C_ID_FIQ ((unsigned int) 0) // Advanced Interrupt Controller (FIQ)
#define AT91C_ID_SYS ((unsigned int) 1) // SWI
#define AT91C_ID_US0 ((unsigned int) 2) // USART 0
#define AT91C_ID_US1 ((unsigned int) 3) // USART 1
#define AT91C_ID_TC0 ((unsigned int) 4) // Timer Counter 0
#define AT91C_ID_TC1 ((unsigned int) 5) // Timer Counter 1
#define AT91C_ID_TC2 ((unsigned int) 6) // Timer Counter 2
#define AT91C_ID_WD ((unsigned int) 7) // Watchdog Timer
#define AT91C_ID_PIO ((unsigned int) 8) // Parallel IO Controller
#define AT91C_ID_IRQ0 ((unsigned int) 16) // Advanced Interrupt Controller (IRQ0)
#define AT91C_ID_IRQ1 ((unsigned int) 17) // Advanced Interrupt Controller (IRQ1)
#define AT91C_ID_IRQ2 ((unsigned int) 18) // Advanced Interrupt Controller (IRQ2)
// *****************************************************************************
// BASE ADDRESS DEFINITIONS FOR AT91R40008
// *****************************************************************************
#define AT91C_BASE_AIC ((AT91PS_AIC) 0xFFFFF000) // (AIC) Base Address
#define AT91C_BASE_WD ((AT91PS_WD) 0xFFFF8000) // (WD) Base Address
#define AT91C_BASE_PS ((AT91PS_PS) 0xFFFF4000) // (PS) Base Address
#define AT91C_BASE_PIO ((AT91PS_PIO) 0xFFFF0000) // (PIO) Base Address
#define AT91C_BASE_TC2 ((AT91PS_TC) 0xFFFE0080) // (TC2) Base Address
#define AT91C_BASE_TC1 ((AT91PS_TC) 0xFFFE0040) // (TC1) Base Address
#define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFE0000) // (TC0) Base Address
#define AT91C_BASE_TCB0 ((AT91PS_TCB) 0xFFFE0000) // (TCB0) Base Address
#define AT91C_BASE_PDC_US1 ((AT91PS_PDC) 0xFFFC4030) // (PDC_US1) Base Address
#define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFCC000) // (US1) Base Address
#define AT91C_BASE_PDC_US0 ((AT91PS_PDC) 0xFFFC0030) // (PDC_US0) Base Address
#define AT91C_BASE_US0 ((AT91PS_USART) 0xFFFD0000) // (US0) Base Address
#define AT91C_BASE_SF ((AT91PS_SF) 0xFFF00000) // (SF) Base Address
#define AT91C_BASE_EBI ((AT91PS_EBI) 0xFFE00000) // (EBI) Base Address
// *****************************************************************************
// MEMORY MAPPING DEFINITIONS FOR AT91R40008
// *****************************************************************************
#define AT91C_SRAM_BEFORE_REMAP ((char *) 0x00300000) // Internal SRAM before remap base address
#define AT91C_SRAM_BEFORE_REMAP_SIZE ((unsigned int) 0x00040000) // Internal SRAM before remap size in byte (256 Kbyte)
#define AT91C_SRAM_AFTER_REMAP ((char *) 0x00000000) // Internal SRAM after remap base address
#define AT91C_SRAM_AFTER_REMAP_SIZE ((unsigned int) 0x00040000) // Internal SRAM after remap size in byte (256 Kbyte)
#endif

24
Demo/ARM7_AT91FR40008_GCC/ATEB40x.cfg Normal file
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[SETUP]
CpuVendor=Atmel
CpuChip=AT91R40807
FlashVendor=Atmel
FlashChip=AT49BV/F1614A
RamAddress=$00000000
RamSupport=1
FlashAddress=$01000000
FlashWidth=16
FlashChipsPerSector=1
LittleEndian=0
SectStart=0
SectEnd=38
AutoErase=0
AutoVerify=1
CpuEndian=LITTLE
SimCount=3
MemoryCount=0
ProgramFile=E:\temp\embesttest\Demo\ARM7_AT91R40008_GCC_Embest\rtosdemo.hex
UploadFile=c:\EB40_Lower.bin
Format=Intel Hex
Sim3=EBI_RCR:$00000001
Sim2=EBI_CSR1:$02002122
Sim1=EBI_CSR0:$01002539

79
Demo/ARM7_AT91FR40008_GCC/FreeRTOSConfig.h Normal file
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/*
FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
FreeRTOS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with FreeRTOS; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes FreeRTOS, without being obliged to provide
the source code for any proprietary components. See the licensing section
of http://www.FreeRTOS.org for full details of how and when the exception
can be applied.
***************************************************************************
See http://www.FreeRTOS.org for documentation, latest information, license
and contact details. Please ensure to read the configuration and relevant
port sections of the online documentation.
***************************************************************************
*/
#ifndef FREERTOS_CONFIG_H
#define FREERTOS_CONFIG_H
#include <AT91R40008.h>
#define configFLASH_SPEED_NSEC 100 /* External flash access speed (for ROM builds) */
/*-----------------------------------------------------------
* Application specific definitions.
*
* These definitions should be adjusted for your particular hardware and
* application requirements.
*
* THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
* FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
*----------------------------------------------------------*/
#define configUSE_PREEMPTION 1
#define configUSE_IDLE_HOOK 0
#define configUSE_TICK_HOOK 0
#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 66000000 ) /* = 66.000MHz clk gen */
#define configTICK_RATE_HZ ( ( portTickType ) 1000 )
#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 )
#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 128 )
#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 25 * 1024 ) )
#define configMAX_TASK_NAME_LEN ( 16 )
#define configUSE_TRACE_FACILITY 0
#define configUSE_16_BIT_TICKS 0
#define configIDLE_SHOULD_YIELD 1
/* Co-routine definitions. */
#define configUSE_CO_ROUTINES 0
#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
/* Set the following definitions to 1 to include the API function, or zero
to exclude the API function. */
#define INCLUDE_vTaskPrioritySet 1
#define INCLUDE_uxTaskPriorityGet 1
#define INCLUDE_vTaskDelete 1
#define INCLUDE_vTaskCleanUpResources 0
#define INCLUDE_vTaskSuspend 1
#define INCLUDE_vTaskDelayUntil 1
#define INCLUDE_vTaskDelay 1
#endif /* FREERTOS_CONFIG_H */

99
Demo/ARM7_AT91FR40008_GCC/Makefile Normal file
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# FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.
#
# This file is part of the FreeRTOS distribution.
#
# FreeRTOS is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2 of the License, or
# (at your option) any later version.
#
# FreeRTOS is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with FreeRTOS; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
#
# A special exception to the GPL can be applied should you wish to distribute
# a combined work that includes FreeRTOS, without being obliged to provide
# the source code for any proprietary components. See the licensing section
# of http://www.FreeRTOS.org for full details of how and when the exception
# can be applied.
#
# ***************************************************************************
# See http://www.FreeRTOS.org for documentation, latest information, license
# and contact details. Please ensure to read the configuration and relevant
# port sections of the online documentation.
# ***************************************************************************
CC=arm-elf-gcc
OBJCOPY=arm-elf-objcopy
ARCH=arm-elf-ar
CRT0=boot.s
#
# CFLAGS common to both the THUMB and ARM mode builds
#
CFLAGS=-Wall -D $(RUN_MODE) -D GCC_AT91FR40008 -I. -I../../Source/include \
-I../Common/include $(DEBUG) -mcpu=arm7tdmi -T$(LDSCRIPT) \
-Wcast-align $(OPTIM)
ifeq ($(USE_THUMB_MODE),YES)
CFLAGS += -mthumb-interwork -D THUMB_INTERWORK
THUMB_FLAGS=-mthumb
endif
LINKER_FLAGS=-Xlinker -ortosdemo.elf -Xlinker -M -Xlinker -Map=rtosdemo.map
#
# Source files that can be built to THUMB mode.
#
THUMB_SRC = \
main.c \
serial/serial.c \
ParTest/ParTest.c \
../Common/Minimal/integer.c \
../Common/Minimal/flash.c \
../Common/Minimal/PollQ.c \
../Common/Minimal/comtest.c \
../Common/Minimal/flop.c \
../Common/Minimal/semtest.c \
../Common/Minimal/dynamic.c \
../Common/Minimal/BlockQ.c \
../../Source/tasks.c \
../../Source/queue.c \
../../Source/list.c \
../../Source/portable/MemMang/heap_2.c \
../../Source/portable/GCC/ARM7_AT91FR40008/port.c
#
# Source files that must be built to ARM mode.
#
ARM_SRC = \
../../Source/portable/GCC/ARM7_AT91FR40008/portISR.c \
serial/serialISR.c
#
# Define all object files.
#
ARM_OBJ = $(ARM_SRC:.c=.o)
THUMB_OBJ = $(THUMB_SRC:.c=.o)
rtosdemo.hex : rtosdemo.elf
$(OBJCOPY) rtosdemo.elf -O ihex rtosdemo.hex
rtosdemo.elf : $(ARM_OBJ) $(THUMB_OBJ) $(CRT0) Makefile
$(CC) $(CFLAGS) $(ARM_OBJ) $(THUMB_OBJ) -nostartfiles $(CRT0) $(LINKER_FLAGS)
$(THUMB_OBJ) : %.o : %.c $(LDSCRIPT) Makefile
$(CC) -c $(THUMB_FLAGS) $(CFLAGS) $< -o $@
$(ARM_OBJ) : %.o : %.c $(LDSCRIPT) Makefile
$(CC) -c $(CFLAGS) $< -o $@
clean :
touch Makefile

120
Demo/ARM7_AT91FR40008_GCC/ParTest/ParTest.c Normal file
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/*
FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
FreeRTOS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with FreeRTOS; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes FreeRTOS, without being obliged to provide
the source code for any proprietary components. See the licensing section
of http://www.FreeRTOS.org for full details of how and when the exception
can be applied.
***************************************************************************
See http://www.FreeRTOS.org for documentation, latest information, license
and contact details. Please ensure to read the configuration and relevant
port sections of the online documentation.
***************************************************************************
*/
/* Scheduler includes. */
#include "FreeRTOS.h"
#include "portable.h"
/* Demo app includes. */
#include "partest.h"
/* Hardware specific definitions. */
#include "AT91R40008.h"
#include "pio.h"
#include "aic.h"
#define partstNUM_LEDS ( 8 )
#define partstALL_OUTPUTS_OFF ( ( unsigned portLONG ) ~(0xFFFFFFFF << partstNUM_LEDS) )
static unsigned portLONG ulLEDReg;
/*-----------------------------------------------------------
* Simple parallel port IO routines.
*-----------------------------------------------------------*/
static void SetLeds (unsigned int leds)
{
unsigned portLONG ulPIOSetReg, ulPIOClearReg;
/* LEDs are grouped in different port bits: P3-P6 and P16-P19.
A port bit set to '0' turns an LED on, '1' turns it off. */
ulPIOSetReg = ( (leds & 0xF) << 16 ) | ( (leds & 0xF0) >> 1 );
ulPIOClearReg = (~ulPIOSetReg) & 0x000F0078;
AT91C_BASE_PIO->PIO_SODR = ulPIOSetReg;
AT91C_BASE_PIO->PIO_CODR = ulPIOClearReg;
}
/*-----------------------------------------------------------*/
void vParTestInitialise( void )
{
/* This is performed from main() as the io bits are shared with other setup
functions. Ensure the outputs are off to start. */
ulLEDReg = partstALL_OUTPUTS_OFF;
/* Enable clock to PIO... */
AT91C_BASE_PS->PS_PCER = AT91C_PS_PIO;
/* Enable all 8 LEDs and the four switches to be controlled by PIO... */
AT91C_BASE_PIO->PIO_PER = P3 | P4 | P5 | P6 | P16 | P17 | P18 | P19 | P1 | P2 | P9 | P12;
/* Configure all LED PIO lines for output... */
AT91C_BASE_PIO->PIO_OER = P3 | P4 | P5 | P6 | P16 | P17 | P18 | P19;
/* Configure all switch PIO lines for input... */
AT91C_BASE_PIO->PIO_ODR = P1 | P2 | P9 | P12;
/* Set initial state of LEDs. */
SetLeds( ulLEDReg );
}
/*-----------------------------------------------------------*/
void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue )
{
/* Switch an LED on or off as requested. */
if (uxLED < partstNUM_LEDS)
{
if( xValue )
{
ulLEDReg &= ~(1 << uxLED);
}
else
{
ulLEDReg |= (1 << uxLED);
}
SetLeds( ulLEDReg );
}
}
/*-----------------------------------------------------------*/
void vParTestToggleLED( unsigned portBASE_TYPE uxLED )
{
/* Toggle the state of the requested LED. */
if (uxLED < partstNUM_LEDS)
{
ulLEDReg ^= ( 1 << uxLED );
SetLeds( ulLEDReg );
}
}

81
Demo/ARM7_AT91FR40008_GCC/aic.h Normal file
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//*----------------------------------------------------------------------------
//* ATMEL Microcontroller Software Support - ROUSSET -
//*----------------------------------------------------------------------------
//* The software is delivered "AS IS" without warranty or condition of any
//* kind, either express, implied or statutory. This includes without
//* limitation any warranty or condition with respect to merchantability or
//* fitness for any particular purpose, or against the infringements of
//* intellectual property rights of others.
//*----------------------------------------------------------------------------
//* File Name : aic.h
//* Object : Advanced Interrupt Controller Definition File.
//*
//* 1.0 01/04/00 JCZ : Creation
//*----------------------------------------------------------------------------
#ifndef aic_h
#define aic_h
//#include "periph/stdc/std_c.h"
/*-----------------------------------------*/
/* AIC User Interface Structure Definition */
/*-----------------------------------------*/
typedef struct
{
at91_reg AIC_SMR[32] ; /* Source Mode Register */
at91_reg AIC_SVR[32] ; /* Source Vector Register */
at91_reg AIC_IVR ; /* IRQ Vector Register */
at91_reg AIC_FVR ; /* FIQ Vector Register */
at91_reg AIC_ISR ; /* Interrupt Status Register */
at91_reg AIC_IPR ; /* Interrupt Pending Register */
at91_reg AIC_IMR ; /* Interrupt Mask Register */
at91_reg AIC_CISR ; /* Core Interrupt Status Register */
at91_reg reserved0 ;
at91_reg reserved1 ;
at91_reg AIC_IECR ; /* Interrupt Enable Command Register */
at91_reg AIC_IDCR ; /* Interrupt Disable Command Register */
at91_reg AIC_ICCR ; /* Interrupt Clear Command Register */
at91_reg AIC_ISCR ; /* Interrupt Set Command Register */
at91_reg AIC_EOICR ; /* End of Interrupt Command Register */
at91_reg AIC_SPU ; /* Spurious Vector Register */
} StructAIC ;
/*--------------------------------------------*/
/* AIC_SMR[]: Interrupt Source Mode Registers */
/*--------------------------------------------*/
#define AIC_PRIOR 0x07 /* Priority */
#define AIC_SRCTYPE 0x60 /* Source Type Definition */
/* Internal Interrupts */
#define AIC_SRCTYPE_INT_LEVEL_SENSITIVE 0x00 /* Level Sensitive */
#define AIC_SRCTYPE_INT_EDGE_TRIGGERED 0x20 /* Edge Triggered */
/* External Interrupts */
#define AIC_SRCTYPE_EXT_LOW_LEVEL 0x00 /* Low Level */
#define AIC_SRCTYPE_EXT_NEGATIVE_EDGE 0x20 /* Negative Edge */
#define AIC_SRCTYPE_EXT_HIGH_LEVEL 0x40 /* High Level */
#define AIC_SRCTYPE_EXT_POSITIVE_EDGE 0x60 /* Positive Edge */
/*------------------------------------*/
/* AIC_ISR: Interrupt Status Register */
/*------------------------------------*/
#define AIC_IRQID 0x1F /* Current source interrupt */
/*------------------------------------------*/
/* AIC_CISR: Interrupt Core Status Register */
/*------------------------------------------*/
#define AIC_NFIQ 0x01 /* Core FIQ Status */
#define AIC_NIRQ 0x02 /* Core IRQ Status */
/*-------------------------------*/
/* Advanced Interrupt Controller */
/*-------------------------------*/
#define AIC_BASE ((StructAIC *)0xFFFFF000)
#endif /* aic_h */

48
Demo/ARM7_AT91FR40008_GCC/atmel-ram.ld Normal file
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MEMORY
{
ram : ORIGIN = 0x00000000, LENGTH = 256K
}
__stack_end__ = 0x00000000 + 256K - 4;
SECTIONS
{
. = 0;
startup : { *(.startup)} >ram
prog :
{
*(.text)
*(.rodata)
*(.rodata*)
*(.glue_7)
*(.glue_7t)
} >ram
__end_of_text__ = .;
.data :
{
__data_beg__ = .;
__data_beg_src__ = __end_of_text__;
*(.data)
__data_end__ = .;
} >ram
.bss :
{
__bss_beg__ = .;
*(.bss)
} >ram
/* Align here to ensure that the .bss section occupies space up to
_end. Align after .bss to ensure correct alignment even if the
.bss section disappears because there are no input sections. */
. = ALIGN(32 / 8);
}
. = ALIGN(32 / 8);
_end = .;
_bss_end__ = . ; __bss_end__ = . ; __end__ = . ;
PROVIDE (end = .);

49
Demo/ARM7_AT91FR40008_GCC/atmel-rom.ld Normal file
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MEMORY
{
flash : ORIGIN = 0x00000000, LENGTH = 2048K
ram : ORIGIN = 0x00300000, LENGTH = 256K
}
__stack_end__ = 0x00300000 + 256K - 4;
SECTIONS
{
. = 0;
startup : { *(.startup)} >flash
prog :
{
*(.text)
*(.rodata)
*(.rodata*)
*(.glue_7)
*(.glue_7t)
} >flash
__end_of_text__ = .;
.data :
{
__data_beg__ = .;
__data_beg_src__ = __end_of_text__;
*(.data)
__data_end__ = .;
} >ram AT>flash
.bss :
{
__bss_beg__ = .;
*(.bss)
} >ram
/* Align here to ensure that the .bss section occupies space up to
_end. Align after .bss to ensure correct alignment even if the
.bss section disappears because there are no input sections. */
. = ALIGN(32 / 8);
}
. = ALIGN(32 / 8);
_end = .;
_bss_end__ = . ; __bss_end__ = . ; __end__ = . ;
PROVIDE (end = .);

157
Demo/ARM7_AT91FR40008_GCC/boot.s Normal file
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/* Sample initialization file */
.extern main
.extern exit
.text
.code 32
.align 0
.extern __bss_beg__
.extern __bss_end__
.extern __stack_end__
.extern __data_beg__
.extern __data_end__
.extern __data+beg_src__
.global start
.global endless_loop
/* Stack Sizes */
.set UND_STACK_SIZE, 0x00000004
.set ABT_STACK_SIZE, 0x00000004
.set FIQ_STACK_SIZE, 0x00000004
.set IRQ_STACK_SIZE, 0X00000400
.set SVC_STACK_SIZE, 0x00000400
/* Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs */
.set MODE_USR, 0x10 /* User Mode */
.set MODE_FIQ, 0x11 /* FIQ Mode */
.set MODE_IRQ, 0x12 /* IRQ Mode */
.set MODE_SVC, 0x13 /* Supervisor Mode */
.set MODE_ABT, 0x17 /* Abort Mode */
.set MODE_UND, 0x1B /* Undefined Mode */
.set MODE_SYS, 0x1F /* System Mode */
.equ I_BIT, 0x80 /* when I bit is set, IRQ is disabled */
.equ F_BIT, 0x40 /* when F bit is set, FIQ is disabled */
start:
_start:
_mainCRTStartup:
/* Setup a stack for each mode - note that this only sets up a usable stack
for system/user, SWI and IRQ modes. Also each mode is setup with
interrupts initially disabled. */
ldr r0, .LC6
msr CPSR_c, #MODE_UND|I_BIT|F_BIT /* Undefined Instruction Mode */
mov sp, r0
sub r0, r0, #UND_STACK_SIZE
msr CPSR_c, #MODE_ABT|I_BIT|F_BIT /* Abort Mode */
mov sp, r0
sub r0, r0, #ABT_STACK_SIZE
msr CPSR_c, #MODE_FIQ|I_BIT|F_BIT /* FIQ Mode */
mov sp, r0
sub r0, r0, #FIQ_STACK_SIZE
msr CPSR_c, #MODE_IRQ|I_BIT|F_BIT /* IRQ Mode */
mov sp, r0
sub r0, r0, #IRQ_STACK_SIZE
msr CPSR_c, #MODE_SVC|I_BIT|F_BIT /* Supervisor Mode */
mov sp, r0
sub r0, r0, #SVC_STACK_SIZE
msr CPSR_c, #MODE_SYS|I_BIT|F_BIT /* System Mode */
mov sp, r0
/* We want to start in supervisor mode. Operation will switch to system
mode when the first task starts. */
msr CPSR_c, #MODE_SVC|I_BIT|F_BIT
/* Clear BSS. */
mov a2, #0 /* Fill value */
mov fp, a2 /* Null frame pointer */
mov r7, a2 /* Null frame pointer for Thumb */
ldr r1, .LC1 /* Start of memory block */
ldr r3, .LC2 /* End of memory block */
subs r3, r3, r1 /* Length of block */
beq .end_clear_loop
mov r2, #0
.clear_loop:
strb r2, [r1], #1
subs r3, r3, #1
bgt .clear_loop
.end_clear_loop:
/* Initialise data. */
ldr r1, .LC3 /* Start of memory block */
ldr r2, .LC4 /* End of memory block */
ldr r3, .LC5
subs r3, r3, r1 /* Length of block */
beq .end_set_loop
.set_loop:
ldrb r4, [r2], #1
strb r4, [r1], #1
subs r3, r3, #1
bgt .set_loop
.end_set_loop:
mov r0, #0 /* no arguments */
mov r1, #0 /* no argv either */
bl main
endless_loop:
b endless_loop
.align 0
.LC1:
.word __bss_beg__
.LC2:
.word __bss_end__
.LC3:
.word __data_beg__
.LC4:
.word __data_beg_src__
.LC5:
.word __data_end__
.LC6:
.word __stack_end__
/* Setup vector table. Note that undf, pabt, dabt, fiq just execute
a null loop. */
.section .startup,"ax"
.code 32
.align 0
b _start /* reset - _start */
ldr pc, _undf /* undefined - _undf */
ldr pc, _swi /* SWI - _swi */
ldr pc, _pabt /* program abort - _pabt */
ldr pc, _dabt /* data abort - _dabt */
nop /* reserved */
ldr pc, [pc,#-0xF20] /* IRQ - read the AIC */
ldr pc, _fiq /* FIQ - _fiq */
_undf: .word __undf /* undefined */
_swi: .word vPortYieldProcessor /* SWI */
_pabt: .word __pabt /* program abort */
_dabt: .word __dabt /* data abort */
_fiq: .word __fiq /* FIQ */
__undf: b . /* undefined */
__pabt: b . /* program abort */
__dabt: b . /* data abort */
__fiq: b . /* FIQ */

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//*-----------------------------------------------------------------------------
//* ATMEL Microcontroller Software Support - ROUSSET -
//*-----------------------------------------------------------------------------
//* The software is delivered "AS IS" without warranty or condition of any
//* kind, either express, implied or statutory. This includes without
//* limitation any warranty or condition with respect to merchantability or
//* fitness for any particular purpose, or against the infringements of
//* intellectual property rights of others.
//*-----------------------------------------------------------------------------
//* File Name : ebi.h
//* Object : External Bus Interface Definition File
//* Translator : ARM Software Development Toolkit V2.11a
//*
//* 1.0 03/11/97 JCZ : Creation
//* 2.0 21/10/98 JCZ : Clean up
//*-----------------------------------------------------------------------------
#ifndef ebi_h
#define ebi_h
/*----------------------------------------*/
/* Memory Controller Interface Definition */
/*----------------------------------------*/
typedef struct
{
at91_reg EBI_CSR[8] ; /* Chip Select Register */
at91_reg EBI_RCR ; /* Remap Control Register */
at91_reg EBI_MCR ; /* Memory Control Register */
} StructEBI ;
/*-----------------------*/
/* Chip Select Registers */
/*-----------------------*/
/* Data Bus Width */
#define DataBus16 (1<<0)
#define DataBus8 (2<<0)
#define DBW (3<<0)
/* Number of Wait States */
#define B_NWS 2
#define WaitState1 (0<<B_NWS)
#define WaitState2 (1<<B_NWS)
#define WaitState3 (2<<B_NWS)
#define WaitState4 (3<<B_NWS)
#define WaitState5 (4<<B_NWS)
#define WaitState6 (5<<B_NWS)
#define WaitState7 (6<<B_NWS)
#define WaitState8 (7<<B_NWS)
#define NWS (7<<B_NWS)
/* Wait State Enable */
#define WaitStateDisable (0<<5)
#define WaitStateEnable (1<<5)
#define WSE (1<<5)
/* Page size */
#define PageSize1M (0<<7)
#define PageSize4M (1<<7)
#define PageSize16M (2<<7)
#define PageSize64M (3<<7)
#define PAGES (3<<7)
/* Number of Data Float Output Time Clock Cycle */
#define B_TDF 9
#define tDF_0cycle (0<<B_TDF)
#define tDF_1cycle (1<<B_TDF)
#define tDF_2cycle (2<<B_TDF)
#define tDF_3cycle (3<<B_TDF)
#define tDF_4cycle (4<<B_TDF)
#define tDF_5cycle (5<<B_TDF)
#define tDF_6cycle (6<<B_TDF)
#define tDF_7cycle (7<<B_TDF)
#define TDF (7<<B_TDF)
/* Byte Access Type */
#define ByteWriteAccessType (0<<12)
#define ByteSelectAccessType (1<<12)
#define BAT 1<<12)
/* Chip Select Enable */
#define CSEnable (1<<13)
#define CSDisable (0<<13)
#define CSE (1<<13)
#define BA ((u_int)(0xFFF)<<20)
/*-------------------------*/
/* Memory Control Register */
/*-------------------------*/
/* Address Line Enable */
#define ALE (7<<0)
#define BankSize16M (0<<0)
#define BankSize8M (4<<0)
#define BankSize4M (5<<0)
#define BankSize2M (6<<0)
#define BankSize1M (7<<0)
/* Data Read Protocol */
#define StandardReadProtocol (0<<4)
#define EarlyReadProtocol (1<<4)
#define DRP (1<<4)
/*------------------------*/
/* Remap Control Register */
/*------------------------*/
#define RCB (1<<0)
/*--------------------------------*/
/* Device Dependancies Definition */
/*--------------------------------*/
#ifdef AT91M40400
/* External Bus Interface User Interface BAse Address */
#define EBI_BASE ((StructEBI *) 0xFFE00000)
#endif
#endif /* ebi_h */

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Demo/ARM7_AT91FR40008_GCC/main.c Normal file
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/*
FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
FreeRTOS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with FreeRTOS; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes FreeRTOS, without being obliged to provide
the source code for any proprietary components. See the licensing section
of http://www.FreeRTOS.org for full details of how and when the exception
can be applied.
***************************************************************************
See http://www.FreeRTOS.org for documentation, latest information, license
and contact details. Please ensure to read the configuration and relevant
port sections of the online documentation.
***************************************************************************
*/
/*
NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode.
The processor MUST be in supervisor mode when vTaskStartScheduler is
called. The demo applications included in the FreeRTOS.org download switch
to supervisor mode prior to main being called. If you are not using one of
these demo application projects then ensure Supervisor mode is used.
*/
/*
* Creates all the demo application tasks, then starts the scheduler. The WEB
* documentation provides more details of the demo application tasks.
*
* Main.c also creates a task called "Check". This only executes every three
* seconds but has the highest priority so is guaranteed to get processor time.
* Its main function is to check that all the other tasks are still operational.
* Each task (other than the "flash" tasks) maintains a unique count that is
* incremented each time the task successfully completes its function. Should
* any error occur within such a task the count is permanently halted. The
* check task inspects the count of each task to ensure it has changed since
* the last time the check task executed. If all the count variables have
* changed all the tasks are still executing error free, and the check task
* toggles the onboard LED. Should any task contain an error at any time
* the LED toggle rate will change from 3 seconds to 500ms.
*
* To check the operation of the memory allocator the check task also
* dynamically creates a task before delaying, and deletes it again when it
* wakes. If memory cannot be allocated for the new task the call to xTaskCreate
* will fail and an error is signalled. The dynamically created task itself
* allocates and frees memory just to give the allocator a bit more exercise.
*
*/
/* Standard includes. */
#include <stdlib.h>
#include <string.h>
/* Scheduler includes. */
#include "FreeRTOS.h"
#include "task.h"
/* Demo application includes. */
#include "partest.h"
#include "flash.h"
#include "integer.h"
#include "PollQ.h"
#include "comtest2.h"
#include "semtest.h"
#include "flop.h"
#include "dynamic.h"
#include "BlockQ.h"
#include "serial.h"
/* Hardware specific definitions. */
#include "aic.h"
#include "ebi.h"
/*-----------------------------------------------------------*/
/* Constants for the ComTest tasks. */
#define mainCOM_TEST_BAUD_RATE ( ( unsigned portLONG ) 115200 )
#define mainCOM_TEST_LED ( 5 )
/* Priorities for the demo application tasks. */
#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 )
#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 )
#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 )
#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 4 )
#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 )
#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 )
/* The rate at which the on board LED will toggle when there is/is not an
error. */
#define mainNO_ERROR_FLASH_PERIOD ( ( portTickType ) 3000 / portTICK_RATE_MS )
#define mainERROR_FLASH_PERIOD ( ( portTickType ) 500 / portTICK_RATE_MS )
#define mainON_BOARD_LED_BIT ( ( unsigned portLONG ) 7 )
/* Constants used by the vMemCheckTask() task. */
#define mainCOUNT_INITIAL_VALUE ( ( unsigned portLONG ) 0 )
#define mainNO_TASK ( 0 )
/* The size of the memory blocks allocated by the vMemCheckTask() task. */
#define mainMEM_CHECK_SIZE_1 ( ( size_t ) 51 )
#define mainMEM_CHECK_SIZE_2 ( ( size_t ) 52 )
#define mainMEM_CHECK_SIZE_3 ( ( size_t ) 151 )
#define MAX_WAIT_STATES 8
static const unsigned portLONG ululCSRWaitValues[ MAX_WAIT_STATES + 1 ] =
{
WaitState1,/* There is no "zero wait state" value, so use one wait state */
WaitState1,
WaitState2,
WaitState3,
WaitState4,
WaitState5,
WaitState6,
WaitState7,
WaitState8
};
/*-----------------------------------------------------------*/
/*
* Checks that all the demo application tasks are still executing without error
* - as described at the top of the file.
*/
static portLONG prvCheckOtherTasksAreStillRunning( unsigned portLONG ulMemCheckTaskCount );
/*
* The task that executes at the highest priority and calls
* prvCheckOtherTasksAreStillRunning(). See the description at the top
* of the file.
*/
static void vErrorChecks( void *pvParameters );
/*
* Dynamically created and deleted during each cycle of the vErrorChecks()
* task. This is done to check the operation of the memory allocator.
* See the top of vErrorChecks for more details.
*/
static void vMemCheckTask( void *pvParameters );
/*
* Configure the processor for use with the Olimex demo board. This includes
* setup for the I/O, system clock, and access timings.
*/
static void prvSetupHardware( void );
/*-----------------------------------------------------------*/
/*
* Starts all the other tasks, then starts the scheduler.
*/
int main( void )
{
/* Setup the hardware for use with the Olimex demo board. */
prvSetupHardware();
/* Start the demo/test application tasks. */
vStartIntegerMathTasks( tskIDLE_PRIORITY );
vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED );
vStartLEDFlashTasks( mainLED_TASK_PRIORITY );
vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );
vStartMathTasks( tskIDLE_PRIORITY );
vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );
vStartDynamicPriorityTasks();
vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );
/* Start the check task - which is defined in this file. */
xTaskCreate( vErrorChecks, ( signed portCHAR * ) "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );
/* Now all the tasks have been started - start the scheduler.
NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode.
The processor MUST be in supervisor mode when vTaskStartScheduler is
called. The demo applications included in the FreeRTOS.org download switch
to supervisor mode prior to main being called. If you are not using one of
these demo application projects then ensure Supervisor mode is used here. */
vTaskStartScheduler();
/* Should never reach here! */
return 0;
}
/*-----------------------------------------------------------*/
static void vErrorChecks( void *pvParameters )
{
portTickType xDelayPeriod = mainNO_ERROR_FLASH_PERIOD;
unsigned portLONG ulMemCheckTaskRunningCount;
xTaskHandle xCreatedTask;
/* Cycle for ever, delaying then checking all the other tasks are still
operating without error. If an error is detected then the delay period
is decreased from mainNO_ERROR_FLASH_PERIOD to mainERROR_FLASH_PERIOD so
the on board LED flash rate will increase.
In addition to the standard tests the memory allocator is tested through
the dynamic creation and deletion of a task each cycle. Each time the
task is created memory must be allocated for its stack. When the task is
deleted this memory is returned to the heap. If the task cannot be created
then it is likely that the memory allocation failed. */
for( ;; )
{
/* Reset xCreatedTask. This is modified by the task about to be
created so we can tell if it is executing correctly or not. */
xCreatedTask = mainNO_TASK;
/* Dynamically create a task - passing ulMemCheckTaskRunningCount as a
parameter. */
ulMemCheckTaskRunningCount = mainCOUNT_INITIAL_VALUE;
if( xTaskCreate( vMemCheckTask, ( signed portCHAR * ) "MEM_CHECK", configMINIMAL_STACK_SIZE, ( void * ) &ulMemCheckTaskRunningCount, tskIDLE_PRIORITY, &xCreatedTask ) != pdPASS )
{
/* Could not create the task - we have probably run out of heap. */
xDelayPeriod = mainERROR_FLASH_PERIOD;
}
/* Delay until it is time to execute again. */
vTaskDelay( xDelayPeriod );
/* Delete the dynamically created task. */
if( xCreatedTask != mainNO_TASK )
{
vTaskDelete( xCreatedTask );
}
/* Check all the standard demo application tasks are executing without
error. ulMemCheckTaskRunningCount is checked to ensure it was
modified by the task just deleted. */
if( prvCheckOtherTasksAreStillRunning( ulMemCheckTaskRunningCount ) != pdPASS )
{
/* An error has been detected in one of the tasks - flash faster. */
xDelayPeriod = mainERROR_FLASH_PERIOD;
}
/* The toggle rate of the LED depends on how long this task delays for.
An error reduces the delay period and so increases the toggle rate. */
vParTestToggleLED( mainON_BOARD_LED_BIT );
}
}
/*-----------------------------------------------------------*/
static void prvSetupHardware( void )
{
portLONG lCount;
#ifdef RUN_FROM_ROM
{
portFLOAT nsecsPerClockTick;
portLONG lNumWaitStates;
unsigned portLONG ulCSRWaitValue;
/* We are compiling to run from ROM (either on-chip or off-chip flash).
Leave the RAM/flash mapped the way they are on reset
(flash @ 0x00000000, RAM @ 0x00300000), and set up the
proper flash wait states (starts out at the maximum number
of wait states on reset, so we should be able to reduce it).
Most of this code will probably get removed by the compiler
if optimization is enabled, since these calculations are
based on constants. But the compiler should still produce
a correct wait state register value. */
nsecsPerClockTick = ( portFLOAT ) 1000000000 / configCPU_CLOCK_HZ;
lNumWaitStates = ( portLONG )( ( configFLASH_SPEED_NSEC / nsecsPerClockTick ) + 0.5 ) - 1;
if( lNumWaitStates < 0 )
{
lNumWaitStates = 0;
}
if( lNumWaitStates > MAX_WAIT_STATES )
{
lNumWaitStates = MAX_WAIT_STATES;
}
ulCSRWaitValue = ululCSRWaitValues[ lNumWaitStates ];
ulCSRWaitValue = WaitState5;
AT91C_BASE_EBI->EBI_CSR[ 0 ] = ulCSRWaitValue | DataBus16 | WaitStateEnable
| PageSize1M | tDF_0cycle
| ByteWriteAccessType | CSEnable
| 0x00000000 /* Base Address */;
}
#else /* else we are compiling to run from on-chip RAM */
{
/* If compiling to run from RAM, we expect the on-chip RAM to already
be mapped at 0x00000000. This is typically done with an initialization
script for the JTAG emulator you are using to download and run the
demo application. So there is nothing to do here in this case. */
}
#endif
/* Disable all interrupts at the AIC level initially... */
AT91C_BASE_AIC->AIC_IDCR = 0xFFFFFFFF;
/* Set all SVR and SMR entries to default values (start with a clean slate)... */
for( lCount = 0; lCount < 32; lCount++ )
{
AT91C_BASE_AIC->AIC_SVR[ lCount ] = (unsigned long) 0;
AT91C_BASE_AIC->AIC_SMR[ lCount ] = AIC_SRCTYPE_INT_EDGE_TRIGGERED;
}
/* Disable clocks to all peripherals initially... */
AT91C_BASE_PS->PS_PCDR = 0xFFFFFFFF;
/* Clear all interrupts at the AIC level initially... */
AT91C_BASE_AIC->AIC_ICCR = 0xFFFFFFFF;
/* Perform 8 "End Of Interrupt" cmds to make sure AIC will not Lock out
nIRQ */
for( lCount = 0; lCount < 8; lCount++ )
{
AT91C_BASE_AIC->AIC_EOICR = 0;
}
/* Initialise LED outputs. */
vParTestInitialise();
}
/*-----------------------------------------------------------*/
static portLONG prvCheckOtherTasksAreStillRunning( unsigned portLONG ulMemCheckTaskCount )
{
portLONG lReturn = ( portLONG ) pdPASS;
/* Check all the demo tasks (other than the flash tasks) to ensure
that they are all still running, and that none of them have detected
an error. */
if( xAreIntegerMathsTaskStillRunning() != pdTRUE )
{
lReturn = ( portLONG ) pdFAIL;
}
if( xAreComTestTasksStillRunning() != pdTRUE )
{
lReturn = ( portLONG ) pdFAIL;
}
if( xArePollingQueuesStillRunning() != pdTRUE )
{
lReturn = ( portLONG ) pdFAIL;
}
if( xAreMathsTaskStillRunning() != pdTRUE )
{
lReturn = ( portLONG ) pdFAIL;
}
if( xAreSemaphoreTasksStillRunning() != pdTRUE )
{
lReturn = ( portLONG ) pdFAIL;
}
if( xAreDynamicPriorityTasksStillRunning() != pdTRUE )
{
lReturn = ( portLONG ) pdFAIL;
}
if( xAreBlockingQueuesStillRunning() != pdTRUE )
{
lReturn = ( portLONG ) pdFAIL;
}
if( ulMemCheckTaskCount == mainCOUNT_INITIAL_VALUE )
{
/* The vMemCheckTask did not increment the counter - it must
have failed. */
lReturn = ( portLONG ) pdFAIL;
}
return lReturn;
}
/*-----------------------------------------------------------*/
static void vMemCheckTask( void *pvParameters )
{
unsigned portLONG *pulMemCheckTaskRunningCounter;
void *pvMem1, *pvMem2, *pvMem3;
static portLONG lErrorOccurred = pdFALSE;
/* This task is dynamically created then deleted during each cycle of the
vErrorChecks task to check the operation of the memory allocator. Each time
the task is created memory is allocated for the stack and TCB. Each time
the task is deleted this memory is returned to the heap. This task itself
exercises the allocator by allocating and freeing blocks.
The task executes at the idle priority so does not require a delay.
pulMemCheckTaskRunningCounter is incremented each cycle to indicate to the
vErrorChecks() task that this task is still executing without error. */
pulMemCheckTaskRunningCounter = ( unsigned portLONG * ) pvParameters;
for( ;; )
{
if( lErrorOccurred == pdFALSE )
{
/* We have never seen an error so increment the counter. */
( *pulMemCheckTaskRunningCounter )++;
}
else
{
/* There has been an error so reset the counter so the check task
can tell that an error occurred. */
*pulMemCheckTaskRunningCounter = mainCOUNT_INITIAL_VALUE;
}
/* Allocate some memory - just to give the allocator some extra
exercise. This has to be in a critical section to ensure the
task does not get deleted while it has memory allocated. */
vTaskSuspendAll();
{
pvMem1 = pvPortMalloc( mainMEM_CHECK_SIZE_1 );
if( pvMem1 == NULL )
{
lErrorOccurred = pdTRUE;
}
else
{
memset( pvMem1, 0xaa, mainMEM_CHECK_SIZE_1 );
vPortFree( pvMem1 );
}
}
xTaskResumeAll();
/* Again - with a different size block. */
vTaskSuspendAll();
{
pvMem2 = pvPortMalloc( mainMEM_CHECK_SIZE_2 );
if( pvMem2 == NULL )
{
lErrorOccurred = pdTRUE;
}
else
{
memset( pvMem2, 0xaa, mainMEM_CHECK_SIZE_2 );
vPortFree( pvMem2 );
}
}
xTaskResumeAll();
/* Again - with a different size block. */
vTaskSuspendAll();
{
pvMem3 = pvPortMalloc( mainMEM_CHECK_SIZE_3 );
if( pvMem3 == NULL )
{
lErrorOccurred = pdTRUE;
}
else
{
memset( pvMem3, 0xaa, mainMEM_CHECK_SIZE_3 );
vPortFree( pvMem3 );
}
}
xTaskResumeAll();
}
}

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//*---------------------------------------------------------------------------
//* ATMEL Microcontroller Software Support - ROUSSET -
//*---------------------------------------------------------------------------
//* The software is delivered "AS IS" without warranty or condition of any
//* kind, either express, implied or statutory. This includes without
//* limitation any warranty or condition with respect to merchantability or
//* fitness for any particular purpose, or against the infringements of
//* intellectual property rights of others.
//*-----------------------------------------------------------------------------
//* File Name : pio.h
//* Object : Parallel I/O Definition File
//* Translator : ARM Software Development Toolkit V2.11a
//*
//* 1.0 20/10/97 JCZ : Creation
//* 2.0 21/10/98 JCZ : Clean up
//*---------------------------------------------------------------------------
#ifndef pio_h
#define pio_h
/*---------------------------------------------*/
/* Parallel I/O Interface Structure Definition */
/*---------------------------------------------*/
typedef struct
{
at91_reg PIO_PER ; /* PIO Enable Register */
at91_reg PIO_PDR ; /* PIO Disable Register */
at91_reg PIO_PSR ; /* PIO Status Register */
at91_reg Reserved0 ;
at91_reg PIO_OER ; /* Output Enable Register */
at91_reg PIO_ODR ; /* Output Disable Register */
at91_reg PIO_OSR ; /* Output Status Register */
at91_reg Reserved1 ;
at91_reg PIO_IFER ; /* Input Filter Enable Register */
at91_reg PIO_IFDR ; /* Input Filter Disable Register */
at91_reg PIO_IFSR ; /* Input Filter Status Register */
at91_reg Reserved2 ;
at91_reg PIO_SODR ; /* Set Output Data Register */
at91_reg PIO_CODR ; /* Clear Output Data Register */
at91_reg PIO_ODSR ; /* Output Data Status Register */
at91_reg PIO_PDSR ; /* Pin Data Status Register */
at91_reg PIO_IER ; /* Interrupt Enable Register */
at91_reg PIO_IDR ; /* Interrupt Disable Register */
at91_reg PIO_IMR ; /* Interrupt Mask Register */
at91_reg PIO_ISR ; /* Interrupt Status Register */
} StructPIO ;
/*-----------------------------*/
/* PIO Handler type definition */
/*-----------------------------*/
//typedef void (*TypePIOHandler) ( StructPIO *pio_pt, u_int pio_mask ) ;
/*--------------------------------*/
/* Device Dependancies Definition */
/*--------------------------------*/
/* Number of PIO Controller */
#define NB_PIO_CTRL 1
/* Base Address */
#define PIO_BASE ((StructPIO *) 0xFFFF0000 )
/* Number of PIO Lines */
#define NB_PIO 32
/* Parallel I/O Bits Definition */
#define P0 (1<<0)
#define P1 (1<<1)
#define P2 (1<<2)
#define P3 (1<<3)
#define P4 (1<<4)
#define P5 (1<<5)
#define P6 (1<<6)
#define P7 (1<<7)
#define P8 (1<<8)
#define P9 (1<<9)
#define P10 (1<<10)
#define P11 (1<<11)
#define P12 (1<<12)
#define P13 (1<<13)
#define P14 (1<<14)
#define P15 (1<<15)
#define P16 (1<<16)
#define P17 (1<<17)
#define P18 (1<<18)
#define P19 (1<<19)
#define P20 (1<<20)
#define P21 (1<<21)
#define P22 (1<<22)
#define P23 (1<<23)
#define P24 (1<<24)
#define P25 (1<<25)
#define P26 (1<<26)
#define P27 (1<<27)
#define P28 (1<<28)
#define P29 (1<<29)
#define P30 (1<<30)
#define P31 (1<<31)
/* PIO Multiplexing Definition */
/* There is only one PIO Controller */
#define PIO_CTRL 0
#define PIO_TC0 PIO_CTRL
#define TCLK0 P0
#define TIOA0 P1
#define TIOB0 P2
#define PIN_TC0 (TIOA0|TIOB0|TCLK0)
#define PIO_TC1 PIO_CTRL
#define TCLK1 P3
#define TIOA1 P4
#define TIOB1 P5
#define PIN_TC1 (TIOA1|TIOB1|TCLK1)
#define PIO_TC2 PIO_CTRL
#define TCLK2 P6
#define TIOA2 P7
#define TIOB2 P8
#define PIN_TC2 (TIOA2|TIOB2|TCLK2)
#define PIO_EXT_IRQ PIO_CTRL
#define PIN_IRQ0 P9
#define PIN_IRQ1 P10
#define PIN_IRQ2 P11
#define PIN_FIQ P12
#define PIO_USART0 PIO_CTRL
#define SCK0 P13
#define TXD0 P14
#define RXD0 P15
#define PIN_USART0 (SCK0|TXD0|RXD0)
#define PIO_USART1 PIO_CTRL
#define SCK1 P20
#define TXD1 P21
#define RXD1 P22
#define PIN_USART1 (SCK1|TXD1|RXD1)
#define MCKO P25
#define CS2 P26
#define CS3 P27
#define CS4 P31
#define CS5 P30
#define CS6 P29
#define CS7 P28
#endif /* pio_h */

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set USE_THUMB_MODE=NO
set DEBUG=-g
set OPTIM=-O0
set RUN_MODE=RUN_FROM_RAM
set LDSCRIPT=atmel-ram.ld
make

6
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set USE_THUMB_MODE=YES
set DEBUG=-g
set OPTIM=-O0
set RUN_MODE=RUN_FROM_RAM
set LDSCRIPT=atmel-ram.ld
make

6
Demo/ARM7_AT91FR40008_GCC/rom_arm.bat Normal file
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set USE_THUMB_MODE=NO
set DEBUG=-g
set OPTIM=-O2
set RUN_MODE=RUN_FROM_ROM
set LDSCRIPT=atmel-rom.ld
make

6
Demo/ARM7_AT91FR40008_GCC/rom_thumb.bat Normal file
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set USE_THUMB_MODE=YES
set DEBUG=-g
set OPTIM=-O2
set RUN_MODE=RUN_FROM_ROM
set LDSCRIPT=atmel-rom.ld
make

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/*
FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
FreeRTOS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with FreeRTOS; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes FreeRTOS, without being obliged to provide
the source code for any proprietary components. See the licensing section
of http://www.FreeRTOS.org for full details of how and when the exception
can be applied.
***************************************************************************
See http://www.FreeRTOS.org for documentation, latest information, license
and contact details. Please ensure to read the configuration and relevant
port sections of the online documentation.
***************************************************************************
*/
/*
BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR USART0.
This file contains all the serial port components that can be compiled to
either ARM or THUMB mode. Components that must be compiled to ARM mode are
contained in serialISR.c.
*/
/* Standard includes. */
#include <stdlib.h>
/* Scheduler includes. */
#include "FreeRTOS.h"
#include "queue.h"
#include "task.h"
/* Demo application includes. */
#include "serial.h"
#include "AT91R40008.h"
#include "usart.h"
#include "pio.h"
#include "aic.h"
/*-----------------------------------------------------------*/
/* Constants to setup and access the UART. */
#define portUSART0_AIC_CHANNEL ( ( unsigned portLONG ) 2 )
#define serINVALID_QUEUE ( ( xQueueHandle ) 0 )
#define serHANDLE ( ( xComPortHandle ) 1 )
#define serNO_BLOCK ( ( portTickType ) 0 )
/*-----------------------------------------------------------*/
/* Queues used to hold received characters, and characters waiting to be
transmitted. */
static xQueueHandle xRxedChars;
static xQueueHandle xCharsForTx;
/*-----------------------------------------------------------*/
/*
* The queues are created in serialISR.c as they are used from the ISR.
* Obtain references to the queues and THRE Empty flag.
*/
extern void vSerialISRCreateQueues( unsigned portBASE_TYPE uxQueueLength, xQueueHandle *pxRxedChars, xQueueHandle *pxCharsForTx );
/*-----------------------------------------------------------*/
xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength )
{
unsigned portLONG ulSpeed;
unsigned portLONG ulCD;
xComPortHandle xReturn = serHANDLE;
extern void ( vUART_ISR )( void );
/* The queues are used in the serial ISR routine, so are created from
serialISR.c (which is always compiled to ARM mode. */
vSerialISRCreateQueues( uxQueueLength, &xRxedChars, &xCharsForTx );
if(
( xRxedChars != serINVALID_QUEUE ) &&
( xCharsForTx != serINVALID_QUEUE ) &&
( ulWantedBaud != ( unsigned portLONG ) 0 )
)
{
portENTER_CRITICAL();
{
/* Enable clock to USART0... */
AT91C_BASE_PS->PS_PCER = AT91C_PS_US0;
/* Disable all USART0 interrupt sources to begin... */
AT91C_BASE_US0->US_IDR = 0xFFFFFFFF;
/* Reset various status bits (just in case)... */
AT91C_BASE_US0->US_CR = US_RSTSTA;
AT91C_BASE_PIO->PIO_PDR = TXD0 | RXD0; /* Enable RXD and TXD pins */
AT91C_BASE_US0->US_CR = US_RSTRX | US_RSTTX | US_RXDIS | US_TXDIS;
/* Clear Transmit and Receive Counters */
AT91C_BASE_US0->US_RCR = 0;
AT91C_BASE_US0->US_TCR = 0;
/* Input clock to baud rate generator is MCK */
ulSpeed = configCPU_CLOCK_HZ * 10;
ulSpeed = ulSpeed / 16;
ulSpeed = ulSpeed / ulWantedBaud;
/* compute the error */
ulCD = ulSpeed / 10;
if ((ulSpeed - (ulCD * 10)) >= 5)
ulCD++;
/* Define the baud rate divisor register */
AT91C_BASE_US0->US_BRGR = ulCD;
/* Define the USART mode */
AT91C_BASE_US0->US_MR = US_CLKS_MCK | US_CHRL_8 | US_PAR_NO | US_NBSTOP_1 | US_CHMODE_NORMAL;
/* Write the Timeguard Register */
AT91C_BASE_US0->US_TTGR = 0;
/* Setup the interrupt for USART0.
Store interrupt handler function address in USART0 vector register... */
AT91C_BASE_AIC->AIC_SVR[ portUSART0_AIC_CHANNEL ] = (unsigned long)vUART_ISR;
/* USART0 interrupt level-sensitive, priority 1... */
AT91C_BASE_AIC->AIC_SMR[ portUSART0_AIC_CHANNEL ] = AIC_SRCTYPE_INT_LEVEL_SENSITIVE | 1;
/* Clear some pending USART0 interrupts (just in case)... */
AT91C_BASE_US0->US_CR = US_RSTSTA;
/* Enable USART0 interrupt sources (but not Tx for now)... */
AT91C_BASE_US0->US_IER = US_RXRDY;
/* Enable USART0 interrupts in the AIC... */
AT91C_BASE_AIC->AIC_IECR = ( 1 << portUSART0_AIC_CHANNEL );
/* Enable receiver and transmitter... */
AT91C_BASE_US0->US_CR = US_RXEN | US_TXEN;
}
portEXIT_CRITICAL();
}
else
{
xReturn = ( xComPortHandle ) 0;
}
return xReturn;
}
/*-----------------------------------------------------------*/
signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime )
{
/* The port handle is not required as this driver only supports UART0. */
( void ) pxPort;
/* Get the next character from the buffer. Return false if no characters
are available, or arrive before xBlockTime expires. */
if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) )
{
return pdTRUE;
}
else
{
return pdFALSE;
}
}
/*-----------------------------------------------------------*/
void vSerialPutString( xComPortHandle pxPort, const signed portCHAR * const pcString, unsigned portSHORT usStringLength )
{
signed portCHAR *pxNext;
/* NOTE: This implementation does not handle the queue being full as no
block time is used! */
/* The port handle is not required as this driver only supports UART0. */
( void ) pxPort;
/* Send each character in the string, one at a time. */
pxNext = ( signed portCHAR * ) pcString;
while( *pxNext )
{
xSerialPutChar( pxPort, *pxNext, serNO_BLOCK );
pxNext++;
}
}
/*-----------------------------------------------------------*/
signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime )
{
/* Place the character in the queue of characters to be transmitted. */
if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) != pdPASS )
{
return pdFAIL;
}
/* Turn on the Tx interrupt so the ISR will remove the character from the
queue and send it. This does not need to be in a critical section as
if the interrupt has already removed the character the next interrupt
will simply turn off the Tx interrupt again. */
AT91C_BASE_US0->US_IER = US_TXRDY;
return pdPASS;
}
/*-----------------------------------------------------------*/
void vSerialClose( xComPortHandle xPort )
{
/* Not supported as not required by the demo application. */
}
/*-----------------------------------------------------------*/

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/*
FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
FreeRTOS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with FreeRTOS; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes FreeRTOS, without being obliged to provide
the source code for any proprietary components. See the licensing section
of http://www.FreeRTOS.org for full details of how and when the exception
can be applied.
***************************************************************************
See http://www.FreeRTOS.org for documentation, latest information, license
and contact details. Please ensure to read the configuration and relevant
port sections of the online documentation.
***************************************************************************
*/
/*
BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR USART0.
This file contains all the serial port components that must be compiled
to ARM mode. The components that can be compiled to either ARM or THUMB
mode are contained in serial.c.
*/
/* Standard includes. */
#include <stdlib.h>
/* Scheduler includes. */
#include "FreeRTOS.h"
#include "queue.h"
#include "task.h"
/* Demo application includes. */
#include "serial.h"
#include "AT91R40008.h"
#include "usart.h"
/*-----------------------------------------------------------*/
/* Constant to access the AIC. */
#define serCLEAR_AIC_INTERRUPT ( ( unsigned portLONG ) 0 )
/* Constants to determine the ISR source. */
#define serSOURCE_THRE ( ( unsigned portCHAR ) 0x02 )
#define serSOURCE_RX_TIMEOUT ( ( unsigned portCHAR ) 0x0c )
#define serSOURCE_ERROR ( ( unsigned portCHAR ) 0x06 )
#define serSOURCE_RX ( ( unsigned portCHAR ) 0x04 )
#define serINTERRUPT_SOURCE_MASK ( ( unsigned portLONG ) (US_RXRDY | US_TXRDY | US_RXBRK | US_OVRE | US_FRAME | US_PARE) )
/* Queues used to hold received characters, and characters waiting to be
transmitted. */
static xQueueHandle xRxedChars;
static xQueueHandle xCharsForTx;
/*-----------------------------------------------------------*/
/* UART0 interrupt service routine. This can cause a context switch so MUST
be declared "naked". */
void vUART_ISR( void ) __attribute__ ((naked));
/*-----------------------------------------------------------*/
void vSerialISRCreateQueues( unsigned portBASE_TYPE uxQueueLength, xQueueHandle *pxRxedChars, xQueueHandle *pxCharsForTx )
{
/* Create the queues used to hold Rx and Tx characters. */
xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );
xCharsForTx = xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );
/* Pass back a reference to the queues so the serial API file can
post/receive characters. */
*pxRxedChars = xRxedChars;
*pxCharsForTx = xCharsForTx;
}
/*-----------------------------------------------------------*/
void vUART_ISR( void )
{
/* This ISR can cause a context switch, so the first statement must be a
call to the portENTER_SWITCHING_ISR() macro. This must be BEFORE any
variable declarations. */
portENTER_SWITCHING_ISR();
/* Now we can declare the local variables. */
signed portCHAR cChar;
portBASE_TYPE xTaskWokenByTx = pdFALSE, xTaskWokenByRx = pdFALSE;
unsigned portLONG ulStatus;
/* What caused the interrupt? */
ulStatus = AT91C_BASE_US0->US_CSR & AT91C_BASE_US0->US_IMR;
if (ulStatus & US_TXRDY)
{
/* The interrupt was caused by the THR becoming empty. Are there any
more characters to transmit? */
if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xTaskWokenByTx ) == pdTRUE )
{
/* A character was retrieved from the queue so can be sent to the
THR now. */
AT91C_BASE_US0->US_THR = cChar;
}
else
{
/* Queue empty, nothing to send so turn off the Tx interrupt. */
AT91C_BASE_US0->US_IDR = US_TXRDY;
}
}
if (ulStatus & US_RXRDY)
{
/* The interrupt was caused by the receiver getting data. */
cChar = AT91C_BASE_US0->US_RHR;
if (xQueueSendFromISR(xRxedChars, &cChar, pdFALSE))
{
xTaskWokenByRx = pdTRUE;
}
}
// Acknowledge the interrupt at AIC level...
AT91C_BASE_AIC->AIC_EOICR = serCLEAR_AIC_INTERRUPT;
/* Exit the ISR. If a task was woken by either a character being received
or transmitted then a context switch will occur. */
portEXIT_SWITCHING_ISR( ( xTaskWokenByTx || xTaskWokenByRx ) );
}
/*-----------------------------------------------------------*/

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//*----------------------------------------------------------------------------
//* ATMEL Microcontroller Software Support - ROUSSET -
//*----------------------------------------------------------------------------
//* The software is delivered "AS IS" without warranty or condition of any
//* kind, either express, implied or statutory. This includes without
//* limitation any warranty or condition with respect to merchantability or
//* fitness for any particular purpose, or against the infringements of
//* intellectual property rights of others.
//*-----------------------------------------------------------------------------
//* File Name : tc.h
//* Object : Timer Counter Header File
//*
//* 1.0 01/04/00 JCZ : Creation
//* 1.0 01/09/00 JPP : modification TC_BEEVT, TC_BEEVT_SET_OUTPUT,
//* TC_BEEVT_CLEAR_OUTPUT, TC_BEEVT_TOGGLE_OUTPUT
//*-----------------------------------------------------------------------------
#ifndef tc_h
#define tc_h
//#include "periph/stdc/std_c.h"
//#include "periph/pio/lib_pio.h"
/*-------------------------------------------*/
/* Timer User Interface Structure Definition */
/*-------------------------------------------*/
typedef struct
{
at91_reg TC_CCR ; /* Control Register */
at91_reg TC_CMR ; /* Mode Register */
at91_reg Reserved0 ;
at91_reg Reserved1 ;
at91_reg TC_CV ; /* Counter value */
at91_reg TC_RA ; /* Register A */
at91_reg TC_RB ; /* Register B */
at91_reg TC_RC ; /* Register C */
at91_reg TC_SR ; /* Status Register */
at91_reg TC_IER ; /* Interrupt Enable Register */
at91_reg TC_IDR ; /* Interrupt Disable Register */
at91_reg TC_IMR ; /* Interrupt Mask Register */
at91_reg Reserved2 ;
at91_reg Reserved3 ;
at91_reg Reserved4 ;
at91_reg Reserved5 ;
} StructTC ;
#define NB_TC_CHANNEL 3
typedef struct
{
StructTC TC[NB_TC_CHANNEL] ;
at91_reg TC_BCR ; /* Block Control Register */
at91_reg TC_BMR ; /* Block Mode Register */
} StructTCBlock ;
/*--------------------------------------------------------*/
/* TC_CCR: Timer Counter Control Register Bits Definition */
/*--------------------------------------------------------*/
#define TC_CLKEN 0x1
#define TC_CLKDIS 0x2
#define TC_SWTRG 0x4
/*---------------------------------------------------------------*/
/* TC_CMR: Timer Counter Channel Mode Register Bits Definition */
/*---------------------------------------------------------------*/
/*-----------------*/
/* Clock Selection */
/*-----------------*/
#define TC_CLKS 0x7
#define TC_CLKS_MCK2 0x0
#define TC_CLKS_MCK8 0x1
#define TC_CLKS_MCK32 0x2
#define TC_CLKS_MCK128 0x3
#define TC_CLKS_MCK1024 0x4
#define TC_CLKS_SLCK 0x4
#define TC_CLKS_XC0 0x5
#define TC_CLKS_XC1 0x6
#define TC_CLKS_XC2 0x7
/*-----------------*/
/* Clock Inversion */
/*-----------------*/
#define TC_CLKI 0x8
/*------------------------*/
/* Burst Signal Selection */
/*------------------------*/
#define TC_BURST 0x30
#define TC_BURST_NONE 0x0
#define TC_BUSRT_XC0 0x10
#define TC_BURST_XC1 0x20
#define TC_BURST_XC2 0x30
/*------------------------------------------------------*/
/* Capture Mode : Counter Clock Stopped with RB Loading */
/*------------------------------------------------------*/
#define TC_LDBSTOP 0x40
/*-------------------------------------------------------*/
/* Waveform Mode : Counter Clock Stopped with RC Compare */
/*-------------------------------------------------------*/
#define TC_CPCSTOP 0x40
/*-------------------------------------------------------*/
/* Capture Mode : Counter Clock Disabled with RB Loading */
/*--------------------------------------------------------*/
#define TC_LDBDIS 0x80
/*--------------------------------------------------------*/
/* Waveform Mode : Counter Clock Disabled with RC Compare */
/*--------------------------------------------------------*/
#define TC_CPCDIS 0x80
/*------------------------------------------------*/
/* Capture Mode : External Trigger Edge Selection */
/*------------------------------------------------*/
#define TC_ETRGEDG 0x300
#define TC_ETRGEDG_EDGE_NONE 0x0
#define TC_ETRGEDG_RISING_EDGE 0x100
#define TC_ETRGEDG_FALLING_EDGE 0x200
#define TC_ETRGEDG_BOTH_EDGE 0x300
/*-----------------------------------------------*/
/* Waveform Mode : External Event Edge Selection */
/*-----------------------------------------------*/
#define TC_EEVTEDG 0x300
#define TC_EEVTEDG_EDGE_NONE 0x0
#define TC_EEVTEDG_RISING_EDGE 0x100
#define TC_EEVTEDG_FALLING_EDGE 0x200
#define TC_EEVTEDG_BOTH_EDGE 0x300
/*--------------------------------------------------------*/
/* Capture Mode : TIOA or TIOB External Trigger Selection */
/*--------------------------------------------------------*/
#define TC_ABETRG 0x400
#define TC_ABETRG_TIOB 0x0
#define TC_ABETRG_TIOA 0x400
/*------------------------------------------*/
/* Waveform Mode : External Event Selection */
/*------------------------------------------*/
#define TC_EEVT 0xC00
#define TC_EEVT_TIOB 0x0
#define TC_EEVT_XC0 0x400
#define TC_EEVT_XC1 0x800
#define TC_EEVT_XC2 0xC00
/*--------------------------------------------------*/
/* Waveform Mode : Enable Trigger on External Event */
/*--------------------------------------------------*/
#define TC_ENETRG 0x1000
/*----------------------------------*/
/* RC Compare Enable Trigger Enable */
/*----------------------------------*/
#define TC_CPCTRG 0x4000
/*----------------*/
/* Mode Selection */
/*----------------*/
#define TC_WAVE 0x8000
#define TC_CAPT 0x0
/*-------------------------------------*/
/* Capture Mode : RA Loading Selection */
/*-------------------------------------*/
#define TC_LDRA 0x30000
#define TC_LDRA_EDGE_NONE 0x0
#define TC_LDRA_RISING_EDGE 0x10000
#define TC_LDRA_FALLING_EDGE 0x20000
#define TC_LDRA_BOTH_EDGE 0x30000
/*-------------------------------------------*/
/* Waveform Mode : RA Compare Effect on TIOA */
/*-------------------------------------------*/
#define TC_ACPA 0x30000
#define TC_ACPA_OUTPUT_NONE 0x0
#define TC_ACPA_SET_OUTPUT 0x10000
#define TC_ACPA_CLEAR_OUTPUT 0x20000
#define TC_ACPA_TOGGLE_OUTPUT 0x30000
/*-------------------------------------*/
/* Capture Mode : RB Loading Selection */
/*-------------------------------------*/
#define TC_LDRB 0xC0000
#define TC_LDRB_EDGE_NONE 0x0
#define TC_LDRB_RISING_EDGE 0x40000
#define TC_LDRB_FALLING_EDGE 0x80000
#define TC_LDRB_BOTH_EDGE 0xC0000
/*-------------------------------------------*/
/* Waveform Mode : RC Compare Effect on TIOA */
/*-------------------------------------------*/
#define TC_ACPC 0xC0000
#define TC_ACPC_OUTPUT_NONE 0x0
#define TC_ACPC_SET_OUTPUT 0x40000
#define TC_ACPC_CLEAR_OUTPUT 0x80000
#define TC_ACPC_TOGGLE_OUTPUT 0xC0000
/*-----------------------------------------------*/
/* Waveform Mode : External Event Effect on TIOA */
/*-----------------------------------------------*/
#define TC_AEEVT 0x300000
#define TC_AEEVT_OUTPUT_NONE 0x0
#define TC_AEEVT_SET_OUTPUT 0x100000
#define TC_AEEVT_CLEAR_OUTPUT 0x200000
#define TC_AEEVT_TOGGLE_OUTPUT 0x300000
/*-------------------------------------------------*/
/* Waveform Mode : Software Trigger Effect on TIOA */
/*-------------------------------------------------*/
#define TC_ASWTRG 0xC00000
#define TC_ASWTRG_OUTPUT_NONE 0x0
#define TC_ASWTRG_SET_OUTPUT 0x400000
#define TC_ASWTRG_CLEAR_OUTPUT 0x800000
#define TC_ASWTRG_TOGGLE_OUTPUT 0xC00000
/*-------------------------------------------*/
/* Waveform Mode : RB Compare Effect on TIOB */
/*-------------------------------------------*/
#define TC_BCPB 0x1000000
#define TC_BCPB_OUTPUT_NONE 0x0
#define TC_BCPB_SET_OUTPUT 0x1000000
#define TC_BCPB_CLEAR_OUTPUT 0x2000000
#define TC_BCPB_TOGGLE_OUTPUT 0x3000000
/*-------------------------------------------*/
/* Waveform Mode : RC Compare Effect on TIOB */
/*-------------------------------------------*/
#define TC_BCPC 0xC000000
#define TC_BCPC_OUTPUT_NONE 0x0
#define TC_BCPC_SET_OUTPUT 0x4000000
#define TC_BCPC_CLEAR_OUTPUT 0x8000000
#define TC_BCPC_TOGGLE_OUTPUT 0xC000000
/*-----------------------------------------------*/
/* Waveform Mode : External Event Effect on TIOB */
/*-----------------------------------------------*/
#define TC_BEEVT 0x30000000 //* bit 29-28
#define TC_BEEVT_OUTPUT_NONE 0x0
#define TC_BEEVT_SET_OUTPUT 0x10000000 //* bit 29-28 01
#define TC_BEEVT_CLEAR_OUTPUT 0x20000000 //* bit 29-28 10
#define TC_BEEVT_TOGGLE_OUTPUT 0x30000000 //* bit 29-28 11
/*- -----------------------------------------------*/
/* Waveform Mode : Software Trigger Effect on TIOB */
/*-------------------------------------------------*/
#define TC_BSWTRG 0xC0000000
#define TC_BSWTRG_OUTPUT_NONE 0x0
#define TC_BSWTRG_SET_OUTPUT 0x40000000
#define TC_BSWTRG_CLEAR_OUTPUT 0x80000000
#define TC_BSWTRG_TOGGLE_OUTPUT 0xC0000000
/*------------------------------------------------------*/
/* TC_SR: Timer Counter Status Register Bits Definition */
/*------------------------------------------------------*/
#define TC_COVFS 0x1 /* Counter Overflow Status */
#define TC_LOVRS 0x2 /* Load Overrun Status */
#define TC_CPAS 0x4 /* RA Compare Status */
#define TC_CPBS 0x8 /* RB Compare Status */
#define TC_CPCS 0x10 /* RC Compare Status */
#define TC_LDRAS 0x20 /* RA Loading Status */
#define TC_LDRBS 0x40 /* RB Loading Status */
#define TC_ETRGS 0x80 /* External Trigger Status */
#define TC_CLKSTA 0x10000 /* Clock Status */
#define TC_MTIOA 0x20000 /* TIOA Mirror */
#define TC_MTIOB 0x40000 /* TIOB Status */
/*--------------------------------------------------------------*/
/* TC_BCR: Timer Counter Block Control Register Bits Definition */
/*--------------------------------------------------------------*/
#define TC_SYNC 0x1 /* Synchronisation Trigger */
/*------------------------------------------------------------*/
/* TC_BMR: Timer Counter Block Mode Register Bits Definition */
/*------------------------------------------------------------*/
#define TC_TC0XC0S 0x3 /* External Clock Signal 0 Selection */
#define TC_TCLK0XC0 0x0
#define TC_NONEXC0 0x1
#define TC_TIOA1XC0 0x2
#define TC_TIOA2XC0 0x3
#define TC_TC1XC1S 0xC /* External Clock Signal 1 Selection */
#define TC_TCLK1XC1 0x0
#define TC_NONEXC1 0x4
#define TC_TIOA0XC1 0x8
#define TC_TIOA2XC1 0xC
#define TC_TC2XC2S 0x30 /* External Clock Signal 2 Selection */
#define TC_TCLK2XC2 0x0
#define TC_NONEXC2 0x10
#define TC_TIOA0XC2 0x20
#define TC_TIOA1XC2 0x30
#endif /* tc_h */

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//*----------------------------------------------------------------------------
//* ATMEL Microcontroller Software Support - ROUSSET -
//*----------------------------------------------------------------------------
//* The software is delivered "AS IS" without warranty or condition of any
//* kind, either express, implied or statutory. This includes without
//* limitation any warranty or condition with respect to merchantability or
//* fitness for any particular purpose, or against the infringements of
//* intellectual property rights of others.
//*-----------------------------------------------------------------------------
//* File Name : usart.h
//* Object : USART Header File.
//*
//* 1.0 01/04/00 JCZ : Creation
//*----------------------------------------------------------------------------
#ifndef usart_h
#define usart_h
//#include "periph/stdc/std_c.h"
//#include "periph/pio/lib_pio.h"
/*-------------------------------------------*/
/* USART User Interface Structure Definition */
/*-------------------------------------------*/
typedef struct
{
at91_reg US_CR ; /* Control Register */
at91_reg US_MR ; /* Mode Register */
at91_reg US_IER ; /* Interrupt Enable Register */
at91_reg US_IDR ; /* Interrupt Disable Register */
at91_reg US_IMR ; /* Interrupt Mask Register */
at91_reg US_CSR ; /* Channel Status Register */
at91_reg US_RHR ; /* Receive Holding Register */
at91_reg US_THR ; /* Transmit Holding Register */
at91_reg US_BRGR ; /* Baud Rate Generator Register */
at91_reg US_RTOR ; /* Receiver Timeout Register */
at91_reg US_TTGR ; /* Transmitter Time-guard Register */
at91_reg Reserved ;
at91_reg US_RPR ; /* Receiver Pointer Register */
at91_reg US_RCR ; /* Receiver Counter Register */
at91_reg US_TPR ; /* Transmitter Pointer Register */
at91_reg US_TCR ; /* Transmitter Counter Register */
} StructUSART ;
/*--------------------------*/
/* US_CR : Control Register */
/*--------------------------*/
#define US_RSTRX 0x0004 /* Reset Receiver */
#define US_RSTTX 0x0008 /* Reset Transmitter */
#define US_RXEN 0x0010 /* Receiver Enable */
#define US_RXDIS 0x0020 /* Receiver Disable */
#define US_TXEN 0x0040 /* Transmitter Enable */
#define US_TXDIS 0x0080 /* Transmitter Disable */
#define US_RSTSTA 0x0100 /* Reset Status Bits */
#define US_STTBRK 0x0200 /* Start Break */
#define US_STPBRK 0x0400 /* Stop Break */
#define US_STTTO 0x0800 /* Start Time-out */
#define US_SENDA 0x1000 /* Send Address */
/*-----------------------*/
/* US_MR : Mode Register */
/*-----------------------*/
#define US_CLKS 0x0030 /* Clock Selection */
#define US_CLKS_MCK 0x00 /* Master Clock */
#define US_CLKS_MCK8 0x10 /* Master Clock divided by 8 */
#define US_CLKS_SCK 0x20 /* External Clock */
#define US_CLKS_SLCK 0x30 /* Slow Clock */
#define US_CHRL 0x00C0 /* Byte Length */
#define US_CHRL_5 0x00 /* 5 bits */
#define US_CHRL_6 0x40 /* 6 bits */
#define US_CHRL_7 0x80 /* 7 bits */
#define US_CHRL_8 0xC0 /* 8 bits */
#define US_SYNC 0x0100 /* Synchronous Mode Enable */
#define US_PAR 0x0E00 /* Parity Mode */
#define US_PAR_EVEN 0x00 /* Even Parity */
#define US_PAR_ODD 0x200 /* Odd Parity */
#define US_PAR_SPACE 0x400 /* Space Parity to 0 */
#define US_PAR_MARK 0x600 /* Marked Parity to 1 */
#define US_PAR_NO 0x800 /* No Parity */
#define US_PAR_MULTIDROP 0xC00 /* Multi-drop Mode */
#define US_NBSTOP 0x3000 /* Stop Bit Number */
#define US_NBSTOP_1 0x0000 /* 1 Stop Bit */
#define US_NBSTOP_1_5 0x1000 /* 1.5 Stop Bits */
#define US_NBSTOP_2 0x2000 /* 2 Stop Bits */
#define US_CHMODE 0xC000 /* Channel Mode */
#define US_CHMODE_NORMAL 0x0000 /* Normal Mode */
#define US_CHMODE_AUTOMATIC_ECHO 0x4000 /* Automatic Echo */
#define US_CHMODE_LOCAL_LOOPBACK 0x8000 /* Local Loopback */
#define US_CHMODE_REMOTE_LOOPBACK 0xC000 /* Remote Loopback */
#define US_MODE9 0x20000 /* 9 Bit Mode */
#define US_CLKO 0x40000 /* Baud Rate Output Enable */
/* Mode Register model */
/* Standard Asynchronous Mode : 8 bits , 1 stop , no parity */
#define US_ASYNC_MODE ( US_CHMODE_NORMAL + \
US_NBSTOP_1 + \
US_PAR_NO + \
US_CHRL_8 + \
US_CLKS_MCK )
/* Standard External Asynchronous Mode : 8 bits , 1 stop , no parity */
#define US_ASYNC_SCK_MODE ( US_CHMODE_NORMAL + \
US_NBSTOP_1 + \
US_PAR_NO + \
US_CHRL_8 + \
US_CLKS_SCK )
/* Standard Synchronous Mode : 8 bits , 1 stop , no parity */
#define US_SYNC_MODE ( US_SYNC + \
US_CHMODE_NORMAL + \
US_NBSTOP_1 + \
US_PAR_NO + \
US_CHRL_8 + \
US_CLKS_MCK )
/* SCK used Label */
#define SCK_USED (US_CLKO | US_CLKS_SCK)
/*---------------------------------------------------------------*/
/* US_IER, US_IDR, US_IMR, US_IMR: Status and Interrupt Register */
/*---------------------------------------------------------------*/
#define US_RXRDY 0x1 /* Receiver Ready */
#define US_TXRDY 0x2 /* Transmitter Ready */
#define US_RXBRK 0x4 /* Receiver Break */
#define US_ENDRX 0x8 /* End of Receiver PDC Transfer */
#define US_ENDTX 0x10 /* End of Transmitter PDC Transfer */
#define US_OVRE 0x20 /* Overrun Error */
#define US_FRAME 0x40 /* Framing Error */
#define US_PARE 0x80 /* Parity Error */
#define US_TIMEOUT 0x100 /* Receiver Timeout */
#define US_TXEMPTY 0x200 /* Transmitter Empty */
#define US_MASK_IRQ_TX (US_TXRDY | US_ENDTX | US_TXEMPTY)
#define US_MASK_IRQ_RX (US_RXRDY | US_ENDRX | US_TIMEOUT)
#define US_MASK_IRQ_ERROR (US_PARE | US_FRAME | US_OVRE | US_RXBRK)
#endif /* usart_h */

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/*
FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
FreeRTOS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with FreeRTOS; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes FreeRTOS, without being obliged to provide
the source code for any proprietary components. See the licensing section
of http://www.FreeRTOS.org for full details of how and when the exception
can be applied.
***************************************************************************
See http://www.FreeRTOS.org for documentation, latest information, license
and contact details. Please ensure to read the configuration and relevant
port sections of the online documentation.
***************************************************************************
*/
#ifndef FREERTOS_CONFIG_H
#define FREERTOS_CONFIG_H
#include <intrinsic.h>
#include "board.h"
/*-----------------------------------------------------------
* Application specific definitions.
*
* These definitions should be adjusted for your particular hardware and
* application requirements.
*
* THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
* FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
*----------------------------------------------------------*/
#define configUSE_PREEMPTION 1
#define configUSE_IDLE_HOOK 0
#define configUSE_TICK_HOOK 0
#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 47923200 )
#define configTICK_RATE_HZ ( ( portTickType ) 1000 )
#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 )
#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 100 )
#define configTOTAL_HEAP_SIZE ( ( size_t ) 14200 )
#define configMAX_TASK_NAME_LEN ( 16 )
#define configUSE_TRACE_FACILITY 0
#define configUSE_16_BIT_TICKS 0
#define configIDLE_SHOULD_YIELD 1
/* Co-routine definitions. */
#define configUSE_CO_ROUTINES 0
#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
/* Set the following definitions to 1 to include the API function, or zero
to exclude the API function. */
#define INCLUDE_vTaskPrioritySet 1
#define INCLUDE_uxTaskPriorityGet 1
#define INCLUDE_vTaskDelete 0
#define INCLUDE_vTaskCleanUpResources 0
#define INCLUDE_vTaskSuspend 1
#define INCLUDE_vTaskDelayUntil 1
#define INCLUDE_vTaskDelay 1
#endif /* FREERTOS_CONFIG_H */

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/*
FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
FreeRTOS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with FreeRTOS; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes FreeRTOS, without being obliged to provide
the source code for any proprietary components. See the licensing section
of http://www.FreeRTOS.org for full details of how and when the exception
can be applied.
***************************************************************************
See http://www.FreeRTOS.org for documentation, latest information, license
and contact details. Please ensure to read the configuration and relevant
port sections of the online documentation.
***************************************************************************
*/
#include "FreeRTOS.h"
#include "partest.h"
#include "board.h"
/*-----------------------------------------------------------
* Simple parallel port IO routines for the LED's.
*-----------------------------------------------------------*/
const unsigned portLONG led_mask[ NB_LED ]= { LED1, LED2, LED3, LED4 };
void vParTestInitialise( void )
{
/* Start with all LED's off. */
AT91F_PIO_SetOutput( AT91C_BASE_PIOA, LED_MASK );
}
/*-----------------------------------------------------------*/
void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue )
{
if( uxLED < ( portBASE_TYPE ) NB_LED )
{
if( xValue )
{
AT91F_PIO_SetOutput( AT91C_BASE_PIOA, led_mask[ uxLED ] );
}
else
{
AT91F_PIO_ClearOutput( AT91C_BASE_PIOA, led_mask[ uxLED ]);
}
}
}
/*-----------------------------------------------------------*/
void vParTestToggleLED( unsigned portBASE_TYPE uxLED )
{
if( uxLED < ( portBASE_TYPE ) NB_LED )
{
if( AT91F_PIO_GetInput( AT91C_BASE_PIOA ) & led_mask[ uxLED ] )
{
AT91F_PIO_ClearOutput( AT91C_BASE_PIOA, led_mask[ uxLED ]);
}
else
{
AT91F_PIO_SetOutput( AT91C_BASE_PIOA, led_mask[ uxLED ] );
}
}
}

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/*----------------------------------------------------------------------------
* ATMEL Microcontroller Software Support - ROUSSET -
*----------------------------------------------------------------------------
* The software is delivered "AS IS" without warranty or condition of any
* kind, either express, implied or statutory. This includes without
* limitation any warranty or condition with respect to merchantability or
* fitness for any particular purpose, or against the infringements of
* intellectual property rights of others.
*----------------------------------------------------------------------------
* File Name : Board.h
* Object : AT91SAM7S Evaluation Board Features Definition File.
*
* Creation : JPP 16/Jun/2004
*----------------------------------------------------------------------------
*/
#ifndef Board_h
#define Board_h
#include "AT91SAM7S64.h"
#define __inline inline
#include "lib_AT91SAM7S64.h"
#define true -1
#define false 0
/*-------------------------------*/
/* SAM7Board Memories Definition */
/*-------------------------------*/
// The AT91SAM7S64 embeds a 16-Kbyte SRAM bank, and 64 K-Byte Flash
#define INT_SARM 0x00200000
#define INT_SARM_REMAP 0x00000000
#define INT_FLASH 0x00000000
#define INT_FLASH_REMAP 0x01000000
#define FLASH_PAGE_NB 512
#define FLASH_PAGE_SIZE 128
/*-----------------*/
/* Leds Definition */
/*-----------------*/
/* PIO Flash PA PB PIN */
#define LED1 (1<<0) /* PA0 / PGMEN0 & PWM0 TIOA0 48 */
#define LED2 (1<<1) /* PA1 / PGMEN1 & PWM1 TIOB0 47 */
#define LED3 (1<<2) /* PA2 & PWM2 SCK0 44 */
#define LED4 (1<<3) /* PA3 & TWD NPCS3 43 */
#define NB_LED 4
#define LED_MASK (LED1|LED2|LED3|LED4)
/*-------------------------*/
/* Push Buttons Definition */
/*-------------------------*/
/* PIO Flash PA PB PIN */
#define SW1_MASK (1<<19) /* PA19 / PGMD7 & RK FIQ 13 */
#define SW2_MASK (1<<20) /* PA20 / PGMD8 & RF IRQ0 16 */
#define SW3_MASK (1<<15) /* PA15 / PGM3 & TF TIOA1 20 */
#define SW4_MASK (1<<14) /* PA14 / PGMD2 & SPCK PWM3 21 */
#define SW_MASK (SW1_MASK|SW2_MASK|SW3_MASK|SW4_MASK)
#define SW1 (1<<19) // PA19
#define SW2 (1<<20) // PA20
#define SW3 (1<<15) // PA15
#define SW4 (1<<14) // PA14
/*------------------*/
/* USART Definition */
/*------------------*/
/* SUB-D 9 points J3 DBGU*/
#define DBGU_RXD AT91C_PA9_DRXD /* JP11 must be close */
#define DBGU_TXD AT91C_PA10_DTXD /* JP12 must be close */
#define AT91C_DBGU_BAUD 115200 // Baud rate
#define US_RXD_PIN AT91C_PA5_RXD0 /* JP9 must be close */
#define US_TXD_PIN AT91C_PA6_TXD0 /* JP7 must be close */
#define US_RTS_PIN AT91C_PA7_RTS0 /* JP8 must be close */
#define US_CTS_PIN AT91C_PA8_CTS0 /* JP6 must be close */
/*--------------*/
/* Master Clock */
/*--------------*/
#define EXT_OC 18432000 // Exetrnal ocilator MAINCK
#define MCK 47923200 // MCK (PLLRC div by 2)
#define MCKKHz (MCK/1000) //
#endif /* Board_h */

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;------------------------------------------------------------------------------
;- ATMEL Microcontroller Software Support - ROUSSET -
;------------------------------------------------------------------------------
; The software is delivered "AS IS" without warranty or condition of any
; kind, either express, implied or statutory. This includes without
; limitation any warranty or condition with respect to merchantability or
; fitness for any particular purpose, or against the infringements of
; intellectual property rights of others.
;-----------------------------------------------------------------------------
;- File source : Cstartup.s79
;- Object : Generic CStartup for IAR No Use REMAP
;- Compilation flag : None
;-
;- 1.0 15/Jun/04 JPP : Creation
;------------------------------------------------------------------------------
#include "AT91SAM7S64_inc.h"
;------------------------------------------------------------------------------
;- Area Definition
;------------------------------------------------------------------------------
;---------------------------------------------------------------
; ?RESET
; Reset Vector.
; Normally, segment INTVEC is linked at address 0.
; For debugging purposes, INTVEC may be placed at other
; addresses.
; A debugger that honors the entry point will start the
; program in a normal way even if INTVEC is not at address 0.
;-------------------------------------------------------------
PROGRAM ?RESET
RSEG INTRAMSTART_REMAP
RSEG INTRAMEND_REMAP
EXTERN vPortYieldProcessor
RSEG ICODE:CODE:ROOT(2)
CODE32 ; Always ARM mode after reset
org 0
reset
;------------------------------------------------------------------------------
;- Exception vectors
;--------------------
;- These vectors can be read at address 0 or at RAM address
;- They ABSOLUTELY requires to be in relative addresssing mode in order to
;- guarantee a valid jump. For the moment, all are just looping.
;- If an exception occurs before remap, this would result in an infinite loop.
;- To ensure if a exeption occurs before start application to infinite loop.
;------------------------------------------------------------------------------
B InitReset ; 0x00 Reset handler
undefvec:
B undefvec ; 0x04 Undefined Instruction
swivec:
B vPortYieldProcessor ; 0x08 Software Interrupt
pabtvec:
B pabtvec ; 0x0C Prefetch Abort
dabtvec:
B dabtvec ; 0x10 Data Abort
rsvdvec:
B rsvdvec ; 0x14 reserved
irqvec:
LDR PC, [PC, #-0xF20] ; Jump directly to the address given by the AIC
fiqvec: ; 0x1c FIQ
;------------------------------------------------------------------------------
;- Function : FIQ_Handler_Entry
;- Treatments : FIQ Controller Interrupt Handler.
;- Called Functions : AIC_FVR[interrupt]
;------------------------------------------------------------------------------
FIQ_Handler_Entry:
;- Switch in SVC/User Mode to allow User Stack access for C code
; because the FIQ is not yet acknowledged
;- Save and r0 in FIQ_Register
mov r9,r0
ldr r0 , [r8, #AIC_FVR]
msr CPSR_c,#I_BIT | F_BIT | ARM_MODE_SVC
;- Save scratch/used registers and LR in User Stack
stmfd sp!, { r1-r3, r12, lr}
;- Branch to the routine pointed by the AIC_FVR
mov r14, pc
bx r0
;- Restore scratch/used registers and LR from User Stack
ldmia sp!, { r1-r3, r12, lr}
;- Leave Interrupts disabled and switch back in FIQ mode
msr CPSR_c, #I_BIT | F_BIT | ARM_MODE_FIQ
;- Restore the R0 ARM_MODE_SVC register
mov r0,r9
;- Restore the Program Counter using the LR_fiq directly in the PC
subs pc,lr,#4
InitReset:
;------------------------------------------------------------------------------
;- Low level Init (PMC, AIC, ? ....) by C function AT91F_LowLevelInit
;------------------------------------------------------------------------------
EXTERN AT91F_LowLevelInit
#define __iramend SFB(INTRAMEND_REMAP)
;- minumum C initialization
;- call AT91F_LowLevelInit( void)
ldr r13,=__iramend ; temporary stack in internal RAM
;--Call Low level init function in ABSOLUTE through the Interworking
ldr r0,=AT91F_LowLevelInit
mov lr, pc
bx r0
;------------------------------------------------------------------------------
;- Stack Sizes Definition
;------------------------
;- Interrupt Stack requires 2 words x 8 priority level x 4 bytes when using
;- the vectoring. This assume that the IRQ management.
;- The Interrupt Stack must be adjusted depending on the interrupt handlers.
;- Fast Interrupt not requires stack If in your application it required you must
;- be definehere.
;- The System stack size is not defined and is limited by the free internal
;- SRAM.
;------------------------------------------------------------------------------
;------------------------------------------------------------------------------
;- Top of Stack Definition
;-------------------------
;- Interrupt and Supervisor Stack are located at the top of internal memory in
;- order to speed the exception handling context saving and restoring.
;- ARM_MODE_SVC (Application, C) Stack is located at the top of the external memory.
;------------------------------------------------------------------------------
IRQ_STACK_SIZE EQU 300
ARM_MODE_FIQ EQU 0x11
ARM_MODE_IRQ EQU 0x12
ARM_MODE_SVC EQU 0x13
I_BIT EQU 0x80
F_BIT EQU 0x40
;------------------------------------------------------------------------------
;- Setup the stack for each mode
;-------------------------------
ldr r0, =__iramend
;- Set up Fast Interrupt Mode and set FIQ Mode Stack
msr CPSR_c, #ARM_MODE_FIQ | I_BIT | F_BIT
;- Init the FIQ register
ldr r8, =AT91C_BASE_AIC
;- Set up Interrupt Mode and set IRQ Mode Stack
msr CPSR_c, #ARM_MODE_IRQ | I_BIT | F_BIT
mov r13, r0 ; Init stack IRQ
sub r0, r0, #IRQ_STACK_SIZE
;- Enable interrupt & Set up Supervisor Mode and set Supervisor Mode Stack
msr CPSR_c, #ARM_MODE_SVC
mov r13, r0
;---------------------------------------------------------------
; ?CSTARTUP
;---------------------------------------------------------------
EXTERN __segment_init
EXTERN main
; Initialize segments.
; __segment_init is assumed to use
; instruction set and to be reachable by BL from the ICODE segment
; (it is safest to link them in segment ICODE).
ldr r0,=__segment_init
mov lr, pc
bx r0
PUBLIC __main
?jump_to_main:
ldr lr,=?call_exit
ldr r0,=main
__main:
bx r0
;------------------------------------------------------------------------------
;- Loop for ever
;---------------
;- End of application. Normally, never occur.
;- Could jump on Software Reset ( B 0x0 ).
;------------------------------------------------------------------------------
?call_exit:
End
b End
;---------------------------------------------------------------
; ?EXEPTION_VECTOR
; This module is only linked if needed for closing files.
;---------------------------------------------------------------
PUBLIC AT91F_Default_FIQ_handler
PUBLIC AT91F_Default_IRQ_handler
PUBLIC AT91F_Spurious_handler
CODE32 ; Always ARM mode after exeption
AT91F_Default_FIQ_handler
b AT91F_Default_FIQ_handler
AT91F_Default_IRQ_handler
b AT91F_Default_IRQ_handler
AT91F_Spurious_handler
b AT91F_Spurious_handler
ENDMOD
END

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//*----------------------------------------------------------------------------
//* ATMEL Microcontroller Software Support - ROUSSET -
//*----------------------------------------------------------------------------
//* The software is delivered "AS IS" without warranty or condition of any
//* kind, either express, implied or statutory. This includes without
//* limitation any warranty or condition with respect to merchantability or
//* fitness for any particular purpose, or against the infringements of
//* intellectual property rights of others.
//*----------------------------------------------------------------------------
//* File Name : Cstartup_SAM7.c
//* Object : Low level initializations written in C for IAR
//* tools
//* Creation : 12/Jun/04
//*
//*----------------------------------------------------------------------------
// Include the board file description
#include "Board.h"
// The following functions must be write in ARM mode this function called directly
// by exception vector
extern void AT91F_Spurious_handler(void);
extern void AT91F_Default_IRQ_handler(void);
extern void AT91F_Default_FIQ_handler(void);
//*----------------------------------------------------------------------------
//* \fn AT91F_LowLevelInit
//* \brief This function performs very low level HW initialization
//* this function can be use a Stack, depending the compilation
//* optimization mode
//*----------------------------------------------------------------------------
void AT91F_LowLevelInit( void );
void AT91F_LowLevelInit( void) @ "ICODE"
{
int i;
AT91PS_PMC pPMC = AT91C_BASE_PMC;
//* Set Flash Waite sate
// Single Cycle Access at Up to 30 MHz, or 40
// if MCK = 47923200 I have 50 Cycle for 1 useconde ( flied MC_FMR->FMCN
AT91C_BASE_MC->MC_FMR = ((AT91C_MC_FMCN)&(50 <<16)) | AT91C_MC_FWS_1FWS ;
//* Watchdog Disable
AT91C_BASE_WDTC->WDTC_WDMR= AT91C_SYSC_WDDIS;
//* Set MCK at 47 923 200
// 1 Enabling the Main Oscillator:
// SCK = 1/32768 = 30.51 uSeconde
// Start up time = 8 * 6 / SCK = 56 * 30.51 = 1,46484375 ms
pPMC->PMC_MOR = (( AT91C_CKGR_OSCOUNT & (0x06 <<8) | AT91C_CKGR_MOSCEN ));
// Wait the startup time
while(!(pPMC->PMC_SR & AT91C_PMC_MOSCS));
// 2 Checking the Main Oscillator Frequency (Optional)
// 3 Setting PLL and divider:
// - div by 5 Fin = 3,6864 =(18,432 / 5)
// - Mul 25+1: Fout = 95,8464 =(3,6864 *26)
// for 96 MHz the erroe is 0.16%
// Field out NOT USED = 0
// PLLCOUNT pll startup time esrtimate at : 0.844 ms
// PLLCOUNT 28 = 0.000844 /(1/32768)
pPMC->PMC_PLLR = ((AT91C_CKGR_DIV & 0x05) |
(AT91C_CKGR_PLLCOUNT & (28<<8)) |
(AT91C_CKGR_MUL & (25<<16)));
// Wait the startup time
while(!(pPMC->PMC_SR & AT91C_PMC_LOCK));
// 4. Selection of Master Clock and Processor Clock
// select the PLL clock divided by 2
pPMC->PMC_MCKR = AT91C_PMC_CSS_PLL_CLK | AT91C_PMC_PRES_CLK_2 ;
// Enable User Reset and set its minimal assertion to 960 us
AT91C_BASE_RSTC->RSTC_RMR = AT91C_SYSC_URSTEN | (0x4<<8) | (unsigned int) (0xA5<<24);
// Set up the default interrupts handler vectors
AT91C_BASE_AIC->AIC_SVR[0] = (int) AT91F_Default_FIQ_handler ;
for (i=1;i < 31; i++)
{
AT91C_BASE_AIC->AIC_SVR[i] = (int) AT91F_Default_IRQ_handler ;
}
AT91C_BASE_AIC->AIC_SPU = (int) AT91F_Spurious_handler ;
}

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Demo/ARM7_AT91SAM7S64_IAR/USB/USBSample.c Normal file
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#ifndef USB_DEMO_H
#define USB_DEMO_H
void vUSBDemoTask( void *pvParameters );
#endif

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Demo/ARM7_AT91SAM7S64_IAR/USB/USB_ISR.s79 Normal file
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RSEG ICODE:CODE
CODE32
EXTERN vUSB_ISR
PUBLIC vUSBISREntry
; Wrapper for the USB interrupt service routine. This can cause a
; context switch so requires an assembly wrapper.
; Defines the portSAVE_CONTEXT and portRESTORE_CONTEXT macros.
#include "ISR_Support.h"
vUSBISREntry:
portSAVE_CONTEXT ; Save the context of the current task.
bl vUSB_ISR ; Call the ISR routine.
portRESTORE_CONTEXT ; Restore the context of the current task -
; which may be different to the task that
; was interrupted.
END

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/*
FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
FreeRTOS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with FreeRTOS; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes FreeRTOS, without being obliged to provide
the source code for any proprietary components. See the licensing section
of http://www.FreeRTOS.org for full details of how and when the exception
can be applied.
***************************************************************************
See http://www.FreeRTOS.org for documentation, latest information, license
and contact details. Please ensure to read the configuration and relevant
port sections of the online documentation.
***************************************************************************
*/
/*
NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode.
The processor MUST be in supervisor mode when vTaskStartScheduler is
called. The demo applications included in the FreeRTOS.org download switch
to supervisor mode prior to main being called. If you are not using one of
these demo application projects then ensure Supervisor mode is used.
*/
/*
* Creates all the demo application tasks, then starts the scheduler. The WEB
* documentation provides more details of the demo application tasks. The SAM7
* includes a sample USB that emulates a Joystick input to a USB host.
*
* Main.c also creates a task called "Check". This only executes every three
* seconds but has the highest priority so is guaranteed to get processor time.
* Its main function is to check that all the other tasks are still operational.
* Each task (other than the "flash" tasks) maintains a unique count that is
* incremented each time the task successfully completes its function. Should
* any error occur within such a task the count is permanently halted. The
* check task inspects the count of each task to ensure it has changed since
* the last time the check task executed. If all the count variables have
* changed all the tasks are still executing error free, and the check task
* toggles the onboard LED. Should any task contain an error at any time
* the LED toggle rate will change from 3 seconds to 500ms.
*
*/
/* Standard includes. */
#include <stdlib.h>
/* Scheduler includes. */
#include "FreeRTOS.h"
#include "task.h"
/* Demo application includes. */
#include "flash.h"
#include "integer.h"
#include "PollQ.h"
#include "BlockQ.h"
#include "semtest.h"
#include "dynamic.h"
#include "partest.h"
#include "comtest2.h"
#include "USB/USBSample.h"
/* Priorities for the demo application tasks. */
#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 )
#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 )
#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 4 )
#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 )
#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 )
#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 )
#define mainUSB_PRIORITY ( tskIDLE_PRIORITY + 2 )
/* Constants required by the 'Check' task. */
#define mainNO_ERROR_FLASH_PERIOD ( ( portTickType ) 3000 / portTICK_RATE_MS )
#define mainERROR_FLASH_PERIOD ( ( portTickType ) 500 / portTICK_RATE_MS )
#define mainCHECK_TASK_LED ( 3 )
/* Constants for the ComTest tasks. */
#define mainCOM_TEST_BAUD_RATE ( ( unsigned portLONG ) 115200 )
#define mainCOM_TEST_LED ( 4 ) /* Off the board. */
/*
* The task that executes at the highest priority and calls
* prvCheckOtherTasksAreStillRunning(). See the description at the top
* of the file.
*/
static void vErrorChecks( void *pvParameters );
/*
* Configure the processor for use with the Atmel demo board. Setup is minimal
* as the low level init function (called from the startup asm file) takes care
* of most things.
*/
static void prvSetupHardware( void );
/*
* Checks that all the demo application tasks are still executing without error
* - as described at the top of the file.
*/
static portLONG prvCheckOtherTasksAreStillRunning( void );
/*-----------------------------------------------------------*/
/*
* Starts all the other tasks, then starts the scheduler.
*/
void main( void )
{
/* Setup any hardware that has not already been configured by the low
level init routines. */
prvSetupHardware();
/* Initialise the LED outputs for use by the demo application tasks. */
vParTestInitialise();
/* Start all the standard demo application tasks. */
vStartIntegerMathTasks( tskIDLE_PRIORITY );
vStartLEDFlashTasks( mainLED_TASK_PRIORITY );
vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );
vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );
vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );
vStartDynamicPriorityTasks();
vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED );
/* Also start the USB demo which is just for the SAM7. */
xTaskCreate( vUSBDemoTask, "USB", configMINIMAL_STACK_SIZE, NULL, mainUSB_PRIORITY, NULL );
/* Start the check task - which is defined in this file. */
xTaskCreate( vErrorChecks, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );
/* Start the scheduler.
NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode.
The processor MUST be in supervisor mode when vTaskStartScheduler is
called. The demo applications included in the FreeRTOS.org download switch
to supervisor mode prior to main being called. If you are not using one of
these demo application projects then ensure Supervisor mode is used here. */
vTaskStartScheduler();
/* We should never get here as control is now taken by the scheduler. */
return;
}
/*-----------------------------------------------------------*/
static void prvSetupHardware( void )
{
/* When using the JTAG debugger the hardware is not always initialised to
the correct default state. This line just ensures that this does not
cause all interrupts to be masked at the start. */
AT91C_BASE_AIC->AIC_EOICR = 0;
/* Most setup is performed by the low level init function called from the
startup asm file. */
/* Configure the PIO Lines corresponding to LED1 to LED4 to be outputs as
well as the UART Tx line. */
AT91F_PIO_CfgOutput( AT91C_BASE_PIOA, LED_MASK );
/* Enable the peripheral clock. */
AT91F_PMC_EnablePeriphClock( AT91C_BASE_PMC, 1 << AT91C_ID_PIOA );
}
/*-----------------------------------------------------------*/
static void vErrorChecks( void *pvParameters )
{
portTickType xDelayPeriod = mainNO_ERROR_FLASH_PERIOD;
/* The parameters are not used in this task. */
( void ) pvParameters;
/* Cycle for ever, delaying then checking all the other tasks are still
operating without error. If an error is detected then the delay period
is decreased from mainNO_ERROR_FLASH_PERIOD to mainERROR_FLASH_PERIOD so
the on board LED flash rate will increase. */
for( ;; )
{
/* Delay until it is time to execute again. */
vTaskDelay( xDelayPeriod );
/* Check all the standard demo application tasks are executing without
error. */
if( prvCheckOtherTasksAreStillRunning() != pdPASS )
{
/* An error has been detected in one of the tasks - flash faster. */
xDelayPeriod = mainERROR_FLASH_PERIOD;
}
vParTestToggleLED( mainCHECK_TASK_LED );
}
}
/*-----------------------------------------------------------*/
static portLONG prvCheckOtherTasksAreStillRunning( void )
{
portLONG lReturn = ( portLONG ) pdPASS;
/* Check all the demo tasks (other than the flash tasks) to ensure
that they are all still running, and that none of them have detected
an error. */
if( xAreIntegerMathsTaskStillRunning() != pdTRUE )
{
lReturn = ( portLONG ) pdFAIL;
}
if( xArePollingQueuesStillRunning() != pdTRUE )
{
lReturn = ( portLONG ) pdFAIL;
}
if( xAreSemaphoreTasksStillRunning() != pdTRUE )
{
lReturn = ( portLONG ) pdFAIL;
}
if( xAreBlockingQueuesStillRunning() != pdTRUE )
{
lReturn = ( portLONG ) pdFAIL;
}
if( xAreComTestTasksStillRunning() != pdTRUE )
{
lReturn = ( portLONG ) pdFAIL;
}
if( xAreDynamicPriorityTasksStillRunning() != pdTRUE )
{
lReturn = ( portLONG ) pdFAIL;
}
return lReturn;
}
/*-----------------------------------------------------------*/

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// ---------------------------------------------------------
// ATMEL Microcontroller Software Support - ROUSSET -
// ---------------------------------------------------------
// The software is delivered "AS IS" without warranty or
// condition of any kind, either express, implied or
// statutory. This includes without limitation any warranty
// or condition with respect to merchantability or fitness
// for any particular purpose, or against the infringements of
// intellectual property rights of others.
// ---------------------------------------------------------
// File: SAM7.mac
//
// User setup file for CSPY debugger to simulate interrupt
// driven Fibonacchi data input.
// 1.1 16/Jun/04 JPP : Creation
//
// $Revision: 1.3 $
//
// ---------------------------------------------------------
__var i;
__var pt;
execUserPreload()
{
//* Set the RAM memory at 0x0020 0000 for code AT 0 flash area
CheckRemap();
//* Get the Chip ID (AT91C_DBGU_C1R & AT91C_DBGU_C2R
i=__readMemory32(0xFFFFF240,"Memory");
__message " ---------------------------------------- Chip ID 0x",i:%X;
i=__readMemory32(0xFFFFF244,"Memory");
__message " ---------------------------------------- Extention 0x",i:%X;
//* Get the chip status
//* Init AIC
AIC();
//* Watchdog Disable
Watchdog();
}
//-----------------------------------------------------------------------------
// Watchdog
//-------------------------------
// Normally, the Watchdog is enable at the reset for load it's preferable to
// Disable.
//-----------------------------------------------------------------------------
Watchdog()
{
//* Watchdog Disable
// AT91C_BASE_WDTC->WDTC_WDMR= AT91C_SYSC_WDDIS;
__writeMemory32(0x00008000,0xFFFFFD44,"Memory");
__message "------------------------------- Watchdog Disable ----------------------------------------";
}
//-----------------------------------------------------------------------------
// Check Remap
//-------------
//-----------------------------------------------------------------------------
CheckRemap()
{
//* Read the value at 0x0
i=__readMemory32(0x00000000,"Memory");
i=i+1;
__writeMemory32(i,0x00,"Memory");
pt=__readMemory32(0x00000000,"Memory");
if (i == pt)
{
__message "------------------------------- The Remap is done ----------------------------------------";
//* Toggel RESET The remap
__writeMemory32(0x00000001,0xFFFFFF00,"Memory");
} else {
__message "------------------------------- The Remap is NOT -----------------------------------------";
}
}
execUserSetup()
{
ini();
__message "-------------------------------Set PC ----------------------------------------";
__writeMemory32(0x00000000,0xB4,"Register");
}
//-----------------------------------------------------------------------------
// Reset the Interrupt Controller
//-------------------------------
// Normally, the code is executed only if a reset has been actually performed.
// So, the AIC initialization resumes at setting up the default vectors.
//-----------------------------------------------------------------------------
AIC()
{
// Mask All interrupt pAic->AIC_IDCR = 0xFFFFFFFF;
__writeMemory32(0xFFFFFFFF,0xFFFFF124,"Memory");
for (i=0;i < 8; i++)
{
// AT91C_BASE_AIC->AIC_EOICR
pt = __readMemory32(0xFFFFF130,"Memory");
}
__message "------------------------------- AIC INIT ---------------------------------------------";
}
ini()
{
__writeMemory32(0x0,0x00,"Register");
__writeMemory32(0x0,0x04,"Register");
__writeMemory32(0x0,0x08,"Register");
__writeMemory32(0x0,0x0C,"Register");
__writeMemory32(0x0,0x10,"Register");
__writeMemory32(0x0,0x14,"Register");
__writeMemory32(0x0,0x18,"Register");
__writeMemory32(0x0,0x1C,"Register");
__writeMemory32(0x0,0x20,"Register");
__writeMemory32(0x0,0x24,"Register");
__writeMemory32(0x0,0x28,"Register");
__writeMemory32(0x0,0x2C,"Register");
__writeMemory32(0x0,0x30,"Register");
__writeMemory32(0x0,0x34,"Register");
__writeMemory32(0x0,0x38,"Register");
// Set CPSR
__writeMemory32(0x0D3,0x98,"Register");
}
RG()
{
i=__readMemory32(0x00,"Register"); __message "R00 0x",i:%X;
i=__readMemory32(0x04,"Register"); __message "R01 0x",i:%X;
i=__readMemory32(0x08,"Register"); __message "R02 0x",i:%X;
i=__readMemory32(0x0C,"Register"); __message "R03 0x",i:%X;
i=__readMemory32(0x10,"Register"); __message "R04 0x",i:%X;
i=__readMemory32(0x14,"Register"); __message "R05 0x",i:%X;
i=__readMemory32(0x18,"Register"); __message "R06 0x",i:%X;
i=__readMemory32(0x1C,"Register"); __message "R07 0x",i:%X;
i=__readMemory32(0x20,"Register"); __message "R08 0x",i:%X;
i=__readMemory32(0x24,"Register"); __message "R09 0x",i:%X;
i=__readMemory32(0x28,"Register"); __message "R10 0x",i:%X;
i=__readMemory32(0x2C,"Register"); __message "R11 0x",i:%X;
i=__readMemory32(0x30,"Register"); __message "R12 0x",i:%X;
i=__readMemory32(0x34,"Register"); __message "R13 0x",i:%X;
i=__readMemory32(0x38,"Register"); __message "R14 0x",i:%X;
i=__readMemory32(0x3C,"Register"); __message "R13 SVC 0x",i:%X;
i=__readMemory32(0x40,"Register"); __message "R14 SVC 0x",i:%X;
i=__readMemory32(0x44,"Register"); __message "R13 ABT 0x",i:%X;
i=__readMemory32(0x48,"Register"); __message "R14 ABT 0x",i:%X;
i=__readMemory32(0x4C,"Register"); __message "R13 UND 0x",i:%X;
i=__readMemory32(0x50,"Register"); __message "R14 UND 0x",i:%X;
i=__readMemory32(0x54,"Register"); __message "R13 IRQ 0x",i:%X;
i=__readMemory32(0x58,"Register"); __message "R14 IRQ 0x",i:%X;
i=__readMemory32(0x5C,"Register"); __message "R08 FIQ 0x",i:%X;
i=__readMemory32(0x60,"Register"); __message "R09 FIQ 0x",i:%X;
i=__readMemory32(0x64,"Register"); __message "R10 FIQ 0x",i:%X;
i=__readMemory32(0x68,"Register"); __message "R11 FIQ 0x",i:%X;
i=__readMemory32(0x6C,"Register"); __message "R12 FIQ 0x",i:%X;
i=__readMemory32(0x70,"Register"); __message "R13 FIQ 0x",i:%X;
i=__readMemory32(0x74,"Register"); __message "R14 FIQ0x",i:%X;
i=__readMemory32(0x98,"Register"); __message "CPSR ",i:%X;
i=__readMemory32(0x94,"Register"); __message "SPSR ",i:%X;
i=__readMemory32(0x9C,"Register"); __message "SPSR ABT ",i:%X;
i=__readMemory32(0xA0,"Register"); __message "SPSR ABT ",i:%X;
i=__readMemory32(0xA4,"Register"); __message "SPSR UND ",i:%X;
i=__readMemory32(0xA8,"Register"); __message "SPSR IRQ ",i:%X;
i=__readMemory32(0xAC,"Register"); __message "SPSR FIQ ",i:%X;
i=__readMemory32(0xB4,"Register"); __message "PC 0x",i:%X;
}

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// ---------------------------------------------------------
// ATMEL Microcontroller Software Support - ROUSSET -
// ---------------------------------------------------------
// The software is delivered "AS IS" without warranty or
// condition of any kind, either express, implied or
// statutory. This includes without limitation any warranty
// or condition with respect to merchantability or fitness
// for any particular purpose, or against the infringements of
// intellectual property rights of others.
// ---------------------------------------------------------
// File: SAM7_RAM.mac
//
// User setup file for CSPY debugger to simulate interrupt
// driven Fibonacchi data input.
// 1.1 16/Jun/04 JPP : Creation
// 1.2 27/Aug/04 JPP : PLL setting
//
// $Revision: 1.3 $
//
// ---------------------------------------------------------
__var i;
__var pt;
execUserPreload()
{
//*
PllSetting();
//* Set the RAM memory at 0x0020 0000 for code AT 0 flash area
CheckNoRemap();
//* Get the Chip ID (AT91C_DBGU_C1R & AT91C_DBGU_C2R
i=__readMemory32(0xFFFFF240,"Memory");
__message " ---------------------------------------- Chip ID 0x",i:%X;
i=__readMemory32(0xFFFFF244,"Memory");
__message " ---------------------------------------- Extention 0x",i:%X;
i=__readMemory32(0xFFFFFF6C,"Memory");
__message " ---------------------------------------- Flash Version 0x",i:%X;
//* Get the chip status
//* Init AIC
AIC();
//* Watchdog Disable
Watchdog();
}
//-----------------------------------------------------------------------------
// PllSetting
//-------------------------------
// Set PLL
//-----------------------------------------------------------------------------
PllSetting()
{
// -1- Enabling the Main Oscillator:
//*#define AT91C_PMC_MOR ((AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register
//*#define AT91C_PMC_PLLR ((AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register
//*#define AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register
//*pPMC->PMC_MOR = (( AT91C_CKGR_OSCOUNT & (0x06 <<8) | //0x0000 0600
// AT91C_CKGR_MOSCEN )); //0x0000 0001
__writeMemory32(0x00000601,0xFFFFFC20,"Memory");
// -2- Wait
// -3- Setting PLL and divider:
// - div by 5 Fin = 3,6864 =(18,432 / 5)
// - Mul 25+1: Fout = 95,8464 =(3,6864 *26)
// for 96 MHz the erroe is 0.16%
// Field out NOT USED = 0
// PLLCOUNT pll startup time esrtimate at : 0.844 ms
// PLLCOUNT 28 = 0.000844 /(1/32768)
// pPMC->PMC_PLLR = ((AT91C_CKGR_DIV & 0x05) | //0x0000 0005
// (AT91C_CKGR_PLLCOUNT & (28<<8)) //0x0000 1C00
// (AT91C_CKGR_MUL & (25<<16))); //0x0019 0000
__writeMemory32(0x00191C05,0xFFFFFC2C,"Memory");
// -2- Wait
// -5- Selection of Master Clock and Processor Clock
// select the PLL clock divided by 2
// pPMC->PMC_MCKR = AT91C_PMC_CSS_PLL_CLK | //0x0000 0003
// AT91C_PMC_PRES_CLK_2 ; //0x0000 0004
__writeMemory32(0x00000007,0xFFFFFC30,"Memory");
__message "------------------------------- PLL Enable ----------------------------------------";
}
//-----------------------------------------------------------------------------
// Watchdog
//-------------------------------
// Normally, the Watchdog is enable at the reset for load it's preferable to
// Disable.
//-----------------------------------------------------------------------------
Watchdog()
{
//* Watchdog Disable
// AT91C_BASE_WDTC->WDTC_WDMR= AT91C_SYSC_WDDIS;
__writeMemory32(0x00008000,0xFFFFFD44,"Memory");
__message "------------------------------- Watchdog Disable ----------------------------------------";
}
CheckNoRemap()
{
//* Read the value at 0x0
i=__readMemory32(0x00000000,"Memory");
i=i+1;
__writeMemory32(i,0x00,"Memory");
pt=__readMemory32(0x00000000,"Memory");
if (i == pt)
{
__message "------------------------------- The Remap is done ----------------------------------------";
} else {
__message "------------------------------- The Remap is NOT -----------------------------------------";
//* Toggel RESET The remap
__writeMemory32(0x00000001,0xFFFFFF00,"Memory");
}
}
execUserSetup()
{
ini();
__message "-------------------------------Set PC ----------------------------------------";
__writeMemory32(0x00000000,0xB4,"Register");
}
//-----------------------------------------------------------------------------
// Reset the Interrupt Controller
//-------------------------------
// Normally, the code is executed only if a reset has been actually performed.
// So, the AIC initialization resumes at setting up the default vectors.
//-----------------------------------------------------------------------------
AIC()
{
// Mask All interrupt pAic->AIC_IDCR = 0xFFFFFFFF;
__writeMemory32(0xFFFFFFFF,0xFFFFF124,"Memory");
for (i=0;i < 8; i++)
{
// AT91C_BASE_AIC->AIC_EOICR
pt = __readMemory32(0xFFFFF130,"Memory");
}
__message "------------------------------- AIC INIT ---------------------------------------------";
}
ini()
{
__writeMemory32(0x0,0x00,"Register");
__writeMemory32(0x0,0x04,"Register");
__writeMemory32(0x0,0x08,"Register");
__writeMemory32(0x0,0x0C,"Register");
__writeMemory32(0x0,0x10,"Register");
__writeMemory32(0x0,0x14,"Register");
__writeMemory32(0x0,0x18,"Register");
__writeMemory32(0x0,0x1C,"Register");
__writeMemory32(0x0,0x20,"Register");
__writeMemory32(0x0,0x24,"Register");
__writeMemory32(0x0,0x28,"Register");
__writeMemory32(0x0,0x2C,"Register");
__writeMemory32(0x0,0x30,"Register");
__writeMemory32(0x0,0x34,"Register");
__writeMemory32(0x0,0x38,"Register");
// Set CPSR
__writeMemory32(0x0D3,0x98,"Register");
}
RG()
{
i=__readMemory32(0x00,"Register"); __message "R00 0x",i:%X;
i=__readMemory32(0x04,"Register"); __message "R01 0x",i:%X;
i=__readMemory32(0x08,"Register"); __message "R02 0x",i:%X;
i=__readMemory32(0x0C,"Register"); __message "R03 0x",i:%X;
i=__readMemory32(0x10,"Register"); __message "R04 0x",i:%X;
i=__readMemory32(0x14,"Register"); __message "R05 0x",i:%X;
i=__readMemory32(0x18,"Register"); __message "R06 0x",i:%X;
i=__readMemory32(0x1C,"Register"); __message "R07 0x",i:%X;
i=__readMemory32(0x20,"Register"); __message "R08 0x",i:%X;
i=__readMemory32(0x24,"Register"); __message "R09 0x",i:%X;
i=__readMemory32(0x28,"Register"); __message "R10 0x",i:%X;
i=__readMemory32(0x2C,"Register"); __message "R11 0x",i:%X;
i=__readMemory32(0x30,"Register"); __message "R12 0x",i:%X;
i=__readMemory32(0x34,"Register"); __message "R13 0x",i:%X;
i=__readMemory32(0x38,"Register"); __message "R14 0x",i:%X;
i=__readMemory32(0x3C,"Register"); __message "R13 SVC 0x",i:%X;
i=__readMemory32(0x40,"Register"); __message "R14 SVC 0x",i:%X;
i=__readMemory32(0x44,"Register"); __message "R13 ABT 0x",i:%X;
i=__readMemory32(0x48,"Register"); __message "R14 ABT 0x",i:%X;
i=__readMemory32(0x4C,"Register"); __message "R13 UND 0x",i:%X;
i=__readMemory32(0x50,"Register"); __message "R14 UND 0x",i:%X;
i=__readMemory32(0x54,"Register"); __message "R13 IRQ 0x",i:%X;
i=__readMemory32(0x58,"Register"); __message "R14 IRQ 0x",i:%X;
i=__readMemory32(0x5C,"Register"); __message "R08 FIQ 0x",i:%X;
i=__readMemory32(0x60,"Register"); __message "R09 FIQ 0x",i:%X;
i=__readMemory32(0x64,"Register"); __message "R10 FIQ 0x",i:%X;
i=__readMemory32(0x68,"Register"); __message "R11 FIQ 0x",i:%X;
i=__readMemory32(0x6C,"Register"); __message "R12 FIQ 0x",i:%X;
i=__readMemory32(0x70,"Register"); __message "R13 FIQ 0x",i:%X;
i=__readMemory32(0x74,"Register"); __message "R14 FIQ0x",i:%X;
i=__readMemory32(0x98,"Register"); __message "CPSR ",i:%X;
i=__readMemory32(0x94,"Register"); __message "SPSR ",i:%X;
i=__readMemory32(0x9C,"Register"); __message "SPSR ABT ",i:%X;
i=__readMemory32(0xA0,"Register"); __message "SPSR ABT ",i:%X;
i=__readMemory32(0xA4,"Register"); __message "SPSR UND ",i:%X;
i=__readMemory32(0xA8,"Register"); __message "SPSR IRQ ",i:%X;
i=__readMemory32(0xAC,"Register"); __message "SPSR FIQ ",i:%X;
i=__readMemory32(0xB4,"Register"); __message "PC 0x",i:%X;
}

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// ---------------------------------------------------------
// ATMEL Microcontroller Software Support - ROUSSET -
// ---------------------------------------------------------
// The software is delivered "AS IS" without warranty or
// condition of any kind, either express, implied or
// statutory. This includes without limitation any warranty
// or condition with respect to merchantability or fitness
// for any particular purpose, or against the infringements of
// intellectual property rights of others.
// ---------------------------------------------------------
// File: at91SAM7S64_16KRAM.xlc
//
// 1.1 16/Jun/04 JPP : Creation for 4.11A
//
// $Revision: 1.1.1.1 $
//
// ---------------------------------------------------------
//*************************************************************************
// XLINK command file template for EWARM/ICCARM
//
// Usage: xlink -f lnkarm <your_object_file(s)>
// -s <program start label> <C/C++ runtime library>
//
// $Revision: 1.1.1.1 $
//*************************************************************************
//************************************************
// Inform the linker about the CPU family used.
// AT91SAM7S64 Memory mapping
// No remap
// ROMSTART
// Start address 0x0000 0000
// Size 64 Kbo 0x0001 0000
// RAMSTART
// Start address 0x0020 0000
// Size 16 Kbo 0x0000 4000
// Remap done
// RAMSTART
// Start address 0x0000 0000
// Size 16 Kbo 0x0000 4000
// ROMSTART
// Start address 0x0010 0000
// Size 64 Kbo 0x0001 0000
//************************************************
-carm
//*************************************************************************
// Internal Ram segments mapped AFTER REMAP 16 K.
//*************************************************************************
// Use these addresses for the .
-Z(CONST)INTRAMSTART_REMAP=00000000
-Z(CONST)INTRAMEND_REMAP=00003FFF
//*************************************************************************
// Read-only segments mapped to Flash 64 K.
//*************************************************************************
-DROMSTART=00000000
-DROMEND=0000FFFF
//*************************************************************************
// Read/write segments mapped to RAM.
//*************************************************************************
-DRAMSTART=00000000
-DRAMEND=00003FFF
//************************************************
// Address range for reset and exception
// vectors (INTVEC).
// The vector area is 32 bytes,
// an additional 32 bytes is allocated for the
// constant table used by ldr PC in cstartup.s79.
//************************************************
-Z(CODE)INTVEC=00-3F
//************************************************
// Startup code and exception routines (ICODE).
//************************************************
-Z(CODE)ICODE,DIFUNCT=ROMSTART-ROMEND
-Z(CODE)SWITAB=ROMSTART-ROMEND
//************************************************
// Code segments may be placed anywhere.
//************************************************
-Z(CODE)CODE=ROMSTART-ROMEND
//************************************************
// Various constants and initializers.
//************************************************
-Z(CONST)INITTAB,DATA_ID,DATA_C=ROMSTART-ROMEND
-Z(CONST)CHECKSUM=ROMSTART-ROMEND
//************************************************
// Data segments.
//************************************************
-Z(DATA)DATA_I,DATA_Z,DATA_N=RAMSTART-RAMEND
//************************************************
// __ramfunc code copied to and executed from RAM.
//************************************************
-Z(DATA)CODE_I=RAMSTART-RAMEND
//************************************************
// ICCARM produces code for __ramfunc functions in
// CODE_I segments. The -Q XLINK command line
// option redirects XLINK to emit the code in the
// debug information associated with the CODE_I
// segment, where the code will execute.
//************************************************
//*************************************************************************
// Stack and heap segments.
//*************************************************************************
-D_CSTACK_SIZE=(100*4)
-D_IRQ_STACK_SIZE=(2*8*4)
-Z(DATA)CSTACK+_CSTACK_SIZE=RAMSTART-RAMEND
-Z(DATA)IRQ_STACK+_IRQ_STACK_SIZE=RAMSTART-RAMEND
//*************************************************************************
// ELF/DWARF support.
//
// Uncomment the line "-Felf" below to generate ELF/DWARF output.
// Available format specifiers are:
//
// "-yn": Suppress DWARF debug output
// "-yp": Multiple ELF program sections
// "-yas": Format suitable for debuggers from ARM Ltd (also sets -p flag)
//
// "-Felf" and the format specifiers can also be supplied directly as
// command line options, or selected from the Xlink Output tab in the
// IAR Embedded Workbench.
//*************************************************************************
// -Felf

136
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@ -0,0 +1,136 @@
// ---------------------------------------------------------
// ATMEL Microcontroller Software Support - ROUSSET -
// ---------------------------------------------------------
// The software is delivered "AS IS" without warranty or
// condition of any kind, either express, implied or
// statutory. This includes without limitation any warranty
// or condition with respect to merchantability or fitness
// for any particular purpose, or against the infringements of
// intellectual property rights of others.
// ---------------------------------------------------------
// File: at91SAM7S64_NoRemap.xlc
//
// 1.1 16/Jun/04 JPP : Creation for 4.11A
//
// $Revision: 1.1.1.1 $
//
// ---------------------------------------------------------
//*************************************************************************
// XLINK command file template for EWARM/ICCARM
//
// Usage: xlink -f lnkarm <your_object_file(s)>
// -s <program start label> <C/C++ runtime library>
//
// $Revision: 1.1.1.1 $
//*************************************************************************
//************************************************
// Inform the linker about the CPU family used.
// AT91SAM7S64 Memory mapping
// No remap
// ROMSTART
// Start address 0x0000 0000
// Size 64 Kbo 0x0001 0000
// RAMSTART
// Start address 0x0020 0000
// Size 16 Kbo 0x0000 4000
// Remap done
// RAMSTART
// Start address 0x0000 0000
// Size 16 Kbo 0x0000 4000
// ROMSTART
// Start address 0x0010 0000
// Size 64 Kbo 0x0001 0000
//************************************************
-carm
//*************************************************************************
// Internal Ram segments mapped AFTER REMAP 16 K.
//*************************************************************************
// Use these addresses for the .
-Z(CONST)INTRAMSTART_REMAP=00200000
-Z(CONST)INTRAMEND_REMAP=00203FFF
//*************************************************************************
// Read-only segments mapped to Flash 64 K.
//*************************************************************************
-DROMSTART=00000000
-DROMEND=0000FFFF
//*************************************************************************
// Read/write segments mapped to RAM.
//*************************************************************************
-DRAMSTART=00200000
-DRAMEND=002003FFF
//************************************************
// Address range for reset and exception
// vectors (INTVEC).
// The vector area is 32 bytes,
// an additional 32 bytes is allocated for the
// constant table used by ldr PC in cstartup.s79.
//************************************************
-Z(CODE)INTVEC=00-3F
//************************************************
// Startup code and exception routines (ICODE).
//************************************************
-Z(CODE)ICODE,DIFUNCT=ROMSTART-ROMEND
-Z(CODE)SWITAB=ROMSTART-ROMEND
//************************************************
// Code segments may be placed anywhere.
//************************************************
-Z(CODE)CODE=ROMSTART-ROMEND
//************************************************
// Various constants and initializers.
//************************************************
-Z(CONST)INITTAB,DATA_ID,DATA_C=ROMSTART-ROMEND
-Z(CONST)CHECKSUM=ROMSTART-ROMEND
//************************************************
// Data segments.
//************************************************
-Z(DATA)DATA_I,DATA_Z,DATA_N=RAMSTART-RAMEND
//************************************************
// __ramfunc code copied to and executed from RAM.
//************************************************
-Z(DATA)CODE_I=RAMSTART-RAMEND
//************************************************
// ICCARM produces code for __ramfunc functions in
// CODE_I segments. The -Q XLINK command line
// option redirects XLINK to emit the code in the
// debug information associated with the CODE_I
// segment, where the code will execute.
//************************************************
//*************************************************************************
// Stack and heap segments.
//*************************************************************************
//-D_CSTACK_SIZE=(100*4)
//-D_IRQ_STACK_SIZE=(2*8*4)
//-Z(DATA)CSTACK+_CSTACK_SIZE=RAMSTART-RAMEND
//-Z(DATA)IRQ_STACK+_IRQ_STACK_SIZE=RAMSTART-RAMEND
//*************************************************************************
// ELF/DWARF support.
//
// Uncomment the line "-Felf" below to generate ELF/DWARF output.
// Available format specifiers are:
//
// "-yn": Suppress DWARF debug output
// "-yp": Multiple ELF program sections
// "-yas": Format suitable for debuggers from ARM Ltd (also sets -p flag)
//
// "-Felf" and the format specifiers can also be supplied directly as
// command line options, or selected from the Xlink Output tab in the
// IAR Embedded Workbench.
//*************************************************************************
// -Felf

905
Demo/ARM7_AT91SAM7S64_IAR/rtosdemo.ewd Normal file
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@ -0,0 +1,905 @@
<?xml version="1.0" encoding="iso-8859-1"?>
<project>
<fileVersion>1</fileVersion>
<configuration>
<name>Flash Debug</name>
<toolchain>
<name>ARM</name>
</toolchain>
<debug>1</debug>
<settings>
<name>C-SPY</name>
<archiveVersion>2</archiveVersion>
<data>
<version>13</version>
<wantNonLocal>1</wantNonLocal>
<debug>1</debug>
<option>
<name>CInput</name>
<state>1</state>
</option>
<option>
<name>CEndian</name>
<state>1</state>
</option>
<option>
<name>CProcessor</name>
<state>1</state>
</option>
<option>
<name>OCVariant</name>
<state>0</state>
</option>
<option>
<name>MacOverride</name>
<state>1</state>
</option>
<option>
<name>MacFile</name>
<state>$PROJ_DIR$\resource\SAM7.mac</state>
</option>
<option>
<name>MemOverride</name>
<state>0</state>
</option>
<option>
<name>MemFile</name>
<state>$TOOLKIT_DIR$\CONFIG\ioat91sam7s64.ddf</state>
</option>
<option>
<name>RunToEnable</name>
<state>0</state>
</option>
<option>
<name>RunToName</name>
<state>main</state>
</option>
<option>
<name>CExtraOptionsCheck</name>
<state>0</state>
</option>
<option>
<name>CExtraOptions</name>
<state></state>
</option>
<option>
<name>CFpuProcessor</name>
<state>1</state>
</option>
<option>
<name>OCDDFArgumentProducer</name>
<state></state>
</option>
<option>
<name>OCDownloadSuppressDownload</name>
<state>0</state>
</option>
<option>
<name>OCDownloadVerifyAll</name>
<state>0</state>
</option>
<option>
<name>OCProductVersion</name>
<state>4.10B</state>
</option>
<option>
<name>OCDynDriverList</name>
<state>JLINK_ID</state>
</option>
<option>
<name>OCLastSavedByProductVersion</name>
<state>4.30A</state>
</option>
<option>
<name>OCDownloadAttachToProgram</name>
<state>0</state>
</option>
<option>
<name>FlashLoaders</name>
<state>,,,,(default),</state>
</option>
<option>
<name>UseFlashLoader</name>
<state>1</state>
</option>
</data>
</settings>
<settings>
<name>ARMSIM_ID</name>
<archiveVersion>2</archiveVersion>
<data>
<version>0</version>
<wantNonLocal>1</wantNonLocal>
<debug>1</debug>
<option>
<name>OCSimDriverInfo</name>
<state>1</state>
</option>
</data>
</settings>
<settings>
<name>ANGEL_ID</name>
<archiveVersion>2</archiveVersion>
<data>
<version>0</version>
<wantNonLocal>1</wantNonLocal>
<debug>1</debug>
<option>
<name>CCAngelHeartbeat</name>
<state>1</state>
</option>
<option>
<name>CAngelCommunication</name>
<state>1</state>
</option>
<option>
<name>CAngelCommBaud</name>
<version>0</version>
<state>3</state>
</option>
<option>
<name>CAngelCommPort</name>
<version>0</version>
<state>0</state>
</option>
<option>
<name>ANGELTCPIP</name>
<state>aaa.bbb.ccc.ddd</state>
</option>
<option>
<name>DoAngelLogfile</name>
<state>0</state>
</option>
<option>
<name>AngelLogFile</name>
<state>$TOOLKIT_DIR$\cspycomm.log</state>
</option>
<option>
<name>OCDriverInfo</name>
<state>1</state>
</option>
</data>
</settings>
<settings>
<name>IARROM_ID</name>
<archiveVersion>2</archiveVersion>
<data>
<version>0</version>
<wantNonLocal>1</wantNonLocal>
<debug>1</debug>
<option>
<name>CRomLogFileCheck</name>
<state>0</state>
</option>
<option>
<name>CRomLogFileEditB</name>
<state>$TOOLKIT_DIR$\cspycomm.log</state>
</option>
<option>
<name>CRomCommunication</name>
<state>0</state>
</option>
<option>
<name>CRomCommPort</name>
<version>0</version>
<state>0</state>
</option>
<option>
<name>CRomCommBaud</name>
<version>0</version>
<state>7</state>
</option>
<option>
<name>OCDriverInfo</name>
<state>1</state>
</option>
</data>
</settings>
<settings>
<name>JLINK_ID</name>
<archiveVersion>2</archiveVersion>
<data>
<version>2</version>
<wantNonLocal>1</wantNonLocal>
<debug>1</debug>
<option>
<name>JLinkSpeed</name>
<state>30</state>
</option>
<option>
<name>CCJLinkHWReset</name>
<state>0</state>
</option>
<option>
<name>CCJLinkTRSTReset</name>
<state>0</state>
</option>
<option>
<name>CCJLinkDoLogfile</name>
<state>0</state>
</option>
<option>
<name>CCJLinkLogFile</name>
<state>$TOOLKIT_DIR$\cspycomm.log</state>
</option>
<option>
<name>CCJLinkHWResetDelay</name>
<state></state>
</option>
<option>
<name>CCJLinkSpeedRadio</name>
<state>0</state>
</option>
<option>
<name>OCDriverInfo</name>
<state>1</state>
</option>
<option>
<name>JLinkInitialSpeed</name>
<state>32</state>
</option>
<option>
<name>CCDoJlinkMultiTarget</name>
<state>0</state>
</option>
<option>
<name>CCScanChainNonARMDevices</name>
<state>0</state>
</option>
<option>
<name>CCJLinkMultiTarget</name>
<state>0</state>
</option>
<option>
<name>CCJLinkIRLength</name>
<state>0</state>
</option>
<option>
<name>CCJLinkCommRadio</name>
<state>0</state>
</option>
<option>
<name>CCJLinkTCPIP</name>
<state>aaa.bbb.ccc.ddd</state>
</option>
</data>
</settings>
<settings>
<name>MACRAIGOR_ID</name>
<archiveVersion>2</archiveVersion>
<data>
<version>1</version>
<wantNonLocal>1</wantNonLocal>
<debug>1</debug>
<option>
<name>jtag</name>
<version>0</version>
<state>0</state>
</option>
<option>
<name>EmuSpeed</name>
<state>1</state>
</option>
<option>
<name>TCPIP</name>
<state>aaa.bbb.ccc.ddd</state>
</option>
<option>
<name>DoLogfile</name>
<state>0</state>
</option>
<option>
<name>LogFile</name>
<state>$TOOLKIT_DIR$\cspycomm.log</state>
</option>
<option>
<name>DoEmuMultiTarget</name>
<state>0</state>
</option>
<option>
<name>EmuMultiTarget</name>
<state>0@ARM7TDMI</state>
</option>
<option>
<name>EmuHWReset</name>
<state>0</state>
</option>
<option>
<name>CEmuCommBaud</name>
<version>0</version>
<state>4</state>
</option>
<option>
<name>CEmuCommPort</name>
<version>0</version>
<state>0</state>
</option>
<option>
<name>jtago</name>
<version>0</version>
<state>0</state>
</option>
<option>
<name>OCDriverInfo</name>
<state>1</state>
</option>
<option>
<name>UnusedAddr</name>
<state>0x00800000</state>
</option>
<option>
<name>CCMacraigorHWResetDelay</name>
<state></state>
</option>
</data>
</settings>
<settings>
<name>RDI_ID</name>
<archiveVersion>2</archiveVersion>
<data>
<version>1</version>
<wantNonLocal>1</wantNonLocal>
<debug>1</debug>
<option>
<name>CRDIDriverDll</name>
<state>Browse to your RDI driver</state>
</option>
<option>
<name>CRDILogFileCheck</name>
<state>0</state>
</option>
<option>
<name>CRDILogFileEdit</name>
<state>$TOOLKIT_DIR$\cspycomm.log</state>
</option>
<option>
<name>CCRDIHWReset</name>
<state>0</state>
</option>
<option>
<name>CCRDICatchReset</name>
<state>0</state>
</option>
<option>
<name>CCRDICatchUndef</name>
<state>0</state>
</option>
<option>
<name>CCRDICatchSWI</name>
<state>0</state>
</option>
<option>
<name>CCRDICatchData</name>
<state>0</state>
</option>
<option>
<name>CCRDICatchPrefetch</name>
<state>0</state>
</option>
<option>
<name>CCRDICatchIRQ</name>
<state>0</state>
</option>
<option>
<name>CCRDICatchFIQ</name>
<state>0</state>
</option>
<option>
<name>CCRDIUseETM</name>
<state>0</state>
</option>
<option>
<name>OCDriverInfo</name>
<state>1</state>
</option>
</data>
</settings>
<settings>
<name>THIRDPARTY_ID</name>
<archiveVersion>2</archiveVersion>
<data>
<version>0</version>
<wantNonLocal>1</wantNonLocal>
<debug>1</debug>
<option>
<name>CThirdPartyDriverDll</name>
<state>Browse to your third-party driver</state>
</option>
<option>
<name>CThirdPartyLogFileCheck</name>
<state>0</state>
</option>
<option>
<name>CThirdPartyLogFileEditB</name>
<state>$TOOLKIT_DIR$\cspycomm.log</state>
</option>
<option>
<name>OCDriverInfo</name>
<state>1</state>
</option>
</data>
</settings>
<debuggerPlugins>
<plugin>
<file>$EW_DIR$\common\plugins\CodeCoverage\CodeCoverage.ewplugin</file>
<loadFlag>1</loadFlag>
</plugin>
<plugin>
<file>$EW_DIR$\common\plugins\Orti\Orti.ewplugin</file>
<loadFlag>0</loadFlag>
</plugin>
<plugin>
<file>$EW_DIR$\common\plugins\Profiling\Profiling.ewplugin</file>
<loadFlag>1</loadFlag>
</plugin>
<plugin>
<file>$TOOLKIT_DIR$\plugins\rtos\CMX\CMXArmPlugin.ewplugin</file>
<loadFlag>0</loadFlag>
</plugin>
<plugin>
<file>$TOOLKIT_DIR$\plugins\rtos\CMX\CMXTinyArmPlugin.ewplugin</file>
<loadFlag>0</loadFlag>
</plugin>
<plugin>
<file>$TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ewplugin</file>
<loadFlag>0</loadFlag>
</plugin>
<plugin>
<file>$TOOLKIT_DIR$\plugins\rtos\OSE\OseEpsilonPlugin.ewplugin</file>
<loadFlag>0</loadFlag>
</plugin>
</debuggerPlugins>
</configuration>
<configuration>
<name>Flash Bin</name>
<toolchain>
<name>ARM</name>
</toolchain>
<debug>1</debug>
<settings>
<name>C-SPY</name>
<archiveVersion>2</archiveVersion>
<data>
<version>13</version>
<wantNonLocal>1</wantNonLocal>
<debug>1</debug>
<option>
<name>CInput</name>
<state>1</state>
</option>
<option>
<name>CEndian</name>
<state>1</state>
</option>
<option>
<name>CProcessor</name>
<state>1</state>
</option>
<option>
<name>OCVariant</name>
<state>0</state>
</option>
<option>
<name>MacOverride</name>
<state>1</state>
</option>
<option>
<name>MacFile</name>
<state>$PROJ_DIR$\resource\SAM7.mac</state>
</option>
<option>
<name>MemOverride</name>
<state>0</state>
</option>
<option>
<name>MemFile</name>
<state>$TOOLKIT_DIR$\CONFIG\ioat91sam7s64.ddf</state>
</option>
<option>
<name>RunToEnable</name>
<state>0</state>
</option>
<option>
<name>RunToName</name>
<state>main</state>
</option>
<option>
<name>CExtraOptionsCheck</name>
<state>0</state>
</option>
<option>
<name>CExtraOptions</name>
<state></state>
</option>
<option>
<name>CFpuProcessor</name>
<state>1</state>
</option>
<option>
<name>OCDDFArgumentProducer</name>
<state></state>
</option>
<option>
<name>OCDownloadSuppressDownload</name>
<state>0</state>
</option>
<option>
<name>OCDownloadVerifyAll</name>
<state>0</state>
</option>
<option>
<name>OCProductVersion</name>
<state>4.10B</state>
</option>
<option>
<name>OCDynDriverList</name>
<state>JLINK_ID</state>
</option>
<option>
<name>OCLastSavedByProductVersion</name>
<state>4.30A</state>
</option>
<option>
<name>OCDownloadAttachToProgram</name>
<state>0</state>
</option>
<option>
<name>FlashLoaders</name>
<state>,,,,(default),</state>
</option>
<option>
<name>UseFlashLoader</name>
<state>1</state>
</option>
</data>
</settings>
<settings>
<name>ARMSIM_ID</name>
<archiveVersion>2</archiveVersion>
<data>
<version>0</version>
<wantNonLocal>1</wantNonLocal>
<debug>1</debug>
<option>
<name>OCSimDriverInfo</name>
<state>1</state>
</option>
</data>
</settings>
<settings>
<name>ANGEL_ID</name>
<archiveVersion>2</archiveVersion>
<data>
<version>0</version>
<wantNonLocal>1</wantNonLocal>
<debug>1</debug>
<option>
<name>CCAngelHeartbeat</name>
<state>1</state>
</option>
<option>
<name>CAngelCommunication</name>
<state>1</state>
</option>
<option>
<name>CAngelCommBaud</name>
<version>0</version>
<state>3</state>
</option>
<option>
<name>CAngelCommPort</name>
<version>0</version>
<state>0</state>
</option>
<option>
<name>ANGELTCPIP</name>
<state>aaa.bbb.ccc.ddd</state>
</option>
<option>
<name>DoAngelLogfile</name>
<state>0</state>
</option>
<option>
<name>AngelLogFile</name>
<state>$TOOLKIT_DIR$\cspycomm.log</state>
</option>
<option>
<name>OCDriverInfo</name>
<state>1</state>
</option>
</data>
</settings>
<settings>
<name>IARROM_ID</name>
<archiveVersion>2</archiveVersion>
<data>
<version>0</version>
<wantNonLocal>1</wantNonLocal>
<debug>1</debug>
<option>
<name>CRomLogFileCheck</name>
<state>0</state>
</option>
<option>
<name>CRomLogFileEditB</name>
<state>$TOOLKIT_DIR$\cspycomm.log</state>
</option>
<option>
<name>CRomCommunication</name>
<state>0</state>
</option>
<option>
<name>CRomCommPort</name>
<version>0</version>
<state>0</state>
</option>
<option>
<name>CRomCommBaud</name>
<version>0</version>
<state>7</state>
</option>
<option>
<name>OCDriverInfo</name>
<state>1</state>
</option>
</data>
</settings>
<settings>
<name>JLINK_ID</name>
<archiveVersion>2</archiveVersion>
<data>
<version>2</version>
<wantNonLocal>1</wantNonLocal>
<debug>1</debug>
<option>
<name>JLinkSpeed</name>
<state>30</state>
</option>
<option>
<name>CCJLinkHWReset</name>
<state>0</state>
</option>
<option>
<name>CCJLinkTRSTReset</name>
<state>0</state>
</option>
<option>
<name>CCJLinkDoLogfile</name>
<state>0</state>
</option>
<option>
<name>CCJLinkLogFile</name>
<state>$TOOLKIT_DIR$\cspycomm.log</state>
</option>
<option>
<name>CCJLinkHWResetDelay</name>
<state></state>
</option>
<option>
<name>CCJLinkSpeedRadio</name>
<state>0</state>
</option>
<option>
<name>OCDriverInfo</name>
<state>1</state>
</option>
<option>
<name>JLinkInitialSpeed</name>
<state>32</state>
</option>
<option>
<name>CCDoJlinkMultiTarget</name>
<state>0</state>
</option>
<option>
<name>CCScanChainNonARMDevices</name>
<state>0</state>
</option>
<option>
<name>CCJLinkMultiTarget</name>
<state>0</state>
</option>
<option>
<name>CCJLinkIRLength</name>
<state>0</state>
</option>
<option>
<name>CCJLinkCommRadio</name>
<state>0</state>
</option>
<option>
<name>CCJLinkTCPIP</name>
<state>aaa.bbb.ccc.ddd</state>
</option>
</data>
</settings>
<settings>
<name>MACRAIGOR_ID</name>
<archiveVersion>2</archiveVersion>
<data>
<version>1</version>
<wantNonLocal>1</wantNonLocal>
<debug>1</debug>
<option>
<name>jtag</name>
<version>0</version>
<state>0</state>
</option>
<option>
<name>EmuSpeed</name>
<state>1</state>
</option>
<option>
<name>TCPIP</name>
<state>aaa.bbb.ccc.ddd</state>
</option>
<option>
<name>DoLogfile</name>
<state>0</state>
</option>
<option>
<name>LogFile</name>
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<?xml version="1.0" encoding="iso-8859-1"?>
<workspace>
<project>
<path>$WS_DIR$\rtosdemo.ewp</path>
</project>
<batchBuild/>
</workspace>

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Demo/ARM7_AT91SAM7S64_IAR/serial/serial.c Normal file
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/*
FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
FreeRTOS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with FreeRTOS; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes FreeRTOS, without being obliged to provide
the source code for any proprietary components. See the licensing section
of http://www.FreeRTOS.org for full details of how and when the exception
can be applied.
***************************************************************************
See http://www.FreeRTOS.org for documentation, latest information, license
and contact details. Please ensure to read the configuration and relevant
port sections of the online documentation.
***************************************************************************
*/
/*
BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR UART0.
*/
/* Standard includes. */
#include <stdlib.h>
/* Scheduler includes. */
#include "FreeRTOS.h"
#include "queue.h"
/* Demo application includes. */
#include "serial.h"
/*-----------------------------------------------------------*/
/* Location of the COM0 registers. */
#define serCOM0 ( ( AT91PS_USART ) AT91C_BASE_US0 )
/* Interrupt control macros. */
#define serINTERRUPT_LEVEL ( 5 )
#define vInterruptOn() AT91F_US_EnableIt( serCOM0, AT91C_US_TXRDY | AT91C_US_RXRDY )
#define vInterruptOff() AT91F_US_DisableIt( serCOM0, AT91C_US_TXRDY )
/* Misc constants. */
#define serINVALID_QUEUE ( ( xQueueHandle ) 0 )
#define serHANDLE ( ( xComPortHandle ) 1 )
#define serNO_BLOCK ( ( portTickType ) 0 )
#define serNO_TIMEGUARD ( ( unsigned portLONG ) 0 )
#define serNO_PERIPHERAL_B_SETUP ( ( unsigned portLONG ) 0 )
/* Queues used to hold received characters, and characters waiting to be
transmitted. */
static xQueueHandle xRxedChars;
static xQueueHandle xCharsForTx;
/*-----------------------------------------------------------*/
/* Interrupt entry point written in the assembler file serialISR.s79. */
extern void vSerialISREntry( void );
/* The interrupt service routine - called from the assembly entry point. */
__arm void vSerialISR( void );
/*-----------------------------------------------------------*/
/*
* See the serial2.h header file.
*/
xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength )
{
xComPortHandle xReturn = serHANDLE;
extern void ( vUART_ISR )( void );
/* Create the queues used to hold Rx and Tx characters. */
xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );
xCharsForTx = xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );
/* If the queues were created correctly then setup the serial port
hardware. */
if( ( xRxedChars != serINVALID_QUEUE ) && ( xCharsForTx != serINVALID_QUEUE ) )
{
portENTER_CRITICAL();
{
/* Enable the USART clock. */
AT91F_PMC_EnablePeriphClock( AT91C_BASE_PMC, 1 << AT91C_ID_US0 );
AT91F_PIO_CfgPeriph( AT91C_BASE_PIOA, ( ( unsigned portLONG ) AT91C_PA5_RXD0 ) | ( ( unsigned portLONG ) AT91C_PA6_TXD0 ), serNO_PERIPHERAL_B_SETUP );
/* Set the required protocol. */
AT91F_US_Configure( serCOM0, configCPU_CLOCK_HZ, AT91C_US_ASYNC_MODE, ulWantedBaud, serNO_TIMEGUARD );
/* Enable Rx and Tx. */
serCOM0->US_CR = AT91C_US_RXEN | AT91C_US_TXEN;
/* Enable the Rx interrupts. The Tx interrupts are not enabled
until there are characters to be transmitted. */
AT91F_US_EnableIt( serCOM0, AT91C_US_RXRDY );
/* Enable the interrupts in the AIC. */
AT91F_AIC_ConfigureIt( AT91C_BASE_AIC, AT91C_ID_US0, serINTERRUPT_LEVEL, AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE, ( void (*)( void ) ) vSerialISREntry );
AT91F_AIC_EnableIt( AT91C_BASE_AIC, AT91C_ID_US0 );
}
portEXIT_CRITICAL();
}
else
{
xReturn = ( xComPortHandle ) 0;
}
/* This demo file only supports a single port but we have to return
something to comply with the standard demo header file. */
return xReturn;
}
/*-----------------------------------------------------------*/
signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime )
{
/* The port handle is not required as this driver only supports one port. */
( void ) pxPort;
/* Get the next character from the buffer. Return false if no characters
are available, or arrive before xBlockTime expires. */
if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) )
{
return pdTRUE;
}
else
{
return pdFALSE;
}
}
/*-----------------------------------------------------------*/
void vSerialPutString( xComPortHandle pxPort, const signed portCHAR * const pcString, unsigned portSHORT usStringLength )
{
signed portCHAR *pxNext;
/* A couple of parameters that this port does not use. */
( void ) usStringLength;
( void ) pxPort;
/* NOTE: This implementation does not handle the queue being full as no
block time is used! */
/* The port handle is not required as this driver only supports UART0. */
( void ) pxPort;
/* Send each character in the string, one at a time. */
pxNext = ( signed portCHAR * ) pcString;
while( *pxNext )
{
xSerialPutChar( pxPort, *pxNext, serNO_BLOCK );
pxNext++;
}
}
/*-----------------------------------------------------------*/
signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime )
{
/* Place the character in the queue of characters to be transmitted. */
if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) != pdPASS )
{
return pdFAIL;
}
/* Turn on the Tx interrupt so the ISR will remove the character from the
queue and send it. This does not need to be in a critical section as
if the interrupt has already removed the character the next interrupt
will simply turn off the Tx interrupt again. */
vInterruptOn();
return pdPASS;
}
/*-----------------------------------------------------------*/
void vSerialClose( xComPortHandle xPort )
{
/* Not supported as not required by the demo application. */
}
/*-----------------------------------------------------------*/
/* Serial port ISR. This can cause a context switch so is not defined as a
standard ISR using the __irq keyword. Instead a wrapper function is defined
within serialISR.s79 which in turn calls this function. See the port
documentation on the FreeRTOS.org website for more information. */
__arm void vSerialISR( void )
{
unsigned portLONG ulStatus;
signed portCHAR cChar;
portBASE_TYPE xTaskWokenByTx = pdFALSE, xTaskWokenByPost = pdFALSE;
/* What caused the interrupt? */
ulStatus = serCOM0->US_CSR &= serCOM0->US_IMR;
if( ulStatus & AT91C_US_TXRDY )
{
/* The interrupt was caused by the THR becoming empty. Are there any
more characters to transmit? */
if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xTaskWokenByTx ) == pdTRUE )
{
/* A character was retrieved from the queue so can be sent to the
THR now. */
serCOM0->US_THR = cChar;
}
else
{
/* Queue empty, nothing to send so turn off the Tx interrupt. */
vInterruptOff();
}
}
if( ulStatus & AT91C_US_RXRDY )
{
/* The interrupt was caused by a character being received. Grab the
character from the RHR and place it in the queue or received
characters. */
cChar = serCOM0->US_RHR;
xTaskWokenByPost = xQueueSendFromISR( xRxedChars, &cChar, xTaskWokenByPost );
}
/* If a task was woken by either a character being received or a character
being transmitted then we may need to switch to another task. */
portEND_SWITCHING_ISR( ( xTaskWokenByPost || xTaskWokenByTx ) );
/* End the interrupt in the AIC. */
AT91C_BASE_AIC->AIC_EOICR = 0;
}

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Demo/ARM7_AT91SAM7S64_IAR/serial/serialISR.s79 Normal file
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RSEG ICODE:CODE
CODE32
EXTERN vSerialISR
PUBLIC vSerialISREntry
; Wrapper for the serial port interrupt service routine. This can cause a
; context switch so requires an assembly wrapper.
; Defines the portSAVE_CONTEXT and portRESTORE_CONTEXT macros.
#include "ISR_Support.h"
vSerialISREntry:
portSAVE_CONTEXT ; Save the context of the current task.
bl vSerialISR ; Call the ISR routine.
portRESTORE_CONTEXT ; Restore the context of the current task -
; which may be different to the task that
; was interrupted.
END

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23
Demo/ARM7_AT91SAM7S64_IAR/settings/Basic.dni Normal file
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80
Demo/ARM7_AT91SAM7S64_IAR/settings/BasicSAM7.wsdt Normal file
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Demo/ARM7_AT91SAM7S64_IAR/settings/rtosdemo.dbgdt Normal file
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Demo/ARM7_AT91SAM7S64_IAR/settings/rtosdemo.dni Normal file
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Demo/ARM7_AT91SAM7S64_IAR/settings/rtosdemo.wsdt Normal file
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Demo/ARM7_LPC2106_GCC/FreeRTOSConfig.h Normal file
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/*
FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
FreeRTOS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with FreeRTOS; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes FreeRTOS, without being obliged to provide
the source code for any proprietary components. See the licensing section
of http://www.FreeRTOS.org for full details of how and when the exception
can be applied.
***************************************************************************
See http://www.FreeRTOS.org for documentation, latest information, license
and contact details. Please ensure to read the configuration and relevant
port sections of the online documentation.
***************************************************************************
*/
#ifndef FREERTOS_CONFIG_H
#define FREERTOS_CONFIG_H
#include <lpc210x.h>
/*-----------------------------------------------------------
* Application specific definitions.
*
* These definitions should be adjusted for your particular hardware and
* application requirements.
*
* THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
* FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
*----------------------------------------------------------*/
#define configUSE_PREEMPTION 1
#define configUSE_IDLE_HOOK 0
#define configUSE_TICK_HOOK 0
#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 58982400 ) /* =14.7456MHz xtal multiplied by 4 using the PLL. */
#define configTICK_RATE_HZ ( ( portTickType ) 1000 )
#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 )
#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 128 )
#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 23 * 1024 ) )
#define configMAX_TASK_NAME_LEN ( 16 )
#define configUSE_TRACE_FACILITY 0
#define configUSE_16_BIT_TICKS 0
#define configIDLE_SHOULD_YIELD 1
/* Co-routine definitions. */
#define configUSE_CO_ROUTINES 0
#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
/* Set the following definitions to 1 to include the API function, or zero
to exclude the API function. */
#define INCLUDE_vTaskPrioritySet 1
#define INCLUDE_uxTaskPriorityGet 1
#define INCLUDE_vTaskDelete 1
#define INCLUDE_vTaskCleanUpResources 0
#define INCLUDE_vTaskSuspend 1
#define INCLUDE_vTaskDelayUntil 1
#define INCLUDE_vTaskDelay 1
#endif /* FREERTOS_CONFIG_H */

118
Demo/ARM7_LPC2106_GCC/Makefile Normal file
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# FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.
#
# This file is part of the FreeRTOS distribution.
#
# FreeRTOS is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2 of the License, or
# (at your option) any later version.
#
# FreeRTOS is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with FreeRTOS; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
#
# A special exception to the GPL can be applied should you wish to distribute
# a combined work that includes FreeRTOS, without being obliged to provide
# the source code for any proprietary components. See the licensing section
# of http://www.FreeRTOS.org for full details of how and when the exception
# can be applied.
#
# ***************************************************************************
# See http://www.FreeRTOS.org for documentation, latest information, license
# and contact details. Please ensure to read the configuration and relevant
# port sections of the online documentation.
# ***************************************************************************
# Changes from V2.4.2
#
# + Replaced source/portable/gcc/arm7/portheap.c with source/portable/memmang/heap_2.c.
CC=arm-elf-gcc
OBJCOPY=arm-elf-objcopy
ARCH=arm-elf-ar
CRT0=boot.s
WARNINGS=-Wall -Wextra -Wshadow -Wpointer-arith -Wbad-function-cast -Wcast-align -Wsign-compare \
-Waggregate-return -Wstrict-prototypes -Wmissing-prototypes -Wmissing-declarations -Wunused
#
# CFLAGS common to both the THUMB and ARM mode builds
#
CFLAGS=$(WARNINGS) -D $(RUN_MODE) -D GCC_ARM7 -I. -I../../Source/include \
-I../Common/include $(DEBUG) -mcpu=arm7tdmi -T$(LDSCRIPT) \
$(OPTIM)
ifeq ($(USE_THUMB_MODE),YES)
CFLAGS += -mthumb-interwork -D THUMB_INTERWORK
THUMB_FLAGS=-mthumb
endif
LINKER_FLAGS=-Xlinker -ortosdemo.elf -Xlinker -M -Xlinker -Map=rtosdemo.map
RTOS_SOURCE_DIR=../../Source
DEMO_SOURCE_DIR=../Common/Minimal
#
# Source files that can be built to THUMB mode.
#
THUMB_SRC = \
main.c \
serial/serial.c \
ParTest/ParTest.c \
$(DEMO_SOURCE_DIR)/integer.c \
$(DEMO_SOURCE_DIR)/flash.c \
$(DEMO_SOURCE_DIR)/PollQ.c \
$(DEMO_SOURCE_DIR)/comtest.c \
$(DEMO_SOURCE_DIR)/flop.c \
$(DEMO_SOURCE_DIR)/semtest.c \
$(DEMO_SOURCE_DIR)/dynamic.c \
$(DEMO_SOURCE_DIR)/BlockQ.c \
$(RTOS_SOURCE_DIR)/tasks.c \
$(RTOS_SOURCE_DIR)/queue.c \
$(RTOS_SOURCE_DIR)/list.c \
$(RTOS_SOURCE_DIR)/portable/MemMang/heap_2.c \
$(RTOS_SOURCE_DIR)/portable/GCC/ARM7_LPC2000/port.c
#
# Source files that must be built to ARM mode.
#
ARM_SRC = \
$(RTOS_SOURCE_DIR)/portable/GCC/ARM7_LPC2000/portISR.c \
serial/serialISR.c
#
# Define all object files.
#
ARM_OBJ = $(ARM_SRC:.c=.o)
THUMB_OBJ = $(THUMB_SRC:.c=.o)
rtosdemo.hex : rtosdemo.elf
$(OBJCOPY) rtosdemo.elf -O ihex rtosdemo.hex
rtosdemo.elf : $(ARM_OBJ) $(THUMB_OBJ) $(CRT0) Makefile
$(CC) $(CFLAGS) $(ARM_OBJ) $(THUMB_OBJ) -nostartfiles $(CRT0) $(LINKER_FLAGS)
$(THUMB_OBJ) : %.o : %.c $(LDSCRIPT) Makefile
$(CC) -c $(THUMB_FLAGS) $(CFLAGS) $< -o $@
$(ARM_OBJ) : %.o : %.c $(LDSCRIPT) Makefile
$(CC) -c $(CFLAGS) $< -o $@
clean :
touch Makefile

106
Demo/ARM7_LPC2106_GCC/ParTest/ParTest.c Normal file
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/*
FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
FreeRTOS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with FreeRTOS; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes FreeRTOS, without being obliged to provide
the source code for any proprietary components. See the licensing section
of http://www.FreeRTOS.org for full details of how and when the exception
can be applied.
***************************************************************************
See http://www.FreeRTOS.org for documentation, latest information, license
and contact details. Please ensure to read the configuration and relevant
port sections of the online documentation.
***************************************************************************
*/
/*
Changes from V2.5.2
+ All LED's are turned off to start.
*/
#include "FreeRTOS.h"
#include "partest.h"
#define partstFIRST_IO ( ( unsigned portLONG ) 0x400 )
#define partstNUM_LEDS ( 4 )
#define partstALL_OUTPUTS_OFF ( ( unsigned portLONG ) 0xffffffff )
/*-----------------------------------------------------------
* Simple parallel port IO routines.
*-----------------------------------------------------------*/
void vParTestInitialise( void )
{
/* This is performed from main() as the io bits are shared with other setup
functions. */
/* Turn all outputs off. */
GPIO_IOSET = partstALL_OUTPUTS_OFF;
}
/*-----------------------------------------------------------*/
void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue )
{
unsigned portLONG ulLED = partstFIRST_IO;
if( uxLED < partstNUM_LEDS )
{
/* Rotate to the wanted bit of port 0. Only P10 to P13 have an LED
attached. */
ulLED <<= ( unsigned portLONG ) uxLED;
/* Set of clear the output. */
if( xValue )
{
GPIO_IOCLR = ulLED;
}
else
{
GPIO_IOSET = ulLED;
}
}
}
/*-----------------------------------------------------------*/
void vParTestToggleLED( unsigned portBASE_TYPE uxLED )
{
unsigned portLONG ulLED = partstFIRST_IO, ulCurrentState;
if( uxLED < partstNUM_LEDS )
{
/* Rotate to the wanted bit of port 0. Only P10 to P13 have an LED
attached. */
ulLED <<= ( unsigned portLONG ) uxLED;
/* If this bit is already set, clear it, and visa versa. */
ulCurrentState = GPIO0_IOPIN;
if( ulCurrentState & ulLED )
{
GPIO_IOCLR = ulLED;
}
else
{
GPIO_IOSET = ulLED;
}
}
}

157
Demo/ARM7_LPC2106_GCC/boot.s Normal file
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/* Sample initialization file */
.extern main
.extern exit
.text
.code 32
.align 0
.extern __bss_beg__
.extern __bss_end__
.extern __stack_end__
.extern __data_beg__
.extern __data_end__
.extern __data+beg_src__
.global start
.global endless_loop
/* Stack Sizes */
.set UND_STACK_SIZE, 0x00000004
.set ABT_STACK_SIZE, 0x00000004
.set FIQ_STACK_SIZE, 0x00000004
.set IRQ_STACK_SIZE, 0X00000400
.set SVC_STACK_SIZE, 0x00000400
/* Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs */
.set MODE_USR, 0x10 /* User Mode */
.set MODE_FIQ, 0x11 /* FIQ Mode */
.set MODE_IRQ, 0x12 /* IRQ Mode */
.set MODE_SVC, 0x13 /* Supervisor Mode */
.set MODE_ABT, 0x17 /* Abort Mode */
.set MODE_UND, 0x1B /* Undefined Mode */
.set MODE_SYS, 0x1F /* System Mode */
.equ I_BIT, 0x80 /* when I bit is set, IRQ is disabled */
.equ F_BIT, 0x40 /* when F bit is set, FIQ is disabled */
start:
_start:
_mainCRTStartup:
/* Setup a stack for each mode - note that this only sets up a usable stack
for system/user, SWI and IRQ modes. Also each mode is setup with
interrupts initially disabled. */
ldr r0, .LC6
msr CPSR_c, #MODE_UND|I_BIT|F_BIT /* Undefined Instruction Mode
mov sp, r0
sub r0, r0, #UND_STACK_SIZE
msr CPSR_c, #MODE_ABT|I_BIT|F_BIT /* Abort Mode */
mov sp, r0
sub r0, r0, #ABT_STACK_SIZE
msr CPSR_c, #MODE_FIQ|I_BIT|F_BIT /* FIQ Mode */
mov sp, r0
sub r0, r0, #FIQ_STACK_SIZE
msr CPSR_c, #MODE_IRQ|I_BIT|F_BIT /* IRQ Mode */
mov sp, r0
sub r0, r0, #IRQ_STACK_SIZE
msr CPSR_c, #MODE_SVC|I_BIT|F_BIT /* Supervisor Mode */
mov sp, r0
sub r0, r0, #SVC_STACK_SIZE
msr CPSR_c, #MODE_SYS|I_BIT|F_BIT /* System Mode */
mov sp, r0
/* We want to start in supervisor mode. Operation will switch to system
mode when the first task starts. */
msr CPSR_c, #MODE_SVC|I_BIT|F_BIT
/* Clear BSS. */
mov a2, #0 /* Fill value */
mov fp, a2 /* Null frame pointer */
mov r7, a2 /* Null frame pointer for Thumb */
ldr r1, .LC1 /* Start of memory block */
ldr r3, .LC2 /* End of memory block */
subs r3, r3, r1 /* Length of block */
beq .end_clear_loop
mov r2, #0
.clear_loop:
strb r2, [r1], #1
subs r3, r3, #1
bgt .clear_loop
.end_clear_loop:
/* Initialise data. */
ldr r1, .LC3 /* Start of memory block */
ldr r2, .LC4 /* End of memory block */
ldr r3, .LC5
subs r3, r3, r1 /* Length of block */
beq .end_set_loop
.set_loop:
ldrb r4, [r2], #1
strb r4, [r1], #1
subs r3, r3, #1
bgt .set_loop
.end_set_loop:
mov r0, #0 /* no arguments */
mov r1, #0 /* no argv either */
bl main
endless_loop:
b endless_loop
.align 0
.LC1:
.word __bss_beg__
.LC2:
.word __bss_end__
.LC3:
.word __data_beg__
.LC4:
.word __data_beg_src__
.LC5:
.word __data_end__
.LC6:
.word __stack_end__
/* Setup vector table. Note that undf, pabt, dabt, fiq just execute
a null loop. */
.section .startup,"ax"
.code 32
.align 0
b _start /* reset - _start */
ldr pc, _undf /* undefined - _undf */
ldr pc, _swi /* SWI - _swi */
ldr pc, _pabt /* program abort - _pabt */
ldr pc, _dabt /* data abort - _dabt */
nop /* reserved */
ldr pc, [pc,#-0xFF0] /* IRQ - read the VIC */
ldr pc, _fiq /* FIQ - _fiq */
_undf: .word __undf /* undefined */
_swi: .word vPortYieldProcessor /* SWI */
_pabt: .word __pabt /* program abort */
_dabt: .word __dabt /* data abort */
_fiq: .word __fiq /* FIQ */
__undf: b . /* undefined */
__pabt: b . /* program abort */
__dabt: b . /* data abort */
__fiq: b . /* FIQ */

49
Demo/ARM7_LPC2106_GCC/lpc2106-ram.ld Normal file
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MEMORY
{
flash : ORIGIN = 0, LENGTH = 120K
ram : ORIGIN = 0x40000000, LENGTH = 64K
}
__stack_end__ = 0x40000000 + 64K - 4;
SECTIONS
{
. = 0;
startup : { *(.startup)} >ram
prog :
{
*(.text)
*(.rodata)
*(.rodata*)
*(.glue_7)
*(.glue_7t)
} >ram
__end_of_text__ = .;
.data :
{
__data_beg__ = .;
__data_beg_src__ = __end_of_text__;
*(.data)
__data_end__ = .;
} >ram
.bss :
{
__bss_beg__ = .;
*(.bss)
} >ram
/* Align here to ensure that the .bss section occupies space up to
_end. Align after .bss to ensure correct alignment even if the
.bss section disappears because there are no input sections. */
. = ALIGN(32 / 8);
}
. = ALIGN(32 / 8);
_end = .;
_bss_end__ = . ; __bss_end__ = . ; __end__ = . ;
PROVIDE (end = .);

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Demo/ARM7_LPC2106_GCC/lpc2106-rom.ld Normal file
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MEMORY
{
flash : ORIGIN = 0, LENGTH = 120K
ram : ORIGIN = 0x40000000, LENGTH = 64K
}
__stack_end__ = 0x40000000 + 64K - 4;
SECTIONS
{
. = 0;
startup : { *(.startup)} >flash
prog :
{
*(.text)
*(.rodata)
*(.rodata*)
*(.glue_7)
*(.glue_7t)
} >flash
__end_of_text__ = .;
.data :
{
__data_beg__ = .;
__data_beg_src__ = __end_of_text__;
*(.data)
__data_end__ = .;
} >ram AT>flash
.bss :
{
__bss_beg__ = .;
*(.bss)
} >ram
/* Align here to ensure that the .bss section occupies space up to
_end. Align after .bss to ensure correct alignment even if the
.bss section disappears because there are no input sections. */
. = ALIGN(32 / 8);
}
. = ALIGN(32 / 8);
_end = .;
_bss_end__ = . ; __bss_end__ = . ; __end__ = . ;
PROVIDE (end = .);

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#ifndef lpc210x_h
#define lpc210x_h
/*******************************************************************************
lpc210x.h - Register defs for Philips LPC210X: LPC2104, LPC2105 and LPC2106
THE SOFTWARE IS DELIVERED "AS IS" WITHOUT WARRANTY OR CONDITION OF ANY KIND,
EITHER EXPRESS, IMPLIED OR STATUTORY. THIS INCLUDES WITHOUT LIMITATION ANY
WARRANTY OR CONDITION WITH RESPECT TO MERCHANTABILITY OR FITNESS FOR ANY
PARTICULAR PURPOSE, OR AGAINST THE INFRINGEMENTS OF INTELLECTUAL PROPERTY RIGHTS
OF OTHERS.
This file may be freely used for commercial and non-commercial applications,
including being redistributed with any tools.
If you find a problem with the file, please report it so that it can be fixed.
Created by Sten Larsson (sten_larsson at yahoo com)
Edited by Richard Barry.
*******************************************************************************/
#define REG8 (volatile unsigned char*)
#define REG16 (volatile unsigned short*)
#define REG32 (volatile unsigned int*)
/*##############################################################################
## MISC
##############################################################################*/
/* Constants for data to put in IRQ/FIQ Exception Vectors */
#define VECTDATA_IRQ 0xE51FFFF0 /* LDR PC,[PC,#-0xFF0] */
#define VECTDATA_FIQ /* __TODO */
/*##############################################################################
## VECTORED INTERRUPT CONTROLLER
##############################################################################*/
#define VICIRQStatus (*(REG32 (0xFFFFF000)))
#define VICFIQStatus (*(REG32 (0xFFFFF004)))
#define VICRawIntr (*(REG32 (0xFFFFF008)))
#define VICIntSelect (*(REG32 (0xFFFFF00C)))
#define VICIntEnable (*(REG32 (0xFFFFF010)))
#define VICIntEnClear (*(REG32 (0xFFFFF014)))
#define VICSoftInt (*(REG32 (0xFFFFF018)))
#define VICSoftIntClear (*(REG32 (0xFFFFF01C)))
#define VICProtection (*(REG32 (0xFFFFF020)))
#define VICVectAddr (*(REG32 (0xFFFFF030)))
#define VICDefVectAddr (*(REG32 (0xFFFFF034)))
#define VICVectAddr0 (*(REG32 (0xFFFFF100)))
#define VICVectAddr1 (*(REG32 (0xFFFFF104)))
#define VICVectAddr2 (*(REG32 (0xFFFFF108)))
#define VICVectAddr3 (*(REG32 (0xFFFFF10C)))
#define VICVectAddr4 (*(REG32 (0xFFFFF110)))
#define VICVectAddr5 (*(REG32 (0xFFFFF114)))
#define VICVectAddr6 (*(REG32 (0xFFFFF118)))
#define VICVectAddr7 (*(REG32 (0xFFFFF11C)))
#define VICVectAddr8 (*(REG32 (0xFFFFF120)))
#define VICVectAddr9 (*(REG32 (0xFFFFF124)))
#define VICVectAddr10 (*(REG32 (0xFFFFF128)))
#define VICVectAddr11 (*(REG32 (0xFFFFF12C)))
#define VICVectAddr12 (*(REG32 (0xFFFFF130)))
#define VICVectAddr13 (*(REG32 (0xFFFFF134)))
#define VICVectAddr14 (*(REG32 (0xFFFFF138)))
#define VICVectAddr15 (*(REG32 (0xFFFFF13C)))
#define VICVectCntl0 (*(REG32 (0xFFFFF200)))
#define VICVectCntl1 (*(REG32 (0xFFFFF204)))
#define VICVectCntl2 (*(REG32 (0xFFFFF208)))
#define VICVectCntl3 (*(REG32 (0xFFFFF20C)))
#define VICVectCntl4 (*(REG32 (0xFFFFF210)))
#define VICVectCntl5 (*(REG32 (0xFFFFF214)))
#define VICVectCntl6 (*(REG32 (0xFFFFF218)))
#define VICVectCntl7 (*(REG32 (0xFFFFF21C)))
#define VICVectCntl8 (*(REG32 (0xFFFFF220)))
#define VICVectCntl9 (*(REG32 (0xFFFFF224)))
#define VICVectCntl10 (*(REG32 (0xFFFFF228)))
#define VICVectCntl11 (*(REG32 (0xFFFFF22C)))
#define VICVectCntl12 (*(REG32 (0xFFFFF230)))
#define VICVectCntl13 (*(REG32 (0xFFFFF234)))
#define VICVectCntl14 (*(REG32 (0xFFFFF238)))
#define VICVectCntl15 (*(REG32 (0xFFFFF23C)))
#define VICITCR (*(REG32 (0xFFFFF300)))
#define VICITIP1 (*(REG32 (0xFFFFF304)))
#define VICITIP2 (*(REG32 (0xFFFFF308)))
#define VICITOP1 (*(REG32 (0xFFFFF30C)))
#define VICITOP2 (*(REG32 (0xFFFFF310)))
#define VICPeriphID0 (*(REG32 (0xFFFFFFE0)))
#define VICPeriphID1 (*(REG32 (0xFFFFFFE4)))
#define VICPeriphID2 (*(REG32 (0xFFFFFFE8)))
#define VICPeriphID3 (*(REG32 (0xFFFFFFEC)))
#define VICIntEnClr VICIntEnClear
#define VICSoftIntClr VICSoftIntClear
/*##############################################################################
## PCB - Pin Connect Block
##############################################################################*/
#define PCB_PINSEL0 (*(REG32 (0xE002C000)))
#define PCB_PINSEL1 (*(REG32 (0xE002C004)))
/*##############################################################################
## GPIO - General Purpose I/O
##############################################################################*/
#define GPIO_IOPIN (*(REG32 (0xE0028000))) /* ALTERNATE NAME GPIO = GPIO0 */
#define GPIO_IOSET (*(REG32 (0xE0028004)))
#define GPIO_IODIR (*(REG32 (0xE0028008)))
#define GPIO_IOCLR (*(REG32 (0xE002800C)))
#define GPIO0_IOPIN (*(REG32 (0xE0028000))) /* ALTERNATE NAME GPIO = GPIO0 */
#define GPIO0_IOSET (*(REG32 (0xE0028004)))
#define GPIO0_IODIR (*(REG32 (0xE0028008)))
#define GPIO0_IOCLR (*(REG32 (0xE002800C)))
/*##############################################################################
## UART0 / UART1
##############################################################################*/
/* ---- UART 0 --------------------------------------------- */
#define UART0_RBR (*(REG32 (0xE000C000)))
#define UART0_THR (*(REG32 (0xE000C000)))
#define UART0_IER (*(REG32 (0xE000C004)))
#define UART0_IIR (*(REG32 (0xE000C008)))
#define UART0_FCR (*(REG32 (0xE000C008)))
#define UART0_LCR (*(REG32 (0xE000C00C)))
#define UART0_LSR (*(REG32 (0xE000C014)))
#define UART0_SCR (*(REG32 (0xE000C01C)))
#define UART0_DLL (*(REG32 (0xE000C000)))
#define UART0_DLM (*(REG32 (0xE000C004)))
/* ---- UART 1 --------------------------------------------- */
#define UART1_RBR (*(REG32 (0xE0010000)))
#define UART1_THR (*(REG32 (0xE0010000)))
#define UART1_IER (*(REG32 (0xE0010004)))
#define UART1_IIR (*(REG32 (0xE0010008)))
#define UART1_FCR (*(REG32 (0xE0010008)))
#define UART1_LCR (*(REG32 (0xE001000C)))
#define UART1_LSR (*(REG32 (0xE0010014)))
#define UART1_SCR (*(REG32 (0xE001001C)))
#define UART1_DLL (*(REG32 (0xE0010000)))
#define UART1_DLM (*(REG32 (0xE0010004)))
#define UART1_MCR (*(REG32 (0xE0010010)))
#define UART1_MSR (*(REG32 (0xE0010018)))
/*##############################################################################
## I2C
##############################################################################*/
#define I2C_I2CONSET (*(REG32 (0xE001C000)))
#define I2C_I2STAT (*(REG32 (0xE001C004)))
#define I2C_I2DAT (*(REG32 (0xE001C008)))
#define I2C_I2ADR (*(REG32 (0xE001C00C)))
#define I2C_I2SCLH (*(REG32 (0xE001C010)))
#define I2C_I2SCLL (*(REG32 (0xE001C014)))
#define I2C_I2CONCLR (*(REG32 (0xE001C018)))
/*##############################################################################
## SPI - Serial Peripheral Interface
##############################################################################*/
#define SPI_SPCR (*(REG32 (0xE0020000)))
#define SPI_SPSR (*(REG32 (0xE0020004)))
#define SPI_SPDR (*(REG32 (0xE0020008)))
#define SPI_SPCCR (*(REG32 (0xE002000C)))
#define SPI_SPTCR (*(REG32 (0xE0020010)))
#define SPI_SPTSR (*(REG32 (0xE0020014)))
#define SPI_SPTOR (*(REG32 (0xE0020018)))
#define SPI_SPINT (*(REG32 (0xE002001C)))
/*##############################################################################
## Timer 0 and Timer 1
##############################################################################*/
/* ---- Timer 0 -------------------------------------------- */
#define T0_IR (*(REG32 (0xE0004000)))
#define T0_TCR (*(REG32 (0xE0004004)))
#define T0_TC (*(REG32 (0xE0004008)))
#define T0_PR (*(REG32 (0xE000400C)))
#define T0_PC (*(REG32 (0xE0004010)))
#define T0_MCR (*(REG32 (0xE0004014)))
#define T0_MR0 (*(REG32 (0xE0004018)))
#define T0_MR1 (*(REG32 (0xE000401C)))
#define T0_MR2 (*(REG32 (0xE0004020)))
#define T0_MR3 (*(REG32 (0xE0004024)))
#define T0_CCR (*(REG32 (0xE0004028)))
#define T0_CR0 (*(REG32 (0xE000402C)))
#define T0_CR1 (*(REG32 (0xE0004030)))
#define T0_CR2 (*(REG32 (0xE0004034)))
#define T0_CR3 (*(REG32 (0xE0004038)))
#define T0_EMR (*(REG32 (0xE000403C)))
/* ---- Timer 1 -------------------------------------------- */
#define T1_IR (*(REG32 (0xE0008000)))
#define T1_TCR (*(REG32 (0xE0008004)))
#define T1_TC (*(REG32 (0xE0008008)))
#define T1_PR (*(REG32 (0xE000800C)))
#define T1_PC (*(REG32 (0xE0008010)))
#define T1_MCR (*(REG32 (0xE0008014)))
#define T1_MR0 (*(REG32 (0xE0008018)))
#define T1_MR1 (*(REG32 (0xE000801C)))
#define T1_MR2 (*(REG32 (0xE0008020)))
#define T1_MR3 (*(REG32 (0xE0008024)))
#define T1_CCR (*(REG32 (0xE0008028)))
#define T1_CR0 (*(REG32 (0xE000802C)))
#define T1_CR1 (*(REG32 (0xE0008030)))
#define T1_CR2 (*(REG32 (0xE0008034)))
#define T1_CR3 (*(REG32 (0xE0008038)))
#define T1_EMR (*(REG32 (0xE000803C)))
/*##############################################################################
## PWM
##############################################################################*/
#define PWM_IR (*(REG32 (0xE0014000)))
#define PWM_TCR (*(REG32 (0xE0014004)))
#define PWM_TC (*(REG32 (0xE0014008)))
#define PWM_PR (*(REG32 (0xE001400C)))
#define PWM_PC (*(REG32 (0xE0014010)))
#define PWM_MCR (*(REG32 (0xE0014014)))
#define PWM_MR0 (*(REG32 (0xE0014018)))
#define PWM_MR1 (*(REG32 (0xE001401C)))
#define PWM_MR2 (*(REG32 (0xE0014020)))
#define PWM_MR3 (*(REG32 (0xE0014024)))
#define PWM_MR4 (*(REG32 (0xE0014040)))
#define PWM_MR5 (*(REG32 (0xE0014044)))
#define PWM_MR6 (*(REG32 (0xE0014048)))
#define PWM_EMR (*(REG32 (0xE001403C)))
#define PWM_PCR (*(REG32 (0xE001404C)))
#define PWM_LER (*(REG32 (0xE0014050)))
#define PWM_CCR (*(REG32 (0xE0014028)))
#define PWM_CR0 (*(REG32 (0xE001402C)))
#define PWM_CR1 (*(REG32 (0xE0014030)))
#define PWM_CR2 (*(REG32 (0xE0014034)))
#define PWM_CR3 (*(REG32 (0xE0014038)))
/*##############################################################################
## RTC
##############################################################################*/
/* ---- RTC: Miscellaneous Register Group ------------------ */
#define RTC_ILR (*(REG32 (0xE0024000)))
#define RTC_CTC (*(REG32 (0xE0024004)))
#define RTC_CCR (*(REG32 (0xE0024008)))
#define RTC_CIIR (*(REG32 (0xE002400C)))
#define RTC_AMR (*(REG32 (0xE0024010)))
#define RTC_CTIME0 (*(REG32 (0xE0024014)))
#define RTC_CTIME1 (*(REG32 (0xE0024018)))
#define RTC_CTIME2 (*(REG32 (0xE002401C)))
/* ---- RTC: Timer Control Group --------------------------- */
#define RTC_SEC (*(REG32 (0xE0024020)))
#define RTC_MIN (*(REG32 (0xE0024024)))
#define RTC_HOUR (*(REG32 (0xE0024028)))
#define RTC_DOM (*(REG32 (0xE002402C)))
#define RTC_DOW (*(REG32 (0xE0024030)))
#define RTC_DOY (*(REG32 (0xE0024034)))
#define RTC_MONTH (*(REG32 (0xE0024038)))
#define RTC_YEAR (*(REG32 (0xE002403C)))
/* ---- RTC: Alarm Control Group --------------------------- */
#define RTC_ALSEC (*(REG32 (0xE0024060)))
#define RTC_ALMIN (*(REG32 (0xE0024064)))
#define RTC_ALHOUR (*(REG32 (0xE0024068)))
#define RTC_ALDOM (*(REG32 (0xE002406C)))
#define RTC_ALDOW (*(REG32 (0xE0024070)))
#define RTC_ALDOY (*(REG32 (0xE0024074)))
#define RTC_ALMON (*(REG32 (0xE0024078)))
#define RTC_ALYEAR (*(REG32 (0xE002407C)))
/* ---- RTC: Reference Clock Divider Group ----------------- */
#define RTC_PREINT (*(REG32 (0xE0024080)))
#define RTC_PREFRAC (*(REG32 (0xE0024084)))
/*##############################################################################
## WD - Watchdog
##############################################################################*/
#define WD_WDMOD (*(REG32 (0xE0000000)))
#define WD_WDTC (*(REG32 (0xE0000004)))
#define WD_WDFEED (*(REG32 (0xE0000008)))
#define WD_WDTV (*(REG32 (0xE000000C)))
/*##############################################################################
## System Control Block
##############################################################################*/
#define SCB_EXTINT (*(REG32 (0xE01FC140)))
#define SCB_EXTWAKE (*(REG32 (0xE01FC144)))
#define SCB_MEMMAP (*(REG32 (0xE01FC040)))
#define SCB_PLLCON (*(REG32 (0xE01FC080)))
#define SCB_PLLCFG (*(REG32 (0xE01FC084)))
#define SCB_PLLSTAT (*(REG32 (0xE01FC088)))
#define SCB_PLLFEED (*(REG32 (0xE01FC08C)))
#define SCB_PCON (*(REG32 (0xE01FC0C0)))
#define SCB_PCONP (*(REG32 (0xE01FC0C4)))
#define SCB_VPBDIV (*(REG32 (0xE01FC100)))
/*##############################################################################
## Memory Accelerator Module (MAM)
##############################################################################*/
#define MAM_TIM (*(REG32 (0xE01FC004)))
#define MAM_CR (*(REG32 (0xE01FC000)))
#endif /* lpc210x_h */

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#include "lpc2114.h"

474
Demo/ARM7_LPC2106_GCC/main.c Normal file
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/*
FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
FreeRTOS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with FreeRTOS; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes FreeRTOS, without being obliged to provide
the source code for any proprietary components. See the licensing section
of http://www.FreeRTOS.org for full details of how and when the exception
can be applied.
***************************************************************************
See http://www.FreeRTOS.org for documentation, latest information, license
and contact details. Please ensure to read the configuration and relevant
port sections of the online documentation.
***************************************************************************
*/
/*
NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode.
The processor MUST be in supervisor mode when vTaskStartScheduler is
called. The demo applications included in the FreeRTOS.org download switch
to supervisor mode prior to main being called. If you are not using one of
these demo application projects then ensure Supervisor mode is used.
*/
/*
* Creates all the demo application tasks, then starts the scheduler. The WEB
* documentation provides more details of the demo application tasks.
*
* Main.c also creates a task called "Check". This only executes every three
* seconds but has the highest priority so is guaranteed to get processor time.
* Its main function is to check that all the other tasks are still operational.
* Each task (other than the "flash" tasks) maintains a unique count that is
* incremented each time the task successfully completes its function. Should
* any error occur within such a task the count is permanently halted. The
* check task inspects the count of each task to ensure it has changed since
* the last time the check task executed. If all the count variables have
* changed all the tasks are still executing error free, and the check task
* toggles the onboard LED. Should any task contain an error at any time
* the LED toggle rate will change from 3 seconds to 500ms.
*
* To check the operation of the memory allocator the check task also
* dynamically creates a task before delaying, and deletes it again when it
* wakes. If memory cannot be allocated for the new task the call to xTaskCreate
* will fail and an error is signalled. The dynamically created task itself
* allocates and frees memory just to give the allocator a bit more exercise.
*
*/
/*
Changes from V2.4.2
+ The vErrorChecks() task now dynamically creates then deletes a task each
cycle. This tests the operation of the memory allocator.
Changes from V2.5.2
+ vParTestInitialise() is called during initialisation to ensure all the
LED's start off.
*/
/* Standard includes. */
#include <stdlib.h>
#include <string.h>
/* Scheduler includes. */
#include "FreeRTOS.h"
#include "task.h"
/* Demo application includes. */
#include "partest.h"
#include "flash.h"
#include "integer.h"
#include "PollQ.h"
#include "comtest2.h"
#include "semtest.h"
#include "flop.h"
#include "dynamic.h"
#include "BlockQ.h"
#include "serial.h"
/*-----------------------------------------------------------*/
/* Constants to setup I/O. */
#define mainTX_ENABLE ( ( unsigned portLONG ) 0x0001 )
#define mainRX_ENABLE ( ( unsigned portLONG ) 0x0004 )
#define mainP0_14 ( ( unsigned portLONG ) 0x4000 )
#define mainJTAG_PORT ( ( unsigned portLONG ) 0x3E0000UL )
/* Constants to setup the PLL. */
#define mainPLL_MUL_4 ( ( unsigned portCHAR ) 0x0003 )
#define mainPLL_DIV_1 ( ( unsigned portCHAR ) 0x0000 )
#define mainPLL_ENABLE ( ( unsigned portCHAR ) 0x0001 )
#define mainPLL_CONNECT ( ( unsigned portCHAR ) 0x0003 )
#define mainPLL_FEED_BYTE1 ( ( unsigned portCHAR ) 0xaa )
#define mainPLL_FEED_BYTE2 ( ( unsigned portCHAR ) 0x55 )
#define mainPLL_LOCK ( ( unsigned portLONG ) 0x0400 )
/* Constants to setup the MAM. */
#define mainMAM_TIM_3 ( ( unsigned portCHAR ) 0x03 )
#define mainMAM_MODE_FULL ( ( unsigned portCHAR ) 0x02 )
/* Constants to setup the peripheral bus. */
#define mainBUS_CLK_FULL ( ( unsigned portCHAR ) 0x01 )
/* Constants for the ComTest tasks. */
#define mainCOM_TEST_BAUD_RATE ( ( unsigned portLONG ) 115200 )
#define mainCOM_TEST_LED ( 3 )
/* Priorities for the demo application tasks. */
#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 )
#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 )
#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 )
#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 4 )
#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 )
#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 )
/* The rate at which the on board LED will toggle when there is/is not an
error. */
#define mainNO_ERROR_FLASH_PERIOD ( ( portTickType ) 3000 / portTICK_RATE_MS )
#define mainERROR_FLASH_PERIOD ( ( portTickType ) 500 / portTICK_RATE_MS )
#define mainON_BOARD_LED_BIT ( ( unsigned portLONG ) 0x80 )
/* Constants used by the vMemCheckTask() task. */
#define mainCOUNT_INITIAL_VALUE ( ( unsigned portLONG ) 0 )
#define mainNO_TASK ( 0 )
/* The size of the memory blocks allocated by the vMemCheckTask() task. */
#define mainMEM_CHECK_SIZE_1 ( ( size_t ) 51 )
#define mainMEM_CHECK_SIZE_2 ( ( size_t ) 52 )
#define mainMEM_CHECK_SIZE_3 ( ( size_t ) 151 )
/*-----------------------------------------------------------*/
/*
* The Olimex demo board has a single built in LED. This function simply
* toggles its state.
*/
void prvToggleOnBoardLED( void );
/*
* Checks that all the demo application tasks are still executing without error
* - as described at the top of the file.
*/
static portLONG prvCheckOtherTasksAreStillRunning( unsigned portLONG ulMemCheckTaskCount );
/*
* The task that executes at the highest priority and calls
* prvCheckOtherTasksAreStillRunning(). See the description at the top
* of the file.
*/
static void vErrorChecks( void *pvParameters );
/*
* Dynamically created and deleted during each cycle of the vErrorChecks()
* task. This is done to check the operation of the memory allocator.
* See the top of vErrorChecks for more details.
*/
static void vMemCheckTask( void *pvParameters );
/*
* Configure the processor for use with the Olimex demo board. This includes
* setup for the I/O, system clock, and access timings.
*/
static void prvSetupHardware( void );
/*-----------------------------------------------------------*/
/*
* Starts all the other tasks, then starts the scheduler.
*/
int main( void )
{
/* Setup the hardware for use with the Olimex demo board. */
prvSetupHardware();
/* Start the demo/test application tasks. */
vStartIntegerMathTasks( tskIDLE_PRIORITY );
vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED );
vStartLEDFlashTasks( mainLED_TASK_PRIORITY );
vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );
vStartMathTasks( tskIDLE_PRIORITY );
vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );
vStartDynamicPriorityTasks();
vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );
/* Start the check task - which is defined in this file. */
xTaskCreate( vErrorChecks, ( signed portCHAR * ) "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );
/* Now all the tasks have been started - start the scheduler.
NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode.
The processor MUST be in supervisor mode when vTaskStartScheduler is
called. The demo applications included in the FreeRTOS.org download switch
to supervisor mode prior to main being called. If you are not using one of
these demo application projects then ensure Supervisor mode is used here. */
vTaskStartScheduler();
/* Should never reach here! */
return 0;
}
/*-----------------------------------------------------------*/
static void vErrorChecks( void *pvParameters )
{
portTickType xDelayPeriod = mainNO_ERROR_FLASH_PERIOD;
unsigned portLONG ulMemCheckTaskRunningCount;
xTaskHandle xCreatedTask;
/* The parameters are not used in this function. */
( void ) pvParameters;
/* Cycle for ever, delaying then checking all the other tasks are still
operating without error. If an error is detected then the delay period
is decreased from mainNO_ERROR_FLASH_PERIOD to mainERROR_FLASH_PERIOD so
the on board LED flash rate will increase.
In addition to the standard tests the memory allocator is tested through
the dynamic creation and deletion of a task each cycle. Each time the
task is created memory must be allocated for its stack. When the task is
deleted this memory is returned to the heap. If the task cannot be created
then it is likely that the memory allocation failed. */
for( ;; )
{
/* Dynamically create a task - passing ulMemCheckTaskRunningCount as a
parameter. */
ulMemCheckTaskRunningCount = mainCOUNT_INITIAL_VALUE;
xCreatedTask = mainNO_TASK;
if( xTaskCreate( vMemCheckTask, ( signed portCHAR * ) "MEM_CHECK", configMINIMAL_STACK_SIZE, ( void * ) &ulMemCheckTaskRunningCount, tskIDLE_PRIORITY, &xCreatedTask ) != pdPASS )
{
/* Could not create the task - we have probably run out of heap. */
xDelayPeriod = mainERROR_FLASH_PERIOD;
}
/* Delay until it is time to execute again. */
vTaskDelay( xDelayPeriod );
/* Delete the dynamically created task. */
if( xCreatedTask != mainNO_TASK )
{
vTaskDelete( xCreatedTask );
}
/* Check all the standard demo application tasks are executing without
error. ulMemCheckTaskRunningCount is checked to ensure it was
modified by the task just deleted. */
if( prvCheckOtherTasksAreStillRunning( ulMemCheckTaskRunningCount ) != pdPASS )
{
/* An error has been detected in one of the tasks - flash faster. */
xDelayPeriod = mainERROR_FLASH_PERIOD;
}
prvToggleOnBoardLED();
}
}
/*-----------------------------------------------------------*/
static void prvSetupHardware( void )
{
#ifdef RUN_FROM_RAM
/* Remap the interrupt vectors to RAM if we are are running from RAM. */
SCB_MEMMAP = 2;
#endif
/* Configure the RS2332 pins. All other pins remain at their default of 0. */
PCB_PINSEL0 |= mainTX_ENABLE;
PCB_PINSEL0 |= mainRX_ENABLE;
/* Set all GPIO to output other than the P0.14 (BSL), and the JTAG pins.
The JTAG pins are left as input as I'm not sure what will happen if the
Wiggler is connected after powerup - not that it would be a good idea to
do that anyway. */
GPIO_IODIR = ~( mainP0_14 + mainJTAG_PORT );
/* Setup the PLL to multiply the XTAL input by 4. */
SCB_PLLCFG = ( mainPLL_MUL_4 | mainPLL_DIV_1 );
/* Activate the PLL by turning it on then feeding the correct sequence of
bytes. */
SCB_PLLCON = mainPLL_ENABLE;
SCB_PLLFEED = mainPLL_FEED_BYTE1;
SCB_PLLFEED = mainPLL_FEED_BYTE2;
/* Wait for the PLL to lock... */
while( !( SCB_PLLSTAT & mainPLL_LOCK ) );
/* ...before connecting it using the feed sequence again. */
SCB_PLLCON = mainPLL_CONNECT;
SCB_PLLFEED = mainPLL_FEED_BYTE1;
SCB_PLLFEED = mainPLL_FEED_BYTE2;
/* Setup and turn on the MAM. Three cycle access is used due to the fast
PLL used. It is possible faster overall performance could be obtained by
tuning the MAM and PLL settings. */
MAM_TIM = mainMAM_TIM_3;
MAM_CR = mainMAM_MODE_FULL;
/* Setup the peripheral bus to be the same as the PLL output. */
SCB_VPBDIV = mainBUS_CLK_FULL;
/* Initialise LED outputs. */
vParTestInitialise();
}
/*-----------------------------------------------------------*/
void prvToggleOnBoardLED( void )
{
unsigned portLONG ulState;
ulState = GPIO0_IOPIN;
if( ulState & mainON_BOARD_LED_BIT )
{
GPIO_IOCLR = mainON_BOARD_LED_BIT;
}
else
{
GPIO_IOSET = mainON_BOARD_LED_BIT;
}
}
/*-----------------------------------------------------------*/
static portLONG prvCheckOtherTasksAreStillRunning( unsigned portLONG ulMemCheckTaskCount )
{
portLONG lReturn = ( portLONG ) pdPASS;
/* Check all the demo tasks (other than the flash tasks) to ensure
that they are all still running, and that none of them have detected
an error. */
if( xAreIntegerMathsTaskStillRunning() != pdTRUE )
{
lReturn = ( portLONG ) pdFAIL;
}
if( xAreComTestTasksStillRunning() != pdTRUE )
{
lReturn = ( portLONG ) pdFAIL;
}
if( xArePollingQueuesStillRunning() != pdTRUE )
{
lReturn = ( portLONG ) pdFAIL;
}
if( xAreMathsTaskStillRunning() != pdTRUE )
{
lReturn = ( portLONG ) pdFAIL;
}
if( xAreSemaphoreTasksStillRunning() != pdTRUE )
{
lReturn = ( portLONG ) pdFAIL;
}
if( xAreDynamicPriorityTasksStillRunning() != pdTRUE )
{
lReturn = ( portLONG ) pdFAIL;
}
if( xAreBlockingQueuesStillRunning() != pdTRUE )
{
lReturn = ( portLONG ) pdFAIL;
}
if( ulMemCheckTaskCount == mainCOUNT_INITIAL_VALUE )
{
/* The vMemCheckTask did not increment the counter - it must
have failed. */
lReturn = ( portLONG ) pdFAIL;
}
return lReturn;
}
/*-----------------------------------------------------------*/
static void vMemCheckTask( void *pvParameters )
{
unsigned portLONG *pulMemCheckTaskRunningCounter;
void *pvMem1, *pvMem2, *pvMem3;
static portLONG lErrorOccurred = pdFALSE;
/* This task is dynamically created then deleted during each cycle of the
vErrorChecks task to check the operation of the memory allocator. Each time
the task is created memory is allocated for the stack and TCB. Each time
the task is deleted this memory is returned to the heap. This task itself
exercises the allocator by allocating and freeing blocks.
The task executes at the idle priority so does not require a delay.
pulMemCheckTaskRunningCounter is incremented each cycle to indicate to the
vErrorChecks() task that this task is still executing without error. */
pulMemCheckTaskRunningCounter = ( unsigned portLONG * ) pvParameters;
for( ;; )
{
if( lErrorOccurred == pdFALSE )
{
/* We have never seen an error so increment the counter. */
( *pulMemCheckTaskRunningCounter )++;
}
/* Allocate some memory - just to give the allocator some extra
exercise. This has to be in a critical section to ensure the
task does not get deleted while it has memory allocated. */
vTaskSuspendAll();
{
pvMem1 = pvPortMalloc( mainMEM_CHECK_SIZE_1 );
if( pvMem1 == NULL )
{
lErrorOccurred = pdTRUE;
}
else
{
memset( pvMem1, 0xaa, mainMEM_CHECK_SIZE_1 );
vPortFree( pvMem1 );
}
}
xTaskResumeAll();
/* Again - with a different size block. */
vTaskSuspendAll();
{
pvMem2 = pvPortMalloc( mainMEM_CHECK_SIZE_2 );
if( pvMem2 == NULL )
{
lErrorOccurred = pdTRUE;
}
else
{
memset( pvMem2, 0xaa, mainMEM_CHECK_SIZE_2 );
vPortFree( pvMem2 );
}
}
xTaskResumeAll();
/* Again - with a different size block. */
vTaskSuspendAll();
{
pvMem3 = pvPortMalloc( mainMEM_CHECK_SIZE_3 );
if( pvMem3 == NULL )
{
lErrorOccurred = pdTRUE;
}
else
{
memset( pvMem3, 0xaa, mainMEM_CHECK_SIZE_3 );
vPortFree( pvMem3 );
}
}
xTaskResumeAll();
}
}

6
Demo/ARM7_LPC2106_GCC/ram_arm.bat Normal file
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set USE_THUMB_MODE=NO
set DEBUG=-g
set OPTIM=-O0
set RUN_MODE=RUN_FROM_RAM
set LDSCRIPT=lpc2106-ram.ld
make

6
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set USE_THUMB_MODE=YES
set DEBUG=-g
set OPTIM=-O0
set RUN_MODE=RUN_FROM_RAM
set LDSCRIPT=lpc2106-ram.ld
make

18
Demo/ARM7_LPC2106_GCC/readme.txt Normal file
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Use one of the following four batch files to build the demo application:
+ rom_arm.bat
Creates an ARM mode release build suitable for programming into flash.
+ ram_arm.bat
Creates an ARM mode debug build suitable for running from RAM.
+ rom_thumb.bat
Creates a THUMB mode release build suitable for programming into flash.
+ ram_thumb.bat
Creates a THUMB mode debug build suitable for running from RAM.

6
Demo/ARM7_LPC2106_GCC/rom_arm.bat Normal file
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set USE_THUMB_MODE=NO
set DEBUG=
set OPTIM=-O3
set RUN_MODE=RUN_FROM_ROM
set LDSCRIPT=lpc2106-rom.ld
make

6
Demo/ARM7_LPC2106_GCC/rom_thumb.bat Normal file
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set USE_THUMB_MODE=YES
set DEBUG=
set OPTIM=-O3
set RUN_MODE=RUN_FROM_ROM
set LDSCRIPT=lpc2106-rom.ld
make

263
Demo/ARM7_LPC2106_GCC/serial/serial.c Normal file
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/*
FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
FreeRTOS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with FreeRTOS; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes FreeRTOS, without being obliged to provide
the source code for any proprietary components. See the licensing section
of http://www.FreeRTOS.org for full details of how and when the exception
can be applied.
***************************************************************************
See http://www.FreeRTOS.org for documentation, latest information, license
and contact details. Please ensure to read the configuration and relevant
port sections of the online documentation.
***************************************************************************
*/
/*
Changes from V2.4.0
+ Made serial ISR handling more complete and robust.
Changes from V2.4.1
+ Split serial.c into serial.c and serialISR.c. serial.c can be
compiled using ARM or THUMB modes. serialISR.c must always be
compiled in ARM mode.
+ Another small change to cSerialPutChar().
Changed from V2.5.1
+ In cSerialPutChar() an extra check is made to ensure the post to
the queue was successful if then attempting to retrieve the posted
character.
*/
/*
BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR UART0.
This file contains all the serial port components that can be compiled to
either ARM or THUMB mode. Components that must be compiled to ARM mode are
contained in serialISR.c.
*/
/* Standard includes. */
#include <stdlib.h>
/* Scheduler includes. */
#include "FreeRTOS.h"
#include "queue.h"
#include "task.h"
/* Demo application includes. */
#include "serial.h"
/*-----------------------------------------------------------*/
/* Constants to setup and access the UART. */
#define serDLAB ( ( unsigned portCHAR ) 0x80 )
#define serENABLE_INTERRUPTS ( ( unsigned portCHAR ) 0x03 )
#define serNO_PARITY ( ( unsigned portCHAR ) 0x00 )
#define ser1_STOP_BIT ( ( unsigned portCHAR ) 0x00 )
#define ser8_BIT_CHARS ( ( unsigned portCHAR ) 0x03 )
#define serFIFO_ON ( ( unsigned portCHAR ) 0x01 )
#define serCLEAR_FIFO ( ( unsigned portCHAR ) 0x06 )
#define serWANTED_CLOCK_SCALING ( ( unsigned portLONG ) 16 )
/* Constants to setup and access the VIC. */
#define serUART0_VIC_CHANNEL ( ( unsigned portLONG ) 0x0006 )
#define serUART0_VIC_CHANNEL_BIT ( ( unsigned portLONG ) 0x0040 )
#define serUART0_VIC_ENABLE ( ( unsigned portLONG ) 0x0020 )
#define serCLEAR_VIC_INTERRUPT ( ( unsigned portLONG ) 0 )
#define serINVALID_QUEUE ( ( xQueueHandle ) 0 )
#define serHANDLE ( ( xComPortHandle ) 1 )
#define serNO_BLOCK ( ( portTickType ) 0 )
/*-----------------------------------------------------------*/
/* Queues used to hold received characters, and characters waiting to be
transmitted. */
static xQueueHandle xRxedChars;
static xQueueHandle xCharsForTx;
/*-----------------------------------------------------------*/
/* Communication flag between the interrupt service routine and serial API. */
static volatile portLONG *plTHREEmpty;
/*
* The queues are created in serialISR.c as they are used from the ISR.
* Obtain references to the queues and THRE Empty flag.
*/
extern void vSerialISRCreateQueues( unsigned portBASE_TYPE uxQueueLength, xQueueHandle *pxRxedChars, xQueueHandle *pxCharsForTx, portLONG volatile **pplTHREEmptyFlag );
/*-----------------------------------------------------------*/
xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength )
{
unsigned portLONG ulDivisor, ulWantedClock;
xComPortHandle xReturn = serHANDLE;
extern void ( vUART_ISR )( void );
/* The queues are used in the serial ISR routine, so are created from
serialISR.c (which is always compiled to ARM mode. */
vSerialISRCreateQueues( uxQueueLength, &xRxedChars, &xCharsForTx, &plTHREEmpty );
if(
( xRxedChars != serINVALID_QUEUE ) &&
( xCharsForTx != serINVALID_QUEUE ) &&
( ulWantedBaud != ( unsigned portLONG ) 0 )
)
{
portENTER_CRITICAL();
{
/* Setup the baud rate: Calculate the divisor value. */
ulWantedClock = ulWantedBaud * serWANTED_CLOCK_SCALING;
ulDivisor = configCPU_CLOCK_HZ / ulWantedClock;
/* Set the DLAB bit so we can access the divisor. */
UART0_LCR |= serDLAB;
/* Setup the divisor. */
UART0_DLL = ( unsigned portCHAR ) ( ulDivisor & ( unsigned portLONG ) 0xff );
ulDivisor >>= 8;
UART0_DLM = ( unsigned portCHAR ) ( ulDivisor & ( unsigned portLONG ) 0xff );
/* Turn on the FIFO's and clear the buffers. */
UART0_FCR = ( serFIFO_ON | serCLEAR_FIFO );
/* Setup transmission format. */
UART0_LCR = serNO_PARITY | ser1_STOP_BIT | ser8_BIT_CHARS;
/* Setup the VIC for the UART. */
VICIntSelect &= ~( serUART0_VIC_CHANNEL_BIT );
VICIntEnable |= serUART0_VIC_CHANNEL_BIT;
VICVectAddr1 = ( portLONG ) vUART_ISR;
VICVectCntl1 = serUART0_VIC_CHANNEL | serUART0_VIC_ENABLE;
/* Enable UART0 interrupts. */
UART0_IER |= serENABLE_INTERRUPTS;
}
portEXIT_CRITICAL();
}
else
{
xReturn = ( xComPortHandle ) 0;
}
return xReturn;
}
/*-----------------------------------------------------------*/
signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime )
{
/* The port handle is not required as this driver only supports UART0. */
( void ) pxPort;
/* Get the next character from the buffer. Return false if no characters
are available, or arrive before xBlockTime expires. */
if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) )
{
return pdTRUE;
}
else
{
return pdFALSE;
}
}
/*-----------------------------------------------------------*/
void vSerialPutString( xComPortHandle pxPort, const signed portCHAR * const pcString, unsigned portSHORT usStringLength )
{
signed portCHAR *pxNext;
/* NOTE: This implementation does not handle the queue being full as no
block time is used! */
/* The port handle is not required as this driver only supports UART0. */
( void ) pxPort;
( void ) usStringLength;
/* Send each character in the string, one at a time. */
pxNext = ( signed portCHAR * ) pcString;
while( *pxNext )
{
xSerialPutChar( pxPort, *pxNext, serNO_BLOCK );
pxNext++;
}
}
/*-----------------------------------------------------------*/
signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime )
{
signed portBASE_TYPE xReturn;
/* This demo driver only supports one port so the parameter is not used. */
( void ) pxPort;
portENTER_CRITICAL();
{
/* Is there space to write directly to the UART? */
if( *plTHREEmpty == ( portLONG ) pdTRUE )
{
/* We wrote the character directly to the UART, so was
successful. */
*plTHREEmpty = pdFALSE;
UART0_THR = cOutChar;
xReturn = pdPASS;
}
else
{
/* We cannot write directly to the UART, so queue the character.
Block for a maximum of xBlockTime if there is no space in the
queue. */
xReturn = xQueueSend( xCharsForTx, &cOutChar, xBlockTime );
/* Depending on queue sizing and task prioritisation: While we
were blocked waiting to post interrupts were not disabled. It is
possible that the serial ISR has emptied the Tx queue, in which
case we need to start the Tx off again. */
if( ( *plTHREEmpty == ( portLONG ) pdTRUE ) && ( xReturn == pdPASS ) )
{
xQueueReceive( xCharsForTx, &cOutChar, serNO_BLOCK );
*plTHREEmpty = pdFALSE;
UART0_THR = cOutChar;
}
}
}
portEXIT_CRITICAL();
return xReturn;
}
/*-----------------------------------------------------------*/
void vSerialClose( xComPortHandle xPort )
{
/* Not supported as not required by the demo application. */
( void ) xPort;
}
/*-----------------------------------------------------------*/

163
Demo/ARM7_LPC2106_GCC/serial/serialISR.c Normal file
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/*
FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
FreeRTOS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with FreeRTOS; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes FreeRTOS, without being obliged to provide
the source code for any proprietary components. See the licensing section
of http://www.FreeRTOS.org for full details of how and when the exception
can be applied.
***************************************************************************
See http://www.FreeRTOS.org for documentation, latest information, license
and contact details. Please ensure to read the configuration and relevant
port sections of the online documentation.
***************************************************************************
*/
/*
BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR UART0.
This file contains all the serial port components that must be compiled
to ARM mode. The components that can be compiled to either ARM or THUMB
mode are contained in serial.c.
*/
/* Standard includes. */
#include <stdlib.h>
/* Scheduler includes. */
#include "FreeRTOS.h"
#include "queue.h"
#include "task.h"
/* Demo application includes. */
#include "serial.h"
/*-----------------------------------------------------------*/
/* Constant to access the VIC. */
#define serCLEAR_VIC_INTERRUPT ( ( unsigned portLONG ) 0 )
/* Constants to determine the ISR source. */
#define serSOURCE_THRE ( ( unsigned portCHAR ) 0x02 )
#define serSOURCE_RX_TIMEOUT ( ( unsigned portCHAR ) 0x0c )
#define serSOURCE_ERROR ( ( unsigned portCHAR ) 0x06 )
#define serSOURCE_RX ( ( unsigned portCHAR ) 0x04 )
#define serINTERRUPT_SOURCE_MASK ( ( unsigned portCHAR ) 0x0f )
/* Queues used to hold received characters, and characters waiting to be
transmitted. */
static xQueueHandle xRxedChars;
static xQueueHandle xCharsForTx;
static volatile portLONG lTHREEmpty;
/*-----------------------------------------------------------*/
/*
* The queues are created in serialISR.c as they are used from the ISR.
* Obtain references to the queues and THRE Empty flag.
*/
void vSerialISRCreateQueues( unsigned portBASE_TYPE uxQueueLength, xQueueHandle *pxRxedChars, xQueueHandle *pxCharsForTx, portLONG volatile **pplTHREEmptyFlag );
/* UART0 interrupt service routine. This can cause a context switch so MUST
be declared "naked". */
void vUART_ISR( void ) __attribute__ ((naked));
/*-----------------------------------------------------------*/
void vSerialISRCreateQueues( unsigned portBASE_TYPE uxQueueLength, xQueueHandle *pxRxedChars,
xQueueHandle *pxCharsForTx, portLONG volatile **pplTHREEmptyFlag )
{
/* Create the queues used to hold Rx and Tx characters. */
xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );
xCharsForTx = xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );
/* Pass back a reference to the queues so the serial API file can
post/receive characters. */
*pxRxedChars = xRxedChars;
*pxCharsForTx = xCharsForTx;
/* Initialise the THRE empty flag - and pass back a reference. */
lTHREEmpty = ( portLONG ) pdTRUE;
*pplTHREEmptyFlag = &lTHREEmpty;
}
/*-----------------------------------------------------------*/
void vUART_ISR( void )
{
/* This ISR can cause a context switch, so the first statement must be a
call to the portENTER_SWITCHING_ISR() macro. This must be BEFORE any
variable declarations. */
portENTER_SWITCHING_ISR();
/* Now we can declare the local variables. */
signed portCHAR cChar;
portBASE_TYPE xTaskWokenByTx = pdFALSE, xTaskWokenByRx = pdFALSE;
/* What caused the interrupt? */
switch( UART0_IIR & serINTERRUPT_SOURCE_MASK )
{
case serSOURCE_ERROR : /* Not handling this, but clear the interrupt. */
cChar = UART0_LSR;
break;
case serSOURCE_THRE : /* The THRE is empty. If there is another
character in the Tx queue, send it now. */
if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xTaskWokenByTx ) == pdTRUE )
{
UART0_THR = cChar;
}
else
{
/* There are no further characters
queued to send so we can indicate
that the THRE is available. */
lTHREEmpty = pdTRUE;
}
break;
case serSOURCE_RX_TIMEOUT :
case serSOURCE_RX : /* A character was received. Place it in
the queue of received characters. */
cChar = UART0_RBR;
if( xQueueSendFromISR( xRxedChars, &cChar, ( portBASE_TYPE ) pdFALSE ) )
{
xTaskWokenByRx = pdTRUE;
}
break;
default : /* There is nothing to do, leave the ISR. */
break;
}
/* Clear the ISR in the VIC. */
VICVectAddr = serCLEAR_VIC_INTERRUPT;
/* Exit the ISR. If a task was woken by either a character being received
or transmitted then a context switch will occur. */
portEXIT_SWITCHING_ISR( ( xTaskWokenByTx || xTaskWokenByRx ) );
}
/*-----------------------------------------------------------*/

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/*
FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
FreeRTOS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with FreeRTOS; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes FreeRTOS, without being obliged to provide
the source code for any proprietary components. See the licensing section
of http://www.FreeRTOS.org for full details of how and when the exception
can be applied.
***************************************************************************
See http://www.FreeRTOS.org for documentation, latest information, license
and contact details. Please ensure to read the configuration and relevant
port sections of the online documentation.
***************************************************************************
*/
#ifndef FREERTOS_CONFIG_H
#define FREERTOS_CONFIG_H
/* Hardware specifics. */
#include <iolpc2129.h>
/*-----------------------------------------------------------
* Application specific definitions.
*
* These definitions should be adjusted for your particular hardware and
* application requirements.
*
* THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
* FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
*----------------------------------------------------------*/
#define configUSE_PREEMPTION 1
#define configUSE_IDLE_HOOK 0
#define configUSE_TICK_HOOK 0
#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 60000000 ) /* =12.0MHz xtal multiplied by 5 using the PLL. */
#define configTICK_RATE_HZ ( ( portTickType ) 1000 )
#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 )
#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 100 )
#define configTOTAL_HEAP_SIZE ( ( size_t ) 14200 )
#define configMAX_TASK_NAME_LEN ( 16 )
#define configUSE_TRACE_FACILITY 0
#define configUSE_16_BIT_TICKS 0
#define configIDLE_SHOULD_YIELD 1
/* Co-routine definitions. */
#define configUSE_CO_ROUTINES 0
#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
/* Set the following definitions to 1 to include the API function, or zero
to exclude the API function. */
#define INCLUDE_vTaskPrioritySet 1
#define INCLUDE_uxTaskPriorityGet 1
#define INCLUDE_vTaskDelete 0
#define INCLUDE_vTaskCleanUpResources 0
#define INCLUDE_vTaskSuspend 1
#define INCLUDE_vTaskDelayUntil 1
#define INCLUDE_vTaskDelay 1
#endif /* FREERTOS_CONFIG_H */

102
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/*
FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
FreeRTOS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with FreeRTOS; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes FreeRTOS, without being obliged to provide
the source code for any proprietary components. See the licensing section
of http://www.FreeRTOS.org for full details of how and when the exception
can be applied.
***************************************************************************
See http://www.FreeRTOS.org for documentation, latest information, license
and contact details. Please ensure to read the configuration and relevant
port sections of the online documentation.
***************************************************************************
*/
/*-----------------------------------------------------------
* Simple parallel port IO routines for the LED's.
*-----------------------------------------------------------*/
/* Scheduler includes. */
#include "FreeRTOS.h"
/* Demo application includes. */
#include "partest.h"
/* Board specific defines. */
#define partstFIRST_IO ( ( unsigned portLONG ) 0x10000 )
#define partstNUM_LEDS ( 8 )
/*-----------------------------------------------------------*/
void vParTestInitialise( void )
{
/* The ports are setup within prvInitialiseHardware(), called by main(). */
}
/*-----------------------------------------------------------*/
void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue )
{
unsigned portLONG ulLED = partstFIRST_IO;
if( uxLED < partstNUM_LEDS )
{
/* Rotate to the wanted bit of port 1. Only P16 to P23 have an LED
attached. */
ulLED <<= ( unsigned portLONG ) uxLED;
/* Set or clear the output. */
if( xValue )
{
IO1SET = ulLED;
}
else
{
IO1CLR = ulLED;
}
}
}
/*-----------------------------------------------------------*/
void vParTestToggleLED( unsigned portBASE_TYPE uxLED )
{
unsigned portLONG ulLED = partstFIRST_IO, ulCurrentState;
if( uxLED < partstNUM_LEDS )
{
/* Rotate to the wanted bit of port 1. Only P10 to P13 have an LED
attached. */
ulLED <<= ( unsigned portLONG ) uxLED;
/* If this bit is already set, clear it, and visa versa. */
ulCurrentState = IO1PIN;
if( ulCurrentState & ulLED )
{
IO1CLR = ulLED;
}
else
{
IO1SET = ulLED;
}
}
}

173
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;-----------------------------------------------------------------------------
; This file contains the startup code used by the ICCARM C compiler.
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; All code in the modules (except ?RESET) will be placed in the ICODE segment.
;
; $Revision: 1.56 $
;
;-----------------------------------------------------------------------------
;
; Naming covention of labels in this file:
;
; ?xxx - External labels only accessed from assembler.
; __xxx - External labels accessed from or defined in C.
; xxx - Labels local to one module (note: this file contains
; several modules).
; main - The starting point of the user program.
;
;---------------------------------------------------------------
; Macros and definitions for the whole file
;---------------------------------------------------------------
; Mode, correspords to bits 0-5 in CPSR
MODE_BITS DEFINE 0x1F ; Bit mask for mode bits in CPSR
USR_MODE DEFINE 0x10 ; User mode
FIQ_MODE DEFINE 0x11 ; Fast Interrupt Request mode
IRQ_MODE DEFINE 0x12 ; Interrupt Request mode
SVC_MODE DEFINE 0x13 ; Supervisor mode
ABT_MODE DEFINE 0x17 ; Abort mode
UND_MODE DEFINE 0x1B ; Undefined Instruction mode
SYS_MODE DEFINE 0x1F ; System mode
I_Bit DEFINE 0x80 ; IRQ Disable Bit
F_Bit DEFINE 0x40 ; FIQ Disable Bit
;---------------------------------------------------------------
; ?RESET
; Reset Vector.
; Normally, segment INTVEC is linked at address 0.
; For debugging purposes, INTVEC may be placed at other
; addresses.
; A debugger that honors the entry point will start the
; program in a normal way even if INTVEC is not at address 0.
;---------------------------------------------------------------
MODULE ?RESET
COMMON INTVEC:CODE:NOROOT(2)
PUBLIC __program_start
EXTERN ?cstartup
EXTERN undef_handler, swi_handler, prefetch_handler
EXTERN data_handler, irq_handler, fiq_handler
EXTERN vPortYieldProcessor
CODE32 ; Always ARM mode after reset
__program_start
org 0x00
B InitReset ; 0x00 Reset handler
undefvec:
B undefvec ; 0x04 Undefined Instruction
swivec:
B vPortYieldProcessor ; 0x08 Software Interrupt
pabtvec:
B pabtvec ; 0x0C Prefetch Abort
dabtvec:
B dabtvec ; 0x10 Data Abort
rsvdvec:
B rsvdvec ; 0x14 reserved
irqvec:
LDR PC, [PC, #-0xFF0] ; Jump directly to the address given by the AIC
fiqvec: ; 0x1c FIQ
;---------------------------------------------------------------
; ?CSTARTUP
;---------------------------------------------------------------
RSEG IRQ_STACK:DATA(2)
RSEG SVC_STACK:DATA:NOROOT(2)
RSEG CSTACK:DATA(2)
RSEG ICODE:CODE:NOROOT(2)
EXTERN ?main
; Execution starts here.
; After a reset, the mode is ARM, Supervisor, interrupts disabled.
CODE32
InitReset
; Add initialization needed before setup of stackpointers here
; Initialize the stack pointers.
; The pattern below can be used for any of the exception stacks:
; FIQ, IRQ, SVC, ABT, UND, SYS.
; The USR mode uses the same stack as SYS.
; The stack segments must be defined in the linker command file,
; and be declared above.
mrs r0,cpsr ; Original PSR value
bic r0,r0,#MODE_BITS ; Clear the mode bits
orr r0,r0,#IRQ_MODE ; Set IRQ mode bits
msr cpsr_c,r0 ; Change the mode
ldr sp,=SFE(IRQ_STACK) & 0xFFFFFFF8 ; End of IRQ_STACK
bic r0,r0,#MODE_BITS ; Clear the mode bits
orr r0,r0,#SYS_MODE ; Set System mode bits
msr cpsr_c,r0 ; Change the mode
ldr sp,=SFE(CSTACK) & 0xFFFFFFF8 ; End of CSTACK
bic r0,r0,#MODE_BITS ; Clear the mode bits
orr r0,r0,#SVC_MODE ; Set System mode bits
msr cpsr_c,r0 ; Change the mode
ldr sp,=SFE(SVC_STACK) & 0xFFFFFFF8 ; End of CSTACK
; Must start in supervisor mode.
MSR CPSR_c, #SVC_MODE|I_Bit|F_Bit
; Add more initialization here
; Continue to ?main for more IAR specific system startup
ldr r0,=?main
bx r0
;---------------------------------------------------------------
; ?EXEPTION_VECTOR
; This module is only linked if needed for closing files.
;---------------------------------------------------------------
PUBLIC AT91F_Default_FIQ_handler
PUBLIC AT91F_Default_IRQ_handler
PUBLIC AT91F_Spurious_handler
CODE32 ; Always ARM mode after exeption
AT91F_Default_FIQ_handler
b AT91F_Default_FIQ_handler
AT91F_Default_IRQ_handler
b AT91F_Default_IRQ_handler
AT91F_Spurious_handler
b AT91F_Spurious_handler
ENDMOD
END
ENDMOD
END

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/*
FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
FreeRTOS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with FreeRTOS; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes FreeRTOS, without being obliged to provide
the source code for any proprietary components. See the licensing section
of http://www.FreeRTOS.org for full details of how and when the exception
can be applied.
***************************************************************************
See http://www.FreeRTOS.org for documentation, latest information, license
and contact details. Please ensure to read the configuration and relevant
port sections of the online documentation.
***************************************************************************
*/
/*
NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode.
The processor MUST be in supervisor mode when vTaskStartScheduler is
called. The demo applications included in the FreeRTOS.org download switch
to supervisor mode prior to main being called. If you are not using one of
these demo application projects then ensure Supervisor mode is used.
*/
/*
* Creates all the demo application tasks, then starts the scheduler. The WEB
* documentation provides more details of the demo application tasks.
*
* Main.c also creates a task called "Check". This only executes every three
* seconds but has the highest priority so is guaranteed to get processor time.
* Its main function is to check that all the other tasks are still operational.
* Each task (other than the "flash" tasks) maintains a unique count that is
* incremented each time the task successfully completes its function. Should
* any error occur within such a task the count is permanently halted. The
* check task inspects the count of each task to ensure it has changed since
* the last time the check task executed. If all the count variables have
* changed all the tasks are still executing error free, and the check task
* toggles the onboard LED. Should any task contain an error at any time
* the LED toggle rate will change from 3 seconds to 500ms.
*
*/
/* Standard includes. */
#include <stdlib.h>
/* Scheduler includes. */
#include "FreeRTOS.h"
#include "task.h"
/* Demo application includes. */
#include "flash.h"
#include "integer.h"
#include "PollQ.h"
#include "BlockQ.h"
#include "semtest.h"
#include "dynamic.h"
#include "partest.h"
#include "comtest2.h"
/* Priorities for the demo application tasks. */
#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 )
#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 )
#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 4 )
#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 )
#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 )
#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 )
/* Constants required by the 'Check' task. */
#define mainNO_ERROR_FLASH_PERIOD ( ( portTickType ) 3000 / portTICK_RATE_MS )
#define mainERROR_FLASH_PERIOD ( ( portTickType ) 500 / portTICK_RATE_MS )
#define mainCHECK_TASK_LED ( 7 )
/* Constants for the ComTest tasks. */
#define mainCOM_TEST_BAUD_RATE ( ( unsigned portLONG ) 115200 )
#define mainCOM_TEST_LED ( 4 )
#define mainTX_ENABLE ( ( unsigned portLONG ) 0x0001 )
#define mainRX_ENABLE ( ( unsigned portLONG ) 0x0004 )
/* Constants to setup the PLL. */
#define mainPLL_MUL_4 ( ( unsigned portCHAR ) 0x0003 )
#define mainPLL_DIV_1 ( ( unsigned portCHAR ) 0x0000 )
#define mainPLL_ENABLE ( ( unsigned portCHAR ) 0x0001 )
#define mainPLL_CONNECT ( ( unsigned portCHAR ) 0x0003 )
#define mainPLL_FEED_BYTE1 ( ( unsigned portCHAR ) 0xaa )
#define mainPLL_FEED_BYTE2 ( ( unsigned portCHAR ) 0x55 )
#define mainPLL_LOCK ( ( unsigned portLONG ) 0x0400 )
/* Constants to setup the MAM. */
#define mainMAM_TIM_3 ( ( unsigned portCHAR ) 0x03 )
#define mainMAM_MODE_FULL ( ( unsigned portCHAR ) 0x02 )
/* Constants to setup the peripheral bus. */
#define mainBUS_CLK_FULL ( ( unsigned portCHAR ) 0x01 )
/* And finally, constant to setup the port for the LED's. */
#define mainLED_TO_OUTPUT ( ( unsigned portLONG ) 0xff0000 )
/*
* The task that executes at the highest priority and calls
* prvCheckOtherTasksAreStillRunning(). See the description at the top
* of the file.
*/
static void vErrorChecks( void *pvParameters );
/*
* Configures the processor for use with this demo.
*/
static void prvSetupHardware( void );
/*
* Checks that all the demo application tasks are still executing without error
* - as described at the top of the file.
*/
static portLONG prvCheckOtherTasksAreStillRunning( void );
/*-----------------------------------------------------------*/
/*
* Starts all the other tasks, then starts the scheduler.
*/
void main( void )
{
/* Setup the processor. */
prvSetupHardware();
/* Start all the standard demo application tasks. */
vStartIntegerMathTasks( tskIDLE_PRIORITY );
vStartLEDFlashTasks( mainLED_TASK_PRIORITY );
vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );
vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );
vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );
vStartDynamicPriorityTasks();
vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED );
/* Start the check task - which is defined in this file. */
xTaskCreate( vErrorChecks, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );
/* Start the scheduler.
NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode.
The processor MUST be in supervisor mode when vTaskStartScheduler is
called. The demo applications included in the FreeRTOS.org download switch
to supervisor mode prior to main being called. If you are not using one of
these demo application projects then ensure Supervisor mode is used here.
*/
vTaskStartScheduler();
/* We should never get here as control is now taken by the scheduler. */
return;
}
/*-----------------------------------------------------------*/
static void prvSetupHardware( void )
{
/* Setup the PLL to multiply the XTAL input by 4. */
PLLCFG = ( mainPLL_MUL_4 | mainPLL_DIV_1 );
/* Activate the PLL by turning it on then feeding the correct sequence of
bytes. */
PLLCON = mainPLL_ENABLE;
PLLFEED = mainPLL_FEED_BYTE1;
PLLFEED = mainPLL_FEED_BYTE2;
/* Wait for the PLL to lock... */
while( !( PLLSTAT & mainPLL_LOCK ) );
/* ...before connecting it using the feed sequence again. */
PLLCON = mainPLL_CONNECT;
PLLFEED = mainPLL_FEED_BYTE1;
PLLFEED = mainPLL_FEED_BYTE2;
/* Setup and turn on the MAM. Three cycle access is used due to the fast
PLL used. It is possible faster overall performance could be obtained by
tuning the MAM and PLL settings. */
MAMTIM = mainMAM_TIM_3;
MAMCR = mainMAM_MODE_FULL;
/* Setup the peripheral bus to be the same as the PLL output. */
VPBDIV = mainBUS_CLK_FULL;
/* Configure the RS2332 pins. All other pins remain at their default of 0. */
PINSEL0 |= mainTX_ENABLE;
PINSEL0 |= mainRX_ENABLE;
/* LED pins need to be output. */
IO1DIR = mainLED_TO_OUTPUT;
/* Setup the peripheral bus to be the same as the PLL output. */
VPBDIV = mainBUS_CLK_FULL;
}
/*-----------------------------------------------------------*/
static void vErrorChecks( void *pvParameters )
{
portTickType xDelayPeriod = mainNO_ERROR_FLASH_PERIOD;
/* The parameters are not used in this task. */
( void ) pvParameters;
/* Cycle for ever, delaying then checking all the other tasks are still
operating without error. If an error is detected then the delay period
is decreased from mainNO_ERROR_FLASH_PERIOD to mainERROR_FLASH_PERIOD so
the on board LED flash rate will increase. */
for( ;; )
{
/* Delay until it is time to execute again. */
vTaskDelay( xDelayPeriod );
/* Check all the standard demo application tasks are executing without
error. */
if( prvCheckOtherTasksAreStillRunning() != pdPASS )
{
/* An error has been detected in one of the tasks - flash faster. */
xDelayPeriod = mainERROR_FLASH_PERIOD;
}
vParTestToggleLED( mainCHECK_TASK_LED );
}
}
/*-----------------------------------------------------------*/
static portLONG prvCheckOtherTasksAreStillRunning( void )
{
portLONG lReturn = ( portLONG ) pdPASS;
/* Check all the demo tasks (other than the flash tasks) to ensure
that they are all still running, and that none of them have detected
an error. */
if( xAreIntegerMathsTaskStillRunning() != pdTRUE )
{
lReturn = ( portLONG ) pdFAIL;
}
if( xArePollingQueuesStillRunning() != pdTRUE )
{
lReturn = ( portLONG ) pdFAIL;
}
if( xAreSemaphoreTasksStillRunning() != pdTRUE )
{
lReturn = ( portLONG ) pdFAIL;
}
if( xAreBlockingQueuesStillRunning() != pdTRUE )
{
lReturn = ( portLONG ) pdFAIL;
}
if( xAreComTestTasksStillRunning() != pdTRUE )
{
lReturn = ( portLONG ) pdFAIL;
}
if( xAreDynamicPriorityTasksStillRunning() != pdTRUE )
{
lReturn = ( portLONG ) pdFAIL;
}
return lReturn;
}
/*-----------------------------------------------------------*/

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//*************************************************************************
// XLINK command file template for EWARM/ICCARM
//
// Usage: xlink -f lnkarm <your_object_file(s)>
// -s <program start label> <C/C++ runtime library>
//
// $Revision: 1.1 $
//*************************************************************************
//*************************************************************************
//
// -------------
// Code segments - may be placed anywhere in memory.
// -------------
//
// INTVEC -- Exception vector table.
// SWITAB -- Software interrupt vector table.
// ICODE -- Startup (cstartup) and exception code.
// DIFUNCT -- Dynamic initialization vectors used by C++.
// CODE -- Compiler generated code.
// CODE_I -- Compiler generated code declared __ramfunc (executes in RAM)
// CODE_ID -- Initializer for CODE_I (ROM).
//
// -------------
// Data segments - may be placed anywhere in memory.
// -------------
//
// CSTACK -- The stack used by C/C++ programs (system and user mode).
// IRQ_STACK -- The stack used by IRQ service routines.
// SVC_STACK -- The stack used in supervisor mode
// (Define other exception stacks as needed for
// FIQ, ABT, UND).
// HEAP -- The heap used by malloc and free in C and new and
// delete in C++.
// INITTAB -- Table containing addresses and sizes of segments that
// need to be initialized at startup (by cstartup).
// CHECKSUM -- The linker places checksum byte(s) in this segment,
// when the -J linker command line option is used.
// DATA_y -- Data objects.
//
// Where _y can be one of:
//
// _AN -- Holds uninitialized located objects, i.e. objects with
// an absolute location given by the @ operator or the
// #pragma location directive. Since these segments
// contain objects which already have a fixed address,
// they should not be mentioned in this linker command
// file.
// _C -- Constants (ROM).
// _I -- Initialized data (RAM).
// _ID -- The original content of _I (copied to _I by cstartup) (ROM).
// _N -- Uninitialized data (RAM).
// _Z -- Zero initialized data (RAM).
//
// Note: Be sure to use end values for the defined address ranges.
// Otherwise, the linker may allocate space outside the
// intended memory range.
//*************************************************************************
//************************************************
// Inform the linker about the CPU family used.
//************************************************
-carm
//*************************************************************************
// Segment placement - General information
//
// All numbers in the segment placement command lines below are interpreted
// as hexadecimal unless they are immediately preceded by a '.', which
// denotes decimal notation.
//
// When specifying the segment placement using the -P instead of the -Z
// option, the linker is free to split each segment into its segment parts
// and randomly place these parts within the given ranges in order to
// achieve a more efficient memory usage. One disadvantage, however, is
// that it is not possible to find the start or end address (using
// the assembler operators .sfb./.sfe.) of a segment which has been split
// and reformed.
//
// When generating an output file which is to be used for programming
// external ROM/Flash devices, the -M linker option is very useful
// (see xlink.pdf for details).
//*************************************************************************
//*************************************************************************
// Read-only segments mapped to ROM.
//*************************************************************************
-DROMSTART=00000000
-DROMEND=00001ffff
//************************************************
// Address range for reset and exception
// vectors (INTVEC).
// The vector area is 32 bytes,
// an additional 32 bytes is allocated for the
// constant table used by ldr PC in cstartup.s79.
//************************************************
-Z(CODE)INTVEC=00000000-0000003f
//************************************************
// Startup code and exception routines (ICODE).
//************************************************
-Z(CODE)ICODE,DIFUNCT=ROMSTART-ROMEND
-Z(CODE)SWITAB=ROMSTART-ROMEND
//************************************************
// Code segments may be placed anywhere.
//************************************************
-Z(CODE)CODE=ROMSTART-ROMEND
//************************************************
// Original ROM location for __ramfunc code copied
// to and executed from RAM.
//************************************************
-Z(CONST)CODE_ID=ROMSTART-ROMEND
//************************************************
// Various constants and initializers.
//************************************************
-Z(CONST)INITTAB,DATA_ID,DATA_C=ROMSTART-ROMEND
-Z(CONST)CHECKSUM=ROMSTART-ROMEND
//*************************************************************************
// Read/write segments mapped to RAM.
//*************************************************************************
-DRAMSTART=40000000
-DRAMEND=40003fff
//************************************************
// Data segments.
//************************************************
-Z(DATA)DATA_I,DATA_Z,DATA_N=RAMSTART-RAMEND
//************************************************
// __ramfunc code copied to and executed from RAM.
//************************************************
-Z(DATA)CODE_I=RAMSTART-RAMEND
//************************************************
// ICCARM produces code for __ramfunc functions in
// CODE_I segments. The -Q XLINK command line
// option redirects XLINK to emit the code in the
// CODE_ID segment instead, but to keep symbol and
// debug information associated with the CODE_I
// segment, where the code will execute.
//************************************************
-QCODE_I=CODE_ID
//*************************************************************************
// Stack and heap segments.
//*************************************************************************
-D_CSTACK_SIZE=200
-D_SVC_STACK_SIZE=190
-D_IRQ_STACK_SIZE=190
-D_HEAP_SIZE=4
-Z(DATA)CSTACK+_CSTACK_SIZE=RAMSTART-RAMEND
-Z(DATA)SVC_STACK+_SVC_STACK_SIZE=RAMSTART-RAMEND
-Z(DATA)IRQ_STACK+_IRQ_STACK_SIZE,HEAP+_HEAP_SIZE=RAMSTART-RAMEND
//*************************************************************************
// ELF/DWARF support.
//
// Uncomment the line "-Felf" below to generate ELF/DWARF output.
// Available format specifiers are:
//
// "-yn": Suppress DWARF debug output
// "-yp": Multiple ELF program sections
// "-yas": Format suitable for debuggers from ARM Ltd (also sets -p flag)
//
// "-Felf" and the format specifiers can also be supplied directly as
// command line options, or selected from the Xlink Output tab in the
// IAR Embedded Workbench.
//*************************************************************************
// -Felf

913
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<name>Flash Bin</name>
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<name>MACRAIGOR_ID</name>
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Demo/ARM7_LPC2129_IAR/rtosdemo.ewp Normal file
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Demo/ARM7_LPC2129_IAR/rtosdemo.eww Normal file
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<?xml version="1.0" encoding="iso-8859-1"?>
<workspace>
<project>
<path>$WS_DIR$\rtosdemo.ewp</path>
</project>
<batchBuild/>
</workspace>

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Demo/ARM7_LPC2129_IAR/serial/serial.c Normal file
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/*
FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
FreeRTOS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with FreeRTOS; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes FreeRTOS, without being obliged to provide
the source code for any proprietary components. See the licensing section
of http://www.FreeRTOS.org for full details of how and when the exception
can be applied.
***************************************************************************
See http://www.FreeRTOS.org for documentation, latest information, license
and contact details. Please ensure to read the configuration and relevant
port sections of the online documentation.
***************************************************************************
*/
/*
BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR UART0.
*/
/* Standard includes. */
#include <stdlib.h>
/* Scheduler includes. */
#include "FreeRTOS.h"
#include "queue.h"
#include "task.h"
/* Demo application includes. */
#include "serial.h"
/*-----------------------------------------------------------*/
/* Constants to setup and access the UART. */
#define serDLAB ( ( unsigned portCHAR ) 0x80 )
#define serENABLE_INTERRUPTS ( ( unsigned portCHAR ) 0x03 )
#define serNO_PARITY ( ( unsigned portCHAR ) 0x00 )
#define ser1_STOP_BIT ( ( unsigned portCHAR ) 0x00 )
#define ser8_BIT_CHARS ( ( unsigned portCHAR ) 0x03 )
#define serFIFO_ON ( ( unsigned portCHAR ) 0x01 )
#define serCLEAR_FIFO ( ( unsigned portCHAR ) 0x06 )
#define serWANTED_CLOCK_SCALING ( ( unsigned portLONG ) 16 )
/* Constants to setup and access the VIC. */
#define serU0VIC_CHANNEL ( ( unsigned portLONG ) 0x0006 )
#define serU0VIC_CHANNEL_BIT ( ( unsigned portLONG ) 0x0040 )
#define serU0VIC_ENABLE ( ( unsigned portLONG ) 0x0020 )
#define serCLEAR_VIC_INTERRUPT ( ( unsigned portLONG ) 0 )
/* Constants to determine the ISR source. */
#define serSOURCE_THRE ( ( unsigned portCHAR ) 0x02 )
#define serSOURCE_RX_TIMEOUT ( ( unsigned portCHAR ) 0x0c )
#define serSOURCE_ERROR ( ( unsigned portCHAR ) 0x06 )
#define serSOURCE_RX ( ( unsigned portCHAR ) 0x04 )
#define serINTERRUPT_SOURCE_MASK ( ( unsigned portCHAR ) 0x0f )
/* Misc. */
#define serINVALID_QUEUE ( ( xQueueHandle ) 0 )
#define serHANDLE ( ( xComPortHandle ) 1 )
#define serNO_BLOCK ( ( portTickType ) 0 )
/*-----------------------------------------------------------*/
/* Queues used to hold received characters, and characters waiting to be
transmitted. */
static xQueueHandle xRxedChars;
static xQueueHandle xCharsForTx;
static volatile portLONG lTHREEmpty = pdFALSE;
/*-----------------------------------------------------------*/
/* The ISR. Note that this is called by a wrapper written in the file
SerialISR.s79. See the WEB documentation for this port for further
information. */
__arm void vSerialISR( void );
/*-----------------------------------------------------------*/
xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength )
{
unsigned portLONG ulDivisor, ulWantedClock;
xComPortHandle xReturn = serHANDLE;
extern void ( vSerialISREntry) ( void );
/* Create the queues used to hold Rx and Tx characters. */
xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );
xCharsForTx = xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );
/* Initialise the THRE empty flag. */
lTHREEmpty = pdTRUE;
if(
( xRxedChars != serINVALID_QUEUE ) &&
( xCharsForTx != serINVALID_QUEUE ) &&
( ulWantedBaud != ( unsigned portLONG ) 0 )
)
{
portENTER_CRITICAL();
{
/* Setup the baud rate: Calculate the divisor value. */
ulWantedClock = ulWantedBaud * serWANTED_CLOCK_SCALING;
ulDivisor = configCPU_CLOCK_HZ / ulWantedClock;
/* Set the DLAB bit so we can access the divisor. */
U0LCR |= serDLAB;
/* Setup the divisor. */
U0DLL = ( unsigned portCHAR ) ( ulDivisor & ( unsigned portLONG ) 0xff );
ulDivisor >>= 8;
U0DLM = ( unsigned portCHAR ) ( ulDivisor & ( unsigned portLONG ) 0xff );
/* Turn on the FIFO's and clear the buffers. */
U0FCR = ( serFIFO_ON | serCLEAR_FIFO );
/* Setup transmission format. */
U0LCR = serNO_PARITY | ser1_STOP_BIT | ser8_BIT_CHARS;
/* Setup the VIC for the UART. */
VICIntSelect &= ~( serU0VIC_CHANNEL_BIT );
VICIntEnable |= serU0VIC_CHANNEL_BIT;
VICVectAddr1 = ( unsigned portLONG ) vSerialISREntry;
VICVectCntl1 = serU0VIC_CHANNEL | serU0VIC_ENABLE;
/* Enable UART0 interrupts. */
U0IER |= serENABLE_INTERRUPTS;
}
portEXIT_CRITICAL();
xReturn = ( xComPortHandle ) 1;
}
else
{
xReturn = ( xComPortHandle ) 0;
}
return xReturn;
}
/*-----------------------------------------------------------*/
signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime )
{
/* The port handle is not required as this driver only supports UART0. */
( void ) pxPort;
/* Get the next character from the buffer. Return false if no characters
are available, or arrive before xBlockTime expires. */
if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) )
{
return pdTRUE;
}
else
{
return pdFALSE;
}
}
/*-----------------------------------------------------------*/
void vSerialPutString( xComPortHandle pxPort, const signed portCHAR * const pcString, unsigned portSHORT usStringLength )
{
signed portCHAR *pxNext;
/* NOTE: This implementation does not handle the queue being full as no
block time is used! */
/* The port handle is not required as this driver only supports UART0. */
( void ) pxPort;
( void ) usStringLength;
/* Send each character in the string, one at a time. */
pxNext = ( signed portCHAR * ) pcString;
while( *pxNext )
{
xSerialPutChar( pxPort, *pxNext, serNO_BLOCK );
pxNext++;
}
}
/*-----------------------------------------------------------*/
signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime )
{
signed portBASE_TYPE xReturn;
/* The port handle is not required as this driver only supports UART0. */
( void ) pxPort;
portENTER_CRITICAL();
{
/* Is there space to write directly to the UART? */
if( lTHREEmpty == ( portLONG ) pdTRUE )
{
/* We wrote the character directly to the UART, so was
successful. */
lTHREEmpty = pdFALSE;
U0THR = cOutChar;
xReturn = pdPASS;
}
else
{
/* We cannot write directly to the UART, so queue the character.
Block for a maximum of xBlockTime if there is no space in the
queue. It is ok to block within a critical section as each
task has it's own critical section management. */
xReturn = xQueueSend( xCharsForTx, &cOutChar, xBlockTime );
/* Depending on queue sizing and task prioritisation: While we
were blocked waiting to post interrupts were not disabled. It is
possible that the serial ISR has emptied the Tx queue, in which
case we need to start the Tx off again. */
if( lTHREEmpty == ( portLONG ) pdTRUE )
{
xQueueReceive( xCharsForTx, &cOutChar, serNO_BLOCK );
lTHREEmpty = pdFALSE;
U0THR = cOutChar;
}
}
}
portEXIT_CRITICAL();
return xReturn;
}
/*-----------------------------------------------------------*/
__arm void vSerialISR( void )
{
signed portCHAR cChar;
portBASE_TYPE xTaskWokenByRx = pdFALSE, xTaskWokenByTx = pdFALSE;
/* What caused the interrupt? */
switch( U0IIR & serINTERRUPT_SOURCE_MASK )
{
case serSOURCE_ERROR : /* Not handling this, but clear the interrupt. */
cChar = U0LSR;
break;
case serSOURCE_THRE : /* The THRE is empty. If there is another
character in the Tx queue, send it now. */
if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xTaskWokenByTx ) == pdTRUE )
{
U0THR = cChar;
}
else
{
/* There are no further characters
queued to send so we can indicate
that the THRE is available. */
lTHREEmpty = pdTRUE;
}
break;
case serSOURCE_RX_TIMEOUT :
case serSOURCE_RX : /* A character was received. Place it in
the queue of received characters. */
cChar = U0RBR;
if( xQueueSendFromISR( xRxedChars, &cChar, pdFALSE ) )
{
xTaskWokenByRx = pdTRUE;
}
break;
default : /* There is nothing to do, leave the ISR. */
break;
}
/* Exit the ISR. If a task was woken by either a character being received
or transmitted then a context switch will occur. */
portEND_SWITCHING_ISR( ( xTaskWokenByTx || xTaskWokenByRx ) );
/* Clear the ISR in the VIC. */
VICVectAddr = serCLEAR_VIC_INTERRUPT;
}
/*-----------------------------------------------------------*/

24
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RSEG ICODE:CODE
CODE32
EXTERN vSerialISR
PUBLIC vSerialISREntry
; Wrapper for the serial port interrupt service routine. This can cause a
; context switch so requires an assembly wrapper.
; Defines the portSAVE_CONTEXT and portRESTORE_CONTEXT macros.
#include "ISR_Support.h"
vSerialISREntry:
portSAVE_CONTEXT ; Save the context of the current task.
bl vSerialISR ; Call the ISR routine.
portRESTORE_CONTEXT ; Restore the context of the current task -
; which may be different to the task that
; was interrupted.
END

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Category=_ 0
[TermIOLog]
LoggingEnabled=_ 0
LogFile=_ ""
[Disassemble mode]
mode=0
[Breakpoints]
Bp0=_ "Code" "{E:\Dev\FreeRTOS\Source\queue.c}.179.3@1" 1 0 0 0 "" 0 ""
Count=1
[Interrupts]
Enabled=1
[MemoryMap]
Enabled=0
TypeVolition=1
UnspecRange=1
ActionState=1
[TraceHelper]
Enabled=0
ShowSource=1

60
Demo/ARM7_LPC2129_IAR/settings/rtosdemo.wsdt Normal file
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<?xml version="1.0" encoding="iso-8859-1"?>
<Workspace>
<ConfigDictionary>
<CurrentConfigs><Project>rtosdemo/Flash Debug</Project></CurrentConfigs></ConfigDictionary>
<Desktop>
<Static>
<Workspace>
<ColumnWidths>
<Column0>229</Column0><Column1>27</Column1><Column2>27</Column2><Column3>27</Column3></ColumnWidths>
</Workspace>
<Build><ColumnWidth0>18</ColumnWidth0><ColumnWidth1>1155</ColumnWidth1><ColumnWidth2>308</ColumnWidth2><ColumnWidth3>77</ColumnWidth3></Build>
<Debug-Log/>
<TerminalIO/>
<CodeCoveragePlugin/>
<Profiling/>
<Watch>
<Format>
<struct_types/>
<watch_formats/>
</Format>
</Watch>
<Disassembly><MixedMode>1</MixedMode><CodeCovEnabled>0</CodeCovEnabled><CodeCovShow>0</CodeCovShow></Disassembly><Memory><ZoneNumber>0</ZoneNumber><FindDirection>1</FindDirection><FindAsHex>0</FindAsHex></Memory><Find-in-Files><ColumnWidth0>552</ColumnWidth0><ColumnWidth1>78</ColumnWidth1><ColumnWidth2>946</ColumnWidth2></Find-in-Files><Breakpoints/></Static>
<Windows>
<Wnd2>
<Tabs>
<Tab>
<Identity>TabID-17425-14382</Identity>
<TabName>Workspace</TabName>
<Factory>Workspace</Factory>
<Session>
<NodeDict><ExpandedNode>rtosdemo</ExpandedNode><ExpandedNode>rtosdemo/Scheduler Source</ExpandedNode><ExpandedNode>rtosdemo/System Files</ExpandedNode></NodeDict></Session>
</Tab>
</Tabs>
<SelectedTab>0</SelectedTab></Wnd2><Wnd3><Tabs><Tab><Identity>TabID-22109-27077</Identity><TabName>Build</TabName><Factory>Build</Factory><Session/></Tab><Tab><Identity>TabID-12074-10873</Identity><TabName>Breakpoints</TabName><Factory>Breakpoints</Factory><Session/></Tab><Tab><Identity>TabID-18349-15872</Identity><TabName>Debug Log</TabName><Factory>Debug-Log</Factory><Session/></Tab><Tab><Identity>TabID-30013-18825</Identity><TabName>Find in Files</TabName><Factory>Find-in-Files</Factory><Session/></Tab></Tabs><SelectedTab>0</SelectedTab></Wnd3></Windows>
<Editor>
<Pane><Tab><Factory>TextEditor</Factory><Filename>E:\Dev\FreeRTOS\Source\list.c</Filename><XPos>0</XPos><YPos>159</YPos><SelStart>6486</SelStart><SelEnd>6613</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>E:\Dev\FreeRTOS\Source\include\list.h</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>0</SelStart><SelEnd>0</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>E:\Dev\FreeRTOS\Source\tasks.c</Filename><XPos>0</XPos><YPos>172</YPos><SelStart>6942</SelStart><SelEnd>6959</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>E:\Dev\FreeRTOS\Source\include\task.h</Filename><XPos>0</XPos><YPos>50</YPos><SelStart>2282</SelStart><SelEnd>2291</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>E:\Dev\FreeRTOS\Demo\ARM7_LPC2129_IAR\serial\serialISR.s79</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>0</SelStart><SelEnd>0</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>E:\Dev\FreeRTOS\Source\portable\IAR\LPC2000\ISR_Support.h</Filename><XPos>0</XPos><YPos>0</YPos><SelStart>0</SelStart><SelEnd>0</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>E:\Dev\FreeRTOS\Source\portable\IAR\LPC2000\portmacro.h</Filename><XPos>0</XPos><YPos>52</YPos><SelStart>2522</SelStart><SelEnd>2531</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>E:\Dev\FreeRTOS\Source\queue.c</Filename><XPos>0</XPos><YPos>148</YPos><SelStart>7593</SelStart><SelEnd>7593</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>E:\Dev\FreeRTOS\Demo\ARM7_LPC2129_IAR\main.c</Filename><XPos>0</XPos><YPos>166</YPos><SelStart>7172</SelStart><SelEnd>7172</SelEnd></Tab><Tab><Factory>TextEditor</Factory><Filename>E:\Dev\FreeRTOS\Source\portable\MemMang\heap_1.c</Filename><XPos>0</XPos><YPos>75</YPos><SelStart>2927</SelStart><SelEnd>2938</SelEnd></Tab><ActiveTab>9</ActiveTab></Pane><ActivePane>0</ActivePane><Sizes><Pane><X>1000000</X><Y>1000000</Y></Pane></Sizes><SplitMode>1</SplitMode></Editor>
<Positions>
<Top><Row0><Sizes><Toolbar-0084fb00><key>iaridepm1</key></Toolbar-0084fb00></Sizes></Row0><Row1><Sizes/></Row1></Top><Left><Row0><Sizes><Wnd2><Rect><Top>-2</Top><Left>-2</Left><Bottom>944</Bottom><Right>303</Right><x>-2</x><y>-2</y><xscreen>0</xscreen><yscreen>0</yscreen><sizeHorzCX>0</sizeHorzCX><sizeHorzCY>0</sizeHorzCY><sizeVertCX>190625</sizeVertCX><sizeVertCY>845397</sizeVertCY></Rect></Wnd2></Sizes></Row0></Left><Right><Row0><Sizes/></Row0></Right><Bottom><Row0><Sizes><Wnd3><Rect><Top>-2</Top><Left>-2</Left><Bottom>128</Bottom><Right>1602</Right><x>-2</x><y>-2</y><xscreen>1604</xscreen><yscreen>130</yscreen><sizeHorzCX>1002500</sizeHorzCX><sizeHorzCY>116175</sizeHorzCY><sizeVertCX>55000</sizeVertCX><sizeVertCY>78641</sizeVertCY></Rect></Wnd3></Sizes></Row0></Bottom><Float><Sizes/></Float></Positions>
</Desktop>
</Workspace>

17
Demo/ARM7_LPC2129_IAR/settings/rtosdemo_lnk.par Normal file
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// IAR XLINK Setup
// Autogenerated file - do not edit
%
setrangelist($evec_ADR,[0-3F]);
setrangelist($internal_ROM,[8000-FFFFF]);
setrangelist($external_ROM,[]);
setrangelist($internal_RAM,[100000-7FFFFF]);
setrangelist($external_RAM,[]);
$CSTACK_SIZE=200;
$IRQSTACK_SIZE=400;
$HEAP_SIZE=4;
$COMMANDS="";
$STACK_LOCATION="Internal RAM";
$IRQSTACK_LOCATION="Internal RAM";
$HEAP_LOCATION="Internal RAM";
$iar_saved_xclfilename="E:\Dev\FreeRTOS\Demo\ARM7_LPC2129_IAR\resource\rtosdemo_lnk.xcl";
%

78
Demo/ARM7_LPC2129_Keil/FreeRTOSConfig.h Normal file
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/*
FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
FreeRTOS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with FreeRTOS; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes FreeRTOS, without being obliged to provide
the source code for any proprietary components. See the licensing section
of http://www.FreeRTOS.org for full details of how and when the exception
can be applied.
***************************************************************************
See http://www.FreeRTOS.org for documentation, latest information, license
and contact details. Please ensure to read the configuration and relevant
port sections of the online documentation.
***************************************************************************
*/
#ifndef FREERTOS_CONFIG_H
#define FREERTOS_CONFIG_H
#include <lpc21xx.h>
/*-----------------------------------------------------------
* Application specific definitions.
*
* These definitions should be adjusted for your particular hardware and
* application requirements.
*
* THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
* FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
*----------------------------------------------------------*/
#define configUSE_PREEMPTION 1
#define configUSE_IDLE_HOOK 0
#define configUSE_TICK_HOOK 0
#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 60000000 ) /* =12.0MHz xtal multiplied by 5 using the PLL. */
#define configTICK_RATE_HZ ( ( portTickType ) 1000 )
#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 )
#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 100 )
#define configTOTAL_HEAP_SIZE ( ( size_t ) 14250 )
#define configMAX_TASK_NAME_LEN ( 16 )
#define configUSE_TRACE_FACILITY 0
#define configUSE_16_BIT_TICKS 0
#define configIDLE_SHOULD_YIELD 1
/* Co-routine definitions. */
#define configUSE_CO_ROUTINES 0
#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
/* Set the following definitions to 1 to include the API function, or zero
to exclude the API function. */
#define INCLUDE_vTaskPrioritySet 1
#define INCLUDE_uxTaskPriorityGet 1
#define INCLUDE_vTaskDelete 1
#define INCLUDE_vTaskCleanUpResources 0
#define INCLUDE_vTaskSuspend 1
#define INCLUDE_vTaskDelayUntil 1
#define INCLUDE_vTaskDelay 1
#endif /* FREERTOS_CONFIG_H */

97
Demo/ARM7_LPC2129_Keil/ParTest/ParTest.c Normal file
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/*
FreeRTOS V4.0.1 - copyright (C) 2003-2006 Richard Barry.
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
FreeRTOS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with FreeRTOS; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes FreeRTOS, without being obliged to provide
the source code for any proprietary components. See the licensing section
of http://www.FreeRTOS.org for full details of how and when the exception
can be applied.
***************************************************************************
See http://www.FreeRTOS.org for documentation, latest information, license
and contact details. Please ensure to read the configuration and relevant
port sections of the online documentation.
***************************************************************************
*/
#include "FreeRTOS.h"
#include "portable.h"
#include "partest.h"
#define partstFIRST_IO ( ( unsigned portLONG ) 0x10000 )
#define partstNUM_LEDS ( 8 )
/*-----------------------------------------------------------
* Simple parallel port IO routines.
*-----------------------------------------------------------*/
void vParTestInitialise( void )
{
/* This is performed from main() as the io bits are shared with other setup
functions. */
}
/*-----------------------------------------------------------*/
void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue )
{
unsigned portLONG ulLED = partstFIRST_IO;
if( uxLED < partstNUM_LEDS )
{
/* Rotate to the wanted bit of port 0. Only P16 to P23 have an LED
attached. */
ulLED <<= ( unsigned portLONG ) uxLED;
/* Set or clear the output. */
if( xValue )
{
IOSET1 = ulLED;
}
else
{
IOCLR1 = ulLED;
}
}
}
/*-----------------------------------------------------------*/
void vParTestToggleLED( unsigned portBASE_TYPE uxLED )
{
unsigned portLONG ulLED = partstFIRST_IO, ulCurrentState;
if( uxLED < partstNUM_LEDS )
{
/* Rotate to the wanted bit of port 0. Only P10 to P13 have an LED
attached. */
ulLED <<= ( unsigned portLONG ) uxLED;
/* If this bit is already set, clear it, and visa versa. */
ulCurrentState = IOPIN1;
if( ulCurrentState & ulLED )
{
IOCLR1 = ulLED;
}
else
{
IOSET1 = ulLED;
}
}
}

40
Demo/ARM7_LPC2129_Keil/RTOSDemoSignal.UVL Normal file
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[Signal 1]
DispName=Port1
PlotType=1
Color=16711935
MinDec=0
MinVal=0.
MaxDec=0
MaxVal=-1.
Mask=65536
Offset=16
[Signal 2]
DispName=Port1
PlotType=1
Color=255
MinDec=0
MinVal=0.
MaxDec=0
MaxVal=-1.
Mask=131072
Offset=17
[Signal 3]
DispName=Port1
PlotType=1
Color=32768
MinDec=0
MinVal=0.
MaxDec=0
MaxVal=-1.
Mask=262144
Offset=18
[Signal 4]
DispName=Port1
PlotType=1
Color=16711680
MinDec=0
MinVal=0.
MaxDec=0
MaxVal=-1.
Mask=524288
Offset=19

379
Demo/ARM7_LPC2129_Keil/Startup.s Normal file
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/***********************************************************************/
/* This file is part of the uVision/ARM development tools */
/* Copyright KEIL ELEKTRONIK GmbH 2002-2004 */
/***********************************************************************/
/* */
/* STARTUP.S: Startup file for Philips LPC2000 device series */
/* */
/***********************************************************************/
/*
//*** <<< Use Configuration Wizard in Context Menu >>> ***
*/
// *** Startup Code (executed after Reset) ***
// Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs
Mode_USR EQU 0x10
Mode_FIQ EQU 0x11
Mode_IRQ EQU 0x12
Mode_SVC EQU 0x13
Mode_ABT EQU 0x17
Mode_UND EQU 0x1B
Mode_SYS EQU 0x1F
I_Bit EQU 0x80 /* when I bit is set, IRQ is disabled */
F_Bit EQU 0x40 /* when F bit is set, FIQ is disabled */
/*
// <h> Stack Configuration (Stack Sizes in Bytes)
// <o0> Undefined Mode <0x0-0xFFFFFFFF>
// <o1> Supervisor Mode <0x0-0xFFFFFFFF>
// <o2> Abort Mode <0x0-0xFFFFFFFF>
// <o3> Fast Interrupt Mode <0x0-0xFFFFFFFF>
// <o4> Interrupt Mode <0x0-0xFFFFFFFF>
// <o5> User/System Mode <0x0-0xFFFFFFFF>
// </h>
*/
UND_Stack_Size EQU 0x00000004
SVC_Stack_Size EQU 0x00000100
ABT_Stack_Size EQU 0x00000004
FIQ_Stack_Size EQU 0x00000004
IRQ_Stack_Size EQU 0x00000300
USR_Stack_Size EQU 0x00000200
AREA STACK, DATA, READWRITE, ALIGN=2
DS (USR_Stack_Size+3)&~3 ; Stack for User/System Mode
DS (IRQ_Stack_Size+3)&~3 ; Stack for Interrupt Mode
DS (FIQ_Stack_Size+3)&~3 ; Stack for Fast Interrupt Mode
DS (ABT_Stack_Size+3)&~3 ; Stack for Abort Mode
DS (SVC_Stack_Size+3)&~3 ; Stack for Supervisor Mode
DS (UND_Stack_Size+3)&~3 ; Stack for Undefined Mode
Top_Stack:
// Phase Locked Loop (PLL) definitions
PLL_BASE EQU 0xE01FC080 /* PLL Base Address */
PLLCON_OFS EQU 0x00 /* PLL Control Offset*/
PLLCFG_OFS EQU 0x04 /* PLL Configuration Offset */
PLLSTAT_OFS EQU 0x08 /* PLL Status Offset */
PLLFEED_OFS EQU 0x0C /* PLL Feed Offset */
PLLCON_PLLE EQU (1<<0) /* PLL Enable */
PLLCON_PLLC EQU (1<<1) /* PLL Connect */
PLLCFG_MSEL EQU (0x1F<<0) /* PLL Multiplier */
PLLCFG_PSEL EQU (0x03<<5) /* PLL Divider */
PLLSTAT_PLOCK EQU (1<<10) /* PLL Lock Status */
/*
// <e> PLL Setup
// <i> Phase Locked Loop
// <o1.0..4> MSEL: PLL Multiplier Selection
// <1-32><#-1>
// <i> M Value
// <o1.5..6> PSEL: PLL Divider Selection
// <0=> 1 <1=> 2 <2=> 4 <3=> 8
// <i> P Value
// </e>
*/
PLL_SETUP EQU 1
PLLCFG_Val EQU 0x00000024
// Memory Accelerator Module (MAM) definitions
MAM_BASE EQU 0xE01FC000 /* MAM Base Address */
MAMCR_OFS EQU 0x00 /* MAM Control Offset*/
MAMTIM_OFS EQU 0x04 /* MAM Timing Offset */
/*
// <e> MAM Setup
// <i> Memory Accelerator Module
// <o1.0..1> MAM Control
// <0=> Disabled
// <1=> Partially Enabled
// <2=> Fully Enabled
// <i> Mode
// <o2.0..2> MAM Timing
// <0=> Reserved <1=> 1 <2=> 2 <3=> 3
// <4=> 4 <5=> 5 <6=> 6 <7=> 7
// <i> Fetch Cycles
// </e>
*/
MAM_SETUP EQU 1
MAMCR_Val EQU 0x00000002
MAMTIM_Val EQU 0x00000003
// External Memory Controller (EMC) definitions
EMC_BASE EQU 0xFFE00000 /* EMC Base Address */
BCFG0_OFS EQU 0x00 /* BCFG0 Offset */
BCFG1_OFS EQU 0x04 /* BCFG1 Offset */
BCFG2_OFS EQU 0x08 /* BCFG2 Offset */
BCFG3_OFS EQU 0x0C /* BCFG3 Offset */
/*
// <e> External Memory Controller (EMC)
*/
EMC_SETUP EQU 0
/*
// <e> Bank Configuration 0 (BCFG0)
// <o1.0..3> IDCY: Idle Cycles <0-15>
// <o1.5..9> WST1: Wait States 1 <0-31>
// <o1.11..15> WST2: Wait States 2 <0-31>
// <o1.10> RBLE: Read Byte Lane Enable
// <o1.26> WP: Write Protect
// <o1.27> BM: Burst ROM
// <o1.28..29> MW: Memory Width <0=> 8-bit <1=> 16-bit
// <2=> 32-bit <3=> Reserved
// </e>
*/
BCFG0_SETUP EQU 0
BCFG0_Val EQU 0x0000FBEF
/*
// <e> Bank Configuration 1 (BCFG1)
// <o1.0..3> IDCY: Idle Cycles <0-15>
// <o1.5..9> WST1: Wait States 1 <0-31>
// <o1.11..15> WST2: Wait States 2 <0-31>
// <o1.10> RBLE: Read Byte Lane Enable
// <o1.26> WP: Write Protect
// <o1.27> BM: Burst ROM
// <o1.28..29> MW: Memory Width <0=> 8-bit <1=> 16-bit
// <2=> 32-bit <3=> Reserved
// </e>
*/
BCFG1_SETUP EQU 0
BCFG1_Val EQU 0x0000FBEF
/*
// <e> Bank Configuration 0 (BCFG2)
// <o1.0..3> IDCY: Idle Cycles <0-15>
// <o1.5..9> WST1: Wait States 1 <0-31>
// <o1.11..15> WST2: Wait States 2 <0-31>
// <o1.10> RBLE: Read Byte Lane Enable
// <o1.26> WP: Write Protect
// <o1.27> BM: Burst ROM
// <o1.28..29> MW: Memory Width <0=> 8-bit <1=> 16-bit
// <2=> 32-bit <3=> Reserved
// </e>
*/
BCFG2_SETUP EQU 0
BCFG2_Val EQU 0x0000FBEF
/*
// <e> Bank Configuration 3 (BCFG3)
// <o1.0..3> IDCY: Idle Cycles <0-15>
// <o1.5..9> WST1: Wait States 1 <0-31>
// <o1.11..15> WST2: Wait States 2 <0-31>
// <o1.10> RBLE: Read Byte Lane Enable
// <o1.26> WP: Write Protect
// <o1.27> BM: Burst ROM
// <o1.28..29> MW: Memory Width <0=> 8-bit <1=> 16-bit
// <2=> 32-bit <3=> Reserved
// </e>
*/
BCFG3_SETUP EQU 0
BCFG3_Val EQU 0x0000FBEF
/*
// </e> End of EMC
*/
// External Memory Pins definitions
PINSEL2 EQU 0xE002C014 /* PINSEL2 Address */
PINSEL2_Val EQU 0x0E6149E4 /* CS0..3, OE, WE, BLS0..3,
D0..31, A2..23, JTAG Pins */
// Starupt Code must be linked first at Address at which it expects to run.
$IF (EXTERNAL_MODE)
CODE_BASE EQU 0x80000000
$ELSE
CODE_BASE EQU 0x00000000
$ENDIF
AREA STARTUPCODE, CODE, AT CODE_BASE // READONLY, ALIGN=4
PUBLIC __startup
EXTERN CODE32 (?C?INIT)
__startup PROC CODE32
// Pre-defined interrupt handlers that may be directly
// overwritten by C interrupt functions
EXTERN CODE32 (Undef_Handler?A)
EXTERN CODE32 (vPortYieldProcessor?A)
EXTERN CODE32 (PAbt_Handler?A)
EXTERN CODE32 (DAbt_Handler?A)
EXTERN CODE32 (IRQ_Handler?A)
EXTERN CODE32 (FIQ_Handler?A)
// Exception Vectors
// Mapped to Address 0.
// Absolute addressing mode must be used.
Vectors: LDR PC,Reset_Addr
LDR PC,Undef_Addr
LDR PC,SWI_Addr
LDR PC,PAbt_Addr
LDR PC,DAbt_Addr
NOP /* Reserved Vector */
; LDR PC,IRQ_Addr
LDR PC,[PC, #-0x0FF0] /* Vector from VicVectAddr */
LDR PC,FIQ_Addr
Reset_Addr: DD Reset_Handler
Undef_Addr: DD Undef_Handler?A
SWI_Addr: DD vPortYieldProcessor?A
PAbt_Addr: DD PAbt_Handler?A
DAbt_Addr: DD DAbt_Handler?A
DD 0 /* Reserved Address */
IRQ_Addr: DD IRQ_Handler?A
FIQ_Addr: DD FIQ_Handler?A
// Reset Handler
Reset_Handler:
$IF (EXTERNAL_MODE)
LDR R0, =PINSEL2
LDR R1, =PINSEL2_Val
STR R1, [R0]
$ENDIF
IF (EMC_SETUP != 0)
LDR R0, =EMC_BASE
IF (BCFG0_SETUP != 0)
LDR R1, =BCFG0_Val
STR R1, [R0, #BCFG0_OFS]
ENDIF
IF (BCFG1_SETUP != 0)
LDR R1, =BCFG1_Val
STR R1, [R0, #BCFG1_OFS]
ENDIF
IF (BCFG2_SETUP != 0)
LDR R1, =BCFG2_Val
STR R1, [R0, #BCFG2_OFS]
ENDIF
IF (BCFG3_SETUP != 0)
LDR R1, =BCFG3_Val
STR R1, [R0, #BCFG3_OFS]
ENDIF
ENDIF
IF (PLL_SETUP != 0)
LDR R0, =PLL_BASE
MOV R1, #0xAA
MOV R2, #0x55
// Configure and Enable PLL
MOV R3, #PLLCFG_Val
STR R3, [R0, #PLLCFG_OFS]
MOV R3, #PLLCON_PLLE
STR R3, [R0, #PLLCON_OFS]
STR R1, [R0, #PLLFEED_OFS]
STR R2, [R0, #PLLFEED_OFS]
// Wait until PLL Locked
PLL_Loop: LDR R3, [R0, #PLLSTAT_OFS]
ANDS R3, R3, #PLLSTAT_PLOCK
BEQ PLL_Loop
// Switch to PLL Clock
MOV R3, #(PLLCON_PLLE | PLLCON_PLLC)
STR R3, [R0, #PLLCON_OFS]
STR R1, [R0, #PLLFEED_OFS]
STR R2, [R0, #PLLFEED_OFS]
ENDIF
IF (MAM_SETUP != 0)
LDR R0, =MAM_BASE
MOV R1, #MAMTIM_Val
STR R1, [R0, #MAMTIM_OFS]
MOV R1, #MAMCR_Val
STR R1, [R0, #MAMCR_OFS]
ENDIF
// Memory Mapping (when Interrupt Vectors are in RAM)
MEMMAP EQU 0xE01FC040 /* Memory Mapping Control */
$IF (RAM_INTVEC)
LDR R0, =MEMMAP
MOV R1, #2
STR R1, [R0]
$ENDIF
// Setup Stack for each mode
LDR R0, =Top_Stack
// Enter Undefined Instruction Mode and set its Stack Pointer
MSR CPSR_c, #Mode_UND|I_Bit|F_Bit
MOV SP, R0
SUB R0, R0, #UND_Stack_Size
// Enter Abort Mode and set its Stack Pointer
MSR CPSR_c, #Mode_ABT|I_Bit|F_Bit
MOV SP, R0
SUB R0, R0, #ABT_Stack_Size
// Enter FIQ Mode and set its Stack Pointer
MSR CPSR_c, #Mode_FIQ|I_Bit|F_Bit
MOV SP, R0
SUB R0, R0, #FIQ_Stack_Size
// Enter IRQ Mode and set its Stack Pointer
MSR CPSR_c, #Mode_IRQ|I_Bit|F_Bit
MOV SP, R0
SUB R0, R0, #IRQ_Stack_Size
// Enter Supervisor Mode and set its Stack Pointer
MSR CPSR_c, #Mode_SVC|I_Bit|F_Bit
MOV SP, R0
SUB R0, R0, #SVC_Stack_Size
// Enter S Mode and set its Stack Pointer
MSR CPSR_c, #Mode_SYS
MOV SP, R0
// Start in supervisor mode
MSR CPSR_c, #Mode_SVC|I_Bit|F_Bit
// Enter the C code
LDR R0,=?C?INIT
TST R0,#1 ; Bit-0 set: INIT is Thumb
LDREQ LR,=exit?A ; ARM Mode
LDRNE LR,=exit?T ; Thumb Mode
BX R0
ENDP
PUBLIC exit?A
exit?A PROC CODE32
B exit?A
ENDP
PUBLIC exit?T
exit?T PROC CODE16
exit: B exit?T
ENDP
END

282
Demo/ARM7_LPC2129_Keil/main.c Normal file
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@ -0,0 +1,282 @@
/*
FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
FreeRTOS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with FreeRTOS; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes FreeRTOS, without being obliged to provide
the source code for any proprietary components. See the licensing section
of http://www.FreeRTOS.org for full details of how and when the exception
can be applied.
***************************************************************************
See http://www.FreeRTOS.org for documentation, latest information, license
and contact details. Please ensure to read the configuration and relevant
port sections of the online documentation.
***************************************************************************
*/
/*
NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode.
The processor MUST be in supervisor mode when vTaskStartScheduler is
called. The demo applications included in the FreeRTOS.org download switch
to supervisor mode prior to main being called. If you are not using one of
these demo application projects then ensure Supervisor mode is used.
*/
/*
* Creates all the demo application tasks, then starts the scheduler. The WEB
* documentation provides more details of the demo application tasks.
*
* Main.c also creates a task called "Check". This only executes every three
* seconds but has the highest priority so is guaranteed to get processor time.
* Its main function is to check that all the other tasks are still operational.
* Each task (other than the "flash" tasks) maintains a unique count that is
* incremented each time the task successfully completes its function. Should
* any error occur within such a task the count is permanently halted. The
* check task inspects the count of each task to ensure it has changed since
* the last time the check task executed. If all the count variables have
* changed all the tasks are still executing error free, and the check task
* toggles the onboard LED. Should any task contain an error at any time
* the LED toggle rate will change from 3 seconds to 500ms.
*
*/
/* Standard includes. */
#include <stdlib.h>
/* Scheduler includes. */
#include "FreeRTOS.h"
#include "task.h"
/* Demo application includes. */
#include "partest.h"
#include "flash.h"
#include "integer.h"
#include "comtest2.h"
#include "serial.h"
#ifdef KEIL_THUMB_INTERWORK
/*
THUMB mode allows more tasks to be created without the executable
binary exceeding the limits allowed by the evaluation version of
uVision3.
*/
#include "PollQ.h"
#include "BlockQ.h"
#include "semtest.h"
#include "dynamic.h"
#endif
/*-----------------------------------------------------------*/
/* Constants to setup I/O and processor. */
#define mainTX_ENABLE ( ( unsigned portLONG ) 0x0001 )
#define mainRX_ENABLE ( ( unsigned portLONG ) 0x0004 )
#define mainBUS_CLK_FULL ( ( unsigned portCHAR ) 0x01 )
#define mainLED_TO_OUTPUT ( ( unsigned portLONG ) 0xff0000 )
/* Constants for the ComTest demo application tasks. */
#define mainCOM_TEST_BAUD_RATE ( ( unsigned portLONG ) 115200 )
#define mainCOM_TEST_LED ( 3 )
/* Priorities for the demo application tasks. */
#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 )
#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 )
#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 )
#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 )
#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 )
#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 4 )
/* Constants used by the "check" task. As described at the head of this file
the check task toggles an LED. The rate at which the LED flashes is used to
indicate whether an error has been detected or not. If the LED toggles every
3 seconds then no errors have been detected. If the rate increases to 500ms
then an error has been detected in at least one of the demo application tasks. */
#define mainCHECK_LED ( 7 )
#define mainNO_ERROR_FLASH_PERIOD ( ( portTickType ) 3000 / portTICK_RATE_MS )
#define mainERROR_FLASH_PERIOD ( ( portTickType ) 500 / portTICK_RATE_MS )
/*-----------------------------------------------------------*/
/*
* Checks that all the demo application tasks are still executing without error
* - as described at the top of the file.
*/
static portLONG prvCheckOtherTasksAreStillRunning( void );
/*
* The task that executes at the highest priority and calls
* prvCheckOtherTasksAreStillRunning(). See the description at the top
* of the file.
*/
static void vErrorChecks( void *pvParameters );
/*
* Configure the processor for use with the Keil demo board. This is very
* minimal as most of the setup is managed by the settings in the project
* file.
*/
static void prvSetupHardware( void );
/*-----------------------------------------------------------*/
/*
* Application entry point:
* Starts all the other tasks, then starts the scheduler.
*/
int main( void )
{
/* Setup the hardware for use with the Keil demo board. */
prvSetupHardware();
/* Start the demo/test application tasks. */
vStartIntegerMathTasks( tskIDLE_PRIORITY );
vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED );
vStartLEDFlashTasks( mainLED_TASK_PRIORITY );
#ifdef KEIL_THUMB_INTERWORK
/* When using THUMB mode we can start more tasks without the executable
exceeding the size limit imposed by the evaluation version of uVision3. */
vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );
vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );
vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );
vStartDynamicPriorityTasks();
#endif
/* Start the check task - which is defined in this file. This is the task
that periodically checks to see that all the other tasks are executing
without error. */
xTaskCreate( vErrorChecks, "Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );
/* Now all the tasks have been started - start the scheduler.
NOTE : Tasks run in system mode and the scheduler runs in Supervisor mode.
The processor MUST be in supervisor mode when vTaskStartScheduler is
called. The demo applications included in the FreeRTOS.org download switch
to supervisor mode prior to main being called. If you are not using one of
these demo application projects then ensure Supervisor mode is used here. */
vTaskStartScheduler();
/* Should never reach here! */
return 0;
}
/*-----------------------------------------------------------*/
static void vErrorChecks( void *pvParameters )
{
portTickType xDelayPeriod = mainNO_ERROR_FLASH_PERIOD;
/* Parameters are not used. */
( void ) pvParameters;
/* Cycle for ever, delaying then checking all the other tasks are still
operating without error. If an error is detected then the delay period
is decreased from mainNO_ERROR_FLASH_PERIOD to mainERROR_FLASH_PERIOD so
the on board LED flash rate will increase.
This task runs at the highest priority. */
for( ;; )
{
/* The period of the delay depends on whether an error has been
detected or not. If an error has been detected then the period
is reduced to increase the LED flash rate. */
vTaskDelay( xDelayPeriod );
if( prvCheckOtherTasksAreStillRunning() != pdPASS )
{
/* An error has been detected in one of the tasks - flash faster. */
xDelayPeriod = mainERROR_FLASH_PERIOD;
}
/* Toggle the LED before going back to wait for the next cycle. */
vParTestToggleLED( mainCHECK_LED );
}
}
/*-----------------------------------------------------------*/
static void prvSetupHardware( void )
{
/* Perform the hardware setup required. This is minimal as most of the
setup is managed by the settings in the project file. */
/* Configure the RS2332 pins. All other pins remain at their default of 0. */
PINSEL0 |= mainTX_ENABLE;
PINSEL0 |= mainRX_ENABLE;
/* LED pins need to be output. */
IODIR1 = mainLED_TO_OUTPUT;
/* Setup the peripheral bus to be the same as the PLL output. */
VPBDIV = mainBUS_CLK_FULL;
}
/*-----------------------------------------------------------*/
static portLONG prvCheckOtherTasksAreStillRunning( void )
{
portLONG lReturn = pdPASS;
/* Check all the demo tasks (other than the flash tasks) to ensure
that they are all still running, and that none of them have detected
an error. */
if( xAreIntegerMathsTaskStillRunning() != pdPASS )
{
lReturn = pdFAIL;
}
if( xAreComTestTasksStillRunning() != pdPASS )
{
lReturn = pdFAIL;
}
#ifdef KEIL_THUMB_INTERWORK
/* When using THUMB mode we can start more tasks without the executable
exceeding the size limit imposed by the evaluation version of uVision3. */
if( xArePollingQueuesStillRunning() != pdTRUE )
{
lReturn = pdFAIL;
}
if( xAreBlockingQueuesStillRunning() != pdTRUE )
{
lReturn = pdFAIL;
}
if( xAreSemaphoreTasksStillRunning() != pdTRUE )
{
lReturn = pdFAIL;
}
if( xAreDynamicPriorityTasksStillRunning() != pdTRUE )
{
lReturn = pdFAIL;
}
#endif
return lReturn;
}
/*-----------------------------------------------------------*/

58
Demo/ARM7_LPC2129_Keil/rtosdemo_ARM.Opt Normal file
View file

@ -0,0 +1,58 @@
### uVision2 Project, (C) Keil Software
### Do not modify !
cExt (*.c)
aExt (*.s*; *.src; *.a*)
oExt (*.obj)
lExt (*.lib)
tExt (*.txt; *.h; *.inc)
pExt (*.plm)
CppX (*.cpp)
DaveTm { 0,0,0,0,0,0,0,0 }
Target (FreeRTOS), 0x0005 // Tools: ''
GRPOPT 1,(ARM_DEMO),1,0,0
OPTFFF 1,1,1,2,0,127,137,0,<.\main.c><main.c> { 44,0,0,0,2,0,0,0,3,0,0,0,255,255,255,255,255,255,255,255,252,255,255,255,228,255,255,255,27,0,0,0,27,0,0,0,41,4,0,0,102,2,0,0 }
OPTFFF 1,2,2,0,0,0,0,0,<.\Startup.s><Startup.s>
OPTFFF 1,3,1,0,0,0,0,0,<.\ParTest\ParTest.c><ParTest.c>
OPTFFF 1,4,1,0,0,0,0,0,<.\serial\serial.c><serial.c>
OPTFFF 1,5,1,0,0,0,0,0,<.\serial\serialISR.c><serialISR.c>
OPTFFF 1,6,1,0,0,0,0,0,<..\..\Source\tasks.c><tasks.c>
OPTFFF 1,7,1,0,0,0,0,0,<..\..\Source\queue.c><queue.c>
OPTFFF 1,8,1,0,0,0,0,0,<..\..\Source\list.c><list.c>
OPTFFF 1,9,1,0,0,0,0,0,<..\..\Source\portable\Keil\ARM7\port.c><port.c>
OPTFFF 1,10,1,0,0,0,0,0,<..\..\Source\portable\Keil\ARM7\portISR.c><portISR.c>
OPTFFF 1,11,1,0,0,0,0,0,<..\Common\Minimal\flash.c><flash.c>
OPTFFF 1,12,1,16777216,0,0,0,0,<..\Common\Minimal\comtest.c><comtest.c>
OPTFFF 1,13,1,0,0,0,0,0,<..\Common\Minimal\integer.c><integer.c>
OPTFFF 1,14,1,0,0,0,0,0,<..\..\Source\portable\MemMang\heap_2.c><heap_2.c>
TARGOPT 1, (FreeRTOS)
KACLK=12000000
OPTTT 1,1,1,0
OPTHX 0,65535,0,0,0
OPTLX 120,65,8,<.\>
OPTOX 16
OPTLT 1,1,1,0,1,1,0,1,0,0,0,0
OPTXL 1,1,1,1,1,1,1,0,0
OPTFL 1,0,1
OPTBL 0,(Data Sheet)<DATASHTS\PHILIPS\LPC2119_2129.PDF>
OPTBL 1,(User Manual)<DATASHTS\PHILIPS\UM_LPC21XX_LPC22XX.PDF>
OPTDL (SARM.DLL)(-cLPC2100)(DARMP.DLL)(-pLPC21x9)(SARM.DLL)()(TARMP.DLL)(-pLPC21x9)
OPTDBG 44029,-1,()()()()()()()()()() (BIN\UL2ARM.DLL)()()()
OPTKEY 0,(DLGTARM)((134=-1,-1,-1,-1,0)(135=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)(108=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(105=-1,-1,-1,-1,0)(80=-1,-1,-1,-1,0)(104=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(101=-1,-1,-1,-1,0)(113=-1,-1,-1,-1,0)(112=-1,-1,-1,-1,0)(136=-1,-1,-1,-1,0)(117=-1,-1,-1,-1,0)(118=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(114=-1,-1,-1,-1,0)(119=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(121=-1,-1,-1,-1,0)(122=-1,-1,-1,-1,0)(115=-1,-1,-1,-1,0)(116=-1,-1,-1,-1,0))
OPTKEY 0,(UL2ARM)(-U174073036 -O7 -S0 -C0 -N00("ARM7TDMI-S Core") -D00(4F1F0F0F) -L00(4) -FO7 -FD40000000 -FC800 -FN1 -FF0LPC_IAP_256 -FS00 -FL03E000)
OPTKEY 0,(DLGDARM)((134=-1,-1,-1,-1,0)(135=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)(108=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(105=-1,-1,-1,-1,0)(80=-1,-1,-1,-1,0)(104=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(101=-1,-1,-1,-1,0)(113=-1,-1,-1,-1,0)(112=-1,-1,-1,-1,0)(136=-1,-1,-1,-1,0)(117=-1,-1,-1,-1,0)(118=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(114=-1,-1,-1,-1,0)(119=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(121=-1,-1,-1,-1,0)(122=-1,-1,-1,-1,0)(132=-1,-1,-1,-1,0)(115=-1,-1,-1,-1,0)(116=-1,-1,-1,-1,0))
OPTKEY 0,(ARMDBGFLAGS)(-T5F)
OPTMM 1,0,(0x40001800)
OPTDF 0x1000080
OPTLE <>
OPTLC <>
OPTLA 0,((Port1 & 0x10000) >> 16)(FF00FF000000000000000000000000000000F0BF010000006400000000E8764817000000506F72743100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000020370000)
OPTLA 1,((Port1 & 0x20000) >> 17)(FF0000000000000000000000000000000000F0BF010000006400000000E8764817000000506F72743100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000020370000)
OPTLA 2,((Port1 & 0x40000) >> 18)(008000000000000000000000000000000000F0BF010000006400000000E8764817000000506F72743100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000020370000)
OPTLA 3,((Port1 & 0x80000) >> 19)(0000FF000000000000000000000000000000F0BF010000006400000000E8764817000000506F72743100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000000000000000000020370000)
EndOpt

106
Demo/ARM7_LPC2129_Keil/rtosdemo_ARM.Uv2 Normal file
View file

@ -0,0 +1,106 @@
### uVision2 Project, (C) Keil Software
### Do not modify !
Target (FreeRTOS), 0x0005 // Tools: ''
Group (ARM_DEMO)
File 1,1,<.\main.c><main.c> 0x4162D96A
File 1,2,<.\Startup.s><Startup.s> 0x415AF382
File 1,1,<.\ParTest\ParTest.c><ParTest.c> 0x415AF50E
File 1,1,<.\serial\serial.c><serial.c> 0x4162D488
File 1,1,<.\serial\serialISR.c><serialISR.c> 0x4162D404
File 1,1,<..\..\Source\tasks.c><tasks.c> 0x4162D9E6
File 1,1,<..\..\Source\queue.c><queue.c> 0x411B5F14
File 1,1,<..\..\Source\list.c><list.c> 0x411B5F24
File 1,1,<..\..\Source\portable\Keil\ARM7\port.c><port.c> 0x4162D434
File 1,1,<..\..\Source\portable\Keil\ARM7\portISR.c><portISR.c> 0x415A85E0
File 1,1,<..\Common\Minimal\flash.c><flash.c> 0x411B5F8E
File 1,1,<..\Common\Minimal\comtest.c><comtest.c> 0x413335E6
File 1,1,<..\Common\Minimal\integer.c><integer.c> 0x415FB7EE
File 1,1,<..\..\Source\portable\MemMang\heap_2.c><heap_2.c> 0x0
Options 1,0,0 // Target 'FreeRTOS'
Device (LPC2129)
Vendor (Philips)
Cpu (IRAM(0x40000000-0x40003FFF) IROM(0-0x3FFFF) CLOCK(12000000) CPUTYPE(ARM7TDMI))
FlashUt (LPC210x_ISP.EXE ("#H" ^X $D COM1: 9600 1))
StupF ("STARTUP\Philips\Startup.s" ("Philips LPC2100 Startup Code"))
FlashDR (UL2ARM(-U40296420 -O7 -C0 -FO7 -FD40000000 -FC800 -FN1 -FF0LPC_IAP_256 -FS00 -FL03E000))
Rgf (LPC21xx.H)
Mem ()
C ()
A ()
RL ()
OH ()
DBC_IFX ()
DBC_CMS ()
DBC_AMS ()
DBC_LMS ()
UseEnv=0
EnvBin (D:\DevTools\Keil\arm\ARM\BIN\)
EnvInc ()
EnvLib ()
EnvReg (ÿPhilips\)
OrgReg (ÿPhilips\)
TgStat=16
OutDir (.\)
OutName (rtosdemo_ARM)
GenApp=1
GenLib=0
GenHex=0
Debug=1
Browse=0
LstDir (.\)
HexSel=0
MG32K=0
TGMORE=0
RunUsr 0 0 <>
RunUsr 1 0 <>
BrunUsr 0 0 <>
BrunUsr 1 0 <>
SVCSID <>
KACPU (ARM7TDMI)
TKAFL { 0,27,183,0,0,15,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
KIROM { 1,0,0,0,0,0,0,4,0 }
KIRAM { 0,0,0,0,64,0,64,0,0 }
KXRAM { 0,0,0,0,0,0,0,0,0 }
KAOCM { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
KCAFLG { 197,132,4,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
KCAMSC (INTERWORK)
KCADEF (KEIL_ARM7)
KCAUDF ()
KCAINC (..\Common\include\;..\..\Source\include\;..\..\Source\portable\Keil\ARM7\)
KAAFLG { 20,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
KAAMSC ()
KAASET ()
KAARST ()
KAAINC ()
PropFld { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
IncBld=1
AlwaysBuild=0
GenAsm=0
AsmAsm=0
PublicsOnly=0
StopCode=3
CustArgs ()
LibMods ()
KLAFLG { 44,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
KLAMSC ()
KLADWN (25)
KLACFI ()
KLAASN ()
KLARES ()
KLACCL ()
KLAUCL ()
KLACSC ()
KLAUCS ()
OPTDL (SARM.DLL)(-cLPC2100)(DARMP.DLL)(-pLPC21x9)(SARM.DLL)()(TARMP.DLL)(-pLPC21x9)
OPTDBG 44029,-1,()()()()()()()()()() (BIN\UL2ARM.DLL)()()()
FLASH1 { 1,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
FLASH2 (BIN\UL2ARM.DLL)
FLASH3 ("LPC210x_ISP.EXE" ("#H" ^X $D COM1: 9600 1))
FLASH4 ()
EndOpt

63
Demo/ARM7_LPC2129_Keil/rtosdemo_THUMB.Opt Normal file
View file

@ -0,0 +1,63 @@
### uVision2 Project, (C) Keil Software
### Do not modify !
cExt (*.c)
aExt (*.s*; *.src; *.a*)
oExt (*.obj)
lExt (*.lib)
tExt (*.txt; *.h; *.inc)
pExt (*.plm)
CppX (*.cpp)
DaveTm { 0,0,0,0,0,0,0,0 }
Target (FreeRTOS), 0x0005 // Tools: ''
GRPOPT 1,(THUMB_DEMO),1,0,0
OPTFFF 1,1,1,1,0,121,137,0,<.\main.c><main.c> { 44,0,0,0,0,0,0,0,1,0,0,0,255,255,255,255,255,255,255,255,252,255,255,255,228,255,255,255,0,0,0,0,0,0,0,0,14,4,0,0,75,2,0,0 }
OPTFFF 1,2,2,0,0,0,0,0,<.\Startup.s><Startup.s>
OPTFFF 1,3,1,1040187392,0,0,0,0,<.\ParTest\ParTest.c><ParTest.c>
OPTFFF 1,4,1,0,0,0,0,0,<.\serial\serial.c><serial.c>
OPTFFF 1,5,1,0,0,0,0,0,<.\serial\serialISR.c><serialISR.c>
OPTFFF 1,6,1,0,0,0,0,0,<..\..\Source\tasks.c><tasks.c>
OPTFFF 1,7,1,0,0,0,0,0,<..\..\Source\queue.c><queue.c>
OPTFFF 1,8,1,0,0,0,0,0,<..\..\Source\list.c><list.c>
OPTFFF 1,9,1,553648128,0,0,0,0,<..\..\Source\portable\Keil\ARM7\port.c><port.c>
OPTFFF 1,10,1,0,0,0,0,0,<..\..\Source\portable\Keil\ARM7\portISR.c><portISR.c>
OPTFFF 1,11,1,0,0,0,0,0,<..\Common\Minimal\BlockQ.c><BlockQ.c>
OPTFFF 1,12,1,402653184,0,0,0,0,<..\Common\Minimal\semtest.c><semtest.c>
OPTFFF 1,13,1,0,0,0,0,0,<..\Common\Minimal\PollQ.c><PollQ.c>
OPTFFF 1,14,1,0,0,0,0,0,<..\Common\Minimal\flash.c><flash.c>
OPTFFF 1,15,1,0,0,0,0,0,<..\Common\Minimal\comtest.c><comtest.c>
OPTFFF 1,16,1,0,0,0,0,0,<..\Common\Minimal\integer.c><integer.c>
OPTFFF 1,17,1,0,0,0,0,0,<..\..\Source\portable\MemMang\heap_2.c><heap_2.c>
OPTFFF 1,18,1,0,0,0,0,0,<..\Common\Minimal\dynamic.c><dynamic.c>
ExtF <..\..\SOURCE\PORTABLE\KEIL\ARM7\PORTMACRO.H> 127,127,0,{ 44,0,0,0,2,0,0,0,3,0,0,0,255,255,255,255,255,255,255,255,252,255,255,255,228,255,255,255,27,0,0,0,27,0,0,0,72,4,0,0,33,2,0,0 }
TARGOPT 1, (FreeRTOS)
KACLK=12000000
OPTTT 1,1,1,0
OPTHX 0,65535,0,0,0
OPTLX 120,65,8,<.\>
OPTOX 16
OPTLT 1,1,1,0,1,1,0,1,0,0,0,0
OPTXL 1,1,1,1,1,1,1,0,0
OPTFL 1,0,1
OPTBL 0,(Data Sheet)<DATASHTS\PHILIPS\LPC2119_2129.PDF>
OPTBL 1,(User Manual)<DATASHTS\PHILIPS\UM_LPC21XX_LPC22XX.PDF>
OPTDL (SARM.DLL)(-cLPC2100)(DARMP.DLL)(-pLPC21x9)(SARM.DLL)()(TARMP.DLL)(-pLPC21x9)
OPTDBG 44029,-1,()()()()()()()()()() (BIN\UL2ARM.DLL)()()()
OPTKEY 0,(DLGTARM)((134=-1,-1,-1,-1,0)(135=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)(108=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(105=-1,-1,-1,-1,0)(80=-1,-1,-1,-1,0)(104=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(101=-1,-1,-1,-1,0)(113=-1,-1,-1,-1,0)(112=-1,-1,-1,-1,0)(136=-1,-1,-1,-1,0)(117=-1,-1,-1,-1,0)(118=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(114=-1,-1,-1,-1,0)(119=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(121=-1,-1,-1,-1,0)(122=-1,-1,-1,-1,0)(115=-1,-1,-1,-1,0)(116=-1,-1,-1,-1,0))
OPTKEY 0,(UL2ARM)(-U170927308 -O7 -S0 -C0 -N00("ARM7TDMI-S Core") -D00(4F1F0F0F) -L00(4) -FO7 -FD40000000 -FC800 -FN1 -FF0LPC_IAP_256 -FS00 -FL03E000)
OPTKEY 0,(DLGDARM)((134=-1,-1,-1,-1,0)(135=-1,-1,-1,-1,0)(107=-1,-1,-1,-1,0)(108=-1,-1,-1,-1,0)(106=-1,-1,-1,-1,0)(105=-1,-1,-1,-1,0)(80=-1,-1,-1,-1,0)(104=-1,-1,-1,-1,0)(100=-1,-1,-1,-1,0)(101=-1,-1,-1,-1,0)(113=-1,-1,-1,-1,0)(112=-1,-1,-1,-1,0)(136=-1,-1,-1,-1,0)(117=-1,-1,-1,-1,0)(118=-1,-1,-1,-1,0)(110=-1,-1,-1,-1,0)(111=-1,-1,-1,-1,0)(114=-1,-1,-1,-1,0)(119=-1,-1,-1,-1,0)(130=-1,-1,-1,-1,0)(131=-1,-1,-1,-1,0)(121=-1,-1,-1,-1,0)(122=-1,-1,-1,-1,0)(132=-1,-1,-1,-1,0)(115=-1,-1,-1,-1,0)(116=-1,-1,-1,-1,0))
OPTKEY 0,(ARMDBGFLAGS)(-T5F)
OPTMM 1,0,(0x40000840)
OPTDF 0x1000086
OPTLE <>
OPTLC <>
OPTLA 0,((Port1 & 0x10000) >> 16)(0000FF000000000000000000000000000000F0BF010000006400000000743BA40B000000506F7274310000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000001C030000)
OPTLA 1,((Port1 & 0x20000) >> 17)(0000FF000000000000000000000000000000F0BF010000006400000000743BA40B000000506F7274310000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000001C030000)
OPTLA 2,((Port1 & 0x40000) >> 18)(0000FF000000000000000000000000000000F0BF010000006400000000743BA40B000000506F7274310000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000001C030000)
OPTLA 3,((Port1 & 0x80000) >> 19)(0000FF000000000000000000000000000000F0BF010000006400000000743BA40B000000506F7274310000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000001C030000)
EndOpt

110
Demo/ARM7_LPC2129_Keil/rtosdemo_THUMB.Uv2 Normal file
View file

@ -0,0 +1,110 @@
### uVision2 Project, (C) Keil Software
### Do not modify !
Target (FreeRTOS), 0x0005 // Tools: ''
Group (THUMB_DEMO)
File 1,1,<.\main.c><main.c> 0x4162D96A
File 1,2,<.\Startup.s><Startup.s> 0x415AF382
File 1,1,<.\ParTest\ParTest.c><ParTest.c> 0x415AF50E
File 1,1,<.\serial\serial.c><serial.c> 0x4162D488
File 1,1,<.\serial\serialISR.c><serialISR.c> 0x4162D404
File 1,1,<..\..\Source\tasks.c><tasks.c> 0x4162D9E6
File 1,1,<..\..\Source\queue.c><queue.c> 0x411B5F14
File 1,1,<..\..\Source\list.c><list.c> 0x411B5F24
File 1,1,<..\..\Source\portable\Keil\ARM7\port.c><port.c> 0x4162D434
File 1,1,<..\..\Source\portable\Keil\ARM7\portISR.c><portISR.c> 0x415A85E0
File 1,1,<..\Common\Minimal\BlockQ.c><BlockQ.c> 0x411B5F8C
File 1,1,<..\Common\Minimal\semtest.c><semtest.c> 0x411B5F8C
File 1,1,<..\Common\Minimal\PollQ.c><PollQ.c> 0x411B5F8E
File 1,1,<..\Common\Minimal\flash.c><flash.c> 0x411B5F8E
File 1,1,<..\Common\Minimal\comtest.c><comtest.c> 0x413335E6
File 1,1,<..\Common\Minimal\integer.c><integer.c> 0x415FB7EE
File 1,1,<..\..\Source\portable\MemMang\heap_2.c><heap_2.c> 0x0
File 1,1,<..\Common\Minimal\dynamic.c><dynamic.c> 0x0
Options 1,0,0 // Target 'FreeRTOS'
Device (LPC2129)
Vendor (Philips)
Cpu (IRAM(0x40000000-0x40003FFF) IROM(0-0x3FFFF) CLOCK(12000000) CPUTYPE(ARM7TDMI))
FlashUt (LPC210x_ISP.EXE ("#H" ^X $D COM1: 9600 1))
StupF ("STARTUP\Philips\Startup.s" ("Philips LPC2100 Startup Code"))
FlashDR (UL2ARM(-U40296420 -O7 -C0 -FO7 -FD40000000 -FC800 -FN1 -FF0LPC_IAP_256 -FS00 -FL03E000))
Rgf (LPC21xx.H)
Mem ()
C ()
A ()
RL ()
OH ()
DBC_IFX ()
DBC_CMS ()
DBC_AMS ()
DBC_LMS ()
UseEnv=0
EnvBin (D:\DevTools\Keil\arm\ARM\BIN\)
EnvInc ()
EnvLib ()
EnvReg (ÿPhilips\)
OrgReg (ÿPhilips\)
TgStat=16
OutDir (.\)
OutName (rtosdemo_THUMB)
GenApp=1
GenLib=0
GenHex=0
Debug=1
Browse=0
LstDir (.\)
HexSel=0
MG32K=0
TGMORE=0
RunUsr 0 0 <>
RunUsr 1 0 <>
BrunUsr 0 0 <>
BrunUsr 1 0 <>
SVCSID <>
KACPU (ARM7TDMI)
TKAFL { 0,27,183,0,0,15,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
KIROM { 1,0,0,0,0,0,0,4,0 }
KIRAM { 0,0,0,0,64,0,64,0,0 }
KXRAM { 0,0,0,0,0,0,0,0,0 }
KAOCM { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
KCAFLG { 197,156,20,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
KCAMSC (INTERWORK)
KCADEF (KEIL_ARM7 KEIL_THUMB_INTERWORK)
KCAUDF ()
KCAINC (..\Common\include\;..\..\Source\include\;..\..\Source\portable\Keil\ARM7\)
KAAFLG { 20,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
KAAMSC ()
KAASET ()
KAARST ()
KAAINC ()
PropFld { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
IncBld=1
AlwaysBuild=0
GenAsm=0
AsmAsm=0
PublicsOnly=0
StopCode=3
CustArgs ()
LibMods ()
KLAFLG { 44,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
KLAMSC ()
KLADWN (25)
KLACFI ()
KLAASN ()
KLARES ()
KLACCL ()
KLAUCL ()
KLACSC ()
KLAUCS ()
OPTDL (SARM.DLL)(-cLPC2100)(DARMP.DLL)(-pLPC21x9)(SARM.DLL)()(TARMP.DLL)(-pLPC21x9)
OPTDBG 44029,-1,()()()()()()()()()() (BIN\UL2ARM.DLL)()()()
FLASH1 { 1,0,0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }
FLASH2 (BIN\UL2ARM.DLL)
FLASH3 ("LPC210x_ISP.EXE" ("#H" ^X $D COM1: 9600 1))
FLASH4 ()
EndOpt

247
Demo/ARM7_LPC2129_Keil/serial/serial.c Normal file
View file

@ -0,0 +1,247 @@
/*
FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
FreeRTOS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with FreeRTOS; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes FreeRTOS, without being obliged to provide
the source code for any proprietary components. See the licensing section
of http://www.FreeRTOS.org for full details of how and when the exception
can be applied.
***************************************************************************
See http://www.FreeRTOS.org for documentation, latest information, license
and contact details. Please ensure to read the configuration and relevant
port sections of the online documentation.
***************************************************************************
*/
/*
BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR UART0.
This file contains all the serial port components that can be compiled to
either ARM or THUMB mode. Components that must be compiled to ARM mode are
contained in serialISR.c.
*/
/* Standard includes. */
#include <stdlib.h>
/* Scheduler includes. */
#include "FreeRTOS.h"
#include "queue.h"
#include "task.h"
/* Demo application includes. */
#include "serial.h"
/*-----------------------------------------------------------*/
/* Constants to setup and access the UART. */
#define serDLAB ( ( unsigned portCHAR ) 0x80 )
#define serENABLE_INTERRUPTS ( ( unsigned portCHAR ) 0x03 )
#define serNO_PARITY ( ( unsigned portCHAR ) 0x00 )
#define ser1_STOP_BIT ( ( unsigned portCHAR ) 0x00 )
#define ser8_BIT_CHARS ( ( unsigned portCHAR ) 0x03 )
#define serFIFO_ON ( ( unsigned portCHAR ) 0x01 )
#define serCLEAR_FIFO ( ( unsigned portCHAR ) 0x06 )
#define serWANTED_CLOCK_SCALING ( ( unsigned portLONG ) 16 )
/* Constants to setup and access the VIC. */
#define serU0VIC_CHANNEL ( ( unsigned portLONG ) 0x0006 )
#define serU0VIC_CHANNEL_BIT ( ( unsigned portLONG ) 0x0040 )
#define serU0VIC_ENABLE ( ( unsigned portLONG ) 0x0020 )
/* Misc. */
#define serINVALID_QUEUE ( ( xQueueHandle ) 0 )
#define serHANDLE ( ( xComPortHandle ) 1 )
#define serNO_BLOCK ( ( portTickType ) 0 )
/*-----------------------------------------------------------*/
/* Queues used to hold received characters, and characters waiting to be
transmitted. */
static xQueueHandle xRxedChars;
static xQueueHandle xCharsForTx;
/*-----------------------------------------------------------*/
/* Communication flag between the interrupt service routine and serial API. */
static volatile portLONG *plTHREEmpty;
/*
* The queues are created in serialISR.c as they are used from the ISR.
* Obtain references to the queues and THRE Empty flag.
*/
extern void vSerialISRCreateQueues( unsigned portBASE_TYPE uxQueueLength, xQueueHandle *pxRxedChars, xQueueHandle *pxCharsForTx, portLONG volatile **pplTHREEmptyFlag );
/*-----------------------------------------------------------*/
xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength )
{
unsigned portLONG ulDivisor, ulWantedClock;
xComPortHandle xReturn = serHANDLE;
/* The queues are used in the serial ISR routine, so are created from
serialISR.c (which is always compiled to ARM mode). */
vSerialISRCreateQueues( uxQueueLength, &xRxedChars, &xCharsForTx, &plTHREEmpty );
if(
( xRxedChars != serINVALID_QUEUE ) &&
( xCharsForTx != serINVALID_QUEUE ) &&
( ulWantedBaud != ( unsigned portLONG ) 0 )
)
{
portENTER_CRITICAL();
{
/* The reference to the ISR function is required to load into the
interrupt controller. The prototype is slightly different
depending on whether in ARM or THUMB mode. */
#ifdef KEIL_THUMB_INTERWORK
extern void ( vUART_ISR )( void ) __arm __task;
#else
extern void ( vUART_ISR )( void ) __task;
#endif
/* Setup the baud rate: Calculate the divisor value. */
ulWantedClock = ulWantedBaud * serWANTED_CLOCK_SCALING;
ulDivisor = configCPU_CLOCK_HZ / ulWantedClock;
/* Set the DLAB bit so we can access the divisor. */
U0LCR |= serDLAB;
/* Setup the divisor. */
U0DLL = ( unsigned portCHAR ) ( ulDivisor & ( unsigned portLONG ) 0xff );
ulDivisor >>= 8;
U0DLM = ( unsigned portCHAR ) ( ulDivisor & ( unsigned portLONG ) 0xff );
/* Turn on the FIFO's and clear the buffers. */
U0FCR = ( serFIFO_ON | serCLEAR_FIFO );
/* Setup transmission format. */
U0LCR = serNO_PARITY | ser1_STOP_BIT | ser8_BIT_CHARS;
/* Setup the VIC for the UART. */
VICIntSelect &= ~( serU0VIC_CHANNEL_BIT );
VICIntEnable |= serU0VIC_CHANNEL_BIT;
VICVectAddr1 = ( unsigned portLONG ) vUART_ISR;
VICVectCntl1 = serU0VIC_CHANNEL | serU0VIC_ENABLE;
/* Enable UART0 interrupts. */
U0IER |= serENABLE_INTERRUPTS;
}
portEXIT_CRITICAL();
}
else
{
xReturn = ( xComPortHandle ) 0;
}
return xReturn;
}
/*-----------------------------------------------------------*/
signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime )
{
/* The port handle is not required as this driver only supports UART0. */
( void ) pxPort;
/* Get the next character from the buffer. Return false if no characters
are available, or arrive before xBlockTime expires. */
if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) )
{
return pdTRUE;
}
else
{
return pdFALSE;
}
}
/*-----------------------------------------------------------*/
void vSerialPutString( xComPortHandle pxPort, const signed portCHAR * const pcString, unsigned portSHORT usStringLength )
{
signed portCHAR *pxNext;
/* NOTE: This implementation does not handle the queue being full as no
block time is used! */
/* The port handle is not required as this driver only supports UART0. */
( void ) pxPort;
( void ) usStringLength;
/* Send each character in the string, one at a time. */
pxNext = ( signed portCHAR * ) pcString;
while( *pxNext )
{
xSerialPutChar( pxPort, *pxNext, serNO_BLOCK );
pxNext++;
}
}
/*-----------------------------------------------------------*/
signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime )
{
signed portBASE_TYPE xReturn;
/* The port handle is not required as this driver only supports UART0. */
( void ) pxPort;
portENTER_CRITICAL();
{
/* Is there space to write directly to the UART? */
if( *plTHREEmpty == ( portLONG ) pdTRUE )
{
/* We wrote the character directly to the UART, so was
successful. */
*plTHREEmpty = pdFALSE;
U0THR = cOutChar;
xReturn = pdPASS;
}
else
{
/* We cannot write directly to the UART, so queue the character.
Block for a maximum of xBlockTime if there is no space in the
queue. It is ok to block within a critical section as each
task has it's own critical section management. */
xReturn = xQueueSend( xCharsForTx, &cOutChar, xBlockTime );
/* Depending on queue sizing and task prioritisation: While we
were blocked waiting to post interrupts were not disabled. It is
possible that the serial ISR has emptied the Tx queue, in which
case we need to start the Tx off again. */
if( *plTHREEmpty == ( portLONG ) pdTRUE )
{
xQueueReceive( xCharsForTx, &cOutChar, serNO_BLOCK );
*plTHREEmpty = pdFALSE;
U0THR = cOutChar;
}
}
}
portEXIT_CRITICAL();
return xReturn;
}
/*-----------------------------------------------------------*/

160
Demo/ARM7_LPC2129_Keil/serial/serialISR.c Normal file
View file

@ -0,0 +1,160 @@
/*
FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
FreeRTOS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with FreeRTOS; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes FreeRTOS, without being obliged to provide
the source code for any proprietary components. See the licensing section
of http://www.FreeRTOS.org for full details of how and when the exception
can be applied.
***************************************************************************
See http://www.FreeRTOS.org for documentation, latest information, license
and contact details. Please ensure to read the configuration and relevant
port sections of the online documentation.
***************************************************************************
*/
/*
BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER FOR UART0.
This file contains all the serial port components that must be compiled
to ARM mode. The components that can be compiled to either ARM or THUMB
mode are contained in serial.c.
*/
/* This file must always be compiled to ARM mode as it contains ISR
definitions. */
#pragma ARM
/* Standard includes. */
#include <stdlib.h>
/* Scheduler includes. */
#include "FreeRTOS.h"
#include "queue.h"
#include "task.h"
/* Demo application includes. */
#include "serial.h"
/*-----------------------------------------------------------*/
/* Constant to access the VIC. */
#define serCLEAR_VIC_INTERRUPT ( ( unsigned portLONG ) 0 )
/* Constants to determine the ISR source. */
#define serSOURCE_THRE ( ( unsigned portCHAR ) 0x02 )
#define serSOURCE_RX_TIMEOUT ( ( unsigned portCHAR ) 0x0c )
#define serSOURCE_ERROR ( ( unsigned portCHAR ) 0x06 )
#define serSOURCE_RX ( ( unsigned portCHAR ) 0x04 )
#define serINTERRUPT_SOURCE_MASK ( ( unsigned portCHAR ) 0x0f )
/* Queues used to hold received characters, and characters waiting to be
transmitted. */
static xQueueHandle xRxedChars;
static xQueueHandle xCharsForTx;
static volatile portLONG lTHREEmpty;
/*-----------------------------------------------------------*/
/* UART0 interrupt service routine. This can cause a context switch so MUST
be declared "naked". */
void vUART_ISR( void );
/*-----------------------------------------------------------*/
void vSerialISRCreateQueues( unsigned portBASE_TYPE uxQueueLength, xQueueHandle *pxRxedChars,
xQueueHandle *pxCharsForTx, portLONG volatile **pplTHREEmptyFlag )
{
/* Create the queues used to hold Rx and Tx characters. */
xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );
xCharsForTx = xQueueCreate( uxQueueLength + 1, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );
/* Pass back a reference to the queues so the serial API file can
post/receive characters. */
*pxRxedChars = xRxedChars;
*pxCharsForTx = xCharsForTx;
/* Initialise the THRE empty flag - and pass back a reference. */
lTHREEmpty = pdTRUE;
*pplTHREEmptyFlag = &lTHREEmpty;
}
/*-----------------------------------------------------------*/
void vUART_ISR( void ) __task
{
portENTER_SWITCHING_ISR()
/* Now we can declare the local variables. */
static signed portCHAR cChar;
static portBASE_TYPE xTaskWokenByRx, xTaskWokenByTx;
xTaskWokenByTx = pdFALSE;
xTaskWokenByRx = pdFALSE;
/* What caused the interrupt? */
switch( U0IIR & serINTERRUPT_SOURCE_MASK )
{
case serSOURCE_ERROR : /* Not handling this, but clear the interrupt. */
cChar = U0LSR;
break;
case serSOURCE_THRE : /* The THRE is empty. If there is another
character in the Tx queue, send it now. */
if( xQueueReceiveFromISR( xCharsForTx, &cChar, &xTaskWokenByTx ) == pdTRUE )
{
U0THR = cChar;
}
else
{
/* There are no further characters
queued to send so we can indicate
that the THRE is available. */
lTHREEmpty = pdTRUE;
}
break;
case serSOURCE_RX_TIMEOUT :
case serSOURCE_RX : /* A character was received. Place it in
the queue of received characters. */
cChar = U0RBR;
if( xQueueSendFromISR( xRxedChars, &cChar, pdFALSE ) )
{
xTaskWokenByRx = pdTRUE;
}
break;
default : /* There is nothing to do, leave the ISR. */
break;
}
/* Clear the ISR in the VIC. */
VICVectAddr = serCLEAR_VIC_INTERRUPT;
/* Exit the ISR. If a task was woken by either a character being received
or transmitted then a context switch will occur. */
portEXIT_SWITCHING_ISR( ( xTaskWokenByTx || xTaskWokenByRx ) );
}
/*-----------------------------------------------------------*/

75
Demo/ARM7_STR71x_IAR/FreeRTOSConfig.h Normal file
View file

@ -0,0 +1,75 @@
/*
FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
FreeRTOS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with FreeRTOS; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes FreeRTOS, without being obliged to provide
the source code for any proprietary components. See the licensing section
of http://www.FreeRTOS.org for full details of how and when the exception
can be applied.
***************************************************************************
See http://www.FreeRTOS.org for documentation, latest information, license
and contact details. Please ensure to read the configuration and relevant
port sections of the online documentation.
***************************************************************************
*/
#ifndef FREERTOS_CONFIG_H
#define FREERTOS_CONFIG_H
/*-----------------------------------------------------------
* Application specific definitions.
*
* These definitions should be adjusted for your particular hardware and
* application requirements.
*
* THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
* FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
*----------------------------------------------------------*/
#define configUSE_PREEMPTION 1
#define configUSE_IDLE_HOOK 0
#define configUSE_TICK_HOOK 0
#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 48000000 )
#define configTICK_RATE_HZ ( ( portTickType ) 1000 )
#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 )
#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 100 )
#define configTOTAL_HEAP_SIZE ( ( size_t ) 20480 )
#define configMAX_TASK_NAME_LEN ( 16 )
#define configUSE_TRACE_FACILITY 0
#define configUSE_16_BIT_TICKS 0
#define configIDLE_SHOULD_YIELD 1
/* Co-routine definitions. */
#define configUSE_CO_ROUTINES 0
#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
/* Set the following definitions to 1 to include the API function, or zero
to exclude the API function. */
#define INCLUDE_vTaskPrioritySet 1
#define INCLUDE_uxTaskPriorityGet 1
#define INCLUDE_vTaskDelete 0
#define INCLUDE_vTaskCleanUpResources 0
#define INCLUDE_vTaskSuspend 1
#define INCLUDE_vTaskDelayUntil 1
#define INCLUDE_vTaskDelay 1
#endif /* FREERTOS_CONFIG_H */

157
Demo/ARM7_STR71x_IAR/Library/71x_lib.c Normal file
View file

@ -0,0 +1,157 @@
/******************** (C) COPYRIGHT 2003 STMicroelectronics ********************
* File Name : 71x_lib.c
* Author : MCD Application Team
* Date First Issued : 05/16/2003
* Description : Peripherals pointers initialization
********************************************************************************
* History:
* 30/11/2004 : V2.0
* 14/07/2004 : V1.3
* 01/01/2004 : V1.2
*******************************************************************************
THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
#define EXT
#include "71x_map.h"
#ifdef DEBUG
extern u32 T0TIMI_Addr;
/*******************************************************************************
* Function Name : debug
* Description : Initialize the pointers to peripherals
* Input : none
* Output : none
* Return : none
*******************************************************************************/
void debug(void)
{
#ifdef _ADC12
ADC12 = (ADC12_TypeDef *)ADC12_BASE;
#endif
#ifdef _APB
#ifdef _APB1
APB1 = (APB_TypeDef *)APB1_BASE;
#endif
#ifdef _APB2
APB2 = (APB_TypeDef *)APB2_BASE;
#endif
#endif
#ifdef _BSPI
#ifdef _BSPI0
BSPI0 = (BSPI_TypeDef *)BSPI0_BASE;
#endif
#ifdef _BSPI1
BSPI1 = (BSPI_TypeDef *)BSPI1_BASE;
#endif
#endif
#ifdef _CAN
CAN = (CAN_TypeDef *)CAN_BASE;
#endif
#ifdef _EIC
EIC = (EIC_TypeDef *)EIC_BASE;
#endif
#ifdef _EMI
EMI = (EMI_TypeDef *)EMI_BASE;
#endif
#ifdef _FLASH
FLASHR = (FLASHR_TypeDef *)FLASHR_BASE;
FLASHPR = (FLASHPR_TypeDef *)FLASHPR_BASE;
#endif
#ifdef _GPIO
#ifdef _GPIO0
GPIO0 = (GPIO_TypeDef *)GPIO0_BASE;
#endif
#ifdef _GPIO1
GPIO1 = (GPIO_TypeDef *)GPIO1_BASE;
#endif
#ifdef _GPIO2
GPIO2 = (GPIO_TypeDef *)GPIO2_BASE;
#endif
#endif
#ifdef _I2C
#ifdef _I2C0
I2C0 = (I2C_TypeDef *)I2C0_BASE;
#endif
#ifdef _I2C1
I2C1 = (I2C_TypeDef *)I2C1_BASE;
#endif
#endif
#ifdef _PCU
PCU = (PCU_TypeDef *)PCU_BASE;
#endif
#ifdef _RCCU
RCCU = (RCCU_TypeDef *)RCCU_BASE;
#endif
#ifdef _RTC
RTC = (RTC_TypeDef *)RTC_BASE;
#endif
#ifdef _TIM
#ifdef _TIM0
TIM0 = (TIM_TypeDef *)TIM0_BASE;
#endif
#ifdef _TIM1
TIM1 = (TIM_TypeDef *)TIM1_BASE;
#endif
#ifdef _TIM2
TIM2 = (TIM_TypeDef *)TIM2_BASE;
#endif
#ifdef _TIM3
TIM3 = (TIM_TypeDef *)TIM3_BASE;
#endif
#endif
#ifdef _UART
#ifdef _UART0
UART0 = (UART_TypeDef *)UART0_BASE;
#endif
#ifdef _UART1
UART1 = (UART_TypeDef *)UART1_BASE;
#endif
#ifdef _UART2
UART2 = (UART_TypeDef *)UART2_BASE;
#endif
#ifdef _UART3
UART3 = (UART_TypeDef *)UART3_BASE;
#endif
#endif
#ifdef _USB
USB = (USB_TypeDef *)USB_BASE;
#endif
#ifdef _WDG
WDG = (WDG_TypeDef *)WDG_BASE;
#endif
#ifdef _XTI
XTI = (XTI_TypeDef *)XTI_BASE;
#endif
#ifdef _IRQVectors
IRQVectors = (IRQVectors_TypeDef *)&T0TIMI_Addr;
#endif
}
#endif /* DEBUG */
/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/

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/******************** (C) COPYRIGHT 2003 STMicroelectronics ********************
* File Name : gpio.c
* Author : MCD Application Team
* Date First Issued : 06/08/2003
* Description : This file provides all the GPIO software functions
********************************************************************************
* History:
* 30/11/2004 : V2.0
* 14/07/2004 : V1.3
* 01/01/2004 : V1.2
*******************************************************************************
THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
#include "gpio.h"
/*******************************************************************************
* Function Name : GPIO_Config
* Description : Configure the GPIO port pins
* Input 1 : GPIOx (x can be 0,1 or 2) the desired port
* Input 2 : Port_Pins : pins placements
* Input 3 : Pins Mode
* Output : None
* Return : None
*******************************************************************************/
void GPIO_Config (GPIO_TypeDef *GPIOx, u16 Port_Pins, GpioPinMode_TypeDef GPIO_Mode)
{
switch (GPIO_Mode)
{
case GPIO_HI_AIN_TRI:
GPIOx->PC0&=~Port_Pins;
GPIOx->PC1&=~Port_Pins;
GPIOx->PC2&=~Port_Pins;
break;
case GPIO_IN_TRI_TTL:
GPIOx->PC0|=Port_Pins;
GPIOx->PC1&=~Port_Pins;
GPIOx->PC2&=~Port_Pins;
break;
case GPIO_IN_TRI_CMOS:
GPIOx->PC0&=~Port_Pins;
GPIOx->PC1|=Port_Pins;
GPIOx->PC2&=~Port_Pins;
break;
case GPIO_IPUPD_WP:
GPIOx->PC0|=Port_Pins;
GPIOx->PC1|=Port_Pins;
GPIOx->PC2&=~Port_Pins;
break;
case GPIO_OUT_OD:
GPIOx->PC0&=~Port_Pins;
GPIOx->PC1&=~Port_Pins;
GPIOx->PC2|=Port_Pins;
break;
case GPIO_OUT_PP:
GPIOx->PC0|=Port_Pins;
GPIOx->PC1&=~Port_Pins;
GPIOx->PC2|=Port_Pins;
break;
case GPIO_AF_OD:
GPIOx->PC0&=~Port_Pins;
GPIOx->PC1|=Port_Pins;
GPIOx->PC2|=Port_Pins;
break;
case GPIO_AF_PP:
GPIOx->PC0|=Port_Pins;
GPIOx->PC1|=Port_Pins;
GPIOx->PC2|=Port_Pins;
break;
}
}
/*******************************************************************************
* Function Name : GPIO_BitWrite
* Description : Set or reset the selected port pin
* Input 1 : Selected GPIO port
* Input 2 : Pin number
* Input 3 : bit value
* Output : None
* Return : None
*******************************************************************************/
void GPIO_BitWrite(GPIO_TypeDef *GPIOx, u8 Port_Pin, u8 Port_Val)
{
if (Port_Val&0x01) GPIOx->PD |= 1<<Port_Pin; else GPIOx->PD &= ~(1<<Port_Pin);
}
/*******************************************************************************
* Function Name : GPIO_ByteWrite
* Description : Write byte value to the selected PD register
* Input 1 : Selected GPIO port
* Input 2 : GPIO_MSB or GPIO_LSB
* Input 3 : Byte value
* Output : None
* Return : None
*******************************************************************************/
void GPIO_ByteWrite(GPIO_TypeDef *GPIOx, u8 Port_Byte, u8 Port_Val)
{
GPIOx->PD = Port_Byte ? (GPIOx->PD&0x00FF) | ((u16)Port_Val<<8)
: (GPIOx->PD&0xFF00) | Port_Val;
}
/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/

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/******************** (C) COPYRIGHT 2003 STMicroelectronics ********************
* File Name : 71x_conf.h
* Author : MCD Application Team
* Date First Issued : 16/05/2003
* Description : Library configuration for the ADC12 example
********************************************************************************
* History:
* 16/05/2003 : Created
* 30/11/2004 : V2.0
*******************************************************************************
THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
#ifndef __71x_CONF_H
#define __71x_CONF_H
/* Comment the line below to put the library in release mode */
//#define DEBUG
//#define inline inline
//#define USE_SERIAL_PORT
//#define USE_UART0
// Main Oscillator Frequency value = 4 Mhz
#define RCCU_Main_Osc 4000000
/* Comment the lines below corresponding to unwanted peripherals */
//#define _ADC12
//#define _APB
//#define _APB1
//#define _APB2
//#define _BSPI
//#define _BSPI0
//#define _BSPI1
//#define _CAN
//#define _EIC
//#define _EMI
//#define _FLASH
#define _GPIO
#define _GPIO0
#define _GPIO1
#define _GPIO2
//#define _I2C
//#define _I2C0
//#define _I2C1
#define _PCU
#define _RCCU
//#define _RTC
#define _TIM
#define _TIM0
//#define _TIM1
//#define _TIM2
//#define _TIM3
//#define _UART
//#define _UART0
//#define _UART1
//#define _UART2
//#define _UART3
//#define _USB
//#define _WDG
//#define _XTI
//#define _IRQVectors
#endif /* __71x_CONF_H */
/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/

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/******************** (C) COPYRIGHT 2003 STMicroelectronics ********************
* File Name : 71x_it.h
* Author : MCD Application Team
* Date First Issued : 05/16/2003
* Description : Interrupt handlers
********************************************************************************
* History:
* 30/11/2004 : V2.0
* 14/07/2004 : V1.3
* 01/01/2004 : V1.2
*******************************************************************************
THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
#ifndef _71x_IT_H
#define _71x_IT_H
#include "71x_lib.h"
void Undefined_Handler (void);
void FIQ_Handler (void);
void SWI_Handler (void);
void Prefetch_Handler (void);
void Abort_Handler (void);
void T0TIMI_IRQHandler (void);
void FLASH_IRQHandler (void);
void RCCU_IRQHandler (void);
void RTC_IRQHandler (void);
void WDG_IRQHandler (void);
void XTI_IRQHandler (void);
void USBHP_IRQHandler (void);
void I2C0ITERR_IRQHandler(void);
void I2C1ITERR_IRQHandler(void);
void UART0_IRQHandler (void);
void UART1_IRQHandler (void);
void UART2_IRQHandler (void);
void UART3_IRQHandler (void);
void BSPI0_IRQHandler (void);
void BSPI1_IRQHandler (void);
void I2C0_IRQHandler (void);
void I2C1_IRQHandler (void);
void CAN_IRQHandler (void);
void ADC12_IRQHandler (void);
void T1TIMI_IRQHandler (void);
void T2TIMI_IRQHandler (void);
void T3TIMI_IRQHandler (void);
void HDLC_IRQHandler (void);
void USBLP_IRQHandler (void);
void T0TOI_IRQHandler (void);
void T0OC1_IRQHandler (void);
void T0OC2_IRQHandler (void);
#endif /* _71x_IT_H */
/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/

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/******************** (C) COPYRIGHT 2003 STMicroelectronics ********************
* File Name : 71x_lib.h
* Author : MCD Application Team
* Date First Issued : 05/16/2003
* Description : Global include for all peripherals
********************************************************************************
* 30/11/2004 : V2.0
* 14/07/2004 : V1.3
* 01/01/2004 : V1.2
*******************************************************************************
THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
#ifndef __71x_LIB_H
#define __71x_LIB_H
#include "71x_map.h"
#include "71x_conf.h"
#ifdef _ADC12
#include "adc12.h"
#endif
#ifdef _APB
#include "apb.h"
#endif
#ifdef _BSPI
#include "bspi.h"
#endif
#ifdef _CAN
#include "can.h"
#endif
#ifdef _EIC
#include "eic.h"
#endif
#ifdef _EMI
#include "emi.h"
#endif
#ifdef _FLASH
#include "flash.h"
#endif
#ifdef _GPIO
#include "gpio.h"
#endif
#ifdef _I2C
#include "i2c.h"
#endif
#ifdef _PCU
#include "pcu.h"
#endif
#ifdef _RCCU
#include "rccu.h"
#endif
#ifdef _RTC
#include "rtc.h"
#endif
#ifdef _TIM
#include "tim.h"
#endif
#ifdef _UART
#include "uart.h"
#endif
#ifdef _USB
#endif
#ifdef _WDG
#include "wdg.h"
#endif
#ifdef _XTI
#include "xti.h"
#endif
#ifdef DEBUG
void debug(void);
#endif
#endif /* __71x_LIB_H */
/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/

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/******************** (C) COPYRIGHT 2003 STMicroelectronics ********************
* File Name : 71x_map.h
* Author : MCD Application Team
* Date First Issued : 05/16/2003
* Description : Peripherals memory mapping and registers structures
********************************************************************************
* History:
* 30/11/2004 : V2.0
* 14/07/2004 : V1.3
* 01/01/2004 : V1.2
*******************************************************************************
THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
#ifndef __71x_map_H
#define __71x_map_H
#ifndef EXT
#define EXT extern
#endif
#include "71x_conf.h"
#include "71x_type.h"
/* IP registers structures */
typedef volatile struct
{
vu16 DATA0;
vu16 EMPTY1[3];
vu16 DATA1;
vu16 EMPTY2[3];
vu16 DATA2;
vu16 EMPTY3[3];
vu16 DATA3;
vu16 EMPTY4[3];
vu16 CSR;
vu16 EMPTY5[7];
vu16 CPR;
} ADC12_TypeDef;
typedef volatile struct
{
vu32 CKDIS;
vu32 SWRES;
} APB_TypeDef;
typedef volatile struct
{
vu16 RXR;
vu16 EMPTY1;
vu16 TXR;
vu16 EMPTY2;
vu16 CSR1;
vu16 EMPTY3;
vu16 CSR2;
vu16 EMPTY4;
vu16 CLK;
} BSPI_TypeDef;
typedef volatile struct
{
vu16 CRR;
vu16 EMPTY1;
vu16 CMR;
vu16 EMPTY2;
vu16 M1R;
vu16 EMPTY3;
vu16 M2R;
vu16 EMPTY4;
vu16 A1R;
vu16 EMPTY5;
vu16 A2R;
vu16 EMPTY6;
vu16 MCR;
vu16 EMPTY7;
vu16 DA1R;
vu16 EMPTY8;
vu16 DA2R;
vu16 EMPTY9;
vu16 DB1R;
vu16 EMPTY10;
vu16 DB2R;
vu16 EMPTY11[27];
} CAN_MsgObj_TypeDef;
typedef volatile struct
{
vu16 CR;
vu16 EMPTY1;
vu16 SR;
vu16 EMPTY2;
vu16 ERR;
vu16 EMPTY3;
vu16 BTR;
vu16 EMPTY4;
vu16 IDR;
vu16 EMPTY5;
vu16 TESTR;
vu16 EMPTY6;
vu16 BRPR;
vu16 EMPTY7[3];
CAN_MsgObj_TypeDef sMsgObj[2];
vu16 EMPTY8[16];
vu16 TR1R;
vu16 EMPTY9;
vu16 TR2R;
vu16 EMPTY10[13];
vu16 ND1R;
vu16 EMPTY11;
vu16 ND2R;
vu16 EMPTY12[13];
vu16 IP1R;
vu16 EMPTY13;
vu16 IP2R;
vu16 EMPTY14[13];
vu16 MV1R;
vu16 EMPTY15;
vu16 MV2R;
vu16 EMPTY16;
} CAN_TypeDef;
typedef volatile struct
{
vu32 ICR;
vu32 CICR;
vu32 CIPR;
vu32 EMPTY1[3];
vu32 IVR;
vu32 FIR;
vu32 IER;
vu32 EMPTY2[7];
vu32 IPR;
vu32 EMPTY3[7];
vu32 SIR[32];
} EIC_TypeDef;
typedef volatile struct
{
vu16 BCON0;
vu16 EMPTY1;
vu16 BCON1;
vu16 EMPTY2;
vu16 BCON2;
vu16 EMPTY3;
vu16 BCON3;
vu16 EMPTY4;
} EMI_TypeDef;
typedef volatile struct
{
vu32 CR0;
vu32 CR1;
vu32 DR0;
vu32 DR1;
vu32 AR;
vu32 ER;
} FLASHR_TypeDef;
typedef volatile struct
{
vu32 NVWPAR;
vu32 EMPTY;
vu32 NVAPR0;
vu32 NVAPR1;
} FLASHPR_TypeDef;
typedef volatile struct
{
vu16 PC0;
vu16 EMPTY1;
vu16 PC1;
vu16 EMPTY2;
vu16 PC2;
vu16 EMPTY3;
vu16 PD;
vu16 EMPTY4;
} GPIO_TypeDef;
typedef volatile struct
{
vu8 CR;
vu8 EMPTY1[3];
vu8 SR1;
vu8 EMPTY2[3];
vu8 SR2;
vu8 EMPTY3[3];
vu8 CCR;
vu8 EMPTY4[3];
vu8 OAR1;
vu8 EMPTY5[3];
vu8 OAR2;
vu8 EMPTY6[3];
vu8 DR;
vu8 EMPTY7[3];
vu8 ECCR;
} I2C_TypeDef;
typedef volatile struct
{
vu32 CCR;
vu32 EMPTY1;
vu32 CFR;
vu32 EMPTY2[3];
vu32 PLL1CR;
vu32 PER;
vu32 SMR;
} RCCU_TypeDef;
typedef volatile struct
{
vu16 MDIVR;
vu16 EMPTY1;
vu16 PDIVR;
vu16 EMPTY2;
vu16 RSTR;
vu16 EMPTY3;
vu16 PLL2CR;
vu16 EMPTY4;
vu16 BOOTCR;
vu16 EMPTY5;
vu16 PWRCR;
} PCU_TypeDef;
typedef volatile struct
{
vu16 CRH;
vu16 EMPTY1;
vu16 CRL;
vu16 EMPTY2;
vu16 PRLH;
vu16 EMPTY3;
vu16 PRLL;
vu16 EMPTY4;
vu16 DIVH;
vu16 EMPTY5;
vu16 DIVL;
vu16 EMPTY6;
vu16 CNTH;
vu16 EMPTY7;
vu16 CNTL;
vu16 EMPTY8;
vu16 ALRH;
vu16 EMPTY9;
vu16 ALRL;
} RTC_TypeDef;
typedef volatile struct
{
vu16 ICAR;
vu16 EMPTY1;
vu16 ICBR;
vu16 EMPTY2;
vu16 OCAR;
vu16 EMPTY3;
vu16 OCBR;
vu16 EMPTY4;
vu16 CNTR;
vu16 EMPTY5;
vu16 CR1;
vu16 EMPTY6;
vu16 CR2;
vu16 EMPTY7;
vu16 SR;
} TIM_TypeDef;
typedef volatile struct
{
vu16 BR;
vu16 EMPTY1;
vu16 TxBUFR;
vu16 EMPTY2;
vu16 RxBUFR;
vu16 EMPTY3;
vu16 CR;
vu16 EMPTY4;
vu16 IER;
vu16 EMPTY5;
vu16 SR;
vu16 EMPTY6;
vu16 GTR;
vu16 EMPTY7;
vu16 TOR;
vu16 EMPTY8;
vu16 TxRSTR;
vu16 EMPTY9;
vu16 RxRSTR;
} UART_TypeDef;
typedef volatile struct
{
vu32 EP0R;
vu32 EP1R;
vu32 EP2R;
vu32 EP3R;
vu32 EP4R;
vu32 EP5R;
vu32 EP6R;
vu32 EP7R;
vu32 EP8R;
vu32 EP9R;
vu32 EP10R;
vu32 EP11R;
vu32 EP12R;
vu32 EP13R;
vu32 EP14R;
vu32 EP15R;
vu32 CNTR;
vu32 ISTR;
vu32 FNR;
vu32 DADDR;
vu32 BTABLE;
} USB_TypeDef;
typedef volatile struct
{
vu16 CR;
vu16 EMPTY1;
vu16 PR;
vu16 EMPTY2;
vu16 VR;
vu16 EMPTY3;
vu16 CNT;
vu16 EMPTY4;
vu16 SR;
vu16 EMPTY5;
vu16 MR;
vu16 EMPTY6;
vu16 KR;
} WDG_TypeDef;
typedef volatile struct
{
vu8 SR;
vu8 EMPTY1[7];
vu8 CTRL;
vu8 EMPTY2[3];
vu8 MRH;
vu8 EMPTY3[3];
vu8 MRL;
vu8 EMPTY4[3];
vu8 TRH;
vu8 EMPTY5[3];
vu8 TRL;
vu8 EMPTY6[3];
vu8 PRH;
vu8 EMPTY7[3];
vu8 PRL;
} XTI_TypeDef;
/* IRQ vectors */
typedef volatile struct
{
vu32 T0TIMI_IRQHandler;
vu32 FLASH_IRQHandler;
vu32 RCCU_IRQHandler;
vu32 RTC_IRQHandler;
vu32 WDG_IRQHandler;
vu32 XTI_IRQHandler;
vu32 USBHP_IRQHandler;
vu32 I2C0ITERR_IRQHandler;
vu32 I2C1ITERR_IRQHandler;
vu32 UART0_IRQHandler;
vu32 UART1_IRQHandler;
vu32 UART2_IRQHandler;
vu32 UART3_IRQHandler;
vu32 BSPI0_IRQHandler;
vu32 BSPI1_IRQHandler;
vu32 I2C0_IRQHandler;
vu32 I2C1_IRQHandler;
vu32 CAN_IRQHandler;
vu32 ADC12_IRQHandler;
vu32 T1TIMI_IRQHandler;
vu32 T2TIMI_IRQHandler;
vu32 T3TIMI_IRQHandler;
vu32 EMPTY1[3];
vu32 HDLC_IRQHandler;
vu32 USBLP_IRQHandler;
vu32 EMPTY2[2];
vu32 T0TOI_IRQHandler;
vu32 T0OC1_IRQHandler;
vu32 T0OC2_IRQHandler;
} IRQVectors_TypeDef;
/*===================================================================*/
/* Memory mapping */
#define RAM_BASE 0x20000000
#define FLASHR_BASE 0x40100000
#define FLASHPR_BASE 0x4010DFB0
#define EXTMEM_BASE 0x60000000
#define RCCU_BASE 0xA0000000
#define PCU_BASE 0xA0000040
#define APB1_BASE 0xC0000000
#define APB2_BASE 0xE0000000
#define EIC_BASE 0xFFFFF800
#define I2C0_BASE (APB1_BASE + 0x1000)
#define I2C1_BASE (APB1_BASE + 0x2000)
#define UART0_BASE (APB1_BASE + 0x4000)
#define UART1_BASE (APB1_BASE + 0x5000)
#define UART2_BASE (APB1_BASE + 0x6000)
#define UART3_BASE (APB1_BASE + 0x7000)
#define CAN_BASE (APB1_BASE + 0x9000)
#define BSPI0_BASE (APB1_BASE + 0xA000)
#define BSPI1_BASE (APB1_BASE + 0xB000)
#define USB_BASE (APB1_BASE + 0x8800)
#define XTI_BASE (APB2_BASE + 0x101C)
#define GPIO0_BASE (APB2_BASE + 0x3000)
#define GPIO1_BASE (APB2_BASE + 0x4000)
#define GPIO2_BASE (APB2_BASE + 0x5000)
#define ADC12_BASE (APB2_BASE + 0x7000)
#define TIM0_BASE (APB2_BASE + 0x9000)
#define TIM1_BASE (APB2_BASE + 0xA000)
#define TIM2_BASE (APB2_BASE + 0xB000)
#define TIM3_BASE (APB2_BASE + 0xC000)
#define RTC_BASE (APB2_BASE + 0xD000)
#define WDG_BASE (APB2_BASE + 0xE000)
#define EMI_BASE (EXTMEM_BASE + 0x0C000000)
/*===================================================================*/
/* IP data access */
#ifndef DEBUG
#define ADC12 ((ADC12_TypeDef *)ADC12_BASE)
#define APB1 ((APB_TypeDef *)APB1_BASE)
#define APB2 ((APB_TypeDef *)APB2_BASE+0x10)
#define BSPI0 ((BSPI_TypeDef *)BSPI0_BASE)
#define BSPI1 ((BSPI_TypeDef *)BSPI1_BASE)
#define CAN ((CAN_TypeDef *)CAN_BASE)
#define EIC ((EIC_TypeDef *)EIC_BASE)
#define EMI ((EMI_TypeDef *)EMI_BASE)
#define FLASHR ((FLASHR_TypeDef *)FLASHR_BASE)
#define FLASHPR ((FLASHPR_TypeDef *)FLASHPR_BASE)
#define GPIO0 ((GPIO_TypeDef *)GPIO0_BASE)
#define GPIO1 ((GPIO_TypeDef *)GPIO1_BASE)
#define GPIO2 ((GPIO_TypeDef *)GPIO2_BASE)
#define I2C0 ((I2C_TypeDef *)I2C0_BASE)
#define I2C1 ((I2C_TypeDef *)I2C1_BASE)
#define PCU ((PCU_TypeDef *)PCU_BASE)
#define RCCU ((RCCU_TypeDef *)RCCU_BASE)
#define RTC ((RTC_TypeDef *)RTC_BASE)
#define TIM0 ((TIM_TypeDef *)TIM0_BASE)
#define TIM1 ((TIM_TypeDef *)TIM1_BASE)
#define TIM2 ((TIM_TypeDef *)TIM2_BASE)
#define TIM3 ((TIM_TypeDef *)TIM3_BASE)
#define UART0 ((UART_TypeDef *)UART0_BASE)
#define UART1 ((UART_TypeDef *)UART1_BASE)
#define UART2 ((UART_TypeDef *)UART2_BASE)
#define UART3 ((UART_TypeDef *)UART3_BASE)
#define USB ((USB_TypeDef *)USB_BASE)
#define WDG ((WDG_TypeDef *)WDG_BASE)
#define XTI ((XTI_TypeDef *)XTI_BASE)
#define IRQVectors ((IRQVectors_TypeDef *)&T0TIMI_Addr)
#else /* DEBUG */
#ifdef _ADC12
EXT ADC12_TypeDef *ADC12;
#endif
#ifdef _APB
#ifdef _APB1
EXT APB_TypeDef *APB1;
#endif
#ifdef _APB2
EXT APB_TypeDef *APB2;
#endif
#endif
#ifdef _BSPI
#ifdef _BSPI0
EXT BSPI_TypeDef *BSPI0;
#endif
#ifdef _BSPI1
EXT BSPI_TypeDef *BSPI1;
#endif
#endif
#ifdef _CAN
EXT CAN_TypeDef *CAN;
#endif
#ifdef _EIC
EXT EIC_TypeDef *EIC;
#endif
#ifdef _EMI
EXT EMI_TypeDef *EMI;
#endif
#ifdef _FLASH
EXT FLASHR_TypeDef *FLASHR;
EXT FLASHPR_TypeDef *FLASHPR;
#endif
#ifdef _GPIO
#ifdef _GPIO0
EXT GPIO_TypeDef *GPIO0;
#endif
#ifdef _GPIO1
EXT GPIO_TypeDef *GPIO1;
#endif
#ifdef _GPIO2
EXT GPIO_TypeDef *GPIO2;
#endif
#endif
#ifdef _I2C
#ifdef _I2C0
EXT I2C_TypeDef *I2C0;
#endif
#ifdef _I2C1
EXT I2C_TypeDef *I2C1;
#endif
#endif
#ifdef _PCU
EXT PCU_TypeDef *PCU;
#endif
#ifdef _RCCU
EXT RCCU_TypeDef *RCCU;
#endif
#ifdef _RTC
EXT RTC_TypeDef *RTC;
#endif
#ifdef _TIM
#ifdef _TIM0
EXT TIM_TypeDef *TIM0;
#endif
#ifdef _TIM1
EXT TIM_TypeDef *TIM1;
#endif
#ifdef _TIM2
EXT TIM_TypeDef *TIM2;
#endif
#ifdef _TIM3
EXT TIM_TypeDef *TIM3;
#endif
#endif
#ifdef _UART
#ifdef _UART0
EXT UART_TypeDef *UART0;
#endif
#ifdef _UART1
EXT UART_TypeDef *UART1;
#endif
#ifdef _UART2
EXT UART_TypeDef *UART2;
#endif
#ifdef _UART3
EXT UART_TypeDef *UART3;
#endif
#endif
#ifdef _USB
EXT USB_TypeDef *USB;
#endif
#ifdef _WDG
EXT WDG_TypeDef *WDG;
#endif
#ifdef _XTI
EXT XTI_TypeDef *XTI;
#endif
#ifdef _IRQVectors
EXT IRQVectors_TypeDef *IRQVectors;
#endif
#endif /* DEBUG */
#endif /* __71x_map_H */
/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/

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/******************** (C) COPYRIGHT 2003 STMicroelectronics ********************
* File Name : 71x_type.h
* Author : MCD Application Team
* Date First Issued : 05/16/2003
* Description : Common data types
********************************************************************************
* History:
* 30/11/2004 : V2.0
* 14/07/2004 : V1.3
* 01/01/2004 : V1.2
*******************************************************************************
THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
#ifndef _71x_type_H
#define _71x_type_H
typedef unsigned long u32;
typedef unsigned short u16;
typedef unsigned char u8;
typedef signed long s32;
typedef signed short s16;
typedef signed char s8;
typedef volatile unsigned long vu32;
typedef volatile unsigned short vu16;
typedef volatile unsigned char vu8;
typedef volatile signed long vs32;
typedef volatile signed short vs16;
typedef volatile signed char vs8;
/*===================================================================*/
typedef enum { FALSE = 0, TRUE = !FALSE } bool;
/*===================================================================*/
typedef enum { RESET = 0, SET = !RESET } FlagStatus;
/*===================================================================*/
typedef enum { DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
/*===================================================================*/
typedef enum { INDIRECT = 0, DIRECT = !INDIRECT} RegisterAccess;
/*===================================================================*/
#endif /* _71x_type_H */
/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/

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/******************** (C) COPYRIGHT 2003 STMicroelectronics ********************
* File Name : eic.h
* Author : MCD Application Team
* Date First Issued : 25/06/2003
* Description : This file contains all the functions prototypes for the
* EIC software library.
********************************************************************************
* History:
* 30/11/2004 : V2.0
* 14/07/2004 : V1.3
* 01/01/2004 : V1.2
*******************************************************************************
THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
#ifndef __eic_H
#define __eic_H
#include "71x_map.h"
typedef enum
{
T0TIMI_IRQChannel = 0,
FLASH_IRQChannel = 1,
RCCU_IRQChannel = 2,
RTC_IRQChannel = 3,
WDG_IRQChannel = 4,
XTI_IRQChannel = 5,
USBHP_IRQChannel = 6,
I2C0ITERR_IRQChannel = 7,
I2C1ITERR_IRQChannel = 8,
UART0_IRQChannel = 9,
UART1_IRQChannel = 10,
UART2_IRQChannel = 11,
UART3_IRQChannel = 12,
SPI0_IRQChannel = 13,
SPI1_IRQChannel = 14,
I2C0_IRQChannel = 15,
I2C1_IRQChannel = 16,
CAN_IRQChannel = 17,
ADC_IRQChannel = 18,
T1TIMI_IRQChannel = 19,
T2TIMI_IRQChannel = 20,
T3TIMI_IRQChannel = 21,
HDLC_IRQChannel = 25,
USBLP_IRQChannel = 26,
T0TOI_IRQChannel = 29,
T0OC1_IRQChannel = 30,
T0OC2_IRQChannel = 31
} IRQChannel_TypeDef;
typedef enum
{
T0TIMI_FIQChannel = 0x00000001,
WDG_FIQChannel = 0x00000002,
WDGT0TIMI_FIQChannels = 0x00000003
} FIQChannel_TypeDef;
/*******************************************************************************
* Function Name : EIC_Init
* Description : Initialise the EIC using the load PC instruction
* (PC = PC +offset)
* Input : None
* Output : None
* Return : None
*******************************************************************************/
void EIC_Init(void);
/*******************************************************************************
* Function Name : EIC_IRQConfig
* Description : Enable or Disable IRQ interrupts
* Input 1 : New status : can be ENABLE or DISABLE
* Output : None
* Return : None
*******************************************************************************/
inline void EIC_IRQConfig(FunctionalState NewState)
{
if (NewState==ENABLE) EIC->ICR |= 0x0001; else EIC->ICR &= ~0x0001;
}
/*******************************************************************************
* Function Name : EIC_FIQConfig
* Description : Enable or Disable FIQ interrupts
* Input 1 : New status : can be ENABLE or DISABLE
* Output : None
* Return : None
*******************************************************************************/
inline void EIC_FIQConfig(FunctionalState NewState)
{
if (NewState==ENABLE) EIC->ICR |= 0x0002; else EIC->ICR &= ~0x0002;
}
/*******************************************************************************
* Function Name : EIC_IRQChannelConfig
* Description : Configure the IRQ Channel
* Input 1 : IRQ channel name
* Input 2 : Channel New status : can be ENABLE or DISABLE
* Output : None
* Return : None
*******************************************************************************/
inline void EIC_IRQChannelConfig(IRQChannel_TypeDef IRQChannel, FunctionalState NewState)
{
if (NewState==ENABLE) EIC->IER |= 0x0001 << IRQChannel;
else EIC->IER &= ~(0x0001 << IRQChannel);
}
/*******************************************************************************
* Function Name : EIC_FIQChannelConfig
* Description : Configure the FIQ Channel
* Input 1 : FIQ channel name
* Input 2 : Channel New status : can be ENABLE or DISABLE
* Output : None
* Return : None
*******************************************************************************/
inline void EIC_FIQChannelConfig(FIQChannel_TypeDef FIQChannel,
FunctionalState NewState)
{
if (NewState==ENABLE) EIC->FIR |= FIQChannel;
else EIC->FIR &= ~FIQChannel;
}
/*******************************************************************************
* Function Name : EIC_IRQChannelPriorityConfig
* Description : Configure the selected IRQ channel priority
* Input 1 : IRQ channel name
* Input 2 : IRQ channel priority
* Output : None
* Return : None
*******************************************************************************/
inline void EIC_IRQChannelPriorityConfig(IRQChannel_TypeDef IRQChannel, u8 Priority)
{
EIC->SIR[IRQChannel] = (EIC->SIR[IRQChannel]&0xFFFF0000) | (u16)Priority & 0x000F;
}
/*******************************************************************************
* Function Name : EIC_CurrentPriorityLevelConfig
* Description : Change the current priority level of the srved IRQ routine
* Input 1 : New priority
* Output : None
* Return : None
*******************************************************************************/
void EIC_CurrentPriorityLevelConfig(u8 NewPriorityLevel);
/*******************************************************************************
* Function Name : EIC_CurrentPriorityLevelValue
* Description : Return the current priority level of the current served IRQ
* routine
* Input : None
* Output : None
* Return : The current priority level
*******************************************************************************/
inline u8 EIC_CurrentPriorityLevelValue(void)
{
return EIC->CIPR & 0xF;
}
/*******************************************************************************
* Function Name : EIC_CurrentIRQChannelValue
* Description : Return the current served IRQ channel number
* Input 0 : None
* Output : None
* Return : The current served IRQ channel number
*******************************************************************************/
inline IRQChannel_TypeDef EIC_CurrentIRQChannelValue(void)
{
return (IRQChannel_TypeDef)(EIC->CICR & 0x1F);
}
/*******************************************************************************
* Function Name : EIC_CurrentFIQChannelValue
* Description : Return the current served FIQ channel number
* Input : None
* Output : None
* Return : The current served FIQ channel number
*******************************************************************************/
inline FIQChannel_TypeDef EIC_CurrentFIQChannelValue(void)
{
return (FIQChannel_TypeDef)((EIC->FIR >> 2) & 0x0003);
}
/*******************************************************************************
* Function Name : EIC_FIPendingBitClear
* Description : Clear the FIQ pending bit
* Input 1 : FIQ channel
* Output : None
* Return : None
*******************************************************************************/
inline void EIC_FIQPendingBitClear(FIQChannel_TypeDef FIQChannel)
{
EIC->FIR = (EIC->FIR & 0x0003) | (FIQChannel << 2);
}
#endif /* __eic_H */
/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/

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/******************** (C) COPYRIGHT 2003 STMicroelectronics ********************
* File Name : gpio.h
* Author : MCD Application Team
* Date First Issued : 08/06/2003
* Description : This file contains all the functions prototypes for the
* GPIO software library.
********************************************************************************
* History:
* 30/11/2004 : V2.0
* 14/07/2004 : V1.3
* 01/01/2004 : V1.2
*******************************************************************************
THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
#ifndef __gpio_H
#define __gpio_H
#include "71x_map.h"
typedef enum
{
GPIO_HI_AIN_TRI,
GPIO_IN_TRI_TTL,
GPIO_IN_TRI_CMOS,
GPIO_IPUPD_WP,
GPIO_OUT_OD,
GPIO_OUT_PP,
GPIO_AF_OD,
GPIO_AF_PP
} GpioPinMode_TypeDef;
#define GPIO_LSB 0x00
#define GPIO_MSB 0x08
/*******************************************************************************
* Function Name : GPIO_Config
* Description : Configure the GPIO port pins
* Input 1 : GPIOx (x can be 0,1 or 2) the desired port
* Input 2 : Port_Pins : pins placements
* Input 3 : Pins Mode
* Output : None
* Return : None
*******************************************************************************/
void GPIO_Config (GPIO_TypeDef *GPIOx, u16 Port_Pins, GpioPinMode_TypeDef GPIO_Mode);
/*******************************************************************************
* Function Name : GPIO_BitRead
* Description : Read the desired port pin value
* Input 1 : Selected GPIO port
* Input 2 : Pin number
* Output : None
* Return : The selected pin value
*******************************************************************************/
inline u8 GPIO_BitRead(GPIO_TypeDef *GPIOx, u8 Port_Pin)
{
return (GPIOx->PD >> Port_Pin) & 0x0001;
}
/*******************************************************************************
* Function Name : GPIO_ByteRead
* Description : Read the desired port Byte value
* Input 1 : Selected GPIO port
* Input 2 : GPIO_MSB or GPIO_LSB
* Output : None
* Return : The GPIO_MSB or GPIO_LSB of the selected PD register
*******************************************************************************/
inline u8 GPIO_ByteRead(GPIO_TypeDef *GPIOx, u8 Port_Byte)
{
return (u8)(GPIOx->PD >> Port_Byte);
}
/*******************************************************************************
* Function Name : GPIO_WordRead
* Description : Read the desired port word value
* Input 1 : Selected GPIO port
* Output : None
* Return : The selected PD register value
*******************************************************************************/
inline u16 GPIO_WordRead(GPIO_TypeDef *GPIOx)
{
return GPIOx->PD;
}
/*******************************************************************************
* Function Name : GPIO_BitWrite
* Description : Set or reset the selected port pin
* Input 1 : Selected GPIO port
* Input 2 : Pin number
* Input 3 : bit value
* Output : None
* Return : None
*******************************************************************************/
void GPIO_BitWrite(GPIO_TypeDef *GPIOx, u8 Port_Pin, u8 Port_Val);
/*******************************************************************************
* Function Name : GPIO_ByteWrite
* Description : Write byte value to the selected PD register
* Input 1 : Selected GPIO port
* Input 2 : GPIO_MSB or GPIO_LSB
* Input 3 : Byte value
* Output : None
* Return : None
*******************************************************************************/
void GPIO_ByteWrite(GPIO_TypeDef *GPIOx, u8 Port_Byte, u8 Port_Val);
/*******************************************************************************
* Function Name : GPIO_WordWrite
* Description : Write word value to the selected PD register
* Input 1 : Selected GPIO port
* Input 2 : Value
* Output : None
* Return : None
*******************************************************************************/
inline void GPIO_WordWrite(GPIO_TypeDef *GPIOx, u16 Port_Val)
{
GPIOx->PD = Port_Val;
}
#endif /* __gpio_H */
/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/

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/******************** (C) COPYRIGHT 2003 STMicroelectronics ********************
* File Name : pcu.h
* Author : MCD Application Team
* Date First Issued : 30/05/2003
* Description : This file contains all the functions prototypes for the
* PCU software library.
********************************************************************************
* History:
* 30/11/2004 : V2.0
* 14/07/2004 : V1.3
* 01/01/2004 : V1.2
*******************************************************************************
THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
#ifndef __PCU_H
#define __PCU_H
#include "71x_map.h"
typedef enum
{
PCU_WREN = 0x8000,
PCU_VROK = 0x1000
} PCU_Flags;
typedef enum
{
PCU_STABLE,
PCU_UNSTABLE
} PCU_VR_Status;
typedef enum
{
PCU_MVR = 0x0008,
PCU_LPR = 0x0020
} PCU_VR;
typedef enum
{
WFI_CLOCK2_16,
WFI_EXTERNAL
} WFI_CLOCKS;
typedef enum
{
PCU_SLOW,
PCU_STOP,
PCU_STANDBY
} LPM_MODES;
// VR_OK : Voltage Regulator OK
#define PCU_VROK_Mask 0x1000
// Main Voltage Regulator
#define PCU_MVR_Mask 0x0008
// Low Power Voltage Regulator
#define PCU_LPR_Mask 0x0020
// PCU register Write Enable Bit
#define PCU_WREN_Mask 0x8000
// Low Voltage Detector
#define PCU_LVD_Mask 0x0100
// Power Down Flag
#define PCU_PWRDWN_Mask 0x0040
// WFI Mode Clock Selection Bit
#define PCU_WFI_CKSEL_Mask 0x00000002
// Halt Mode Enable Bit
#define PCU_EN_HALT_Mask 0x00000800
// Halt Mode Flag
#define PCU_HALT_Mask 0x0002
// Stop Mode Enable Bit
#define PCU_STOP_EN_Mask 0x00000400
// Low Power Regulator in Wait For interrupt Mode
#define PCU_LPRWFI_Mask 0x0020
// Low Power Mode in Wait For interrupt Mode
#define PCU_LPOWFI_Mask 0x00000001
// Software Reset Enable
#define PCU_SRESEN_Mask 0x00000001
/*******************************************************************************
* Function Name : PCU_MVRStatus
* Description : This routine is used to check the Main Voltage Regulator
* : NewState.
* Input : None
* Return : STABLE, UNSTABLE
*******************************************************************************/
inline PCU_VR_Status PCU_MVRStatus ( void )
{
return (PCU->PWRCR & PCU_VROK_Mask) == 0x00 ? PCU_UNSTABLE : PCU_STABLE;
}
/*******************************************************************************
* Function Name : PCU_FlagStatus
* Description : This routine is used to return the PCU register flag
* Input 1 : The flag to get
* Return : RESET, SET
*******************************************************************************/
inline FlagStatus PCU_FlagStatus ( PCU_Flags Xflag )
{
return ( PCU->PWRCR & Xflag ) == 0x00 ? RESET : SET;
}
/*******************************************************************************
* Function Name : PCU_VRConfig
* Description : This routine is used to configure PCU voltage regultors
* Input 1 : MVR : Main voltage Regulator
LPR : Low Power Regulator
* Input 2 : ENABLE : Enable the Voltage Regulator
DISABLE: Disable ( ByPass ) the VR
* Return : None
*******************************************************************************/
void PCU_VRConfig ( PCU_VR xVR, FunctionalState NewState );
/*******************************************************************************
* Function Name : PCU_VRStatus
* Description : This routine is used to get the PCU voltage regultors status
* Input : MVR : Main voltage Regulator
LPR : Low Power Regulator
* Return : ENABLE : Enable the Voltage Regulator
DISABLE: Disable ( ByPass ) the VR
*******************************************************************************/
inline FunctionalState PCU_VRStatus ( PCU_VR xVR )
{
return ( PCU->PWRCR & xVR ) == 0 ? ENABLE : DISABLE;
}
/*******************************************************************************
* Function Name : PCU_LVDDisable
* Description : This routine is used to disable the Low Voltage Detector.
* Input : None
* Return : None
*******************************************************************************/
inline void PCU_LVDDisable ( void )
{
PCU->PWRCR |= PCU_WREN_Mask; // Unlock Power Control Register
PCU->PWRCR |= PCU_LVD_Mask; // Set the LVD DIS Flag
}
/*******************************************************************************
* Function Name : PCU_LVDStatus
* Description : This routine is used to get the LVD NewState.
* Input : None
* Return : ENABLE, DISABLE
*******************************************************************************/
inline FunctionalState PCU_LVDStatus ( void )
{
return ( PCU->PWRCR & PCU_LVD_Mask ) == 0 ? ENABLE : DISABLE;
}
/*******************************************************************************
* Function Name : PCU_WFIEnter
* Description : This routine is used to force the Device to enter in WFI mode
* Input 1 : CLOCK2_16 : Clock2_16 as system clock for WFI mode
* EXTERNAL : external clock as system clock for WFI mode
* Input 2 : ENABLE : Enable Low Power Regulator during Wait For Interrupt Mode
* DISABLE: Disable Low Power Regulator during Wait For Interrupt Mode
* Input 3 : ENABLE : Enable Low Power Mode during Wait For Interrupt Mode
* DISABLE: Disable Low Power Mode during Wait For Interrupt Mode
* Return : None
*******************************************************************************/
void PCU_WFIEnter ( WFI_CLOCKS Xclock, FunctionalState Xlpr, FunctionalState Xlpm );
/*******************************************************************************
* Function Name : PCU_LPMEnter
* Description : This routine is used to force the Device to enter low
* power mode
* Input : SLOW : Slow Mode
STOP : Stop Mode
HALT : Halt Mode
* Return : None
*******************************************************************************/
void PCU_LPMEnter ( LPM_MODES Xmode);
#endif // __PCU_H
/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/

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/******************** (C) COPYRIGHT 2003 STMicroelectronics ********************
* File Name : rccu.h
* Author : MCD Application Team
* Date First Issued : 28/07/2003
* Description : This file contains all the functions prototypes for the
* RCCU software library.
********************************************************************************
* History:
* 30/11/2004 : V2.0
* 14/07/2004 : V1.3
* 01/01/2004 : V1.2
*******************************************************************************
THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
#ifndef __RCCU_H
#define __RCCU_H
#include "71x_map.h"
typedef enum {
RCCU_DEFAULT=0x00,
RCCU_RCLK_2 =0x01,
RCCU_RCLK_4 =0x02,
RCCU_RCLK_8 =0x03
} RCCU_Clock_Div;
typedef enum {
RCCU_PLL1_Output,
RCCU_CLOCK2_16,
RCCU_CLOCK2,
RCCU_RTC_CLOCK
} RCCU_RCLK_Clocks;
typedef enum {
RCCU_PLL1_Mul_12=0x01,
RCCU_PLL1_Mul_16=0x03,
RCCU_PLL1_Mul_20=0x00,
RCCU_PLL1_Mul_24=0x02
} RCCU_PLL1_Mul;
typedef enum {
RCCU_PLL2_Mul_12=0x01,
RCCU_PLL2_Mul_16=0x03,
RCCU_PLL2_Mul_20=0x00,
RCCU_PLL2_Mul_28=0x02
} RCCU_PLL2_Mul;
typedef enum {
RCCU_Div_1=0x00,
RCCU_Div_2=0x01,
RCCU_Div_3=0x02,
RCCU_Div_4=0x03,
RCCU_Div_5=0x04,
RCCU_Div_6=0x05,
RCCU_Div_7=0x06
} RCCU_PLL_Div;
typedef enum {
RCCU_PLL2_Output = 0x01,
RCCU_USBCK = 0x00
} RCCU_USB_Clocks;
typedef enum {
RCCU_CLK2,
RCCU_RCLK,
RCCU_MCLK,
RCCU_PCLK,
RCCU_FCLK
} RCCU_Clocks;
typedef enum {
RCCU_PLL1_LOCK_IT = 0x0080,
RCCU_CKAF_IT = 0x0100,
RCCU_CK2_16_IT = 0x0200,
RCCU_STOP_IT = 0x0400
} RCCU_Interrupts;
typedef enum {
RCCU_PLL1_LOCK = 0x0002,
RCCU_CKAF_ST = 0x0004,
RCCU_PLL1_LOCK_I = 0x0800,
RCCU_CKAF_I = 0x1000,
RCCU_CK2_16_I = 0x2000,
RCCU_STOP_I = 0x4000
} RCCU_Flags;
typedef enum {
RCCU_ExternalReset = 0x00000000,
RCCU_SoftwareReset = 0x00000020,
RCCU_WDGReset = 0x00000040,
RCCU_RTCAlarmReset = 0x00000080,
RCCU_LVDReset = 0x00000200,
RCCU_WKPReset = 0x00000400
}RCCU_ResetSources;
#define RCCU_Div2_Mask 0x00008000
#define RCCU_Div2_Index 0x0F
#define RCCU_FACT_Mask 0x0003
#define RCCU_FACT1_Mask 0x0003
#define RCCU_FACT2_Mask 0x0300
#define RCCU_FACT2_Index 0x08
#define RCCU_MX_Mask 0x00000030
#define RCCU_MX_Index 0x04
#define RCCU_DX_Mask 0x00000007
#define RCCU_FREEN_Mask 0x00000080
#define RCCU_CSU_CKSEL_Mask 0x00000001
#define RCCU_CK2_16_Mask 0x00000008
#define RCCU_CKAF_SEL_Mask 0x00000004
#define RCCU_LOCK_Mask 0x00000002
#define RCCU_USBEN_Mask 0x0100
#define RCCU_USBEN_Index 0x08
#define RCCU_ResetSources_Mask 0x000006E0
// RTC Oscillator Frequency value = 32 768 Hz
#define RCCU_RTC_Osc 32768
/*******************************************************************************
* Function Name : RCCU_Div2Config
* Description : Enables/Disables the clock division by two
* Input : NewState : ENABLE or DISABLE
* Return : None
*******************************************************************************/
inline void RCCU_Div2Config ( FunctionalState NewState )
{
if (NewState == ENABLE) RCCU->CFR |= RCCU_Div2_Mask;
else RCCU->CFR &= ~RCCU_Div2_Mask;
}
/*******************************************************************************
* Function Name : RCCU_Div2Status
* Description : Gets the Div2 Flag status
* Input : None
* Input : FlagStatus
* Return : None
*******************************************************************************/
inline FlagStatus RCCU_Div2Status ( void )
{
return (RCCU->CFR & RCCU_Div2_Mask) == 0 ? RESET : SET;
}
/*******************************************************************************
* Function Name : RCCU_MCLKConfig
* Description : Selects the division factor for RCLK to obtain the
* MCLK clock for the CPU
* Input : New_Clock : RCCU_DEFAULT, RCCU_RCLK_2, RCCU_RCLK_4, RCCU_RCLK_8
* Return : None
*******************************************************************************/
inline void RCCU_MCLKConfig ( RCCU_Clock_Div New_Clock )
{
PCU->MDIVR = ( PCU->MDIVR & ~RCCU_FACT_Mask ) | New_Clock;
}
/*******************************************************************************
* Function Name : RCCU_FCLKConfig
* Description : Selects the division factor for RCLK to obtain the
* FCLK clock for the APB1 fast peripherals (PCLK1).
* Input : New_Clock : RCCU_DEFAULT, RCCU_RCLK_2,
* RCCU_RCLK_4, RCCU_RCLK_8
* Return : None
*******************************************************************************/
inline void RCCU_FCLKConfig ( RCCU_Clock_Div New_Clock )
{
PCU->PDIVR = ( PCU->PDIVR & ~RCCU_FACT1_Mask ) | New_Clock;
}
/*******************************************************************************
* Function Name : RCCU_PCLKConfig
* Description : Selects the division factor for RCLK to obtain the
* PCLK clock for the APB2 peripherals (PCLK2).
* Input : New_Clock : RCCU_DEFAULT, RCCU_RCLK_2,
* RCCU_RCLK_4, RCCU_RCLK_8
* Return : None
*******************************************************************************/
inline void RCCU_PCLKConfig ( RCCU_Clock_Div New_Clock )
{
PCU->PDIVR =(PCU->PDIVR & ~RCCU_FACT2_Mask)|(New_Clock << RCCU_FACT2_Index);
}
/*******************************************************************************
* Function Name : RCCU_PLL1Config
* Description : Configures the PLL1 div & mul factors.
* Input : New_Mul : RCCU_Mul_12, RCCU_Mul_16, RCCU_Mul_20, RCCU_Mul_28
* : New_Div : RCCU_Div_1, RCCU_Div_2, RCCU_Div_3,
* RCCU_Div_4, RCCU_Div_5, RCCU_Div_6, RCCU_Div_7
* Return : None
*******************************************************************************/
void RCCU_PLL1Config ( RCCU_PLL1_Mul New_Mul, RCCU_PLL_Div New_Div );
/*******************************************************************************
* Function Name : RCCU_PLL2Config
* Description : Configures the PLL2 div & mul factors.
* Input : New_Mul : RCCU_Mul_12, RCCU_Mul_16, RCCU_Mul_20, RCCU_Mul_28
* : New_Div : RCCU_Div_1, RCCU_Div_2, RCCU_Div_3, RCCU_Div_4,
* RCCU_Div_5, RCCU_Div_6, RCCU_Div_7
* Return : None
*******************************************************************************/
void RCCU_PLL2Config ( RCCU_PLL2_Mul New_Mul, RCCU_PLL_Div New_Div );
/*******************************************************************************
* Function Name : RCCU_RCLKSourceConfig
* Description : Selects the RCLK source clock
* Input : New_Clock : RCCU_PLL1_OutPut, RCCU_CLOCK2_16, RCCU_CLOCK2
* Return : None
*******************************************************************************/
void RCCU_RCLKSourceConfig ( RCCU_RCLK_Clocks New_Clock );
/*******************************************************************************
* Function Name : RCCU_RCLKClockSource
* Description : Returns the current RCLK source clock
* Input : None
* Return : RCCU_PLL1_Output, RCCU_CLOCK2_16, RCCU_CLOCK2
*******************************************************************************/
RCCU_RCLK_Clocks RCCU_RCLKClockSource ( void );
/*******************************************************************************
* Function Name : RCCU_USBCLKConfig
* Description : Selects the USB source clock
* Input : New_Clock : RCCU_PLL2_Output, RCCU_USBCK
* Return : None
*******************************************************************************/
inline void RCCU_USBCLKConfig ( RCCU_USB_Clocks New_Clock )
{
PCU->PLL2CR = (PCU->PLL2CR & ~RCCU_USBEN_Mask)|(New_Clock << RCCU_USBEN_Index);
}
/*******************************************************************************
* Function Name : RCCU_USBClockSource
* Description : Gets the USB source clock
* Input : None
* Return : RCCU_USB_Clocks
*******************************************************************************/
RCCU_USB_Clocks RCCU_USBClockSource ( void );
/*******************************************************************************
* Function Name : RCCU_FrequencyValue
* Description : Calculates & Returns any internal RCCU clock freuqency
* passed in parametres
* Input : RCCU_Clocks : RCCU_CLK2, RCCU_RCLK, RCCU_MCLK,
* RCCU_PCLK, RCCU_FCLK
* Return : u32
*******************************************************************************/
u32 RCCU_FrequencyValue ( RCCU_Clocks Internal_Clk );
/*******************************************************************************
* Function Name : RCCU_ITConfig
* Description : Configures the RCCU interrupts
* Input : RCCU interrupts : RCCU_CK2_16_IT, RCCU_CKAF_IT,
* RCCU_PLL1_LOCK_IT
* Return : None
*******************************************************************************/
inline void RCCU_ITConfig ( RCCU_Interrupts RCCU_IT, FunctionalState NewState)
{
if (NewState == ENABLE) RCCU->CCR |= RCCU_IT; else RCCU->CCR &= ~RCCU_IT;
}
/*******************************************************************************
* Function Name : RCCU_FlagStatus
* Description : Checks the RCCU clock flag register status
* Input : RCCU Flags : RCCU_CK2_16, RCCU_CKAF, RCCU_PLL1_LOCK
* Return : FlagStatus : SET or RESET
*******************************************************************************/
inline FlagStatus RCCU_FlagStatus ( RCCU_Flags RCCU_flag )
{
return (RCCU->CFR & RCCU_flag) == 0 ? RESET : SET;
}
/*******************************************************************************
* Function Name : RCCU_FlagClear
* Description : Clears a specified flag in the RCCU registers
* Input : RCCU Flags : RCCU_CK2_16, RCCU_CKAF, RCCU_PLL1_LOCK
* Return : None
*******************************************************************************/
inline void RCCU_FlagClear ( RCCU_Interrupts RCCU_IT )
{
RCCU->CFR |= RCCU_IT;
}
/*******************************************************************************
* Function Name : RCCU_ResetSources
* Description : Return the source of the system reset
* Input : None
* Return : The reset source
*******************************************************************************/
inline RCCU_ResetSources RCCU_ResetSource ()
{
switch(RCCU->CFR & RCCU_ResetSources_Mask)
{
case 0x00000020: return RCCU_SoftwareReset;
case 0x00000040: return RCCU_WDGReset;
case 0x00000080: return RCCU_RTCAlarmReset;
case 0x00000200: return RCCU_LVDReset;
case 0x00000400: return RCCU_WKPReset;
default : return RCCU_ExternalReset;
}
}
#endif // __RCCU_H
/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/

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/******************** (C) COPYRIGHT 2003 STMicroelectronics ********************
* File Name : tim.h
* Author : MCD Application Team
* Date First Issued : 08/09/2003
* Description : This file contains all the functions prototypes for the
* TIM software library.
********************************************************************************
* History:
* 30/11/2004 : V2.0
* 14/07/2004 : V1.3
* 01/01/2004 : V1.2
*******************************************************************************
THE PRESENT SOFTWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH
CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT
OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT
OF SUCH SOFTWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION
CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
*******************************************************************************/
#ifndef __TIM_H
#define __TIM_H
#include "71x_map.h"
typedef enum { TIM_EXTERNAL,
TIM_INTERNAL
} TIM_Clocks;
typedef enum { TIM_RISING,
TIM_FALLING
} TIM_Clock_Edges;
typedef enum { TIM_CHANNEL_A,
TIM_CHANNEL_B
} TIM_Channels;
typedef enum { TIM_WITH_IT,
TIM_WITHOUT_IT
} TIM_IT_Mode;
typedef enum { TIM_TIMING,
TIM_WAVE
} TIM_OC_Modes;
typedef enum { TIM_HIGH,
TIM_LOW
} TIM_Logic_Levels;
typedef enum { TIM_START,
TIM_STOP,
TIM_CLEAR
} TIM_CounterOperations;
typedef enum { TIM_ICFA = 0x8000,
TIM_OCFA = 0x4000,
TIM_TOF = 0x2000,
TIM_ICFB = 0x1000,
TIM_OCFB = 0x0800
} TIM_Flags;
typedef struct { u16 Pulse;
u16 Period;
} PWMI_parameters;
#define TIM_ECKEN_Mask 0x0001
#define TIM_EXEDG_Mask 0x0002
#define TIM_IEDGA_Mask 0x0004
#define TIM_IEDGB_Mask 0x0008
#define TIM_PWM_Mask 0x0010
#define TIM_OMP_Mask 0x0020
#define TIM_OCAE_Mask 0x0040
#define TIM_OCBE_Mask 0x0080
#define TIM_OLVLA_Mask 0x0100
#define TIM_OLVLB_Mask 0x0200
#define TIM_FOLVA_Mask 0x0400
#define TIM_FOLVB_Mask 0x0800
#define TIM_PWMI_Mask 0x4000
#define TIM_EN_Mask 0x8000
#define TIM_OCBIE_mask 0x0800
#define TIM_ICBIE_Mask 0x1000
#define TIM_TOE_Mask 0x2000
#define TIM_ICAIE_Mask 0x8000
#define TIM_OCAIE_mask 0x4000
#define TIM_ICA_IT 0x8000 // Input Capture Channel A
#define TIM_OCA_IT 0x4000 // Output Compare Channel A
#define TIM_TO_IT 0x2000 // Timer OverFlow
#define TIM_ICB_IT 0x1000 // Input Capture Channel B
#define TIM_OCB_IT 0x0800 // Input Capture Channel A
/*******************************************************************************
* Function Name : TIM_Init
* Description : This routine is used to Initialize the TIM peripheral
* Input : TIM Timer to Initialize
* Return : None
*******************************************************************************/
void TIM_Init( TIM_TypeDef *TIMx );
/*******************************************************************************
* Function Name : TIM_ClockSourceConfig
* Description : This routine is used to configure the TIM clock source
* Input : (1) TIM Timer
* : (2) TIM_Clocks : Specifies the TIM source clock
* - TIM_INTERNAL : The TIM is clocked by the APB2 frequency
* divided by the prescaler value.
* - TIM_EXTERNAL : The TIM is clocked by an external Clock
* Return : None
*******************************************************************************/
inline void TIM_ClockSourceConfig ( TIM_TypeDef *TIMx, TIM_Clocks Xclock )
{
if (Xclock==TIM_EXTERNAL) TIMx->CR1|=TIM_ECKEN_Mask; else TIMx->CR1&=~TIM_ECKEN_Mask;
}
/*******************************************************************************
* Function Name : TIM_ClockSourceValue
* Description : This routine is used to get the TIM clock source
* Input : TIM Timer
* Return : TIM_Clocks : Specifies the TIM source clock
* - TIM_INTERNAL : The TIM is clocked by the APB2 frequency
* divided by the prescaler value.
* - TIM_EXTERNAL : The TIM is clocked by an external Clock
*******************************************************************************/
inline TIM_Clocks TIM_ClockSourceValue ( TIM_TypeDef *TIMx )
{
return ( TIMx->CR1 & TIM_ECKEN_Mask) == 0 ? TIM_INTERNAL : TIM_EXTERNAL;
}
/*******************************************************************************
* Function Name : TIM_PrescalerConfig
* Description : This routine is used to configure the TIM prescaler value
* ( using an internal clock )
* Input : (1) TIM Timer
* : (2) Prescaler ( u8 )
* Return : None
*******************************************************************************/
inline void TIM_PrescalerConfig ( TIM_TypeDef *TIMx, u8 Xprescaler )
{
TIMx->CR2 = ( TIMx->CR2 & 0xFF00 ) | Xprescaler;
}
/*******************************************************************************
* Function Name : TIM_PrescalerValue
* Description : This routine is used to get the TIM prescaler value
* ( when using using an internal clock )
* Input : TIM Timer
* Return : Prescaler ( u8 )
*******************************************************************************/
inline u8 TIM_PrescalerValue ( TIM_TypeDef *TIMx )
{
return TIMx->CR2 & 0x00FF;
}
/*******************************************************************************
* Function Name : TIM_ClockLevelConfig
* Description : This routine is used to configure the TIM clock level
* ( using an external clock )
* Input : TIM Timer
* : TIM_Clock_Edges : Specifies the active adge of the external clock
* - TIM_RISING : The rising edge
* - TIM_FALLING : The falling edge
* Return : None
*******************************************************************************/
inline void TIM_ClockLevelConfig ( TIM_TypeDef *TIMx, TIM_Clock_Edges Xedge )
{
if (Xedge == TIM_RISING) TIMx->CR1 |= TIM_EXEDG_Mask; else TIMx->CR1 &= ~TIM_EXEDG_Mask;
}
/*******************************************************************************
* Function Name : TIM_ClockLevelValue
* Description : This routine is used to get the TIM clock level
* Input : TIM Timer
* Output : TIM_Clock_Edges : Specifies the active adge of the external clock
* - TIM_RISING : The rising edge
* - TIM_FALLING : The falling edge
*******************************************************************************/
inline TIM_Clock_Edges TIM_ClockLevelValue ( TIM_TypeDef *TIMx )
{
return ( TIMx->CR1 & TIM_EXEDG_Mask ) == 0 ? TIM_FALLING : TIM_RISING;
}
/*******************************************************************************
* Function Name : TIM_ICAPModeConfig
* Description : This routine is used to configure the input capture feature
* Input : (1) TIM Timer
* : (2) Input Capture Channel ( Channel_A or Channel_B )
* : (3) Active Edge : Rising edge or Falling edge.
* Output : None
*******************************************************************************/
void TIM_ICAPModeConfig ( TIM_TypeDef *TIMx,
TIM_Channels Xchannel,
TIM_Clock_Edges Xedge );
/*******************************************************************************
* Function Name : TIM_ICAPValue
* Description : This routine is used to get the Input Capture value
* Input : (1) TIM Timer
* : (2) Input Capture Channel ( Channel_A or Channel_B )
* Output : None
*******************************************************************************/
inline u16 TIM_ICAPValue ( TIM_TypeDef *TIMx, TIM_Channels Xchannel )
{
return Xchannel == TIM_CHANNEL_A ? TIMx->ICAR : TIMx->ICBR;
}
/*******************************************************************************
* Function Name : TIM_OCMPModeConfig
* Description : This routine is used to configure the output compare feature
* Input : (1) TIM Timer
* : (2) OCMP Channel ( Channel_A or Channel_B )
* : (3) Pulse Length
* : (4) OC_Mode : output wave, or only timing.
* : (5) Level : Rising edge or Falling edge after the ==
* Output : None
*******************************************************************************/
void TIM_OCMPModeConfig ( TIM_TypeDef *TIMx,
TIM_Channels Xchannel,
u16 XpulseLength,
TIM_OC_Modes Xmode,
TIM_Logic_Levels Xlevel );
/*******************************************************************************
* Function Name : TIM_OPModeConfig
* Description : This routine is used to configure the one pulse mode
* Input : (1) TIM Timer
* : (3) XpulseLength : Length of the pulse
* : (4) Level1 : Level during the pulse
* : (5) Level2 : Level after the pulse
* : (6) Activation Edge : High or Low on ICAP A
* Output : None
*******************************************************************************/
void TIM_OPModeConfig ( TIM_TypeDef *TIMx,
u16 XpulseLength,
TIM_Logic_Levels XLevel1,
TIM_Logic_Levels XLevel2,
TIM_Clock_Edges Xedge );
/*******************************************************************************
* Function Name : TIM_PWMOModeConfig
* Description : This routine is used to configure the PWM in output mode
* Input : (1) TIM Timer
* : (2) DutyCycle : u16
* : (3) Level 1 : During the Duty Cycle
* : (4) Level 2 : During the after the pulse
* : (5) Full period : u16
* Output : None
*******************************************************************************/
void TIM_PWMOModeConfig ( TIM_TypeDef *TIMx,
u16 XDutyCycle,
TIM_Logic_Levels XLevel1,
u16 XFullperiod,
TIM_Logic_Levels XLevel2
);
/*******************************************************************************
* Function Name : TIM_PWMInputConfig
* Description : This routine is used to configure the PWM in input mode
* Input : (1) TIM Timer
* : (2) First Activation Edge
* Output : None
*******************************************************************************/
void TIM_PWMIModeConfig ( TIM_TypeDef *TIMx, TIM_Clock_Edges Xedge );
/*******************************************************************************
* Function Name : TIM_PWMIValue
* Description : This routine is used to get the PWMI values
* Input : (1) TIM Timer
* Output : PWMI_parameters : - u16 Dyty cycle
- u16 Full period
*******************************************************************************/
PWMI_parameters TIM_PWMIValue (TIM_TypeDef *TIMx );
/*******************************************************************************
* Function Name : TIM_CounterConfig
* Description : This routine is used to start/stop and clear the selected
* timer counter
* Input : (1) TIM Timer
* : (2) TIM_CounterOperations
TIM_START Enables or resumes the counter
* TIM_STOP Stops the TIM counter
* TIM_CLEAR Set the TIM counter value to FFFCh
* Output : None
*******************************************************************************/
void TIM_CounterConfig ( TIM_TypeDef *TIMx, TIM_CounterOperations Xoperation );
/*******************************************************************************
* Function Name : TIM_ITConfig
* Description : This routine is used to configure the TIM IT
* Input : (1) TIM Timer
* : (2) TIM interrupt
* : (2) ENABLE / DISABLE
* Output : None
*******************************************************************************/
inline void TIM_ITConfig ( TIM_TypeDef *TIMx, u16 New_IT, FunctionalState NewState )
{
if (NewState == ENABLE) TIMx->CR2 |= New_IT; else TIMx->CR2 &= ~New_IT;
}
/*******************************************************************************
* Function Name : TIM_FlagStatus
* Description : This routine is used to check whether a Flag is Set.
* Input : (1) TIM Timer
* : (2) The TIM FLag
* Output : Flag NewState
*******************************************************************************/
inline FlagStatus TIM_FlagStatus ( TIM_TypeDef *TIMx, TIM_Flags Xflag )
{
return (TIMx->SR & Xflag) == 0 ? RESET : SET;
}
/*******************************************************************************
* Function Name : TIM_FlagClear
* Description : This routine is used to clear Flags.
* Input : (1) TIM Timer
* : (2) The TIM FLag
* Output : None
*******************************************************************************/
inline void TIM_FlagClear ( TIM_TypeDef *TIMx, TIM_Flags Xflag )
{
TIMx->SR &= ~Xflag;
}
/*******************************************************************************
* Function Name : TIM_CounterValue
* Description : This routine returns the timer counter value.
* Input : TIM Timer
* Output : The counter value
*******************************************************************************/
inline u16 TIM_CounterValue(TIM_TypeDef *TIMx)
{
return TIMx->CNTR;
}
#endif // __TIM_H
/******************* (C) COPYRIGHT 2003 STMicroelectronics *****END OF FILE****/

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