mirror of
https://github.com/FreeRTOS/FreeRTOS-Kernel.git
synced 2025-08-19 09:38:32 -04:00
First version under SVN is V4.0.1
This commit is contained in:
Richard Barry
parent
243393860c
commit
b6df57c7e3
918 changed files with 269038 additions and 0 deletions
337
Source/portable/GCC/MicroBlaze/port.c
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337
Source/portable/GCC/MicroBlaze/port.c
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@ -0,0 +1,337 @@
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/*
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FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.
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This file is part of the FreeRTOS distribution.
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FreeRTOS is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
|
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the Free Software Foundation; either version 2 of the License, or
|
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(at your option) any later version.
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FreeRTOS is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
|
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with FreeRTOS; if not, write to the Free Software
|
||||
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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||||
|
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A special exception to the GPL can be applied should you wish to distribute
|
||||
a combined work that includes FreeRTOS, without being obliged to provide
|
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the source code for any proprietary components. See the licensing section
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||||
of http://www.FreeRTOS.org for full details of how and when the exception
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||||
can be applied.
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***************************************************************************
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See http://www.FreeRTOS.org for documentation, latest information, license
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and contact details. Please ensure to read the configuration and relevant
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port sections of the online documentation.
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***************************************************************************
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*/
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/*-----------------------------------------------------------
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* Implementation of functions defined in portable.h for the MicroBlaze port.
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*----------------------------------------------------------*/
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/* Scheduler includes. */
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#include "FreeRTOS.h"
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#include "task.h"
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/* Standard includes. */
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#include <string.h>
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/* Hardware includes. */
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#include <xintc.h>
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#include <xintc_i.h>
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#include <xtmrctr.h>
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/* Tasks are started with interrupts enabled. */
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#define portINITIAL_MSR_STATE ( ( portSTACK_TYPE ) 0x02 )
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/* Tasks are started with a critical section nesting of 0 - however prior
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to the scheduler being commenced we don't want the critical nesting level
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to reach zero, so it is initialised to a high value. */
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#define portINITIAL_NESTING_VALUE ( 0xff )
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/* Our hardware setup only uses one counter. */
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#define portCOUNTER_0 0
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/* The stack used by the ISR is filled with a known value to assist in
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debugging. */
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#define portISR_STACK_FILL_VALUE 0x55555555
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/* Counts the nesting depth of calls to portENTER_CRITICAL(). Each task
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maintains it's own count, so this variable is saved as part of the task
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context. */
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volatile unsigned portBASE_TYPE uxCriticalNesting = portINITIAL_NESTING_VALUE;
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/* To limit the amount of stack required by each task, this port uses a
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separate stack for interrupts. */
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unsigned portLONG *pulISRStack;
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/*-----------------------------------------------------------*/
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/*
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* Sets up the periodic ISR used for the RTOS tick. This uses timer 0, but
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* could have alternatively used the watchdog timer or timer 1.
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*/
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static void prvSetupTimerInterrupt( void );
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/*-----------------------------------------------------------*/
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/*
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* Initialise the stack of a task to look exactly as if a call to
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* portSAVE_CONTEXT had been made.
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*
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* See the header file portable.h.
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*/
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portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters )
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{
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extern void *_SDA2_BASE_, *_SDA_BASE_;
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const unsigned portLONG ulR2 = ( unsigned portLONG ) &_SDA2_BASE_;
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const unsigned portLONG ulR13 = ( unsigned portLONG ) &_SDA_BASE_;
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/* Place a few bytes of known values on the bottom of the stack.
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This is essential for the Microblaze port and these lines must
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not be omitted. The parameter value will overwrite the
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0x22222222 value during the function prologue. */
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*pxTopOfStack = ( portSTACK_TYPE ) 0x11111111;
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pxTopOfStack--;
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*pxTopOfStack = ( portSTACK_TYPE ) 0x22222222;
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pxTopOfStack--;
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*pxTopOfStack = ( portSTACK_TYPE ) 0x33333333;
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pxTopOfStack--;
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/* First stack an initial value for the critical section nesting. This
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is initialised to zero as tasks are started with interrupts enabled. */
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*pxTopOfStack = ( portSTACK_TYPE ) 0x00; /* R0. */
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/* Place an initial value for all the general purpose registers. */
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pxTopOfStack--;
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*pxTopOfStack = ( portSTACK_TYPE ) ulR2; /* R2 - small data area. */
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pxTopOfStack--;
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*pxTopOfStack = ( portSTACK_TYPE ) 0x03; /* R3. */
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pxTopOfStack--;
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*pxTopOfStack = ( portSTACK_TYPE ) 0x04; /* R4. */
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pxTopOfStack--;
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*pxTopOfStack = ( portSTACK_TYPE ) pvParameters;/* R5 contains the function call parameters. */
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pxTopOfStack--;
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*pxTopOfStack = ( portSTACK_TYPE ) 0x06; /* R6. */
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pxTopOfStack--;
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*pxTopOfStack = ( portSTACK_TYPE ) 0x07; /* R7. */
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pxTopOfStack--;
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*pxTopOfStack = ( portSTACK_TYPE ) 0x08; /* R8. */
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pxTopOfStack--;
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*pxTopOfStack = ( portSTACK_TYPE ) 0x09; /* R9. */
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pxTopOfStack--;
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*pxTopOfStack = ( portSTACK_TYPE ) 0x0a; /* R10. */
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pxTopOfStack--;
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*pxTopOfStack = ( portSTACK_TYPE ) 0x0b; /* R11. */
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pxTopOfStack--;
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*pxTopOfStack = ( portSTACK_TYPE ) 0x0c; /* R12. */
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pxTopOfStack--;
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*pxTopOfStack = ( portSTACK_TYPE ) ulR13; /* R13 - small data read write area. */
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pxTopOfStack--;
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*pxTopOfStack = ( portSTACK_TYPE ) pxCode; /* R14. */
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pxTopOfStack--;
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*pxTopOfStack = ( portSTACK_TYPE ) 0x0f; /* R15. */
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pxTopOfStack--;
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*pxTopOfStack = ( portSTACK_TYPE ) 0x10; /* R16. */
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pxTopOfStack--;
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*pxTopOfStack = ( portSTACK_TYPE ) 0x11; /* R17. */
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pxTopOfStack--;
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*pxTopOfStack = ( portSTACK_TYPE ) 0x12; /* R18. */
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pxTopOfStack--;
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*pxTopOfStack = ( portSTACK_TYPE ) 0x13; /* R19. */
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pxTopOfStack--;
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*pxTopOfStack = ( portSTACK_TYPE ) 0x14; /* R20. */
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pxTopOfStack--;
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*pxTopOfStack = ( portSTACK_TYPE ) 0x15; /* R21. */
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pxTopOfStack--;
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*pxTopOfStack = ( portSTACK_TYPE ) 0x16; /* R22. */
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pxTopOfStack--;
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*pxTopOfStack = ( portSTACK_TYPE ) 0x17; /* R23. */
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pxTopOfStack--;
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*pxTopOfStack = ( portSTACK_TYPE ) 0x18; /* R24. */
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pxTopOfStack--;
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*pxTopOfStack = ( portSTACK_TYPE ) 0x19; /* R25. */
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pxTopOfStack--;
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*pxTopOfStack = ( portSTACK_TYPE ) 0x1a; /* R26. */
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pxTopOfStack--;
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*pxTopOfStack = ( portSTACK_TYPE ) 0x1b; /* R27. */
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pxTopOfStack--;
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*pxTopOfStack = ( portSTACK_TYPE ) 0x1c; /* R28. */
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pxTopOfStack--;
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*pxTopOfStack = ( portSTACK_TYPE ) 0x1d; /* R29. */
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pxTopOfStack--;
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*pxTopOfStack = ( portSTACK_TYPE ) 0x1e; /* R30. */
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pxTopOfStack--;
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/* The MSR is stacked between R30 and R31. */
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*pxTopOfStack = portINITIAL_MSR_STATE;
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pxTopOfStack--;
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*pxTopOfStack = ( portSTACK_TYPE ) 0x1f; /* R31. */
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pxTopOfStack--;
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/* Return a pointer to the top of the stack we have generated so this can
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be stored in the task control block for the task. */
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return pxTopOfStack;
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}
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/*-----------------------------------------------------------*/
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portBASE_TYPE xPortStartScheduler( void )
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{
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extern void ( __FreeRTOS_interrupt_Handler )( void );
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extern void ( vStartFirstTask )( void );
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/* Setup the FreeRTOS interrupt handler. Code copied from crt0.s. */
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asm volatile ( "la r6, r0, __FreeRTOS_interrupt_handler \n\t" \
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"sw r6, r1, r0 \n\t" \
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"lhu r7, r1, r0 \n\t" \
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"shi r7, r0, 0x12 \n\t" \
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"shi r6, r0, 0x16 " );
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/* Setup the hardware to generate the tick. Interrupts are disabled when
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this function is called. */
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prvSetupTimerInterrupt();
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/* Allocate the stack to be used by the interrupt handler. */
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pulISRStack = ( unsigned portLONG * ) pvPortMalloc( configMINIMAL_STACK_SIZE * sizeof( portSTACK_TYPE ) );
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/* Restore the context of the first task that is going to run. */
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if( pulISRStack != NULL )
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{
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/* Fill the ISR stack with a known value to facilitate debugging. */
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memset( pulISRStack, portISR_STACK_FILL_VALUE, configMINIMAL_STACK_SIZE * sizeof( portSTACK_TYPE ) );
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pulISRStack += ( configMINIMAL_STACK_SIZE - 1 );
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/* Kick off the first task. */
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vStartFirstTask();
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}
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/* Should not get here as the tasks are now running! */
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return pdFALSE;
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}
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/*-----------------------------------------------------------*/
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void vPortEndScheduler( void )
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{
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/* Not implemented. */
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}
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/*-----------------------------------------------------------*/
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/*
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* Manual context switch called by portYIELD or taskYIELD.
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*/
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void vPortYield( void )
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{
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extern void VPortYieldASM( void );
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/* Perform the context switch in a critical section to assure it is
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not interrupted by the tick ISR. It is not a problem to do this as
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each task maintains it's own interrupt status. */
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portENTER_CRITICAL();
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/* Jump directly to the yield function to ensure there is no
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compiler generated prologue code. */
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asm volatile ( "bralid r14, VPortYieldASM \n\t" \
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"or r0, r0, r0 \n\t" );
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portEXIT_CRITICAL();
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}
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/*-----------------------------------------------------------*/
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/*
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* Hardware initialisation to generate the RTOS tick.
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*/
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static void prvSetupTimerInterrupt( void )
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{
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XTmrCtr xTimer;
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const unsigned portLONG ulCounterValue = configCPU_CLOCK_HZ / configTICK_RATE_HZ;
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unsigned portBASE_TYPE uxMask;
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/* The OPB timer1 is used to generate the tick. Use the provided library
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functions to enable the timer and set the tick frequency. */
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XTmrCtr_mDisable( XPAR_OPB_TIMER_1_BASEADDR, XPAR_OPB_TIMER_1_DEVICE_ID );
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XTmrCtr_Initialize( &xTimer, XPAR_OPB_TIMER_1_DEVICE_ID );
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XTmrCtr_mSetLoadReg( XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, ulCounterValue );
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XTmrCtr_mSetControlStatusReg( XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, XTC_CSR_LOAD_MASK | XTC_CSR_INT_OCCURED_MASK );
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/* Set the timer interrupt enable bit while maintaining the other bit
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states. */
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uxMask = XIntc_In32( ( XPAR_OPB_INTC_0_BASEADDR + XIN_IER_OFFSET ) );
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uxMask |= XPAR_OPB_TIMER_1_INTERRUPT_MASK;
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XIntc_Out32( ( XPAR_OPB_INTC_0_BASEADDR + XIN_IER_OFFSET ), ( uxMask ) );
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XTmrCtr_Start( &xTimer, XPAR_OPB_TIMER_1_DEVICE_ID );
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XTmrCtr_mSetControlStatusReg(XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, XTC_CSR_ENABLE_TMR_MASK | XTC_CSR_ENABLE_INT_MASK | XTC_CSR_AUTO_RELOAD_MASK | XTC_CSR_DOWN_COUNT_MASK | XTC_CSR_INT_OCCURED_MASK );
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XIntc_mAckIntr( XPAR_INTC_SINGLE_BASEADDR, 1 );
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}
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/*-----------------------------------------------------------*/
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/*
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* The interrupt handler placed in the interrupt vector when the scheduler is
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* started. The task context has already been saved when this is called.
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* This handler determines the interrupt source and calls the relevant
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* peripheral handler.
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*/
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void vTaskISRHandler( void )
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{
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static unsigned portLONG ulPending;
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/* Which interrupts are pending? */
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ulPending = XIntc_In32( ( XPAR_INTC_SINGLE_BASEADDR + XIN_IVR_OFFSET ) );
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if( ulPending < XPAR_INTC_MAX_NUM_INTR_INPUTS )
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{
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static XIntc_VectorTableEntry *pxTablePtr;
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static XIntc_Config *pxConfig;
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static unsigned portLONG ulInterruptMask;
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ulInterruptMask = ( unsigned portLONG ) 1 << ulPending;
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/* Get the configuration data using the device ID */
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pxConfig = &XIntc_ConfigTable[ ( unsigned portLONG ) XPAR_INTC_SINGLE_DEVICE_ID ];
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pxTablePtr = &( pxConfig->HandlerTable[ ulPending ] );
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if( pxConfig->AckBeforeService & ( ulInterruptMask ) )
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{
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XIntc_mAckIntr( pxConfig->BaseAddress, ulInterruptMask );
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pxTablePtr->Handler( pxTablePtr->CallBackRef );
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}
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else
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{
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pxTablePtr->Handler( pxTablePtr->CallBackRef );
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XIntc_mAckIntr( pxConfig->BaseAddress, ulInterruptMask );
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}
|
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}
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}
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/*-----------------------------------------------------------*/
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/*
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* Handler for the timer interrupt.
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*/
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void vTickISR( void *pvBaseAddress )
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{
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unsigned portLONG ulCSR;
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/* Increment the RTOS tick - this might cause a task to unblock. */
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vTaskIncrementTick();
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/* Clear the timer interrupt */
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ulCSR = XTmrCtr_mGetControlStatusReg(XPAR_OPB_TIMER_1_BASEADDR, 0);
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XTmrCtr_mSetControlStatusReg( XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, ulCSR );
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/* If we are using the preemptive scheduler then we also need to determine
|
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if this tick should cause a context switch. */
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#if configUSE_PREEMPTION == 1
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vTaskSwitchContext();
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#endif
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}
|
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/*-----------------------------------------------------------*/
|
||||
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|
||||
|
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171
Source/portable/GCC/MicroBlaze/portasm.s
Normal file
171
Source/portable/GCC/MicroBlaze/portasm.s
Normal file
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@ -0,0 +1,171 @@
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.extern pxCurrentTCB
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.extern vTaskISRHandler
|
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.extern vTaskSwitchContext
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.extern uxCriticalNesting
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.extern pulISRStack
|
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|
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.global __FreeRTOS_interrupt_handler
|
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.global VPortYieldASM
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.global vStartFirstTask
|
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|
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.macro portSAVE_CONTEXT
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/* Make room for the context on the stack. */
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addik r1, r1, -132
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/* Save r31 so it can then be used. */
|
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swi r31, r1, 4
|
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/* Copy the msr into r31 - this is stacked later. */
|
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mfs r31, rmsr
|
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/* Stack general registers. */
|
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swi r30, r1, 12
|
||||
swi r29, r1, 16
|
||||
swi r28, r1, 20
|
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swi r27, r1, 24
|
||||
swi r26, r1, 28
|
||||
swi r25, r1, 32
|
||||
swi r24, r1, 36
|
||||
swi r23, r1, 40
|
||||
swi r22, r1, 44
|
||||
swi r21, r1, 48
|
||||
swi r20, r1, 52
|
||||
swi r19, r1, 56
|
||||
swi r18, r1, 60
|
||||
swi r17, r1, 64
|
||||
swi r16, r1, 68
|
||||
swi r15, r1, 72
|
||||
swi r13, r1, 80
|
||||
swi r12, r1, 84
|
||||
swi r11, r1, 88
|
||||
swi r10, r1, 92
|
||||
swi r9, r1, 96
|
||||
swi r8, r1, 100
|
||||
swi r7, r1, 104
|
||||
swi r6, r1, 108
|
||||
swi r5, r1, 112
|
||||
swi r4, r1, 116
|
||||
swi r3, r1, 120
|
||||
swi r2, r1, 124
|
||||
/* Stack the critical section nesting value. */
|
||||
lwi r3, r0, uxCriticalNesting
|
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swi r3, r1, 128
|
||||
/* Save the top of stack value to the TCB. */
|
||||
lwi r3, r0, pxCurrentTCB
|
||||
sw r1, r0, r3
|
||||
|
||||
.endm
|
||||
|
||||
.macro portRESTORE_CONTEXT
|
||||
/* Load the top of stack value from the TCB. */
|
||||
lwi r3, r0, pxCurrentTCB
|
||||
lw r1, r0, r3
|
||||
/* Restore the general registers. */
|
||||
lwi r31, r1, 4
|
||||
lwi r30, r1, 12
|
||||
lwi r29, r1, 16
|
||||
lwi r28, r1, 20
|
||||
lwi r27, r1, 24
|
||||
lwi r26, r1, 28
|
||||
lwi r25, r1, 32
|
||||
lwi r24, r1, 36
|
||||
lwi r23, r1, 40
|
||||
lwi r22, r1, 44
|
||||
lwi r21, r1, 48
|
||||
lwi r20, r1, 52
|
||||
lwi r19, r1, 56
|
||||
lwi r18, r1, 60
|
||||
lwi r17, r1, 64
|
||||
lwi r16, r1, 68
|
||||
lwi r15, r1, 72
|
||||
lwi r14, r1, 76
|
||||
lwi r13, r1, 80
|
||||
lwi r12, r1, 84
|
||||
lwi r11, r1, 88
|
||||
lwi r10, r1, 92
|
||||
lwi r9, r1, 96
|
||||
lwi r8, r1, 100
|
||||
lwi r7, r1, 104
|
||||
lwi r6, r1, 108
|
||||
lwi r5, r1, 112
|
||||
lwi r4, r1, 116
|
||||
lwi r2, r1, 124
|
||||
|
||||
/* Load the critical nesting value. */
|
||||
lwi r3, r1, 128
|
||||
swi r3, r0, uxCriticalNesting
|
||||
|
||||
/* Obtain the MSR value from the stack. */
|
||||
lwi r3, r1, 8
|
||||
|
||||
/* Are interrupts enabled in the MSR? If so return using an return from
|
||||
interrupt instruction to ensure interrupts are enabled only once the task
|
||||
is running again. */
|
||||
andi r3, r3, 2
|
||||
beqid r3, 36
|
||||
or r0, r0, r0
|
||||
|
||||
/* Reload the rmsr from the stack, clear the enable interrupt bit in the
|
||||
value before saving back to rmsr register, then return enabling interrupts
|
||||
as we return. */
|
||||
lwi r3, r1, 8
|
||||
andi r3, r3, ~2
|
||||
mts rmsr, r3
|
||||
lwi r3, r1, 120
|
||||
addik r1, r1, 132
|
||||
rtid r14, 0
|
||||
or r0, r0, r0
|
||||
|
||||
/* Reload the rmsr from the stack, place it in the rmsr register, and
|
||||
return without enabling interrupts. */
|
||||
lwi r3, r1, 8
|
||||
mts rmsr, r3
|
||||
lwi r3, r1, 120
|
||||
addik r1, r1, 132
|
||||
rtsd r14, 0
|
||||
or r0, r0, r0
|
||||
|
||||
.endm
|
||||
|
||||
.text
|
||||
.align 2
|
||||
|
||||
|
||||
__FreeRTOS_interrupt_handler:
|
||||
portSAVE_CONTEXT
|
||||
/* Entered via an interrupt so interrupts must be enabled in msr. */
|
||||
ori r31, r31, 2
|
||||
/* Stack msr. */
|
||||
swi r31, r1, 8
|
||||
/* Stack the return address. As we entered via an interrupt we do
|
||||
not need to modify the return address prior to stacking. */
|
||||
swi r14, r1, 76
|
||||
/* Now switch to use the ISR stack. */
|
||||
lwi r3, r0, pulISRStack
|
||||
add r1, r3, r0
|
||||
bralid r15, vTaskISRHandler
|
||||
or r0, r0, r0
|
||||
portRESTORE_CONTEXT
|
||||
|
||||
|
||||
VPortYieldASM:
|
||||
portSAVE_CONTEXT
|
||||
/* Stack msr. */
|
||||
swi r31, r1, 8
|
||||
/* Modify the return address so we return to the instruction after the
|
||||
exception. */
|
||||
addi r14, r14, 8
|
||||
swi r14, r1, 76
|
||||
/* Now switch to use the ISR stack. */
|
||||
lwi r3, r0, pulISRStack
|
||||
add r1, r3, r0
|
||||
bralid r15, vTaskSwitchContext
|
||||
or r0, r0, r0
|
||||
portRESTORE_CONTEXT
|
||||
|
||||
vStartFirstTask:
|
||||
portRESTORE_CONTEXT
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
115
Source/portable/GCC/MicroBlaze/portmacro.h
Normal file
115
Source/portable/GCC/MicroBlaze/portmacro.h
Normal file
|
|
@ -0,0 +1,115 @@
|
|||
/*
|
||||
FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.
|
||||
|
||||
This file is part of the FreeRTOS distribution.
|
||||
|
||||
FreeRTOS is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
FreeRTOS is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with FreeRTOS; if not, write to the Free Software
|
||||
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
|
||||
A special exception to the GPL can be applied should you wish to distribute
|
||||
a combined work that includes FreeRTOS, without being obliged to provide
|
||||
the source code for any proprietary components. See the licensing section
|
||||
of http://www.FreeRTOS.org for full details of how and when the exception
|
||||
can be applied.
|
||||
|
||||
***************************************************************************
|
||||
See http://www.FreeRTOS.org for documentation, latest information, license
|
||||
and contact details. Please ensure to read the configuration and relevant
|
||||
port sections of the online documentation.
|
||||
***************************************************************************
|
||||
*/
|
||||
|
||||
#ifndef PORTMACRO_H
|
||||
#define PORTMACRO_H
|
||||
|
||||
/*-----------------------------------------------------------
|
||||
* Port specific definitions.
|
||||
*
|
||||
* The settings in this file configure FreeRTOS correctly for the
|
||||
* given hardware and compiler.
|
||||
*
|
||||
* These settings should not be altered.
|
||||
*-----------------------------------------------------------
|
||||
*/
|
||||
|
||||
/* Type definitions. */
|
||||
#define portCHAR char
|
||||
#define portFLOAT float
|
||||
#define portDOUBLE double
|
||||
#define portLONG long
|
||||
#define portSHORT short
|
||||
#define portSTACK_TYPE unsigned portLONG
|
||||
#define portBASE_TYPE portLONG
|
||||
|
||||
#if( configUSE_16_BIT_TICKS == 1 )
|
||||
typedef unsigned portSHORT portTickType;
|
||||
#define portMAX_DELAY ( portTickType ) 0xffff
|
||||
#else
|
||||
typedef unsigned portLONG portTickType;
|
||||
#define portMAX_DELAY ( portTickType ) 0xffffffff
|
||||
#endif
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Interrupt control macros. */
|
||||
void microblaze_disable_interrupts( void );
|
||||
void microblaze_enable_interrupts( void );
|
||||
#define portDISABLE_INTERRUPTS() microblaze_disable_interrupts()
|
||||
#define portENABLE_INTERRUPTS() microblaze_enable_interrupts()
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Critical section macros. */
|
||||
void vPortEnterCritical( void );
|
||||
void vPortExitCritical( void );
|
||||
#define portENTER_CRITICAL() { \
|
||||
extern unsigned portBASE_TYPE uxCriticalNesting; \
|
||||
microblaze_disable_interrupts(); \
|
||||
uxCriticalNesting++; \
|
||||
}
|
||||
|
||||
#define portEXIT_CRITICAL() { \
|
||||
extern unsigned portBASE_TYPE uxCriticalNesting; \
|
||||
/* Interrupts are disabled, so we can */ \
|
||||
/* access the variable directly. */ \
|
||||
uxCriticalNesting--; \
|
||||
if( uxCriticalNesting == 0 ) \
|
||||
{ \
|
||||
/* The nesting has unwound and we \
|
||||
can enable interrupts again. */ \
|
||||
portENABLE_INTERRUPTS(); \
|
||||
} \
|
||||
}
|
||||
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Task utilities. */
|
||||
void vPortYield( void );
|
||||
#define portYIELD() vPortYield()
|
||||
|
||||
void vTaskSwitchContext();
|
||||
#define portYIELD_FROM_ISR() vTaskSwitchContext()
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Hardware specifics. */
|
||||
#define portBYTE_ALIGNMENT 4
|
||||
#define portSTACK_GROWTH ( -1 )
|
||||
#define portTICK_RATE_MS ( ( portTickType ) 1000 / configTICK_RATE_HZ )
|
||||
#define portNOP() asm volatile ( "NOP" )
|
||||
/*-----------------------------------------------------------*/
|
||||
|
||||
/* Task function macros as described on the FreeRTOS.org WEB site. */
|
||||
#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
|
||||
#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
|
||||
|
||||
#endif /* PORTMACRO_H */
|
||||
|
||||
Loading…
Add table
Add a link
Reference in a new issue