mirror of
https://github.com/FreeRTOS/FreeRTOS-Kernel.git
synced 2026-01-16 23:00:34 -05:00
First version under SVN is V4.0.1
This commit is contained in:
Richard Barry
parent
243393860c
commit
b6df57c7e3
918 changed files with 269038 additions and 0 deletions
194
Demo/uIP_Demo_IAR_ARM7/resource/SAM7.mac
Normal file
194
Demo/uIP_Demo_IAR_ARM7/resource/SAM7.mac
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@ -0,0 +1,194 @@
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// ---------------------------------------------------------
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// Microcontroller Software Support - ROUSSET -
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// ---------------------------------------------------------
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// The software is delivered "AS IS" without warranty or
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// condition of any kind, either express, implied or
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// statutory. This includes without limitation any warranty
|
||||
// or condition with respect to merchantability or fitness
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// for any particular purpose, or against the infringements of
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// intellectual property rights of others.
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// ---------------------------------------------------------
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// File: SAM7.mac
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//
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// 1.0 08/Mar/04 JPP : Creation
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// 1.1 23/Mar/05 JPP : Change Variable name
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//
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// $Revision: 1.5 $
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//
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// ---------------------------------------------------------
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__var __mac_i;
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__var __mac_pt;
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execUserReset()
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{
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AIC();
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//* Watchdog Disable
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Watchdog();
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}
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execUserPreload()
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{
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//* Set the RAM memory at 0x0020 0000 for code AT 0 flash area
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CheckRemap();
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//* Get the Chip ID (AT91C_DBGU_C1R & AT91C_DBGU_C2R
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__mac_i =__readMemory32(0xFFFFF240,"Memory");
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__message " ---------------------------------------- Chip ID 0x",__mac_i:%X;
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__mac_i =__readMemory32(0xFFFFF244,"Memory");
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__message " ---------------------------------------- Extention 0x",__mac_i:%X;
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//* Get the chip status
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//* Init AIC
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AIC();
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//* Watchdog Disable
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Watchdog();
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}
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//-----------------------------------------------------------------------------
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// Watchdog
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//-------------------------------
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// Normally, the Watchdog is enable at the reset for load it's preferable to
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// Disable.
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//-----------------------------------------------------------------------------
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Watchdog()
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{
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//* Watchdog Disable
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// AT91C_BASE_WDTC->WDTC_WDMR= AT91C_WDTC_WDDIS;
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__writeMemory32(0x00008000,0xFFFFFD44,"Memory");
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__message "------------------------------- Watchdog Disable ----------------------------------------";
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}
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//-----------------------------------------------------------------------------
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// Check Remap
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//-------------
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//-----------------------------------------------------------------------------
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CheckRemap()
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{
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//* Read the value at 0x0
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__mac_i =__readMemory32(0x00000000,"Memory");
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__mac_i =__mac_i+1;
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__writeMemory32(__mac_i,0x00,"Memory");
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__mac_pt =__readMemory32(0x00000000,"Memory");
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if (__mac_i == __mac_pt)
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{
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__message "------------------------------- The Remap is done ----------------------------------------";
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//* Toggel RESET The remap
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__writeMemory32(0x00000001,0xFFFFFF00,"Memory");
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} else {
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__message "------------------------------- The Remap is NOT -----------------------------------------";
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}
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}
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execUserSetup()
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{
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ini();
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__message "-------------------------------Set PC ----------------------------------------";
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__writeMemory32(0x00000000,0xB4,"Register");
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}
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//-----------------------------------------------------------------------------
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// Reset the Interrupt Controller
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//-------------------------------
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// Normally, the code is executed only if a reset has been actually performed.
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// So, the AIC initialization resumes at setting up the default vectors.
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//-----------------------------------------------------------------------------
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AIC()
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{
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// Mask All interrupt pAic->AIC_IDCR = 0xFFFFFFFF;
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__writeMemory32(0xffffffff,0xFFFFF124,"Memory");
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__writeMemory32(0xffffffff,0xFFFFF128,"Memory");
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// disable peripheral clock Peripheral Clock Disable Register
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__writeMemory32(0xffffffff,0xFFFFFC14,"Memory");
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// #define AT91C_TC0_SR ((AT91_REG *) 0xFFFA0020) // (TC0) Status Register
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// #define AT91C_TC1_SR ((AT91_REG *) 0xFFFA0060) // (TC1) Status Register
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// #define AT91C_TC2_SR ((AT91_REG *) 0xFFFA00A0) // (TC2) Status Register
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__readMemory32(0xFFFA0020,"Memory");
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__readMemory32(0xFFFA0060,"Memory");
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__readMemory32(0xFFFA00A0,"Memory");
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for (__mac_i=0;__mac_i < 8; __mac_i++)
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{
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// AT91C_BASE_AIC->AIC_EOICR
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__mac_pt = __readMemory32(0xFFFFF130,"Memory");
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}
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__message "------------------------------- AIC 2 INIT ---------------------------------------------";
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}
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ini()
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{
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__writeMemory32(0x0,0x00,"Register");
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__writeMemory32(0x0,0x04,"Register");
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__writeMemory32(0x0,0x08,"Register");
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__writeMemory32(0x0,0x0C,"Register");
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__writeMemory32(0x0,0x10,"Register");
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__writeMemory32(0x0,0x14,"Register");
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__writeMemory32(0x0,0x18,"Register");
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__writeMemory32(0x0,0x1C,"Register");
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__writeMemory32(0x0,0x20,"Register");
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__writeMemory32(0x0,0x24,"Register");
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__writeMemory32(0x0,0x28,"Register");
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__writeMemory32(0x0,0x2C,"Register");
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__writeMemory32(0x0,0x30,"Register");
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__writeMemory32(0x0,0x34,"Register");
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__writeMemory32(0x0,0x38,"Register");
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// Set CPSR
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__writeMemory32(0x0D3,0x98,"Register");
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}
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RG()
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{
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__mac_i =__readMemory32(0x00,"Register"); __message "R00 0x",__mac_i:%X;
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__mac_i =__readMemory32(0x04,"Register"); __message "R01 0x",__mac_i:%X;
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__mac_i =__readMemory32(0x08,"Register"); __message "R02 0x",__mac_i:%X;
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__mac_i =__readMemory32(0x0C,"Register"); __message "R03 0x",__mac_i:%X;
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__mac_i =__readMemory32(0x10,"Register"); __message "R04 0x",__mac_i:%X;
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__mac_i =__readMemory32(0x14,"Register"); __message "R05 0x",__mac_i:%X;
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__mac_i =__readMemory32(0x18,"Register"); __message "R06 0x",__mac_i:%X;
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__mac_i =__readMemory32(0x1C,"Register"); __message "R07 0x",__mac_i:%X;
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__mac_i =__readMemory32(0x20,"Register"); __message "R08 0x",__mac_i:%X;
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__mac_i =__readMemory32(0x24,"Register"); __message "R09 0x",__mac_i:%X;
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__mac_i =__readMemory32(0x28,"Register"); __message "R10 0x",__mac_i:%X;
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__mac_i =__readMemory32(0x2C,"Register"); __message "R11 0x",__mac_i:%X;
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__mac_i =__readMemory32(0x30,"Register"); __message "R12 0x",__mac_i:%X;
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__mac_i =__readMemory32(0x34,"Register"); __message "R13 0x",__mac_i:%X;
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__mac_i =__readMemory32(0x38,"Register"); __message "R14 0x",__mac_i:%X;
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__mac_i =__readMemory32(0x3C,"Register"); __message "R13 SVC 0x",__mac_i:%X;
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__mac_i =__readMemory32(0x40,"Register"); __message "R14 SVC 0x",__mac_i:%X;
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__mac_i =__readMemory32(0x44,"Register"); __message "R13 ABT 0x",__mac_i:%X;
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__mac_i =__readMemory32(0x48,"Register"); __message "R14 ABT 0x",__mac_i:%X;
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__mac_i =__readMemory32(0x4C,"Register"); __message "R13 UND 0x",__mac_i:%X;
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__mac_i =__readMemory32(0x50,"Register"); __message "R14 UND 0x",__mac_i:%X;
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__mac_i =__readMemory32(0x54,"Register"); __message "R13 IRQ 0x",__mac_i:%X;
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__mac_i =__readMemory32(0x58,"Register"); __message "R14 IRQ 0x",__mac_i:%X;
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__mac_i =__readMemory32(0x5C,"Register"); __message "R08 FIQ 0x",__mac_i:%X;
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__mac_i =__readMemory32(0x60,"Register"); __message "R09 FIQ 0x",__mac_i:%X;
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__mac_i =__readMemory32(0x64,"Register"); __message "R10 FIQ 0x",__mac_i:%X;
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__mac_i =__readMemory32(0x68,"Register"); __message "R11 FIQ 0x",__mac_i:%X;
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__mac_i =__readMemory32(0x6C,"Register"); __message "R12 FIQ 0x",__mac_i:%X;
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__mac_i =__readMemory32(0x70,"Register"); __message "R13 FIQ 0x",__mac_i:%X;
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__mac_i =__readMemory32(0x74,"Register"); __message "R14 FIQ0x",__mac_i:%X;
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__mac_i =__readMemory32(0x98,"Register"); __message "CPSR ",__mac_i:%X;
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__mac_i =__readMemory32(0x94,"Register"); __message "SPSR ",__mac_i:%X;
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__mac_i =__readMemory32(0x9C,"Register"); __message "SPSR ABT ",__mac_i:%X;
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__mac_i =__readMemory32(0xA0,"Register"); __message "SPSR ABT ",__mac_i:%X;
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__mac_i =__readMemory32(0xA4,"Register"); __message "SPSR UND ",__mac_i:%X;
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__mac_i =__readMemory32(0xA8,"Register"); __message "SPSR IRQ ",__mac_i:%X;
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__mac_i =__readMemory32(0xAC,"Register"); __message "SPSR FIQ ",__mac_i:%X;
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__mac_i =__readMemory32(0xB4,"Register"); __message "PC 0x",__mac_i:%X;
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}
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227
Demo/uIP_Demo_IAR_ARM7/resource/SAM7_RAM.mac
Normal file
227
Demo/uIP_Demo_IAR_ARM7/resource/SAM7_RAM.mac
Normal file
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@ -0,0 +1,227 @@
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// ---------------------------------------------------------
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// ATMEL Microcontroller Software Support - ROUSSET -
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// ---------------------------------------------------------
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// The software is delivered "AS IS" without warranty or
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// condition of any kind, either express, implied or
|
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// statutory. This includes without limitation any warranty
|
||||
// or condition with respect to merchantability or fitness
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// for any particular purpose, or against the infringements of
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// intellectual property rights of others.
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// ---------------------------------------------------------
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// File: SAM7_RAM.mac
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//
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// 1.0 08/Mar/05 JPP : Creation
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// 1.1 23/Mar/05 JPP : Change Variable name
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//
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// $Revision: 1.6 $
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//
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// ---------------------------------------------------------
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__var __mac_i;
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__var __mac_pt;
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__var __mac_mem;
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execUserReset()
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{
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CheckNoRemap();
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ini();
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AIC();
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__message "-------------------------------Set PC Reset ----------------------------------";
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__writeMemory32(0x00000000,0xB4,"Register");
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}
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execUserPreload()
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{
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//* __message "-------------------------------Set CPSR ----------------------------------";
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__writeMemory32(0xD3,0x98,"Register");
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__writeMemory32(0xffffffff,0xFFFFFC14,"Memory");
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PllSetting();
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//* Init AIC
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AIC();
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//* Set the RAM memory at 0x0020 0000 for code AT 0 flash area
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CheckNoRemap();
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//* Get the Chip ID (AT91C_DBGU_C1R & AT91C_DBGU_C2R
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__mac_i=__readMemory32(0xFFFFF240,"Memory");
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__message " ---------------------------------------- Chip ID 0x",__mac_i:%X;
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__mac_i=__readMemory32(0xFFFFF244,"Memory");
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__message " ---------------------------------------- Extention 0x",__mac_i:%X;
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__mac_i=__readMemory32(0xFFFFFF6C,"Memory");
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__message " ---------------------------------------- Flash Version 0x",__mac_i:%X;
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//* Watchdog Disable
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Watchdog();
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//* RG();
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}
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//-----------------------------------------------------------------------------
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// PllSetting
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//-------------------------------
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// Set PLL
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//-----------------------------------------------------------------------------
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PllSetting()
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{
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// -1- Enabling the Main Oscillator:
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//*#define AT91C_PMC_MOR ((AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register
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//*#define AT91C_PMC_PLLR ((AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register
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//*#define AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register
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//*pPMC->PMC_MOR = (( AT91C_CKGR_OSCOUNT & (0x06 <<8) | //0x0000 0600
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// AT91C_CKGR_MOSCEN )); //0x0000 0001
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__writeMemory32(0x00000601,0xFFFFFC20,"Memory");
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// -2- Wait
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// -3- Setting PLL and divider:
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// - div by 5 Fin = 3,6864 =(18,432 / 5)
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// - Mul 25+1: Fout = 95,8464 =(3,6864 *26)
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// for 96 MHz the erroe is 0.16%
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// Field out NOT USED = 0
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// PLLCOUNT pll startup time esrtimate at : 0.844 ms
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// PLLCOUNT 28 = 0.000844 /(1/32768)
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// pPMC->PMC_PLLR = ((AT91C_CKGR_DIV & 0x05) | //0x0000 0005
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// (AT91C_CKGR_PLLCOUNT & (28<<8)) //0x0000 1C00
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// (AT91C_CKGR_MUL & (25<<16))); //0x0019 0000
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__writeMemory32(0x00191C05,0xFFFFFC2C,"Memory");
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// -2- Wait
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// -5- Selection of Master Clock and Processor Clock
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// select the PLL clock divided by 2
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// pPMC->PMC_MCKR = AT91C_PMC_CSS_PLL_CLK | //0x0000 0003
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// AT91C_PMC_PRES_CLK_2 ; //0x0000 0004
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__writeMemory32(0x00000007,0xFFFFFC30,"Memory");
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__message "------------------------------- PLL Enable ----------------------------------------";
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}
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|
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//-----------------------------------------------------------------------------
|
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// Watchdog
|
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//-------------------------------
|
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// Normally, the Watchdog is enable at the reset for load it's preferable to
|
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// Disable.
|
||||
//-----------------------------------------------------------------------------
|
||||
Watchdog()
|
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{
|
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//* Watchdog Disable
|
||||
// AT91C_BASE_WDTC->WDTC_WDMR= AT91C_WDTC_WDDIS;
|
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__writeMemory32(0x00008000,0xFFFFFD44,"Memory");
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__message "------------------------------- Watchdog Disable ----------------------------------------";
|
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}
|
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|
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CheckNoRemap()
|
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{
|
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//* Read the value at 0x0
|
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__mac_i =__readMemory32(0x00000000,"Memory");
|
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__mac_mem = __mac_i;
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__mac_i=__mac_i+1;
|
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__writeMemory32(__mac_i,0x00,"Memory");
|
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__mac_pt=__readMemory32(0x00000000,"Memory");
|
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|
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if (__mac_i == __mac_pt)
|
||||
{
|
||||
__message "------------------------------- The Remap is done ----------------------------------------";
|
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__writeMemory32( __mac_mem,0x00000000,"Memory");
|
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|
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} else {
|
||||
__message "------------------------------- The Remap is NOT -----------------------------------------";
|
||||
//* Toggel RESET The remap
|
||||
__writeMemory32(0x00000001,0xFFFFFF00,"Memory");
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
// Reset the Interrupt Controller
|
||||
//-------------------------------
|
||||
// Normally, the code is executed only if a reset has been actually performed.
|
||||
// So, the AIC initialization resumes at setting up the default vectors.
|
||||
//-----------------------------------------------------------------------------
|
||||
AIC()
|
||||
{
|
||||
// Mask All interrupt pAic->AIC_IDCR = 0xFFFFFFFF;
|
||||
__writeMemory32(0xffffffff,0xFFFFF124,"Memory");
|
||||
__writeMemory32(0xffffffff,0xFFFFF128,"Memory");
|
||||
// disable peripheral clock Peripheral Clock Disable Register
|
||||
__writeMemory32(0xffffffff,0xFFFFFC14,"Memory");
|
||||
|
||||
// #define AT91C_TC0_SR ((AT91_REG *) 0xFFFA0020) // (TC0) Status Register
|
||||
// #define AT91C_TC1_SR ((AT91_REG *) 0xFFFA0060) // (TC1) Status Register
|
||||
// #define AT91C_TC2_SR ((AT91_REG *) 0xFFFA00A0) // (TC2) Status Register
|
||||
__readMemory32(0xFFFA0020,"Memory");
|
||||
__readMemory32(0xFFFA0060,"Memory");
|
||||
__readMemory32(0xFFFA00A0,"Memory");
|
||||
for (__mac_i=0;__mac_i < 8; __mac_i++)
|
||||
{
|
||||
// AT91C_BASE_AIC->AIC_EOICR
|
||||
__mac_pt = __readMemory32(0xFFFFF130,"Memory");
|
||||
|
||||
}
|
||||
__message "------------------------------- AIC 2 INIT ---------------------------------------------";
|
||||
}
|
||||
|
||||
ini()
|
||||
{
|
||||
__writeMemory32(0x0,0x00,"Register");
|
||||
__writeMemory32(0x0,0x04,"Register");
|
||||
__writeMemory32(0x0,0x08,"Register");
|
||||
__writeMemory32(0x0,0x0C,"Register");
|
||||
__writeMemory32(0x0,0x10,"Register");
|
||||
__writeMemory32(0x0,0x14,"Register");
|
||||
__writeMemory32(0x0,0x18,"Register");
|
||||
__writeMemory32(0x0,0x1C,"Register");
|
||||
__writeMemory32(0x0,0x20,"Register");
|
||||
__writeMemory32(0x0,0x24,"Register");
|
||||
__writeMemory32(0x0,0x28,"Register");
|
||||
__writeMemory32(0x0,0x2C,"Register");
|
||||
__writeMemory32(0x0,0x30,"Register");
|
||||
__writeMemory32(0x0,0x34,"Register");
|
||||
__writeMemory32(0x0,0x38,"Register");
|
||||
|
||||
// Set CPSR
|
||||
__writeMemory32(0x0D3,0x98,"Register");
|
||||
|
||||
|
||||
}
|
||||
|
||||
RG()
|
||||
{
|
||||
|
||||
__mac_i =__readMemory32(0x00,"Register"); __message "R00 0x",__mac_i:%X;
|
||||
__mac_i =__readMemory32(0x04,"Register"); __message "R01 0x",__mac_i:%X;
|
||||
__mac_i =__readMemory32(0x08,"Register"); __message "R02 0x",__mac_i:%X;
|
||||
__mac_i =__readMemory32(0x0C,"Register"); __message "R03 0x",__mac_i:%X;
|
||||
__mac_i =__readMemory32(0x10,"Register"); __message "R04 0x",__mac_i:%X;
|
||||
__mac_i =__readMemory32(0x14,"Register"); __message "R05 0x",__mac_i:%X;
|
||||
__mac_i =__readMemory32(0x18,"Register"); __message "R06 0x",__mac_i:%X;
|
||||
__mac_i =__readMemory32(0x1C,"Register"); __message "R07 0x",__mac_i:%X;
|
||||
__mac_i =__readMemory32(0x20,"Register"); __message "R08 0x",__mac_i:%X;
|
||||
__mac_i =__readMemory32(0x24,"Register"); __message "R09 0x",__mac_i:%X;
|
||||
__mac_i =__readMemory32(0x28,"Register"); __message "R10 0x",__mac_i:%X;
|
||||
__mac_i =__readMemory32(0x2C,"Register"); __message "R11 0x",__mac_i:%X;
|
||||
__mac_i =__readMemory32(0x30,"Register"); __message "R12 0x",__mac_i:%X;
|
||||
__mac_i =__readMemory32(0x34,"Register"); __message "R13 0x",__mac_i:%X;
|
||||
__mac_i =__readMemory32(0x38,"Register"); __message "R14 0x",__mac_i:%X;
|
||||
__mac_i =__readMemory32(0x3C,"Register"); __message "R13 SVC 0x",__mac_i:%X;
|
||||
__mac_i =__readMemory32(0x40,"Register"); __message "R14 SVC 0x",__mac_i:%X;
|
||||
__mac_i =__readMemory32(0x44,"Register"); __message "R13 ABT 0x",__mac_i:%X;
|
||||
__mac_i =__readMemory32(0x48,"Register"); __message "R14 ABT 0x",__mac_i:%X;
|
||||
__mac_i =__readMemory32(0x4C,"Register"); __message "R13 UND 0x",__mac_i:%X;
|
||||
__mac_i =__readMemory32(0x50,"Register"); __message "R14 UND 0x",__mac_i:%X;
|
||||
__mac_i =__readMemory32(0x54,"Register"); __message "R13 IRQ 0x",__mac_i:%X;
|
||||
__mac_i =__readMemory32(0x58,"Register"); __message "R14 IRQ 0x",__mac_i:%X;
|
||||
__mac_i =__readMemory32(0x5C,"Register"); __message "R08 FIQ 0x",__mac_i:%X;
|
||||
__mac_i =__readMemory32(0x60,"Register"); __message "R09 FIQ 0x",__mac_i:%X;
|
||||
__mac_i =__readMemory32(0x64,"Register"); __message "R10 FIQ 0x",__mac_i:%X;
|
||||
__mac_i =__readMemory32(0x68,"Register"); __message "R11 FIQ 0x",__mac_i:%X;
|
||||
__mac_i =__readMemory32(0x6C,"Register"); __message "R12 FIQ 0x",__mac_i:%X;
|
||||
__mac_i =__readMemory32(0x70,"Register"); __message "R13 FIQ 0x",__mac_i:%X;
|
||||
__mac_i =__readMemory32(0x74,"Register"); __message "R14 FIQ0x",__mac_i:%X;
|
||||
__mac_i =__readMemory32(0x98,"Register"); __message "CPSR ",__mac_i:%X;
|
||||
__mac_i =__readMemory32(0x94,"Register"); __message "SPSR ",__mac_i:%X;
|
||||
__mac_i =__readMemory32(0x9C,"Register"); __message "SPSR ABT ",__mac_i:%X;
|
||||
__mac_i =__readMemory32(0xA0,"Register"); __message "SPSR ABT ",__mac_i:%X;
|
||||
__mac_i =__readMemory32(0xA4,"Register"); __message "SPSR UND ",__mac_i:%X;
|
||||
__mac_i =__readMemory32(0xA8,"Register"); __message "SPSR IRQ ",__mac_i:%X;
|
||||
__mac_i =__readMemory32(0xAC,"Register"); __message "SPSR FIQ ",__mac_i:%X;
|
||||
|
||||
__mac_i =__readMemory32(0xB4,"Register"); __message "PC 0x",__mac_i:%X;
|
||||
|
||||
}
|
||||
|
||||
135
Demo/uIP_Demo_IAR_ARM7/resource/at91SAM7X256_NoRemap.xcl
Normal file
135
Demo/uIP_Demo_IAR_ARM7/resource/at91SAM7X256_NoRemap.xcl
Normal file
|
|
@ -0,0 +1,135 @@
|
|||
// ---------------------------------------------------------
|
||||
// ATMEL Microcontroller Software Support - ROUSSET -
|
||||
// ---------------------------------------------------------
|
||||
// The software is delivered "AS IS" without warranty or
|
||||
// condition of any kind, either express, implied or
|
||||
// statutory. This includes without limitation any warranty
|
||||
// or condition with respect to merchantability or fitness
|
||||
// for any particular purpose, or against the infringements of
|
||||
// intellectual property rights of others.
|
||||
// ---------------------------------------------------------
|
||||
// File: at91SAM7x256_NoRemap.xlc
|
||||
//
|
||||
//
|
||||
// $Revision: 1.1.1.1 $
|
||||
//
|
||||
// ---------------------------------------------------------
|
||||
|
||||
//*************************************************************************
|
||||
// XLINK command file template for EWARM/ICCARM
|
||||
//
|
||||
// Usage: xlink -f lnkarm <your_object_file(s)>
|
||||
// -s <program start label> <C/C++ runtime library>
|
||||
//
|
||||
// $Revision: 1.1.1.1 $
|
||||
//*************************************************************************
|
||||
|
||||
//************************************************
|
||||
// Inform the linker about the CPU family used.
|
||||
// AT91SAM7S64 Memory mapping
|
||||
// No remap
|
||||
// ROMSTART
|
||||
// Start address 0x0000 0000
|
||||
// Size 256 Kbo 0x0004 0000
|
||||
// RAMSTART
|
||||
// Start address 0x0020 0000
|
||||
// Size 64Kbo 0x0001 0000
|
||||
// Remap done
|
||||
// RAMSTART
|
||||
// Start address 0x0000 0000
|
||||
// Size 64Kbo 0x0001 0000
|
||||
// ROMSTART
|
||||
// Start address 0x0010 0000
|
||||
// Size 256Kbo 0x0004 0000
|
||||
|
||||
//************************************************
|
||||
-carm
|
||||
|
||||
//*************************************************************************
|
||||
// Internal Ram segments mapped AFTER REMAP 64K.
|
||||
//*************************************************************************
|
||||
// Use these addresses for the .
|
||||
-Z(CONST)INTRAMSTART_REMAP=00200000
|
||||
-Z(CONST)INTRAMEND_REMAP=0020FFFF
|
||||
|
||||
//*************************************************************************
|
||||
// Read-only segments mapped to Flash 256K.
|
||||
//*************************************************************************
|
||||
-DROMSTART=00000000
|
||||
-DROMEND=0003FFFF
|
||||
//*************************************************************************
|
||||
// Read/write segments mapped to RAM.
|
||||
//*************************************************************************
|
||||
-DRAMSTART=00200000
|
||||
-DRAMEND=00200FFFF
|
||||
|
||||
//************************************************
|
||||
// Address range for reset and exception
|
||||
// vectors (INTVEC).
|
||||
// The vector area is 32 bytes,
|
||||
// an additional 32 bytes is allocated for the
|
||||
// constant table used by ldr PC in cstartup.s79.
|
||||
//************************************************
|
||||
-Z(CODE)INTVEC=00-3F
|
||||
|
||||
//************************************************
|
||||
// Startup code and exception routines (ICODE).
|
||||
//************************************************
|
||||
-Z(CODE)ICODE,DIFUNCT=ROMSTART-ROMEND
|
||||
-Z(CODE)SWITAB=ROMSTART-ROMEND
|
||||
|
||||
//************************************************
|
||||
// Code segments may be placed anywhere.
|
||||
//************************************************
|
||||
-Z(CODE)CODE=ROMSTART-ROMEND
|
||||
|
||||
//************************************************
|
||||
// Various constants and initializers.
|
||||
//************************************************
|
||||
-Z(CONST)INITTAB,DATA_ID,DATA_C=ROMSTART-ROMEND
|
||||
-Z(CONST)CHECKSUM=ROMSTART-ROMEND
|
||||
|
||||
|
||||
//************************************************
|
||||
// Data segments.
|
||||
//************************************************
|
||||
-Z(DATA)DATA_I,DATA_Z,DATA_N=RAMSTART-RAMEND
|
||||
|
||||
//************************************************
|
||||
// __ramfunc code copied to and executed from RAM.
|
||||
//************************************************
|
||||
-Z(DATA)CODE_I=RAMSTART-RAMEND
|
||||
|
||||
//************************************************
|
||||
// ICCARM produces code for __ramfunc functions in
|
||||
// CODE_I segments. The -Q XLINK command line
|
||||
// option redirects XLINK to emit the code in the
|
||||
// debug information associated with the CODE_I
|
||||
// segment, where the code will execute.
|
||||
//************************************************
|
||||
|
||||
//*************************************************************************
|
||||
// Stack and heap segments.
|
||||
//*************************************************************************
|
||||
//-D_CSTACK_SIZE=(400*4)
|
||||
//-D_IRQ_STACK_SIZE=(2*8*4)
|
||||
|
||||
//-Z(DATA)CSTACK+_CSTACK_SIZE=RAMSTART-RAMEND
|
||||
//-Z(DATA)IRQ_STACK+_IRQ_STACK_SIZE=RAMSTART-RAMEND
|
||||
|
||||
//*************************************************************************
|
||||
// ELF/DWARF support.
|
||||
//
|
||||
// Uncomment the line "-Felf" below to generate ELF/DWARF output.
|
||||
// Available format specifiers are:
|
||||
//
|
||||
// "-yn": Suppress DWARF debug output
|
||||
// "-yp": Multiple ELF program sections
|
||||
// "-yas": Format suitable for debuggers from ARM Ltd (also sets -p flag)
|
||||
//
|
||||
// "-Felf" and the format specifiers can also be supplied directly as
|
||||
// command line options, or selected from the Xlink Output tab in the
|
||||
// IAR Embedded Workbench.
|
||||
//*************************************************************************
|
||||
|
||||
// -Felf
|
||||
Loading…
Add table
Add a link
Reference in a new issue