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First version under SVN is V4.0.1

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Richard Barry 2006-05-02 09:39:15 +00:00
parent 243393860c
commit b6df57c7e3
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38
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#ifndef INC_2329_H
#define INC_2329_H
/* DATA TYPES MIGHT NOT BE CORRECT. */
#define BASE2329 0xFF0000
/* Definitions for GPIO. */
#define P1DDR ( *( ( volatile unsigned char * ) 0xFFFEB0 ) )
#define P1DR ( *( ( volatile unsigned char * ) 0xFFFF60 ) )
#define PORT1 ( *( ( volatile unsigned char * ) 0xFFFF50 ) )
#define P2DDR ( *( ( volatile unsigned char * ) 0xFFFEB1 ) )
#define P2DR ( *( ( volatile unsigned char * ) 0xFFFF61 ) )
#define PORT2 ( *( ( volatile unsigned char * ) 0xFFFF51 ) )
#define P3DDR ( *( ( volatile unsigned char * ) 0xFFFEB2 ) )
#define P3DR ( *( ( volatile unsigned char * ) 0xFFFF62 ) )
#define PORT3 ( *( ( volatile unsigned char * ) 0xFFFF52 ) )
#define P3ODR ( *( ( volatile unsigned char * ) 0xFFFF76 ) )
#define PORT4 ( *( ( volatile unsigned char * ) 0xFFFF53 ) )
#define P5DDR ( *( ( volatile unsigned char * ) 0xFFFEB4 ) )
#define P5DR ( *( ( volatile unsigned char * ) 0xFFFF64 ) )
#define PORT5 ( *( ( volatile unsigned char * ) 0xFFFF54 ) )
#define PFCR2 ( *( ( volatile unsigned char * ) 0xFFFFAC ) )
#define SYSCR ( *( ( volatile unsigned char * ) 0xFFFF39 ) )
#define P6DDR ( *( ( volatile unsigned char * ) 0xFFFEB5 ) )
#define P6DR ( *( ( volatile unsigned char * ) 0xFFFF65 ) )
#define PORT6 ( *( ( volatile unsigned char * ) 0xFFFF55 ) )
#define PFCR2 ( *( ( volatile unsigned char * ) 0xFFFFAC ) )
#define PADDR ( *( ( volatile unsigned char * ) 0xFFFEB9 ) )
#define PADR ( *( ( volatile unsigned char * ) 0xFFFF69 ) )
#define PORTA ( *( ( volatile unsigned char * ) 0xFFFF59 ) )
#define PAPCR ( *( ( volatile unsigned char * ) 0xFFFF70 ) )
#define PAODR ( *( ( volatile unsigned char * ) 0xFFFF77 ) )
#define PFCR1 ( *( ( volatile unsigned char * ) 0xFFFF45 ) )
#define PBDDR ( *( ( volatile unsigned char * ) 0xFFFEBA ) )
#define PBDR ( *( ( volatile unsigned char * ) 0xFFFF6A ) )
#define PORTB ( *( ( volatile unsigned char * ) 0xFFFF5A ) )
#define PBPCR ( *( ( volatile unsigned char * ) 0xFFFF71 ) )
#define PCDDR ( *( ( volatile unsigned char * ) 0xFFFEBB ) )
#define PCDR ( *( ( volatile unsigned char * ) 0xFFFF6B ) )
#define PORTC ( *( ( volatile unsigned char * ) 0xFFFF5B ) )
#define PCPCR ( *( ( volatile unsigned char * ) 0xFFFF72 ) )
#define PDDDR ( *( ( volatile unsigned char * ) 0xFFFEBC ) )
#define PDDR ( *( ( volatile unsigned char * ) 0xFFFF6C ) )
#define PORTD ( *( ( volatile unsigned char * ) 0xFFFF5C ) )
#define PDPCR ( *( ( volatile unsigned char * ) 0xFFFF73 ) )
#define PEDDR ( *( ( volatile unsigned char * ) 0xFFFEBD ) )
#define PEDR ( *( ( volatile unsigned char * ) 0xFFFF6D ) )
#define PORTE ( *( ( volatile unsigned char * ) 0xFFFF5D ) )
#define PEPCR ( *( ( volatile unsigned char * ) 0xFFFF74 ) )
#define PFDDR ( *( ( volatile unsigned char * ) 0xFFFEBE ) )
#define PFDR ( *( ( volatile unsigned char * ) 0xFFFF6E ) )
#define PORTF ( *( ( volatile unsigned char * ) 0xFFFF5E ) )
#define PFCR2 ( *( ( volatile unsigned char * ) 0xFFFFAC ) )
#define SYSCR ( *( ( volatile unsigned char * ) 0xFFFF39 ) )
#define PGDDR ( *( ( volatile unsigned char * ) 0xFFFEBF ) )
#define PGDR ( *( ( volatile unsigned char * ) 0xFFFF6F ) )
#define PORTG ( *( ( volatile unsigned char * ) 0xFFFF5F ) )
#define PFCR2 ( *( ( volatile unsigned char * ) 0xFFFFAC ) )
/* Definitions for TPU. */
#define TCR0 ( *( ( volatile unsigned char * ) 0xFFFFD0 ) )
#define TMDR0 ( *( ( volatile unsigned char * ) 0xFFFFD1 ) )
#define TIOR0H ( *( ( volatile unsigned char * ) 0xFFFFD2 ) )
#define TIOR0L ( *( ( volatile unsigned char * ) 0xFFFFD3 ) )
#define TIER0 ( *( ( volatile unsigned char * ) 0xFFFFD4 ) )
#define TSR0 ( *( ( volatile unsigned char * ) 0xFFFFD5 ) )
#define TCNT0 ( *( ( volatile unsigned short * ) 0xFFFFD6 ) )
#define TGR0A ( *( ( volatile unsigned short * ) 0xFFFFD8 ) )
#define TGR0B ( *( ( volatile unsigned short * ) 0xFFFFDA ) )
#define TGR0C ( *( ( volatile unsigned short * ) 0xFFFFDC ) )
#define TGR0D ( *( ( volatile unsigned short * ) 0xFFFFDE ) )
#define TCR1 ( *( ( volatile unsigned char * ) 0xFFFFE0 ) )
#define TMDR1 ( *( ( volatile unsigned char * ) 0xFFFFE1 ) )
#define TIOR1 ( *( ( volatile unsigned char * ) 0xFFFFE2 ) )
#define TIER1 ( *( ( volatile unsigned char * ) 0xFFFFE4 ) )
#define TSR1 ( *( ( volatile unsigned char * ) 0xFFFFE5 ) )
#define TCNT1 ( *( ( volatile unsigned short * ) 0xFFFFE6 ) )
#define TGR1A ( *( ( volatile unsigned short * ) 0xFFFFE8 ) )
#define TGR1B ( *( ( volatile unsigned short * ) 0xFFFFEA ) )
#define TCR2 ( *( ( volatile unsigned char * ) 0xFFFFF0 ) )
#define TMDR2 ( *( ( volatile unsigned char * ) 0xFFFFF1 ) )
#define TIOR2 ( *( ( volatile unsigned char * ) 0xFFFFF2 ) )
#define TIER2 ( *( ( volatile unsigned char * ) 0xFFFFF4 ) )
#define TSR2 ( *( ( volatile unsigned char * ) 0xFFFFF5 ) )
#define TCNT2 ( *( ( volatile unsigned short * ) 0xFFFFF6 ) )
#define TGR2A ( *( ( volatile unsigned short * ) 0xFFFFF8 ) )
#define TGR2B ( *( ( volatile unsigned short * ) 0xFFFFFA ) )
#define TCR3 ( *( ( volatile unsigned char * ) 0xFFFE80 ) )
#define TMDR3 ( *( ( volatile unsigned char * ) 0xFFFE81 ) )
#define TIOR3H ( *( ( volatile unsigned char * ) 0xFFFE82 ) )
#define TIOR3L ( *( ( volatile unsigned char * ) 0xFFFE83 ) )
#define TIER3 ( *( ( volatile unsigned char * ) 0xFFFE84 ) )
#define TSR3 ( *( ( volatile unsigned char * ) 0xFFFE85 ) )
#define TCNT3 ( *( ( volatile unsigned short * ) 0xFFFE86 ) )
#define TGR3A ( *( ( volatile unsigned short * ) 0xFFFE88 ) )
#define TGR3B ( *( ( volatile unsigned short * ) 0xFFFE8A ) )
#define TGR3C ( *( ( volatile unsigned short * ) 0xFFFE8C ) )
#define TGR3D ( *( ( volatile unsigned short * ) 0xFFFE8E ) )
#define TCR4 ( *( ( volatile unsigned char * ) 0xFFFE90 ) )
#define TMDR4 ( *( ( volatile unsigned char * ) 0xFFFE91 ) )
#define TIOR4 ( *( ( volatile unsigned char * ) 0xFFFE92 ) )
#define TIER4 ( *( ( volatile unsigned char * ) 0xFFFE94 ) )
#define TSR4 ( *( ( volatile unsigned char * ) 0xFFFE95 ) )
#define TCNT4 ( *( ( volatile unsigned short * ) 0xFFFE96 ) )
#define TGR4A ( *( ( volatile unsigned short * ) 0xFFFE98 ) )
#define TGR4B ( *( ( volatile unsigned short * ) 0xFFFE9A ) )
#define TCR5 ( *( ( volatile unsigned char * ) 0xFFFEA0 ) )
#define TMDR5 ( *( ( volatile unsigned char * ) 0xFFFEA1 ) )
#define TIOR5 ( *( ( volatile unsigned char * ) 0xFFFEA2 ) )
#define TIER5 ( *( ( volatile unsigned char * ) 0xFFFEA4 ) )
#define TSR5 ( *( ( volatile unsigned char * ) 0xFFFEA5 ) )
#define TCNT5 ( *( ( volatile unsigned short * ) 0xFFFEA6 ) )
#define TGR5A ( *( ( volatile unsigned short * ) 0xFFFEA8 ) )
#define TGR5B ( *( ( volatile unsigned short * ) 0xFFFEAA ) )
#define TSTR ( *( ( volatile unsigned char * ) 0xFFFFC0 ) )
#define TSYR ( *( ( volatile unsigned char * ) 0xFFFFC1 ) )
#define MSTPCR ( *( ( volatile unsigned short * ) 0xFFFF3C ) )
#define SCKCR ( *( ( volatile unsigned short * ) 0xFFFF3A ) )
/* Serial port. */
#define SMR0 ( *( ( volatile unsigned char * ) 0xFFFF78 ) )
#define BRR0 ( *( ( volatile unsigned char * ) 0xFFFF79 ) )
#define SCR0 ( *( ( volatile unsigned char * ) 0xFFFF7A ) )
#define TDR0 ( *( ( volatile unsigned char * ) 0xFFFF7B ) )
#define SSR0 ( *( ( volatile unsigned char * ) 0xFFFF7C ) )
#define RDR0 ( *( ( volatile unsigned char * ) 0xFFFF7D ) )
#define SCMR0 ( *( ( volatile unsigned char * ) 0xFFFF7E ) )
#define SMR1 ( *( ( volatile unsigned char * ) 0xFFFF80 ) )
#define BRR1 ( *( ( volatile unsigned char * ) 0xFFFF81 ) )
#define SCR1 ( *( ( volatile unsigned char * ) 0xFFFF82 ) )
#define TDR1 ( *( ( volatile unsigned char * ) 0xFFFF83 ) )
#define SSR1 ( *( ( volatile unsigned char * ) 0xFFFF84 ) )
#define RDR1 ( *( ( volatile unsigned char * ) 0xFFFF85 ) )
#endif

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[HEWGNUBARNEYMCGREW]
SELECTEDCPU=H8/S2000
SELECTEDMODE=Advanced
INT32=N
SELECTEDRENESAS=N
SELECTEDENDIAN=Big endian

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Demo/H8S/RTOSDemo/FreeRTOSConfig.h Normal file
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/*
FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
FreeRTOS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with FreeRTOS; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes FreeRTOS, without being obliged to provide
the source code for any proprietary components. See the licensing section
of http://www.FreeRTOS.org for full details of how and when the exception
can be applied.
***************************************************************************
See http://www.FreeRTOS.org for documentation, latest information, license
and contact details. Please ensure to read the configuration and relevant
port sections of the online documentation.
***************************************************************************
*/
#ifndef FREERTOS_CONFIG_H
#define FREERTOS_CONFIG_H
/* IO definitions for the chosen device. */
#include <2329S.h>
/*-----------------------------------------------------------
* Application specific definitions.
*
* These definitions should be adjusted for your particular hardware and
* application requirements.
*
* THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
* FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
*----------------------------------------------------------*/
#define configUSE_PREEMPTION 1
#define configUSE_IDLE_HOOK 0
#define configUSE_TICK_HOOK 0
#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 22118400 )
#define configTICK_RATE_HZ ( ( portTickType ) 1000 )
#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 4 )
#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 200 )
#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 15 * 1024 ) )
#define configMAX_TASK_NAME_LEN ( 8 )
#define configUSE_TRACE_FACILITY 0
#define configUSE_16_BIT_TICKS 1
#define configIDLE_SHOULD_YIELD 1
/* Co-routine definitions. */
#define configUSE_CO_ROUTINES 0
#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
/* Set the following definitions to 1 to include the API function, or zero
to exclude the API function. */
#define INCLUDE_vTaskPrioritySet 1
#define INCLUDE_uxTaskPriorityGet 1
#define INCLUDE_vTaskDelete 1
#define INCLUDE_vTaskCleanUpResources 0
#define INCLUDE_vTaskSuspend 1
#define INCLUDE_vTaskDelayUntil 1
#define INCLUDE_vTaskDelay 1
#endif /* FREERTOS_CONFIG_H */

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/*
FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
FreeRTOS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with FreeRTOS; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes FreeRTOS, without being obliged to provide
the source code for any proprietary components. See the licensing section
of http://www.FreeRTOS.org for full details of how and when the exception
can be applied.
***************************************************************************
See http://www.FreeRTOS.org for documentation, latest information, license
and contact details. Please ensure to read the configuration and relevant
port sections of the online documentation.
***************************************************************************
*/
/* Scheduler include files. */
#include "FreeRTOS.h"
#include "portable.h"
/* Demo application include files. */
#include "partest.h"
/*-----------------------------------------------------------
* Simple parallel port IO routines.
*
* This is for the demo application which uses port 2 for LED outputs.
*-----------------------------------------------------------*/
/* Value for the LED to be off. */
#define partstLED_OUTPUTS ( ( unsigned portCHAR ) 0xff )
/* P2.0 is not used as an output so there are only 7 LEDs on port 2. */
#define partstMAX_LEDs ( 7 )
#define partstALL_OUTPUTS_OFF ( ( unsigned portCHAR ) 0 )
/* Maps the LED outputs used by the standard demo application files to
convenient outputs for the EDK2329. Mainly this insures that the LED
used by the Check task is one of the on board LEDs so the demo can be
executed on an EDK without any modification. */
static inline unsigned portCHAR prvMapLED( unsigned portBASE_TYPE uxLED );
/*-----------------------------------------------------------*/
void vParTestInitialise( void )
{
/* LED's are connected to port 2. P2.1 and P2.2 are built onto the EDK.
P2.3 to P2.7 are soldered onto the expansion port. */
P2DDR = partstLED_OUTPUTS;
P2DR = partstALL_OUTPUTS_OFF;
}
/*-----------------------------------------------------------*/
/*
* Described at the top of the file.
*/
static inline unsigned portCHAR prvMapLED( unsigned portBASE_TYPE uxLED )
{
switch( uxLED )
{
case 0 : return ( unsigned portCHAR ) 2;
case 1 : return ( unsigned portCHAR ) 3;
case 2 : return ( unsigned portCHAR ) 4;
case 3 : return ( unsigned portCHAR ) 5;
case 4 : return ( unsigned portCHAR ) 6;
case 5 : return ( unsigned portCHAR ) 0;
case 6 : return ( unsigned portCHAR ) 1;
default : return 0;
}
}
/*-----------------------------------------------------------*/
/*
* Turn an LED on or off.
*/
void vParTestSetLED( unsigned portBASE_TYPE uxLED, signed portBASE_TYPE xValue )
{
unsigned portCHAR ucLED;
if( uxLED < partstMAX_LEDs )
{
ucLED = prvMapLED( uxLED );
/* Set a bit in the required LED position. LED 0 is bit 1. */
ucLED = ( unsigned portCHAR ) 1 << ( ucLED + 1 );
if( xValue )
{
portENTER_CRITICAL();
P2DR |= ucLED;
portEXIT_CRITICAL();
}
else
{
portENTER_CRITICAL();
P2DR &= ~ucLED;
portEXIT_CRITICAL();
}
}
}
/*-----------------------------------------------------------*/
void vParTestToggleLED( unsigned portBASE_TYPE uxLED )
{
unsigned portCHAR ucLED;
if( uxLED < partstMAX_LEDs )
{
ucLED = prvMapLED( uxLED );
/* Set a bit in the required LED position. LED 0 is bit 1. */
ucLED = ( unsigned portCHAR ) 1 << ( ucLED + 1 );
portENTER_CRITICAL();
{
if( P2DR & ucLED )
{
P2DR &= ~ucLED;
}
else
{
P2DR |= ucLED;
}
}
portEXIT_CRITICAL();
}
}

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[HIMDBVersion]
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[DATABASE_VERSION]
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[INFORMATION]
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"Debug" "C:\E\Dev\FreeRTOS\Demo\H8S\rtosdemo\debug"
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33
Demo/H8S/RTOSDemo/RTOSDemo.tps Normal file
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@ -0,0 +1,33 @@
[HIMDBVersion]
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247
Demo/H8S/RTOSDemo/Release session.hsf Normal file
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@ -0,0 +1,247 @@
[HIMDBVersion]
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"{633553C0-6FE9-11D5-B7CE-00E029352378}ProfileCtrlChartMultiOpen" "0"
"{7FA2E460-7EC0-11D5-8EB6-00004CC34E9D}SimIOWndInstanceKey0" "{WK_00000001_SIMIO}RTOSDemoSimulator"
"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_BREAK_BREAK_ACCESS_COUNT" "0"
"{C088D861-776D-45F4-A70E-079CC28D82D5}C_REGISTER_REG_1" "0000000011111111"
"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_SYSTEM_CALL_SYSTEM_CALL_FLAG" "OFF"
"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_BREAK_BREAK_DATA_COUNT" "0"
"{2BA6A3EF-6488-11D5-80D4-00C04F68EAD7}StatusWnd1ScrollHorz" "0"
"{2BA6A3EF-6488-11D5-80D4-00C04F68EAD7}StatusWnd2ColWidth1" "250"
"{AC411480-6F0A-11D5-8EB6-00004CC34E9D}ECX_IMAGE_VIEW" "0,0,0,0,0,0"
"{8A898260-6F1D-11D5-8EB6-00004CC34E9D}ECX_WAVE" "00000000,00000000,0,0"
"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd1ECX_WATCH" ""
"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegisterWnd0ColWidth0" "100"
"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_BREAK_BREAK_REGISTER_COUNT" "0"
"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_MEMORY_MAP_MAP0" "0x00000000,0x0005FFFF,16, 2,ROM"
"{287A8023-99B5-49E1-A54E-4DDCA43D7959}MapCtrlViews" "0"
"{C088D861-776D-45F4-A70E-079CC28D82D5}C_REGISTER_REG_2" "0000000000000000"
"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_EXEC_STEP_RATE" "40000"
"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_EXEC_MULT_VAL" "00000000"
"{EEDC9300-6FBE-11D5-8613-00A024591A38}LocalsCtrlViews" "0"
"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0ScrollVert" "0"
"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd2ColWidth0" "200"
"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegisterWnd0ColWidth1" "1600"
"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_MEMORY_MAP_MAP1" "0x00FF7C00,0x00FFFBFF,16, 2,RAM"
"{C088D861-776D-45F4-A70E-079CC28D82D5}C_REGISTER_REG_3" "0000000033333333"
"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_CONTROL_REGS_SYSCR_ADR" "0x00FFFF39"
"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd2ColWidth1" "200"
"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd1ScrollVert" "0"
"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegisterWndViewB0ScrollHorz" "0"
"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_MEMORY_MAP_MEMORY_MODE" "0"
"{C088D861-776D-45F4-A70E-079CC28D82D5}C_REGISTER_REG_4" "0000000044444444"
"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_EXEC_EXEC_MODE" "STOP"
"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_MEMORY_MAP_BUS_WIDTH" "24"
"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_MEMORY_MAP_ADDRESS_MAP" "24"
"{2BA6A3EF-6488-11D5-80D4-00C04F68EAD7}StatusCtrlViews" "1"
"{AC411480-6F0A-11D5-8EB6-00004CC34E9D}ECX_IMAGE_COMB_ADDRESS" ",,,,"
"{48FF5DA0-6FFA-11D5-B7CE-00E029352378}CoverageFileName" "0"
"{85AC95E0-0CE6-11D6-8EB6-00004CC34E9D}TriggerCtrlViews" "0"
"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_MEMORY_MAP_MAP2" "0x00FFFE50,0x00FFFF07,16, 2,I/O"
"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd2ColWidth2" "200"
"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ScrollHorz" "0"
"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewBInstanceKey0" "{WK_00000001_MEMORY}ViewB"
"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryCtrlViews0" "16743424"
"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_BREAK_BREAK_DATA_COUNT" "0"
"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineCtrlViews" "0"
"{C088D861-776D-45F4-A70E-079CC28D82D5}C_REGISTER_REG_5" "0000000055555555"
"{C088D861-776D-45F4-A70E-079CC28D82D5}C_REGISTER_REG_10" "000000000000007F"
"{2BA6A3EF-6488-11D5-80D4-00C04F68EAD7}StatusWnd1ScrollVert" "0"
"{AC411480-6F0A-11D5-8EB6-00004CC34E9D}ECX_IMAGE_COMB_PALETTE" ",,,,"
"{7FA2E460-7EC0-11D5-8EB6-00004CC34E9D}SimIOCtrlViews" "1"
"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_MEMORY_MAP_MAP3" "0x00FFFF28,0x00FFFFFF,16, 2,I/O"
"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd3ScrollHorz" "0"
"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0Exp0" "0"
"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryCtrlOneLineBytesCount0" "16"
"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegisterWndViewB0ColWidth0" "100"
"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_MEMORY_MAP_MEMORY_MAP_COUNT" "4"
"{C088D861-776D-45F4-A70E-079CC28D82D5}C_REGISTER_REG_6" "0000000000FF820C"
"{C088D861-776D-45F4-A70E-079CC28D82D5}C_REGISTER_REG_11" "0000000000000000"
"{2BA6A3EF-6488-11D5-80D4-00C04F68EAD7}StatusWnd0ScrollHorz" "0"
"{5F75FDA0-6FF0-11D5-B7CE-00E029352378}PACtrlViews" "0"
"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd3ColWidth0" "200"
"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd2ECX_WATCH" ""
"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegisterWndViewB0ColWidth1" "1600"
"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_SESSION_IS_SAVED" "YES"
"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_MEMORY_MAP_BUS_WIDTH" "24"
"{C088D861-776D-45F4-A70E-079CC28D82D5}C_REGISTER_REG_7" "0000000000FF8200"
"{C088D861-776D-45F4-A70E-079CC28D82D5}C_REGISTER_REG_12" "00000000FFFFFF00"
"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOCtrlViews" "1"
"{AC411480-6F0A-11D5-8EB6-00004CC34E9D}ECX_IMAGE_BUFFER" "00000000,00000000,0,0"
"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd3ColWidth1" "200"
"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryCtrlProperty0" "5"
"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegisterWndViewB0ScrollVert" "0"
"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegisterWndViewB0ECX_REGISTER_DISPLAYED" "1,1,1,1,1,1,1,1,1,1,1"
"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegisterWndViewB0ECX_REGISTER_COUNT" "11"
"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_MEMORY_RESOURCE_MEMORY_RESOURCE_COUNT" "4"
"{C088D861-776D-45F4-A70E-079CC28D82D5}C_REGISTER_REG_8" "0000000000004E9C"
"{C088D861-776D-45F4-A70E-079CC28D82D5}C_REGISTER_REG_13" "0000000000000000"
"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_CONFIG_FETCH_MODE" "32"
"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_MEMORY_RESOURCE_MEMRES0" "0x00000000,0x0005FFFF,14"
"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_TRACE_TRACE_ACQUISITION" "0,1024,0,0"
"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_SESSION_IS_SAVED" "YES"
"{2BA6A3EF-6488-11D5-80D4-00C04F68EAD7}StatusWnd0ColWidth0" "250"
"{D595F9C0-EF22-11D5-B7DB-0000E10B3DA9}EventCtrlViews" "0"
"{B266D880-6FA1-11D5-8613-00A024591A38}WatchCtrlViews" "0"
"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd3ColWidth2" "200"
"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ScrollVert" "0"
"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_TRACE_TRACE_ACQUISITION" "0,1024,0,0"
"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_MEMORY_RESOURCE_MEMRES0" "0x00000000,0x00005FFF,14"
"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_SYSTEM_CALL_SYSTEM_CALL_FLAG" "OFF"
"{C088D861-776D-45F4-A70E-079CC28D82D5}C_REGISTER_REG_9" "0000000000000080"
"{C088D861-776D-45F4-A70E-079CC28D82D5}C_REGISTER_REG_14" "0000000000000000"
"{2BA6A3EF-6488-11D5-80D4-00C04F68EAD7}StatusWnd0ColWidth1" "250"
"{8A898260-6F1D-11D5-8EB6-00004CC34E9D}ECX_WAVE_COMB_ADDRESS" ",,,,"
"{5F75FDA0-6FF0-11D5-B7CE-00E029352378}PACtrlPAState" "0"
"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd3ScrollVert" "0"
"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ColWidth0" "200"
"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryCtrlViews30" "16776191"
"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_MEMORY_RESOURCE_MEMRES1" "0x00FF7C00,0x00FFFBFF,15"
"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_CONTROL_REGS_CREG_CNT" "0"
"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_CONFIG_ENDIAN" "BIG"
"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_CONFIG_MULTIPLIER" "DISABLE"
"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_BREAK_PC_BREAK_COUNT" "0"
"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_BREAK_BREAK_CYCLE_COUNT" "0"
"{2BA6A3EF-6488-11D5-80D4-00C04F68EAD7}StatusWnd0ScrollVert" "0"
"{30F726A1-F13D-4E21-9A4F-FD7FF70EDFDA}TraceCtrlViews" "0"
"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd2ScrollHorz" "0"
"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ColWidth1" "200"
"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryCtrlViews20" "16743424"
"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegisterWnd0ScrollHorz" "0"
"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegisterWnd0ECX_REGISTER_COUNT" "11"
"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_BREAK_BREAK_CYCLE_COUNT" "0"
"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineCtrlBatchFileName" ""
"{313F4FC0-6566-11D5-8BBE-0004E2013C71}DisassemblyCtrlViews" "0"
"{8A898260-6F1D-11D5-8EB6-00004CC34E9D}WaveformCtrlViews" "0"
"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_MEMORY_RESOURCE_MEMRES2" "0x00FFFE50,0x00FFFF07,7"
"{7943C44E-7D44-422A-9140-4CF55C88F7D3}DifferenceCtrlViews" "0"
"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd3ECX_WATCH" ""
"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ColWidth2" "200"
"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_EXEC_STEP_RATE" "40000"
"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegisterCtrlViews" "0"
"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_CONFIG_ROUND" "RM_NEAR"
"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_MEMORY_MAP_MAP0" "0x00000000,0x0005FFFF, 8, 3,ROM"
"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_CONTROL_REGS_CREG_CNT" "3"
"{2BA6A3EF-6488-11D5-80D4-00C04F68EAD7}StatusWnd1ColWidth0" "250"
"{2BA6A3EF-6488-11D5-80D4-00C04F68EAD7}StatusWnd2ScrollHorz" "0"
"{633553C0-6FE9-11D5-B7CE-00E029352378}ProfileCtrlEnable" "0"
"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_MEMORY_RESOURCE_MEMRES3" "0x00FFFF28,0x00FFFFFF,7"
"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0ColWidth0" "200"
"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryCtrlDataCount0" "4"
"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegisterWndViewBInstanceKey0" "{WK_00000001_REGISTER}ViewB"
"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_BREAK_PC_BREAK_COUNT" "0"
"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_SYSTEM_CALL_SYSTEM_CALL_ADDRESS" "0x00000000"
"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_CONFIG_ENDIAN" "BIG"
"{C088D861-776D-45F4-A70E-079CC28D82D5}C_REGISTER_REG_COUNT" "11"
"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_MEMORY_MAP_MAP1" "0x00FF7C00,0x00FFFBFF, 8, 3,RAM"
"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_BREAK_BREAK_SEQUENCE_COUNT" "0"
"{2BA6A3EF-6488-11D5-80D4-00C04F68EAD7}StatusWnd1ColWidth1" "250"
"{8A898260-6F1D-11D5-8EB6-00004CC34E9D}ECX_WAVE_COMB_BUFFER" ",,,,"
"{48FF5DA0-6FFA-11D5-B7CE-00E029352378}CoverageCtrlViews" "0"
"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0ColWidth1" "100"
"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ECX_WATCH" "pxCreatedTask,"
"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_EXEC_EXEC_MODE" "STOP"
"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineCtrlLogFileName" ""
"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_MEMORY_MAP_PRG_WIDTH" "24"
"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_MEMORY_MAP_MEMORY_MAP_COUNT" "4"
"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_MEMORY_MAP_MAP2" "0x00FFFE50,0x00FFFF07, 8, 2,RAM"
"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_BREAK_BREAK_ACCESS_COUNT" "0"
"{633553C0-6FE9-11D5-B7CE-00E029352378}ProfileCtrlViews" "0"
"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0ColWidth2" "100"
"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd2ScrollVert" "0"
"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd1ColWidth0" "200"
"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegisterWndInstanceKey0" "{WK_00000001_REGISTER}"
"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegisterWnd0ScrollVert" "0"
"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_CONFIG_ROUND" "RM_NEAR"
"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_SYSTEM_CALL_SYSTEM_CALL_ADDRESS" "0x00000000"
"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_MEMORY_MAP_MAP3" "0x00FFFF28,0x00FFFFFF, 8, 2,RAM"
"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_CONTROL_REGS_CREG0" "0x00FFFF39,2,0x00000101"
"{AC411480-6F0A-11D5-8EB6-00004CC34E9D}ImageCtrlViews" "0"
"{48FF5DA0-6FFA-11D5-B7CE-00E029352378}CoverageCtrlViewsFromDiffFile" "0"
"{EEDC9301-6FBE-11D5-8613-00A024591A38}StackTraceCtrlViews" "0"
"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0ColWidth3" "100"
"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0ScrollHorz" "0"
[LANGUAGE]
"English"
[CONFIG_INFO_VD1]
1
[CONFIG_INFO_VD2]
0
[CONFIG_INFO_VD3]
0
[CONFIG_INFO_VD4]
0
[WINDOW_POSITION_STATE_DATA_VD1]
"{WK_TB00000009_VERSIONCONTROL}" "TOOLBAR 0" 59419 0 4 "0.00" 0 0 0 0 0 17 0 "" "0.0"
"{WK_TB00000004_TEMPLATES}" "TOOLBAR 0" 59419 0 8 "0.00" 0 0 0 0 0 18 0 "" "0.0"
"TCL Toolkit" "WINDOW" 59422 1 0 "-1.000000" -1 -1000 -1000 -1 -1 17 0 "" "-1"
"{WK_TB00000002_EDITOR}" "TOOLBAR 0" 59419 0 2 "0.00" 0 0 0 0 0 18 0 "" "0.0"
"{WK_TB00000012_MAP}" "TOOLBAR 0" 59419 0 3 "0.00" 0 0 0 0 0 18 0 "" "0.0"
"{WK_TB00000017_FDT}" "TOOLBAR 0" 59419 0 1 "0.00" 0 0 0 0 0 18 0 "" "0.0"
"{WK_00000001_MAP}RTOSDemoRelease session" "WINDOW" 59421 -1 -1 "-1.000000" -1 -1000 -1000 -1 -1 18 0 "" "-1"
"{WK_TB00000003_BOOKMARKS}" "TOOLBAR 0" 59419 1 0 "0.00" 0 0 0 0 0 18 0 "" "0.0"
"{WK_TB00000018_DEFAULTWINDOW}" "TOOLBAR 0" 59419 1 1 "0.00" 0 0 0 0 0 17 0 "" "0.0"
"{WK_TB00000008_DEBUGRUN}" "TOOLBAR 0" 59419 0 5 "0.00" 0 0 0 0 0 17 0 "" "0.0"
"{WK_TB00000005_SEARCH}" "TOOLBAR 0" 59419 0 7 "0.00" 0 0 0 0 0 18 0 "" "0.0"
"{WK_00000001_OUTPUT}" "WINDOW" 59422 0 0 "1.00" 180 0 0 350 200 18 0 "" "0.0"
"{WK_00000002_WORKSPACE}" "WINDOW" 59420 0 0 "1.00" 280 0 0 350 200 18 0 "" "0.0"
"{WK_TB00000001_STANDARD}" "TOOLBAR 0" 59419 0 0 "0.00" 0 0 0 0 0 18 0 "" "0.0"
"{WK_TB00000007_DEBUG}" "TOOLBAR 0" 59419 0 6 "0.00" 0 0 0 0 0 17 0 "" "0.0"
[WINDOW_POSITION_STATE_DATA_VD2]
[WINDOW_POSITION_STATE_DATA_VD3]
[WINDOW_POSITION_STATE_DATA_VD4]
[WINDOW_Z_ORDER]
"C:\E\Dev\FreeRTOS\Demo\H8S\rtosdemo\partest\partest.c"
"C:\E\Dev\FreeRTOS\Demo\H8S\rtosdemo\serial\serial.c"
"c:\e\Dev\FreeRTOS\Source\queue.c"
"C:\E\Dev\FreeRTOS\Source\portable\GCC\H8S2329\portmacro.h"
"c:\e\Dev\FreeRTOS\Source\portable\GCC\H8S2329\port.c"
"C:\E\Dev\FreeRTOS\Demo\H8S\rtosdemo\main.c"
"C:\E\Dev\FreeRTOS\Source\include\portable.h"
"c:\e\Dev\FreeRTOS\Demo\Common\Minimal\BlockQ.c"
[TARGET_NAME]
""
[DEBUGGER_OPTIONS]
""
[DOWNLOAD_MODULES]
[CONNECT_ON_GO]
"TRUE"
[DOWNLOAD_MODULES_AFTER_BUILD]
"TRUE"
[REMOVE_BREAKPOINTS_ON_DOWNLOAD]
"FALSE"
[COMMAND_FILES]
[DEFAULT_DEBUG_FORMAT]
""
[FLASH_DETAILS]
"2212.000000" 1 -127 "B" 0 "COM1" 115200 1 "H8S/2329BF" 1 0 0 0 1 0 0 "D:\DevTools\Hitachi\FDT2.2\Kernels\ProtB\2329\hitachi\1_1_00\" "" "" "" ""
[BREAKPOINTS]
[END]

6
Demo/H8S/RTOSDemo/Release/gnuconfig.ini Normal file
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[HEWGNUBARNEYMCGREW]
SELECTEDCPU=H8/S2000
SELECTEDMODE=Advanced
INT32=N
SELECTEDRENESAS=N
SELECTEDENDIAN=Big endian

245
Demo/H8S/RTOSDemo/Simulator sessions.hsf Normal file
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[HIMDBVersion]
2.0
[DATABASE_VERSION]
"2.0"
[SESSION_DETAILS]
""
[INFORMATION]
""
[GENERAL_DATA]
"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd1ColWidth1" "200"
"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewAInstanceKey0" "{WK_00000001_MEMORY}RTOSDemoSimulator"
"{2BA6A3EF-6488-11D5-80D4-00C04F68EAD7}StatusWnd2ScrollVert" "0"
"{AC411480-6F0A-11D5-8EB6-00004CC34E9D}ECX_IMAGE_COLOR" "0,0,0,0"
"{2BA6A3EE-6488-11D5-80D4-00C04F68EAD7}LabelCtrlViews" "0"
"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_BREAK_BREAK_REGISTER_COUNT" "0"
"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_MEMORY_RESOURCE_MEMORY_RESOURCE_COUNT" "1"
"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_CONTROL_REGS_CREG1" "0x00FFFF32,1,0x00000000"
"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_MEMORY_MAP_MAP4" "0x00E00000,0x00EFFFFF, 8, 3,EXT"
"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_MEMORY_MAP_MEMORY_MODE" "0"
"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_BREAK_BREAK_SEQUENCE_COUNT" "0"
"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd1ScrollHorz" "0"
"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd1ColWidth2" "200"
"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWndInstanceKey0" "{WK_00000001_WATCH}RTOSDemoSimulator"
"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegisterWnd0ECX_REGISTER_DISPLAYED" "1,1,1,1,1,1,1,1,1,1,1"
"{2BA6A3EF-6488-11D5-80D4-00C04F68EAD7}StatusWnd2ColWidth0" "250"
"{633553C0-6FE9-11D5-B7CE-00E029352378}ProfileCtrlChartMultiOpen" "0"
"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryCtrlViews" "0"
"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_CONTROL_REGS_CREG2" "0x00FFFD95,1,0x00000000"
"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_MEMORY_MAP_MAP5" "0x00F00000,0x00FDBFFF, 8, 3,EXT"
"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_CONFIG_DIVISOR" "DISABLE"
"{C088D861-776D-45F4-A70E-079CC28D82D5}C_REGISTER_REG_0" "0000000000000000"
"{313F4FC1-6566-11D5-8BBE-0004E2013C71}TclTkCtrlLogFileName" ""
"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_MEMORY_MAP_PRG_WIDTH" "24"
"{7FA2E460-7EC0-11D5-8EB6-00004CC34E9D}SimIOWndInstanceKey0" "{WK_00000001_SIMIO}RTOSDemoSimulator"
"{2BA6A3EF-6488-11D5-80D4-00C04F68EAD7}StatusWnd2ColWidth1" "250"
"{2BA6A3EF-6488-11D5-80D4-00C04F68EAD7}StatusWnd1ScrollHorz" "0"
"{8A898260-6F1D-11D5-8EB6-00004CC34E9D}ECX_WAVE" "00000000,00000000,0,0"
"{AC411480-6F0A-11D5-8EB6-00004CC34E9D}ECX_IMAGE_VIEW" "0,0,0,0,0,0"
"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_BREAK_BREAK_DATA_COUNT" "0"
"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_MEMORY_MAP_MAP6" "0x00FDC000,0x00FEBFFF,16, 3,RAM"
"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_SYSTEM_CALL_SYSTEM_CALL_FLAG" "OFF"
"{C088D861-776D-45F4-A70E-079CC28D82D5}C_REGISTER_REG_1" "0000000011111111"
"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_BREAK_BREAK_ACCESS_COUNT" "0"
"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd1ECX_WATCH" ""
"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegisterWnd0ColWidth0" "100"
"{EEDC9300-6FBE-11D5-8613-00A024591A38}LocalsCtrlViews" "0"
"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_MEMORY_MAP_MAP7" "0x00FEC000,0x00FFBFFF,16, 1,RAM"
"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_EXEC_MULT_VAL" "00000000"
"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_EXEC_STEP_RATE" "40000"
"{C088D861-776D-45F4-A70E-079CC28D82D5}C_REGISTER_REG_2" "0000000000000001"
"{287A8023-99B5-49E1-A54E-4DDCA43D7959}MapCtrlViews" "0"
"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_MEMORY_MAP_MAP0" "0x00000000,0x0005FFFF,16, 2,ROM"
"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_BREAK_BREAK_REGISTER_COUNT" "0"
"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0ScrollVert" "0"
"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd2ColWidth0" "200"
"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegisterWnd0ColWidth1" "1600"
"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_CONTROL_REGS_SYSCR_ADR" "0x00FFFF39"
"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_MEMORY_MAP_MAP8" "0x00FFC000,0x00FFDFFF, 8, 3,EXT"
"{C088D861-776D-45F4-A70E-079CC28D82D5}C_REGISTER_REG_3" "0000000033333333"
"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_MEMORY_MAP_MAP1" "0x00FF7C00,0x00FFFBFF,16, 2,RAM"
"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd2ColWidth1" "200"
"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd1ScrollVert" "0"
"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegisterWndViewB0ScrollHorz" "0"
"{85AC95E0-0CE6-11D6-8EB6-00004CC34E9D}TriggerCtrlViews" "0"
"{48FF5DA0-6FFA-11D5-B7CE-00E029352378}CoverageFileName" "0"
"{AC411480-6F0A-11D5-8EB6-00004CC34E9D}ECX_IMAGE_COMB_ADDRESS" ",,,,"
"{2BA6A3EF-6488-11D5-80D4-00C04F68EAD7}StatusCtrlViews" "1"
"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_MEMORY_MAP_ADDRESS_MAP" "24"
"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_MEMORY_MAP_MAP9" "0x00FFE000,0x00FFE9FF, 8, 3,EXT"
"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_MEMORY_MAP_BUS_WIDTH" "24"
"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_EXEC_EXEC_MODE" "STOP"
"{C088D861-776D-45F4-A70E-079CC28D82D5}C_REGISTER_REG_4" "0000000044444444"
"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_MEMORY_MAP_MEMORY_MODE" "0"
"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_MEMORY_MAP_MAP2" "0x00FFFE50,0x00FFFF07,16, 2,I/O"
"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd2ColWidth2" "200"
"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ScrollHorz" "0"
"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryWndViewBInstanceKey0" "{WK_00000001_MEMORY}RTOSDemoSimulatorViewB"
"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryCtrlViews0" "16756480"
"{2BA6A3EF-6488-11D5-80D4-00C04F68EAD7}StatusWnd1ScrollVert" "0"
"{7FA2E460-7EC0-11D5-8EB6-00004CC34E9D}SimIOCtrlViews" "1"
"{AC411480-6F0A-11D5-8EB6-00004CC34E9D}ECX_IMAGE_COMB_PALETTE" ",,,,"
"{C088D861-776D-45F4-A70E-079CC28D82D5}C_REGISTER_REG_10" "000000000000007F"
"{C088D861-776D-45F4-A70E-079CC28D82D5}C_REGISTER_REG_5" "0000000055555555"
"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineCtrlViews" "0"
"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_BREAK_BREAK_DATA_COUNT" "0"
"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_MEMORY_MAP_MAP3" "0x00FFFF28,0x00FFFFFF,16, 2,I/O"
"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd3ScrollHorz" "0"
"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0Exp0" "0"
"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryCtrlOneLineBytesCount0" "16"
"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegisterWndViewB0ColWidth0" "100"
"{2BA6A3EF-6488-11D5-80D4-00C04F68EAD7}StatusWnd0ScrollHorz" "0"
"{5F75FDA0-6FF0-11D5-B7CE-00E029352378}PACtrlViews" "0"
"{C088D861-776D-45F4-A70E-079CC28D82D5}C_REGISTER_REG_11" "0000000000000000"
"{C088D861-776D-45F4-A70E-079CC28D82D5}C_REGISTER_REG_6" "0000000000FF81E4"
"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_MEMORY_MAP_MEMORY_MAP_COUNT" "4"
"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd3ColWidth0" "200"
"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd2ECX_WATCH" ""
"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegisterWndViewB0ColWidth1" "1600"
"{AC411480-6F0A-11D5-8EB6-00004CC34E9D}ECX_IMAGE_BUFFER" "00000000,00000000,0,0"
"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOCtrlViews" "1"
"{C088D861-776D-45F4-A70E-079CC28D82D5}C_REGISTER_REG_12" "00000000FFFFFF00"
"{C088D861-776D-45F4-A70E-079CC28D82D5}C_REGISTER_REG_7" "0000000000FF81E4"
"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_MEMORY_MAP_BUS_WIDTH" "24"
"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_SESSION_IS_SAVED" "YES"
"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd3ColWidth1" "200"
"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryCtrlProperty0" "5"
"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegisterWndViewB0ScrollVert" "0"
"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegisterWndViewB0ECX_REGISTER_DISPLAYED" "1,1,1,1,1,1,1,1,1,1,1"
"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegisterWndViewB0ECX_REGISTER_COUNT" "11"
"{2BA6A3EF-6488-11D5-80D4-00C04F68EAD7}StatusWnd0ColWidth0" "250"
"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_MEMORY_RESOURCE_MEMRES0" "0x00000000,0x0005FFFF,14"
"{B266D880-6FA1-11D5-8613-00A024591A38}WatchCtrlViews" "0"
"{D595F9C0-EF22-11D5-B7DB-0000E10B3DA9}EventCtrlViews" "0"
"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_SESSION_IS_SAVED" "YES"
"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_TRACE_TRACE_ACQUISITION" "0,1024,0,0"
"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_CONFIG_FETCH_MODE" "32"
"{C088D861-776D-45F4-A70E-079CC28D82D5}C_REGISTER_REG_13" "0000000000000000"
"{C088D861-776D-45F4-A70E-079CC28D82D5}C_REGISTER_REG_8" "0000000000003F48"
"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_MEMORY_RESOURCE_MEMORY_RESOURCE_COUNT" "4"
"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd3ColWidth2" "200"
"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ScrollVert" "0"
"{2BA6A3EF-6488-11D5-80D4-00C04F68EAD7}StatusWnd0ColWidth1" "250"
"{5F75FDA0-6FF0-11D5-B7CE-00E029352378}PACtrlPAState" "0"
"{8A898260-6F1D-11D5-8EB6-00004CC34E9D}ECX_WAVE_COMB_ADDRESS" ",,,,"
"{C088D861-776D-45F4-A70E-079CC28D82D5}C_REGISTER_REG_14" "0000000000000000"
"{C088D861-776D-45F4-A70E-079CC28D82D5}C_REGISTER_REG_9" "0000000000000021"
"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_SYSTEM_CALL_SYSTEM_CALL_FLAG" "OFF"
"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_TRACE_TRACE_ACQUISITION" "0,1024,0,0"
"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_MEMORY_RESOURCE_MEMRES0" "0x00000000,0x00005FFF,14"
"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd3ScrollVert" "0"
"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ColWidth0" "200"
"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryCtrlViews30" "16773120"
"{2BA6A3EF-6488-11D5-80D4-00C04F68EAD7}StatusWnd0ScrollVert" "0"
"{30F726A1-F13D-4E21-9A4F-FD7FF70EDFDA}TraceCtrlViews" "0"
"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_BREAK_BREAK_CYCLE_COUNT" "0"
"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_BREAK_PC_BREAK_COUNT" "0"
"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_CONFIG_MULTIPLIER" "DISABLE"
"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_CONFIG_ENDIAN" "BIG"
"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_CONTROL_REGS_CREG_CNT" "0"
"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_MEMORY_RESOURCE_MEMRES1" "0x00FF7C00,0x00FFFBFF,15"
"{7943C44E-7D44-422A-9140-4CF55C88F7D3}DifferenceCtrlViews" "0"
"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd2ScrollHorz" "0"
"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ColWidth1" "200"
"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryCtrlViews20" "16756480"
"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegisterWnd0ScrollHorz" "0"
"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegisterWnd0ECX_REGISTER_COUNT" "11"
"{8A898260-6F1D-11D5-8EB6-00004CC34E9D}WaveformCtrlViews" "0"
"{313F4FC0-6566-11D5-8BBE-0004E2013C71}DisassemblyCtrlViews" "0"
"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineCtrlBatchFileName" ""
"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_BREAK_BREAK_CYCLE_COUNT" "0"
"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_MEMORY_RESOURCE_MEMRES2" "0x00FFFE50,0x00FFFF07,7"
"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd3ECX_WATCH" ""
"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ColWidth2" "200"
"{2BA6A3EF-6488-11D5-80D4-00C04F68EAD7}StatusWnd2ScrollHorz" "0"
"{2BA6A3EF-6488-11D5-80D4-00C04F68EAD7}StatusWnd1ColWidth0" "250"
"{633553C0-6FE9-11D5-B7CE-00E029352378}ProfileCtrlEnable" "0"
"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_CONTROL_REGS_CREG_CNT" "3"
"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_MEMORY_MAP_MAP10" "0x00FFEA00,0x00FFFEFF, 8, 2,I/O"
"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_MEMORY_MAP_MAP0" "0x00000000,0x0005FFFF, 8, 3,ROM"
"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_CONFIG_ROUND" "RM_NEAR"
"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegisterCtrlViews" "0"
"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_EXEC_STEP_RATE" "40000"
"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_MEMORY_RESOURCE_MEMRES3" "0x00FFFF28,0x00FFFFFF,7"
"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0ColWidth0" "200"
"{313F4FC2-6566-11D5-8BBE-0004E2013C71}MemoryCtrlDataCount0" "4"
"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegisterWndViewBInstanceKey0" "{WK_00000001_REGISTER}RTOSDemoSimulatorViewB"
"{2BA6A3EF-6488-11D5-80D4-00C04F68EAD7}StatusWnd1ColWidth1" "250"
"{48FF5DA0-6FFA-11D5-B7CE-00E029352378}CoverageCtrlViews" "0"
"{8A898260-6F1D-11D5-8EB6-00004CC34E9D}ECX_WAVE_COMB_BUFFER" ",,,,"
"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_BREAK_BREAK_SEQUENCE_COUNT" "0"
"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_MEMORY_MAP_MAP11" "0x00FFFF00,0x00FFFF1F, 8, 3,EXT"
"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_MEMORY_MAP_MAP1" "0x00FF7C00,0x00FFFBFF, 8, 3,RAM"
"{C088D861-776D-45F4-A70E-079CC28D82D5}C_REGISTER_REG_COUNT" "11"
"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_CONFIG_ENDIAN" "BIG"
"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_SYSTEM_CALL_SYSTEM_CALL_ADDRESS" "0x00000000"
"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_BREAK_PC_BREAK_COUNT" "0"
"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0ColWidth1" "100"
"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd0ECX_WATCH" "pxTCB,"
"{633553C0-6FE9-11D5-B7CE-00E029352378}ProfileCtrlViews" "0"
"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_BREAK_BREAK_ACCESS_COUNT" "0"
"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_MEMORY_MAP_MAP12" "0x00FFFF20,0x00FFFFFF, 8, 2,I/O"
"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_MEMORY_MAP_MAP2" "0x00FFFE50,0x00FFFF07, 8, 2,RAM"
"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_MEMORY_MAP_MEMORY_MAP_COUNT" "4"
"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_MEMORY_MAP_PRG_WIDTH" "24"
"{313F4FC1-6566-11D5-8BBE-0004E2013C71}CmdLineCtrlLogFileName" ""
"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_EXEC_EXEC_MODE" "STOP"
"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0ColWidth2" "100"
"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd2ScrollVert" "0"
"{B266D880-6FA1-11D5-8613-00A024591A38}WatchWnd1ColWidth0" "200"
"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegisterWndInstanceKey0" "{WK_00000001_REGISTER}RTOSDemoSimulator"
"{95A081A1-7001-11D5-B1FD-00A0C9E23A58}RegisterWnd0ScrollVert" "0"
"{EEDC9301-6FBE-11D5-8613-00A024591A38}StackTraceCtrlViews" "0"
"{48FF5DA0-6FFA-11D5-B7CE-00E029352378}CoverageCtrlViewsFromDiffFile" "0"
"{AC411480-6F0A-11D5-8EB6-00004CC34E9D}ImageCtrlViews" "0"
"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_CONTROL_REGS_CREG0" "0x00FFFF39,2,0x00000101"
"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_MEMORY_MAP_MAP3" "0x00FFFF28,0x00FFFFFF, 8, 2,RAM"
"{06B41D64-E6B9-4D0A-A48B-7552E69CF77D}T_SYSTEM_CALL_SYSTEM_CALL_ADDRESS" "0x00000000"
"{6B38B820-B4D5-11D4-A5D8-0000E2257DCD}T_CONFIG_ROUND" "RM_NEAR"
"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0ColWidth3" "100"
"{F866DB60-6186-11D5-8BBE-0004E2013C71}IOWnd0ScrollHorz" "0"
[LANGUAGE]
"English"
[CONFIG_INFO_VD1]
0
[CONFIG_INFO_VD2]
0
[CONFIG_INFO_VD3]
0
[CONFIG_INFO_VD4]
0
[WINDOW_POSITION_STATE_DATA_VD1]
"Status" "WINDOW" 59420 0 1 "-1.000000" 569 -1000 -1000 -1 -1 17 0 "" "-1"
"{WK_00000001_WATCH}" "WINDOW" 59421 -1 -1 "-1.000000" -1 -1000 -1000 -1 -1 18 0 "" "-1"
"{WK_00000001_REGISTER}RTOSDemoSimulator" "WINDOW" 59421 -1 -1 "-1.000000" -1 -1000 -1000 -1 -1 18 0 "" "-1"
"{WK_00000001_MEMORY}RTOSDemoSimulator" "WINDOW" 59421 -1 -1 "-1.000000" -1 -1000 -1000 -1 -1 18 0 "" "-1"
"{WK_00000001_SIMIO}RTOSDemoSimulator" "WINDOW" 59422 3 0 "-1.000000" 486 -1000 -1000 -1 -1 17 0 "" "-1"
"{WK_00000001_MAP}RTOSDemoSimulator" "WINDOW" 59421 -1 -1 "-1.000000" -1 -1000 -1000 -1 -1 18 0 "" "-1"
"{WK_00000001_STATUS}RTOSDemoSimulator" "WINDOW" 59422 1 0 "-1.000000" 282 -1000 -1000 -1 -1 17 0 "" "-1"
"{WK_00000001_IO}RTOSDemoSimulator" "WINDOW" 59422 2 0 "-1.000000" 180 -1000 -1000 -1 -1 17 0 "" "-1"
"{WK_00000001_REGISTER}" "WINDOW" 59421 -1 -1 "-1.000000" -1 -1000 -1000 -1 -1 18 0 "" "-1"
"{WK_00000001_WATCH}RTOSDemoSimulator" "WINDOW" 59421 -1 -1 "-1.000000" -1 -1000 -1000 -1 -1 18 0 "" "-1"
"{WK_00000001_MEMORY}" "WINDOW" 59421 -1 -1 "-1.000000" -1 -1000 -1000 -1 -1 18 0 "" "-1"
[WINDOW_POSITION_STATE_DATA_VD2]
[WINDOW_POSITION_STATE_DATA_VD3]
[WINDOW_POSITION_STATE_DATA_VD4]
[WINDOW_Z_ORDER]
[TARGET_NAME]
"H8S/2000A Simulator"
[DEBUGGER_OPTIONS]
"[S|MAP|^"0x00000000,0x0005FFFF,ROM,16,2 0x00FF7C00,0x00FFFBFF,RAM,16,2 0x00FFFE50,0x00FFFF07,I/O,16,2 0x00FFFF28,0x00FFFFFF,I/O,16,2^"] [S|RESOURCE|^"0x00000000,0x00005FFF,R 0x00FF7C00,0x00FFFBFF,R/W 0x00FFFE50,0x00FFFF07,R/W 0x00FFFF28,0x00FFFFFF,R/W^"] [B|SIMIOF|0] [I|SIMIOADR|0x00000000] [V|VERSION|] [S|ROM_MODE|^"^"]"
[DOWNLOAD_MODULES]
"$(PROJDIR)\Debug\RTOSDemo.x" 0 "Elf/Dwarf2_KPIT" 0 0 1 0
[CONNECT_ON_GO]
"TRUE"
[DOWNLOAD_MODULES_AFTER_BUILD]
"TRUE"
[REMOVE_BREAKPOINTS_ON_DOWNLOAD]
"FALSE"
[COMMAND_FILES]
[DEFAULT_DEBUG_FORMAT]
"Elf/Dwarf2_KPIT"
[FLASH_DETAILS]
"2212.000000" 1 -127 "B" 0 "COM1" 115200 1 "H8S/2329BF" 1 0 0 0 1 0 0 "D:\DevTools\Hitachi\FDT2.2\Kernels\ProtB\2329\hitachi\1_1_00\" "" "" "" ""
[BREAKPOINTS]
[END]

372
Demo/H8S/RTOSDemo/main.c Normal file
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@ -0,0 +1,372 @@
/*
FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
FreeRTOS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with FreeRTOS; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes FreeRTOS, without being obliged to provide
the source code for any proprietary components. See the licensing section
of http://www.FreeRTOS.org for full details of how and when the exception
can be applied.
***************************************************************************
See http://www.FreeRTOS.org for documentation, latest information, license
and contact details. Please ensure to read the configuration and relevant
port sections of the online documentation.
***************************************************************************
*/
/*
* Creates all the demo application tasks, then starts the scheduler. The WEB
* documentation provides more details of the demo application tasks.
*
* Main.c also creates a task called "Check". This only executes every three
* seconds but has the highest priority so is guaranteed to get processor time.
* Its main function is to check that all the other tasks are still operational.
* Each task (other than the "flash" tasks) maintains a unique count that is
* incremented each time the task successfully completes its function. Should
* any error occur within such a task the count is permanently halted. The
* check task inspects the count of each task to ensure it has changed since
* the last time the check task executed. If all the count variables have
* changed all the tasks are still executing error free, and the check task
* toggles the onboard LED. Should any task contain an error at any time
* the LED toggle rate will change from 3 seconds to 500ms.
*
* To check the operation of the memory allocator the check task also
* dynamically creates a task before delaying, and deletes it again when it
* wakes. If memory cannot be allocated for the new task the call to xTaskCreate
* will fail and an error is signalled. The dynamically created task itself
* allocates and frees memory just to give the allocator a bit more exercise.
*
*/
/* Standard includes. */
#include <stdlib.h>
#include <string.h>
/* Scheduler include files. */
#include "FreeRTOS.h"
#include "task.h"
/* Demo application file headers. */
#include "flash.h"
#include "integer.h"
#include "PollQ.h"
#include "comtest2.h"
#include "semtest.h"
#include "flop.h"
#include "dynamic.h"
#include "BlockQ.h"
#include "serial.h"
#include "partest.h"
/* Priority definitions for most of the tasks in the demo application. Some
tasks just use the idle priority. */
#define mainLED_TASK_PRIORITY ( tskIDLE_PRIORITY + 1 )
#define mainCOM_TEST_PRIORITY ( tskIDLE_PRIORITY + 2 )
#define mainQUEUE_POLL_PRIORITY ( tskIDLE_PRIORITY + 2 )
#define mainCHECK_TASK_PRIORITY ( tskIDLE_PRIORITY + 3 )
#define mainSEM_TEST_PRIORITY ( tskIDLE_PRIORITY + 1 )
#define mainBLOCK_Q_PRIORITY ( tskIDLE_PRIORITY + 2 )
/* Baud rate used by the serial port tasks (ComTest tasks). */
#define mainCOM_TEST_BAUD_RATE ( ( unsigned portLONG ) 115200 )
/* LED used by the serial port tasks. This is toggled on each character Tx,
and mainCOM_TEST_LED + 1 is toggles on each character Rx. */
#define mainCOM_TEST_LED ( 3 )
/* LED that is toggled by the check task. The check task periodically checks
that all the other tasks are operating without error. If no errors are found
the LED is toggled with mainCHECK_PERIOD frequency. If an error is found
the the toggle rate increases to mainERROR_CHECK_PERIOD. */
#define mainCHECK_TASK_LED ( 5 )
#define mainCHECK_PERIOD ( ( portTickType ) 3000 / portTICK_RATE_MS )
#define mainERROR_CHECK_PERIOD ( ( portTickType ) 500 / portTICK_RATE_MS )
/* Constants used by the vMemCheckTask() task. */
#define mainCOUNT_INITIAL_VALUE ( ( unsigned portLONG ) 0 )
#define mainNO_TASK ( 0 )
/* The size of the memory blocks allocated by the vMemCheckTask() task. */
#define mainMEM_CHECK_SIZE_1 ( ( size_t ) 51 )
#define mainMEM_CHECK_SIZE_2 ( ( size_t ) 52 )
#define mainMEM_CHECK_SIZE_3 ( ( size_t ) 151 )
/*
* The 'Check' task.
*/
static void vErrorChecks( void *pvParameters );
/*
* Checks the unique counts of other tasks to ensure they are still operational.
*/
static portLONG prvCheckOtherTasksAreStillRunning( unsigned portLONG ulMemCheckTaskCount );
/*
* Dynamically created and deleted during each cycle of the vErrorChecks()
* task. This is done to check the operation of the memory allocator.
* See the top of vErrorChecks for more details.
*/
static void vMemCheckTask( void *pvParameters );
/*-----------------------------------------------------------*/
/*
* Start all the tasks then start the scheduler.
*/
int main( void )
{
/* Setup the LED's for output. */
vParTestInitialise();
/* Start the various standard demo application tasks. */
vStartIntegerMathTasks( tskIDLE_PRIORITY );
vAltStartComTestTasks( mainCOM_TEST_PRIORITY, mainCOM_TEST_BAUD_RATE, mainCOM_TEST_LED );
vStartLEDFlashTasks( mainLED_TASK_PRIORITY );
vStartPolledQueueTasks( mainQUEUE_POLL_PRIORITY );
vStartMathTasks( tskIDLE_PRIORITY );
vStartSemaphoreTasks( mainSEM_TEST_PRIORITY );
vStartDynamicPriorityTasks();
vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );
/* Start the 'Check' task. */
xTaskCreate( vErrorChecks, ( signed portCHAR * )"Check", configMINIMAL_STACK_SIZE, NULL, mainCHECK_TASK_PRIORITY, NULL );
/* In this port, to use preemptive scheduler define configUSE_PREEMPTION
as 1 in portmacro.h. To use the cooperative scheduler define
configUSE_PREEMPTION as 0. */
vTaskStartScheduler();
/* Should never get here! */
return 0;
}
/*-----------------------------------------------------------*/
/*
* Cycle for ever, delaying then checking all the other tasks are still
* operating without error. If an error is detected then the delay period
* is decreased from mainCHECK_PERIOD to mainERROR_CHECK_PERIOD so
* the on board LED flash rate will increase.
*
* In addition to the standard tests the memory allocator is tested through
* the dynamic creation and deletion of a task each cycle. Each time the
* task is created memory must be allocated for its stack. When the task is
* deleted this memory is returned to the heap. If the task cannot be created
* then it is likely that the memory allocation failed. In addition the
* dynamically created task allocates and frees memory while it runs.
*/
static void vErrorChecks( void *pvParameters )
{
portTickType xDelayPeriod = mainCHECK_PERIOD;
volatile unsigned portLONG ulMemCheckTaskRunningCount;
xTaskHandle xCreatedTask;
portTickType xLastWakeTime;
/* Initialise xLastWakeTime to ensure the first call to vTaskDelayUntil()
functions correctly. */
xLastWakeTime = xTaskGetTickCount();
for( ;; )
{
/* Set ulMemCheckTaskRunningCount to a known value so we can check
later that it has changed. */
ulMemCheckTaskRunningCount = mainCOUNT_INITIAL_VALUE;
/* Dynamically create a task - passing ulMemCheckTaskRunningCount as a
parameter. */
xCreatedTask = mainNO_TASK;
if( xTaskCreate( vMemCheckTask, ( signed portCHAR * ) "MEM_CHECK", configMINIMAL_STACK_SIZE, ( void * ) &ulMemCheckTaskRunningCount, tskIDLE_PRIORITY, &xCreatedTask ) != pdPASS )
{
/* Could not create the task - we have probably run out of heap. */
xDelayPeriod = mainERROR_CHECK_PERIOD;
}
/* Delay until it is time to execute again. The delay period is
shorter following an error. */
vTaskDelayUntil( &xLastWakeTime, xDelayPeriod );
/* Delete the dynamically created task. */
if( xCreatedTask != mainNO_TASK )
{
vTaskDelete( xCreatedTask );
}
/* Check all the standard demo application tasks are executing without
error. ulMemCheckTaskRunningCount is checked to ensure it was
modified by the task just deleted. */
if( prvCheckOtherTasksAreStillRunning( ulMemCheckTaskRunningCount ) != pdPASS )
{
/* An error has been detected in one of the tasks - flash faster. */
xDelayPeriod = mainERROR_CHECK_PERIOD;
}
vParTestToggleLED( mainCHECK_TASK_LED );
}
}
/*-----------------------------------------------------------*/
/*
* Check each set of tasks in turn to see if they have experienced any
* error conditions.
*/
static portLONG prvCheckOtherTasksAreStillRunning( unsigned portLONG ulMemCheckTaskCount )
{
portLONG lNoErrorsDiscovered = ( portLONG ) pdTRUE;
if( xAreIntegerMathsTaskStillRunning() != pdTRUE )
{
lNoErrorsDiscovered = pdFALSE;
}
if( xAreComTestTasksStillRunning() != pdTRUE )
{
lNoErrorsDiscovered = pdFALSE;
}
if( xArePollingQueuesStillRunning() != pdTRUE )
{
lNoErrorsDiscovered = pdFALSE;
}
if( xAreMathsTaskStillRunning() != pdTRUE )
{
lNoErrorsDiscovered = pdFALSE;
}
if( xAreSemaphoreTasksStillRunning() != pdTRUE )
{
lNoErrorsDiscovered = pdFALSE;
}
if( xAreDynamicPriorityTasksStillRunning() != pdTRUE )
{
lNoErrorsDiscovered = pdFALSE;
}
if( xAreBlockingQueuesStillRunning() != pdTRUE )
{
lNoErrorsDiscovered = pdFALSE;
}
if( ulMemCheckTaskCount == mainCOUNT_INITIAL_VALUE )
{
/* The vMemCheckTask task did not increment the counter - it must
have failed. */
lNoErrorsDiscovered = pdFALSE;
}
return lNoErrorsDiscovered;
}
/*-----------------------------------------------------------*/
static void vMemCheckTask( void *pvParameters )
{
unsigned portLONG *pulMemCheckTaskRunningCounter;
void *pvMem1, *pvMem2, *pvMem3;
static portLONG lErrorOccurred = pdFALSE;
/* This task is dynamically created then deleted during each cycle of the
vErrorChecks task to check the operation of the memory allocator. Each time
the task is created memory is allocated for the stack and TCB. Each time
the task is deleted this memory is returned to the heap. This task itself
exercises the allocator by allocating and freeing blocks.
The task executes at the idle priority so does not require a delay.
pulMemCheckTaskRunningCounter is incremented each cycle to indicate to the
vErrorChecks() task that this task is still executing without error. */
pulMemCheckTaskRunningCounter = ( unsigned portLONG * ) pvParameters;
for( ;; )
{
if( lErrorOccurred == pdFALSE )
{
/* We have never seen an error so increment the counter. */
( *pulMemCheckTaskRunningCounter )++;
}
else
{
/* Reset the count so an error is detected by the
prvCheckOtherTasksAreStillRunning() function. */
*pulMemCheckTaskRunningCounter = mainCOUNT_INITIAL_VALUE;
}
/* Allocate some memory - just to give the allocator some extra
exercise. This has to be in a critical section to ensure the
task does not get deleted while it has memory allocated. */
vTaskSuspendAll();
{
pvMem1 = pvPortMalloc( mainMEM_CHECK_SIZE_1 );
if( pvMem1 == NULL )
{
lErrorOccurred = pdTRUE;
}
else
{
memset( pvMem1, 0xaa, mainMEM_CHECK_SIZE_1 );
vPortFree( pvMem1 );
}
}
xTaskResumeAll();
/* Again - with a different size block. */
vTaskSuspendAll();
{
pvMem2 = pvPortMalloc( mainMEM_CHECK_SIZE_2 );
if( pvMem2 == NULL )
{
lErrorOccurred = pdTRUE;
}
else
{
memset( pvMem2, 0xaa, mainMEM_CHECK_SIZE_2 );
vPortFree( pvMem2 );
}
}
xTaskResumeAll();
/* Again - with a different size block. */
vTaskSuspendAll();
{
pvMem3 = pvPortMalloc( mainMEM_CHECK_SIZE_3 );
if( pvMem3 == NULL )
{
lErrorOccurred = pdTRUE;
}
else
{
memset( pvMem3, 0xaa, mainMEM_CHECK_SIZE_3 );
vPortFree( pvMem3 );
}
}
xTaskResumeAll();
}
}
/*-----------------------------------------------------------*/
/*
* Called by the startup code. Initial processor setup can be placed in this
* function.
*/
void hw_initialise (void)
{
}

260
Demo/H8S/RTOSDemo/serial/serial.c Normal file
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@ -0,0 +1,260 @@
/*
FreeRTOS V4.0.1 - Copyright (C) 2003-2006 Richard Barry.
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
FreeRTOS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with FreeRTOS; if not, write to the Free Software
Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
A special exception to the GPL can be applied should you wish to distribute
a combined work that includes FreeRTOS, without being obliged to provide
the source code for any proprietary components. See the licensing section
of http://www.FreeRTOS.org for full details of how and when the exception
can be applied.
***************************************************************************
See http://www.FreeRTOS.org for documentation, latest information, license
and contact details. Please ensure to read the configuration and relevant
port sections of the online documentation.
***************************************************************************
*/
/* BASIC INTERRUPT DRIVEN SERIAL PORT DRIVER for port 1.
Note that this driver is written to test the RTOS port and is not intended
to represent an optimised solution. In particular no use is made of the DMA
peripheral. */
/* Standard include files. */
#include <stdlib.h>
/* Scheduler include files. */
#include "FreeRTOS.h"
#include "queue.h"
#include "task.h"
/* Demo application include files. */
#include "serial.h"
/* The queues used to communicate between the task code and the interrupt
service routines. */
static xQueueHandle xRxedChars;
static xQueueHandle xCharsForTx;
/* Hardware specific constants. */
#define serTX_INTERRUPT ( ( unsigned portCHAR ) 0x80 )
#define serRX_INTERRUPT ( ( unsigned portCHAR ) 0x40 )
#define serTX_ENABLE ( ( unsigned portCHAR ) 0x20 )
#define serRX_ENABLE ( ( unsigned portCHAR ) 0x10 )
/* Macros to turn on and off the serial port THRE interrupt while leaving the
other register bits in their correct state. The Rx interrupt is always
enabled. */
#define serTX_INTERRUPT_ON() SCR1 = serTX_INTERRUPT | serRX_INTERRUPT | serTX_ENABLE | serRX_ENABLE;
#define serTX_INTERRUPT_OFF() SCR1 = serRX_INTERRUPT | serTX_ENABLE | serRX_ENABLE;
/* Bit used to switch on the channel 1 serial port in the module stop
register. */
#define serMSTP6 ( ( unsigned portSHORT ) 0x0040 )
/* Interrupt service routines. Note that the Rx and Tx service routines can
cause a context switch and are therefore defined with the saveall attribute in
addition to the interrupt_handler attribute. See the FreeRTOS.org WEB site
documentation for a full explanation.*/
void vCOM_1_Rx_ISR( void ) __attribute__ ( ( saveall, interrupt_handler ) );
void vCOM_1_Tx_ISR( void ) __attribute__ ( ( saveall, interrupt_handler ) );
void vCOM_1_Error_ISR( void ) __attribute__ ( ( interrupt_handler ) );
/*-----------------------------------------------------------*/
/*
* Initialise port 1 for interrupt driven communications.
*/
xComPortHandle xSerialPortInitMinimal( unsigned portLONG ulWantedBaud, unsigned portBASE_TYPE uxQueueLength )
{
/* Create the queues used to communicate between the tasks and the
interrupt service routines. */
xRxedChars = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );
xCharsForTx = xQueueCreate( uxQueueLength, ( unsigned portBASE_TYPE ) sizeof( signed portCHAR ) );
/* No parity, 8 data bits and 1 stop bit is the default so does not require
configuration - setup the remains of the hardware. */
portENTER_CRITICAL();
{
/* Turn channel 1 on. */
MSTPCR &= ~serMSTP6;
/* Enable the channels and the Rx interrupt. The Tx interrupt is only
enabled when data is being transmitted. */
SCR1 = serRX_INTERRUPT | serTX_ENABLE | serRX_ENABLE;
/* Bit rate settings for 22.1184MHz clock only!. */
switch( ulWantedBaud )
{
case 4800 : BRR1 = 143;
break;
case 9600 : BRR1 = 71;
break;
case 19200 : BRR1 = 35;
break;
case 38400 : BRR1 = 17;
break;
case 57600 : BRR1 = 11;
break;
case 115200 : BRR1 = 5;
break;
default : BRR1 = 5;
break;
}
}
portEXIT_CRITICAL();
/* Unlike some ports, this driver code does not allow for more than one
com port. We therefore don't return a pointer to a port structure and can
instead just return NULL. */
return NULL;
}
/*-----------------------------------------------------------*/
signed portBASE_TYPE xSerialGetChar( xComPortHandle pxPort, signed portCHAR *pcRxedChar, portTickType xBlockTime )
{
/* Get the next character from the buffer queue. Return false if no characters
are available, or arrive before xBlockTime expires. */
if( xQueueReceive( xRxedChars, pcRxedChar, xBlockTime ) )
{
return pdTRUE;
}
else
{
return pdFALSE;
}
}
/*-----------------------------------------------------------*/
signed portBASE_TYPE xSerialPutChar( xComPortHandle pxPort, signed portCHAR cOutChar, portTickType xBlockTime )
{
signed portBASE_TYPE xReturn = pdPASS;
/* Return false if after the block time there is no room on the Tx queue. */
portENTER_CRITICAL();
{
/* Send a character to the queue of characters waiting transmission.
The queue is serviced by the Tx ISR. */
if( xQueueSend( xCharsForTx, &cOutChar, xBlockTime ) != pdPASS )
{
/* Could not post onto the queue. */
xReturn = pdFAIL;
}
else
{
/* The message was posted onto the queue so we turn on the Tx
interrupt to allow the Tx ISR to remove the character from the
queue. */
serTX_INTERRUPT_ON();
}
}
portEXIT_CRITICAL();
return xReturn;
}
/*-----------------------------------------------------------*/
void vSerialClose( xComPortHandle xPort )
{
/* Not supported. */
( void ) xPort;
}
/*-----------------------------------------------------------*/
void vCOM_1_Rx_ISR( void )
{
/* This can cause a context switch so this macro must be the first line
in the function. */
portENTER_SWITCHING_ISR();
/* As this is a switching ISR the local variables must be declared as
static. */
static portCHAR cRxByte;
static portBASE_TYPE xTaskWokenByPost;
/* Get the character. */
cRxByte = RDR1;
/* Post the character onto the queue of received characters - noting
whether or not this wakes a task. */
xTaskWokenByPost = xQueueSendFromISR( xRxedChars, &cRxByte, pdFALSE );
/* Clear the interrupt. */
SSR1 &= ~serRX_INTERRUPT;
/* This must be the last line in the function. We pass cTaskWokenByPost so
a context switch will occur if the received character woke a task that has
a priority higher than the task we interrupted. */
portEXIT_SWITCHING_ISR( xTaskWokenByPost );
}
/*-----------------------------------------------------------*/
void vCOM_1_Tx_ISR( void )
{
/* This can cause a context switch so this macro must be the first line
in the function. */
portENTER_SWITCHING_ISR();
/* As this is a switching ISR the local variables must be declared as
static. */
static portCHAR cTxByte;
static signed portBASE_TYPE xTaskWokenByTx;
/* This variable is static so must be explicitly reinitialised each
time the function executes. */
xTaskWokenByTx = pdFALSE;
/* The interrupt was caused by the THR becoming empty. Are there any
more characters to transmit? Note whether or not the Tx interrupt has
woken a task. */
if( xQueueReceiveFromISR( xCharsForTx, &cTxByte, &xTaskWokenByTx ) == pdTRUE )
{
/* A character was retrieved from the queue so can be sent to the
THR now. */
TDR1 = cTxByte;
/* Clear the interrupt. */
SSR1 &= ~serTX_INTERRUPT;
}
else
{
/* Queue empty, nothing to send so turn off the Tx interrupt. */
serTX_INTERRUPT_OFF();
}
/* This must be the last line in the function. We pass cTaskWokenByTx so
a context switch will occur if the Tx'ed character woke a task that has
a priority higher than the task we interrupted. */
portEXIT_SWITCHING_ISR( xTaskWokenByTx );
}
/*-----------------------------------------------------------*/
/*
* This ISR cannot cause a context switch so requires no special
* considerations.
*/
void vCOM_1_Error_ISR( void )
{
volatile unsigned portCHAR ucIn;
ucIn = SSR1;
SSR1 = 0;
}

115
Demo/H8S/RTOSDemo/start.asm Normal file
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;/****************************************************************
;KPIT Cummins Infosystems Ltd, Pune, India. - 4th September 2003.
;
;This program is distributed in the hope that it will be useful,
;but WITHOUT ANY WARRANTY; without even the implied warranty of
;MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE
;
;*****************************************************************/
;*********************************************************************
; File: start.asm
;
;
; desc:
;
; System initialisation routine - entry point for the application.
; The stack pointer is initialised, then the hardware initialisation
; routine called. The static data areas are then initialised, before
; the main function is executed. A simple exit funtion is also
; supplied
;
;*********************************************************************
#ifdef __H8300H__
#ifdef __NORMAL_MODE__
.h8300hn
#else
.h8300h
#endif
#endif /*_H8300H_ */
#ifdef __H8300S__
#ifdef __NORMAL_MODE__
.h8300sn
#else
.h8300s
#endif
#endif /* __H8300S__ */
.section .text
.global _start
#if DEBUG
.extern _exit
#endif
.extern _hw_initialise
.extern _main
.extern _data
.extern _mdata
.extern _edata
.extern _bss
.extern _ebss
.extern _stack
_start:
; initialise the SP for non-vectored code
mov.l #_stack,er7
; call the hardware initialiser
jsr @_hw_initialise
#ifdef ROMSTART
; get the boundaries for the .data section initialisation
mov.l #_data,er0
mov.l #_edata,er1
mov.l #_mdata,er2
cmp.l er0,er1
beq start_1
start_l:
mov.b @er2,r3l ;get from src
mov.b r3l,@er0 ;place in dest
inc.l #1,er2 ;inc src
inc.l #1,er0 ;inc dest
cmp.l er0,er1 ;dest == edata?
bne start_l
start_1:
#endif //ROMSTART
; zero out bss
mov.l #_bss,er0
mov.l #_ebss,er1
cmp.l er0,er1
beq start_3
sub.b r2l,r2l
start_2:
mov.b r2l,@er0
inc.l #1,er0
cmp.l er0,er1
bne start_2
start_3:
#ifdef CPPAPP
;Initialize global constructor
jsr @___main
#endif
; call the mainline
jsr @_main
mov.l er0,er4
;call to exit
#if DEBUG
jsr @_exit
#endif
#if RELEASE
exit:
bra exit
#endif

137
Demo/H8S/RTOSDemo/vects.c Normal file
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@ -0,0 +1,137 @@
/****************************************************************
KPIT Cummins Infosystems Ltd, Pune, India. - 19-June-2003.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
*****************************************************************/
void start(void); /* Startup code (in start.asm) */
/*
* Manual context switch trap function.
*/
void vPortYield( void );
/*
* The RTOS tick ISR.
*/
void vTickISR( void );
/*
* Serial port ISR functions.
*/
void vCOM_1_Rx_ISR( void );
void vCOM_1_Tx_ISR( void );
void vCOM_1_Error_ISR( void );
typedef void (*fp) (void);
#define VECT_SECT __attribute__ ((section (".vects")))
const fp HardwareVectors[] VECT_SECT = {
start, /* vector 0 */
(fp)(0), /* vector 1 */
(fp)(0), /* vector 2 */
(fp)(0), /* vector 3 */
(fp)(0), /* vector 4 */
(fp)(0), /* vector 5 */
(fp)(0), /* vector 6 */
(fp)(0), /* vector 7 */
vPortYield, /* vector 8 */
(fp)(0), /* vector 9 */
(fp)(0), /* vector 10 */
(fp)(0), /* vector 11 */
(fp)(0), /* vector 12 */
(fp)(0), /* vector 13 */
(fp)(0), /* vector 14 */
(fp)(0), /* vector 15 */
(fp)(0), /* vector 16 */
(fp)(0), /* vector 17 */
(fp)(0), /* vector 18 */
(fp)(0), /* vector 19 */
(fp)(0), /* vector 20 */
(fp)(0), /* vector 21 */
(fp)(0), /* vector 22 */
(fp)(0), /* vector 23 */
(fp)(0), /* vector 24 */
(fp)(0), /* vector 25 */
(fp)(0), /* vector 26 */
(fp)(0), /* vector 27 */
(fp)(0), /* vector 28 */
(fp)(0), /* vector 29 */
(fp)(0), /* vector 30 */
(fp)(0), /* vector 31 */
(fp)(0), /* vector 32 */
(fp)(0), /* vector 33 */
(fp)(0), /* vector 34 */
(fp)(0), /* vector 35 */
(fp)(0), /* vector 36 */
(fp)(0), /* vector 37 */
(fp)(0), /* vector 38 */
(fp)(0), /* vector 39 */
vTickISR, /* vector 40 */
(fp)(0), /* vector 41 */
(fp)(0), /* vector 42 */
(fp)(0), /* vector 43 */
(fp)(0), /* vector 44 */
(fp)(0), /* vector 45 */
(fp)(0), /* vector 46 */
(fp)(0), /* vector 47 */
(fp)(0), /* vector 48 */
(fp)(0), /* vector 49 */
(fp)(0), /* vector 50 */
(fp)(0), /* vector 51 */
(fp)(0), /* vector 52 */
(fp)(0), /* vector 53 */
(fp)(0), /* vector 54 */
(fp)(0), /* vector 55 */
(fp)(0), /* vector 56 */
(fp)(0), /* vector 57 */
(fp)(0), /* vector 58 */
(fp)(0), /* vector 59 */
(fp)(0), /* vector 60 */
(fp)(0), /* vector 61 */
(fp)(0), /* vector 62 */
(fp)(0), /* vector 63 */
(fp)(0), /* vector 64 */
(fp)(0), /* vector 65 */
(fp)(0), /* vector 66 */
(fp)(0), /* vector 67 */
(fp)(0), /* vector 68 */
(fp)(0), /* vector 69 */
(fp)(0), /* vector 70 */
(fp)(0), /* vector 71 */
(fp)(0), /* vector 72 */
(fp)(0), /* vector 73 */
(fp)(0), /* vector 74 */
(fp)(0), /* vector 75 */
(fp)(0), /* vector 76 */
(fp)(0), /* vector 77 */
(fp)(0), /* vector 78 */
(fp)(0), /* vector 79 */
(fp)(0), /* vector 80 */
(fp)(0), /* vector 81 */
(fp)(0), /* vector 82 */
(fp)(0), /* vector 83 */
vCOM_1_Error_ISR, /* vector 84 */
vCOM_1_Rx_ISR, /* vector 85 */
vCOM_1_Tx_ISR, /* vector 86 */
(fp)(0), /* vector 87 */
(fp)(0), /* vector 88 */
(fp)(0), /* vector 89 */
(fp)(0), /* vector 90 */
(fp)(0), /* vector 91 */
(fp)(0), /* vector 92 */
(fp)(0), /* vector 93 */
(fp)(0), /* vector 94 */
(fp)(0), /* vector 95 */
(fp)(0), /* vector 96 */
(fp)(0), /* vector 97 */
(fp)(0), /* vector 98 */
(fp)(0), /* vector 99 */
(fp)(0), /* vector 100 */
(fp)(0), /* vector 101 */
(fp)(0), /* vector 102 */
(fp)(0) /* vector 103 */
};