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First version under SVN is V4.0.1
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Richard Barry
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212
Demo/ARM7_STR71x_IAR/cstartup.s79
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212
Demo/ARM7_STR71x_IAR/cstartup.s79
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;-----------------------------------------------------------------------------
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; This file contains the startup code used by the ICCARM C compiler.
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;
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; The modules in this file are included in the libraries, and may be replaced
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; by any user-defined modules that define the PUBLIC symbol _program_start or
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; a user defined start symbol.
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; To override the cstartup defined in the library, simply add your modified
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; version to the workbench project.
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;
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; All code in the modules (except ?RESET) will be placed in the ICODE segment.
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;
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; $Revision: 1.1 $
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;
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;-----------------------------------------------------------------------------
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;
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; Naming covention of labels in this file:
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;
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; ?xxx - External labels only accessed from assembler.
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; __xxx - External labels accessed from or defined in C.
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; xxx - Labels local to one module (note: this file contains
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; several modules).
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; main - The starting point of the user program.
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;
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;---------------------------------------------------------------
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; Macros and definitions for the whole file
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;---------------------------------------------------------------
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; --- Standard definitions of mode bits and interrupt (I & F) flags in PSRs
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Mode_USR DEFINE 0x10
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Mode_FIQ DEFINE 0x11
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Mode_IRQ DEFINE 0x12
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Mode_SVC DEFINE 0x13
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Mode_ABT DEFINE 0x17
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Mode_UNDEF DEFINE 0x1B
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Mode_SYS DEFINE 0x1F ; available on ARM Arch 4 and later
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I_Bit DEFINE 0x80 ; when I bit is set, IRQ is disabled
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F_Bit DEFINE 0x40 ; when F bit is set, FIQ is disabled
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; --- System memory locations
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RAM_Base DEFINE 0x20000000
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RAM_Limit DEFINE 0x20010000
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SRAM_Base DEFINE 0x60000000
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SVC_Stack DEFINE RAM_Limit ; 512 byte SVC stack at
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; top of memory - used by kernel.
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IRQ_Stack DEFINE SVC_Stack-512 ; followed by IRQ stack
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USR_Stack DEFINE IRQ_Stack-512 ; followed by USR stack. Tasks run in
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; system mode but task stacks are allocated
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; when the task is created.
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FIQ_Stack DEFINE USR_Stack-8 ; followed by FIQ stack
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ABT_Stack DEFINE FIQ_Stack-8 ; followed by ABT stack
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UNDEF_Stack DEFINE ABT_Stack-8 ; followed by UNDEF stack
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EIC_Base_addr DEFINE 0xFFFFF800 ; EIC base address
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ICR_off_addr DEFINE 0x00 ; Interrupt Control register offset
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CIPR_off_addr DEFINE 0x08 ; Current Interrupt Priority Register offset
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IVR_off_addr DEFINE 0x18 ; Interrupt Vector Register offset
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FIR_off_addr DEFINE 0x1C ; Fast Interrupt Register offset
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IER_off_addr DEFINE 0x20 ; Interrupt Enable Register offset
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IPR_off_addr DEFINE 0x40 ; Interrupt Pending Bit Register offset
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SIR0_off_addr DEFINE 0x60 ; Source Interrupt Register 0
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EMI_Base_addr DEFINE 0x6C000000 ; EMI base address
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BCON0_off_addr DEFINE 0x00 ; Bank 0 configuration register offset
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BCON1_off_addr DEFINE 0x04 ; Bank 1 configuration register offset
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BCON2_off_addr DEFINE 0x08 ; Bank 2 configuration register offset
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BCON3_off_addr DEFINE 0x0C ; Bank 3 configuration register offset
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GPIO2_Base_addr DEFINE 0xE0005000 ; GPIO2 base address
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PC0_off_addr DEFINE 0x00 ; Port Configuration Register 0 offset
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PC1_off_addr DEFINE 0x04 ; Port Configuration Register 1 offset
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PC2_off_addr DEFINE 0x08 ; Port Configuration Register 2 offset
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PD_off_addr DEFINE 0x0C ; Port Data Register offset
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CPM_Base_addr DEFINE 0xA0000040 ; CPM Base Address
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BOOTCONF_off_addr DEFINE 0x10 ; CPM - Boot Configuration Register
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FLASH_mask DEFINE 0x0000 ; to remap FLASH at 0x0
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RAM_mask DEFINE 0x0002 ; to remap RAM at 0x0
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EXTMEM_mask DEFINE 0x0003 ; to remap EXTMEM at 0x0
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;---------------------------------------------------------------
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; ?RESET
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; Reset Vector.
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; Normally, segment INTVEC is linked at address 0.
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; For debugging purposes, INTVEC may be placed at other
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; addresses.
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; A debugger that honors the entry point will start the
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; program in a normal way even if INTVEC is not at address 0.
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;---------------------------------------------------------------
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MODULE ?RESET
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COMMON INTVEC:CODE:NOROOT(2)
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PUBLIC __program_start
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EXTERN ?cstartup
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CODE32 ; Always ARM mode after reset
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__program_start
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ldr pc,=?cstartup ; Absolute jump can reach 4 GByte
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b ?cstartup ; Relative branch allows remap, limited to 32 MByte
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LTORG
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ENDMOD
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;---------------------------------------------------------------
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; ?CSTARTUP
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;---------------------------------------------------------------
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MODULE ?CSTARTUP
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; RSEG IRQ_STACK:DATA(2)
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; RSEG SVC_STACK:DATA:NOROOT(2)
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; RSEG CSTACK:DATA(2)
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RSEG ICODE:CODE:NOROOT(2)
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PUBLIC ?cstartup
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EXTERN ?main
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CODE32
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?cstartup
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NOP ; Wait for OSC stabilization
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP
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NOP
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/* Setup a stack for each mode - note that this only sets up a usable stack
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for system/user, SWI and IRQ modes. Also each mode is setup with
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interrupts initially disabled. */
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msr CPSR_c, #Mode_UNDEF|I_Bit|F_Bit /* Undefined Instruction Mode */
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LDR SP, =UNDEF_Stack
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msr CPSR_c, #Mode_ABT|I_Bit|F_Bit /* Abort Mode */
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LDR SP, =ABT_Stack
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msr CPSR_c, #Mode_FIQ|I_Bit|F_Bit /* FIQ Mode */
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LDR SP, =FIQ_Stack
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msr CPSR_c, #Mode_IRQ|I_Bit|F_Bit /* IRQ Mode */
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LDR SP, =IRQ_Stack
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msr CPSR_c, #Mode_SVC|I_Bit|F_Bit /* Supervisor Mode */
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LDR SP, =SVC_Stack
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msr CPSR_c, #Mode_SYS|I_Bit|F_Bit /* System Mode */
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LDR SP, =USR_Stack
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/* We want to start in supervisor mode. Operation will switch to system
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mode when the first task starts. */
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msr CPSR_c, #Mode_SVC|I_Bit|F_Bit
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IMPORT T0TIMI_Addr
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EIC_INIT
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LDR r3, =EIC_Base_addr
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LDR r4, =0x00000000
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STR r4, [r3, #ICR_off_addr] ; Disable FIQ and IRQ
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STR r4, [r3, #IER_off_addr] ; Disable all channels interrupts
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LDR r4, =0xFFFFFFFF
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STR r4, [r3, #IPR_off_addr] ; Clear all IRQ pending bits
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LDR r4, =0x0C
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STR r4, [r3, #FIR_off_addr] ; Disable FIQ channels and clear FIQ pending bits
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LDR r4, =0x00000000
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STR r4, [r3, #CIPR_off_addr] ; Reset the current priority register
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LDR r4, =0xE59F0000
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STR r4, [r3, #IVR_off_addr] ; Write the LDR pc,pc,#offset instruction code in IVR[31:16]
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LDR r2, =32 ; 32 Channel to initialize
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LDR r0, =T0TIMI_Addr ; Read the address of the IRQs address table
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LDR r1, =0x00000FFF
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AND r0,r0,r1
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LDR r5, =SIR0_off_addr ; Read SIR0 address
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SUB r4,r0,#8 ; subtract 8 for prefetch
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LDR r1, =0xF7E8 ; add the offset to the 0x00000000 address(IVR address + 7E8 = 0x00000000)
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; 0xF7E8 used to complete the LDR pc,pc,#offset opcode
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ADD r1,r4,r1 ; compute the jump offset
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EIC_INI MOV r4, r1, LSL #16 ; Left shift the result
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STR r4, [r3, r5] ; Store the result in SIRx register
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ADD r1, r1, #4 ; Next IRQ address
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ADD r5, r5, #4 ; Next SIR
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SUBS r2, r2, #1 ; Decrement the number of SIR registers to initialize
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BNE EIC_INI ; If more then continue
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ldr r0,=?main
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bx r0
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LTORG
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ENDMOD
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END
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