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First version under SVN is V4.0.1
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Richard Barry
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211
Demo/ARM7_AT91SAM7S64_IAR/resource/SAM7_RAM.mac
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211
Demo/ARM7_AT91SAM7S64_IAR/resource/SAM7_RAM.mac
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// ---------------------------------------------------------
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// ATMEL Microcontroller Software Support - ROUSSET -
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// ---------------------------------------------------------
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// The software is delivered "AS IS" without warranty or
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// condition of any kind, either express, implied or
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// statutory. This includes without limitation any warranty
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// or condition with respect to merchantability or fitness
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// for any particular purpose, or against the infringements of
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// intellectual property rights of others.
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// ---------------------------------------------------------
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// File: SAM7_RAM.mac
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//
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// User setup file for CSPY debugger to simulate interrupt
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// driven Fibonacchi data input.
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// 1.1 16/Jun/04 JPP : Creation
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// 1.2 27/Aug/04 JPP : PLL setting
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//
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// $Revision: 1.3 $
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//
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// ---------------------------------------------------------
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__var i;
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__var pt;
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execUserPreload()
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{
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//*
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PllSetting();
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//* Set the RAM memory at 0x0020 0000 for code AT 0 flash area
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CheckNoRemap();
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//* Get the Chip ID (AT91C_DBGU_C1R & AT91C_DBGU_C2R
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i=__readMemory32(0xFFFFF240,"Memory");
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__message " ---------------------------------------- Chip ID 0x",i:%X;
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i=__readMemory32(0xFFFFF244,"Memory");
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__message " ---------------------------------------- Extention 0x",i:%X;
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i=__readMemory32(0xFFFFFF6C,"Memory");
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__message " ---------------------------------------- Flash Version 0x",i:%X;
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//* Get the chip status
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//* Init AIC
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AIC();
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//* Watchdog Disable
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Watchdog();
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}
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//-----------------------------------------------------------------------------
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// PllSetting
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//-------------------------------
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// Set PLL
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//-----------------------------------------------------------------------------
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PllSetting()
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{
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// -1- Enabling the Main Oscillator:
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//*#define AT91C_PMC_MOR ((AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register
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//*#define AT91C_PMC_PLLR ((AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register
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//*#define AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register
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//*pPMC->PMC_MOR = (( AT91C_CKGR_OSCOUNT & (0x06 <<8) | //0x0000 0600
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// AT91C_CKGR_MOSCEN )); //0x0000 0001
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__writeMemory32(0x00000601,0xFFFFFC20,"Memory");
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// -2- Wait
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// -3- Setting PLL and divider:
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// - div by 5 Fin = 3,6864 =(18,432 / 5)
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// - Mul 25+1: Fout = 95,8464 =(3,6864 *26)
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// for 96 MHz the erroe is 0.16%
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// Field out NOT USED = 0
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// PLLCOUNT pll startup time esrtimate at : 0.844 ms
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// PLLCOUNT 28 = 0.000844 /(1/32768)
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// pPMC->PMC_PLLR = ((AT91C_CKGR_DIV & 0x05) | //0x0000 0005
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// (AT91C_CKGR_PLLCOUNT & (28<<8)) //0x0000 1C00
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// (AT91C_CKGR_MUL & (25<<16))); //0x0019 0000
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__writeMemory32(0x00191C05,0xFFFFFC2C,"Memory");
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// -2- Wait
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// -5- Selection of Master Clock and Processor Clock
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// select the PLL clock divided by 2
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// pPMC->PMC_MCKR = AT91C_PMC_CSS_PLL_CLK | //0x0000 0003
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// AT91C_PMC_PRES_CLK_2 ; //0x0000 0004
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__writeMemory32(0x00000007,0xFFFFFC30,"Memory");
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__message "------------------------------- PLL Enable ----------------------------------------";
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}
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//-----------------------------------------------------------------------------
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// Watchdog
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//-------------------------------
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// Normally, the Watchdog is enable at the reset for load it's preferable to
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// Disable.
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//-----------------------------------------------------------------------------
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Watchdog()
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{
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//* Watchdog Disable
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// AT91C_BASE_WDTC->WDTC_WDMR= AT91C_SYSC_WDDIS;
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__writeMemory32(0x00008000,0xFFFFFD44,"Memory");
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__message "------------------------------- Watchdog Disable ----------------------------------------";
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}
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CheckNoRemap()
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{
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//* Read the value at 0x0
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i=__readMemory32(0x00000000,"Memory");
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i=i+1;
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__writeMemory32(i,0x00,"Memory");
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pt=__readMemory32(0x00000000,"Memory");
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if (i == pt)
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{
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__message "------------------------------- The Remap is done ----------------------------------------";
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} else {
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__message "------------------------------- The Remap is NOT -----------------------------------------";
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//* Toggel RESET The remap
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__writeMemory32(0x00000001,0xFFFFFF00,"Memory");
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}
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}
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execUserSetup()
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{
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ini();
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__message "-------------------------------Set PC ----------------------------------------";
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__writeMemory32(0x00000000,0xB4,"Register");
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}
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//-----------------------------------------------------------------------------
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// Reset the Interrupt Controller
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//-------------------------------
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// Normally, the code is executed only if a reset has been actually performed.
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// So, the AIC initialization resumes at setting up the default vectors.
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//-----------------------------------------------------------------------------
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AIC()
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{
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// Mask All interrupt pAic->AIC_IDCR = 0xFFFFFFFF;
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__writeMemory32(0xFFFFFFFF,0xFFFFF124,"Memory");
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for (i=0;i < 8; i++)
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{
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// AT91C_BASE_AIC->AIC_EOICR
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pt = __readMemory32(0xFFFFF130,"Memory");
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}
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__message "------------------------------- AIC INIT ---------------------------------------------";
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}
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ini()
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{
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__writeMemory32(0x0,0x00,"Register");
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__writeMemory32(0x0,0x04,"Register");
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__writeMemory32(0x0,0x08,"Register");
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__writeMemory32(0x0,0x0C,"Register");
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__writeMemory32(0x0,0x10,"Register");
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__writeMemory32(0x0,0x14,"Register");
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__writeMemory32(0x0,0x18,"Register");
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__writeMemory32(0x0,0x1C,"Register");
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__writeMemory32(0x0,0x20,"Register");
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__writeMemory32(0x0,0x24,"Register");
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__writeMemory32(0x0,0x28,"Register");
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__writeMemory32(0x0,0x2C,"Register");
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__writeMemory32(0x0,0x30,"Register");
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__writeMemory32(0x0,0x34,"Register");
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__writeMemory32(0x0,0x38,"Register");
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// Set CPSR
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__writeMemory32(0x0D3,0x98,"Register");
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}
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RG()
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{
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i=__readMemory32(0x00,"Register"); __message "R00 0x",i:%X;
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i=__readMemory32(0x04,"Register"); __message "R01 0x",i:%X;
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i=__readMemory32(0x08,"Register"); __message "R02 0x",i:%X;
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i=__readMemory32(0x0C,"Register"); __message "R03 0x",i:%X;
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i=__readMemory32(0x10,"Register"); __message "R04 0x",i:%X;
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i=__readMemory32(0x14,"Register"); __message "R05 0x",i:%X;
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i=__readMemory32(0x18,"Register"); __message "R06 0x",i:%X;
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i=__readMemory32(0x1C,"Register"); __message "R07 0x",i:%X;
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i=__readMemory32(0x20,"Register"); __message "R08 0x",i:%X;
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i=__readMemory32(0x24,"Register"); __message "R09 0x",i:%X;
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i=__readMemory32(0x28,"Register"); __message "R10 0x",i:%X;
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i=__readMemory32(0x2C,"Register"); __message "R11 0x",i:%X;
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i=__readMemory32(0x30,"Register"); __message "R12 0x",i:%X;
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i=__readMemory32(0x34,"Register"); __message "R13 0x",i:%X;
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i=__readMemory32(0x38,"Register"); __message "R14 0x",i:%X;
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i=__readMemory32(0x3C,"Register"); __message "R13 SVC 0x",i:%X;
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i=__readMemory32(0x40,"Register"); __message "R14 SVC 0x",i:%X;
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i=__readMemory32(0x44,"Register"); __message "R13 ABT 0x",i:%X;
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i=__readMemory32(0x48,"Register"); __message "R14 ABT 0x",i:%X;
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i=__readMemory32(0x4C,"Register"); __message "R13 UND 0x",i:%X;
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i=__readMemory32(0x50,"Register"); __message "R14 UND 0x",i:%X;
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i=__readMemory32(0x54,"Register"); __message "R13 IRQ 0x",i:%X;
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i=__readMemory32(0x58,"Register"); __message "R14 IRQ 0x",i:%X;
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i=__readMemory32(0x5C,"Register"); __message "R08 FIQ 0x",i:%X;
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i=__readMemory32(0x60,"Register"); __message "R09 FIQ 0x",i:%X;
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i=__readMemory32(0x64,"Register"); __message "R10 FIQ 0x",i:%X;
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i=__readMemory32(0x68,"Register"); __message "R11 FIQ 0x",i:%X;
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i=__readMemory32(0x6C,"Register"); __message "R12 FIQ 0x",i:%X;
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i=__readMemory32(0x70,"Register"); __message "R13 FIQ 0x",i:%X;
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i=__readMemory32(0x74,"Register"); __message "R14 FIQ0x",i:%X;
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i=__readMemory32(0x98,"Register"); __message "CPSR ",i:%X;
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i=__readMemory32(0x94,"Register"); __message "SPSR ",i:%X;
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i=__readMemory32(0x9C,"Register"); __message "SPSR ABT ",i:%X;
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i=__readMemory32(0xA0,"Register"); __message "SPSR ABT ",i:%X;
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i=__readMemory32(0xA4,"Register"); __message "SPSR UND ",i:%X;
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i=__readMemory32(0xA8,"Register"); __message "SPSR IRQ ",i:%X;
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i=__readMemory32(0xAC,"Register"); __message "SPSR FIQ ",i:%X;
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i=__readMemory32(0xB4,"Register"); __message "PC 0x",i:%X;
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}
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