mirror of
https://github.com/FreeRTOS/FreeRTOS-Kernel.git
synced 2025-08-19 17:48:33 -04:00
First version under SVN is V4.0.1
This commit is contained in:
Richard Barry
parent
243393860c
commit
b6df57c7e3
918 changed files with 269038 additions and 0 deletions
180
Demo/ARM7_AT91SAM7S64_IAR/resource/SAM7.mac
Normal file
180
Demo/ARM7_AT91SAM7S64_IAR/resource/SAM7.mac
Normal file
|
|
@ -0,0 +1,180 @@
|
|||
// ---------------------------------------------------------
|
||||
// ATMEL Microcontroller Software Support - ROUSSET -
|
||||
// ---------------------------------------------------------
|
||||
// The software is delivered "AS IS" without warranty or
|
||||
// condition of any kind, either express, implied or
|
||||
// statutory. This includes without limitation any warranty
|
||||
// or condition with respect to merchantability or fitness
|
||||
// for any particular purpose, or against the infringements of
|
||||
// intellectual property rights of others.
|
||||
// ---------------------------------------------------------
|
||||
// File: SAM7.mac
|
||||
//
|
||||
// User setup file for CSPY debugger to simulate interrupt
|
||||
// driven Fibonacchi data input.
|
||||
// 1.1 16/Jun/04 JPP : Creation
|
||||
//
|
||||
// $Revision: 1.3 $
|
||||
//
|
||||
// ---------------------------------------------------------
|
||||
|
||||
__var i;
|
||||
__var pt;
|
||||
|
||||
execUserPreload()
|
||||
{
|
||||
//* Set the RAM memory at 0x0020 0000 for code AT 0 flash area
|
||||
CheckRemap();
|
||||
//* Get the Chip ID (AT91C_DBGU_C1R & AT91C_DBGU_C2R
|
||||
i=__readMemory32(0xFFFFF240,"Memory");
|
||||
__message " ---------------------------------------- Chip ID 0x",i:%X;
|
||||
i=__readMemory32(0xFFFFF244,"Memory");
|
||||
__message " ---------------------------------------- Extention 0x",i:%X;
|
||||
//* Get the chip status
|
||||
|
||||
//* Init AIC
|
||||
AIC();
|
||||
//* Watchdog Disable
|
||||
Watchdog();
|
||||
|
||||
}
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
// Watchdog
|
||||
//-------------------------------
|
||||
// Normally, the Watchdog is enable at the reset for load it's preferable to
|
||||
// Disable.
|
||||
//-----------------------------------------------------------------------------
|
||||
Watchdog()
|
||||
{
|
||||
//* Watchdog Disable
|
||||
// AT91C_BASE_WDTC->WDTC_WDMR= AT91C_SYSC_WDDIS;
|
||||
__writeMemory32(0x00008000,0xFFFFFD44,"Memory");
|
||||
__message "------------------------------- Watchdog Disable ----------------------------------------";
|
||||
}
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
// Check Remap
|
||||
//-------------
|
||||
//-----------------------------------------------------------------------------
|
||||
CheckRemap()
|
||||
{
|
||||
//* Read the value at 0x0
|
||||
i=__readMemory32(0x00000000,"Memory");
|
||||
i=i+1;
|
||||
__writeMemory32(i,0x00,"Memory");
|
||||
pt=__readMemory32(0x00000000,"Memory");
|
||||
|
||||
if (i == pt)
|
||||
{
|
||||
__message "------------------------------- The Remap is done ----------------------------------------";
|
||||
//* Toggel RESET The remap
|
||||
__writeMemory32(0x00000001,0xFFFFFF00,"Memory");
|
||||
|
||||
} else {
|
||||
__message "------------------------------- The Remap is NOT -----------------------------------------";
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
||||
execUserSetup()
|
||||
{
|
||||
ini();
|
||||
__message "-------------------------------Set PC ----------------------------------------";
|
||||
__writeMemory32(0x00000000,0xB4,"Register");
|
||||
}
|
||||
|
||||
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
// Reset the Interrupt Controller
|
||||
//-------------------------------
|
||||
// Normally, the code is executed only if a reset has been actually performed.
|
||||
// So, the AIC initialization resumes at setting up the default vectors.
|
||||
//-----------------------------------------------------------------------------
|
||||
AIC()
|
||||
{
|
||||
// Mask All interrupt pAic->AIC_IDCR = 0xFFFFFFFF;
|
||||
__writeMemory32(0xFFFFFFFF,0xFFFFF124,"Memory");
|
||||
|
||||
for (i=0;i < 8; i++)
|
||||
{
|
||||
// AT91C_BASE_AIC->AIC_EOICR
|
||||
pt = __readMemory32(0xFFFFF130,"Memory");
|
||||
|
||||
}
|
||||
__message "------------------------------- AIC INIT ---------------------------------------------";
|
||||
}
|
||||
|
||||
ini()
|
||||
{
|
||||
__writeMemory32(0x0,0x00,"Register");
|
||||
__writeMemory32(0x0,0x04,"Register");
|
||||
__writeMemory32(0x0,0x08,"Register");
|
||||
__writeMemory32(0x0,0x0C,"Register");
|
||||
__writeMemory32(0x0,0x10,"Register");
|
||||
__writeMemory32(0x0,0x14,"Register");
|
||||
__writeMemory32(0x0,0x18,"Register");
|
||||
__writeMemory32(0x0,0x1C,"Register");
|
||||
__writeMemory32(0x0,0x20,"Register");
|
||||
__writeMemory32(0x0,0x24,"Register");
|
||||
__writeMemory32(0x0,0x28,"Register");
|
||||
__writeMemory32(0x0,0x2C,"Register");
|
||||
__writeMemory32(0x0,0x30,"Register");
|
||||
__writeMemory32(0x0,0x34,"Register");
|
||||
__writeMemory32(0x0,0x38,"Register");
|
||||
|
||||
// Set CPSR
|
||||
__writeMemory32(0x0D3,0x98,"Register");
|
||||
|
||||
|
||||
}
|
||||
|
||||
RG()
|
||||
{
|
||||
|
||||
i=__readMemory32(0x00,"Register"); __message "R00 0x",i:%X;
|
||||
i=__readMemory32(0x04,"Register"); __message "R01 0x",i:%X;
|
||||
i=__readMemory32(0x08,"Register"); __message "R02 0x",i:%X;
|
||||
i=__readMemory32(0x0C,"Register"); __message "R03 0x",i:%X;
|
||||
i=__readMemory32(0x10,"Register"); __message "R04 0x",i:%X;
|
||||
i=__readMemory32(0x14,"Register"); __message "R05 0x",i:%X;
|
||||
i=__readMemory32(0x18,"Register"); __message "R06 0x",i:%X;
|
||||
i=__readMemory32(0x1C,"Register"); __message "R07 0x",i:%X;
|
||||
i=__readMemory32(0x20,"Register"); __message "R08 0x",i:%X;
|
||||
i=__readMemory32(0x24,"Register"); __message "R09 0x",i:%X;
|
||||
i=__readMemory32(0x28,"Register"); __message "R10 0x",i:%X;
|
||||
i=__readMemory32(0x2C,"Register"); __message "R11 0x",i:%X;
|
||||
i=__readMemory32(0x30,"Register"); __message "R12 0x",i:%X;
|
||||
i=__readMemory32(0x34,"Register"); __message "R13 0x",i:%X;
|
||||
i=__readMemory32(0x38,"Register"); __message "R14 0x",i:%X;
|
||||
i=__readMemory32(0x3C,"Register"); __message "R13 SVC 0x",i:%X;
|
||||
i=__readMemory32(0x40,"Register"); __message "R14 SVC 0x",i:%X;
|
||||
i=__readMemory32(0x44,"Register"); __message "R13 ABT 0x",i:%X;
|
||||
i=__readMemory32(0x48,"Register"); __message "R14 ABT 0x",i:%X;
|
||||
i=__readMemory32(0x4C,"Register"); __message "R13 UND 0x",i:%X;
|
||||
i=__readMemory32(0x50,"Register"); __message "R14 UND 0x",i:%X;
|
||||
i=__readMemory32(0x54,"Register"); __message "R13 IRQ 0x",i:%X;
|
||||
i=__readMemory32(0x58,"Register"); __message "R14 IRQ 0x",i:%X;
|
||||
i=__readMemory32(0x5C,"Register"); __message "R08 FIQ 0x",i:%X;
|
||||
i=__readMemory32(0x60,"Register"); __message "R09 FIQ 0x",i:%X;
|
||||
i=__readMemory32(0x64,"Register"); __message "R10 FIQ 0x",i:%X;
|
||||
i=__readMemory32(0x68,"Register"); __message "R11 FIQ 0x",i:%X;
|
||||
i=__readMemory32(0x6C,"Register"); __message "R12 FIQ 0x",i:%X;
|
||||
i=__readMemory32(0x70,"Register"); __message "R13 FIQ 0x",i:%X;
|
||||
i=__readMemory32(0x74,"Register"); __message "R14 FIQ0x",i:%X;
|
||||
i=__readMemory32(0x98,"Register"); __message "CPSR ",i:%X;
|
||||
i=__readMemory32(0x94,"Register"); __message "SPSR ",i:%X;
|
||||
i=__readMemory32(0x9C,"Register"); __message "SPSR ABT ",i:%X;
|
||||
i=__readMemory32(0xA0,"Register"); __message "SPSR ABT ",i:%X;
|
||||
i=__readMemory32(0xA4,"Register"); __message "SPSR UND ",i:%X;
|
||||
i=__readMemory32(0xA8,"Register"); __message "SPSR IRQ ",i:%X;
|
||||
i=__readMemory32(0xAC,"Register"); __message "SPSR FIQ ",i:%X;
|
||||
|
||||
i=__readMemory32(0xB4,"Register"); __message "PC 0x",i:%X;
|
||||
|
||||
}
|
||||
|
||||
211
Demo/ARM7_AT91SAM7S64_IAR/resource/SAM7_RAM.mac
Normal file
211
Demo/ARM7_AT91SAM7S64_IAR/resource/SAM7_RAM.mac
Normal file
|
|
@ -0,0 +1,211 @@
|
|||
// ---------------------------------------------------------
|
||||
// ATMEL Microcontroller Software Support - ROUSSET -
|
||||
// ---------------------------------------------------------
|
||||
// The software is delivered "AS IS" without warranty or
|
||||
// condition of any kind, either express, implied or
|
||||
// statutory. This includes without limitation any warranty
|
||||
// or condition with respect to merchantability or fitness
|
||||
// for any particular purpose, or against the infringements of
|
||||
// intellectual property rights of others.
|
||||
// ---------------------------------------------------------
|
||||
// File: SAM7_RAM.mac
|
||||
//
|
||||
// User setup file for CSPY debugger to simulate interrupt
|
||||
// driven Fibonacchi data input.
|
||||
// 1.1 16/Jun/04 JPP : Creation
|
||||
// 1.2 27/Aug/04 JPP : PLL setting
|
||||
//
|
||||
// $Revision: 1.3 $
|
||||
//
|
||||
// ---------------------------------------------------------
|
||||
|
||||
__var i;
|
||||
__var pt;
|
||||
|
||||
execUserPreload()
|
||||
{
|
||||
//*
|
||||
PllSetting();
|
||||
//* Set the RAM memory at 0x0020 0000 for code AT 0 flash area
|
||||
CheckNoRemap();
|
||||
//* Get the Chip ID (AT91C_DBGU_C1R & AT91C_DBGU_C2R
|
||||
i=__readMemory32(0xFFFFF240,"Memory");
|
||||
__message " ---------------------------------------- Chip ID 0x",i:%X;
|
||||
i=__readMemory32(0xFFFFF244,"Memory");
|
||||
__message " ---------------------------------------- Extention 0x",i:%X;
|
||||
i=__readMemory32(0xFFFFFF6C,"Memory");
|
||||
__message " ---------------------------------------- Flash Version 0x",i:%X;
|
||||
//* Get the chip status
|
||||
|
||||
//* Init AIC
|
||||
AIC();
|
||||
//* Watchdog Disable
|
||||
Watchdog();
|
||||
}
|
||||
//-----------------------------------------------------------------------------
|
||||
// PllSetting
|
||||
//-------------------------------
|
||||
// Set PLL
|
||||
//-----------------------------------------------------------------------------
|
||||
PllSetting()
|
||||
{
|
||||
// -1- Enabling the Main Oscillator:
|
||||
//*#define AT91C_PMC_MOR ((AT91_REG *) 0xFFFFFC20) // (PMC) Main Oscillator Register
|
||||
//*#define AT91C_PMC_PLLR ((AT91_REG *) 0xFFFFFC2C) // (PMC) PLL Register
|
||||
//*#define AT91C_PMC_MCKR ((AT91_REG *) 0xFFFFFC30) // (PMC) Master Clock Register
|
||||
|
||||
//*pPMC->PMC_MOR = (( AT91C_CKGR_OSCOUNT & (0x06 <<8) | //0x0000 0600
|
||||
// AT91C_CKGR_MOSCEN )); //0x0000 0001
|
||||
__writeMemory32(0x00000601,0xFFFFFC20,"Memory");
|
||||
|
||||
// -2- Wait
|
||||
// -3- Setting PLL and divider:
|
||||
// - div by 5 Fin = 3,6864 =(18,432 / 5)
|
||||
// - Mul 25+1: Fout = 95,8464 =(3,6864 *26)
|
||||
// for 96 MHz the erroe is 0.16%
|
||||
// Field out NOT USED = 0
|
||||
// PLLCOUNT pll startup time esrtimate at : 0.844 ms
|
||||
// PLLCOUNT 28 = 0.000844 /(1/32768)
|
||||
// pPMC->PMC_PLLR = ((AT91C_CKGR_DIV & 0x05) | //0x0000 0005
|
||||
// (AT91C_CKGR_PLLCOUNT & (28<<8)) //0x0000 1C00
|
||||
// (AT91C_CKGR_MUL & (25<<16))); //0x0019 0000
|
||||
__writeMemory32(0x00191C05,0xFFFFFC2C,"Memory");
|
||||
// -2- Wait
|
||||
// -5- Selection of Master Clock and Processor Clock
|
||||
// select the PLL clock divided by 2
|
||||
// pPMC->PMC_MCKR = AT91C_PMC_CSS_PLL_CLK | //0x0000 0003
|
||||
// AT91C_PMC_PRES_CLK_2 ; //0x0000 0004
|
||||
__writeMemory32(0x00000007,0xFFFFFC30,"Memory");
|
||||
|
||||
__message "------------------------------- PLL Enable ----------------------------------------";
|
||||
}
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
// Watchdog
|
||||
//-------------------------------
|
||||
// Normally, the Watchdog is enable at the reset for load it's preferable to
|
||||
// Disable.
|
||||
//-----------------------------------------------------------------------------
|
||||
Watchdog()
|
||||
{
|
||||
//* Watchdog Disable
|
||||
// AT91C_BASE_WDTC->WDTC_WDMR= AT91C_SYSC_WDDIS;
|
||||
__writeMemory32(0x00008000,0xFFFFFD44,"Memory");
|
||||
__message "------------------------------- Watchdog Disable ----------------------------------------";
|
||||
}
|
||||
|
||||
CheckNoRemap()
|
||||
{
|
||||
//* Read the value at 0x0
|
||||
i=__readMemory32(0x00000000,"Memory");
|
||||
i=i+1;
|
||||
__writeMemory32(i,0x00,"Memory");
|
||||
pt=__readMemory32(0x00000000,"Memory");
|
||||
|
||||
if (i == pt)
|
||||
{
|
||||
__message "------------------------------- The Remap is done ----------------------------------------";
|
||||
|
||||
} else {
|
||||
__message "------------------------------- The Remap is NOT -----------------------------------------";
|
||||
//* Toggel RESET The remap
|
||||
__writeMemory32(0x00000001,0xFFFFFF00,"Memory");
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
execUserSetup()
|
||||
{
|
||||
ini();
|
||||
__message "-------------------------------Set PC ----------------------------------------";
|
||||
__writeMemory32(0x00000000,0xB4,"Register");
|
||||
}
|
||||
|
||||
//-----------------------------------------------------------------------------
|
||||
// Reset the Interrupt Controller
|
||||
//-------------------------------
|
||||
// Normally, the code is executed only if a reset has been actually performed.
|
||||
// So, the AIC initialization resumes at setting up the default vectors.
|
||||
//-----------------------------------------------------------------------------
|
||||
AIC()
|
||||
{
|
||||
// Mask All interrupt pAic->AIC_IDCR = 0xFFFFFFFF;
|
||||
__writeMemory32(0xFFFFFFFF,0xFFFFF124,"Memory");
|
||||
|
||||
for (i=0;i < 8; i++)
|
||||
{
|
||||
// AT91C_BASE_AIC->AIC_EOICR
|
||||
pt = __readMemory32(0xFFFFF130,"Memory");
|
||||
|
||||
}
|
||||
__message "------------------------------- AIC INIT ---------------------------------------------";
|
||||
}
|
||||
|
||||
ini()
|
||||
{
|
||||
__writeMemory32(0x0,0x00,"Register");
|
||||
__writeMemory32(0x0,0x04,"Register");
|
||||
__writeMemory32(0x0,0x08,"Register");
|
||||
__writeMemory32(0x0,0x0C,"Register");
|
||||
__writeMemory32(0x0,0x10,"Register");
|
||||
__writeMemory32(0x0,0x14,"Register");
|
||||
__writeMemory32(0x0,0x18,"Register");
|
||||
__writeMemory32(0x0,0x1C,"Register");
|
||||
__writeMemory32(0x0,0x20,"Register");
|
||||
__writeMemory32(0x0,0x24,"Register");
|
||||
__writeMemory32(0x0,0x28,"Register");
|
||||
__writeMemory32(0x0,0x2C,"Register");
|
||||
__writeMemory32(0x0,0x30,"Register");
|
||||
__writeMemory32(0x0,0x34,"Register");
|
||||
__writeMemory32(0x0,0x38,"Register");
|
||||
|
||||
// Set CPSR
|
||||
__writeMemory32(0x0D3,0x98,"Register");
|
||||
|
||||
}
|
||||
|
||||
RG()
|
||||
{
|
||||
|
||||
i=__readMemory32(0x00,"Register"); __message "R00 0x",i:%X;
|
||||
i=__readMemory32(0x04,"Register"); __message "R01 0x",i:%X;
|
||||
i=__readMemory32(0x08,"Register"); __message "R02 0x",i:%X;
|
||||
i=__readMemory32(0x0C,"Register"); __message "R03 0x",i:%X;
|
||||
i=__readMemory32(0x10,"Register"); __message "R04 0x",i:%X;
|
||||
i=__readMemory32(0x14,"Register"); __message "R05 0x",i:%X;
|
||||
i=__readMemory32(0x18,"Register"); __message "R06 0x",i:%X;
|
||||
i=__readMemory32(0x1C,"Register"); __message "R07 0x",i:%X;
|
||||
i=__readMemory32(0x20,"Register"); __message "R08 0x",i:%X;
|
||||
i=__readMemory32(0x24,"Register"); __message "R09 0x",i:%X;
|
||||
i=__readMemory32(0x28,"Register"); __message "R10 0x",i:%X;
|
||||
i=__readMemory32(0x2C,"Register"); __message "R11 0x",i:%X;
|
||||
i=__readMemory32(0x30,"Register"); __message "R12 0x",i:%X;
|
||||
i=__readMemory32(0x34,"Register"); __message "R13 0x",i:%X;
|
||||
i=__readMemory32(0x38,"Register"); __message "R14 0x",i:%X;
|
||||
i=__readMemory32(0x3C,"Register"); __message "R13 SVC 0x",i:%X;
|
||||
i=__readMemory32(0x40,"Register"); __message "R14 SVC 0x",i:%X;
|
||||
i=__readMemory32(0x44,"Register"); __message "R13 ABT 0x",i:%X;
|
||||
i=__readMemory32(0x48,"Register"); __message "R14 ABT 0x",i:%X;
|
||||
i=__readMemory32(0x4C,"Register"); __message "R13 UND 0x",i:%X;
|
||||
i=__readMemory32(0x50,"Register"); __message "R14 UND 0x",i:%X;
|
||||
i=__readMemory32(0x54,"Register"); __message "R13 IRQ 0x",i:%X;
|
||||
i=__readMemory32(0x58,"Register"); __message "R14 IRQ 0x",i:%X;
|
||||
i=__readMemory32(0x5C,"Register"); __message "R08 FIQ 0x",i:%X;
|
||||
i=__readMemory32(0x60,"Register"); __message "R09 FIQ 0x",i:%X;
|
||||
i=__readMemory32(0x64,"Register"); __message "R10 FIQ 0x",i:%X;
|
||||
i=__readMemory32(0x68,"Register"); __message "R11 FIQ 0x",i:%X;
|
||||
i=__readMemory32(0x6C,"Register"); __message "R12 FIQ 0x",i:%X;
|
||||
i=__readMemory32(0x70,"Register"); __message "R13 FIQ 0x",i:%X;
|
||||
i=__readMemory32(0x74,"Register"); __message "R14 FIQ0x",i:%X;
|
||||
i=__readMemory32(0x98,"Register"); __message "CPSR ",i:%X;
|
||||
i=__readMemory32(0x94,"Register"); __message "SPSR ",i:%X;
|
||||
i=__readMemory32(0x9C,"Register"); __message "SPSR ABT ",i:%X;
|
||||
i=__readMemory32(0xA0,"Register"); __message "SPSR ABT ",i:%X;
|
||||
i=__readMemory32(0xA4,"Register"); __message "SPSR UND ",i:%X;
|
||||
i=__readMemory32(0xA8,"Register"); __message "SPSR IRQ ",i:%X;
|
||||
i=__readMemory32(0xAC,"Register"); __message "SPSR FIQ ",i:%X;
|
||||
|
||||
i=__readMemory32(0xB4,"Register"); __message "PC 0x",i:%X;
|
||||
|
||||
}
|
||||
|
||||
135
Demo/ARM7_AT91SAM7S64_IAR/resource/at91SAM7S64_16KRAM.xcl
Normal file
135
Demo/ARM7_AT91SAM7S64_IAR/resource/at91SAM7S64_16KRAM.xcl
Normal file
|
|
@ -0,0 +1,135 @@
|
|||
// ---------------------------------------------------------
|
||||
// ATMEL Microcontroller Software Support - ROUSSET -
|
||||
// ---------------------------------------------------------
|
||||
// The software is delivered "AS IS" without warranty or
|
||||
// condition of any kind, either express, implied or
|
||||
// statutory. This includes without limitation any warranty
|
||||
// or condition with respect to merchantability or fitness
|
||||
// for any particular purpose, or against the infringements of
|
||||
// intellectual property rights of others.
|
||||
// ---------------------------------------------------------
|
||||
// File: at91SAM7S64_16KRAM.xlc
|
||||
//
|
||||
// 1.1 16/Jun/04 JPP : Creation for 4.11A
|
||||
//
|
||||
// $Revision: 1.1.1.1 $
|
||||
//
|
||||
// ---------------------------------------------------------
|
||||
|
||||
//*************************************************************************
|
||||
// XLINK command file template for EWARM/ICCARM
|
||||
//
|
||||
// Usage: xlink -f lnkarm <your_object_file(s)>
|
||||
// -s <program start label> <C/C++ runtime library>
|
||||
//
|
||||
// $Revision: 1.1.1.1 $
|
||||
//*************************************************************************
|
||||
|
||||
//************************************************
|
||||
// Inform the linker about the CPU family used.
|
||||
// AT91SAM7S64 Memory mapping
|
||||
// No remap
|
||||
// ROMSTART
|
||||
// Start address 0x0000 0000
|
||||
// Size 64 Kbo 0x0001 0000
|
||||
// RAMSTART
|
||||
// Start address 0x0020 0000
|
||||
// Size 16 Kbo 0x0000 4000
|
||||
// Remap done
|
||||
// RAMSTART
|
||||
// Start address 0x0000 0000
|
||||
// Size 16 Kbo 0x0000 4000
|
||||
// ROMSTART
|
||||
// Start address 0x0010 0000
|
||||
// Size 64 Kbo 0x0001 0000
|
||||
|
||||
//************************************************
|
||||
-carm
|
||||
|
||||
//*************************************************************************
|
||||
// Internal Ram segments mapped AFTER REMAP 16 K.
|
||||
//*************************************************************************
|
||||
// Use these addresses for the .
|
||||
-Z(CONST)INTRAMSTART_REMAP=00000000
|
||||
-Z(CONST)INTRAMEND_REMAP=00003FFF
|
||||
|
||||
//*************************************************************************
|
||||
// Read-only segments mapped to Flash 64 K.
|
||||
//*************************************************************************
|
||||
-DROMSTART=00000000
|
||||
-DROMEND=0000FFFF
|
||||
//*************************************************************************
|
||||
// Read/write segments mapped to RAM.
|
||||
//*************************************************************************
|
||||
-DRAMSTART=00000000
|
||||
-DRAMEND=00003FFF
|
||||
|
||||
//************************************************
|
||||
// Address range for reset and exception
|
||||
// vectors (INTVEC).
|
||||
// The vector area is 32 bytes,
|
||||
// an additional 32 bytes is allocated for the
|
||||
// constant table used by ldr PC in cstartup.s79.
|
||||
//************************************************
|
||||
-Z(CODE)INTVEC=00-3F
|
||||
|
||||
//************************************************
|
||||
// Startup code and exception routines (ICODE).
|
||||
//************************************************
|
||||
-Z(CODE)ICODE,DIFUNCT=ROMSTART-ROMEND
|
||||
-Z(CODE)SWITAB=ROMSTART-ROMEND
|
||||
|
||||
//************************************************
|
||||
// Code segments may be placed anywhere.
|
||||
//************************************************
|
||||
-Z(CODE)CODE=ROMSTART-ROMEND
|
||||
|
||||
//************************************************
|
||||
// Various constants and initializers.
|
||||
//************************************************
|
||||
-Z(CONST)INITTAB,DATA_ID,DATA_C=ROMSTART-ROMEND
|
||||
-Z(CONST)CHECKSUM=ROMSTART-ROMEND
|
||||
|
||||
//************************************************
|
||||
// Data segments.
|
||||
//************************************************
|
||||
-Z(DATA)DATA_I,DATA_Z,DATA_N=RAMSTART-RAMEND
|
||||
|
||||
//************************************************
|
||||
// __ramfunc code copied to and executed from RAM.
|
||||
//************************************************
|
||||
-Z(DATA)CODE_I=RAMSTART-RAMEND
|
||||
|
||||
//************************************************
|
||||
// ICCARM produces code for __ramfunc functions in
|
||||
// CODE_I segments. The -Q XLINK command line
|
||||
// option redirects XLINK to emit the code in the
|
||||
// debug information associated with the CODE_I
|
||||
// segment, where the code will execute.
|
||||
//************************************************
|
||||
|
||||
//*************************************************************************
|
||||
// Stack and heap segments.
|
||||
//*************************************************************************
|
||||
-D_CSTACK_SIZE=(100*4)
|
||||
-D_IRQ_STACK_SIZE=(2*8*4)
|
||||
|
||||
-Z(DATA)CSTACK+_CSTACK_SIZE=RAMSTART-RAMEND
|
||||
-Z(DATA)IRQ_STACK+_IRQ_STACK_SIZE=RAMSTART-RAMEND
|
||||
|
||||
//*************************************************************************
|
||||
// ELF/DWARF support.
|
||||
//
|
||||
// Uncomment the line "-Felf" below to generate ELF/DWARF output.
|
||||
// Available format specifiers are:
|
||||
//
|
||||
// "-yn": Suppress DWARF debug output
|
||||
// "-yp": Multiple ELF program sections
|
||||
// "-yas": Format suitable for debuggers from ARM Ltd (also sets -p flag)
|
||||
//
|
||||
// "-Felf" and the format specifiers can also be supplied directly as
|
||||
// command line options, or selected from the Xlink Output tab in the
|
||||
// IAR Embedded Workbench.
|
||||
//*************************************************************************
|
||||
|
||||
// -Felf
|
||||
136
Demo/ARM7_AT91SAM7S64_IAR/resource/at91SAM7S64_NoRemap.xcl
Normal file
136
Demo/ARM7_AT91SAM7S64_IAR/resource/at91SAM7S64_NoRemap.xcl
Normal file
|
|
@ -0,0 +1,136 @@
|
|||
// ---------------------------------------------------------
|
||||
// ATMEL Microcontroller Software Support - ROUSSET -
|
||||
// ---------------------------------------------------------
|
||||
// The software is delivered "AS IS" without warranty or
|
||||
// condition of any kind, either express, implied or
|
||||
// statutory. This includes without limitation any warranty
|
||||
// or condition with respect to merchantability or fitness
|
||||
// for any particular purpose, or against the infringements of
|
||||
// intellectual property rights of others.
|
||||
// ---------------------------------------------------------
|
||||
// File: at91SAM7S64_NoRemap.xlc
|
||||
//
|
||||
// 1.1 16/Jun/04 JPP : Creation for 4.11A
|
||||
//
|
||||
// $Revision: 1.1.1.1 $
|
||||
//
|
||||
// ---------------------------------------------------------
|
||||
|
||||
//*************************************************************************
|
||||
// XLINK command file template for EWARM/ICCARM
|
||||
//
|
||||
// Usage: xlink -f lnkarm <your_object_file(s)>
|
||||
// -s <program start label> <C/C++ runtime library>
|
||||
//
|
||||
// $Revision: 1.1.1.1 $
|
||||
//*************************************************************************
|
||||
|
||||
//************************************************
|
||||
// Inform the linker about the CPU family used.
|
||||
// AT91SAM7S64 Memory mapping
|
||||
// No remap
|
||||
// ROMSTART
|
||||
// Start address 0x0000 0000
|
||||
// Size 64 Kbo 0x0001 0000
|
||||
// RAMSTART
|
||||
// Start address 0x0020 0000
|
||||
// Size 16 Kbo 0x0000 4000
|
||||
// Remap done
|
||||
// RAMSTART
|
||||
// Start address 0x0000 0000
|
||||
// Size 16 Kbo 0x0000 4000
|
||||
// ROMSTART
|
||||
// Start address 0x0010 0000
|
||||
// Size 64 Kbo 0x0001 0000
|
||||
|
||||
//************************************************
|
||||
-carm
|
||||
|
||||
//*************************************************************************
|
||||
// Internal Ram segments mapped AFTER REMAP 16 K.
|
||||
//*************************************************************************
|
||||
// Use these addresses for the .
|
||||
-Z(CONST)INTRAMSTART_REMAP=00200000
|
||||
-Z(CONST)INTRAMEND_REMAP=00203FFF
|
||||
|
||||
//*************************************************************************
|
||||
// Read-only segments mapped to Flash 64 K.
|
||||
//*************************************************************************
|
||||
-DROMSTART=00000000
|
||||
-DROMEND=0000FFFF
|
||||
//*************************************************************************
|
||||
// Read/write segments mapped to RAM.
|
||||
//*************************************************************************
|
||||
-DRAMSTART=00200000
|
||||
-DRAMEND=002003FFF
|
||||
|
||||
//************************************************
|
||||
// Address range for reset and exception
|
||||
// vectors (INTVEC).
|
||||
// The vector area is 32 bytes,
|
||||
// an additional 32 bytes is allocated for the
|
||||
// constant table used by ldr PC in cstartup.s79.
|
||||
//************************************************
|
||||
-Z(CODE)INTVEC=00-3F
|
||||
|
||||
//************************************************
|
||||
// Startup code and exception routines (ICODE).
|
||||
//************************************************
|
||||
-Z(CODE)ICODE,DIFUNCT=ROMSTART-ROMEND
|
||||
-Z(CODE)SWITAB=ROMSTART-ROMEND
|
||||
|
||||
//************************************************
|
||||
// Code segments may be placed anywhere.
|
||||
//************************************************
|
||||
-Z(CODE)CODE=ROMSTART-ROMEND
|
||||
|
||||
//************************************************
|
||||
// Various constants and initializers.
|
||||
//************************************************
|
||||
-Z(CONST)INITTAB,DATA_ID,DATA_C=ROMSTART-ROMEND
|
||||
-Z(CONST)CHECKSUM=ROMSTART-ROMEND
|
||||
|
||||
|
||||
//************************************************
|
||||
// Data segments.
|
||||
//************************************************
|
||||
-Z(DATA)DATA_I,DATA_Z,DATA_N=RAMSTART-RAMEND
|
||||
|
||||
//************************************************
|
||||
// __ramfunc code copied to and executed from RAM.
|
||||
//************************************************
|
||||
-Z(DATA)CODE_I=RAMSTART-RAMEND
|
||||
|
||||
//************************************************
|
||||
// ICCARM produces code for __ramfunc functions in
|
||||
// CODE_I segments. The -Q XLINK command line
|
||||
// option redirects XLINK to emit the code in the
|
||||
// debug information associated with the CODE_I
|
||||
// segment, where the code will execute.
|
||||
//************************************************
|
||||
|
||||
//*************************************************************************
|
||||
// Stack and heap segments.
|
||||
//*************************************************************************
|
||||
//-D_CSTACK_SIZE=(100*4)
|
||||
//-D_IRQ_STACK_SIZE=(2*8*4)
|
||||
|
||||
//-Z(DATA)CSTACK+_CSTACK_SIZE=RAMSTART-RAMEND
|
||||
//-Z(DATA)IRQ_STACK+_IRQ_STACK_SIZE=RAMSTART-RAMEND
|
||||
|
||||
//*************************************************************************
|
||||
// ELF/DWARF support.
|
||||
//
|
||||
// Uncomment the line "-Felf" below to generate ELF/DWARF output.
|
||||
// Available format specifiers are:
|
||||
//
|
||||
// "-yn": Suppress DWARF debug output
|
||||
// "-yp": Multiple ELF program sections
|
||||
// "-yas": Format suitable for debuggers from ARM Ltd (also sets -p flag)
|
||||
//
|
||||
// "-Felf" and the format specifiers can also be supplied directly as
|
||||
// command line options, or selected from the Xlink Output tab in the
|
||||
// IAR Embedded Workbench.
|
||||
//*************************************************************************
|
||||
|
||||
// -Felf
|
||||
Loading…
Add table
Add a link
Reference in a new issue