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https://github.com/FreeRTOS/FreeRTOS-Kernel.git
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First version under SVN is V4.0.1
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Richard Barry
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89
Demo/ARM7_AT91SAM7S64_IAR/SrcIAR/Board.h
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89
Demo/ARM7_AT91SAM7S64_IAR/SrcIAR/Board.h
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/*----------------------------------------------------------------------------
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* ATMEL Microcontroller Software Support - ROUSSET -
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*----------------------------------------------------------------------------
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* The software is delivered "AS IS" without warranty or condition of any
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* kind, either express, implied or statutory. This includes without
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* limitation any warranty or condition with respect to merchantability or
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* fitness for any particular purpose, or against the infringements of
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* intellectual property rights of others.
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*----------------------------------------------------------------------------
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* File Name : Board.h
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* Object : AT91SAM7S Evaluation Board Features Definition File.
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*
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* Creation : JPP 16/Jun/2004
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*----------------------------------------------------------------------------
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*/
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#ifndef Board_h
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#define Board_h
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#include "AT91SAM7S64.h"
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#define __inline inline
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#include "lib_AT91SAM7S64.h"
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#define true -1
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#define false 0
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/*-------------------------------*/
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/* SAM7Board Memories Definition */
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/*-------------------------------*/
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// The AT91SAM7S64 embeds a 16-Kbyte SRAM bank, and 64 K-Byte Flash
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#define INT_SARM 0x00200000
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#define INT_SARM_REMAP 0x00000000
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#define INT_FLASH 0x00000000
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#define INT_FLASH_REMAP 0x01000000
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#define FLASH_PAGE_NB 512
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#define FLASH_PAGE_SIZE 128
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/*-----------------*/
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/* Leds Definition */
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/*-----------------*/
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/* PIO Flash PA PB PIN */
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#define LED1 (1<<0) /* PA0 / PGMEN0 & PWM0 TIOA0 48 */
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#define LED2 (1<<1) /* PA1 / PGMEN1 & PWM1 TIOB0 47 */
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#define LED3 (1<<2) /* PA2 & PWM2 SCK0 44 */
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#define LED4 (1<<3) /* PA3 & TWD NPCS3 43 */
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#define NB_LED 4
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#define LED_MASK (LED1|LED2|LED3|LED4)
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/*-------------------------*/
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/* Push Buttons Definition */
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/*-------------------------*/
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/* PIO Flash PA PB PIN */
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#define SW1_MASK (1<<19) /* PA19 / PGMD7 & RK FIQ 13 */
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#define SW2_MASK (1<<20) /* PA20 / PGMD8 & RF IRQ0 16 */
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#define SW3_MASK (1<<15) /* PA15 / PGM3 & TF TIOA1 20 */
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#define SW4_MASK (1<<14) /* PA14 / PGMD2 & SPCK PWM3 21 */
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#define SW_MASK (SW1_MASK|SW2_MASK|SW3_MASK|SW4_MASK)
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#define SW1 (1<<19) // PA19
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#define SW2 (1<<20) // PA20
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#define SW3 (1<<15) // PA15
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#define SW4 (1<<14) // PA14
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/*------------------*/
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/* USART Definition */
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/*------------------*/
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/* SUB-D 9 points J3 DBGU*/
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#define DBGU_RXD AT91C_PA9_DRXD /* JP11 must be close */
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#define DBGU_TXD AT91C_PA10_DTXD /* JP12 must be close */
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#define AT91C_DBGU_BAUD 115200 // Baud rate
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#define US_RXD_PIN AT91C_PA5_RXD0 /* JP9 must be close */
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#define US_TXD_PIN AT91C_PA6_TXD0 /* JP7 must be close */
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#define US_RTS_PIN AT91C_PA7_RTS0 /* JP8 must be close */
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#define US_CTS_PIN AT91C_PA8_CTS0 /* JP6 must be close */
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/*--------------*/
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/* Master Clock */
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/*--------------*/
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#define EXT_OC 18432000 // Exetrnal ocilator MAINCK
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#define MCK 47923200 // MCK (PLLRC div by 2)
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#define MCKKHz (MCK/1000) //
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#endif /* Board_h */
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223
Demo/ARM7_AT91SAM7S64_IAR/SrcIAR/Cstartup.s79
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223
Demo/ARM7_AT91SAM7S64_IAR/SrcIAR/Cstartup.s79
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@ -0,0 +1,223 @@
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;------------------------------------------------------------------------------
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;- ATMEL Microcontroller Software Support - ROUSSET -
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;------------------------------------------------------------------------------
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; The software is delivered "AS IS" without warranty or condition of any
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; kind, either express, implied or statutory. This includes without
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; limitation any warranty or condition with respect to merchantability or
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; fitness for any particular purpose, or against the infringements of
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; intellectual property rights of others.
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;-----------------------------------------------------------------------------
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;- File source : Cstartup.s79
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;- Object : Generic CStartup for IAR No Use REMAP
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;- Compilation flag : None
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;-
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;- 1.0 15/Jun/04 JPP : Creation
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;------------------------------------------------------------------------------
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#include "AT91SAM7S64_inc.h"
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;------------------------------------------------------------------------------
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;- Area Definition
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;------------------------------------------------------------------------------
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;---------------------------------------------------------------
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; ?RESET
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; Reset Vector.
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; Normally, segment INTVEC is linked at address 0.
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; For debugging purposes, INTVEC may be placed at other
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; addresses.
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; A debugger that honors the entry point will start the
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; program in a normal way even if INTVEC is not at address 0.
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;-------------------------------------------------------------
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PROGRAM ?RESET
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RSEG INTRAMSTART_REMAP
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RSEG INTRAMEND_REMAP
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EXTERN vPortYieldProcessor
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RSEG ICODE:CODE:ROOT(2)
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CODE32 ; Always ARM mode after reset
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org 0
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reset
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;------------------------------------------------------------------------------
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;- Exception vectors
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;--------------------
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;- These vectors can be read at address 0 or at RAM address
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;- They ABSOLUTELY requires to be in relative addresssing mode in order to
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;- guarantee a valid jump. For the moment, all are just looping.
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;- If an exception occurs before remap, this would result in an infinite loop.
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;- To ensure if a exeption occurs before start application to infinite loop.
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;------------------------------------------------------------------------------
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B InitReset ; 0x00 Reset handler
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undefvec:
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B undefvec ; 0x04 Undefined Instruction
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swivec:
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B vPortYieldProcessor ; 0x08 Software Interrupt
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pabtvec:
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B pabtvec ; 0x0C Prefetch Abort
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dabtvec:
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B dabtvec ; 0x10 Data Abort
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rsvdvec:
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B rsvdvec ; 0x14 reserved
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irqvec:
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LDR PC, [PC, #-0xF20] ; Jump directly to the address given by the AIC
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fiqvec: ; 0x1c FIQ
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;------------------------------------------------------------------------------
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;- Function : FIQ_Handler_Entry
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;- Treatments : FIQ Controller Interrupt Handler.
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;- Called Functions : AIC_FVR[interrupt]
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;------------------------------------------------------------------------------
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FIQ_Handler_Entry:
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;- Switch in SVC/User Mode to allow User Stack access for C code
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; because the FIQ is not yet acknowledged
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;- Save and r0 in FIQ_Register
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mov r9,r0
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ldr r0 , [r8, #AIC_FVR]
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msr CPSR_c,#I_BIT | F_BIT | ARM_MODE_SVC
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;- Save scratch/used registers and LR in User Stack
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stmfd sp!, { r1-r3, r12, lr}
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;- Branch to the routine pointed by the AIC_FVR
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mov r14, pc
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bx r0
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;- Restore scratch/used registers and LR from User Stack
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ldmia sp!, { r1-r3, r12, lr}
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;- Leave Interrupts disabled and switch back in FIQ mode
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msr CPSR_c, #I_BIT | F_BIT | ARM_MODE_FIQ
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;- Restore the R0 ARM_MODE_SVC register
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mov r0,r9
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;- Restore the Program Counter using the LR_fiq directly in the PC
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subs pc,lr,#4
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InitReset:
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;------------------------------------------------------------------------------
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;- Low level Init (PMC, AIC, ? ....) by C function AT91F_LowLevelInit
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;------------------------------------------------------------------------------
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EXTERN AT91F_LowLevelInit
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#define __iramend SFB(INTRAMEND_REMAP)
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;- minumum C initialization
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;- call AT91F_LowLevelInit( void)
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ldr r13,=__iramend ; temporary stack in internal RAM
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;--Call Low level init function in ABSOLUTE through the Interworking
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ldr r0,=AT91F_LowLevelInit
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mov lr, pc
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bx r0
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;------------------------------------------------------------------------------
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;- Stack Sizes Definition
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;------------------------
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;- Interrupt Stack requires 2 words x 8 priority level x 4 bytes when using
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;- the vectoring. This assume that the IRQ management.
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;- The Interrupt Stack must be adjusted depending on the interrupt handlers.
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;- Fast Interrupt not requires stack If in your application it required you must
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;- be definehere.
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;- The System stack size is not defined and is limited by the free internal
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;- SRAM.
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;------------------------------------------------------------------------------
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;------------------------------------------------------------------------------
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;- Top of Stack Definition
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;-------------------------
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;- Interrupt and Supervisor Stack are located at the top of internal memory in
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;- order to speed the exception handling context saving and restoring.
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;- ARM_MODE_SVC (Application, C) Stack is located at the top of the external memory.
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;------------------------------------------------------------------------------
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IRQ_STACK_SIZE EQU 300
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ARM_MODE_FIQ EQU 0x11
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ARM_MODE_IRQ EQU 0x12
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ARM_MODE_SVC EQU 0x13
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I_BIT EQU 0x80
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F_BIT EQU 0x40
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;------------------------------------------------------------------------------
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;- Setup the stack for each mode
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;-------------------------------
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ldr r0, =__iramend
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;- Set up Fast Interrupt Mode and set FIQ Mode Stack
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msr CPSR_c, #ARM_MODE_FIQ | I_BIT | F_BIT
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;- Init the FIQ register
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ldr r8, =AT91C_BASE_AIC
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;- Set up Interrupt Mode and set IRQ Mode Stack
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msr CPSR_c, #ARM_MODE_IRQ | I_BIT | F_BIT
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mov r13, r0 ; Init stack IRQ
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sub r0, r0, #IRQ_STACK_SIZE
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;- Enable interrupt & Set up Supervisor Mode and set Supervisor Mode Stack
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msr CPSR_c, #ARM_MODE_SVC
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mov r13, r0
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;---------------------------------------------------------------
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; ?CSTARTUP
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;---------------------------------------------------------------
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EXTERN __segment_init
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EXTERN main
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; Initialize segments.
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; __segment_init is assumed to use
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; instruction set and to be reachable by BL from the ICODE segment
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; (it is safest to link them in segment ICODE).
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ldr r0,=__segment_init
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mov lr, pc
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bx r0
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PUBLIC __main
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?jump_to_main:
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ldr lr,=?call_exit
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ldr r0,=main
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__main:
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bx r0
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;------------------------------------------------------------------------------
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;- Loop for ever
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;---------------
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;- End of application. Normally, never occur.
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;- Could jump on Software Reset ( B 0x0 ).
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;------------------------------------------------------------------------------
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?call_exit:
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End
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b End
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;---------------------------------------------------------------
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; ?EXEPTION_VECTOR
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; This module is only linked if needed for closing files.
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;---------------------------------------------------------------
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PUBLIC AT91F_Default_FIQ_handler
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PUBLIC AT91F_Default_IRQ_handler
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PUBLIC AT91F_Spurious_handler
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CODE32 ; Always ARM mode after exeption
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AT91F_Default_FIQ_handler
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b AT91F_Default_FIQ_handler
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AT91F_Default_IRQ_handler
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b AT91F_Default_IRQ_handler
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AT91F_Spurious_handler
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b AT91F_Spurious_handler
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ENDMOD
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END
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84
Demo/ARM7_AT91SAM7S64_IAR/SrcIAR/Cstartup_SAM7.c
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84
Demo/ARM7_AT91SAM7S64_IAR/SrcIAR/Cstartup_SAM7.c
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@ -0,0 +1,84 @@
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//*----------------------------------------------------------------------------
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//* ATMEL Microcontroller Software Support - ROUSSET -
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//*----------------------------------------------------------------------------
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//* The software is delivered "AS IS" without warranty or condition of any
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//* kind, either express, implied or statutory. This includes without
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//* limitation any warranty or condition with respect to merchantability or
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//* fitness for any particular purpose, or against the infringements of
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//* intellectual property rights of others.
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//*----------------------------------------------------------------------------
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//* File Name : Cstartup_SAM7.c
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//* Object : Low level initializations written in C for IAR
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//* tools
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//* Creation : 12/Jun/04
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//*
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//*----------------------------------------------------------------------------
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// Include the board file description
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#include "Board.h"
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// The following functions must be write in ARM mode this function called directly
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// by exception vector
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extern void AT91F_Spurious_handler(void);
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extern void AT91F_Default_IRQ_handler(void);
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extern void AT91F_Default_FIQ_handler(void);
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//*----------------------------------------------------------------------------
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//* \fn AT91F_LowLevelInit
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//* \brief This function performs very low level HW initialization
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//* this function can be use a Stack, depending the compilation
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//* optimization mode
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//*----------------------------------------------------------------------------
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void AT91F_LowLevelInit( void );
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void AT91F_LowLevelInit( void) @ "ICODE"
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{
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int i;
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AT91PS_PMC pPMC = AT91C_BASE_PMC;
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//* Set Flash Waite sate
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// Single Cycle Access at Up to 30 MHz, or 40
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// if MCK = 47923200 I have 50 Cycle for 1 useconde ( flied MC_FMR->FMCN
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AT91C_BASE_MC->MC_FMR = ((AT91C_MC_FMCN)&(50 <<16)) | AT91C_MC_FWS_1FWS ;
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//* Watchdog Disable
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AT91C_BASE_WDTC->WDTC_WDMR= AT91C_SYSC_WDDIS;
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//* Set MCK at 47 923 200
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// 1 Enabling the Main Oscillator:
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// SCK = 1/32768 = 30.51 uSeconde
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// Start up time = 8 * 6 / SCK = 56 * 30.51 = 1,46484375 ms
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pPMC->PMC_MOR = (( AT91C_CKGR_OSCOUNT & (0x06 <<8) | AT91C_CKGR_MOSCEN ));
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// Wait the startup time
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while(!(pPMC->PMC_SR & AT91C_PMC_MOSCS));
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// 2 Checking the Main Oscillator Frequency (Optional)
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// 3 Setting PLL and divider:
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// - div by 5 Fin = 3,6864 =(18,432 / 5)
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// - Mul 25+1: Fout = 95,8464 =(3,6864 *26)
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// for 96 MHz the erroe is 0.16%
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// Field out NOT USED = 0
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// PLLCOUNT pll startup time esrtimate at : 0.844 ms
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// PLLCOUNT 28 = 0.000844 /(1/32768)
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pPMC->PMC_PLLR = ((AT91C_CKGR_DIV & 0x05) |
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(AT91C_CKGR_PLLCOUNT & (28<<8)) |
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(AT91C_CKGR_MUL & (25<<16)));
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// Wait the startup time
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while(!(pPMC->PMC_SR & AT91C_PMC_LOCK));
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// 4. Selection of Master Clock and Processor Clock
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// select the PLL clock divided by 2
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pPMC->PMC_MCKR = AT91C_PMC_CSS_PLL_CLK | AT91C_PMC_PRES_CLK_2 ;
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// Enable User Reset and set its minimal assertion to 960 us
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AT91C_BASE_RSTC->RSTC_RMR = AT91C_SYSC_URSTEN | (0x4<<8) | (unsigned int) (0xA5<<24);
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// Set up the default interrupts handler vectors
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AT91C_BASE_AIC->AIC_SVR[0] = (int) AT91F_Default_FIQ_handler ;
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for (i=1;i < 31; i++)
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{
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AT91C_BASE_AIC->AIC_SVR[i] = (int) AT91F_Default_IRQ_handler ;
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}
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AT91C_BASE_AIC->AIC_SPU = (int) AT91F_Spurious_handler ;
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}
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