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https://github.com/FreeRTOS/FreeRTOS-Kernel.git
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ARM_CA53: add support for FIQ
FIQ is used in the context of ARM SCP firmware instead of IRQ. This patch adds FIQ support for this context. Signed-off-by: Nicolas Royer <nroyer@baylibre.com>
This commit is contained in:
Nicolas Royer
David Chalco
parent
ef4c305244
commit
b6a112b850
3 changed files with 58 additions and 22 deletions
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@ -353,7 +353,11 @@ void vPortEndScheduler( void )
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void vPortEnterCritical( void )
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{
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/* Mask interrupts up to the max syscall interrupt priority. */
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uxPortSetInterruptMask();
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#if defined( configNO_INTERRUPT_MASK )
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portDISABLE_INTERRUPTS();
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#else
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uxPortSetInterruptMask();
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#endif
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/* Now interrupts are disabled ullCriticalNesting can be accessed
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directly. Increment ullCriticalNesting to keep a count of how many times
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@ -386,7 +390,11 @@ void vPortExitCritical( void )
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{
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/* Critical nesting has reached zero so all interrupt priorities
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should be unmasked. */
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portCLEAR_INTERRUPT_MASK();
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#if defined( configNO_INTERRUPT_MASK )
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portENABLE_INTERRUPTS();
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#else
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portCLEAR_INTERRUPT_MASK();
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#endif
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}
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}
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}
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@ -411,14 +419,18 @@ void FreeRTOS_Tick_Handler( void )
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}
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#endif /* configASSERT_DEFINED */
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/* Set interrupt mask before altering scheduler structures. The tick
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handler runs at the lowest priority, so interrupts cannot already be masked,
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so there is no need to save and restore the current mask value. It is
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necessary to turn off interrupts in the CPU itself while the ICCPMR is being
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updated. */
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portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
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__asm volatile ( "dsb sy \n"
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"isb sy \n" ::: "memory" );
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#if !defined( configNO_INTERRUPT_MASK )
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{
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/* Set interrupt mask before altering scheduler structures. The tick
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handler runs at the lowest priority, so interrupts cannot already be masked,
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so there is no need to save and restore the current mask value. It is
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necessary to turn off interrupts in the CPU itself while the ICCPMR is being
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updated. */
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portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
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__asm volatile ( "dsb sy \n"
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"isb sy \n" ::: "memory" );
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}
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#endif /* configNO_INTERRUPT_MASK */
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/* Ok to enable interrupts after the interrupt source has been cleared. */
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configCLEAR_TICK_INTERRUPT();
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@ -140,6 +140,7 @@
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/* Set the PMR register to be correct for the current critical nesting
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depth. */
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LDR X0, ullCriticalNestingConst /* X0 holds the address of ullCriticalNesting. */
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#if !defined( configNO_INTERRUPT_MASK )
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MOV X1, #255 /* X1 holds the unmask value. */
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LDR X4, ullICCPMRConst /* X4 holds the address of the ICCPMR constant. */
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CMP X3, #0
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@ -151,6 +152,7 @@
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STR W1, [X5] /* Write the mask value to ICCPMR. */
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DSB SY /* _RB_Barriers probably not required here. */
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ISB SY
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#endif
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STR X3, [X0] /* Restore the task's critical nesting count. */
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/* Restore the FPU context indicator. */
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@ -232,7 +234,7 @@ FreeRTOS_SWI_Handler:
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LSR X1, X0, #26
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#if defined( GUEST )
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#if defined( GUEST ) || defined( configUSE_SVC )
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CMP X1, #0x15 /* 0x15 = SVC instruction. */
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#else
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CMP X1, #0x17 /* 0x17 = SMC instruction. */
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@ -306,6 +308,7 @@ FreeRTOS_IRQ_Handler:
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/* Maintain the interrupt nesting information across the function call. */
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STP X1, X5, [SP, #-0x10]!
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#if !defined( configUSE_FIQ )
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/* Read value from the interrupt acknowledge register, which is stored in W0
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for future parameter and interrupt clearing use. */
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LDR X2, ullICCIARConst
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@ -314,15 +317,21 @@ FreeRTOS_IRQ_Handler:
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/* Maintain the ICCIAR value across the function call. */
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STP X0, X1, [SP, #-0x10]!
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#endif
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/* Call the C handler. */
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BL vApplicationIRQHandler
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/* Disable interrupts. */
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#if defined( configUSE_FIQ )
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MSR DAIFSET, #1
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#else
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MSR DAIFSET, #2
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#endif
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DSB SY
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ISB SY
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#if !defined( configUSE_FIQ )
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/* Restore the ICCIAR value. */
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LDP X0, X1, [SP], #0x10
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@ -330,6 +339,7 @@ FreeRTOS_IRQ_Handler:
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LDR X4, ullICCEOIRConst
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LDR X4, [X4]
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STR W0, [X4]
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#endif
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/* Restore the critical nesting count. */
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LDP X1, X5, [SP], #0x10
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@ -416,6 +426,7 @@ ullPortTaskHasFPUContextConst: .dword ullPortTaskHasFPUContext
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ullICCPMRConst: .dword ullICCPMR
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ullMaxAPIPriorityMaskConst: .dword ullMaxAPIPriorityMask
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vApplicationIRQHandlerConst: .word vApplicationIRQHandler
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.word 0
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ullPortInterruptNestingConst: .dword ullPortInterruptNesting
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ullPortYieldRequiredConst: .dword ullPortYieldRequired
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ullICCIARConst: .dword ullICCIAR
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@ -86,7 +86,7 @@ extern uint64_t ullPortYieldRequired; \
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}
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#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
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#if defined( GUEST )
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#if defined( GUEST ) || defined( configUSE_SVC )
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#define portYIELD() __asm volatile ( "SVC 0" ::: "memory" )
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#else
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#define portYIELD() __asm volatile ( "SMC 0" ::: "memory" )
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@ -101,23 +101,36 @@ extern UBaseType_t uxPortSetInterruptMask( void );
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extern void vPortClearInterruptMask( UBaseType_t uxNewMaskValue );
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extern void vPortInstallFreeRTOSVectorTable( void );
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#define portDISABLE_INTERRUPTS() \
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__asm volatile ( "MSR DAIFSET, #2" ::: "memory" ); \
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__asm volatile ( "DSB SY" ); \
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__asm volatile ( "ISB SY" );
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#if defined( configUSE_FIQ )
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#define portDISABLE_INTERRUPTS() \
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__asm volatile ( "MSR DAIFSET, #1" ::: "memory" ); \
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__asm volatile ( "DSB SY" ); \
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__asm volatile ( "ISB SY" );
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#define portENABLE_INTERRUPTS() \
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__asm volatile ( "MSR DAIFCLR, #2" ::: "memory" ); \
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__asm volatile ( "DSB SY" ); \
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__asm volatile ( "ISB SY" );
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#define portENABLE_INTERRUPTS() \
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__asm volatile ( "MSR DAIFCLR, #1" ::: "memory" ); \
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__asm volatile ( "DSB SY" ); \
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__asm volatile ( "ISB SY" );
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#else
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#define portDISABLE_INTERRUPTS() \
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__asm volatile ( "MSR DAIFSET, #2" ::: "memory" ); \
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__asm volatile ( "DSB SY" ); \
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__asm volatile ( "ISB SY" );
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#define portENABLE_INTERRUPTS() \
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__asm volatile ( "MSR DAIFCLR, #2" ::: "memory" ); \
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__asm volatile ( "DSB SY" ); \
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__asm volatile ( "ISB SY" );
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#endif
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/* These macros do not globally disable/enable interrupts. They do mask off
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interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */
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#define portENTER_CRITICAL() vPortEnterCritical();
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#define portEXIT_CRITICAL() vPortExitCritical();
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#define portSET_INTERRUPT_MASK_FROM_ISR() uxPortSetInterruptMask()
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#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vPortClearInterruptMask(x)
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#ifndef configNO_INTERRUPT_MASK
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#define portSET_INTERRUPT_MASK_FROM_ISR() uxPortSetInterruptMask()
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#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x) vPortClearInterruptMask(x)
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#endif
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/*-----------------------------------------------------------*/
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