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Cleanup license text in Xtensa XCC and Xtensa ESP32 GCC ports.
Add SPXD license identifiers.
This commit is contained in:
Paul Bartell
Paul Bartell
parent
1041b63586
commit
b5e9896ad7
37 changed files with 964 additions and 783 deletions
87
portable/ThirdParty/XCC/Xtensa/xtensa_vectors.S
vendored
87
portable/ThirdParty/XCC/Xtensa/xtensa_vectors.S
vendored
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@ -1,25 +1,30 @@
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/*
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* Copyright (c) 2015-2019 Cadence Design Systems, Inc.
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/*
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* FreeRTOS Kernel <DEVELOPMENT BRANCH>
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* Copyright (C) 2015-2019 Cadence Design Systems, Inc.
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* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sublicense, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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* SPDX-License-Identifier: MIT
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*
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* The above copyright notice and this permission notice shall be included
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* in all copies or substantial portions of the Software.
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* Permission is hereby granted, free of charge, to any person obtaining a copy of
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* this software and associated documentation files (the "Software"), to deal in
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* the Software without restriction, including without limitation the rights to
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* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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* the Software, and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* https://www.FreeRTOS.org
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* https://github.com/FreeRTOS
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
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* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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/*
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@ -36,14 +41,14 @@
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medium level interrupts, by calling xt_set_interrupt_handler(). These
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handlers can be written in C, and must obey C calling convention. The
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handler table is indexed by the interrupt number. Each handler may be
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provided with an argument.
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provided with an argument.
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Note that the system timer interrupt is handled specially, and is
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dispatched to the RTOS-specific handler. This timer cannot be hooked
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by application code.
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Optional hooks are also provided to install a handler per level at
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run-time, made available by compiling this source file with
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Optional hooks are also provided to install a handler per level at
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run-time, made available by compiling this source file with
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'-DXT_INTEXC_HOOKS' (useful for automated testing).
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!! This file is a template that usually needs to be modified to handle !!
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@ -83,10 +88,10 @@
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This allows more flexibility in locating code without the performance
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overhead of the 'l32r' literal data load in cases where the destination
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is in range of 'call0'. There is an additional benefit in that 'call0'
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has a longer range than 'j' due to the target being word-aligned, so
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has a longer range than 'j' due to the target being word-aligned, so
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the 'l32r' sequence is less likely needed.
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3. The use of 'call0' with -mlongcalls requires that register a0 not be
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live at the time of the call, which is always the case for a function
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3. The use of 'call0' with -mlongcalls requires that register a0 not be
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live at the time of the call, which is always the case for a function
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call but needs to be ensured if 'call0' is used as a jump in lieu of 'j'.
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4. This use of 'call0' is independent of the C function call ABI.
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@ -292,7 +297,7 @@
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/*
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--------------------------------------------------------------------------------
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Panic handler.
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Should be reached by call0 (preferable) or jump only. If call0, a0 says where
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Should be reached by call0 (preferable) or jump only. If call0, a0 says where
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from. If on simulator, display panic message and abort, else loop indefinitely.
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--------------------------------------------------------------------------------
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*/
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@ -326,7 +331,7 @@ _xt_panic_message:
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--------------------------------------------------------------------------------
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Hooks to dynamically install handlers for exceptions and interrupts.
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Allows automated regression frameworks to install handlers per test.
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Consists of an array of function pointers indexed by interrupt level,
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Consists of an array of function pointers indexed by interrupt level,
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with index 0 containing the entry for user exceptions.
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Initialized with all 0s, meaning no handler is installed at each level.
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See comment in xtensa_rtos.h for more details.
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@ -358,7 +363,7 @@ _xt_intexc_hooks:
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the appropriate stack frame, saves a few vector-specific registers and
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calls XT_RTOS_INT_ENTER to save the rest of the interrupted context
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and enter the RTOS, then sets up a C environment. It then calls the
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user's interrupt handler code (which may be coded in C) and finally
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user's interrupt handler code (which may be coded in C) and finally
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calls XT_RTOS_INT_EXIT to transfer control to the RTOS for scheduling.
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While XT_RTOS_INT_EXIT does not return directly to the interruptee,
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@ -734,7 +739,7 @@ _xt_syscall_exc:
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--------------------------------------------------------------------------------
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Co-Processor Exception Handler (jumped to from User Exception Handler).
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These exceptions are generated by co-processor instructions, which are only
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allowed in thread code (not in interrupts or kernel code). This restriction is
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allowed in thread code (not in interrupts or kernel code). This restriction is
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deliberately imposed to reduce the burden of state-save/restore in interrupts.
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--------------------------------------------------------------------------------
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*/
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@ -874,8 +879,8 @@ _xt_coproc_exc:
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/*
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The config-specific HAL macro invoked below destroys a2-5, preserves a0-1.
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It is theoretically possible for Xtensa processor designers to write TIE
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that causes more address registers to be affected, but it is generally
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It is theoretically possible for Xtensa processor designers to write TIE
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that causes more address registers to be affected, but it is generally
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unlikely. If that ever happens, more registers needs to be saved/restored
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around this macro invocation, and the value in a15 needs to be recomputed.
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*/
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@ -900,8 +905,8 @@ _xt_coproc_exc:
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/*
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The config-specific HAL macro invoked below destroys a2-5, preserves a0-1.
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It is theoretically possible for Xtensa processor designers to write TIE
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that causes more address registers to be affected, but it is generally
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It is theoretically possible for Xtensa processor designers to write TIE
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that causes more address registers to be affected, but it is generally
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unlikely. If that ever happens, more registers needs to be saved/restored
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around this macro invocation.
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*/
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@ -953,7 +958,7 @@ _xt_coproc_exc:
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-------------------------------------------------------------------------------
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*/
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.text
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.text
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.type _xt_lowint1,@function
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.align 4
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@ -973,12 +978,12 @@ _xt_lowint1:
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/* Save rest of interrupt context and enter RTOS. */
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call0 XT_RTOS_INT_ENTER /* common RTOS interrupt entry */
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/* !! We are now on the RTOS system stack !! */
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/* !! We are now on the RTOS system stack !! */
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/* Set up PS for C, enable interrupts above this level and clear EXCM. */
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#ifdef __XTENSA_CALL0_ABI__
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movi a0, PS_INTLEVEL(1) | PS_UM
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#else
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#else
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movi a0, PS_INTLEVEL(1) | PS_UM | PS_WOE
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#endif
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wsr a0, PS
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@ -1010,7 +1015,7 @@ _xt_lowint1:
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the appropriate stack frame, saves a few vector-specific registers and
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calls XT_RTOS_INT_ENTER to save the rest of the interrupted context
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and enter the RTOS, then sets up a C environment. It then calls the
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user's interrupt handler code (which may be coded in C) and finally
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user's interrupt handler code (which may be coded in C) and finally
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calls XT_RTOS_INT_EXIT to transfer control to the RTOS for scheduling.
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While XT_RTOS_INT_EXIT does not return directly to the interruptee,
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@ -1392,7 +1397,7 @@ and used for purposes requiring very short service times.
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Here are templates for high priority (level 2+) interrupt vectors.
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They assume only one interrupt per level to avoid the burden of identifying
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which interrupts at this level are pending and enabled. This allows for
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which interrupts at this level are pending and enabled. This allows for
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minimum latency and avoids having to save/restore a2 in addition to a0.
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If more than one interrupt per high priority level is configured, this burden
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is on the handler which in any case must provide a way to save and restore
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@ -1655,12 +1660,12 @@ _xt_nmi:
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WINDOW OVERFLOW AND UNDERFLOW EXCEPTION VECTORS AND ALLOCA EXCEPTION HANDLER
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Here is the code for each window overflow/underflow exception vector and
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Here is the code for each window overflow/underflow exception vector and
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(interspersed) efficient code for handling the alloca exception cause.
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Window exceptions are handled entirely in the vector area and are very
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tight for performance. The alloca exception is also handled entirely in
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tight for performance. The alloca exception is also handled entirely in
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the window vector area so comes at essentially no cost in code size.
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Users should never need to modify them and Cadence Design Systems recommends
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Users should never need to modify them and Cadence Design Systems recommends
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they do not.
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Window handlers go at predetermined vector locations according to the
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