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Cleanup license text in Xtensa XCC and Xtensa ESP32 GCC ports.
Add SPXD license identifiers.
This commit is contained in:
Paul Bartell
Paul Bartell
parent
1041b63586
commit
b5e9896ad7
37 changed files with 964 additions and 783 deletions
75
portable/ThirdParty/XCC/Xtensa/xtensa_context.S
vendored
75
portable/ThirdParty/XCC/Xtensa/xtensa_context.S
vendored
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@ -1,25 +1,30 @@
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/*
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* Copyright (c) 2015-2019 Cadence Design Systems, Inc.
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/*
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* FreeRTOS Kernel <DEVELOPMENT BRANCH>
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* Copyright (C) 2015-2019 Cadence Design Systems, Inc.
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* Copyright (C) 2021 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sublicense, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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* SPDX-License-Identifier: MIT
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*
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* The above copyright notice and this permission notice shall be included
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* in all copies or substantial portions of the Software.
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* Permission is hereby granted, free of charge, to any person obtaining a copy of
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* this software and associated documentation files (the "Software"), to deal in
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* the Software without restriction, including without limitation the rights to
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* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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* the Software, and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* https://www.FreeRTOS.org
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* https://github.com/FreeRTOS
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
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* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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/*
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@ -69,7 +74,7 @@ interrupt stack frame defined in xtensa_rtos.h.
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Its counterpart is _xt_context_restore (which also restores A12, A13).
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Caller is expected to have saved PC, PS, A0, A1 (SP), A12, A13 in the frame.
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This function preserves A12 & A13 in order to provide the caller with 2 scratch
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This function preserves A12 & A13 in order to provide the caller with 2 scratch
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regs that need not be saved over the call to this function. The choice of which
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2 regs to provide is governed by xthal_window_spill_nw and xthal_save_extra_nw,
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to avoid moving data more than necessary. Caller can assign regs accordingly.
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@ -78,7 +83,7 @@ Entry Conditions:
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A0 = Return address in caller.
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A1 = Stack pointer of interrupted thread or handler ("interruptee").
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Original A12, A13 have already been saved in the interrupt stack frame.
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Other processor state except PC, PS, A0, A1 (SP), A12, A13, is as at the
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Other processor state except PC, PS, A0, A1 (SP), A12, A13, is as at the
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point of interruption.
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If windowed ABI, PS.EXCM = 1 (exceptions disabled).
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@ -147,8 +152,8 @@ _xt_context_save:
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and underflow exceptions disabled (assured by PS.EXCM == 1).
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*/
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s32i a12, sp, XT_STK_TMP0 /* temp. save stuff in stack frame */
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s32i a13, sp, XT_STK_TMP1
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s32i a9, sp, XT_STK_TMP2
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s32i a13, sp, XT_STK_TMP1
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s32i a9, sp, XT_STK_TMP2
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/*
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Save the overlay state if we are supporting overlays. Since we just saved
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@ -168,12 +173,12 @@ _xt_context_save:
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call0 xthal_window_spill_nw /* preserves only a4,5,8,9,12,13 */
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addi sp, sp, -XT_STK_FRMSZ
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l32i a12, sp, XT_STK_TMP0 /* recover stuff from stack frame */
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l32i a13, sp, XT_STK_TMP1
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l32i a9, sp, XT_STK_TMP2
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l32i a13, sp, XT_STK_TMP1
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l32i a9, sp, XT_STK_TMP2
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#endif
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#if XCHAL_EXTRA_SA_SIZE > 0
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/*
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/*
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NOTE: Normally the xthal_save_extra_nw macro only affects address
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registers a2-a5. It is theoretically possible for Xtensa processor
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designers to write TIE that causes more address registers to be
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@ -203,7 +208,7 @@ _xt_context_restore
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!! MUST BE CALLED ONLY BY 'CALL0' INSTRUCTION !!
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Restores all Xtensa processor state except PC, PS, A0, A1 (SP) (and in Call0
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ABI, A14, A15 which are preserved by all interrupt handlers) from an interrupt
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ABI, A14, A15 which are preserved by all interrupt handlers) from an interrupt
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stack frame defined in xtensa_rtos.h .
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Its counterpart is _xt_context_save (whose caller saved A12, A13).
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@ -216,7 +221,7 @@ Entry Conditions:
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Exit conditions:
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A0 = Return address in caller.
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A1 = Stack pointer of interrupted thread or handler ("interruptee").
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Other processor state except PC, PS, A0, A1 (SP), is as at the point
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Other processor state except PC, PS, A0, A1 (SP), is as at the point
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of interruption.
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*******************************************************************************/
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@ -227,7 +232,7 @@ Exit conditions:
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_xt_context_restore:
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#if XCHAL_EXTRA_SA_SIZE > 0
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/*
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/*
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NOTE: Normally the xthal_restore_extra_nw macro only affects address
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registers a2-a5. It is theoretically possible for Xtensa processor
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designers to write TIE that causes more address registers to be
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@ -297,7 +302,7 @@ _xt_context_restore:
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/*
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Call0 ABI callee-saved regs a12-15 do not need to be restored here.
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However a12-13 were saved for scratch before XT_RTOS_INT_ENTER(),
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However a12-13 were saved for scratch before XT_RTOS_INT_ENTER(),
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so need to be restored anyway, despite being callee-saved in Call0.
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*/
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l32i a12, sp, XT_STK_A12
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@ -320,7 +325,7 @@ to "unowned". Leaves CPENABLE as it found it (does NOT clear it).
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Called during initialization of the RTOS, before any threads run.
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This may be called from normal Xtensa single-threaded application code which
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might use co-processors. The Xtensa run-time initialization enables all
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might use co-processors. The Xtensa run-time initialization enables all
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co-processors. They must remain enabled here, else a co-processor exception
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might occur outside of a thread, which the exception handler doesn't expect.
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@ -361,13 +366,13 @@ _xt_coproc_init:
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_xt_coproc_release
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Releases any and all co-processors owned by a given thread. The thread is
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Releases any and all co-processors owned by a given thread. The thread is
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identified by it's co-processor state save area defined in xtensa_context.h .
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Must be called before a thread's co-proc save area is deleted to avoid
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memory corruption when the exception handler tries to save the state.
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May be called when a thread terminates or completes but does not delete
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the co-proc save area, to avoid the exception handler having to save the
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the co-proc save area, to avoid the exception handler having to save the
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thread's co-proc state before another thread can use it (optimization).
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Entry Conditions:
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@ -553,13 +558,13 @@ _xt_coproc_restorecs:
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s32i a3, a15, XT_CP_CS_ST /* update saved CP mask */
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movi a13, _xt_coproc_sa_offset /* array of CP save offsets */
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l32i a15, a15, XT_CP_ASA /* a15 = base of aligned save area */
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#if XCHAL_CP0_SA_SIZE
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bbci.l a2, 0, 2f /* CP 0 not enabled */
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l32i a14, a13, 0 /* a14 = _xt_coproc_sa_offset[0] */
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add a3, a14, a15 /* a3 = save area for CP 0 */
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xchal_cp0_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
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2:
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2:
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#endif
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#if XCHAL_CP1_SA_SIZE
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