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Final mods prior to release.

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This commit is contained in:
Richard Barry 2009-06-01 11:41:16 +00:00
parent c36f76a062
commit b5ab3cd823
3 changed files with 23 additions and 23 deletions
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2
Demo/CORTEX_LPC1766_GCC_RedSuite/FreeRTOSConfig.h
View file

@ -69,7 +69,7 @@
#define configUSE_IDLE_HOOK 0 #define configUSE_IDLE_HOOK 0
#define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 ) #define configMAX_PRIORITIES ( ( unsigned portBASE_TYPE ) 5 )
#define configUSE_TICK_HOOK 1 #define configUSE_TICK_HOOK 1
#define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 72000000 ) #define configCPU_CLOCK_HZ ( ( unsigned portLONG ) 64000000 )
#define configTICK_RATE_HZ ( ( portTickType ) 1000 ) #define configTICK_RATE_HZ ( ( portTickType ) 1000 )
#define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 80 ) #define configMINIMAL_STACK_SIZE ( ( unsigned portSHORT ) 80 )
#define configTOTAL_HEAP_SIZE ( ( size_t ) ( 19 * 1024 ) ) #define configTOTAL_HEAP_SIZE ( ( size_t ) ( 19 * 1024 ) )

4
Demo/CORTEX_LPC1766_GCC_RedSuite/main.c
View file

@ -377,7 +377,7 @@ void prvSetupHardware( void )
PLL0FEED = PLLFEED_FEED1; PLL0FEED = PLLFEED_FEED1;
PLL0FEED = PLLFEED_FEED2; PLL0FEED = PLLFEED_FEED2;
/* 6x CPU clock divider (72 MHz) */ /* 6x CPU clock divider (64 MHz) */
CCLKCFG = 5; CCLKCFG = 5;
/* Wait for the PLL to lock. */ /* Wait for the PLL to lock. */
@ -388,7 +388,7 @@ void prvSetupHardware( void )
PLL0FEED = PLLFEED_FEED1; PLL0FEED = PLLFEED_FEED1;
PLL0FEED = PLLFEED_FEED2; PLL0FEED = PLLFEED_FEED2;
/* Setup the peripheral bus to be the same as the PLL output (72 MHz). */ /* Setup the peripheral bus to be the same as the PLL output (64 MHz). */
PCLKSEL0 = 0x05555555; PCLKSEL0 = 0x05555555;
/* Configure LED GPIOs as outputs. */ /* Configure LED GPIOs as outputs. */

40
Demo/CORTEX_LPC1766_GCC_RedSuite/webserver/httpd-fsdata.c
View file

@ -298,29 +298,29 @@ static const char data_runtime_shtml[] = {
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static const char data_stats_shtml[] = { static const char data_stats_shtml[] = {
/* /stats.shtml */ /* /stats.shtml */