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https://github.com/FreeRTOS/FreeRTOS-Kernel.git
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Fix spelling
This commit is contained in:
ActoryOu
parent
c0585ad814
commit
b384312829
132 changed files with 215 additions and 215 deletions
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@ -627,8 +627,8 @@ typedef struct _AT91S_MC
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/* -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- */
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#define AT91C_MC_RCB ( ( unsigned int ) 0x1 << 0 ) /* (MC) Remap Command Bit */
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/* -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- */
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#define AT91C_MC_UNDADD ( ( unsigned int ) 0x1 << 0 ) /* (MC) Undefined Addess Abort Status */
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#define AT91C_MC_MISADD ( ( unsigned int ) 0x1 << 1 ) /* (MC) Misaligned Addess Abort Status */
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#define AT91C_MC_UNDADD ( ( unsigned int ) 0x1 << 0 ) /* (MC) Undefined Address Abort Status */
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#define AT91C_MC_MISADD ( ( unsigned int ) 0x1 << 1 ) /* (MC) Misaligned Address Abort Status */
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#define AT91C_MC_ABTSZ ( ( unsigned int ) 0x3 << 8 ) /* (MC) Abort Size Status */
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#define AT91C_MC_ABTSZ_BYTE ( ( unsigned int ) 0x0 << 8 ) /* (MC) Byte */
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#define AT91C_MC_ABTSZ_HWORD ( ( unsigned int ) 0x1 << 8 ) /* (MC) Half-word */
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@ -1509,7 +1509,7 @@ typedef struct _AT91S_EMAC
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AT91_REG EMAC_ECOL; /* Excessive Collision Register */
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AT91_REG EMAC_TUND; /* Transmit Underrun Error Register */
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AT91_REG EMAC_CSE; /* Carrier Sense Error Register */
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AT91_REG EMAC_RRE; /* Receive Ressource Error Register */
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AT91_REG EMAC_RRE; /* Receive Resource Error Register */
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AT91_REG EMAC_ROV; /* Receive Overrun Errors Register */
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AT91_REG EMAC_RSE; /* Receive Symbol Errors Register */
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AT91_REG EMAC_ELE; /* Excessive Length Errors Register */
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@ -2393,7 +2393,7 @@ typedef struct _AT91S_TDES
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#define AT91C_EMAC_SA1H ( ( AT91_REG * ) 0xFFFDC09C ) /* (EMAC) Specific Address 1 Top, Last 2 bytes */
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#define AT91C_EMAC_CSE ( ( AT91_REG * ) 0xFFFDC068 ) /* (EMAC) Carrier Sense Error Register */
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#define AT91C_EMAC_SA3H ( ( AT91_REG * ) 0xFFFDC0AC ) /* (EMAC) Specific Address 3 Top, Last 2 bytes */
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#define AT91C_EMAC_RRE ( ( AT91_REG * ) 0xFFFDC06C ) /* (EMAC) Receive Ressource Error Register */
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#define AT91C_EMAC_RRE ( ( AT91_REG * ) 0xFFFDC06C ) /* (EMAC) Receive Resource Error Register */
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#define AT91C_EMAC_STE ( ( AT91_REG * ) 0xFFFDC084 ) /* (EMAC) SQE Test Error Register */
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/* ========== Register definition for PDC_ADC peripheral ========== */
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#define AT91C_ADC_PTSR ( ( AT91_REG * ) 0xFFFD8124 ) /* (PDC_ADC) PDC Transfer Status Register */
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@ -627,8 +627,8 @@ typedef struct _AT91S_MC
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/* -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- */
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#define AT91C_MC_RCB ( ( unsigned int ) 0x1 << 0 ) /* (MC) Remap Command Bit */
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/* -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- */
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#define AT91C_MC_UNDADD ( ( unsigned int ) 0x1 << 0 ) /* (MC) Undefined Addess Abort Status */
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#define AT91C_MC_MISADD ( ( unsigned int ) 0x1 << 1 ) /* (MC) Misaligned Addess Abort Status */
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#define AT91C_MC_UNDADD ( ( unsigned int ) 0x1 << 0 ) /* (MC) Undefined Address Abort Status */
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#define AT91C_MC_MISADD ( ( unsigned int ) 0x1 << 1 ) /* (MC) Misaligned Address Abort Status */
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#define AT91C_MC_ABTSZ ( ( unsigned int ) 0x3 << 8 ) /* (MC) Abort Size Status */
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#define AT91C_MC_ABTSZ_BYTE ( ( unsigned int ) 0x0 << 8 ) /* (MC) Byte */
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#define AT91C_MC_ABTSZ_HWORD ( ( unsigned int ) 0x1 << 8 ) /* (MC) Half-word */
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@ -1509,7 +1509,7 @@ typedef struct _AT91S_EMAC
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AT91_REG EMAC_ECOL; /* Excessive Collision Register */
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AT91_REG EMAC_TUND; /* Transmit Underrun Error Register */
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AT91_REG EMAC_CSE; /* Carrier Sense Error Register */
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AT91_REG EMAC_RRE; /* Receive Ressource Error Register */
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AT91_REG EMAC_RRE; /* Receive Resource Error Register */
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AT91_REG EMAC_ROV; /* Receive Overrun Errors Register */
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AT91_REG EMAC_RSE; /* Receive Symbol Errors Register */
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AT91_REG EMAC_ELE; /* Excessive Length Errors Register */
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@ -2393,7 +2393,7 @@ typedef struct _AT91S_TDES
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#define AT91C_EMAC_SA1H ( ( AT91_REG * ) 0xFFFDC09C ) /* (EMAC) Specific Address 1 Top, Last 2 bytes */
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#define AT91C_EMAC_CSE ( ( AT91_REG * ) 0xFFFDC068 ) /* (EMAC) Carrier Sense Error Register */
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#define AT91C_EMAC_SA3H ( ( AT91_REG * ) 0xFFFDC0AC ) /* (EMAC) Specific Address 3 Top, Last 2 bytes */
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#define AT91C_EMAC_RRE ( ( AT91_REG * ) 0xFFFDC06C ) /* (EMAC) Receive Ressource Error Register */
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#define AT91C_EMAC_RRE ( ( AT91_REG * ) 0xFFFDC06C ) /* (EMAC) Receive Resource Error Register */
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#define AT91C_EMAC_STE ( ( AT91_REG * ) 0xFFFDC084 ) /* (EMAC) SQE Test Error Register */
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/* ========== Register definition for PDC_ADC peripheral ========== */
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#define AT91C_ADC_PTSR ( ( AT91_REG * ) 0xFFFD8124 ) /* (PDC_ADC) PDC Transfer Status Register */
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@ -3125,9 +3125,9 @@ AT91C_MC_RCB EQU( 0x1 << 0 );
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-( MC ) Remap Command Bit
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/* - -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- */
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AT91C_MC_UNDADD EQU( 0x1 << 0 );
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-( MC ) Undefined Addess Abort Status
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-( MC ) Undefined Address Abort Status
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AT91C_MC_MISADD EQU( 0x1 << 1 );
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-( MC ) Misaligned Addess Abort Status
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-( MC ) Misaligned Address Abort Status
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AT91C_MC_ABTSZ EQU( 0x3 << 8 );
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-( MC ) Abort Size Status
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AT91C_MC_ABTSZ_BYTE EQU( 0x0 << 8 );
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@ -5698,7 +5698,7 @@ AT91C_US_CLKS EQU( 0x3 << 4 );
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AT91C_EMAC_SA3H EQU( 0xFFFDC0AC );
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-( EMAC ) Specific Address 3 Top, Last 2 bytes
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AT91C_EMAC_RRE EQU( 0xFFFDC06C );
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-( EMAC ) Receive Ressource Error Register
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-( EMAC ) Receive Resource Error Register
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AT91C_EMAC_STE EQU( 0xFFFDC084 );
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-( EMAC ) SQE Test Error Register
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/* - ========== Register definition for PDC_ADC peripheral ========== */
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@ -210,7 +210,7 @@
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/** \brief Set the next receive transfer descriptor */
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/**---------------------------------------------------------------------------- */
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__inline void AT91F_PDC_SetNextRx( AT91PS_PDC pPDC, /* \arg pointer to a PDC controller */
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char * address, /* \arg address to the next bloc to be received */
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char * address, /* \arg address to the next block to be received */
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unsigned int bytes ) /* \arg number of bytes to be received */
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{
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pPDC->PDC_RNPR = ( unsigned int ) address;
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@ -222,7 +222,7 @@
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/** \brief Set the next transmit transfer descriptor */
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/**---------------------------------------------------------------------------- */
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__inline void AT91F_PDC_SetNextTx( AT91PS_PDC pPDC, /* \arg pointer to a PDC controller */
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char * address, /* \arg address to the next bloc to be transmitted */
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char * address, /* \arg address to the next block to be transmitted */
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unsigned int bytes ) /* \arg number of bytes to be transmitted */
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{
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pPDC->PDC_TNPR = ( unsigned int ) address;
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@ -234,7 +234,7 @@
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/** \brief Set the receive transfer descriptor */
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/**---------------------------------------------------------------------------- */
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__inline void AT91F_PDC_SetRx( AT91PS_PDC pPDC, /* \arg pointer to a PDC controller */
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char * address, /* \arg address to the next bloc to be received */
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char * address, /* \arg address to the next block to be received */
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unsigned int bytes ) /* \arg number of bytes to be received */
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{
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pPDC->PDC_RPR = ( unsigned int ) address;
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@ -246,7 +246,7 @@
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/** \brief Set the transmit transfer descriptor */
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/**---------------------------------------------------------------------------- */
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__inline void AT91F_PDC_SetTx( AT91PS_PDC pPDC, /* \arg pointer to a PDC controller */
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char * address, /* \arg address to the next bloc to be transmitted */
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char * address, /* \arg address to the next block to be transmitted */
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unsigned int bytes ) /* \arg number of bytes to be transmitted */
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{
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pPDC->PDC_TPR = ( unsigned int ) address;
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@ -1054,7 +1054,7 @@
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/**---------------------------------------------------------------------------- */
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/** \fn AT91F_CKGR_CfgMainOscStartUpTime */
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/** \brief Cfg MOR Register according to the main osc startup time */
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/** \brief Cfg MORE Register according to the main osc startup time */
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/**---------------------------------------------------------------------------- */
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__inline void AT91F_CKGR_CfgMainOscStartUpTime( AT91PS_CKGR pCKGR, /* \arg pointer to CKGR controller */
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unsigned int startup_time, /* \arg main osc startup time in microsecond (us) */
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