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https://github.com/FreeRTOS/FreeRTOS-Kernel.git
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Fix bug in core_cm3.c atomic macros.
Rename the portable/GCC/RISC-V-RV32 directory to just RISC-V as also adding support for 64-bit cores.
This commit is contained in:
Richard Barry
parent
3153131fa7
commit
b2b1b09ea5
33 changed files with 8363 additions and 6092 deletions
396
FreeRTOS/Source/portable/GCC/RISC-V/portASM.S
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396
FreeRTOS/Source/portable/GCC/RISC-V/portASM.S
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/*
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* FreeRTOS Kernel V10.1.1
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* Copyright (C) 2018 Amazon.com, Inc. or its affiliates. All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy of
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* this software and associated documentation files (the "Software"), to deal in
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* the Software without restriction, including without limitation the rights to
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* use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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* the Software, and to permit persons to whom the Software is furnished to do so,
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* subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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* FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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* COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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* IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* http://www.FreeRTOS.org
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* http://aws.amazon.com/freertos
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*
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* 1 tab == 4 spaces!
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*/
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#if __riscv_xlen == 64
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#error Not implemented yet - change lw to ld, and sw to sd.
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#define portWORD_SIZE 8
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#elif __riscv_xlen == 32
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#define portWORD_SIZE 4
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#else
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#error Assembler did not define __riscv_xlen
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#endif
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/*
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* The FreeRTOS kernel's RISC-V port is split between the the code that is
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* common across all currently supported RISC-V chips (implementations of the
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* RISC-V ISA), and code which tailors the port to a specific RISC-V chip:
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*
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* + The code that is common to all RISC-V chips is implemented in
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* FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S. There is only one
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* portASM.S file because the same file is used no matter which RISC-V chip is
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* in use.
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*
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* + The code that tailors the kernel's RISC-V port to a specific RISC-V
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* chip is implemented in freertos_risc_v_chip_specific_extensions.h. There
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* is one freertos_risc_v_chip_specific_extensions.h that can be used with any
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* RISC-V chip that both includes a standard CLINT and does not add to the
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* base set of RISC-V registers. There are additional
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* freertos_risc_v_chip_specific_extensions.h files for RISC-V implementations
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* that do not include a standard CLINT or do add to the base set of RISC-V
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* registers.
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*
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* CARE MUST BE TAKEN TO INCLDUE THE CORRECT
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* freertos_risc_v_chip_specific_extensions.h HEADER FILE FOR THE CHIP
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* IN USE. To include the correct freertos_risc_v_chip_specific_extensions.h
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* header file ensure the path to the correct header file is in the assembler's
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* include path.
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*
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* This freertos_risc_v_chip_specific_extensions.h is for use on RISC-V chips
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* that include a standard CLINT and do not add to the base set of RISC-V
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* registers.
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*
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*/
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#include "freertos_risc_v_chip_specific_extensions.h"
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/* Check the freertos_risc_v_chip_specific_extensions.h and/or command line
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definitions. */
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#ifndef portasmHAS_CLINT
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#error freertos_risc_v_chip_specific_extensions.h must define portasmHAS_CLINT to either 1 (CLINT present) or 0 (clint not present).
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#endif
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#ifndef portasmHANDLE_INTERRUPT
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#error portasmHANDLE_INTERRUPT must be defined to the function to be called to handle external/peripheral interrupts. portasmHANDLE_INTERRUPT can be defined on the assmbler command line or in the appropriate freertos_risc_v_chip_specific_extensions.h header file.
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#endif
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/* Only the standard core registers are stored by default. Any additional
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registers must be saved by the portasmSAVE_ADDITIONAL_REGISTERS and
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portasmRESTORE_ADDITIONAL_REGISTERS macros - which can be defined in a chip
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specific version of freertos_risc_v_chip_specific_extensions.h. See the notes
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at the top of this file. */
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#define portCONTEXT_SIZE ( 30 * portWORD_SIZE )
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.global xPortStartFirstTask
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.global freertos_risc_v_trap_handler
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.global pxPortInitialiseStack
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.extern pxCurrentTCB
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.extern ulPortTrapHandler
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.extern vTaskSwitchContext
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.extern Timer_IRQHandler
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.extern pullMachineTimerCompareRegister
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.extern pullNextTime
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.extern ulTimerIncrementsForOneTick
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.extern xISRStackTop
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/*-----------------------------------------------------------*/
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.align 8
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.func
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freertos_risc_v_trap_handler:
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addi sp, sp, -portCONTEXT_SIZE
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sw x1, 1 * portWORD_SIZE( sp )
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sw x5, 2 * portWORD_SIZE( sp )
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sw x6, 3 * portWORD_SIZE( sp )
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sw x7, 4 * portWORD_SIZE( sp )
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sw x8, 5 * portWORD_SIZE( sp )
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sw x9, 6 * portWORD_SIZE( sp )
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sw x10, 7 * portWORD_SIZE( sp )
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sw x11, 8 * portWORD_SIZE( sp )
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sw x12, 9 * portWORD_SIZE( sp )
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sw x13, 10 * portWORD_SIZE( sp )
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sw x14, 11 * portWORD_SIZE( sp )
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sw x15, 12 * portWORD_SIZE( sp )
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sw x16, 13 * portWORD_SIZE( sp )
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sw x17, 14 * portWORD_SIZE( sp )
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sw x18, 15 * portWORD_SIZE( sp )
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sw x19, 16 * portWORD_SIZE( sp )
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sw x20, 17 * portWORD_SIZE( sp )
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sw x21, 18 * portWORD_SIZE( sp )
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sw x22, 19 * portWORD_SIZE( sp )
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sw x23, 20 * portWORD_SIZE( sp )
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sw x24, 21 * portWORD_SIZE( sp )
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sw x25, 22 * portWORD_SIZE( sp )
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sw x26, 23 * portWORD_SIZE( sp )
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sw x27, 24 * portWORD_SIZE( sp )
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sw x28, 25 * portWORD_SIZE( sp )
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sw x29, 26 * portWORD_SIZE( sp )
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sw x30, 27 * portWORD_SIZE( sp )
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sw x31, 28 * portWORD_SIZE( sp )
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csrr t0, mstatus /* Required for MPIE bit. */
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sw t0, 29 * portWORD_SIZE( sp )
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portasmSAVE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_chip_specific_extensions.h to save any registers unique to the RISC-V implementation. */
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lw t0, pxCurrentTCB /* Load pxCurrentTCB. */
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sw sp, 0( t0 ) /* Write sp to first TCB member. */
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csrr a0, mcause
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csrr a1, mepc
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test_if_asynchronous:
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srli a2, a0, 0x1f /* MSB of mcause is 1 if handing an asynchronous interrupt - shift to LSB to clear other bits. */
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beq a2, x0, handle_synchronous /* Branch past interrupt handing if not asynchronous. */
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sw a1, 0( sp ) /* Asynch so save unmodified exception return address. */
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handle_asynchronous:
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#if( portasmHAS_CLINT != 0 )
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test_if_mtimer: /* If there is a CLINT then the mtimer is used to generate the tick interrupt. */
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lui t0, 0x80000
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addi t1, t0, 7 /* 0x80000007 == machine timer interrupt. */
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bne a0, t1, test_if_external_interrupt
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lw t0, pullMachineTimerCompareRegister /* Load address of compare register into t0. */
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lw t1, pullNextTime /* Load the address of ullNextTime into t1. */
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lw t2, 0(t1) /* Load the low word of ullNextTime into t2. */
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lw t3, 4(t1) /* Load the high word of ullNextTime into t3. */
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sw t2, 0(t0) /* Store low word of ullNextTime into compare register. */
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sw t3, 4(t0) /* Store high word of ullNextTime into compare register. */
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lw t0, ulTimerIncrementsForOneTick /* Load the value of ullTimerIncrementForOneTick into t0 (could this be optimized by storing in an array next to pullNextTime?). */
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add t4, t0, t2 /* Add the low word of ullNextTime to the timer increments for one tick (assumes timer increment for one tick fits in 32-bits. */
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sltu t5, t4, t2 /* See if the sum of low words overflowed (what about the zero case?). */
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add t6, t3, t5 /* Add overflow to high word of ullNextTime. */
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sw t4, 0(t1) /* Store new low word of ullNextTime. */
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sw t6, 4(t1) /* Store new high word of ullNextTime. */
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lw sp, xISRStackTop /* Switch to ISR stack before function call. */
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jal xTaskIncrementTick
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beqz a0, processed_source /* Don't switch context if incrementing tick didn't unblock a task. */
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jal vTaskSwitchContext
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j processed_source
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test_if_external_interrupt: /* If there is a CLINT and the mtimer interrupt is not pending then check to see if an external interrupt is pending. */
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addi t1, t1, 4 /* 0x80000007 + 4 = 0x8000000b == Machine external interrupt. */
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bne a0, t1, as_yet_unhandled /* Something as yet unhandled. */
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#endif /* portasmHAS_CLINT */
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lw sp, xISRStackTop /* Switch to ISR stack before function call. */
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jal portasmHANDLE_INTERRUPT /* Jump to the interrupt handler if there is no CLINT or if there is a CLINT and it has been determined that an external interrupt is pending. */
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j processed_source
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handle_synchronous:
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addi a1, a1, 4 /* Synchronous so updated exception return address to the instruction after the instruction that generated the exeption. */
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sw a1, 0( sp ) /* Save updated exception return address. */
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test_if_environment_call:
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li t0, 11 /* 11 == environment call. */
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bne a0, t0, is_exception /* Not an M environment call, so some other exception. */
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lw sp, xISRStackTop /* Switch to ISR stack before function call. */
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jal vTaskSwitchContext
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j processed_source
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is_exception:
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ebreak
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j is_exception
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as_yet_unhandled:
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ebreak
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j as_yet_unhandled
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processed_source:
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lw sp, pxCurrentTCB /* Load pxCurrentTCB. */
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lw sp, 0( sp ) /* Read sp from first TCB member. */
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/* Load mret with the address of the next instruction in the task to run next. */
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lw t0, 0( sp )
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csrw mepc, t0
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portasmRESTORE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_chip_specific_extensions.h to restore any registers unique to the RISC-V implementation. */
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/* Load mstatus with the interrupt enable bits used by the task. */
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lw t0, 29 * portWORD_SIZE( sp )
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csrw mstatus, t0 /* Required for MPIE bit. */
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lw x1, 1 * portWORD_SIZE( sp )
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lw x5, 2 * portWORD_SIZE( sp ) /* t0 */
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lw x6, 3 * portWORD_SIZE( sp ) /* t1 */
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lw x7, 4 * portWORD_SIZE( sp ) /* t2 */
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lw x8, 5 * portWORD_SIZE( sp ) /* s0/fp */
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lw x9, 6 * portWORD_SIZE( sp ) /* s1 */
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lw x10, 7 * portWORD_SIZE( sp ) /* a0 */
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lw x11, 8 * portWORD_SIZE( sp ) /* a1 */
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lw x12, 9 * portWORD_SIZE( sp ) /* a2 */
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lw x13, 10 * portWORD_SIZE( sp ) /* a3 */
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lw x14, 11 * portWORD_SIZE( sp ) /* a4 */
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lw x15, 12 * portWORD_SIZE( sp ) /* a5 */
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lw x16, 13 * portWORD_SIZE( sp ) /* a6 */
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lw x17, 14 * portWORD_SIZE( sp ) /* a7 */
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lw x18, 15 * portWORD_SIZE( sp ) /* s2 */
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lw x19, 16 * portWORD_SIZE( sp ) /* s3 */
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lw x20, 17 * portWORD_SIZE( sp ) /* s4 */
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lw x21, 18 * portWORD_SIZE( sp ) /* s5 */
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lw x22, 19 * portWORD_SIZE( sp ) /* s6 */
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lw x23, 20 * portWORD_SIZE( sp ) /* s7 */
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lw x24, 21 * portWORD_SIZE( sp ) /* s8 */
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lw x25, 22 * portWORD_SIZE( sp ) /* s9 */
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lw x26, 23 * portWORD_SIZE( sp ) /* s10 */
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lw x27, 24 * portWORD_SIZE( sp ) /* s11 */
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lw x28, 25 * portWORD_SIZE( sp ) /* t3 */
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lw x29, 26 * portWORD_SIZE( sp ) /* t4 */
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lw x30, 27 * portWORD_SIZE( sp ) /* t5 */
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lw x31, 28 * portWORD_SIZE( sp ) /* t6 */
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addi sp, sp, portCONTEXT_SIZE
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mret
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.endfunc
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/*-----------------------------------------------------------*/
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.align 8
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.func
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xPortStartFirstTask:
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#if( portasmHAS_CLINT != 0 )
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/* If there is a clint then interrupts can branch directly to the FreeRTOS
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trap handler. Otherwise the interrupt controller will need to be configured
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outside of this file. */
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la t0, freertos_risc_v_trap_handler
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csrw mtvec, t0
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#endif /* portasmHAS_CLILNT */
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lw sp, pxCurrentTCB /* Load pxCurrentTCB. */
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lw sp, 0( sp ) /* Read sp from first TCB member. */
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lw x1, 0( sp ) /* Note for starting the scheduler the exception return address is used as the function return address. */
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portasmRESTORE_ADDITIONAL_REGISTERS /* Defined in freertos_risc_v_chip_specific_extensions.h to restore any registers unique to the RISC-V implementation. */
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lw t0, 29 * portWORD_SIZE( sp ) /* mstatus */
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csrrw x0, mstatus, t0 /* Interrupts enabled from here! */
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lw x5, 2 * portWORD_SIZE( sp ) /* t0 */
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lw x6, 3 * portWORD_SIZE( sp ) /* t1 */
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lw x7, 4 * portWORD_SIZE( sp ) /* t2 */
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lw x8, 5 * portWORD_SIZE( sp ) /* s0/fp */
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lw x9, 6 * portWORD_SIZE( sp ) /* s1 */
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lw x10, 7 * portWORD_SIZE( sp ) /* a0 */
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lw x11, 8 * portWORD_SIZE( sp ) /* a1 */
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lw x12, 9 * portWORD_SIZE( sp ) /* a2 */
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lw x13, 10 * portWORD_SIZE( sp ) /* a3 */
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lw x14, 11 * portWORD_SIZE( sp ) /* a4 */
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lw x15, 12 * portWORD_SIZE( sp ) /* a5 */
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lw x16, 13 * portWORD_SIZE( sp ) /* a6 */
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lw x17, 14 * portWORD_SIZE( sp ) /* a7 */
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lw x18, 15 * portWORD_SIZE( sp ) /* s2 */
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lw x19, 16 * portWORD_SIZE( sp ) /* s3 */
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lw x20, 17 * portWORD_SIZE( sp ) /* s4 */
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lw x21, 18 * portWORD_SIZE( sp ) /* s5 */
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lw x22, 19 * portWORD_SIZE( sp ) /* s6 */
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lw x23, 20 * portWORD_SIZE( sp ) /* s7 */
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lw x24, 21 * portWORD_SIZE( sp ) /* s8 */
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lw x25, 22 * portWORD_SIZE( sp ) /* s9 */
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lw x26, 23 * portWORD_SIZE( sp ) /* s10 */
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lw x27, 24 * portWORD_SIZE( sp ) /* s11 */
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lw x28, 25 * portWORD_SIZE( sp ) /* t3 */
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lw x29, 26 * portWORD_SIZE( sp ) /* t4 */
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lw x30, 27 * portWORD_SIZE( sp ) /* t5 */
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lw x31, 28 * portWORD_SIZE( sp ) /* t6 */
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addi sp, sp, portCONTEXT_SIZE
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ret
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.endfunc
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/*-----------------------------------------------------------*/
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/*
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* Unlike other ports pxPortInitialiseStack() is written in assembly code as it
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* needs access to the portasmADDITIONAL_CONTEXT_SIZE constant. The prototype
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* for the function is as per the other ports:
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* StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters );
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*
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* As per the standard RISC-V ABI pxTopcOfStack is passed in in a0, pxCode in
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* a1, and pvParameters in a2. The new top of stack is passed out in a0.
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*
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* RISC-V maps registers to ABI names as follows (X1 to X31 integer registers
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* for the 'I' profile, X1 to X15 for the 'E' profile, currently I assumed).
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*
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* Register ABI Name Description Saver
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* x0 zero Hard-wired zero -
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* x1 ra Return address Caller
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* x2 sp Stack pointer Callee
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* x3 gp Global pointer -
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* x4 tp Thread pointer -
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* x5-7 t0-2 Temporaries Caller
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* x8 s0/fp Saved register/Frame pointer Callee
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* x9 s1 Saved register Callee
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* x10-11 a0-1 Function Arguments/return values Caller
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* x12-17 a2-7 Function arguments Caller
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* x18-27 s2-11 Saved registers Callee
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* x28-31 t3-6 Temporaries Caller
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*
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* The RISC-V context is saved t FreeRTOS tasks in the following stack frame,
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* where the global and thread pointers are currently assumed to be constant so
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* are not saved:
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*
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* mstatus
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* x31
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* x30
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* x29
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* x28
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* x27
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* x26
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* x25
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* x24
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* x23
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* x22
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* x21
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* x20
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* x19
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* x18
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* x17
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* x16
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* x15
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* x14
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* x13
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* x12
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* x11
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* pvParameters
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* x9
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* x8
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* x7
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* x6
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* x5
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* portTASK_RETURN_ADDRESS
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* [chip specific registers go here]
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* pxCode
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*/
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.align 8
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.func
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pxPortInitialiseStack:
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csrr t0, mstatus /* Obtain current mstatus value. */
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addi t1, x0, 0x188 /* Generate the value 0x1880, which are the MPIE and MPP bits to set in mstatus. */
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slli t1, t1, 4
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or t0, t0, t1 /* Set MPIE and MPP bits in mstatus value. */
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addi a0, a0, -portWORD_SIZE
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sw t0, 0(a0) /* mstatus onto the stack. */
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addi a0, a0, -(22 * portWORD_SIZE) /* Space for registers x11-x31. */
|
||||
sw a2, 0(a0) /* Task parameters (pvParameters parameter) goes into register X10/a0 on the stack. */
|
||||
addi a0, a0, -(6 * portWORD_SIZE) /* Space for registers x5-x9. */
|
||||
sw x0, 0(a0) /* Return address onto the stack, could be portTASK_RETURN_ADDRESS */
|
||||
addi t0, x0, portasmADDITIONAL_CONTEXT_SIZE /* The number of chip specific additional registers. */
|
||||
chip_specific_stack_frame: /* First add any chip specific registers to the stack frame being created. */
|
||||
beq t0, x0, 1f /* No more chip specific registers to save. */
|
||||
addi a0, a0, -portWORD_SIZE /* Make space for chip specific register. */
|
||||
sw x0, 0(a0) /* Give the chip specific register an initial value of zero. */
|
||||
addi t0, t0, -1 /* Decrement the count of chip specific registers remaining. */
|
||||
j chip_specific_stack_frame /* Until no more chip specific registers. */
|
||||
1:
|
||||
addi a0, a0, -portWORD_SIZE
|
||||
sw a1, 0(a0) /* mret value (pxCode parameter) onto the stack. */
|
||||
ret
|
||||
.endfunc
|
||||
/*-----------------------------------------------------------*/
|
||||
Loading…
Add table
Add a link
Reference in a new issue