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Fix bug in core_cm3.c atomic macros.

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Rename the portable/GCC/RISC-V-RV32 directory to just RISC-V as also adding support for 64-bit cores.
This commit is contained in:
Richard Barry 2019-02-16 01:08:38 +00:00
parent 3153131fa7
commit b2b1b09ea5
33 changed files with 8363 additions and 6092 deletions
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4
FreeRTOS/Demo/CORTEX_AT91SAM3U256_IAR/AT91Lib/cmsis/core_cm3.c
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@ -718,7 +718,7 @@ uint32_t __STREXB(uint8_t value, uint8_t *addr)
{
uint32_t result=0;
__ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
__ASM volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
return(result);
}
@ -735,7 +735,7 @@ uint32_t __STREXH(uint16_t value, uint16_t *addr)
{
uint32_t result=0;
__ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
__ASM volatile ("strexh %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
return(result);
}