len0rd/FreeRTOS-Kernel
1
0
Fork 0
mirror of https://github.com/FreeRTOS/FreeRTOS-Kernel.git synced 2025-08-19 17:48:33 -04:00
Code Issues Projects Releases Packages Wiki Activity

Fix bug in core_cm3.c atomic macros.

Browse source 
Rename the portable/GCC/RISC-V-RV32 directory to just RISC-V as also adding support for 64-bit cores.
This commit is contained in:
Richard Barry 2019-02-16 01:08:38 +00:00
parent 3153131fa7
commit b2b1b09ea5
33 changed files with 8363 additions and 6092 deletions
Download patch file Download diff file Expand all files Collapse all files

1
FreeRTOS/Demo/CORTEX_A2F200_SoftConsole/.project
View file

@ -7,6 +7,7 @@
<buildSpec>
<buildCommand>
<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
<triggers>clean,full,incremental,</triggers>
<arguments>
<dictionary>
<key>?children?</key>

4
FreeRTOS/Demo/CORTEX_A2F200_SoftConsole/MicroSemi_Code/CMSIS/core_cm3.c
View file

@ -733,7 +733,7 @@ uint32_t __STREXB(uint8_t value, uint8_t *addr)
{
uint32_t result=0;
__ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
__ASM volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
return(result);
}
@ -750,7 +750,7 @@ uint32_t __STREXH(uint16_t value, uint16_t *addr)
{
uint32_t result=0;
__ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
__ASM volatile ("strexh %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
return(result);
}