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Introduce the prvTaskExitError() function for all ARM_CMn ports.

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Introduce the configTASK_RETURN_ADDRESS macro for the GCC ARM_CMn ports.
Improve time slippage penalty when entering tickless mode is abandoned.
This commit is contained in:
Richard Barry 2013-10-08 11:30:40 +00:00
parent 81e141ad86
commit aedf7824cb
7 changed files with 217 additions and 29 deletions
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48
FreeRTOS/Source/portable/IAR/ARM_CM4F/portasm.s
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@ -81,11 +81,11 @@
/*-----------------------------------------------------------*/
xPortPendSVHandler:
mrs r0, psp
mrs r0, psp
/* Get the location of the current TCB. */
ldr r3, =pxCurrentTCB
ldr r2, [r3]
ldr r3, =pxCurrentTCB
ldr r2, [r3]
/* Is the task using the FPU context? If so, push high vfp registers. */
tst r14, #0x10
@ -93,34 +93,42 @@ xPortPendSVHandler:
vstmdbeq r0!, {s16-s31}
/* Save the core registers. */
stmdb r0!, {r4-r11, r14}
stmdb r0!, {r4-r11, r14}
/* Save the new top of stack into the first member of the TCB. */
str r0, [r2]
stmdb sp!, {r3, r14}
mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
msr basepri, r0
bl vTaskSwitchContext
bl vTaskSwitchContext
mov r0, #0
msr basepri, r0
ldmia sp!, {r3, r14}
/* The first item in pxCurrentTCB is the task top of stack. */
ldr r1, [r3]
ldr r1, [r3]
ldr r0, [r1]
/* Pop the core registers. */
ldmia r0!, {r4-r11, r14}
/* Is the task using the FPU context? If so, pop the high vfp registers
/* Is the task using the FPU context? If so, pop the high vfp registers
too. */
tst r14, #0x10
it eq
vldmiaeq r0!, {s16-s31}
msr psp, r0
bx r14
msr psp, r0
#ifdef WORKAROUND_PMU_CM001 /* XMC4000 specific errata */
#if WORKAROUND_PMU_CM001 == 1
push { r14 }
pop { pc }
#endif
#endif
bx r14
/*-----------------------------------------------------------*/
@ -130,7 +138,7 @@ ulPortSetInterruptMask:
mov r1, #configMAX_SYSCALL_INTERRUPT_PRIORITY
msr basepri, r1
bx r14
/*-----------------------------------------------------------*/
vPortClearInterruptMask:
@ -148,7 +156,7 @@ vPortSVCHandler:
ldmia r0!, {r4-r11, r14}
msr psp, r0
mov r0, #0
msr basepri, r0
msr basepri, r0
bx r14
/*-----------------------------------------------------------*/
@ -170,13 +178,13 @@ vPortEnableVFP:
/* The FPU enable bits are in the CPACR. */
ldr.w r0, =0xE000ED88
ldr r1, [r0]
/* Enable CP10 and CP11 coprocessors, then save back. */
orr r1, r1, #( 0xf << 20 )
str r1, [r0]
bx r14
bx r14
END